From 51a012b76267f2de8a0209ffdf91f67f3fb3ff42 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 29 Jun 2016 06:31:03 -0700 Subject: ARM: dts: imx: ventana: Add ext watchdog reset bc677ff42e81bbf78308a7b66cf7b63b0f5c26b0 adds a device-tree property to specify that an external watchdog reset is used to reset other portions of the board and not just the IMX6 SoC. This adds the property to the proper watchdog as well as the pinmux for the Gateworks Ventana boards that use this external watchdog reset to reset the PMIC which will reset all the PMIC power rails and not just a chip-level IMX6 reset. This helps to work around various system issues that can cause a hang when coming out of reset. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 12 ++++++++++++ arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 12 ++++++++++++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 12 ++++++++++++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 12 ++++++++++++ arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 12 ++++++++++++ 6 files changed, 77 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 9d7ab6cdc9a6..1340e2760406 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -228,6 +228,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw51xx { pinctrl_enet: enetgrp { @@ -364,5 +370,11 @@ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 7191b84770b9..8bf1020affa0 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -353,6 +353,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw52xx { pinctrl_audmux: audmuxgrp { @@ -549,5 +555,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 40d06b09deba..a3dd0c41b995 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -351,6 +351,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw53xx { pinctrl_audmux: audmuxgrp { @@ -539,5 +545,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index d6dbe2a88ee6..5a8dbabbd20f 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -453,6 +453,17 @@ status = "okay"; }; +&wdog1 { + status = "disabled"; +}; + +&wdog2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { imx6qdl-gw54xx { pinctrl_audmux: audmuxgrp { @@ -654,5 +665,11 @@ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 118bea524dab..4b9fef834822 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -239,6 +239,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw51xx { pinctrl_flexcan1: flexcan1grp { @@ -333,5 +339,11 @@ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index f27f184558fb..805e23674a94 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -197,6 +197,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { imx6qdl-gw552x { pinctrl_gpio_leds: gpioledsgrp { @@ -286,5 +292,11 @@ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; }; }; -- cgit v1.2.3 From d4da51213a2ce337cb98a468886d5b0bc1e45bcc Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Tue, 28 Jun 2016 12:51:18 +0800 Subject: ARM: dts: rockchip: add eDP/panel display device nodes for rk3288-evb The default eDP panel on RK3288 EVB board is LG LP079QX1-SP0V TFT LCD, we haven't declared the panel regulator in the 'panel-simple' device node here, so the specific board like ACT8846 / RK8080 need to support the panel power supply. Signed-off-by: Yakir Yang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb.dtsi | 45 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 963365d12208..d59208b5eb6c 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -48,7 +48,7 @@ reg = <0x0 0x80000000>; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; brightness-levels = < 0 1 2 3 4 5 6 7 @@ -97,6 +97,21 @@ #clock-cells = <0>; }; + panel: panel { + compatible ="lg,lp079qx1-sp0v", "simple-panel"; + backlight = <&backlight>; + enable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>; + pinctrl-0 = <&lcd_cs>; + + ports { + panel_in: port { + panel_in_edp: endpoint { + remote-endpoint = <&edp_out_panel>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -170,6 +185,28 @@ cpu0-supply = <&vdd_cpu>; }; +&edp { + force-hpd; + status = "okay"; + + ports { + edp_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + edp_out_panel: endpoint { + reg = <0>; + remote-endpoint = <&panel_in_edp>; + }; + }; + }; +}; + +&edp_phy { + status = "okay"; +}; + &emmc { bus-width = <8>; cap-mmc-highspeed; @@ -280,6 +317,12 @@ }; }; + lcd { + lcd_cs: lcd-cs { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + pmic { pmic_int: pmic-int { rockchip,pins = ; -- cgit v1.2.3 From 1752371e1335a3a820ed7b64a2b8386ff3157751 Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Tue, 28 Jun 2016 12:51:21 +0800 Subject: ARM: dts: rockchip: add the panel power supply for rk3288-evb board with act8846 pmu Panel regulator is controller by a normal GPIO, so we need to write a regulator-fixed node for it. Signed-off-by: Yakir Yang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb-act8846.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index 452ca2441e84..041dd5d2d18c 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -206,6 +206,10 @@ }; }; +&panel { + power-supply = <&vcc_lcd>; +}; + &pinctrl { lcd { lcd_en: lcd-en { -- cgit v1.2.3 From f9fa05b60f5495cfd9bfb24ee3c2c139efb4a58c Mon Sep 17 00:00:00 2001 From: Yakir Yang Date: Tue, 28 Jun 2016 12:51:24 +0800 Subject: ARM: dts: rockchip: add the panel power supply for rk3288-evb board with rk808 pmu Panel regulator is controller by a regulator of the rk808 pmic. Signed-off-by: Yakir Yang Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-evb-rk808.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 736b08b0bfdd..44ebc6e59b3a 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -233,3 +233,7 @@ }; }; }; + +&panel { + power-supply = <&vcc_lcd>; +}; -- cgit v1.2.3 From 0b1115bcbc9d28014c38e93c6c2cd9e1c3f6f69f Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Thu, 7 Jul 2016 18:01:12 +0800 Subject: ARM: dts: rockchip: add dts for RK3288-Fennec boards This adds support for RK3288-Fennec boards. Currently supported are serial console, wired networking, hdmi output and USB. Signed-off-by: Xing Zheng Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3288-fennec.dts | 382 +++++++++++++++++++++ 3 files changed, 387 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-fennec.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index 666864517069..d7a9b2e9efa2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -110,6 +110,10 @@ Rockchip platforms device tree bindings - Rockchip RK3229 Evaluation board: - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; +- Rockchip RK3288 Fennec board: + Required root node properties: + - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; + - Rockchip RK3399 evb: Required root node properties: - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..40e3e96eae58 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -624,6 +624,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3229-evb.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb \ + rk3288-fennec.dtb \ rk3288-firefly-beta.dtb \ rk3288-firefly.dtb \ rk3288-miqi.dtb \ diff --git a/arch/arm/boot/dts/rk3288-fennec.dts b/arch/arm/boot/dts/rk3288-fennec.dts new file mode 100644 index 000000000000..2e3c34135ed8 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-fennec.dts @@ -0,0 +1,382 @@ +/* + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "rk3288.dtsi" + +/ { + model = "Rockchip RK3288 Fennec Board"; + compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; + + memory { + reg = <0x0 0x80000000>; + device_type = "memory"; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int &global_pwroff>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc6-supply = <&vcc_sys>; + vcc7-supply = <&vcc_sys>; + vcc8-supply = <&vcc_io>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc11-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_33: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_33"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_wl: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_wl"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_lcd: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_sd: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_sd"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_lan: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lan"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { + drive-strength = <8>; + }; + + pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { + bias-pull-up; + drive-strength = <8>; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + pmic { + pmic_int: pmic-int { + rockchip,pins = ; + }; + }; + + usbphy { + host_drv: host-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&host_drv>; + vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host1 { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&usb_hsic { + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; -- cgit v1.2.3 From 4421db1c2bb92592fc090a68deb0ad422e13a939 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Mon, 18 Jul 2016 23:32:32 +0800 Subject: ARM: dts: rockchip: add rk3288-firefly-reload The Firefly RK3288 Reload is a combination Firefly rk3288 core board with the Reload baseboard. Add a dtsi for the Firefly rk3288 core which can be included into the dts for the various baseboards in the future and dts for Reload base board. Currently supported are serial console, wired networking, eMMC and SD storage, SPFIF, IR receiver, LEDs, SDIO wifi and USB. But only the OTG could work on the host mode now, the other USB host can't work now, additional patches are required. Signed-off-by: Randy Li Acked-by: Rob Herring Signed-off-by: Heiko Stuebner --- Documentation/devicetree/bindings/arm/rockchip.txt | 4 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 338 +++++++++++++++++++ arch/arm/boot/dts/rk3288-firefly-reload.dts | 356 +++++++++++++++++++++ 4 files changed, 699 insertions(+) create mode 100644 arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi create mode 100644 arch/arm/boot/dts/rk3288-firefly-reload.dts diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt index d7a9b2e9efa2..a4f59b579685 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.txt +++ b/Documentation/devicetree/bindings/arm/rockchip.txt @@ -31,6 +31,10 @@ Rockchip platforms device tree bindings or - compatible = "firefly,firefly-rk3288-beta", "rockchip,rk3288"; +- Firefly Firefly-RK3288 Reload board: + Required root node properties: + - compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + - ChipSPARK PopMetal-RK3288 board: Required root node properties: - compatible = "chipspark,popmetal-rk3288", "rockchip,rk3288"; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 40e3e96eae58..0a65a7f86c8c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -627,6 +627,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-fennec.dtb \ rk3288-firefly-beta.dtb \ rk3288-firefly.dtb \ + rk3288-firefly-reload.dtb \ rk3288-miqi.dtb \ rk3288-popmetal.dtb \ rk3288-r89.dtb \ diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi new file mode 100644 index 000000000000..73c88ffd8260 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -0,0 +1,338 @@ +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "rk3288.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0 0x80000000>; + }; + + dovdd_1v8: dovdd-1v8-regulator { + compatible = "regulator-fixed"; + regulator-name = "dovdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc28_dvp>; + }; + + ext_gmac: external-gmac-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "ext_gmac"; + }; + + vbat_wl: vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_flash: flash-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_flash"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + + vcc_5v: usb-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_pwr>, <&emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc_flash>; + status = "okay"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC>; + assigned-clock-parents = <&ext_gmac>; + clock_in_out = "input"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>; + phy-supply = <&vcc_lan>; + phy-mode = "rgmii"; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>; + tx_delay = <0x30>; + rx_delay = <0x10>; + status = "ok"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + vdd_cpu: syr827@40 { + compatible = "silergy,syr827"; + fcs,suspend-voltage-selector = <1>; + reg = <0x40>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + regulator-enable-ramp-delay = <300>; + regulator-ramp-delay = <8000>; + vin-supply = <&vcc_sys>; + }; + + vdd_gpu: syr828@41 { + compatible = "silergy,syr828"; + fcs,suspend-voltage-selector = <1>; + reg = <0x41>; + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + vin-supply = <&vcc_sys>; + }; + + act8846: act8846@5a { + compatible = "active-semi,act8846"; + reg = <0x5a>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_vsel>, <&pwr_hold>; + system-power-controller; + + vp1-supply = <&vcc_sys>; + vp2-supply = <&vcc_sys>; + vp3-supply = <&vcc_sys>; + vp4-supply = <&vcc_sys>; + inl1-supply = <&vcc_sys>; + inl2-supply = <&vcc_sys>; + inl3-supply = <&vcc_20>; + + regulators { + vcc_ddr: REG1 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + vcc_io: REG2 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_log: REG3 { + regulator-name = "vdd_log"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + + vcc_20: REG4 { + regulator-name = "vcc_20"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + }; + + vccio_sd: REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd10_lcd: REG6 { + regulator-name = "vdd10_lcd"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vcca_33: REG7 { + regulator-name = "vcca_33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vcc_lan: REG8 { + regulator-name = "vcca_lan"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vccio_pmu: REG9 { + regulator-name = "vccio_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vdd_10: REG10 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + vccio_wl: vcc_18: REG11 { + regulator-name = "vcc_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vcc18_lcd: REG12 { + regulator-name = "vcc18_lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + audio-supply = <&vcca_33>; + bb-supply = <&vcc_io>; + dvp-supply = <&dovdd_1v8>; + flash0-supply = <&vcc_flash>; + flash1-supply = <&vcc_lan>; + gpio30-supply = <&vcc_io>; + gpio1830-supply = <&vcc_io>; + lcdc-supply = <&vcc_io>; + sdcard-supply = <&vccio_sd>; + wifi-supply = <&vccio_wl>; +}; + +&pinctrl { + pcfg_output_high: pcfg-output-high { + output-high; + }; + + pcfg_output_low: pcfg-output-low { + output-low; + }; + + pcfg_pull_up_drv_12ma: pcfg-pull-up-drv-12ma { + bias-pull-up; + drive-strength = <12>; + }; + + act8846 { + pwr_hold: pwr-hold { + rockchip,pins = <0 1 RK_FUNC_GPIO &pcfg_output_high>; + }; + + pmic_vsel: pmic-vsel { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>; + }; + }; + + gmac { + phy_int: phy-int { + rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_pmeb: phy-pmeb { + rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + phy_rst: phy-rst { + rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; +}; + +&tsadc { + rockchip,hw-tshut-mode = <0>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&vopb { + status = "okay"; +}; + +&vopb_mmu { + status = "okay"; +}; + +&vopl { + status = "okay"; +}; + +&vopl_mmu { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts new file mode 100644 index 000000000000..dd8ab233438f --- /dev/null +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -0,0 +1,356 @@ +/* + * Device tree file for Firefly Rockchip RK3288 Core board + * Copyright (c) 2016 Randy Li + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3288-firefly-reload-core.dtsi" + +/ { + model = "Firefly-RK3288-reload"; + compatible = "firefly,firefly-rk3288-reload", "rockchip,rk3288"; + + gpio-keys { + compatible = "gpio-keys"; + + power { + wakeup-source; + gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; + label = "GPIO Power"; + linux,code = ; + pinctrl-names = "default"; + pinctrl-0 = <&pwr_key>; + }; + }; + + ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + }; + + leds { + compatible = "gpio-leds"; + + power { + gpios = <&gpio8 2 GPIO_ACTIVE_LOW>; + label = "firefly:blue:power"; + pinctrl-names = "default"; + pinctrl-0 = <&power_led>; + panic-indicator; + }; + + work { + gpios = <&gpio8 1 GPIO_ACTIVE_LOW>; + label = "firefly:blue:user"; + linux,default-trigger = "rc-feedback"; + pinctrl-names = "default"; + pinctrl-0 = <&work_led>; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&hym8563>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable>; + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "SPDIF"; + simple-audio-card,dai-link@1 { /* S/PDIF - S/PDIF */ + cpu { sound-dai = <&spdif>; }; + codec { sound-dai = <&spdif_out>; }; + }; + }; + + spdif_out: spdif-out { + compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + }; + + vcc_host_5v: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc_host_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vcc_otg_5v: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc_otg_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + vin-supply = <&vcc_5v>; + }; + + /* + * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled + * by the dvp_pwr pin. + */ + vcc28_dvp: vcc28-dvp-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "vcc28_dvp"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + vin-supply = <&vcc_io>; + }; +}; + +&i2c0 { + hym8563: hym8563@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "xin32k"; + interrupt-parent = <&gpio7>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + }; +}; + +&i2c2 { + status = "okay"; + + codec: es8328@10 { + compatible = "everest,es8328"; + DVDD-supply = <&vcca_33>; + AVDD-supply = <&vcca_33>; + PVDD-supply = <&vcca_33>; + HPVDD-supply = <&vcca_33>; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + clock-names = "i2s_hclk", "i2s_clk"; + reg = <0x10>; + }; +}; + +&i2s { + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + sd-uhs-ddr50; + vmmc-supply = <&vcc_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdio0 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + disable-wp; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdio0_bus4>, <&sdio0_cmd>, <&sdio0_clk>, <&sdio0_int>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-ddr50; + vmmc-supply = <&vbat_wl>; + vqmmc-supply = <&vccio_wl>; + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>, <&uart0_cts>, <&uart0_rts>; + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; + +&usb_host1 { + pinctrl-names = "default"; + pinctrl-0 = <&usbhub_rst>; + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + +&pinctrl { + ir { + ir_int: ir-int { + rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + dvp { + dvp_pwr: dvp-pwr { + rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + keys { + pwr_key: pwr-key { + rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + power_led: power-led { + rockchip,pins = <8 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + work_led: work-led { + rockchip,pins = <8 1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc { + /* + * Default drive strength isn't enough to achieve even + * high-speed mode on firefly board so bump up to 12ma. + */ + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 17 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 18 RK_FUNC_1 &pcfg_pull_up_drv_12ma>, + <6 19 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_clk: sdmmc-clk { + rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_12ma>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_12ma>; + }; + + sdmmc_pwr: sdmmc-pwr { + rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdio { + wifi_enable: wifi-enable { + rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + usbhub_rst: usbhub-rst { + rockchip,pins = <8 3 RK_FUNC_GPIO &pcfg_output_high>; + }; + }; + + usb_otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; -- cgit v1.2.3 From 546a3521f251462128d877e48fb3544c74976ce4 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Sat, 26 Mar 2016 22:49:57 +0100 Subject: ARM: dts: rockchip: move rk3288 usbphy under the GRF node The rk3288 usbphy is completely enclosed in the general register files and the updated binding allows it to be a subnode of the GRF now. So move the node appropriately. Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288.dtsi | 63 +++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd33f0170890..e5c4a11f6bc6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -832,6 +832,37 @@ compatible = "rockchip,rk3288-io-voltage-domain"; status = "disabled"; }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; }; wdt: watchdog@ff800000 { @@ -1085,38 +1116,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; -- cgit v1.2.3 From e46f48ad86f4483dfaa5947a7b7dbd4a63b0398a Mon Sep 17 00:00:00 2001 From: Olivier Schonken Date: Tue, 5 Jul 2016 10:05:50 +0200 Subject: ARM: dts: at91: sama5d2: add ETM and ETB nodes Add node to support SAMA5D2 Embedded Trace Macrocell and Embedded Trace Buffer. This patch depends on coresight-etm3x: Add ARM ETM-A5 peripheral ID for proper coresight functionality. It also depends on clocksource: timer-atmel-pit: enable mck to not stall SAMA5D2 on bootup. Signed-off-by: Olivier Schonken Acked-by: Mathieu Poirier Acked-by: Boris Brezillon Signed-off-by: Alexandre Belloni --- arch/arm/boot/dts/sama5d2.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi index 353d0e5ec83b..7173ec9059a1 100644 --- a/arch/arm/boot/dts/sama5d2.dtsi +++ b/arch/arm/boot/dts/sama5d2.dtsi @@ -77,6 +77,35 @@ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>; }; + etb { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x740000 0x1000>; + + clocks = <&mck>; + clock-names = "apb_pclk"; + + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x73C000 0x1000>; + + clocks = <&mck>; + clock-names = "apb_pclk"; + + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; + memory { reg = <0x20000000 0x20000000>; }; -- cgit v1.2.3 From 02183a5250193aae6913ed3ee720be021ae92b03 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 15 Jul 2016 00:00:05 +0300 Subject: ARM: dts: r8a7792: add PFC support Define the generic R8A7792 part of the PFC device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 3fd61d7ab906..0b746ddd5cd6 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -108,6 +108,11 @@ #power-domain-cells = <1>; }; + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7792"; + reg = <0 0xe6060000 0 0x144>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; -- cgit v1.2.3 From 2cd452d19e6e79ea58c8022c43248b64d579db60 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 15 Jul 2016 00:00:56 +0300 Subject: ARM: dts: blanche: add SCIF0/3 pins Add the (previously omitted) SCIF0/3 pin data to the Blanche board's device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index e7b40f0e7da6..9b550bde939a 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -57,10 +57,28 @@ clock-frequency = <20000000>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif3_pins: scif3 { + groups = "scif3_data"; + function = "scif3"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + status = "okay"; }; &scif3 { + pinctrl-0 = <&scif3_pins>; + pinctrl-names = "default"; + status = "okay"; }; -- cgit v1.2.3 From 1d93a8b5a234282724f6f4a3113e1d32bea0ec71 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 14:02:01 -0700 Subject: ARM: dts: blanche: add Ethernet pins Add the (previously omitted) pin data for the SMSC LAN89218 Ethernet chip to the Blanche board's device tree: the chip's IRQ output is connected to the SoC's IRQ0 pin and its nCS input is connected to the SoC's EX_CS0# pin. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 9b550bde939a..4777a609ff81 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -50,6 +50,9 @@ reg-io-width = <4>; vddvario-supply = <&d3_3v>; vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; }; }; @@ -67,6 +70,17 @@ groups = "scif3_data"; function = "scif3"; }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; }; &scif0 { -- cgit v1.2.3 From 4e2b4f6626541dd791d468c9ccd2d0cc72cc0989 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 6 Jul 2016 01:01:22 +0300 Subject: ARM: dts: r8a7792: add GPIO clocks Describe the GPIO clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 0b746ddd5cd6..da3eb295c6f1 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -370,6 +370,27 @@ clock-output-names = "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; + mstp9_clks: mstp9_clks@e6150994 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, + <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>; + #clock-cells = <1>; + clock-indices = < + R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 + R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 + R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 + R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 + R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 + >; + clock-output-names = + "gpio7", "gpio6", "gpio5", "gpio4", + "gpio3", "gpio2", "gpio1", "gpio0", + "gpio11", "gpio10", "gpio9", "gpio8"; + }; }; /* External root clock */ -- cgit v1.2.3 From 63359c2ddc86bded339f38bde504994f123ebd63 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 6 Jul 2016 01:02:20 +0300 Subject: ARM: dts: r8a7792: add GPIO support Describe all 12 GPIO controllers in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 168 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 168 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index da3eb295c6f1..d5ab9474297e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -113,6 +113,174 @@ reg = <0 0xe6060000 0 0x144>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 23>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio6: gpio@e6055100 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055100 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio7: gpio@e6055200 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055200 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio8: gpio@e6055300 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055300 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 256 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio9: gpio@e6055400 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 288 17>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio10: gpio@e6055500 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055500 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 320 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + gpio11: gpio@e6055600 { + compatible = "renesas,gpio-r8a7792", + "renesas,gpio-rcar"; + reg = <0 0xe6055600 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 352 30>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a7792", "renesas,rcar-dmac"; -- cgit v1.2.3 From 08cafff67e8881e1622068924aaab3c3aa052b0b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 5 Jul 2016 00:22:38 +0300 Subject: ARM: dts: r8a7792: add EtherAVB clocks Add the EtherAVB clock and its parent, HP clock to the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index d5ab9474297e..f97b034da35f 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -471,6 +471,13 @@ clock-div = <6>; clock-mult = <1>; }; + hp_clk: hp { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + }; p_clk: p { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -538,6 +545,15 @@ clock-output-names = "hscif1", "hscif0", "scif3", "scif2", "scif1", "scif0"; }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&hp_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "etheravb"; + }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From b12dcdcc474977095ce72152b285be7f94d0efd3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 5 Jul 2016 00:23:30 +0300 Subject: ARM: dts: r8a7792: add EtherAVB support Define the generic R8A7792 part of the EtherAVB device node. Based on the commit 89aac8af1a60 ("ARM: dts: r8a7794: add EtherAVB support"). Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index f97b034da35f..37c9d95688cf 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -444,6 +444,18 @@ power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7792", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v1.2.3 From 47db051c22a03d41eac0d8193f3fe37b4f9768e9 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:19:44 +0300 Subject: ARM: dts: r8a7792: add CAN clocks The R-Car CAN controllers can derive the CAN bus clock not only from their peripheral clock input (clkp1) but also from the other internal clock (clkp2) and the external clock fed on the CAN_CLK pin. Describe those clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 37c9d95688cf..af8020bfc030 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -511,6 +511,13 @@ clock-div = <8>; clock-mult = <1>; }; + rcan_clk: rcan { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <49>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { @@ -572,7 +579,8 @@ reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>; + <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, + <&cp_clk>, <&cp_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 @@ -580,12 +588,14 @@ R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 + R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 >; clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "gpio9", "gpio8"; + "gpio11", "gpio10", "can1", "can0", + "gpio9", "gpio8"; }; }; @@ -604,4 +614,12 @@ /* This value must be overridden by the board. */ clock-frequency = <0>; }; + + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; }; -- cgit v1.2.3 From f947c02a0f86dffa5258ef347c6b6980953a9679 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:20:35 +0300 Subject: ARM: dts: r8a7792: add CAN support Define the generic R8A7792 parts of the CAN0/1 device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index af8020bfc030..1b96bf6393fb 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -456,6 +456,30 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_CAN0>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7792", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_CAN1>, + <&rcan_clk>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v1.2.3 From 38584104eafb6ed40ca06c8421dcc369c9015c1d Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 14 Jul 2016 23:21:15 +0300 Subject: ARM: dts: blanche: add CAN0 support Define the Blanche board dependent part of the CAN0 device node along with the CAN_CLK crystal. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 4777a609ff81..eeffba870211 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -60,6 +60,10 @@ clock-frequency = <20000000>; }; +&can_clk { + clock-frequency = <48000000>; +}; + &pfc { scif0_pins: scif0 { groups = "scif0_data"; @@ -81,6 +85,11 @@ function = "lbsc"; }; }; + + can0_pins: can0 { + groups = "can0_data", "can_clk"; + function = "can0"; + }; }; &scif0 { @@ -96,3 +105,10 @@ status = "okay"; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From 83701e00ded47e7f6390c6a123209426565046b7 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Thu, 21 Jul 2016 08:44:08 +0900 Subject: ARM: dts: r8a7794: Correct SDHI register size r8a7794 SDHI ch0 has SD_DMACR which is located in 0x324. This patch updates register size Based on work for the r8a7790 by Kuninori Morimoto. Cc: Kuninori Morimoto Signed-off-by: Simon Horman Reviewed-by: Wolfram Sang --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 685f986cf962..55737bca4e63 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -697,7 +697,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; - reg = <0 0xee100000 0 0x200>; + reg = <0 0xee100000 0 0x328>; interrupts = ; clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, -- cgit v1.2.3 From 1113603e39b1ea10d02f97c86c25d57b971cb470 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 13 Jul 2016 11:55:17 +0200 Subject: ARM: dts: mvebu: Add SPI1 pinctrl defines for Armada XP This patch defines and uses common Armada XP pinctrl settings in armada-xp.dtsi for the SPI1 interface (MPP13,14,16,17). Signed-off-by: Stefan Roese Reviewed-by: Thomas Petazzoni Cc: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-xp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 553349c07f28..40337909ac4c 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -94,6 +94,8 @@ spi1: spi@10680 { compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; }; @@ -362,6 +364,12 @@ marvell,function = "spi0"; }; + spi1_pins: spi1-pins { + marvell,pins = "mpp13", "mpp14", + "mpp16", "mpp17"; + marvell,function = "spi1"; + }; + uart2_pins: uart2-pins { marvell,pins = "mpp42", "mpp43"; marvell,function = "uart2"; -- cgit v1.2.3 From 0160a4b68987ef8df1d57529d13be7ed4f674374 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 13 Jul 2016 11:55:18 +0200 Subject: ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node This patch moves all Armada 370/XP/38x/39x SPI controller nodes from the 'internal-regs' node down into the 'soc' node. This is in preparation to enable the usage of the SPI direct access mode. A follow-up patch will add the static MBus mappings for the SPI devices into the 'reg' property of the SPI controller DT node. By moving these SPI controller nodes, this patch also makes use of the labels rather than keeping the tree structure. Signed-off-by: Stefan Roese Cc: Thomas Petazzoni Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Jason Cooper Cc: Mark Brown Cc: Arnd Bergmann Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-db.dts | 29 +++--- .../dts/armada-370-seagate-personal-cloud.dtsi | 40 ++++---- arch/arm/boot/dts/armada-370-synology-ds213j.dts | 112 ++++++++++----------- arch/arm/boot/dts/armada-370-xp.dtsi | 40 ++++---- arch/arm/boot/dts/armada-370.dtsi | 34 +++---- arch/arm/boot/dts/armada-385-db-ap.dts | 28 +++--- arch/arm/boot/dts/armada-385-linksys.dtsi | 9 +- arch/arm/boot/dts/armada-388-clearfog.dts | 48 ++++----- arch/arm/boot/dts/armada-388-db.dts | 25 ++--- arch/arm/boot/dts/armada-388-gp.dts | 30 +++--- arch/arm/boot/dts/armada-388-rd.dts | 25 ++--- arch/arm/boot/dts/armada-38x.dtsi | 48 ++++----- arch/arm/boot/dts/armada-398-db.dts | 48 ++++----- arch/arm/boot/dts/armada-39x.dtsi | 48 ++++----- arch/arm/boot/dts/armada-xp-axpwifiap.dts | 24 ++--- arch/arm/boot/dts/armada-xp-db.dts | 24 ++--- arch/arm/boot/dts/armada-xp-gp.dts | 24 ++--- arch/arm/boot/dts/armada-xp-linksys-mamba.dts | 24 ++--- arch/arm/boot/dts/armada-xp-synology-ds414.dts | 112 ++++++++++----------- arch/arm/boot/dts/armada-xp.dtsi | 27 +++-- 20 files changed, 398 insertions(+), 401 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 2364fc56ae13..033fa63544f7 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -155,20 +155,6 @@ status = "okay"; }; - spi0: spi@10600 { - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "mx25l25635e", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - }; - }; - nand@d0000 { status = "okay"; num-cs = <1>; @@ -274,3 +260,18 @@ compatible = "linux,spdif-dir"; }; }; + +&spi0 { + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mx25l25635e", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + }; +}; + diff --git a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi index 1aba08e4377c..01cded310cbc 100644 --- a/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi +++ b/arch/arm/boot/dts/armada-370-seagate-personal-cloud.dtsi @@ -68,26 +68,6 @@ phy-mode = "rgmii-id"; }; - spi@10600 { - status = "okay"; - pinctrl-0 = <&spi0_pins2>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - /* MX25L8006E */ - compatible = "mxicy,mx25l8005", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - - partition@0 { - label = "u-boot"; - reg = <0x0 0x100000>; - }; - }; - }; - usb@50000 { status = "okay"; }; @@ -176,3 +156,23 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + /* MX25L8006E */ + compatible = "mxicy,mx25l8005", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x100000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts index 8ca7a4340c0f..a9cc42776874 100644 --- a/arch/arm/boot/dts/armada-370-synology-ds213j.dts +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -87,62 +87,6 @@ status = "disabled"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000c0000>; /* 768KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000c0000 0x002d0000>; /* 2880KB */ - }; - - partition@00390000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x00390000 0x00440000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; - }; - i2c@11000 { compatible = "marvell,mv64xxx-i2c"; pinctrl-0 = <&i2c0_pins>; @@ -347,3 +291,59 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000c0000 0x002d0000>; /* 2880KB */ + }; + + partition@00390000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x00390000 0x00440000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index a718866ba52d..a0903cd9c8c8 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -148,26 +148,6 @@ interrupts = <50>; }; - spi0: spi@10600 { - reg = <0x10600 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = <30>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - reg = <0x10680 0x28>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = <92>; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; #address-cells = <1>; @@ -320,6 +300,26 @@ status = "disabled"; }; }; + + spi0: spi@10600 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = <30>; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = <92>; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 3b06aa835448..b4258105e91f 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -134,24 +134,6 @@ wt-override; }; - /* - * Default SPI pinctrl setting, can be overwritten on - * board level if a different configuration is used. - */ - spi0: spi@10600 { - compatible = "marvell,armada-370-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins1>; - pinctrl-names = "default"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-370-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - }; - i2c0: i2c@11000 { reg = <0x11000 0x20>; }; @@ -447,3 +429,19 @@ marvell,function = "ge1"; }; }; + +/* + * Default SPI pinctrl setting, can be overwritten on + * board level if a different configuration is used. + */ +&spi0 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins1>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 2d3fd6e76e2c..ca38200a4f0d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -65,20 +65,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi1: spi@10680 { - pinctrl-names = "default"; - pinctrl-0 = <&spi1_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <54000000>; - }; - }; - i2c0: i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -239,3 +225,17 @@ gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; }; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <54000000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi index 22f7a13e20b4..8f0e508f64ae 100644 --- a/arch/arm/boot/dts/armada-385-linksys.dtsi +++ b/arch/arm/boot/dts/armada-385-linksys.dtsi @@ -62,11 +62,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { - - spi@10600 { - status = "disabled"; - }; - i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -332,3 +327,7 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts index 2e0556af6e5e..2d2593023fd0 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dts +++ b/arch/arm/boot/dts/armada-388-clearfog.dts @@ -315,30 +315,6 @@ status = "okay"; }; - spi@10680 { - /* - * We don't seem to have the W25Q32 on the - * A1 Rev 2.0 boards, so disable SPI. - * CS0: W25Q32 (doesn't appear to be present) - * CS1: - * CS2: mikrobus - */ - pinctrl-0 = <&spi1_pins - &clearfog_spi1_cs_pins - &mikro_spi_pins>; - pinctrl-names = "default"; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <3000000>; - status = "disabled"; - }; - }; - usb@58000 { /* CON3, nearest power. */ status = "okay"; @@ -444,3 +420,27 @@ }; }; }; + +&spi1 { + /* + * We don't seem to have the W25Q32 on the + * A1 Rev 2.0 boards, so disable SPI. + * CS0: W25Q32 (doesn't appear to be present) + * CS1: + * CS2: mikrobus + */ + pinctrl-0 = <&spi1_pins + &clearfog_spi1_cs_pins + &mikro_spi_pins>; + pinctrl-names = "default"; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <3000000>; + status = "disabled"; + }; +}; diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts index ea93ed727030..de26c762239c 100644 --- a/arch/arm/boot/dts/armada-388-db.dts +++ b/arch/arm/boot/dts/armada-388-db.dts @@ -70,18 +70,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25q32", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -201,3 +189,16 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25q32", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts index fd75e5e9550f..895fa6cfa15a 100644 --- a/arch/arm/boot/dts/armada-388-gp.dts +++ b/arch/arm/boot/dts/armada-388-gp.dts @@ -64,21 +64,6 @@ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>; internal-regs { - spi@10600 { - pinctrl-names = "default"; - pinctrl-0 = <&spi0_pins>; - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <50000000>; - m25p,fast-read; - }; - }; - i2c@11000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins>; @@ -433,3 +418,18 @@ marvell,function = "gpio"; }; }; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <50000000>; + m25p,fast-read; + }; +}; diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts index 853f9735cc70..dd3462ddb6b9 100644 --- a/arch/arm/boot/dts/armada-388-rd.dts +++ b/arch/arm/boot/dts/armada-388-rd.dts @@ -70,18 +70,6 @@ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>; internal-regs { - spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "st,m25p128", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -142,3 +130,16 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,m25p128", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; + diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 3312be6c82cc..c065ecd8d36b 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -170,30 +170,6 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-380-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; @@ -649,6 +625,30 @@ no-memory-wc; status = "disabled"; }; + + spi0: spi@10600 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-380-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts index 788c3badb681..c5f14a767bce 100644 --- a/arch/arm/boot/dts/armada-398-db.dts +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -65,30 +65,6 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; internal-regs { - spi@10680 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <108000000>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0x1000000>; - }; - }; - }; - i2c@11000 { pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; @@ -151,3 +127,27 @@ }; }; }; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <108000000>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0x1000000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index dc6efd386dbc..251a2b6799d5 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -131,30 +131,6 @@ <0xc100 0x100>; }; - spi0: spi@10600 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = <0x10600 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-390-spi", - "marvell,orion-spi"; - reg = <0x10680 0x50>; - #address-cells = <1>; - #size-cells = <0>; - cell-index = <1>; - interrupts = ; - clocks = <&coreclk 0>; - status = "disabled"; - }; - i2c0: i2c@11000 { compatible = "marvell,mv64xxx-i2c"; reg = <0x11000 0x20>; @@ -501,6 +477,30 @@ status = "disabled"; }; }; + + spi0: spi@10600 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; + + spi1: spi@10680 { + compatible = "marvell,armada-390-spi", + "marvell,orion-spi"; + reg = ; + #address-cells = <1>; + #size-cells = <0>; + cell-index = <1>; + interrupts = ; + clocks = <&coreclk 0>; + status = "disabled"; + }; }; clocks { diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index 5c21b236721f..ce152719bc28 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -135,18 +135,6 @@ phy = <&phy1>; phy-mode = "rgmii-id"; }; - - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; }; }; @@ -179,3 +167,15 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts index 62422a90aeb2..075120bc3ec4 100644 --- a/arch/arm/boot/dts/armada-xp-db.dts +++ b/arch/arm/boot/dts/armada-xp-db.dts @@ -231,18 +231,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "m25p64", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - }; - }; - nand@d0000 { status = "okay"; num-cs = <1>; @@ -277,3 +265,15 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p64", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 061f4237760e..190e4eccb180 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -232,18 +232,6 @@ status = "okay"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - }; - }; - bm@c0000 { status = "okay"; }; @@ -262,3 +250,15 @@ }; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts index 7a461541ce50..076f27f22c3b 100644 --- a/arch/arm/boot/dts/armada-xp-linksys-mamba.dts +++ b/arch/arm/boot/dts/armada-xp-linksys-mamba.dts @@ -279,18 +279,6 @@ reg = <0x180000 0x780000>; /* 7.5MB */ }; }; - - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "everspin,mr25h256"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <40000000>; - }; - }; }; }; @@ -398,3 +386,15 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "everspin,mr25h256"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <40000000>; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index d17dab0a6f51..ae286736b90a 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -110,62 +110,6 @@ status = "disabled"; }; - spi0: spi@10600 { - status = "okay"; - - spi-flash@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "micron,n25q064", "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <20000000>; - - /* - * Warning! - * - * Synology u-boot uses its compiled-in environment - * and it seems Synology did not care to change u-boot - * default configuration in order to allow saving a - * modified environment at a sensible location. So, - * if you do a 'saveenv' under u-boot, your modified - * environment will be saved at 1MB after the start - * of the flash, i.e. in the middle of the uImage. - * For that reason, it is strongly advised not to - * change the default environment, unless you know - * what you are doing. - */ - partition@00000000 { /* u-boot */ - label = "RedBoot"; - reg = <0x00000000 0x000d0000>; /* 832KB */ - }; - - partition@000c0000 { /* uImage */ - label = "zImage"; - reg = <0x000d0000 0x002d0000>; /* 2880KB */ - }; - - partition@003a0000 { /* uInitramfs */ - label = "rd.gz"; - reg = <0x003a0000 0x00430000>; /* 4250KB */ - }; - - partition@007d0000 { /* MAC address and serial number */ - label = "vendor"; - reg = <0x007d0000 0x00010000>; /* 64KB */ - }; - - partition@007e0000 { - label = "RedBoot config"; - reg = <0x007e0000 0x00010000>; /* 64KB */ - }; - - partition@007f0000 { - label = "FIS directory"; - reg = <0x007f0000 0x00010000>; /* 64KB */ - }; - }; - }; - i2c@11000 { clock-frequency = <400000>; status = "okay"; @@ -362,3 +306,59 @@ marvell,function = "gpio"; }; }; + +&spi0 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index 40337909ac4c..4a5f99e65b51 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -84,21 +84,6 @@ wt-override; }; - spi0: spi@10600 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi0_pins>; - pinctrl-names = "default"; - }; - - spi1: spi@10680 { - compatible = "marvell,armada-xp-spi", - "marvell,orion-spi"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - }; - - i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; @@ -380,3 +365,15 @@ marvell,function = "uart3"; }; }; + +&spi0 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; +}; + +&spi1 { + compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 55877f58b0be83a4ffb4639a83f99c28df418e3e Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 13 Jul 2016 11:55:19 +0200 Subject: ARM: dts: mvebu: armada-370-xp: Add MBus mappings for all SPI devices This patch adds the static MBus mappings for all supported SPI devices (8 per controller) for the direct access SPI mode. They can be configured and enabled by setting these MBus mapping in the 'ranges' property of the per-board 'soc' node. If nothing is changed here, the default 'normal' (indirect) SPI mode is used. Signed-off-by: Stefan Roese Cc: Thomas Petazzoni Cc: Gregory CLEMENT Cc: Andrew Lunn Cc: Jason Cooper Cc: Mark Brown Cc: Arnd Bergmann Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-370-xp.dtsi | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index a0903cd9c8c8..3ccedc9dffb2 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -302,7 +302,15 @@ }; spi0: spi@10600 { - reg = ; + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ #address-cells = <1>; #size-cells = <0>; cell-index = <0>; @@ -312,7 +320,15 @@ }; spi1: spi@10680 { - reg = ; + reg = , /* control */ + , /* CS0 */ + , /* CS1 */ + , /* CS2 */ + , /* CS3 */ + , /* CS4 */ + , /* CS5 */ + , /* CS6 */ + ; /* CS7 */ #address-cells = <1>; #size-cells = <0>; cell-index = <1>; -- cgit v1.2.3 From b583e291ba282d0d9851d4c95a234979f5a90e63 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:06 +0200 Subject: ARM: dts: mvebu: a385-db-ap: enable USB (orion-ehci) port The Armada 385 Access Point Development board contains USB port, which can be handled by existing orion-ehci driver. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-db-ap.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index ca38200a4f0d..4f7c3aad8d01 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -141,6 +141,10 @@ bm,pool-short = <3>; }; + usb@58000 { + status = "okay"; + }; + /* CON4 */ ethernet@70000 { pinctrl-names = "default"; -- cgit v1.2.3 From 4ec17292a9a0b9cf7eb43f59aa638fbbbe66467e Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:07 +0200 Subject: ARM: dts: mvebu: a385-db-ap: add default partition description for NAND The Armada 385 Access Point Development board contains NAND FLSH which is already enabled in existing dts. Nevertheless the default partition description was missing. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-385-db-ap.dts | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts index 4f7c3aad8d01..db5b9f6b615d 100644 --- a/arch/arm/boot/dts/armada-385-db-ap.dts +++ b/arch/arm/boot/dts/armada-385-db-ap.dts @@ -168,15 +168,35 @@ nfc: flash@d0000 { status = "okay"; - #address-cells = <1>; - #size-cells = <1>; - num-cs = <1>; nand-ecc-strength = <4>; nand-ecc-step-size = <512>; marvell,nand-keep-config; marvell,nand-enable-arbiter; nand-on-flash-bbt; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00800000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00800000 0x00400000>; + read-only; + }; + + partition@c00000 { + label = "Root"; + reg = <0x00c00000 0x3f400000>; + }; + }; }; usb3@f0000 { -- cgit v1.2.3 From 061492cfad9f11dbc32df741a7164f307b69b6e6 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:08 +0200 Subject: ARM: dts: mvebu: armada-390: add missing compatibility string and bracket The armada-390.dtsi was broken since the first patch which adds Device Tree files for Armada 39x SoC was introduced. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Cc: # 4.0+ Fixes 538da83 ("ARM: mvebu: add Device Tree files for Armada 39x SoC and board") Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-390.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi index 094e39c66039..6cd18d8aaac7 100644 --- a/arch/arm/boot/dts/armada-390.dtsi +++ b/arch/arm/boot/dts/armada-390.dtsi @@ -47,6 +47,8 @@ #include "armada-39x.dtsi" / { + compatible = "marvell,armada390"; + soc { internal-regs { pinctrl@18000 { @@ -54,4 +56,5 @@ reg = <0x18000 0x20>; }; }; + }; }; -- cgit v1.2.3 From 39f3c23f51cdd0dfe9ef5a618f14060f4003909e Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:09 +0200 Subject: ARM: dts: mvebu: armada-39x: update the SDHCI node on Armada 39x Commit 1140011ee9d9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") has extended the Device Tree binding used to describe PXAv3 SDHCI controllers in order to be able to use the SDR50 and DDR50 modes. This commit updates the Device Tree description of the Armada 39x SDHCI controller in other to take advantage of this functionality. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 251a2b6799d5..b11f86d2a3cf 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -356,7 +356,10 @@ sdhci@d8000 { compatible = "marvell,armada-380-sdhci"; - reg = <0xd8000 0x1000>, <0xdc000 0x100>; + reg-names = "sdhci", "mbus", "conf-sdio3"; + reg = <0xd8000 0x1000>, + <0xdc000 0x100>, + <0x18454 0x4>; interrupts = ; clocks = <&gateclk 17>; mrvl,clk-delay-cycles = <0x1F>; -- cgit v1.2.3 From 8deebf8b8a8323cfa590e9ea1a1507abe12d75e0 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:10 +0200 Subject: ARM: dts: mvebu: armada-39x: enable PMU, CA9 SoC Controller and Coherency fabric This commit enables: - CA9's Performance Monitor Unit - CA9 MPcore SoC Controller - Coherency fabric on Armada 39x, basing on the Armada 38x (which has the same CA9 CPU). Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Lior Amsalem Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index b11f86d2a3cf..0a13265f8f52 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -78,6 +78,11 @@ }; }; + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts-extended = <&mpic 3>; + }; + soc { compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus", "simple-bus"; @@ -298,6 +303,16 @@ reg = <0x20800 0x10>; }; + mpcore-soc-ctrl@20d20 { + compatible = "marvell,armada-380-mpcore-soc-ctrl"; + reg = <0x20d20 0x6c>; + }; + + coherency-fabric@21010 { + compatible = "marvell,armada-380-coherency-fabric"; + reg = <0x21010 0x1c>; + }; + pmsu@22000 { compatible = "marvell,armada-390-pmsu", "marvell,armada-380-pmsu"; -- cgit v1.2.3 From 16ae883151ab64ebd0cdf8436e794df26bae2e24 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:11 +0200 Subject: ARM: dts: mvebu: armada-39x: enable the thermal sensor in Armada-39x SoCs The whole Armada 39x SoC family of processors has thermal sensor which can be supported with existing driver. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 0a13265f8f52..54df09f97595 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -389,6 +389,12 @@ clocks = <&mainpll>; clock-output-names = "nand"; }; + + thermal@e8078 { + compatible = "marvell,armada380-thermal"; + reg = <0xe4078 0x4>, <0xe4074 0x4>; + status = "okay"; + }; }; pcie-controller { -- cgit v1.2.3 From 100a20a9ff895297115b8359b0ed858faa3d4e44 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:12 +0200 Subject: ARM: dts: mvebu: armada-39x: enable watchdog for all Armada-39x SoCs The whole Armada 39x SoC family of processors has watchdog which can be supported with existing driver. Signed-off-by: Grzegorz Jaszczyk Reviewed-by: Lior Amsalem Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 54df09f97595..785f661ee610 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -298,6 +298,14 @@ clock-names = "nbclk", "fixed"; }; + watchdog@20300 { + compatible = "marvell,armada-380-wdt"; + reg = <0x20300 0x34>, <0x20704 0x4>, + <0x18260 0x4>; + clocks = <&coreclk 2>, <&refclk>; + clock-names = "nbclk", "fixed"; + }; + cpurst@20800 { compatible = "marvell,armada-370-cpu-reset"; reg = <0x20800 0x10>; @@ -534,5 +542,12 @@ #clock-cells = <0>; clock-frequency = <1000000000>; }; + + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; }; -- cgit v1.2.3 From d81a914fc630fe969a71f6f275cb66e232c1f71d Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:13 +0200 Subject: ARM: dts: mvebu: armada-39x: add missing nodes describing GPIO's The whole Armada 39x SoC family of processors has GPIO's which all can be supported with existing driver. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 785f661ee610..c521378e239f 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -55,6 +55,8 @@ compatible = "marvell,armada390"; aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; @@ -250,6 +252,34 @@ }; }; + gpio0: gpio@18100 { + compatible = "marvell,orion-gpio"; + reg = <0x18100 0x40>; + ngpios = <32>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + + gpio1: gpio@18140 { + compatible = "marvell,orion-gpio"; + reg = <0x18140 0x40>; + ngpios = <28>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = , + , + , + ; + }; + system-controller@18200 { compatible = "marvell,armada-390-system-controller", "marvell,armada-370-xp-system-controller"; -- cgit v1.2.3 From daab54316b957c12f097a7b133f96b8ba031bdd6 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:15 +0200 Subject: ARM: dts: mvebu: armada-39x: enable rtc for all Armada-39x SoCs Despite that FS states that rtc is present only in A395 and A398 and not in A390, the rtc is working with A390. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-39x.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index c521378e239f..34cba87f9200 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -397,6 +397,13 @@ }; }; + rtc@a3800 { + compatible = "marvell,armada-380-rtc"; + reg = <0xa3800 0x20>, <0x184a0 0x0c>; + reg-names = "rtc", "rtc-soc"; + interrupts = ; + }; + flash@d0000 { compatible = "marvell,armada370-nand"; reg = <0xd0000 0x54>; -- cgit v1.2.3 From eebead7853de56809ddd16aea5e5cddba286175e Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:16 +0200 Subject: ARM: dts: mvebu: armada-395: add support for the Armada 395 SoC family Beside interfaces described in the armada-39x.dtsi, the Armada 395 SoC family supports: 2 x SATA3 (2 ports in one unit) and the USB3.0 Signed-off-by: Grzegorz Jaszczyk Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/arm/marvell/armada-39x.txt | 11 +++- arch/arm/boot/dts/armada-395.dtsi | 76 ++++++++++++++++++++++ 2 files changed, 85 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/armada-395.dtsi diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt index 53d4ff9ea8ad..2d922126cbcc 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt @@ -8,8 +8,15 @@ Required root node property: - compatible: must contain "marvell,armada390" -In addition, boards using the Marvell Armada 398 SoC shall have the -following property before the previous one: +In addition, boards using the Marvell Armada 395 SoC shall have the +following property before the common "marvell,armada390" one: + +Required root node property: + +compatible: must contain "marvell,armada395" + +Boards using the Marvell Armada 398 SoC shall have the following +property before the common "marvell,armada390" one: Required root node property: diff --git a/arch/arm/boot/dts/armada-395.dtsi b/arch/arm/boot/dts/armada-395.dtsi new file mode 100644 index 000000000000..ab5dc49f2bff --- /dev/null +++ b/arch/arm/boot/dts/armada-395.dtsi @@ -0,0 +1,76 @@ +/* + * Device Tree Include file for Marvell Armada 395 SoC. + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "armada-39x.dtsi" + +/ { + compatible = "marvell,armada395", "marvell,armada390"; + + soc { + internal-regs { + pinctrl@18000 { + compatible = "marvell,mv88f6925-pinctrl"; + reg = <0x18000 0x20>; + }; + + sata@a8000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xa8000 0x2000>; + interrupts = ; + clocks = <&gateclk 15>; + status = "disabled"; + }; + + usb3@f0000 { + compatible = "marvell,armada-380-xhci"; + reg = <0xf0000 0x4000>,<0xf4000 0x4000>; + interrupts = ; + clocks = <&gateclk 9>; + status = "disabled"; + }; + }; + }; +}; -- cgit v1.2.3 From d2dd856e8c21083560e92ded3e81a6b28cedef2b Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:17 +0200 Subject: ARM: dts: mvebu: armada-398: update the dtsi about missing interfaces Beside interfaces described in the armada-39x.dtsi and armada-395.dtsi, the Armada 398 SoC family supports 2 additional SATA port (2 ports in one unit) Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-398.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi index fdc25914e3a3..234a99891a29 100644 --- a/arch/arm/boot/dts/armada-398.dtsi +++ b/arch/arm/boot/dts/armada-398.dtsi @@ -44,7 +44,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "armada-39x.dtsi" +#include "armada-395.dtsi" / { compatible = "marvell,armada398", "marvell,armada390"; @@ -55,6 +55,14 @@ compatible = "marvell,mv88f6928-pinctrl"; reg = <0x18000 0x20>; }; + + sata@e0000 { + compatible = "marvell,armada-380-ahci"; + reg = <0xe0000 0x2000>; + interrupts = ; + clocks = <&gateclk 30>; + status = "disabled"; + }; }; }; }; -- cgit v1.2.3 From dacf5f546598fefa6fe8b4c6d5e7eb05326863e3 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:18 +0200 Subject: ARM: dts: mvebu: armada-398-db: enable supported usb interfaces The Marvell Armada 398 Development board contains both USB2.0 and USB3.0 ports, which can be handled by existing drivers. Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-398-db.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts index c5f14a767bce..268c8349c884 100644 --- a/arch/arm/boot/dts/armada-398-db.dts +++ b/arch/arm/boot/dts/armada-398-db.dts @@ -84,6 +84,10 @@ status = "okay"; }; + usb@58000 { + status = "okay"; + }; + flash@d0000 { status = "okay"; pinctrl-0 = <&nand_pins>; @@ -108,6 +112,10 @@ reg = <0x1000000 0x3f000000>; }; }; + + usb3@f8000 { + status = "okay"; + }; }; pcie-controller { -- cgit v1.2.3 From 0c2123a69e06488f9328aec9f3ee99948002483d Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:19 +0200 Subject: ARM: dts: mvebu: armada-390-db: add support for the Armada 390 DB board This commit adds description for following features for this board: - Serial port - I2C buses - 16MB SPI-NOR - USB2.0 - USB3.0 - PCIe interfaces Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-390-db.dts | 175 ++++++++++++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) create mode 100644 arch/arm/boot/dts/armada-390-db.dts diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts new file mode 100644 index 000000000000..9d0d9b2e9bfc --- /dev/null +++ b/arch/arm/boot/dts/armada-390-db.dts @@ -0,0 +1,175 @@ +/* + * Device Tree file for Marvell Armada 390 Development Board + * (DB-88F6920) + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-390.dtsi" + +/ { + model = "Marvell Armada 390 Development Board"; + compatible = "marvell,a390-db", "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000>; /* 2 GB */ + }; + + soc { + ranges = ; + + internal-regs { + spi@10680 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", + "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; + }; + + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + }; + + /* CON104 */ + serial@12000 { + status = "okay"; + }; + + /* CON97 */ + usb@58000 { + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x800000>; + }; + partition@800000 { + label = "Linux"; + reg = <0x800000 0x800000>; + }; + partition@1000000 { + label = "Filesystem"; + reg = <0x1000000 0x3f000000>; + }; + }; + }; + + /* CON98 */ + usb3@f8000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + /* CON30 */ + pcie@1,0 { + status = "okay"; + }; + + /* CON44 */ + pcie@2,0 { + status = "okay"; + }; + + /* CON61 */ + pcie@3,0 { + status = "okay"; + }; + }; + }; +}; -- cgit v1.2.3 From 35664512358115f2ddefbff2769af5d3cbe554f1 Mon Sep 17 00:00:00 2001 From: Grzegorz Jaszczyk Date: Thu, 4 Aug 2016 12:14:20 +0200 Subject: ARM: dts: mvebu: armada-395-gp: add support for the Armada 395 GP Board This commit adds description for the following features for this board: - Serial port - PCIe interfaces - USB2.0 - USB3.0 - SDIO - 1024 MiB NAND-FLASH - SATA - I2C buses Signed-off-by: Grzegorz Jaszczyk Acked-by: Gregory CLEMENT Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/arm/marvell/armada-39x.txt | 4 + arch/arm/boot/dts/armada-395-gp.dts | 163 +++++++++++++++++++++ 2 files changed, 167 insertions(+) create mode 100644 arch/arm/boot/dts/armada-395-gp.dts diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt index 2d922126cbcc..89468664f6ea 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt @@ -15,6 +15,10 @@ Required root node property: compatible: must contain "marvell,armada395" +Example: + +compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; + Boards using the Marvell Armada 398 SoC shall have the following property before the common "marvell,armada390" one: diff --git a/arch/arm/boot/dts/armada-395-gp.dts b/arch/arm/boot/dts/armada-395-gp.dts new file mode 100644 index 000000000000..2cdbba804c1e --- /dev/null +++ b/arch/arm/boot/dts/armada-395-gp.dts @@ -0,0 +1,163 @@ +/* + * Device Tree file for Marvell Armada 395 GP board + * + * Copyright (C) 2016 Marvell + * + * Grzegorz Jaszczyk + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without + * any warranty of any kind, whether express or implied. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "armada-395.dtsi" + +/ { + model = "Marvell Armada 395 GP Board"; + compatible = "marvell,a395-gp", "marvell,armada395", + "marvell,armada390"; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x40000000>; /* 1 GB */ + }; + + soc { + ranges = ; + + internal-regs { + i2c@11000 { + status = "okay"; + clock-frequency = <100000>; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + }; + }; + + serial@12000 { + /* + * Exported on the micro USB connector CON17 + * through an FTDI + */ + status = "okay"; + }; + + /* CON1 */ + usb@58000 { + status = "okay"; + }; + + /* CON2 */ + sata@a8000 { + status = "okay"; + }; + + flash@d0000 { + status = "okay"; + pinctrl-0 = <&nand_pins>; + pinctrl-names = "default"; + num-cs = <1>; + marvell,nand-keep-config; + marvell,nand-enable-arbiter; + nand-on-flash-bbt; + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0x00000000 0x00600000>; + read-only; + }; + + partition@800000 { + label = "uImage"; + reg = <0x00600000 0x00400000>; + read-only; + }; + + partition@1000000 { + label = "Root"; + reg = <0x00a00000 0x3f600000>; + }; + }; + }; + + /* CON18 */ + sdhci@d8000 { + clock-frequency = <200000000>; + broken-cd; + wp-inverted; + bus-width = <8>; + status = "okay"; + no-1-8-v; + }; + + /* CON4 */ + usb3@f0000 { + status = "okay"; + }; + }; + + pcie-controller { + status = "okay"; + + /* + * The two PCIe units are accessible through + * mini PCIe slot on the board. + */ + + /* CON7 */ + pcie@2,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + + /* CON8 */ + pcie@4,0 { + /* Port 3, Lane 0 */ + status = "okay"; + }; + }; + }; +}; -- cgit v1.2.3 From 1ff4023aabffd4efbc4fa80fbed8b1e43c40ac55 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 15 Jul 2016 08:54:19 +0200 Subject: ARM: dts: sun6i-a31s-colorfly-e708-q1: Add full otg support Now that we've all the necessary bits in place we can enable full otg support on these tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 32 +++++++++++++++++------ 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts index e182eec6d878..9040bb9f80f3 100644 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -106,6 +106,13 @@ allwinner,drive = ; allwinner,pull = ; }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; }; &p2wi { @@ -116,6 +123,8 @@ reg = <0x68>; interrupt-parent = <&nmi_intc>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; }; }; @@ -185,24 +194,31 @@ regulator-name = "vcc-pg"; }; +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + &simplefb_lcd { vcc-lcd-supply = <®_dc1sw>; vcc-pg-supply = <®_dldo2>; }; -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp221 pmic on the board. - * - * Once we have axp221 power-supply and vbus-usb support we should switch - * to fully supporting otg. - */ &usb_otg { - dr_mode = "host"; + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { status = "okay"; }; &usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; usb1_vbus-supply = <®_dldo1>; status = "okay"; }; -- cgit v1.2.3 From 97c6d82b0f0a5a5e3f80a1554ae96c07aaa75dfe Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Tue, 26 Jul 2016 23:04:31 +0200 Subject: ARM: dts: sun8i: Add dts file for the Orange Pi PC Plus SBC There is a new Orange Pi PC *Plus* version available now, this is an extended version of the regular Orange Pi PC with sdio wifi and an eMMC. Signed-off-by: Hans de Goede [Maxime: Fix model and compatible] Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 88 +++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..6b3bdb6f7e7f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -791,6 +791,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ + sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN9I) += \ diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts new file mode 100644 index 000000000000..851fd2c2cc8c --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* The Orange Pi PC Plus is an extended version of the regular PC */ +#include "sun8i-h3-orangepi-pc.dts" + +/ { + model = "Xunlong Orange Pi PC Plus"; + compatible = "xunlong,orangepi-pc-plus", "allwinner,sun8i-h3"; + + aliases { + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189ftv; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_8bit_pins>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&mmc2_8bit_pins { + /* Increase drive strength for DDR modes */ + allwinner,drive = ; + /* eMMC is missing pull-ups */ + allwinner,pull = ; +}; -- cgit v1.2.3 From fbd073102c6910cc3b2f35b98ddc1fea5eb12795 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 9 Jul 2016 22:21:57 +0200 Subject: ARM: dts: sun8i: Add ethernet1 alias to Orange Pi 2 dts This will allow u-boot to fill in a mac-address for Orange Pi 2 variants which use an sdio wifi without an eeprom for the mac. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index f93f5d1695c4..f89fe00ddec5 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -54,6 +54,8 @@ aliases { serial0 = &uart0; + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */ + ethernet1 = &rtl8189; }; chosen { @@ -131,6 +133,14 @@ bus-width = <4>; non-removable; status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189: sdio_wifi@1 { + reg = <1>; + }; }; &pio { -- cgit v1.2.3 From 07d4510f5251a9992bff642f4fe84386bd55adc7 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 7 Jul 2016 19:08:58 -0400 Subject: dt-bindings: net: bgmac: add bindings documentation for bgmac Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- .../devicetree/bindings/net/brcm,amac.txt | 24 ++++++++++++++++++++++ .../devicetree/bindings/net/brcm,bgmac-nsp.txt | 24 ++++++++++++++++++++++ 2 files changed, 48 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/brcm,amac.txt create mode 100644 Documentation/devicetree/bindings/net/brcm,bgmac-nsp.txt diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt new file mode 100644 index 000000000000..ba5ecc1041a5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/brcm,amac.txt @@ -0,0 +1,24 @@ +Broadcom AMAC Ethernet Controller Device Tree Bindings +------------------------------------------------------------- + +Required properties: + - compatible: "brcm,amac" or "brcm,nsp-amac" + - reg: Address and length of the GMAC registers, + Address and length of the GMAC IDM registers + - reg-names: Names of the registers. Must have both "amac_base" and + "idm_base" + - interrupts: Interrupt number + +Optional properties: +- mac-address: See ethernet.txt file in the same directory + +Examples: + +amac0: ethernet@18022000 { + compatible = "brcm,nsp-amac"; + reg = <0x18022000 0x1000>, + <0x18110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/net/brcm,bgmac-nsp.txt b/Documentation/devicetree/bindings/net/brcm,bgmac-nsp.txt new file mode 100644 index 000000000000..022946caa7e2 --- /dev/null +++ b/Documentation/devicetree/bindings/net/brcm,bgmac-nsp.txt @@ -0,0 +1,24 @@ +Broadcom GMAC Ethernet Controller Device Tree Bindings +------------------------------------------------------------- + +Required properties: + - compatible: "brcm,bgmac-nsp" + - reg: Address and length of the GMAC registers, + Address and length of the GMAC IDM registers + - reg-names: Names of the registers. Must have both "gmac_base" and + "idm_base" + - interrupts: Interrupt number + +Optional properties: +- mac-address: See ethernet.txt file in the same directory + +Examples: + +gmac0: ethernet@18022000 { + compatible = "brcm,bgmac-nsp"; + reg = <0x18022000 0x1000>, + <0x18110000 0x1000>; + reg-names = "gmac_base", "idm_base"; + interrupts = ; + status = "disabled"; +}; -- cgit v1.2.3 From 13d04f20935cc4e334576a520069d6e7b85a82f2 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Fri, 8 Jul 2016 11:56:02 -0400 Subject: ARM: dts: NSP: Add AMAC entries Add Device Tree entries for the Ethernet devices (AMAC) present on the Broadcom Northstar Plus SoCs. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 18 ++++++++++++++++++ arch/arm/boot/dts/bcm958625k.dts | 8 ++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index c3bf7d23f136..80b51806dc10 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -209,6 +209,24 @@ #dma-cells = <1>; }; + amac0: ethernet@22000 { + compatible = "brcm,nsp-amac"; + reg = <0x022000 0x1000>, + <0x110000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; + }; + + amac1: ethernet@23000 { + compatible = "brcm,nsp-amac"; + reg = <0x023000 0x1000>, + <0x111000 0x1000>; + reg-names = "amac_base", "idm_base"; + interrupts = ; + status = "disabled"; + }; + nand: nand@26000 { compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1"; reg = <0x026000 0x600>, diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 2d8422632b2b..18bab8320257 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -56,6 +56,14 @@ status = "okay"; }; +&amac0 { + status = "okay"; +}; + +&amac1 { + status = "okay"; +}; + &pcie0 { status = "okay"; }; -- cgit v1.2.3 From bf2289bedef42426250283ce0e44ec64937920d4 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 8 Jul 2016 11:49:28 -0700 Subject: ARM: dts: NSP: Add Switch Register Access Block node Add the Switch Register Access Block node, this peripheral is identical to the BCM5301x Northstar SoC, but we utilize the SoC-wide "brcm,nsp-srab" compatible string to illustrate the integration difference here. Reviewed-by: Andrew Lunn Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index 80b51806dc10..d39c38da015c 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -264,6 +264,17 @@ clock-names = "apb_pclk"; }; + srab: srab@36000 { + compatible = "brcm,nsp-srab"; + reg = <0x36000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + /* ports are defined in board DTS */ + }; + i2c0: i2c@38000 { compatible = "brcm,iproc-i2c"; reg = <0x38000 0x50>; -- cgit v1.2.3 From 1bc1d822cdd37829076ffe8dcf0fbe0ee8143c5b Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Fri, 8 Jul 2016 11:49:29 -0700 Subject: ARM: dts: NSP: Add BCM958625HR switch ports Add the layout of the switch ports found on the BCM958625HR reference board. The CPU port is hooked up to the AMAC0 Ethernet controlelr adapter, so we also enable it. Reviewed-by: Andrew Lunn Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625hr.dts | 49 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 03b8bbeb694f..4239e58cf97f 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -109,3 +109,52 @@ groups = "nand_grp"; }; }; + +&amac0 { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm58625-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; -- cgit v1.2.3 From 2709d3932c47191b99a545f821ab09e355637eaf Mon Sep 17 00:00:00 2001 From: RafaÅ‚ MiÅ‚ecki Date: Wed, 1 Jun 2016 22:07:07 +0200 Subject: ARM: BCM5301X: Specify PHY of USB 2.0 in DT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Driver for Northstar USB 2.0 PHY was added in 4.7-rc1 by: commit d3feb4067335 ("phy: bcm-ns-usb2: new driver for USB 2.0 PHY on Northstar"). It should be used to let EHCI platform driver init PHY. Signed-off-by: RafaÅ‚ MiÅ‚ecki Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm5301x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 8af47913b3b4..ae4b3880616d 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -140,6 +140,15 @@ }; }; + usb2_phy: usb2-phy { + compatible = "brcm,ns-usb2-phy"; + reg = <0x1800c000 0x1000>; + reg-names = "dmu"; + #phy-cells = <0>; + clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>; + clock-names = "phy-ref-clk"; + }; + axi@18000000 { compatible = "brcm,bus-axi"; reg = <0x18000000 0x1000>; @@ -232,6 +241,8 @@ #address-cells = <1>; #size-cells = <1>; + + phys = <&usb2_phy>; }; usb3: usb3@23000 { -- cgit v1.2.3 From 4a590fbfc353bab3bb501850a4d81b79dc8dda87 Mon Sep 17 00:00:00 2001 From: Yendapally Reddy Dhananjaya Reddy Date: Tue, 5 Jul 2016 02:00:26 -0400 Subject: ARM: dts: NSP: Add PWM Support to DT Add PWM support to the device tree for the Broadcom Northstar Plus SoC. Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm-nsp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi index d39c38da015c..7c9e0fae9bb9 100644 --- a/arch/arm/boot/dts/bcm-nsp.dtsi +++ b/arch/arm/boot/dts/bcm-nsp.dtsi @@ -241,6 +241,14 @@ brcm,nand-has-wp; }; + pwm: pwm@31000 { + compatible = "brcm,iproc-pwm"; + reg = <0x31000 0x28>; + clocks = <&osc>; + #pwm-cells = <3>; + status = "disabled"; + }; + rng: rng@33000 { compatible = "brcm,bcm-nsp-rng"; reg = <0x33000 0x14>; -- cgit v1.2.3 From c53beb47f621e4a56f31af9f86470041655516c7 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Thu, 14 Jul 2016 16:14:17 -0400 Subject: ARM: dts: NSP: Correct RAM amount for BCM958625HR board The BCM958625HR board has 2GB of RAM available. Increase the amount from 512MB to 2GB and add the device type to the memory entry. Fixes: 9a4865d42fe5 ("ARM: dts: NSP: Specify RAM amount for BCM958625HR board") Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625hr.dts | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 4239e58cf97f..4caa8fa7dfee 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -47,7 +47,8 @@ }; memory { - reg = <0x60000000 0x20000000>; + device_type = "memory"; + reg = <0x60000000 0x80000000>; }; }; -- cgit v1.2.3 From 70725d6e97ac7772cd99332ddc05c7faea56fe9c Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:38:56 -0400 Subject: ARM: dts: NSP: Enable SATA on bcm958625hr Add SATA support to bcm958625hr DTS Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625hr.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 4caa8fa7dfee..0059d9fb6026 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -159,3 +159,15 @@ }; }; }; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; -- cgit v1.2.3 From bb239550d8767b379be3f8bfd76d02f475754937 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:38:57 -0400 Subject: ARM: dts: NSP: Enable SATA and add i2c devices on XMC Enable SATA on bcm958625xmc and add the i2c devices present. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958525xmc.dts | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index d257e83dedfc..a337f2d6a912 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -47,6 +47,24 @@ }; }; +&i2c0 { + temperature-sensor@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "st,m41t81"; + reg = <0x68>; + }; +}; + &nand { nandcs@0 { compatible = "brcm,nandcs"; @@ -85,7 +103,7 @@ }; }; -/* XHCI, SATA, MMC, and Ethernet support needed to be complete */ +/* XHCI, MMC, and Ethernet support needed to be complete */ &uart0 { status = "okay"; @@ -99,6 +117,18 @@ status = "okay"; }; +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + &pinctrl { pinctrl-names = "default"; pinctrl-0 = <&nand_sel>; -- cgit v1.2.3 From 21af8f454696c83d4e001f9547a969aba7810731 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:38:58 -0400 Subject: ARM: dts: NSP: Specify RAM amount for BCM958625K board Add 2GB of memory starting at physical offset 0x6000_0000. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625k.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts index 18bab8320257..05c5f98c8782 100644 --- a/arch/arm/boot/dts/bcm958625k.dts +++ b/arch/arm/boot/dts/bcm958625k.dts @@ -46,6 +46,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; }; &uart0 { -- cgit v1.2.3 From 70c341cfe9939174c1b9960eba55bc6012556afc Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:38:59 -0400 Subject: ARM: dts: NSP: Specify RAM amount for BCM958525XMC board Add 1GB of memory starting at physical offset 0x6000_0000. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958525xmc.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index a337f2d6a912..9517360fd904 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -45,6 +45,11 @@ chosen { stdout-path = "serial0:115200n8"; }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; }; &i2c0 { -- cgit v1.2.3 From b1aaf88bb7dc64fef21b853b404c267c7a2bc6c1 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:00 -0400 Subject: ARM: dts: NSP: Add GPIO reboot method to bcm958625hr DTS file Add the ability to reboot the bcm958625hr board via GPIO. Unfortunately, not all of the NSP based boards use the same GPIO pin and one doesn't have the ability to reboot via GPIO at all. So, this will need to be specified per DTS file. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958625hr.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts index 0059d9fb6026..442002597063 100644 --- a/arch/arm/boot/dts/bcm958625hr.dts +++ b/arch/arm/boot/dts/bcm958625hr.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-nsp.dtsi" +#include / { model = "NorthStar Plus SVK (BCM958625HR)"; @@ -50,6 +51,12 @@ device_type = "memory"; reg = <0x60000000 0x80000000>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; &nand { -- cgit v1.2.3 From 10baed1cdfca0bd6357a3a9048e8b72c844d29ec Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:01 -0400 Subject: ARM: dts: NSP: Add GPIO reboot method to bcm958625xmc DTS file Add the ability to reboot the bcm958625xmc board via GPIO. Unfortunately, not all of the NSP based boards use the same GPIO pin and one doesn't have the ability to reboot via GPIO at all. So, this will need to be specified per DTS file. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/bcm958525xmc.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts index 9517360fd904..959cde911c3c 100644 --- a/arch/arm/boot/dts/bcm958525xmc.dts +++ b/arch/arm/boot/dts/bcm958525xmc.dts @@ -33,6 +33,7 @@ /dts-v1/; #include "bcm-nsp.dtsi" +#include / { model = "NorthStar Plus XMC (BCM958525xmc)"; @@ -50,6 +51,12 @@ device_type = "memory"; reg = <0x60000000 0x40000000>; }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 31 GPIO_ACTIVE_LOW>; + priority = <200>; + }; }; &i2c0 { -- cgit v1.2.3 From e3227c128990deb8a9a12236fe4796a5951d0d22 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:02 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm958525er Create a new device tree file for the Broadcom Northstar Plus bcm958525er SVK. This SVK has 2GB RAM, 2 ports Ethernet, 2 eSATA, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future is support for the USB. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm958525er.dts | 142 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 143 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958525er.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..84555f4bac31 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm21664-garnet.dtb \ bcm23550-sparrow.dtb dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958525er.dtb \ bcm958525xmc.dtb \ bcm958625hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts new file mode 100644 index 000000000000..be7f2f8ecf39 --- /dev/null +++ b/arch/arm/boot/dts/bcm958525er.dts @@ -0,0 +1,142 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958525ER)"; + compatible = "brcm,bcm58525", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + + +&amac1 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 088e3148cff387af5f56605bd8fa387eace46b06 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:03 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm958522er Create a new device tree file for the Broadcom Northstar Plus bcm958522er SVK. This SVK has 2GB RAM, 2 ports Ethernet, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future is support for the USB. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm958522er.dts | 130 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958522er.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 84555f4bac31..aa6f2d2ddf25 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -102,6 +102,7 @@ dtb-$(CONFIG_ARCH_BCM_MOBILE) += \ bcm21664-garnet.dtb \ bcm23550-sparrow.dtb dtb-$(CONFIG_ARCH_BCM_NSP) += \ + bcm958522er.dtb \ bcm958525er.dtb \ bcm958525xmc.dtb \ bcm958625hr.dtb \ diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts new file mode 100644 index 000000000000..a21b0fd21f4e --- /dev/null +++ b/arch/arm/boot/dts/bcm958522er.dts @@ -0,0 +1,130 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958522ER)"; + compatible = "brcm,bcm58522", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + + +&amac1 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From f27eacf247da6a10deee9a9f8a75b749be921471 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:04 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm988312hr Create a new device tree file for the Broadcom Northstar Plus bcm988312hr SVK. This SVK has 2GB RAM, 5 ports Ethernet, 2 eSATA, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future is support for the USB. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm988312hr.dts | 182 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 183 insertions(+) create mode 100644 arch/arm/boot/dts/bcm988312hr.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index aa6f2d2ddf25..2c23c0a5a439 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -106,6 +106,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958525er.dtb \ bcm958525xmc.dtb \ bcm958625hr.dtb \ + bcm988312hr.dtb \ bcm958625k.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ berlin2-sony-nsz-gs7.dtb \ diff --git a/arch/arm/boot/dts/bcm988312hr.dts b/arch/arm/boot/dts/bcm988312hr.dts new file mode 100644 index 000000000000..104afe98a43b --- /dev/null +++ b/arch/arm/boot/dts/bcm988312hr.dts @@ -0,0 +1,182 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM988312HR)"; + compatible = "brcm,bcm88312", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata_phy1 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&srab { + compatible = "brcm,bcm88312-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From d454c3762437b6652626a6e6f12bcb607d81e842 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:05 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm958623hr Create a new device tree file for the Broadcom Northstar Plus bcm958623hr SVK. This SVK has 2GB RAM, 5 ports Ethernet, SATA, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future are support for the USB and SLIC audio. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm958623hr.dts | 178 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958623hr.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2c23c0a5a439..a29b64d5d69b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -105,6 +105,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958522er.dtb \ bcm958525er.dtb \ bcm958525xmc.dtb \ + bcm958623hr.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ bcm958625k.dtb diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts new file mode 100644 index 000000000000..4ceb8fef8041 --- /dev/null +++ b/arch/arm/boot/dts/bcm958623hr.dts @@ -0,0 +1,178 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958623HR)"; + compatible = "brcm,bcm58623", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 and SLIC support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&srab { + compatible = "brcm,bcm58623-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&sata_phy0 { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 2f8bc002e069a10e777ab92b9ac53d3669b3d8d3 Mon Sep 17 00:00:00 2001 From: Jon Mason Date: Wed, 3 Aug 2016 14:39:06 -0400 Subject: ARM: dts: NSP: Add new DT file for bcm958622hr Create a new device tree file for the Broadcom Northstar Plus bcm958622hr SVK. This SVK has 2GB RAM, 5 port Ethernet, 2 PCI slots, and 1 UART. Also, it has the ability to reboot via GPIO. To be added in the future are support for the USB and SLIC audio. Signed-off-by: Jon Mason Signed-off-by: Florian Fainelli --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/bcm958622hr.dts | 170 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 171 insertions(+) create mode 100644 arch/arm/boot/dts/bcm958622hr.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a29b64d5d69b..8e11aae1b95f 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -105,6 +105,7 @@ dtb-$(CONFIG_ARCH_BCM_NSP) += \ bcm958522er.dtb \ bcm958525er.dtb \ bcm958525xmc.dtb \ + bcm958622hr.dtb \ bcm958623hr.dtb \ bcm958625hr.dtb \ bcm988312hr.dtb \ diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts new file mode 100644 index 000000000000..ad2aa87dd15a --- /dev/null +++ b/arch/arm/boot/dts/bcm958622hr.dts @@ -0,0 +1,170 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2016 Broadcom. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-nsp.dtsi" +#include + +/ { + model = "NorthStar Plus SVK (BCM958622HR)"; + compatible = "brcm,bcm58622", "brcm,nsp"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x60000000 0x80000000>; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpioa 15 GPIO_ACTIVE_LOW>; + priority = <200>; + }; +}; + +/* USB 2/3 and SLIC support needed to be complete */ + +&amac0 { + status = "okay"; +}; + +&nand { + nandcs@0 { + compatible = "brcm,nandcs"; + reg = <0>; + nand-on-flash-bbt; + + #address-cells = <1>; + #size-cells = <1>; + + nand-ecc-strength = <24>; + nand-ecc-step-size = <1024>; + + brcm,nand-oob-sector-size = <27>; + + partition@0 { + label = "nboot"; + reg = <0x00000000 0x00200000>; + read-only; + }; + partition@200000 { + label = "nenv"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "nsystem"; + reg = <0x00600000 0x00a00000>; + }; + partition@1000000 { + label = "nrootfs"; + reg = <0x01000000 0x03000000>; + }; + partition@4000000 { + label = "ncustfs"; + reg = <0x04000000 0x3c000000>; + }; + }; +}; + +&pcie0 { + status = "okay"; +}; + +&pcie1 { + status = "okay"; +}; + +&pinctrl { + pinctrl-names = "default"; + pinctrl-0 = <&nand_sel>; + nand_sel: nand_sel { + function = "nand"; + groups = "nand_grp"; + }; +}; + +&srab { + compatible = "brcm,bcm58622-srab", "brcm,nsp-srab"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + label = "port0"; + reg = <0>; + }; + + port@1 { + label = "port1"; + reg = <1>; + }; + + port@2 { + label = "port2"; + reg = <2>; + }; + + port@3 { + label = "port3"; + reg = <3>; + }; + + port@4 { + label = "port4"; + reg = <4>; + }; + + port@5 { + ethernet = <&amac0>; + label = "cpu"; + reg = <5>; + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From c007b3a697ac4a9a11947bec63d2ae443a29cde1 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Fri, 8 Jul 2016 23:22:54 +0200 Subject: ARM: dts: imx6qdl: don't configure reserved pad settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Several dts files set a bit in the SPEED field for pads RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there doesn't have an effect and the bit reads as zero. Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-riotboard.dts | 22 +++++++++++----------- arch/arm/boot/dts/imx6q-arm2.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-ba16.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-cm-fx6.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-evi.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-gw5400-a.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-marsboard.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-novena.dts | 12 ++++++------ arch/arm/boot/dts/imx6q-sbc6x.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6q-tbs2910.dts | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-apalis.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 12 ++++++------ arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-rex.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-udoo.dtsi | 24 ++++++++++++------------ arch/arm/boot/dts/imx6qdl-wandboard.dtsi | 24 ++++++++++++------------ 28 files changed, 323 insertions(+), 323 deletions(-) diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index 2becd7cd6544..75d73437adf7 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -376,18 +376,18 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: IO voltage: pull up */ + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#0: pull down */ + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#1: pull up */ + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts index d8acf15611e4..4989d0bff10f 100644 --- a/arch/arm/boot/dts/imx6q-arm2.dts +++ b/arch/arm/boot/dts/imx6q-arm2.dts @@ -79,19 +79,19 @@ fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi index f2adc60723da..308e11cea1db 100644 --- a/arch/arm/boot/dts/imx6q-ba16.dtsi +++ b/arch/arm/boot/dts/imx6q-ba16.dtsi @@ -448,19 +448,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* FEC Reset */ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* AR8033 Interrupt */ diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts index b5de7e620905..59bc5a4dce17 100644 --- a/arch/arm/boot/dts/imx6q-cm-fx6.dts +++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts @@ -168,18 +168,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts index 905907325f3b..908dab68bdca 100644 --- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts +++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts @@ -324,18 +324,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index 4fa56019225e..9647c099acc6 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -303,19 +303,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 >; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 0511137d1e23..747bc104ad00 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -421,18 +421,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index 3f8013c85fb9..f7995c513b67 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -252,26 +252,26 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x0a0b1 /* AR8035 pin strapping: IO voltage: pull up */ - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 /* AR8035 pin strapping: PHYADDR#0: pull down */ - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x130b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x13030 /* AR8035 pin strapping: PHYADDR#1: pull down */ - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x130b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x13030 /* AR8035 pin strapping: MODE#1: pull up */ - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 /* AR8035 pin strapping: MODE#3: pull up */ - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 /* AR8035 pin strapping: MODE#0: pull down */ - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x13030 /* GPIO16 -> AR8035 25MHz */ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* RGMII_nRST */ diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index 5acd0c63b33b..1723e89e3acc 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -549,12 +549,12 @@ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b028 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b028 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* Ethernet reset */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts index 86cf09364664..255733063ea4 100644 --- a/arch/arm/boot/dts/imx6q-sbc6x.dts +++ b/arch/arm/boot/dts/imx6q-sbc6x.dts @@ -31,19 +31,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index d7c8ccb2da95..06f492e17ca7 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -284,19 +284,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 >; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 315e033ff1d8..99e323b57261 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -586,19 +586,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Ethernet PHY reset */ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 /* Ethernet PHY interrupt */ diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi index da1341d47b14..b2c083d57598 100644 --- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi +++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi @@ -67,18 +67,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 1340e2760406..afec2c7628ef 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -238,18 +238,18 @@ imx6qdl-gw51xx { pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 8bf1020affa0..208e3c291165 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -382,18 +382,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index a3dd0c41b995..35b9e808a4bb 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -371,18 +371,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 5a8dbabbd20f..5f8f1ea6d2a2 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -478,18 +478,18 @@ pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi index f8d945a56525..d5c3aa88adbe 100644 --- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi +++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi @@ -254,19 +254,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index cfd50ea1ed48..880bd782a5b7 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -361,12 +361,12 @@ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 9677bf323823..b0b3220a1fd9 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -484,19 +484,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 97d9c333902b..db868bc42c0f 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -394,19 +394,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x000b0 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index d6d98d426384..e4b894c61a95 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -231,19 +231,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index cacf5933707d..17704a5c1bcb 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -196,19 +196,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* Phy reset */ MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0 diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 6aa193fb283f..e000e6f12bf5 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -345,19 +345,19 @@ fsl,pins = < MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi index f65fdfc2536d..81dd6cd1937d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi @@ -359,19 +359,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 /* Phy reset */ MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index d77ea9423bbc..8e9e0d98db2f 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -380,19 +380,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 >; }; diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi index 3bee2f910067..c96c91d83678 100644 --- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi +++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi @@ -132,18 +132,18 @@ imx6q-udoo { pinctrl_enet: enetgrp { fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi index 3ffe00c557f1..2b9c2be436f9 100644 --- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi @@ -109,19 +109,19 @@ fsl,pins = < MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; -- cgit v1.2.3 From ffebc8c0344934db710afc76e3bfda11a823bb3d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Jul 2016 11:19:06 -0300 Subject: ARM: dts: imx7s-warp: Add initial support Add the initial support for the Warp7 board. For more information about this reference design, please visit: https://www.element14.com/community/docs/DOC-79058/l/warp-7-the-next-generation-wearable-reference-platform Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx7s-warp.dts | 246 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 248 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx7s-warp.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..98c4b9d6ba9c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -417,7 +417,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-nitrogen7.dtb \ imx7d-sbc-imx7.dtb \ imx7d-sdb.dtb \ - imx7s-colibri-eval-v3.dtb + imx7s-colibri-eval-v3.dtb \ + imx7s-warp.dtb dtb-$(CONFIG_SOC_LS1021A) += \ ls1021a-qds.dtb \ ls1021a-twr.dtb diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts new file mode 100644 index 000000000000..e318c989c18f --- /dev/null +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -0,0 +1,246 @@ +/* + * Copyright (C) 2016 NXP Semiconductors. + * Author: Fabio Estevam + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "imx7s.dtsi" + +/ { + model = "Warp i.MX7 Board"; + compatible = "warp,imx7s-warp", "fsl,imx7s"; + + memory { + reg = <0x80000000 0x20000000>; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pfuze3000@08 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + fsl,tuning-step = <2>; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b + >; + }; +}; -- cgit v1.2.3 From 942526c35e97b7758b4a07ba456870f4ca15c1c6 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Thu, 14 Jul 2016 12:30:34 +0200 Subject: ARM: i.MX6 Phytec PFLA02: Add supplies for the SoC internal regulators The SoC internal regulators for the CPU and the SoC come from the DA9063 vdd_core and vdd_soc. Add this relationship to the device tree so that the voltage drop on the SoC internal LDO regulators can be minimized. Signed-off-by: Sascha Hauer Acked-by: Mark Brown Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index e4b894c61a95..e0280cac2484 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -379,6 +379,18 @@ status = "disabled"; }; +®_arm { + vin-supply = <&vddcore_reg>; +}; + +®_pu { + vin-supply = <&vddsoc_reg>; +}; + +®_soc { + vin-supply = <&vddsoc_reg>; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; -- cgit v1.2.3 From 9eebb750bb3ab56cb00911cd01fb00aad52f0d82 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Mon, 18 Jul 2016 13:25:10 -0300 Subject: ARM: dts: imx6ul-pico-hobbit: Add Wifi support imx6ul-pico-hobbit has a bcm4343 wifi chip connected to usdhc2 port. Add support for it. Signed-off-by: Vanessa Maegima Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 86f68faded0e..7b18dc4727a9 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -100,6 +100,18 @@ gpio = <&gpio1 6 0>; }; + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6ul-sgtl5000"; @@ -325,12 +337,21 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; no-1-8-v; + non-removable; keep-power-in-suspend; wakeup-source; + vmmc-supply = <®_brcm>; status = "okay"; }; &iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x10b0 /* WL_REG_ON */ + MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x10b0 /* WL_HOST_WAKE */ + >; + }; + pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x1b0b0 -- cgit v1.2.3 From 38b8da79163be3fe4a83f02df77edb0157b1b49f Mon Sep 17 00:00:00 2001 From: "Cooper Jr., Franklin" Date: Mon, 11 Jul 2016 14:11:46 -0500 Subject: ARM: dts: da850: Add new ECAP and EPWM bindings For some devices, the PWMSS is a parent of eCAP and ePWM and provides the functional clocks for those submodules. The ti,am33xx-ecap and ti,am33xx-ehrpwm bindings were based on this parent child relationship where the functional clock would be grabbed from the module's parent. However, DA850 doesn't have a PWMSS and the eCAP and ePWM provides their functional clock themselves. Therefore, prefer the new binding that doesn't assume this parent child relationship. Signed-off-by: Franklin S Cooper Jr Acked-by: Rob Herring [nsekhar@ti.com: minor commit message fixes] Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 25f0f8e6dde5..09cf663c4170 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -274,31 +274,36 @@ status = "disabled"; }; ehrpwm0: pwm@300000 { - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x300000 0x2000>; status = "disabled"; }; ehrpwm1: pwm@302000 { - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm"; + compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", + "ti,am33xx-ehrpwm"; #pwm-cells = <3>; reg = <0x302000 0x2000>; status = "disabled"; }; ecap0: ecap@306000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x306000 0x80>; status = "disabled"; }; ecap1: ecap@307000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x307000 0x80>; status = "disabled"; }; ecap2: ecap@308000 { - compatible = "ti,da850-ecap", "ti,am33xx-ecap"; + compatible = "ti,da850-ecap", "ti,am3352-ecap", + "ti,am33xx-ecap"; #pwm-cells = <3>; reg = <0x308000 0x80>; status = "disabled"; -- cgit v1.2.3 From 10ead752aab9755f4044abc64b51b0264a72853c Mon Sep 17 00:00:00 2001 From: Karl Beldan Date: Thu, 4 Aug 2016 11:06:56 +0000 Subject: ARM: dts: da850: Add missing pin muxing for the UARTs This adds 2 pinctrl groups (rtscts, rxtx) for each of the 3 UARTs. Signed-off-by: Karl Beldan Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 09cf663c4170..5aac622c7959 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -41,6 +41,42 @@ pinctrl-single,function-mask = <0xf>; status = "disabled"; + serial0_rtscts_pins: pinmux_serial0_rtscts_pins { + pinctrl-single,bits = < + /* UART0_RTS UART0_CTS */ + 0x0c 0x22000000 0xff000000 + >; + }; + serial0_rxtx_pins: pinmux_serial0_rxtx_pins { + pinctrl-single,bits = < + /* UART0_TXD UART0_RXD */ + 0x0c 0x00220000 0x00ff0000 + >; + }; + serial1_rtscts_pins: pinmux_serial1_rtscts_pins { + pinctrl-single,bits = < + /* UART1_CTS UART1_RTS */ + 0x00 0x00440000 0x00ff0000 + >; + }; + serial1_rxtx_pins: pinmux_serial1_rxtx_pins { + pinctrl-single,bits = < + /* UART1_TXD UART1_RXD */ + 0x10 0x22000000 0xff000000 + >; + }; + serial2_rtscts_pins: pinmux_serial2_rtscts_pins { + pinctrl-single,bits = < + /* UART2_CTS UART2_RTS */ + 0x00 0x44000000 0xff000000 + >; + }; + serial2_rxtx_pins: pinmux_serial2_rxtx_pins { + pinctrl-single,bits = < + /* UART2_TXD UART2_RXD */ + 0x10 0x00220000 0x00ff0000 + >; + }; nand_cs3_pins: pinmux_nand_pins { pinctrl-single,bits = < /* EMA_OE, EMA_WE */ -- cgit v1.2.3 From 44524a010a55fc523e1d901613d5ee213cb79b97 Mon Sep 17 00:00:00 2001 From: Karl Beldan Date: Fri, 5 Aug 2016 20:29:49 +0000 Subject: ARM: dts: da850: Add basic DTS for the LCDK The LCDK is the successor to the late Hawkboard. Among the differences are the flash (16bits vs 8bits) and some pins (MMC, LEDs, buttons, some external connectors), however the main components remain the same (eth. phy, audio codec, video decoder and DAC) except for the main PMIC, different and hard-wired on the LCDK (the LDOs and DCDCs are always on). A DT-only boot with this addition gives functional UART, reboot via watchdog, RTC, ethernet and MMC (I added the CD GPIO for the MMC although davinci_mmc doesn't call the OF facilities of mmc core). Cc: Sekhar Nori Tested-by: Kevin Hilman Signed-off-by: Karl Beldan Signed-off-by: Sekhar Nori --- Documentation/devicetree/bindings/arm/davinci.txt | 4 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/da850-lcdk.dts | 70 +++++++++++++++++++++++ arch/arm/mach-davinci/da8xx-dt.c | 1 + 4 files changed, 76 insertions(+) create mode 100644 arch/arm/boot/dts/da850-lcdk.dts diff --git a/Documentation/devicetree/bindings/arm/davinci.txt b/Documentation/devicetree/bindings/arm/davinci.txt index cfaeda4274e6..f0841ce725b5 100644 --- a/Documentation/devicetree/bindings/arm/davinci.txt +++ b/Documentation/devicetree/bindings/arm/davinci.txt @@ -5,6 +5,10 @@ DA850/OMAP-L138/AM18x Evaluation Module (EVM) board Required root node properties: - compatible = "ti,da850-evm", "ti,da850"; +DA850/OMAP-L138/AM18x L138/C6748 Development Kit (LCDK) board +Required root node properties: + - compatible = "ti,da850-lcdk", "ti,da850"; + EnBW AM1808 based CMC board Required root node properties: - compatible = "enbw,cmc", "ti,da850; diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..f80f5b74c87a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -114,6 +114,7 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ dtb-$(CONFIG_ARCH_CLPS711X) += \ ep7211-edb7211.dtb dtb-$(CONFIG_ARCH_DAVINCI) += \ + da850-lcdk.dtb \ da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_DIGICOLOR) += \ diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts new file mode 100644 index 000000000000..dbcca0bc18d0 --- /dev/null +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2016 BayLibre, Inc. + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "da850.dtsi" +#include + +/ { + model = "DA850/AM1808/OMAP-L138 LCDK"; + compatible = "ti,da850-lcdk", "ti,da850"; + + aliases { + serial2 = &serial2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0xc0000000 0x08000000>; + }; +}; + +&pmx_core { + status = "okay"; +}; + +&serial2 { + pinctrl-names = "default"; + pinctrl-0 = <&serial2_rxtx_pins>; + status = "okay"; +}; + +&wdt { + status = "okay"; +}; + +&rtc0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&mdio { + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>; + bus_freq = <2200000>; + status = "okay"; +}; + +ð0 { + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + status = "okay"; +}; + +&mmc0 { + max-frequency = <50000000>; + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; + cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c index 754f478110b4..ca997114b1f4 100644 --- a/arch/arm/mach-davinci/da8xx-dt.c +++ b/arch/arm/mach-davinci/da8xx-dt.c @@ -49,6 +49,7 @@ static void __init da850_init_machine(void) static const char *const da850_boards_compat[] __initconst = { "enbw,cmc", + "ti,da850-lcdk", "ti,da850-evm", "ti,da850", NULL, -- cgit v1.2.3 From fe683922cb436097ac5b1f65148fa0db3a6735a3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:10:31 +0300 Subject: ARM: dts: r8a7792: add SD clocks Describe the SDHI0 clock and its parent, SD clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 1b96bf6393fb..4148c5867c07 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -535,6 +535,13 @@ clock-div = <8>; clock-mult = <1>; }; + sd_clk: sd { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + }; rcan_clk: rcan { compatible = "fixed-factor-clock"; clocks = <&pll1_div2_clk>; @@ -564,6 +571,15 @@ >; clock-output-names = "sys-dmac1", "sys-dmac0"; }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&sd_clk>; + #clock-cells = <1>; + renesas,clock-indices = ; + clock-output-names = "sdhi0"; + }; mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; -- cgit v1.2.3 From ce01b14ecf19a18cd95e698f915f5ea582086c21 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:11:26 +0300 Subject: ARM: dts: r8a7792: add SDHI support Define the generic R8A7792 part of the SDHI0 device node. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 4148c5867c07..228860d9464a 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -435,6 +435,18 @@ status = "disabled"; }; + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7792"; + reg = <0 0xee100000 0 0x328>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7792", "renesas,rcar-gen2-jpu"; -- cgit v1.2.3 From eedee25c2181ffd5463a994d456349dd39dc1b54 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:48:33 +0300 Subject: ARM: dts: r8a7792: add I2C clocks Describe the I2C[0-5] clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 228860d9464a..353bc303b165 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -632,7 +632,8 @@ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cp_clk>, <&cp_clk>; + <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, + <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 @@ -642,12 +643,16 @@ R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 + R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 + R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 + R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 >; clock-output-names = "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "gpio11", "gpio10", "can1", "can0", - "gpio9", "gpio8"; + "gpio9", "gpio8", "i2c5", "i2c4", + "i2c3", "i2c2", "i2c1", "i2c0"; }; }; -- cgit v1.2.3 From 78082700c8885a2b370c23ed9caec781fdf72139 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 21:49:12 +0300 Subject: ARM: dts: r8a7792: add I2C support Define the generic R8A7792 parts of the I2C[0-5] device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 82 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 353bc303b165..89f248c5cd9e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -18,6 +18,15 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; +}; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -468,6 +477,79 @@ status = "disabled"; }; + /* I2C doesn't need pinmux */ + i2c0: i2c@e6508000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <6>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + compatible = "renesas,i2c-r8a7792"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can"; -- cgit v1.2.3 From 62855bcf15796de1231c93652d385a8b11be75c4 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 22:16:38 +0300 Subject: ARM: dts: r8a7792: add VIN clocks Describe the VIN[0-5] clocks and their parent, ZG clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 89f248c5cd9e..dbe2f28fee99 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -643,6 +643,13 @@ clock-div = <49>; clock-mult = <1>; }; + zg_clk: zg { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <5>; + clock-mult = <1>; + }; /* Gate clocks */ mstp1_clks: mstp1_clks@e6150134 { @@ -702,10 +709,17 @@ compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>; + clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, + <&zg_clk>, <&zg_clk>, <&hp_clk>; #clock-cells = <1>; - clock-indices = ; - clock-output-names = "etheravb"; + clock-indices = < + R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 + R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 + R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 + R8A7792_CLK_ETHERAVB + >; + clock-output-names = "vin5", "vin4", "vin3", "vin2", + "vin1", "vin0", "etheravb"; }; mstp9_clks: mstp9_clks@e6150994 { compatible = "renesas,r8a7792-mstp-clocks", -- cgit v1.2.3 From a2d30b9c555f02c6a2aa389fbd41a103503242dd Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 23 Jul 2016 22:17:42 +0300 Subject: ARM: dts: r8a7792: add VIN support Define the generic R8A7792 parts of the VIN[0-5] device nodes. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index dbe2f28fee99..e1f85a9904d0 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -25,6 +25,12 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; + vin4 = &vin4; + vin5 = &vin5; }; cpus { @@ -574,6 +580,66 @@ status = "disabled"; }; + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a7792", + "renesas,rcar-gen2-vin"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v1.2.3 From 0b1f0e374404f70b77c0f79c6f16fdcf5484552b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 23:59:18 +0300 Subject: ARM: dts: r8a7794: add audio clocks Describe the external audio clocks (signals AUDIO_CLK[ABC]) required by the sound driver. Boards that provide audio clocks need to override the clock frequencies. This patch is based on the commit 0d3dbde84a45 ("ARM: shmobile: r8a7791: add audio clock on DTSI"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 55737bca4e63..5d1fded79633 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -952,6 +952,27 @@ clock-frequency = <0>; }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7794-cpg-clocks", -- cgit v1.2.3 From 2a29f9d6fea82485941449c2328af5b2a4ea636f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 23:59:59 +0300 Subject: ARM: dts: r8a7794: add MSTP5 clocks Add some MSTP5 clocks to the R8A7794 device tree. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 9 +++++++++ include/dt-bindings/clock/r8a7794-clock.h | 1 + 2 files changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 5d1fded79633..1c2d3846d70e 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1204,6 +1204,15 @@ clock-indices = ; clock-output-names = "irqc"; }; + mstp5_clks: mstp5_clks@e6150144 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&hp_clk>, <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "audmac0", "pwm"; + }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index a3491ba2f6ec..f8279eca033e 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -67,6 +67,7 @@ #define R8A7794_CLK_IRQC 7 /* MSTP5 */ +#define R8A7794_CLK_AUDIO_DMAC0 2 #define R8A7794_CLK_PWM 23 /* MSTP7 */ -- cgit v1.2.3 From 975fb77f874be95e50e653e90bcbcf09c08e66c2 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 27 Jul 2016 14:01:01 -0700 Subject: ARM: dts: r8a7794: add MSTP10 clocks Add MSTP10 clocks to the R8A7794 device tree. This patch is based on the commit ee9141522dcf ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 52 +++++++++++++++++++++++++++++++ include/dt-bindings/clock/r8a7794-clock.h | 24 ++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 1c2d3846d70e..cba41c199fd8 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1267,6 +1267,58 @@ "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; }; + mstp10_clks: mstp10_clks@e6150998 { + compatible = "renesas,r8a7794-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; + clocks = <&p_clk>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&p_clk>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>, + <&mstp10_clks R8A7794_CLK_SCU_ALL>; + #clock-cells = <1>; + clock-indices = ; + clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", + "ssi6", "ssi5", "ssi4", "ssi3", + "ssi2", "ssi1", "ssi0", + "scu-all", "scu-dvc1", "scu-dvc0", + "scu-ctu1-mix1", "scu-ctu0-mix0", + "scu-src6", "scu-src5", "scu-src4", + "scu-src3", "scu-src2", "scu-src1"; + }; mstp11_clks: mstp11_clks@e615099c { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h index f8279eca033e..9d02f5317c7c 100644 --- a/include/dt-bindings/clock/r8a7794-clock.h +++ b/include/dt-bindings/clock/r8a7794-clock.h @@ -108,6 +108,30 @@ #define R8A7794_CLK_I2C1 30 #define R8A7794_CLK_I2C0 31 +/* MSTP10 */ +#define R8A7794_CLK_SSI_ALL 5 +#define R8A7794_CLK_SSI9 6 +#define R8A7794_CLK_SSI8 7 +#define R8A7794_CLK_SSI7 8 +#define R8A7794_CLK_SSI6 9 +#define R8A7794_CLK_SSI5 10 +#define R8A7794_CLK_SSI4 11 +#define R8A7794_CLK_SSI3 12 +#define R8A7794_CLK_SSI2 13 +#define R8A7794_CLK_SSI1 14 +#define R8A7794_CLK_SSI0 15 +#define R8A7794_CLK_SCU_ALL 17 +#define R8A7794_CLK_SCU_DVC1 18 +#define R8A7794_CLK_SCU_DVC0 19 +#define R8A7794_CLK_SCU_CTU1_MIX1 20 +#define R8A7794_CLK_SCU_CTU0_MIX0 21 +#define R8A7794_CLK_SCU_SRC6 25 +#define R8A7794_CLK_SCU_SRC5 26 +#define R8A7794_CLK_SCU_SRC4 27 +#define R8A7794_CLK_SCU_SRC3 28 +#define R8A7794_CLK_SCU_SRC2 29 +#define R8A7794_CLK_SCU_SRC1 30 + /* MSTP11 */ #define R8A7794_CLK_SCIFA3 6 #define R8A7794_CLK_SCIFA4 7 -- cgit v1.2.3 From 298e4ee3d213a0764e8d4baa5336d4d1649a5bc5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:02:18 +0300 Subject: ARM: dts: r8a7794: add Audio-DMAC support Describe Audio-DMAC in the R8A7794 device tree. This patch is loosely based on the commit 8994fff67761 ("ARM: shmobile: r8a7791: Add Audio DMAC devices to DT"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index cba41c199fd8..668e1383dd09 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -296,6 +296,34 @@ dma-channels = <15>; }; + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7794", "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", + "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + power-domains = <&cpg_clocks>; + #dma-cells = <1>; + dma-channels = <13>; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7794", "renesas,rcar-gen2-scifa", "renesas,scifa"; -- cgit v1.2.3 From 320d6c5a08a4abd3990ee4744033ade6ed53d5fb Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:03:10 +0300 Subject: ARM: dts: r8a7794: add sound support Define the generic R8A7794 part of the sound device node. This sound device is a complex one and comprises the Audio Clock Generator (ADG), Sampling Rate Converter Unit (SCU), Serial Sound Interface [Unit] (SSI[U]), and Audio DMAC-Peripheral-Peripheral. It is up to the board file to enable the device. This patch is based on the R8A7791 sound work by Kuninori Morimoto. Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 181 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 181 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 668e1383dd09..6216a170a3df 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1416,4 +1416,185 @@ #iommu-cells = <1>; status = "disabled"; }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7794", + "renesas,rcar_sound-gen2"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, + <&mstp10_clks R8A7794_CLK_SSI9>, + <&mstp10_clks R8A7794_CLK_SSI8>, + <&mstp10_clks R8A7794_CLK_SSI7>, + <&mstp10_clks R8A7794_CLK_SSI6>, + <&mstp10_clks R8A7794_CLK_SSI5>, + <&mstp10_clks R8A7794_CLK_SSI4>, + <&mstp10_clks R8A7794_CLK_SSI3>, + <&mstp10_clks R8A7794_CLK_SSI2>, + <&mstp10_clks R8A7794_CLK_SSI1>, + <&mstp10_clks R8A7794_CLK_SSI0>, + <&mstp10_clks R8A7794_CLK_SCU_SRC6>, + <&mstp10_clks R8A7794_CLK_SCU_SRC5>, + <&mstp10_clks R8A7794_CLK_SCU_SRC4>, + <&mstp10_clks R8A7794_CLK_SCU_SRC3>, + <&mstp10_clks R8A7794_CLK_SCU_SRC2>, + <&mstp10_clks R8A7794_CLK_SCU_SRC1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, + <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, + <&mstp10_clks R8A7794_CLK_SCU_DVC0>, + <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + <&audio_clka>, <&audio_clkb>, <&audio_clkc>, + <&m2_clk>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", + "src.6", "src.5", "src.4", "src.3", "src.2", + "src.1", + "ctu.0", "ctu.1", + "mix.0", "mix.1", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&cpg_clocks>; + + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc@0 { + dmas = <&audma0 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc@1 { + dmas = <&audma0 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix@0 { }; + mix1: mix@1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu@0 { }; + ctu01: ctu@1 { }; + ctu02: ctu@2 { }; + ctu03: ctu@3 { }; + ctu10: ctu@4 { }; + ctu11: ctu@5 { }; + ctu12: ctu@6 { }; + ctu13: ctu@7 { }; + }; + + rcar_sound,src { + src@0 { + status = "disabled"; + }; + src1: src@1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma0 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src@2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma0 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src@3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma0 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src@4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma0 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src@5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma0 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src@6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma0 0xb4>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi@0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma0 0x02>, + <&audma0 0x15>, <&audma0 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi@1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma0 0x04>, + <&audma0 0x49>, <&audma0 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi@2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma0 0x06>, + <&audma0 0x63>, <&audma0 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi@3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma0 0x08>, + <&audma0 0x6f>, <&audma0 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi@4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma0 0x0a>, + <&audma0 0x71>, <&audma0 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi@5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma0 0x0c>, + <&audma0 0x73>, <&audma0 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi@6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma0 0x0e>, + <&audma0 0x75>, <&audma0 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi@7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma0 0x10>, + <&audma0 0x79>, <&audma0 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi@8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma0 0x12>, + <&audma0 0x7b>, <&audma0 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi@9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma0 0x14>, + <&audma0 0x7d>, <&audma0 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; }; -- cgit v1.2.3 From feb13b95c3fc461bb01ef32cdb818f99d6a859db Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 28 Jul 2016 00:05:58 +0300 Subject: ARM: dts: silk: add sound support Define the SILK board dependent part of the R8A7794 sound device node. Add device node for Asahi Kasei AK4643 stereo codec to the I2C1 bus. Add the "simple-audio-card" device node to interconnect the SoC sound device and the codec. This patch is based on the commit 493b4da7c10c ("ARM: dts: porter: add sound support"). Signed-off-by: Sergei Shtylyov Acked-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-silk.dts | 70 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index cf24f45fff22..cf880ac06f4b 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -10,6 +10,17 @@ * kind, whether express or implied. */ +/* + * SSI-AK4643 + * + * SW1: 2-1: AK4643 + * 2-3: ADV7511 + * + * This command is required before playback/capture: + * + * amixer set "LINEOUT Mixer DACL" on + */ + /dts-v1/; #include "r8a7794.dtsi" #include @@ -119,6 +130,29 @@ #clock-cells = <0>; clock-frequency = <74250000>; }; + + x9_clk: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <12288000>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&soundcodec>; + simple-audio-card,frame-master = <&soundcodec>; + + simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + soundcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + clocks = <&x9_clk>; + }; + }; }; &extal_clk { @@ -193,6 +227,16 @@ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out"; function = "du1"; }; + + ssi_pins: sound { + groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + function = "ssi"; + }; + + audio_clk_pins: audio_clk { + groups = "audio_clkc"; + function = "audio_clk"; + }; }; &scif2 { @@ -230,6 +274,12 @@ status = "okay"; clock-frequency = <400000>; + ak4643: codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + composite-in@20 { compatible = "adi,adv7180"; reg = <0x20>; @@ -392,3 +442,23 @@ }; }; }; + +&rcar_sound { + pinctrl-0 = <&ssi_pins &audio_clk_pins>; + pinctrl-names = "default"; + status = "okay"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0>; + capture = <&ssi1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; -- cgit v1.2.3 From d6f5fe84b5f99ab3fad6911b825098ebdeb4a921 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 6 Aug 2016 00:52:39 +0300 Subject: ARM: dts: r8a7792: fix misindented line Commit 2a0900655d5e (ARM: dts: r8a7792: add I2C support) had a wrongly indented line at the end of the "aliases" subnode -- fix it. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index e1f85a9904d0..eaa0c48c6184 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -31,7 +31,7 @@ vin3 = &vin3; vin4 = &vin4; vin5 = &vin5; -}; + }; cpus { #address-cells = <1>; -- cgit v1.2.3 From 3b0211af06298682d5faaa4c4cedf666fb1281c3 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 21:25:47 +0300 Subject: ARM: dts: r8a7792: add DU clocks Describe the DU0/1 clocks and their parent, ZX clock in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index eaa0c48c6184..7e0c57ff9892 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -660,6 +660,13 @@ clock-div = <2>; clock-mult = <1>; }; + zx_clk: zx { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7792_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + }; zs_clk: zs { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A7792_CLK_PLL1>; @@ -761,15 +768,17 @@ "renesas,cpg-mstp-clocks"; reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>; + <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; #clock-cells = <1>; clock-indices = < R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 + R8A7792_CLK_DU1 R8A7792_CLK_DU0 >; clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0"; + "scif2", "scif1", "scif0", + "du1", "du0"; }; mstp8_clks: mstp8_clks@e6150990 { compatible = "renesas,r8a7792-mstp-clocks", -- cgit v1.2.3 From 8bec0842ba2bb1b3bd954a1ef50f426b8f09c84f Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 5 Aug 2016 21:26:25 +0300 Subject: ARM: dts: r8a7792: add DU support Define the generic R8A7792 part of the DU device node. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 7e0c57ff9892..9763289db5ce 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -556,6 +556,34 @@ status = "disabled"; }; + du: display@feb00000 { + compatible = "renesas,du-r8a7792"; + reg = <0 0xfeb00000 0 0x40000>; + reg-names = "du"; + interrupts = , + ; + clocks = <&mstp7_clks R8A7792_CLK_DU0>, + <&mstp7_clks R8A7792_CLK_DU1>; + clock-names = "du.0", "du.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + can0: can@e6e80000 { compatible = "renesas,can-r8a7792", "renesas,rcar-gen2-can"; -- cgit v1.2.3 From d04eba90998fdfeb09b7c655fa894207fe175042 Mon Sep 17 00:00:00 2001 From: Fabien Lahoudere Date: Thu, 4 Aug 2016 12:22:37 +0200 Subject: ARM: dts: imx53: Add DMA configuration for UART In order to use sdma with UART, we need to add DMA configuration in device tree. Signed-off-by: Fabien Lahoudere Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index cd170376eaca..c1bc97c747cb 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -217,6 +217,8 @@ clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, <&clks IMX5_CLK_UART3_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -498,6 +500,8 @@ clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, <&clks IMX5_CLK_UART1_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -508,6 +512,8 @@ clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, <&clks IMX5_CLK_UART2_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -591,6 +597,8 @@ clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, <&clks IMX5_CLK_UART4_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; }; @@ -621,6 +629,8 @@ clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, <&clks IMX5_CLK_UART5_PER_GATE>; clock-names = "ipg", "per"; + dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; -- cgit v1.2.3 From 2a8e583c09c841744a6aa17d7247bc4fd5c6dfbf Mon Sep 17 00:00:00 2001 From: Fabien Lahoudere Date: Thu, 4 Aug 2016 15:47:32 +0200 Subject: ARM: dts: imx53: Add IPU nodes for csi We have the following messages that tell csi devices are not used: imx-ipuv3 18000000.ipu: no port@0 node in /soc/ipu@18000000, not using CSI0 imx-ipuv3 18000000.ipu: no port@1 node in /soc/ipu@18000000, not using CSI1 So we add them in the common device tree to make CSI ports available on imx53 boards. Signed-off-by: Fabien Lahoudere Acked-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index c1bc97c747cb..0777b41cdfe8 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -136,6 +136,14 @@ clock-names = "bus", "di0", "di1"; resets = <&src 2>; + ipu_csi0: port@0 { + reg = <0>; + }; + + ipu_csi1: port@1 { + reg = <1>; + }; + ipu_di0: port@2 { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 18a21e2c079a01805607bb474b3536a99620d162 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Wed, 6 Jul 2016 21:28:34 +0800 Subject: soc: rockchip: add reboot-mode header Rockchip platform use a SYSCON mapped register store the reboot mode magic value for bootloader to use when system reboot. Add the shared header describing the values firmware expects for different boot modes. Signed-off-by: Andy Yan Reviewed-by: Matthias Brugger Signed-off-by: Heiko Stuebner --- include/dt-bindings/soc/rockchip,boot-mode.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 include/dt-bindings/soc/rockchip,boot-mode.h diff --git a/include/dt-bindings/soc/rockchip,boot-mode.h b/include/dt-bindings/soc/rockchip,boot-mode.h new file mode 100644 index 000000000000..ae7c867e736a --- /dev/null +++ b/include/dt-bindings/soc/rockchip,boot-mode.h @@ -0,0 +1,15 @@ +#ifndef __ROCKCHIP_BOOT_MODE_H +#define __ROCKCHIP_BOOT_MODE_H + +/*high 24 bits is tag, low 8 bits is type*/ +#define REBOOT_FLAG 0x5242C300 +/* normal boot */ +#define BOOT_NORMAL (REBOOT_FLAG + 0) +/* enter bootloader rockusb mode */ +#define BOOT_BL_DOWNLOAD (REBOOT_FLAG + 1) +/* enter recovery */ +#define BOOT_RECOVERY (REBOOT_FLAG + 3) + /* enter fastboot mode */ +#define BOOT_FASTBOOT (REBOOT_FLAG + 9) + +#endif -- cgit v1.2.3 From b60ab70bbeced9a780ba297ffc555bc3a8ae6045 Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Wed, 6 Jul 2016 21:28:34 +0800 Subject: ARM: dts: rockchip: add syscon-reboot-mode DT node Rockchip platform use a SYSCON mapped register store the reboot mode magic value for bootloader to use when system reboot. So add syscon-reboot-mode driver DT node for rk3xxx/rk3036/rk3288 based platform Signed-off-by: Andy Yan Reviewed-by: Matthias Brugger Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3036.dtsi | 12 +++++++++++- arch/arm/boot/dts/rk3288.dtsi | 10 ++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 12 +++++++++++- 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi index 843d2be2e4e9..a935523a1eb8 100644 --- a/arch/arm/boot/dts/rk3036.dtsi +++ b/arch/arm/boot/dts/rk3036.dtsi @@ -43,6 +43,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -313,8 +314,17 @@ }; grf: syscon@20008000 { - compatible = "rockchip,rk3036-grf", "syscon"; + compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd"; reg = <0x20008000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x1d8>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; acodec: acodec-ana@20030000 { diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index e5c4a11f6bc6..48ca4e452564 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -45,6 +45,7 @@ #include #include #include +#include #include "skeleton.dtsi" / { @@ -791,6 +792,15 @@ clocks = <&cru ACLK_GPU>; }; }; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x94>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; sgrf: syscon@ff740000 { diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 99bbcc2c9b89..405d61258f10 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -43,6 +43,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -246,8 +247,17 @@ }; pmu: pmu@20004000 { - compatible = "rockchip,rk3066-pmu", "syscon"; + compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd"; reg = <0x20004000 0x100>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x40>; + mode-normal = ; + mode-recovery = ; + mode-bootloader = ; + mode-loader = ; + }; }; grf: grf@20008000 { -- cgit v1.2.3 From 974a3abcffaebc5ac9da03540f1bc5440f6ae7cf Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 25 Jul 2016 23:42:35 -0700 Subject: ARM: dts: imx7d: move ARM platform peripherals inside soc node Since we have a SoC level node we should make use of it and have all nodes which are within the SoC, inside that node. This also saves an extra interrupt-parent properties. While at it, also order the Coresight nodes according to register addresses. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 32 ++--- arch/arm/boot/dts/imx7s.dtsi | 301 +++++++++++++++++++++---------------------- 2 files changed, 167 insertions(+), 166 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 51c13cbdffb7..3d77d95bbc9d 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -52,23 +52,25 @@ }; }; - etm@3007d000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007d000 0x1000>; + soc { + etm@3007d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007d000 0x1000>; - /* - * System will hang if added nosmp in kernel command line - * without arm,primecell-periphid because amba bus try to - * read id and core1 power off at this time. - */ - arm,primecell-periphid = <0xbb956>; - cpu = <&cpu1>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + /* + * System will hang if added nosmp in kernel command line + * without arm,primecell-periphid because amba bus try to + * read id and core1 power off at this time. + */ + arm,primecell-periphid = <0xbb956>; + cpu = <&cpu1>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port { - etm1_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port1>; + port { + etm1_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port1>; + }; }; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 1e90bdbe3a6e..d89587a97725 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -95,16 +95,6 @@ }; }; - intc: interrupt-controller@31001000 { - compatible = "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x31001000 0x1000>, - <0x31002000 0x1000>, - <0x31004000 0x2000>, - <0x31006000 0x2000>; - }; - ckil: clock-cki { compatible = "fixed-clock"; #clock-cells = <0>; @@ -119,195 +109,204 @@ clock-output-names = "osc"; }; - timer { - compatible = "arm,armv7-timer"; - interrupts = , - , - , - ; + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; interrupt-parent = <&intc>; - }; + ranges; - etr@30086000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30086000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + funnel@30041000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30041000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; + + ca_funnel_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel input ports */ + port@0 { + reg = <0>; + ca_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* funnel output port */ + port@2 { + reg = <0>; + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; - port { - etr_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + /* the other input ports are not connect to anything */ }; }; - }; - tpiu@30087000 { - compatible = "arm,coresight-tpiu", "arm,primecell"; - reg = <0x30087000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + etm@3007c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x3007c000 0x1000>; + cpu = <&cpu0>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port { - tpiu_in_port: endpoint { - slave-mode; - remote-endpoint = <&replicator_out_port1>; + port { + etm0_out_port: endpoint { + remote-endpoint = <&ca_funnel_in_port0>; + }; }; }; - }; - replicator { - /* - * non-configurable replicators don't show up on the - * AMBA bus. As such no need to add "arm,primecell" - */ - compatible = "arm,coresight-replicator"; + funnel@30083000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0x30083000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - /* replicator output ports */ - port@0 { - reg = <0>; - replicator_out_port0: endpoint { - remote-endpoint = <&tpiu_in_port>; + /* funnel input ports */ + port@0 { + reg = <0>; + hugo_funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ca_funnel_out_port0>; + }; }; - }; - port@1 { - reg = <1>; - replicator_out_port1: endpoint { - remote-endpoint = <&etr_in_port>; + port@1 { + reg = <1>; + hugo_funnel_in_port1: endpoint { + slave-mode; /* M4 input */ + }; }; - }; - /* replicator input port */ - port@2 { - reg = <0>; - replicator_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etf_out_port>; + port@2 { + reg = <0>; + hugo_funnel_out_port0: endpoint { + remote-endpoint = <&etf_in_port>; + }; }; + + /* the other input ports are not connect to anything */ }; }; - }; - etf@30084000 { - compatible = "arm,coresight-tmc", "arm,primecell"; - reg = <0x30084000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + etf@30084000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30084000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - port@0 { - reg = <0>; - etf_in_port: endpoint { - slave-mode; - remote-endpoint = <&hugo_funnel_out_port0>; + port@0 { + reg = <0>; + etf_in_port: endpoint { + slave-mode; + remote-endpoint = <&hugo_funnel_out_port0>; + }; }; - }; - port@1 { - reg = <0>; - etf_out_port: endpoint { - remote-endpoint = <&replicator_in_port0>; + port@1 { + reg = <0>; + etf_out_port: endpoint { + remote-endpoint = <&replicator_in_port0>; + }; }; }; }; - }; - funnel@30083000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30083000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - ports { - #address-cells = <1>; - #size-cells = <0>; + etr@30086000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x30086000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - /* funnel input ports */ - port@0 { - reg = <0>; - hugo_funnel_in_port0: endpoint { + port { + etr_in_port: endpoint { slave-mode; - remote-endpoint = <&ca_funnel_out_port0>; + remote-endpoint = <&replicator_out_port1>; }; }; + }; - port@1 { - reg = <1>; - hugo_funnel_in_port1: endpoint { - slave-mode; /* M4 input */ - }; - }; + tpiu@30087000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0x30087000 0x1000>; + clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; + clock-names = "apb_pclk"; - port@2 { - reg = <0>; - hugo_funnel_out_port0: endpoint { - remote-endpoint = <&etf_in_port>; + port { + tpiu_in_port: endpoint { + slave-mode; + remote-endpoint = <&replicator_out_port1>; }; }; - - /* the other input ports are not connect to anything */ }; - }; - funnel@30041000 { - compatible = "arm,coresight-funnel", "arm,primecell"; - reg = <0x30041000 0x1000>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; + replicator { + /* + * non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell" + */ + compatible = "arm,coresight-replicator"; - ca_funnel_ports: ports { - #address-cells = <1>; - #size-cells = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - /* funnel input ports */ - port@0 { - reg = <0>; - ca_funnel_in_port0: endpoint { - slave-mode; - remote-endpoint = <&etm0_out_port>; + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; }; - }; - /* funnel output port */ - port@2 { - reg = <0>; - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&etr_in_port>; + }; }; - }; - /* the other input ports are not connect to anything */ + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&etf_out_port>; + }; + }; + }; }; - }; - etm@3007c000 { - compatible = "arm,coresight-etm3x", "arm,primecell"; - reg = <0x3007c000 0x1000>; - cpu = <&cpu0>; - clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; - clock-names = "apb_pclk"; - - port { - etm0_out_port: endpoint { - remote-endpoint = <&ca_funnel_in_port0>; - }; + intc: interrupt-controller@31001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x31001000 0x1000>, + <0x31002000 0x1000>, + <0x31004000 0x2000>, + <0x31006000 0x2000>; }; - }; - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; aips1: aips-bus@30000000 { compatible = "fsl,aips-bus", "simple-bus"; -- cgit v1.2.3 From b28c9bf65c4f216308fab42e34a1dfd34b3f1740 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Mon, 25 Jul 2016 23:42:36 -0700 Subject: ARM: dts: imx7d: fix GIC nodes interrupt and register specification The i.MX 7 as a GICv2, hence its CPU interface register map (the second register region) is 8kB long. Add the VGIC maintenance interrupt which allows to use the new VGIC driver. Signed-off-by: Stefan Agner Suggested-by: Marc Zyngier Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index d89587a97725..c63591c1f25e 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -292,10 +292,11 @@ intc: interrupt-controller@31001000 { compatible = "arm,cortex-a7-gic"; + interrupts = ; #interrupt-cells = <3>; interrupt-controller; reg = <0x31001000 0x1000>, - <0x31002000 0x1000>, + <0x31002000 0x2000>, <0x31004000 0x2000>, <0x31006000 0x2000>; }; -- cgit v1.2.3 From 0a88c95eed22db280b919f8a471aa576279e6320 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 9 Aug 2016 11:49:07 -0700 Subject: ARM: dts: imx: add Gateworks Ventana GW553x support The Gateworks Ventana GW553x is a single-board computer based on the NXP IMX6 SoC with the following features: * IMX6 DualLite Soc (supports IMX6S,IMX6DL,IMX6Q) * small form factor (35x70mm) * 512MB DDR3 DRAM (2x32bit) (options up to 2GB) * 256MB NAND flash (4GB option) * Gateworks System Controller: - hardware watchdog - hardware monitor - pushbutton controller - EEPROM storage - power control * JTAG programmable * 1x miniPCI socket (with PCIe, USB, SIM) * 1x microSD socket * 1x SIM socket * Inertial Module (LSM9DS1 9DOF: 3x acc, 3x rate, 3x mag) * analog CVBS video in * GPS (optional uBlox EVA-M8M) * Application headers: - 2x TTL UART (TX/RX) - 4x TTL GPIO (3x configurable as PWM) - 3x CVBS Analog video input (1x decoder with 3x selectable inputs) * Front panel connectors: - micro-HDMI audio/video out - 1x user programmable LED - 1x configurable user pushbutton - 1x USB OTG See http://www.gateworks.com for more info Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-gw553x.dts | 55 +++++ arch/arm/boot/dts/imx6q-gw553x.dts | 55 +++++ arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 433 ++++++++++++++++++++++++++++++++++ 4 files changed, 545 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-gw553x.dts create mode 100644 arch/arm/boot/dts/imx6q-gw553x.dts create mode 100644 arch/arm/boot/dts/imx6qdl-gw553x.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 98c4b9d6ba9c..dbd6a35b2a92 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -330,6 +330,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-gw54xx.dtb \ imx6dl-gw551x.dtb \ imx6dl-gw552x.dtb \ + imx6dl-gw553x.dtb \ imx6dl-hummingboard.dtb \ imx6dl-nit6xlite.dtb \ imx6dl-nitrogen6x.dtb \ @@ -368,6 +369,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-gw54xx.dtb \ imx6q-gw551x.dtb \ imx6q-gw552x.dtb \ + imx6q-gw553x.dtb \ imx6q-h100.dtb \ imx6q-hummingboard.dtb \ imx6q-icore-rqs.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-gw553x.dts b/arch/arm/boot/dts/imx6dl-gw553x.dts new file mode 100644 index 000000000000..59b8afc36e66 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW553X"; + compatible = "gw,imx6dl-gw553x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-gw553x.dts b/arch/arm/boot/dts/imx6q-gw553x.dts new file mode 100644 index 000000000000..e9c224cea752 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw553x.dts @@ -0,0 +1,55 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-gw553x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW553X"; + compatible = "gw,imx6q-gw553x", "gw,ventana", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi new file mode 100644 index 000000000000..86cec0527f73 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -0,0 +1,433 @@ +/* + * Copyright 2016 Gateworks Corporation + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + stdout-path = &uart2; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P0V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ + status = "disabled"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ + status = "disabled"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ + MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 + >; + }; +}; -- cgit v1.2.3 From 82515ff777fdbbe260f8f8de72a8d1fa143e6e53 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Tue, 9 Aug 2016 12:18:49 -0700 Subject: ARM: dts: imx: ventana: add RS485 txen gpio support Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 3 +++ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 3 +++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 3 +++ 3 files changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 208e3c291165..a7100f99123e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -315,6 +315,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -493,6 +495,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 35b9e808a4bb..8953eba0573d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -312,6 +312,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -482,6 +484,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 5f8f1ea6d2a2..6ac41c7ed32e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -414,6 +414,8 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -603,6 +605,7 @@ fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ >; }; -- cgit v1.2.3 From 1a7723b1ec42767396ce5001a63cf89e11201598 Mon Sep 17 00:00:00 2001 From: Lucile Quirion Date: Tue, 9 Aug 2016 11:15:43 -0400 Subject: of: documentation: add bindings documentation for TS-4900 This adds the documentation for the TS-4900 by Technologic Systems. Signed-off-by: Lucile Quirion Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/arm/technologic.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/technologic.txt b/Documentation/devicetree/bindings/arm/technologic.txt index 842298894cf0..33797acad846 100644 --- a/Documentation/devicetree/bindings/arm/technologic.txt +++ b/Documentation/devicetree/bindings/arm/technologic.txt @@ -4,3 +4,9 @@ Technologic Systems Platforms Device Tree Bindings TS-4800 board Required root node properties: - compatible = "technologic,imx51-ts4800", "fsl,imx51"; + +TS-4900 is a System-on-Module based on the Freescale i.MX6 System-on-Chip. +It can be mounted on a carrier board providing additional peripheral connectors. +Required root node properties: + - compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl" + - compatible = "technologic,imx6q-ts4900", "fsl,imx6q" -- cgit v1.2.3 From a2f11455316420c749151da3fcb2a89f3cfb51bb Mon Sep 17 00:00:00 2001 From: Lucile Quirion Date: Tue, 9 Aug 2016 11:15:44 -0400 Subject: ARM: dts: TS-4900: add basic device tree These device trees add support for TS-4900 by Technologic Systems. More details here: http://wiki.embeddedarm.com/wiki/TS-4900 Signed-off-by: Lucile Quirion Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/imx6dl-ts4900.dts | 49 ++++ arch/arm/boot/dts/imx6q-ts4900.dts | 53 ++++ arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 481 ++++++++++++++++++++++++++++++++++ 4 files changed, 585 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-ts4900.dts create mode 100644 arch/arm/boot/dts/imx6q-ts4900.dts create mode 100644 arch/arm/boot/dts/imx6qdl-ts4900.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index dbd6a35b2a92..606a8b632d27 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -340,6 +340,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-sabreauto.dtb \ imx6dl-sabrelite.dtb \ imx6dl-sabresd.dtb \ + imx6dl-ts4900.dtb \ imx6dl-tx6dl-comtft.dtb \ imx6dl-tx6s-8034.dtb \ imx6dl-tx6s-8035.dtb \ @@ -384,6 +385,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ imx6q-tbs2910.dtb \ + imx6q-ts4900.dtb \ imx6q-tx6q-1010.dtb \ imx6q-tx6q-1010-comtft.dtb \ imx6q-tx6q-1020.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts new file mode 100644 index 000000000000..85eddeb30e21 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-ts4900.dts @@ -0,0 +1,49 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts new file mode 100644 index 000000000000..9b81ebc8b0d4 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-ts4900.dts @@ -0,0 +1,53 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx6q.dtsi" +#include "imx6qdl-ts4900.dtsi" + +/ { + model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; + compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi new file mode 100644 index 000000000000..5c26b26e851a --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi @@ -0,0 +1,481 @@ +/* + * Copyright 2015 Technologic Systems + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +/ { + aliases { + ethernet0 = &fec; + }; + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds1>; + compatible = "gpio-leds"; + + green-led { + label = "green-led"; + gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + default-state = "on"; + }; + + red-led { + label = "red-led"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usb_otg_vbus: regulator-usb-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + + n25q064: flash@0 { + compatible = "micron,n25q064", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&ecspi2 { + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + status = "okay"; + + isl12022: rtc@6f { + compatible = "isil,isl12022"; + reg = <0x6f>; + }; + + gpio8: gpio@28 { + compatible = "technologic,ts4900-gpio"; + reg = <0x28>; + #gpio-cells = <2>; + gpio-controller; + ngpio = <32>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x100b1 /* Onboard flash CS1# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x100b1 /* Offboard CS0# */ + MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x100b1 /* FPGA CS1# */ + MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b1 /* FPGA_RESET# */ + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b1 /* FPGA_DONE */ + MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x10 /* FPGA 24MHZ */ + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b1 /* FPGA_IRQ */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b1 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b1 /* ETH_PHY_RESET */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b1 /* OFF_BD_RESET# */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 /* EN_USB_5V# */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b1 /* EN_LCD_3.3V */ + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* Audio CLK */ + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 /* DIO_1 */ + MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b1 /* DIO_3 */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1b0b1 /* DIO_4 */ + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 /* DIO_5 */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b1 /* DIO_7 */ + MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b1 /* DIO_8 */ + MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b1 /* DIO_9 */ + MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b1 /* DIO_0 */ + MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b1 /* DIO_6 */ + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b1 /* CPU_DIO_A */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b1 /* DIO_2 */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b1 /* CPU_DIO_B */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1b0b1 /* BUS_ALE# */ + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1b0b1 /* DIO_15 */ + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1b0b1 /* BUS_DIR */ + MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x1b0b1 /* BUS_CS# */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* DIO_14 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b1 /* DIO_16 */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x1b0b1 /* DIO_12 */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b1 /* DIO_18 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b1 /* DIO_19 */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b1 /* DIO_20 */ + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b1 /* BUS_BHE# */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b1 /* DIO_13 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1b0b1 /* EIM_WAIT# */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b1 /* DIO_10 */ + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x1b0b1 /* MUX_AD_00 */ + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x1b0b1 /* MUX_AD_01 */ + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 /* MUX_AD_02 */ + MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1b0b1 /* MUX_AD_03 */ + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1b0b1 /* MUX_AD_04 */ + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 /* MUX_AD_05 */ + MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b0b1 /* MUX_AD_06 */ + MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b0b1 /* MUX_AD_07 */ + MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1b0b1 /* MUX_AD_08 */ + MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1b0b1 /* MUX_AD_09 */ + MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x1b0b1 /* MUX_AD_10 */ + MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x1b0b1 /* MUX_AD_11 */ + MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x1b0b1 /* MUX_AD_12 */ + MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x1b0b1 /* MUX_AD_13 */ + MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x1b0b1 /* MUX_AD_14 */ + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b1 /* MUX_AD_15 */ + MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 /* LCD_CLK */ + MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x1b0b1 /* DE */ + MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b1 /* Hsync */ + MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x1b0b1 /* Vsync */ + MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b1 + MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x1b0b1 + MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x1b0b1 + MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x1b0b1 + MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1 + MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b1 + MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x1b0b1 + MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x1b0b1 + MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x1b0b1 + MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x1b0b1 + MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b1 + MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x1b0b1 + MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b1 + MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1b0b1 + MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 + MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 + MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 + MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b0b1 + MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1b0b1 + MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1b0b1 + MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1b0b1 + MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1b0b1 + MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x4001b8b1 + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + + pinctrl_leds1: leds1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 /* RED_LED# */ + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x1b0b1 /* GREEN_LED# */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x17059 /* WIFI IRQ */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b1 /* EN_SD_POWER# */ + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + >; + }; +}; + +&pcie { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +/* SD */ +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + fsl,wp-controller; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + vmmc-supply = <®_3p3v>; + bus-width = <4>; + non-removable; + status = "okay"; +}; -- cgit v1.2.3 From 171befefb274cb3af2fef7e135f325e1063fff56 Mon Sep 17 00:00:00 2001 From: Breno Lima Date: Tue, 9 Aug 2016 15:40:45 -0300 Subject: ARM: dts: imx7s-warp: Add MPL3115 sensor support Add support for MPL3115 NXP pressure sensor. Tested by reading temperature and pressure: $ cat /sys/bus/iio/devices/iio:device0/in_temp_raw $ cat /sys/bus/iio/devices/iio:device0/in_pressure_raw Signed-off-by: Breno Lima Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index e318c989c18f..ae23781034fd 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -155,6 +155,18 @@ }; }; +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + mpl3115@60 { + compatible = "fsl,mpl3115"; + reg = <0x60>; + }; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -189,6 +201,13 @@ >; }; + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- cgit v1.2.3 From f515f81424cbd75734197ac4723c4c379ab60add Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:46:55 -0400 Subject: ARM: dts: omap3/am4372: add missing unit name to ocp node This patch fixes the following DTC warnings for many boards: "Node /ocp has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517.dtsi | 2 +- arch/arm/boot/dts/am4372.dtsi | 2 +- arch/arm/boot/dts/omap3.dtsi | 2 +- arch/arm/boot/dts/omap34xx.dtsi | 2 +- arch/arm/boot/dts/omap36xx.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index 5e3f5e86ffcf..0db19d39d24c 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -15,7 +15,7 @@ serial3 = &uart4; }; - ocp { + ocp@68000000 { am35x_otg_hs: am35x_otg_hs@5c040000 { compatible = "ti,omap3-musb"; ti,hwmods = "am35x_otg_hs"; diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 0fadae5396e1..d8689878d67b 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -132,7 +132,7 @@ cache-level = <2>; }; - ocp { + ocp@44000000 { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 4c3c471d2a83..16cf2fdfec75 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -78,7 +78,7 @@ * the moment, just use a fake OCP bus entry to represent the whole bus * hierarchy. */ - ocp { + ocp@68000000 { compatible = "ti,omap3-l3-smx", "simple-bus"; reg = <0x68000000 0x10000>; interrupts = <9 10>; diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi index e44656258225..e41c52d3b113 100644 --- a/arch/arm/boot/dts/omap34xx.dtsi +++ b/arch/arm/boot/dts/omap34xx.dtsi @@ -28,7 +28,7 @@ }; }; - ocp { + ocp@68000000 { omap3_pmx_core2: pinmux@480025d8 { compatible = "ti,omap3-padconf", "pinctrl-single"; reg = <0x480025d8 0x24>; diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi index 8b7979153008..718fa88407cd 100644 --- a/arch/arm/boot/dts/omap36xx.dtsi +++ b/arch/arm/boot/dts/omap36xx.dtsi @@ -30,7 +30,7 @@ }; }; - ocp { + ocp@68000000 { uart4: serial@49042000 { compatible = "ti,omap3-uart"; reg = <0x49042000 0x400>; -- cgit v1.2.3 From 0b965a13ad81fa895e534d1f50b355ff8b0b3ed3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:46:56 -0400 Subject: ARM: dts: omap3: overo: add missing unit name for lcd35 display Commit b8d368caa8dc ("ARM: dts: omap3: overo: remove unneded unit names in display nodes") removed the unit names for all Overo display nodes that didn't have a reg property. But the display in arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi does have a reg property so the correct fix was to make the unit name match the value of the reg property, instead of removing it. This patch fixes the following DTC warning for boards using this dtsi: "ocp/spi@48098000/display has a reg or ranges property, but no unit name" Fixes: b8d368caa8dc ("ARM: dts: omap3: overo: remove unneded unit names in display nodes") Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi index ca86da68220c..854117dc0b77 100644 --- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi @@ -119,7 +119,7 @@ pinctrl-names = "default"; pinctrl-0 = <&mcspi1_pins>; - lcd0: display { + lcd0: display@1 { compatible = "lgphilips,lb035q02"; label = "lcd35"; -- cgit v1.2.3 From 18ad99d4c2d0c02f7811ecde37a79fd993258621 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:46:57 -0400 Subject: ARM: dts: am335x/am437x: remove unneeded unit name for gpio-matrix-keypad This patch fixes the following DTC warnings for many boards: "Node /matrix_keypad@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am437x-gp-evm.dts | 2 +- arch/arm/boot/dts/am437x-sk-evm.dts | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 5d28712ad253..d5e6da5a782a 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -53,7 +53,7 @@ enable-active-high; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 14677d599595..128dbefa77e7 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -58,7 +58,7 @@ default-brightness-level = <8>; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 5687d6b4da60..9d71246d31ad 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -64,7 +64,7 @@ }; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index ad32e55532f8..3ce23f2920e6 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -67,7 +67,7 @@ }; }; - matrix_keypad: matrix_keypad@0 { + matrix_keypad: matrix_keypad0 { compatible = "gpio-matrix-keypad"; debounce-delay-ms = <5>; col-scan-delay-us = <2>; -- cgit v1.2.3 From 4c049a5b7c89012872184c1fdaefe04ea3dc7dc0 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:46:58 -0400 Subject: ARM: dts: am335x/am437x: remove unneeded unit name for fixed regulators This patch fixes the following DTC warnings for many boards: "Node /fixedregulator@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 4 ++-- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-cm-t335.dts | 4 ++-- arch/arm/boot/dts/am335x-evm.dts | 6 +++--- arch/arm/boot/dts/am335x-evmsk.dts | 8 ++++---- arch/arm/boot/dts/am335x-icev2.dts | 4 ++-- arch/arm/boot/dts/am335x-igep0033.dtsi | 4 ++-- arch/arm/boot/dts/am335x-lxm.dts | 4 ++-- arch/arm/boot/dts/am335x-pepper.dts | 6 +++--- arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +- arch/arm/boot/dts/am335x-shc.dts | 2 +- arch/arm/boot/dts/am335x-sl50.dts | 2 +- arch/arm/boot/dts/am335x-wega.dtsi | 2 +- arch/arm/boot/dts/am43x-epos-evm.dts | 2 +- 14 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index b689172632ef..df0dd2a54b00 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -29,7 +29,7 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -37,7 +37,7 @@ regulator-boot-on; }; - wl12xx_vmmc: fixedregulator@2 { + wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index e247c15e5176..d4890149dac4 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -57,7 +57,7 @@ }; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 817b1dec0683..1dbc70de1070 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -34,7 +34,7 @@ }; /* regulator for mmc */ - vmmc_fixed: fixedregulator@0 { + vmmc_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmc_fixed"; regulator-min-microvolt = <3300000>; @@ -42,7 +42,7 @@ }; /* Regulator for WiFi */ - vwlan_fixed: fixedregulator@2 { + vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "vwlan_fixed"; gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>; /* gpio0_20 */ diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index d5e6da5a782a..63124f898186 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -25,7 +25,7 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -33,13 +33,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wlan_en_reg: fixedregulator@2 { + wlan_en_reg: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "wlan-en-regulator"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 09308d66645b..c96c42cb84f6 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -32,7 +32,7 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -40,13 +40,13 @@ regulator-boot-on; }; - lis3_reg: fixedregulator@1 { + lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; - wl12xx_vmmc: fixedregulator@2 { + wl12xx_vmmc: fixedregulator2 { pinctrl-names = "default"; pinctrl-0 = <&wl12xx_gpio>; compatible = "regulator-fixed"; @@ -58,7 +58,7 @@ enable-active-high; }; - vtt_fixed: fixedregulator@3 { + vtt_fixed: fixedregulator3 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 7d8b8fefdf08..859e801f7627 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -24,7 +24,7 @@ reg = <0x80000000 0x10000000>; /* 256 MB */ }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -32,7 +32,7 @@ regulator-boot-on; }; - vtt_fixed: fixedregulator@1 { + vtt_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vtt"; regulator-min-microvolt = <1500000>; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index e7d9ca1305fa..856ee31c7cc8 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -38,7 +38,7 @@ }; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -46,7 +46,7 @@ regulator-boot-on; }; - vmmc: fixedregulator@0 { + vmmc: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index d97b0efa43f3..6594ce7449f3 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -25,7 +25,7 @@ }; /* Power supply provides a fixed 5V @2A */ - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; @@ -34,7 +34,7 @@ }; /* Power supply provides a fixed 3.3V @3A */ - vmmcsd_fixed: fixedregulator@1 { + vmmcsd_fixed: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 8867aaaec54d..5fe52a3a7f47 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -41,15 +41,15 @@ compatible = "ti,da830-evm-audio"; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; }; - v3v3c_reg: fixedregulator@1 { + v3v3c_reg: fixedregulator1 { compatible = "regulator-fixed"; }; - vdd5_reg: fixedregulator@2 { + vdd5_reg: fixedregulator2 { compatible = "regulator-fixed"; }; }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 1263c9d4cba3..29c2ea7950f6 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -33,7 +33,7 @@ regulators { compatible = "simple-bus"; - vcc5v: fixedregulator@0 { + vcc5v: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vcc5v"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 837d5b80ea1d..41b1b1206c31 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -107,7 +107,7 @@ reg = <0x80000000 0x20000000>; /* 512 MB */ }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index a6efbe6eda3b..560ebfcddcc5 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -103,7 +103,7 @@ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index 282f6d4b27bc..d5fdf6244af8 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -14,7 +14,7 @@ regulators { compatible = "simple-bus"; - vcc3v3: fixedregulator@1 { + vcc3v3: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index 3ce23f2920e6..a44580248571 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -32,7 +32,7 @@ enable-active-high; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; -- cgit v1.2.3 From 0b0d912ab516782beeb3449149d2a126882d550a Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:46:59 -0400 Subject: ARM: dts: da850/dm81x: remove unneeded unit name for fixed regulators This patch fixes the following DTC warnings for many boards: "Node /fixedregulator@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/da850-evm.dts | 2 +- arch/arm/boot/dts/dm8148-evm.dts | 2 +- arch/arm/boot/dts/dm8148-t410.dts | 2 +- arch/arm/boot/dts/dm8168-evm.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1a15db8e376b..5fd4c37680fd 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -136,7 +136,7 @@ pinctrl-names = "default"; pinctrl-0 = <&nand_cs3_pins>; }; - vbat: fixedregulator@0 { + vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 4128fa91823c..376b85381e8c 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -18,7 +18,7 @@ }; /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts index 3f184863e0c5..b1ce1398b3ed 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/dm8148-t410.dts @@ -27,7 +27,7 @@ regulator-always-on; }; - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index f50348bdd857..1380922827be 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -19,7 +19,7 @@ }; /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; -- cgit v1.2.3 From 909b0ebde95d24af3cdecbe22863830413f3fe81 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:47:00 -0400 Subject: ARM: dts: omap3/dra62x: remove unneeded unit name for fixed regulators This patch fixes the following DTC warnings for many boards: "Node /fixedregulator@0 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra62x-j5eco-evm.dts | 2 +- arch/arm/boot/dts/omap3-n950-n9.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index f820573f4a4a..68e31d122762 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -18,7 +18,7 @@ }; /* MIC94060YC6 controlled by SD1_POW pin */ - vmmcsd_fixed: fixedregulator@0 { + vmmcsd_fixed: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 927b17fc4ed8..284849008fc5 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -29,7 +29,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - vemmc: fixedregulator@0 { + vemmc: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "VEMMC"; regulator-min-microvolt = <2900000>; @@ -39,7 +39,7 @@ enable-active-high; }; - vwlan_fixed: fixedregulator@2 { + vwlan_fixed: fixedregulator2 { compatible = "regulator-fixed"; regulator-name = "VWLAN"; gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; /* gpio 35 */ -- cgit v1.2.3 From 57a78a8a6f6e07253c6ff276847923e523a90a59 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:47:01 -0400 Subject: ARM: dts: am335x/am437x: remove unneeded unit name for gpio-keys nodes This patch fixes the following DTC warnings for many boards: "Node /gpio_keys/button0@10 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 6 +++--- arch/arm/boot/dts/am335x-evmsk.dts | 10 +++++----- arch/arm/boot/dts/am335x-pepper.dts | 6 +++--- arch/arm/boot/dts/am437x-idk-evm.dts | 2 +- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 63124f898186..944914e5b15a 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -73,20 +73,20 @@ 0x0201006c>; /* DOWN */ }; - gpio_keys: volume_keys@0 { + gpio_keys: volume_keys0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; - switch@9 { + switch9 { label = "volume-up"; linux,code = <115>; gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; wakeup-source; }; - switch@10 { + switch10 { label = "volume-down"; linux,code = <114>; gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index c96c42cb84f6..80e9978402e1 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -102,31 +102,31 @@ }; }; - gpio_buttons: gpio_buttons@0 { + gpio_buttons: gpio_buttons0 { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - switch@1 { + switch1 { label = "button0"; linux,code = <0x100>; gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; }; - switch@2 { + switch2 { label = "button1"; linux,code = <0x101>; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; - switch@3 { + switch3 { label = "button2"; linux,code = <0x102>; gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>; wakeup-source; }; - switch@4 { + switch4 { label = "button3"; linux,code = <0x103>; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index 5fe52a3a7f47..dbf079065659 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -616,21 +616,21 @@ #address-cells = <1>; #size-cells = <0>; - button@0 { + button0 { label = "home"; linux,code = ; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; wakeup-source; }; - button@1 { + button1 { label = "menu"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; wakeup-source; }; - buttons@2 { + buttons2 { label = "power"; linux,code = ; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts index 12a69518383e..25ce611c6568 100644 --- a/arch/arm/boot/dts/am437x-idk-evm.dts +++ b/arch/arm/boot/dts/am437x-idk-evm.dts @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch0 { label = "power-button"; linux,code = ; gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; -- cgit v1.2.3 From 45ed37f7b92d20541c0c651884815a9e504246fa Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:47:02 -0400 Subject: ARM: dts: omap3/4: remove unneeded unit name for gpio-keys nodes This patch fixes the following DTC warnings for many boards: "Node /gpio_keys/button0@10 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-overo-alto35-common.dtsi | 2 +- arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi | 4 ++-- arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi | 4 ++-- arch/arm/boot/dts/omap3-overo-palo35-common.dtsi | 4 ++-- arch/arm/boot/dts/omap3-overo-palo43-common.dtsi | 4 ++-- arch/arm/boot/dts/omap4-duovero-parlor.dts | 2 +- 6 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi index 3b3a75997f81..99a7eee6e61f 100644 --- a/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-alto35-common.dtsi @@ -44,7 +44,7 @@ #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&button_pins>; - button0@10 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; /* gpio_10 */ diff --git a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi index 4f4c6efbd518..56dbd113430e 100644 --- a/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-chestnut43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi index 250cc7fe5d5e..286f5baddf07 100644 --- a/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-gallop43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi index 8df7ec35d17d..a8020fb42464 100644 --- a/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-palo35-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi index 0ea2c451c809..11965737e2c9 100644 --- a/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi +++ b/arch/arm/boot/dts/omap3-overo-palo43-common.dtsi @@ -37,13 +37,13 @@ pinctrl-0 = <&button_pins>; #address-cells = <1>; #size-cells = <0>; - button0@23 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; /* gpio_23 */ wakeup-source; }; - button1@14 { + button1 { label = "button1"; linux,code = ; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; /* gpio_14 */ diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 6b39808b8313..1b825128a7b9 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -32,7 +32,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - button0@121 { + button0 { label = "button0"; linux,code = ; gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */ -- cgit v1.2.3 From c731abd99121cae0b9a1735c062c96c56e2b72fc Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:47:03 -0400 Subject: ARM: dts: am335x/437x/57xx: remove unneeded unit name for gpio-leds nodes This patch fixes the following DTC warnings for many boards: "Node /leds/led@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-base0033.dts | 4 ++-- arch/arm/boot/dts/am335x-bone-common.dtsi | 8 ++++---- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 8 ++++---- arch/arm/boot/dts/am335x-icev2.dts | 32 +++++++++++++++---------------- arch/arm/boot/dts/am335x-igep0033.dtsi | 2 +- arch/arm/boot/dts/am335x-nano.dts | 2 +- arch/arm/boot/dts/am335x-pepper.dts | 4 ++-- arch/arm/boot/dts/am335x-shc.dts | 12 ++++++------ arch/arm/boot/dts/am335x-sl50.dts | 8 ++++---- arch/arm/boot/dts/am437x-sk-evm.dts | 8 ++++---- arch/arm/boot/dts/am57xx-beagle-x15.dts | 8 ++++---- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 2 +- 13 files changed, 50 insertions(+), 50 deletions(-) diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts index 58a05f7d0b7c..c2bee452dab8 100644 --- a/arch/arm/boot/dts/am335x-base0033.dts +++ b/arch/arm/boot/dts/am335x-base0033.dts @@ -29,13 +29,13 @@ compatible = "gpio-leds"; - led@0 { + led0 { label = "base:red:user"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */ default-state = "off"; }; - led@1 { + led1 { label = "base:green:user"; gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */ default-state = "off"; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index d4890149dac4..8d21aca69f37 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -28,28 +28,28 @@ compatible = "gpio-leds"; - led@2 { + led2 { label = "beaglebone:green:heartbeat"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@3 { + led3 { label = "beaglebone:green:mmc0"; gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@4 { + led4 { label = "beaglebone:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@5 { + led5 { label = "beaglebone:green:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc1"; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 1dbc70de1070..4c0d6d7a37c2 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -26,7 +26,7 @@ compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&gpio_led_pins>; - led@0 { + led0 { label = "cm_t335:green"; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* gpio2_0 */ linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 80e9978402e1..c9b11107803d 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -75,26 +75,26 @@ compatible = "gpio-leds"; - led@1 { + led1 { label = "evmsk:green:usr0"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "evmsk:green:usr1"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "evmsk:green:mmc0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@4 { + led4 { label = "evmsk:green:heartbeat"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 859e801f7627..bc0190e4f10f 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -43,52 +43,52 @@ enable-active-high; }; - leds@0 { + leds0 { compatible = "gpio-leds"; - led@0 { + led0 { label = "out0"; gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@1 { + led1 { label = "out1"; gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "out2"; gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "out3"; gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@4 { + led4 { label = "out4"; gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "out5"; gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@6 { + led6 { label = "out6"; gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@7 { + led7 { label = "out7"; gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; default-state = "off"; @@ -96,44 +96,44 @@ }; /* Tricolor status LEDs */ - leds@1 { + leds1 { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&user_leds>; - led@0 { + led0 { label = "status0:red:cpu0"; gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "cpu0"; }; - led@1 { + led1 { label = "status0:green:usr"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "status0:yellow:usr"; gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@3 { + led3 { label = "status1:red:mmc0"; gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; - led@4 { + led4 { label = "status1:green:usr"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "status1:yellow:usr"; gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index 856ee31c7cc8..df95818b4f67 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -31,7 +31,7 @@ compatible = "gpio-leds"; - led@0 { + led0 { label = "com:green:user"; gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index f313999c503e..71e082ca3f34 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -27,7 +27,7 @@ leds { compatible = "gpio-leds"; - led@0 { + led0 { label = "nanobone:green:usr1"; gpios = <&gpio1 5 0>; default-state = "off"; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index dbf079065659..ddfdf3ca3d66 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -595,14 +595,14 @@ pinctrl-names = "default"; pinctrl-0 = <&user_leds_pins>; - led@0 { + led0 { label = "pepper:user0:blue"; gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; default-state = "off"; }; - led@1 { + led1 { label = "pepper:user1:red"; gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; linux,default-trigger = "none"; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index 41b1b1206c31..f9a15afb66c7 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -64,38 +64,38 @@ compatible = "gpio-leds"; - led@1 { + led1 { label = "shc:power:red"; gpios = <&gpio0 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@2 { + led2 { label = "shc:power:bl"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; linux,default-trigger = "timer"; default-state = "on"; }; - led@3 { + led3 { label = "shc:lan:red"; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@4 { + led4 { label = "shc:lan:bl"; gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@5 { + led5 { label = "shc:cloud:red"; gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - led@6 { + led6 { label = "shc:cloud:bl"; gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index 560ebfcddcc5..f802adb23ff9 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -28,25 +28,25 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - led@0 { + led0 { label = "sl50:green:usr0"; gpios = <&gpio1 21 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led1 { label = "sl50:red:usr1"; gpios = <&gpio1 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led2 { label = "sl50:green:usr2"; gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led3 { label = "sl50:red:usr3"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 9d71246d31ad..23e7c9ecb76f 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -93,28 +93,28 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins>; - led@0 { + led0 { label = "am437x-sk:red:heartbeat"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@1 { + led1 { label = "am437x-sk:green:mmc1"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */ linux,default-trigger = "mmc0"; default-state = "off"; }; - led@2 { + led2 { label = "am437x-sk:blue:cpu0"; gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */ linux,default-trigger = "cpu0"; default-state = "off"; }; - led@3 { + led3 { label = "am437x-sk:blue:usr3"; gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */ default-state = "off"; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index c4d04c5293b9..8b115e1b48a3 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -62,28 +62,28 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - led@0 { + led0 { label = "beagle-x15:usr0"; gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@1 { + led1 { label = "beagle-x15:usr1"; gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "cpu0"; default-state = "off"; }; - led@2 { + led2 { label = "beagle-x15:usr2"; gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; default-state = "off"; }; - led@3 { + led3 { label = "beagle-x15:usr3"; gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; linux,default-trigger = "disk-activity"; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 378b142ef88c..832d766cd31e 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -29,7 +29,7 @@ pinctrl-names = "default"; pinctrl-0 = <&leds_pins_default>; - led@0 { + led0 { label = "cl-som-am57x:green"; gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; -- cgit v1.2.3 From 08ef98069718cfa8dc9acab46fdc52810511636d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Mon, 1 Aug 2016 12:47:04 -0400 Subject: ARM: dts: omap3/4/5/dra7: remove unneeded unit name for gpio-leds nodes This patch fixes the following DTC warnings for many boards: "Node /leds/led@1 has a unit name, but no reg property" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 8 ++++---- arch/arm/boot/dts/omap3-pandora-common.dtsi | 8 ++++---- arch/arm/boot/dts/omap5-board-common.dtsi | 2 +- arch/arm/boot/dts/omap5-cm-t54.dts | 2 +- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index bafcfac067ec..d47c8739bdaa 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -105,25 +105,25 @@ leds { compatible = "gpio-leds"; - led@0 { + led0 { label = "dra7:usr1"; gpios = <&pcf_lcd 4 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@1 { + led1 { label = "dra7:usr2"; gpios = <&pcf_lcd 5 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@2 { + led2 { label = "dra7:usr3"; gpios = <&pcf_lcd 6 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led@3 { + led3 { label = "dra7:usr4"; gpios = <&pcf_lcd 7 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index dbc4dc721cc2..af30d4d99307 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -45,28 +45,28 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pins>; - led@1 { + led1 { label = "pandora::sd1"; gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* GPIO_128 */ linux,default-trigger = "mmc0"; default-state = "off"; }; - led@2 { + led2 { label = "pandora::sd2"; gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* GPIO_129 */ linux,default-trigger = "mmc1"; default-state = "off"; }; - led@3 { + led3 { label = "pandora::bluetooth"; gpios = <&gpio5 30 GPIO_ACTIVE_HIGH>; /* GPIO_158 */ linux,default-trigger = "heartbeat"; default-state = "off"; }; - led@4 { + led4 { label = "pandora::wifi"; gpios = <&gpio5 31 GPIO_ACTIVE_HIGH>; /* GPIO_159 */ linux,default-trigger = "mmc2"; diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index 5196113202a2..d1f5ce3d3651 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -79,7 +79,7 @@ leds { compatible = "gpio-leds"; - led@1 { + led1 { label = "omap5:blue:usr1"; gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index a9765605d53b..fe724da3ec0d 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -72,7 +72,7 @@ leds { compatible = "gpio-leds"; - led@1 { + led1 { label = "Heartbeat"; gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */ linux,default-trigger = "heartbeat"; -- cgit v1.2.3 From a70cb07bb397fce6675d7ab055fb447519fc7c76 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 15 Aug 2016 11:31:31 -0600 Subject: ARM: tegra: Fix Tegra114 USB compatible values DT compatible values should always include an entry for the specific chip in addition to any earlier generations that the HW is backwards- compatible with. This doesn't affect the kernel at all given current driver code, but U-Boot needs to distinguish between Tegra114 and Tegra30 for this HW, and I'd like to synchronize the DT content. Signed-off-by: Stephen Warren Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index cb9393a53422..8932ea3afd5f 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -672,7 +672,7 @@ }; usb@7d000000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d000000 0x4000>; interrupts = ; phy_type = "utmi"; @@ -684,7 +684,7 @@ }; phy1: usb-phy@7d000000 { - compatible = "nvidia,tegra30-usb-phy"; + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d000000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>, @@ -708,7 +708,7 @@ }; usb@7d008000 { - compatible = "nvidia,tegra30-ehci", "usb-ehci"; + compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d008000 0x4000>; interrupts = ; phy_type = "utmi"; @@ -720,7 +720,7 @@ }; phy3: usb-phy@7d008000 { - compatible = "nvidia,tegra30-usb-phy"; + compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; reg = <0x7d008000 0x4000 0x7d000000 0x4000>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>, -- cgit v1.2.3 From 7e9d474954f4c8c27534633252500e0c477581bd Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Tue, 2 Aug 2016 11:34:27 +0100 Subject: ARM: tegra: Correct polarity for Tegra114 PMIC interrupt The ARM GIC only supports interrupts with either level-high or rising-edge types for SPIs. The interrupt type for the Palmas PMIC used for Tegra114 boards is specified as level-low which is invalid for the GIC. This has gone undetected because until recently, failures to set the interrupt type when the interrupts are mapped via firmware (such as device-tree) have not been reported. Since commits 4b357daed698 ("genirq: Look-up trigger type if not specified by caller") and 1e2a7d78499e ("irqdomain: Don't set type when mapping an IRQ"), failure to set the interrupt type will cause the requesting of the interrupt to fail and exposing incorrectly configured interrupts. Please note that although the interrupt type was never being set for the Palmas PMIC, it was still working fine, because the default type setting for the interrupt, 'level-high', happen to match the correct type for the interrupt. Finally, it should be noted that the Palmas interrupt from the PMIC is actually 'level-low', however, this interrupt signal is inverted by the Tegra PMC and so the GIC actually sees a 'level-high' interrupt which is what should be specified in the device-tree interrupt specifier. Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra114-dalmore.dts | 2 +- arch/arm/boot/dts/tegra114-roth.dts | 2 +- arch/arm/boot/dts/tegra114-tn7.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 1dfc492cc004..1444fbd543e7 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -897,7 +897,7 @@ palmas: tps65913@58 { compatible = "ti,palmas"; reg = <0x58>; - interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; #interrupt-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index 70cf40996c3f..966a7fc044af 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -802,7 +802,7 @@ palmas: pmic@58 { compatible = "ti,palmas"; reg = <0x58>; - interrupts = ; + interrupts = ; #interrupt-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 17dd14545862..a161fa1dfb61 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -63,7 +63,7 @@ palmas: pmic@58 { compatible = "ti,palmas"; reg = <0x58>; - interrupts = ; + interrupts = ; #interrupt-cells = <2>; interrupt-controller; -- cgit v1.2.3 From bb249cdc3e55b099c05cd350772368ae85592706 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 16 Aug 2016 00:52:58 +0300 Subject: ARM: dts: r8a7794: add VSP1 support Describe two instances (VSPS and VSPD0) of the VSP1 in the R8A7794 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 6216a170a3df..611ec6df5cf6 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -894,6 +894,22 @@ }; }; + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; + power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7794"; reg = <0 0xfeb00000 0 0x40000>; -- cgit v1.2.3 From 2b41091b896bb99ec1da1ed30113603fc91b84d6 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 9 Aug 2016 14:19:03 +0200 Subject: ARM: dts: alt: add SDHI0 and 1 support Define the Alt board dependent part of the SDHI0 and 1 device nodes along with the necessary voltage regulators. Based on work by the original patch by Vladimir Barinov and Sergei Shtylyov for the Silk board. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 81 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index 1ad37d431a2a..fe7c128cc965 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -10,6 +10,7 @@ /dts-v1/; #include "r8a7794.dtsi" +#include / { model = "Alt"; @@ -29,6 +30,54 @@ reg = <0 0x40000000 0 0x40000000>; }; + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + lbsc { #address-cells = <1>; #size-cells = <1>; @@ -140,6 +189,16 @@ groups = "vin0_data8", "vin0_clk"; function = "vin0"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + }; }; &cmt0 { @@ -169,6 +228,28 @@ }; }; +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &i2c1 { pinctrl-0 = <&i2c1_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From e6ed3f533d54a92f8d67d301f9209ca64d593e03 Mon Sep 17 00:00:00 2001 From: Simon Horman Date: Tue, 9 Aug 2016 14:19:04 +0200 Subject: ARM: dts: alt: add MMCIF support Define the Alt board dependent part of the MMCIF device node. Like the Silk the board has eMMC chip along with the necessary voltage regulator (note that the Vcc/Vccq regulator is dummy -- it's required by the MMCIF driver but doesn't actually exist on the board). Based on work for the Silk board by Vladimir Barinov and Sergei Shtylyov. Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index fe7c128cc965..8d1b35afaf82 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -30,6 +30,15 @@ reg = <0 0x40000000 0 0x40000000>; }; + d3_3v: regulator-d3-3v { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; @@ -190,6 +199,11 @@ function = "vin0"; }; + mmcif0_pins: mmcif0 { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -228,6 +242,17 @@ }; }; +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&d3_3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; -- cgit v1.2.3 From 7b2d7a214708e06d89fd8019aa6f3acf744a3446 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 16 Aug 2016 16:56:31 +0200 Subject: ARM: dts: r8a7790: Remove obsolete vsp1 properties As of commit 5aa2eb3c86d4fd16 ("[media] v4l: vsp1: Configure device based on IP version"), the DT properties to identify the exact VSP device instance features are no longer used. Hence remove them. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index d18558f21102..351fcc2f87df 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -944,11 +944,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe928000 { @@ -957,12 +952,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lut; - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <3>; - renesas,#wpf = <4>; }; vsp1@fe930000 { @@ -971,12 +960,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe938000 { @@ -985,12 +968,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; du: display@feb00000 { -- cgit v1.2.3 From 17d9af9e069f2982f578c65e987df309d1736eb5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 16 Aug 2016 16:56:32 +0200 Subject: ARM: dts: r8a7791: Remove obsolete vsp1 properties As of commit 5aa2eb3c86d4fd16 ("[media] v4l: vsp1: Configure device based on IP version"), the DT properties to identify the exact VSP device instance features are no longer used. Hence remove them. Signed-off-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 8f0086bbd96b..162b55c665a3 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -983,12 +983,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lut; - renesas,has-sru; - renesas,#rpf = <5>; - renesas,#uds = <3>; - renesas,#wpf = <4>; }; vsp1@fe930000 { @@ -997,12 +991,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; vsp1@fe938000 { @@ -1011,12 +999,6 @@ interrupts = ; clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; - - renesas,has-lif; - renesas,has-lut; - renesas,#rpf = <4>; - renesas,#uds = <1>; - renesas,#wpf = <4>; }; du: display@feb00000 { -- cgit v1.2.3 From 2f5ac9ba208c1049d822a2f98d8193b4e322f3ca Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 10 Aug 2016 13:00:28 -0300 Subject: ARM: dts: imx7s: Add SDMA node Add a SDMA entry in the dtsi file. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index c63591c1f25e..9a5fdbbcedcd 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -911,6 +911,17 @@ status = "disabled"; }; + sdma: sdma@30bd0000 { + compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; + reg = <0x30bd0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SDMA_CORE_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; + }; + fec1: ethernet@30be0000 { compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; reg = <0x30be0000 0x10000>; -- cgit v1.2.3 From 7310f07531f786a8d776f637b4504caa52c57460 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 10 Aug 2016 13:00:27 -0300 Subject: ARM: dts: imx7s: Add SAI nodes Add the three SAI ports nodes. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 45 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9a5fdbbcedcd..be80156d8061 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -723,6 +723,51 @@ status = "disabled"; }; + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; + flexcan1: can@30a00000 { compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; reg = <0x30a00000 0x10000>; -- cgit v1.2.3 From e7d0dbf9e29852064aa03d7b44f3f134808cdae4 Mon Sep 17 00:00:00 2001 From: Joshua Clayton Date: Mon, 15 Aug 2016 22:29:45 +0800 Subject: ARM: dts: imx6q-evi: Use GPIO_6 for fec irq Apply hardware workaround for ethernet problem See nxp erratum err006687 Signed-off-by: Joshua Clayton Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-evi.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts index 9647c099acc6..6de21ff47c3a 100644 --- a/arch/arm/boot/dts/imx6q-evi.dts +++ b/arch/arm/boot/dts/imx6q-evi.dts @@ -139,6 +139,9 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; phy-reset-gpios = <&gpio1 25 0>; + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, + <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; + fsl,err006687-workaround-present; status = "okay"; }; @@ -318,6 +321,7 @@ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 >; }; -- cgit v1.2.3 From f5bd51b60f4994023b5edd9241d2c0a839598553 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 11 Aug 2016 17:11:06 -0700 Subject: ARM: dts: imx7d: move CPU operating points to imx7d.dtsi Only i.MX 7Dual SoC supports CPU frequencies of up to 1GHz. The i.MX 7Solo can run with up to 800MHz and does so without making use of DVFS usually. While the device tree clearly specified a too fast operating point for i.MX 7Solo, the kernel did not used it in practise so far because the CPUfreq driver does not get loaded on i.MX 7Solo devices (since the fsl,imx7s compatible string is not in the list of devices making use of the cpufreq-dt driver...). Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 8 ++++++++ arch/arm/boot/dts/imx7s.dtsi | 5 ----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 3d77d95bbc9d..d0b199c2e0df 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -45,6 +45,14 @@ / { cpus { + cpu0: cpu@0 { + operating-points = < + /* KHz uV */ + 996000 1075000 + 792000 975000 + >; + }; + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index be80156d8061..75e9d1b55994 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -85,11 +85,6 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; - operating-points = < - /* KHz uV */ - 996000 1075000 - 792000 975000 - >; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; }; -- cgit v1.2.3 From 1c4e2a11bac4b5b04cd6588840341af28e137588 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Thu, 11 Aug 2016 17:11:07 -0700 Subject: ARM: dts: imx7d: add clock-frequency to CPU nodes Add clock-frequency property to CPU nodes. Avoids warnings like "/cpus/cpu@0 missing clock-frequency property". Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 2 ++ arch/arm/boot/dts/imx7s.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index d0b199c2e0df..f6dee41a05d9 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -51,12 +51,14 @@ 996000 1075000 792000 975000 >; + clock-frequency = <996000000>; }; cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; + clock-frequency = <996000000>; }; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 75e9d1b55994..bb7102cae899 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -85,6 +85,7 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; }; -- cgit v1.2.3 From 9a3bb943c26d6e16effa7cb828f35ed660538fee Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 Aug 2016 13:47:32 -0300 Subject: ARM: dts: imx7s-warp: Add audio support warp7 has a sgtl5000 audio codec. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 51 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index ae23781034fd..f819003f2d4a 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -53,6 +53,27 @@ memory { reg = <0x80000000 0x20000000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; }; &cpu0 { @@ -161,12 +182,32 @@ pinctrl-0 = <&pinctrl_i2c4>; status = "okay"; + codec: sgtl5000@0a { + #sound-dai-cells = <0>; + reg = <0x0a>; + compatible = "fsl,sgtl5000"; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + VDDA-supply = <&vgen4_reg>; + VDDIO-supply = <&vgen4_reg>; + VDDD-supply = <&vgen2_reg>; + }; + mpl3115@60 { compatible = "fsl,mpl3115"; reg = <0x60>; }; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; @@ -208,6 +249,16 @@ >; }; + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 -- cgit v1.2.3 From 44e645faffa7428502712cc6062a92a07ae09679 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 Aug 2016 13:47:33 -0300 Subject: ARM: dts: imx7s-warp: Add Wifi support Warp7 has a BCM43430 Wifi chip connected to the USDHC1 port. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 41 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index f819003f2d4a..4d4959c856a9 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -54,6 +54,18 @@ reg = <0x80000000 0x20000000>; }; + reg_brcm: regulator-brcm { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_reg>; + regulator-name = "brcm_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <200000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -221,6 +233,17 @@ status = "okay"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + keep-power-in-suspend; + no-1-8-v; + non-removable; + vmmc-supply = <®_brcm>; + status = "okay"; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; @@ -235,6 +258,12 @@ }; &iomuxc { + pinctrl_brcm_reg: brcmreggrp { + fsl,pins = < + MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f @@ -266,6 +295,18 @@ >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */ + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX7D_PAD_SD3_CMD__SD3_CMD 0x59 -- cgit v1.2.3 From a7311c0c9a338d18f4a6d21dfad34c66053c9225 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 15 Aug 2016 13:47:34 -0300 Subject: ARM: dts: imx7s-warp: Use WDOG_B pin reset imx7s-warpd has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via the PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 4d4959c856a9..92d9c8570716 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -257,6 +257,13 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < @@ -354,4 +361,10 @@ MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B 0x74 + >; + }; }; -- cgit v1.2.3 From 31e3a8817b66034d49c988617f8ca2822275db7c Mon Sep 17 00:00:00 2001 From: Karl Beldan Date: Tue, 16 Aug 2016 22:33:37 +0000 Subject: ARM: dts: da850,da850-evm: Add an aemif node and use it for the NAND Currently the davinci da8xx boards use the mach-davinci aemif code. Instantiating an aemif node into the DT allows to use the ti-aemif memory driver and is another step to better DT support. This change adds an aemif node in the dtsi while retiring the nand_cs3 node. The NAND is now instantiated in the dts as a subnode of the aemif one along with its pins. Signed-off-by: Karl Beldan Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-evm.dts | 49 ++++++++++++++++++++++++++++++++++++----- arch/arm/boot/dts/da850.dtsi | 35 +++++++---------------------- 2 files changed, 52 insertions(+), 32 deletions(-) diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1a15db8e376b..eedcc592ba51 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -29,6 +29,20 @@ 0x04 0x00011000 0x000ff000 >; }; + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[4], EMA_CS[3] */ + 0x1c 0x10110110 0xf0ff0ff0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; }; serial0: serial@42000 { status = "okay"; @@ -131,11 +145,6 @@ status = "okay"; }; }; - nand_cs3@62000000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&nand_cs3_pins>; - }; vbat: fixedregulator@0 { compatible = "regulator-fixed"; regulator-name = "vbat"; @@ -250,3 +259,33 @@ &edma1 { ti,edma-reserved-slot-ranges = <32 90>; }; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "ok"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + }; + }; +}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index 5aac622c7959..f79e1b91c680 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -77,22 +77,6 @@ 0x10 0x00220000 0x00ff0000 >; }; - nand_cs3_pins: pinmux_nand_pins { - pinctrl-single,bits = < - /* EMA_OE, EMA_WE */ - 0x1c 0x00110000 0x00ff0000 - /* EMA_CS[4],EMA_CS[3]*/ - 0x1c 0x00000110 0x00000ff0 - /* - * EMA_D[0], EMA_D[1], EMA_D[2], - * EMA_D[3], EMA_D[4], EMA_D[5], - * EMA_D[6], EMA_D[7] - */ - 0x24 0x11111111 0xffffffff - /* EMA_A[1], EMA_A[2] */ - 0x30 0x01100000 0x0ff00000 - >; - }; i2c0_pins: pinmux_i2c0_pins { pinctrl-single,bits = < /* I2C0_SDA,I2C0_SCL */ @@ -416,17 +400,14 @@ dma-names = "tx", "rx"; }; }; - nand_cs3@62000000 { - compatible = "ti,davinci-nand"; - reg = <0x62000000 0x807ff - 0x68000000 0x8000>; - ti,davinci-chipselect = <1>; - ti,davinci-mask-ale = <0>; - ti,davinci-mask-cle = <0>; - ti,davinci-mask-chipsel = <0>; - ti,davinci-ecc-mode = "hw"; - ti,davinci-ecc-bits = <4>; - ti,davinci-nand-use-bbt; + aemif: aemif@68000000 { + compatible = "ti,da850-aemif"; + #address-cells = <2>; + #size-cells = <1>; + + reg = <0x68000000 0x00008000>; + ranges = <0 0 0x60000000 0x08000000 + 1 0 0x68000000 0x00008000>; status = "disabled"; }; }; -- cgit v1.2.3 From 3625de0fef696b8220f3d452156fecc2295831d4 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Thu, 18 Aug 2016 01:03:10 +0800 Subject: ARM: dts: rockchip: remove excess sd properties from firefly reload Because of a bug in hardware design, the sdcard at firefly rk3288 reload board can't switch the io voltage level to 1.8v. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly-reload.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index dd8ab233438f..a127b453d0a1 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -207,11 +207,6 @@ num-slots = <1>; pinctrl-names = "default"; pinctrl-0 = <&sdmmc_clk>, <&sdmmc_cmd>, <&sdmmc_cd>, <&sdmmc_bus4>; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; - sd-uhs-ddr50; vmmc-supply = <&vcc_sd>; vqmmc-supply = <&vccio_sd>; status = "okay"; -- cgit v1.2.3 From 7693df8319dfdedca0bfb678402b95200eb70e50 Mon Sep 17 00:00:00 2001 From: Randy Li Date: Thu, 18 Aug 2016 01:03:11 +0800 Subject: ARM: dts: rockchip: add missing regulators for firefly reload board There are many regulators are missed in previous commit, this commit complete most of them. It also fix some mistakes in the regulator properties. The VDD_10(REG10) and VCC_18(REG11) had better to keep in always-on state, as it is used as the USB PHY supply, corretly we have no way to assign power supply to a USB PHY. The VCCA_33(REG8) should be enabled or the GMAC won't work. It also fix the wrong properties for audio in io-domains, the supply connected to APIO4_VDD is different to firefly release version. Signed-off-by: Randy Li Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi | 48 ++++-------------- arch/arm/boot/dts/rk3288-firefly-reload.dts | 62 +++++++++++++++++++++-- 2 files changed, 67 insertions(+), 43 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi index 73c88ffd8260..ec418c99de95 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi +++ b/arch/arm/boot/dts/rk3288-firefly-reload-core.dtsi @@ -50,14 +50,6 @@ reg = <0 0x80000000>; }; - dovdd_1v8: dovdd-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "dovdd_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc28_dvp>; - }; - ext_gmac: external-gmac-clock { compatible = "fixed-clock"; #clock-cells = <0>; @@ -65,14 +57,6 @@ clock-output-names = "ext_gmac"; }; - vbat_wl: vcc_sys: vsys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; vcc_flash: flash-regulator { compatible = "regulator-fixed"; @@ -81,16 +65,6 @@ regulator-max-microvolt = <1800000>; vin-supply = <&vcc_io>; }; - - vcc_5v: usb-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_5v"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; }; &cpu0 { @@ -205,34 +179,34 @@ regulator-name = "vccio_sd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; vdd10_lcd: REG6 { regulator-name = "vdd10_lcd"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + }; + + vcca_18: REG7 { + regulator-name = "vcca_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-always-on; }; - vcca_33: REG7 { + vcca_33: REG8 { regulator-name = "vcca_33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; - vcc_lan: REG8 { + vcc_lan: REG9 { regulator-name = "vcca_lan"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; - vccio_pmu: REG9 { - regulator-name = "vccio_pmu"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - vdd_10: REG10 { regulator-name = "vdd_10"; regulator-min-microvolt = <1000000>; @@ -244,14 +218,12 @@ regulator-name = "vcc_18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; }; vcc18_lcd: REG12 { regulator-name = "vcc18_lcd"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-always-on; }; }; }; @@ -260,7 +232,7 @@ &io_domains { status = "okay"; - audio-supply = <&vcca_33>; + audio-supply = <&vccio_wl>; bb-supply = <&vcc_io>; dvp-supply = <&dovdd_1v8>; flash0-supply = <&vcc_flash>; diff --git a/arch/arm/boot/dts/rk3288-firefly-reload.dts b/arch/arm/boot/dts/rk3288-firefly-reload.dts index a127b453d0a1..751bee81128e 100644 --- a/arch/arm/boot/dts/rk3288-firefly-reload.dts +++ b/arch/arm/boot/dts/rk3288-firefly-reload.dts @@ -122,6 +122,15 @@ vin-supply = <&vcc_5v>; }; + vcc_5v: vcc_sys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_sd: sdmmc-regulator { compatible = "regulator-fixed"; gpio = <&gpio7 11 GPIO_ACTIVE_LOW>; @@ -147,10 +156,18 @@ vin-supply = <&vcc_5v>; }; - /* - * A TT8142 creates both dovdd_1v8 and vcc28_dvp, controlled - * by the dvp_pwr pin. - */ + dovdd_1v8: dovdd-1v8-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "dovdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_io>; + }; + vcc28_dvp: vcc28-dvp-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -160,7 +177,38 @@ regulator-name = "vcc28_dvp"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; + vin-supply = <&vcc_io>; + }; + + af_28: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&dvp_pwr>; + regulator-name = "af_28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <&vcc_io>; + }; + + dvdd_1v2: af_28-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cif_pwr>; + regulator-name = "dvdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + vin-supply = <&vcc_io>; + }; + + vbat_wl: wifi-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbat_wl"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; vin-supply = <&vcc_io>; }; }; @@ -278,6 +326,10 @@ dvp_pwr: dvp-pwr { rockchip,pins = <0 11 RK_FUNC_GPIO &pcfg_pull_none>; }; + + cif_pwr: cif-pwr { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; hym8563 { -- cgit v1.2.3 From 5a5232d1932b5d1ca472037bc8b38c21fa0cb6f8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 17 Aug 2016 09:34:58 +0200 Subject: ARM: dts: exynos: Use stdout non-deprecated property and add serial options to Odroid XU/XU3/XU4 The "linux,stdout-path" is deprecated. Add serial options so the console can be properly configured when bootloader does not pass "console" parameter to the command line. Without options and lack of "console" in command line, the serial output dies during boot (just after probing sound, probably because of rate change). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index d9499310a301..3912969ec223 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -26,7 +26,7 @@ }; chosen { - linux,stdout-path = &serial_2; + stdout-path = "serial2:115200n8"; }; emmc_pwrseq: pwrseq { diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccb..d04490d40b07 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -26,7 +26,7 @@ }; chosen { - linux,stdout-path = &serial_2; + stdout-path = "serial2:115200n8"; }; firmware@02073000 { -- cgit v1.2.3 From 9d05b389846312751108b16f3f8fccd51fa92715 Mon Sep 17 00:00:00 2001 From: Karl Beldan Date: Wed, 17 Aug 2016 12:54:54 +0000 Subject: ARM: dts: da850-lcdk: Audio support via simple-card The LCDK embeds a TLV320AIC3106 connected to the SoC McASP for analog audio. The power supply of the codec comes from the main PMIC (TPS650250) DCDCs which are always on per HW design and not controllable by SW, so SW wise the codec driver will rely on the 'dummy' regulator. Quality is good with arecord -pipe- aplay on Line In/Line Out. Tested-by: Kevin Hilman Signed-off-by: Karl Beldan Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lcdk.dts | 68 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index dbcca0bc18d0..7563260e95d1 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -23,10 +23,46 @@ device_type = "memory"; reg = <0xc0000000 0x08000000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 LCDK"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; }; &pmx_core { status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* AHCLKX AFSX ACLKX */ + 0x00 0x00101010 0x00f0f0f0 + /* ARX13 ARX14 */ + 0x04 0x00000110 0x00000ff0 + >; + }; }; &serial2 { @@ -68,3 +104,35 @@ cd-gpios = <&gpio 64 GPIO_ACTIVE_HIGH>; status = "okay"; }; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; + + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + }; +}; + +&mcasp0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + status = "okay"; + + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 1 2 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; -- cgit v1.2.3 From 1c7f349a896330b05754fd63938c9b1218e35c73 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 17 Aug 2016 22:03:06 +0300 Subject: ARM: dts: blanche: add support for general purpose switches Add support for the general purpose software switches SW2 and tactile switches SW24/25 as a virtual keyboard (like it was done with the Lager/ Koelsch boards). Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index eeffba870211..808a6aab7e5e 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -11,6 +11,8 @@ /dts-v1/; #include "r8a7792.dtsi" +#include +#include / { model = "Blanche"; @@ -54,6 +56,53 @@ pinctrl-0 = <&lan89218_pins>; pinctrl-names = "default"; }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = ; + label = "SW2-1"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 10 GPIO_ACTIVE_LOW>; + }; + key-2 { + linux,code = ; + label = "SW2-2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + }; + key-3 { + linux,code = ; + label = "SW2-3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + }; + key-4 { + linux,code = ; + label = "SW2-4"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + key-a { + linux,code = ; + label = "SW24"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = ; + label = "SW25"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; }; &extal_clk { -- cgit v1.2.3 From 614a749a1050fc87bad09ac5d155f269ed66aa80 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 27 Feb 2016 15:55:29 -0800 Subject: ARM: dt: axp209: Add AXP209 GPIO driver Add the AXP209 GPIO node to our AXP209 DTSI so that boards can use it. Signed-off-by: Maxime Ripard Acked-by: Linus Walleij --- arch/arm/boot/dts/axp209.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi index afbe89c01df5..675bb0f30825 100644 --- a/arch/arm/boot/dts/axp209.dtsi +++ b/arch/arm/boot/dts/axp209.dtsi @@ -53,6 +53,12 @@ interrupt-controller; #interrupt-cells = <1>; + axp_gpio: gpio { + compatible = "x-powers,axp209-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + regulators { /* Default work frequency for buck regulators */ x-powers,dcdc-freq = <1500>; -- cgit v1.2.3 From 3d3f05e643dbe79c996803fff8de97cb7209d057 Mon Sep 17 00:00:00 2001 From: Maxime Ripard Date: Sat, 27 Feb 2016 15:56:21 -0800 Subject: ARM: sun5i: chip: Add status LED The CHIP has a status LED connected to one of the AXP GPIOs. Add the gpio-leds node to be able to use the proper LED framework to control it. Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-r8-chip.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index f694482bdeb6..b68a12374b35 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -64,6 +64,16 @@ chosen { stdout-path = "serial0:115200n8"; }; + + leds { + compatible = "gpio-leds"; + + status { + label = "chip:white:status"; + gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; }; &be0 { -- cgit v1.2.3 From 4b09a6faa83705864ff53f3c287800b7244f5a6a Mon Sep 17 00:00:00 2001 From: Stefan Mavrodiev Date: Mon, 15 Aug 2016 10:36:33 +0300 Subject: ARM: dts: sun8i: Add dts file for Olimex A33-OLinuXino A33-OLinuXino is A33 development board designed by Olimex LTD. It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector, headphone and mic jacks, connector for LiPo battery and optional 4GB NAND Flash. It has two 40-pin headers. One for LCD panel, and one for additional modules. Also there is CSI/DSI connector. Signed-off-by: Stefan Mavrodiev Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-a33-olinuxino.dts | 226 ++++++++++++++++++++++++++++++ 2 files changed, 227 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a33-olinuxino.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6b3bdb6f7e7f..75cd98a86707 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -783,6 +783,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ + sun8i-a33-olinuxino.dtb \ sun8i-a33-q8-tablet.dtb \ sun8i-a33-sinlinx-sina33.dtb \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a33-olinuxino.dts b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts new file mode 100644 index 000000000000..9ea637e82b2d --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-olinuxino.dts @@ -0,0 +1,226 @@ +/* + * Copyright 2016 - Stefan Mavrodiev + * Olimex LTD. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "Olimex A33-OLinuXino"; + compatible = "olimex,a33-olinuxino","allwinner,sun8i-a33"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_olinuxino>; + + green { + label = "a33-olinuxino:green:usr"; + gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&ehci0 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ + cd-inverted; + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&pio { + led_pin_olinuxino: led_pins@0 { + allwinner,pins = "PB7"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PB3"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_rsb { + status = "okay"; + + axp22x: pmic@3a3 { + compatible = "x-powers,axp223"; + reg = <0x3a3>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + eldoin-supply = <®_dcdc1>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-io"; +}; + +®_aldo2 { + regulator-always-on; + regulator-min-microvolt = <2350000>; + regulator-max-microvolt = <2650000>; + regulator-name = "vdd-dll"; +}; + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpus"; +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +®_rtc_ldo { + regulator-name = "vcc-rtc"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_b>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + status = "okay"; +}; -- cgit v1.2.3 From dc36787fedf0248c752cf1c53092104d54489617 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 7 Aug 2016 16:16:44 +0200 Subject: ARM: dts: sun8i: Add dts file for the Orange Pi Lite SBC The Orange Pi Lite SBC is a small H3 based SBC, with 512MB RAM, micro-sd slot, HDMI out, 2 USB-A connectors, 1 micro-USB connector, sdio attached rtl8189ftv wifi and an ir receiver. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts | 178 +++++++++++++++++++++++++++ 2 files changed, 179 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 75cd98a86707..55a3e9d8545a 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -790,6 +790,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ sun8i-h3-orangepi-2.dtb \ + sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts new file mode 100644 index 000000000000..1550fee1ec68 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-lite.dts @@ -0,0 +1,178 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + model = "Xunlong Orange Pi Lite"; + compatible = "xunlong,orangepi-lite", "allwinner,sun8i-h3"; + + aliases { + /* The H3 emac is not used so the wifi is ethernet0 */ + ethernet0 = &rtl8189ftv; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr_led { + label = "orangepi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + status_led { + label = "orangepi:red:status"; + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>; + }; + }; + + r_gpio_keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&sw_r_opc>; + + sw4 { + label = "sw4"; + linux,code = ; + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ir { + pinctrl-names = "default"; + pinctrl-0 = <&ir_pins_a>; + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + + /* + * Explicitly define the sdio device, so that we can add an ethernet + * alias for it (which e.g. makes u-boot set a mac-address). + */ + rtl8189ftv: sdio_wifi@1 { + reg = <1>; + }; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&pio { + leds_opc: led_pins@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_pio { + leds_r_opc: led_pins@0 { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + + sw_r_opc: key_pins@0 { + allwinner,pins = "PL3"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; -- cgit v1.2.3 From 9d3ee5754335416bde2e75e93048294b8423e7c6 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 8 Aug 2016 21:43:11 +0200 Subject: ARM: dts: sun8i: Use sun8i-reference-design-tablet for gt90h dts This results in quite a nice cleanup for this dts file. As an added bonus this also enables full otg support. I've tested that this works as advertised. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts | 192 +------------------------------ 1 file changed, 1 insertion(+), 191 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts index b2ce284a65a2..f27ebbbeac09 100644 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts @@ -42,70 +42,18 @@ /dts-v1/; #include "sun8i-a23.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include -#include +#include "sun8i-reference-design-tablet.dtsi" / { model = "Allwinner GT90H Dual Core Tablet (v4)"; compatible = "allwinner,gt90h-v4", "allwinner,sun8i-a23"; - - aliases { - serial0 = &r_uart; - }; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&bl_en_pin_gt90h>; - pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>; - brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; - default-brightness-level = <8>; - enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */ - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; }; &ehci0 { status = "okay"; }; -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; -}; - &lradc { - vref-supply = <®_vcc3v0>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; - button@600 { label = "Back"; linux,code = ; @@ -114,144 +62,6 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_gt90h>; - vmmc-supply = <®_aldo1>; - bus-width = <4>; - cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */ - cd-inverted; - status = "okay"; -}; - -&pio { - bl_en_pin_gt90h: bl_en_pin@0 { - allwinner,pins = "PH6"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - mmc0_cd_pin_gt90h: mmc0_cd_pin@0 { - allwinner,pins = "PB4"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pins>; - status = "okay"; -}; - -&r_rsb { - status = "okay"; - - axp22x: pmic@3a3 { - compatible = "x-powers,axp223"; - reg = <0x3a3>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - eldoin-supply = <®_dcdc1>; - }; -}; - -&r_uart { - pinctrl-names = "default"; - pinctrl-0 = <&r_uart_pins_a>; - status = "okay"; -}; - -#include "axp22x.dtsi" - -®_aldo1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-io"; -}; - -®_aldo2 { - regulator-always-on; - regulator-min-microvolt = <2350000>; - regulator-max-microvolt = <2650000>; - regulator-name = "vdd-dll"; -}; - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-pll-avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpus"; -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-sys"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_rtc_ldo { - regulator-name = "vcc-rtc"; -}; - -&simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; -}; - -/* - * FIXME for now we only support host mode and rely on u-boot to have - * turned on Vbus which is controlled by the axp223 pmic on the board. - * - * Once we have axp223 support we should switch to fully supporting otg. - */ -&usb_otg { - dr_mode = "host"; - status = "okay"; -}; - &usbphy { usb1_vbus-supply = <®_dldo1>; - status = "okay"; }; -- cgit v1.2.3 From 835dbe8ffafa45907495811cb2f3a57b2cccfa27 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 8 Aug 2016 21:43:12 +0200 Subject: ARM: dts: sun8i: Add dt node for rtl8703as wifi chip on ga10h The ga10h tablet has a rtl8703as wifi chip, add a dt node describing it. This enables usage of wifi on this tablet (together with the out of tree rtl8732bs driver). Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index 65660324005c..de6269dcac3a 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -47,6 +47,11 @@ / { model = "Allwinner GA10H Quad Core Tablet (v1.1)"; compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33"; + + aliases { + /* Make u-boot set mac-address for rtl8703as (no eeprom) */ + ethernet0 = &rtl8703as; + }; }; &ehci0 { @@ -62,6 +67,19 @@ }; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8703as: sdio_wifi@1 { + reg = <1>; + }; +}; + &ohci0 { status = "okay"; }; -- cgit v1.2.3 From e8552107ae5845dd1d281cddca026ef0e4d30c80 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 8 Aug 2016 21:43:13 +0200 Subject: ARM: dts: sun8i: reference-design-tablet: Add gsl1680 touchscreen node Almost all sun8i tablets use a gsl1680 touchscreen controller, so add a node describing it to reference-design-tablet.dtsi. Almost all, but not all, so mark it as disabled by default (dts files will also need to supply a firmware-name and resolution info). Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-reference-design-tablet.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index 9d9036140511..f29897c40ae8 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -63,6 +63,27 @@ }; }; +&i2c0 { + /* + * The gsl1680 is rated at 400KHz and it will not work reliable at + * 100KHz, this has been confirmed on multiple different q8 tablets. + * The gsl1680 is the only device on this bus. + */ + clock-frequency = <400000>; + + gsl1680: touchscreen@40 { + compatible = "silead,gsl1680"; + reg = <0x40>; + interrupt-parent = <&pio>; + interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ + pinctrl-names = "default"; + pinctrl-0 = <&ts_power_pin>; + power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ + /* Most tablets use this touchscreen, but not all */ + status = "disabled"; + }; +}; + &mmc0 { pinctrl-names = "default"; pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; @@ -88,6 +109,13 @@ allwinner,pull = ; }; + ts_power_pin: ts_power_pin@0 { + allwinner,pins = "PH1"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; + usb0_id_detect_pin: usb0_id_detect_pin@0 { allwinner,pins = "PH8"; allwinner,function = "gpio_in"; -- cgit v1.2.3 From 9caf39bfb98a59848ffe05f19a0bbab65220f7e5 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 Aug 2016 15:42:24 +0800 Subject: ARM: dts: sun9i: a80-optimus: Add device node for AC100 Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index 7fd22e888602..e35c06c162a7 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -322,6 +322,30 @@ }; }; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; #include "axp809.dtsi" -- cgit v1.2.3 From 38f151d410056149c0a539bbaa2873db4d3fc9a4 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 Aug 2016 15:42:25 +0800 Subject: ARM: dts: sun9i: cubieboard4: Add device node for AC100 Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 1526b41c70f1..cf2f4b72a841 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -250,6 +250,30 @@ }; }; }; + + ac100: codec@e89 { + compatible = "x-powers,ac100"; + reg = <0xe89>; + + ac100_codec: codec { + compatible = "x-powers,ac100-codec"; + interrupt-parent = <&r_pio>; + interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */ + #clock-cells = <0>; + clock-output-names = "4M_adda"; + }; + + ac100_rtc: rtc { + compatible = "x-powers,ac100-rtc"; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + clocks = <&ac100_codec>; + #clock-cells = <1>; + clock-output-names = "cko1_rtc", + "cko2_rtc", + "cko3_rtc"; + }; + }; }; #include "axp809.dtsi" -- cgit v1.2.3 From 162669876bbecf6fb4d5b69f2cc79635565c6c3f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 19 Aug 2016 15:42:26 +0800 Subject: ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for osc32k The 32.768 kHz clock inside the A80 SoC is fed from an external source, typically the AC100 RTC module. Make the osc32k placeholder a fixed-factor clock so board dts files can specify its source. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80-optimus.dts | 5 +++++ arch/arm/boot/dts/sun9i-a80.dtsi | 11 +++++------ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index cf2f4b72a841..04b014603659 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -103,6 +103,11 @@ allwinner,drive = ; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_cubieboard4: led-pins@0 { allwinner,pins = "PH6", "PH17"; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index e35c06c162a7..fd874ded890e 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -152,6 +152,11 @@ status = "okay"; }; +&osc32k { + /* osc32k input is from AC100 */ + clocks = <&ac100_rtc 0>; +}; + &pio { led_pins_optimus: led-pins@0 { allwinner,pins = "PH0", "PH1"; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index f68b3242b33a..24e3cac4f571 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -148,15 +148,14 @@ /* * The 32k clock is from an external source, normally the - * AC100 codec/RTC chip. This clock is by default enabled - * and clocked at 32768 Hz, from the oscillator connected - * to the AC100. It is configurable, but no such driver or - * bindings exist yet. + * AC100 codec/RTC chip. This serves as a placeholder for + * board dts files to specify the source. */ osc32k: osc32k_clk { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; clock-output-names = "osc32k"; }; -- cgit v1.2.3 From a343dfdd9612855395cb6a65a8907dd7256ef80e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Aug 2016 20:02:15 +0200 Subject: ARM: dts: sun6i: colorfly-e708-q1: Remove unused mma8452_int_e708_q1 node The presence of the mma8452_int_e708_q1 node is a copy and paste error, remove it. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts index 9040bb9f80f3..34d8710a7c46 100644 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -93,13 +93,6 @@ }; &pio { - mma8452_int_e708_q1: mma8452_int_pin@0 { - allwinner,pins = "PA9"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { allwinner,pins = "PA8"; allwinner,function = "gpio_in"; -- cgit v1.2.3 From b32aea85144ff046b2f8f40c48113d1a06086239 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Aug 2016 20:02:16 +0200 Subject: ARM: dts: sun6i: Add sun6i-reference-design-tablet.dtsi Just like with a13/a23/a33 most a31 tablets are derived from the same reference design. Add a .dtsi file with all the common bits to avoid endless copy and pasting of these. The sun6i-reference-design-tablet.dtsi this commit adds is a copy of sun6i-a31s-colorfly-e708-q1.dts with a few tablet specific bits removed / left in sun6i-a31s-colorfly-e708-q1.dts. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts | 147 +--------------- .../boot/dts/sun6i-reference-design-tablet.dtsi | 193 +++++++++++++++++++++ 2 files changed, 194 insertions(+), 146 deletions(-) create mode 100644 arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi diff --git a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts index 34d8710a7c46..882a4d89fa22 100644 --- a/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts +++ b/arch/arm/boot/dts/sun6i-a31s-colorfly-e708-q1.dts @@ -42,32 +42,11 @@ /dts-v1/; #include "sun6i-a31s.dtsi" -#include "sunxi-common-regulators.dtsi" - -#include -#include -#include +#include "sun6i-reference-design-tablet.dtsi" / { model = "Colorfly E708 Q1 tablet"; compatible = "colorfly,e708-q1", "allwinner,sun6i-a31s"; - - aliases { - serial0 = &uart0; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&cpu0 { - cpu-supply = <®_dcdc3>; -}; - -&ehci0 { - /* rtl8188etv wifi is connected here */ - status = "okay"; }; &lradc { @@ -82,136 +61,12 @@ }; }; -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; - vmmc-supply = <®_dcdc1>; - bus-width = <4>; - cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ - cd-inverted; - status = "okay"; -}; - -&pio { - mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { - allwinner,pins = "PA8"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PA15"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -&p2wi { - status = "okay"; - - axp22x: pmic@68 { - compatible = "x-powers,axp221"; - reg = <0x68>; - interrupt-parent = <&nmi_intc>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - drivevbus-supply = <®_vcc5v0>; - x-powers,drive-vbus-en; - }; -}; - -#include "axp22x.dtsi" - -®_aldo3 { - regulator-always-on; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3300000>; - regulator-name = "avcc"; -}; - -®_dc1sw { - regulator-name = "vcc-lcd"; -}; - -®_dc5ldo { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpus"; /* This is an educated guess */ -}; - -®_dcdc1 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; -}; - -®_dcdc2 { - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-gpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc4 { - regulator-always-on; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <1320000>; - regulator-name = "vdd-sys-dll"; -}; - -®_dcdc5 { - regulator-always-on; - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-name = "vcc-dram"; -}; - -®_dldo1 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - ®_dldo2 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-name = "vcc-pg"; }; -®_drivevbus { - regulator-name = "usb0-vbus"; - status = "okay"; -}; - &simplefb_lcd { - vcc-lcd-supply = <®_dc1sw>; vcc-pg-supply = <®_dldo2>; }; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb_power_supply { - status = "okay"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>; - usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ - usb0_vbus_power-supply = <&usb_power_supply>; - usb0_vbus-supply = <®_drivevbus>; - usb1_vbus-supply = <®_dldo1>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi new file mode 100644 index 000000000000..0c434304e040 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-reference-design-tablet.dtsi @@ -0,0 +1,193 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "sunxi-common-regulators.dtsi" + +#include +#include +#include + +/ { + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc3>; +}; + +&ehci0 { + /* Wifi is connected here */ + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_e708_q1>; + vmmc-supply = <®_dcdc1>; + bus-width = <4>; + cd-gpios = <&pio 0 8 GPIO_ACTIVE_HIGH>; /* PA8 */ + cd-inverted; + status = "okay"; +}; + +&pio { + mmc0_cd_pin_e708_q1: mmc0_cd_pin@0 { + allwinner,pins = "PA8"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; + + usb0_id_detect_pin: usb0_id_detect_pin@0 { + allwinner,pins = "PA15"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&p2wi { + status = "okay"; + + axp22x: pmic@68 { + compatible = "x-powers,axp221"; + reg = <0x68>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + drivevbus-supply = <®_vcc5v0>; + x-powers,drive-vbus-en; + }; +}; + +#include "axp22x.dtsi" + +®_aldo3 { + regulator-always-on; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3300000>; + regulator-name = "avcc"; +}; + +®_dc1sw { + regulator-name = "vcc-lcd"; +}; + +®_dc5ldo { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpus"; /* This is an educated guess */ +}; + +®_dcdc1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-3v0"; +}; + +®_dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-gpu"; +}; + +®_dcdc3 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc4 { + regulator-always-on; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1320000>; + regulator-name = "vdd-sys-dll"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +®_dldo1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi"; +}; + +®_drivevbus { + regulator-name = "usb0-vbus"; + status = "okay"; +}; + +&simplefb_lcd { + vcc-lcd-supply = <®_dc1sw>; +}; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usb_power_supply { + status = "okay"; +}; + +&usbphy { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_id_detect_pin>; + usb0_id_det-gpio = <&pio 0 15 GPIO_ACTIVE_HIGH>; /* PA15 */ + usb0_vbus_power-supply = <&usb_power_supply>; + usb0_vbus-supply = <®_drivevbus>; + usb1_vbus-supply = <®_dldo1>; + status = "okay"; +}; -- cgit v1.2.3 From f0b631edb8a1f66e6171150d54c1533accb10b04 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Thu, 18 Aug 2016 20:02:17 +0200 Subject: ARM: dts: sun6i: Add new dts file for tablets using the inet-q972 PCB Add a dts file for tablets using the generic inet-q972 PCB. Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host, micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot, (mini) power-barrel and an usb wifi module. This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet. Signed-off-by: Hans de Goede Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun6i-a31s-inet-q972.dts | 100 +++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) create mode 100644 arch/arm/boot/dts/sun6i-a31s-inet-q972.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 55a3e9d8545a..1ec7fe99de33 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -743,6 +743,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-mele-a1000g-quad.dtb \ sun6i-a31s-colorfly-e708-q1.dtb \ sun6i-a31s-cs908.dtb \ + sun6i-a31s-inet-q972.dtb \ sun6i-a31s-primo81.dtb \ sun6i-a31s-sina31s.dtb \ sun6i-a31s-sinovoip-bpi-m2.dtb \ diff --git a/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts new file mode 100644 index 000000000000..e584e6b186a7 --- /dev/null +++ b/arch/arm/boot/dts/sun6i-a31s-inet-q972.dts @@ -0,0 +1,100 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun6i-a31s.dtsi" +#include "sun6i-reference-design-tablet.dtsi" + +/ { + model = "iNet Q972 tablet"; + compatible = "inet-tek,inet-q972", "allwinner,sun6i-a31s"; +}; + +&ehci1 { + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + ft5406ee8: touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&pio>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; /* PA3 */ + touchscreen-size-x = <768>; + touchscreen-size-y = <1024>; + touchscreen-swapped-x-y; + }; +}; + +&lradc { + vref-supply = <®_aldo3>; + status = "okay"; + + button@200 { + label = "Volume Down"; + linux,code = ; + channel = <0>; + voltage = <200000>; + }; + + button@900 { + label = "Volume Up"; + linux,code = ; + channel = <0>; + voltage = <900000>; + }; + + button@1200 { + label = "Back"; + linux,code = ; + channel = <0>; + voltage = <1200000>; + }; +}; + +&ohci1 { + status = "okay"; +}; -- cgit v1.2.3 From eed3da2cf3897de7ed3e5e4ea3cd323946ca87e0 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Thu, 18 Aug 2016 21:31:54 +0300 Subject: ARM: dts: blanche: add SDHI0 support Define the Blanche board dependent part of the SDHI0 (connected to the micro-SD slot) device node along with the necessary voltage regulator. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 808a6aab7e5e..436d44ea3c12 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -103,6 +103,17 @@ gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; }; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &extal_clk { @@ -139,6 +150,11 @@ groups = "can0_data", "can_clk"; function = "can0"; }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; }; &scif0 { @@ -161,3 +177,12 @@ status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -- cgit v1.2.3 From a66f74f464fb1e501d1b448c99e8f9ae4e64da2b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 19 Aug 2016 23:42:54 +0300 Subject: ARM: dts: blanche: add DU support Define the Blanche board dependent part of the DU device node. Add the device nodes for the Analog Devices ADV7511W HDMI transmitter (connected to DU0) and ADV7123 video DAC (connected to DU1). Add the necessary subnodes to interconnect DU, HDMI/VDAC devices, and HDMI/VGA connectors. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 125 ++++++++++++++++++++++++++++++++++ 1 file changed, 125 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 436d44ea3c12..3c6f42b9fe9f 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -57,6 +57,61 @@ pinctrl-names = "default"; }; + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; + + x1_clk: x1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <74250000>; + }; + + x2_clk: x2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <65000000>; + }; + keyboard { compatible = "gpio-keys"; @@ -155,6 +210,16 @@ groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; }; + + du0_pins: du0 { + groups = "du0_rgb888", "du0_sync", "du0_disp"; + function = "du0"; + }; + + du1_pins: du1 { + groups = "du1_rgb666", "du1_sync", "du1_disp"; + function = "du1"; + }; }; &scif0 { @@ -186,3 +251,63 @@ cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&irqc>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + adi,input-style = <1>; + adi,input-justification = "evenly"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du0_pins &du1_pins>; + pinctrl-names = "default"; + + clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, + <&x1_clk>, <&x2_clk>; + clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + }; +}; -- cgit v1.2.3 From 5c2312ba0596224653580cbd0a89d07fe63cd057 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 20 Aug 2016 01:18:54 +0300 Subject: ARM: dts: r8a7792: add VSP1V clocks Describe the VSP1V clocks in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 9763289db5ce..856e6c5b94bc 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -757,10 +757,15 @@ compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>; + clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; - clock-indices = ; - clock-output-names = "jpu"; + clock-indices = < + R8A7792_CLK_JPU + R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 + R8A7792_CLK_VSP1_SY + >; + clock-output-names = "jpu", "vsp1du1", "vsp1du0", + "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7792-mstp-clocks", -- cgit v1.2.3 From 9e1019c690ab0d7829e8d795cc46dba23728d997 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 20 Aug 2016 01:19:48 +0300 Subject: ARM: dts: r8a7792: add VSP1V support Describe 3 instances (VSPS, VSPD0, and VSPD1) of the VSP1V in the R8A7792 device tree. Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 856e6c5b94bc..ff47755fb01e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -668,6 +668,30 @@ status = "disabled"; }; + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = ; + clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = ; + clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = ; + clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7792-cpg-clocks", -- cgit v1.2.3 From ec5200bb59abf28bf21df444caf26230bef6ae0c Mon Sep 17 00:00:00 2001 From: John Stultz Date: Fri, 1 Jul 2016 22:33:25 -0700 Subject: device-tree: nexus7: Set phy mode to otg instead of host In order to have the usb phy work in gadget mode, override the default host mode with otg mode. This allows gadget mode to work w/o any hacks to the dtsi file. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 7b05f072bfc2..94e9cbbc6122 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -253,6 +253,7 @@ vddcx-supply = <&pm8921_s3>; v3p3-supply = <&pm8921_l3>; v1p8-supply = <&pm8921_l4>; + dr_mode = "otg"; }; gadget@12500000 { -- cgit v1.2.3 From 3f874a44f54628484238b5986233fc802116d93f Mon Sep 17 00:00:00 2001 From: John Stultz Date: Tue, 12 Jul 2016 15:39:55 -0700 Subject: device-tree: aqp8064.dtsi: Remove usb phy dr_mode = "host" Most 8064 devices have micro-usb ports for phy1, so setting the dr_mode to host here seems incorrect. Leaving it unspecified should default to otg, and then any boards that wish to specify something else, can override it in their dts file. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 74a9b6c394f5..e9aaeb257422 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -712,7 +712,6 @@ reg = <0x12500000 0x400>; interrupts = ; status = "disabled"; - dr_mode = "host"; clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>; -- cgit v1.2.3 From 5cae8a9fbf0bfd5b4b090d260cb3a7e1138aed7d Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Wed, 13 Jul 2016 13:04:26 +0530 Subject: ARM: dts: msm8974: Add nodes for blsp1_uart1 serial port This serial port is used by LG Nexus 5 (codenammed hammerhead). Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 561d4d136762..4d0cfeb4c2e6 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -430,6 +430,15 @@ reg = <0xfc428000 0x4000>; }; + blsp1_uart1: serial@f991d000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf991d000 0x1000>; + interrupts = <0 107 0x0>; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart2: serial@f991e000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xf991e000 0x1000>; -- cgit v1.2.3 From 67f8425d0ee18c1047a5aaaea529d14d32ca9b43 Mon Sep 17 00:00:00 2001 From: "twp@codeaurora.org" Date: Wed, 13 Jul 2016 11:47:22 -0700 Subject: ipq8064: dts: force AP148 SATA port mapping AP148 has a SATA port, but no entity to populate the AHCI Port Implemented register, so force this in DT. Signed-off-by: Thomas Pedersen Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts index d501382493e3..348503d1a1c1 100644 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -95,6 +95,7 @@ }; sata@29000000 { + ports-implemented = <0x1>; status = "ok"; }; }; -- cgit v1.2.3 From b1100d8c31a95efbea087b11d16789e9236a4436 Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 29 Jul 2016 11:39:06 +0530 Subject: ARM: dts: qcom: Add initial DTS for LG Nexus 5 Phone This DTS file have support LG Nexus 5 (codenamed hammerhead). Initial version have support for just serial console over headphone jack. Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Mark Rutland Cc: Rob Herring Cc: Russell King Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/Makefile | 1 + .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..2e9a9e58d308 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -603,6 +603,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8960-cdp.dtb \ + qcom-msm8974-lge-nexus5-hammerhead.dtb \ qcom-msm8974-sony-xperia-honami.dtb dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts new file mode 100644 index 000000000000..68f3a8ac42f3 --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -0,0 +1,23 @@ +#include "qcom-msm8974.dtsi" +#include "qcom-pm8841.dtsi" +#include "qcom-pm8941.dtsi" + +/ { + model = "LGE MSM 8974 HAMMERHEAD"; + compatible = "lge,hammerhead", "qcom,msm8974"; + + aliases { + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&soc { + serial@f991d000 { + status = "ok"; + }; + +}; -- cgit v1.2.3 From b8066645f6c1783434cc1ef66f57a8f4384dcdcb Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 29 Jul 2016 11:39:09 +0530 Subject: ARM: dts: msm8974-hammerhead: Add regulator nodes for hammerhead Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 203 +++++++++++++++++++++ 1 file changed, 203 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 68f3a8ac42f3..df957cb1f6d3 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -1,6 +1,8 @@ #include "qcom-msm8974.dtsi" #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" +#include +#include / { model = "LGE MSM 8974 HAMMERHEAD"; @@ -13,6 +15,207 @@ chosen { stdout-path = "serial0:115200n8"; }; + + smd { + rpm { + rpm_requests { + pm8841-regulators { + s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + pm8941-regulators { + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + regulator-always-on; + regulator-boot-on; + }; + + s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + + regulator-boot-on; + }; + + s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + + regulator-always-on; + regulator-boot-on; + }; + + l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + l3 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-boot-on; + }; + + l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + l11 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + }; + + l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-always-on; + regulator-boot-on; + }; + + l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + l19 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-boot-on; + }; + + l22 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3300000>; + }; + + l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + + regulator-boot-on; + }; + }; + }; + }; + }; }; &soc { -- cgit v1.2.3 From f7af7de89fd50cc2d7aa092bb9a5e61654d65850 Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 29 Jul 2016 11:39:10 +0530 Subject: ARM: dts: msm8974-hammerhead: Introduce gpio-keys nodes This introduces the gpio-keys node for keys of hammerhead and pinctrl state associated with it. Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../dts/qcom-msm8974-lge-nexus5-hammerhead.dts | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index df957cb1f6d3..c0fb4a698c56 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -2,6 +2,7 @@ #include "qcom-pm8841.dtsi" #include "qcom-pm8941.dtsi" #include +#include #include / { @@ -223,4 +224,39 @@ status = "ok"; }; + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pin_a>; + + volume-up { + label = "volume_up"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + + volume-down { + label = "volume_down"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + }; + }; +}; + +&spmi_bus { + pm8941@0 { + gpios@c000 { + gpio_keys_pin_a: gpio-keys-active { + pins = "gpio2", "gpio3"; + function = "normal"; + + bias-pull-up; + power-source = ; + }; + }; + }; }; -- cgit v1.2.3 From ca88696e8b73a9fa2b1de445747e9235c3a7bd50 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 5 Aug 2016 10:38:37 +0200 Subject: ARM: dts: MSM8064 remove flags from SPMI/MPP IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Qualcomm PMIC GPIO and MPP lines are problematic: the are fetched from the main MFD driver with platform_get_irq() which means that at this point they will all be assigned the flags set up for the interrupts in the device tree. That is problematic since these are flagged as rising edge and an this point the interrupt descriptor is assigned a rising edge, while the only thing the GPIO/MPP drivers really do is issue irq_get_irqchip_state() on the line to read it out and to provide a .to_irq() helper for *other* IRQ consumers. If another device tree node tries to flag the same IRQ for use as something else than rising edge, the kernel irqdomain core will protest like this: type mismatch, failed to map hwirq-NN for ! Which is what happens when the device tree defines two contradictory flags for the same interrupt line. To work around this and alleviate the problem, assign 0 as flag for the interrupts taken by the PM GPIO and MPP drivers. This will lead to the flag being unset, and a second consumer requesting rising, falling, both or level interrupts will be respected. This is what the qcom-pm*.dtsi files already do. Switched to using the symbolic name IRQ_TYPE_NONE so that we get this more readable. Cc: stable@vger.kernel.org Fixes: bce360469676 ("ARM: dts: apq8064: add pm8921 mpp support") Fixes: 874443fe9e33 ("ARM: dts: apq8064: Add pm8921 mfd and its gpio node") Cc: Srinivas Kandagatla Cc: Stephen Boyd Cc: Björn Andersson Cc: Ivan T. Ivanov Cc: John Stultz Cc: Andy Gross Signed-off-by: Linus Walleij Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064.dtsi | 76 +++++++++++++++++++++++++++---------- 1 file changed, 57 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index e9aaeb257422..7e43416e250f 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -5,6 +5,7 @@ #include #include #include +#include #include / { model = "Qualcomm APQ8064"; @@ -559,22 +560,50 @@ compatible = "qcom,pm8921-gpio", "qcom,ssbi-gpio"; reg = <0x150>; - interrupts = <192 1>, <193 1>, <194 1>, - <195 1>, <196 1>, <197 1>, - <198 1>, <199 1>, <200 1>, - <201 1>, <202 1>, <203 1>, - <204 1>, <205 1>, <206 1>, - <207 1>, <208 1>, <209 1>, - <210 1>, <211 1>, <212 1>, - <213 1>, <214 1>, <215 1>, - <216 1>, <217 1>, <218 1>, - <219 1>, <220 1>, <221 1>, - <222 1>, <223 1>, <224 1>, - <225 1>, <226 1>, <227 1>, - <228 1>, <229 1>, <230 1>, - <231 1>, <232 1>, <233 1>, - <234 1>, <235 1>; - + interrupts = <192 IRQ_TYPE_NONE>, + <193 IRQ_TYPE_NONE>, + <194 IRQ_TYPE_NONE>, + <195 IRQ_TYPE_NONE>, + <196 IRQ_TYPE_NONE>, + <197 IRQ_TYPE_NONE>, + <198 IRQ_TYPE_NONE>, + <199 IRQ_TYPE_NONE>, + <200 IRQ_TYPE_NONE>, + <201 IRQ_TYPE_NONE>, + <202 IRQ_TYPE_NONE>, + <203 IRQ_TYPE_NONE>, + <204 IRQ_TYPE_NONE>, + <205 IRQ_TYPE_NONE>, + <206 IRQ_TYPE_NONE>, + <207 IRQ_TYPE_NONE>, + <208 IRQ_TYPE_NONE>, + <209 IRQ_TYPE_NONE>, + <210 IRQ_TYPE_NONE>, + <211 IRQ_TYPE_NONE>, + <212 IRQ_TYPE_NONE>, + <213 IRQ_TYPE_NONE>, + <214 IRQ_TYPE_NONE>, + <215 IRQ_TYPE_NONE>, + <216 IRQ_TYPE_NONE>, + <217 IRQ_TYPE_NONE>, + <218 IRQ_TYPE_NONE>, + <219 IRQ_TYPE_NONE>, + <220 IRQ_TYPE_NONE>, + <221 IRQ_TYPE_NONE>, + <222 IRQ_TYPE_NONE>, + <223 IRQ_TYPE_NONE>, + <224 IRQ_TYPE_NONE>, + <225 IRQ_TYPE_NONE>, + <226 IRQ_TYPE_NONE>, + <227 IRQ_TYPE_NONE>, + <228 IRQ_TYPE_NONE>, + <229 IRQ_TYPE_NONE>, + <230 IRQ_TYPE_NONE>, + <231 IRQ_TYPE_NONE>, + <232 IRQ_TYPE_NONE>, + <233 IRQ_TYPE_NONE>, + <234 IRQ_TYPE_NONE>, + <235 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; @@ -587,9 +616,18 @@ gpio-controller; #gpio-cells = <2>; interrupts = - <128 1>, <129 1>, <130 1>, <131 1>, - <132 1>, <133 1>, <134 1>, <135 1>, - <136 1>, <137 1>, <138 1>, <139 1>; + <128 IRQ_TYPE_NONE>, + <129 IRQ_TYPE_NONE>, + <130 IRQ_TYPE_NONE>, + <131 IRQ_TYPE_NONE>, + <132 IRQ_TYPE_NONE>, + <133 IRQ_TYPE_NONE>, + <134 IRQ_TYPE_NONE>, + <135 IRQ_TYPE_NONE>, + <136 IRQ_TYPE_NONE>, + <137 IRQ_TYPE_NONE>, + <138 IRQ_TYPE_NONE>, + <139 IRQ_TYPE_NONE>; }; rtc@11d { -- cgit v1.2.3 From dcf5907e0e09a160a57160729f920add5df8e358 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 5 Aug 2016 10:38:38 +0200 Subject: ARM: dts: MSM8660 remove flags from SPMI/MPP IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Qualcomm SPMI GPIO and MPP lines are problematic: the are fetched from the main MFD driver with platform_get_irq() which means that at this point they will all be assigned the flags set up for the interrupts in the device tree. That is problematic since these are flagged as rising edge and an this point the interrupt descriptor is assigned a rising edge, while the only thing the GPIO/MPP drivers really do is issue irq_get_irqchip_state() on the line to read it out and to provide a .to_irq() helper for *other* IRQ consumers. If another device tree node tries to flag the same IRQ for use as something else than rising edge, the kernel irqdomain core will protest like this: type mismatch, failed to map hwirq-NN for ! Which is what happens when the device tree defines two contradictory flags for the same interrupt line. To work around this and alleviate the problem, assign 0 as flag for the interrupts taken by the PM GPIO and MPP drivers. This will lead to the flag being unset, and a second consumer requesting rising, falling, both or level interrupts will be respected. This is what the qcom-pm*.dtsi files already do. Switched to using the symbolic name IRQ_TYPE_NONE so that we get this more readable. This misconfiguration was caused by a copy/pasting the APQ8064 set-up, the latter has been fixed in a separate patch. Tested with one of the SPMI GPIOs: after this I can successfully request one of these GPIOs as falling edge from the device tree. Fixes: 0840ea9e4457 ("ARM: dts: add GPIO and MPP to MSM8660 PMIC") Cc: Srinivas Kandagatla Cc: Stephen Boyd Cc: Björn Andersson Cc: Ivan T. Ivanov Cc: John Stultz Cc: Andy Gross Signed-off-by: Linus Walleij Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8660.dtsi | 75 ++++++++++++++++++++++++++++--------- 1 file changed, 57 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index acbe71febe13..8c65e0d82559 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include #include #include #include @@ -159,21 +160,50 @@ "qcom,ssbi-gpio"; reg = <0x150>; interrupt-parent = <&pmicintc>; - interrupts = <192 1>, <193 1>, <194 1>, - <195 1>, <196 1>, <197 1>, - <198 1>, <199 1>, <200 1>, - <201 1>, <202 1>, <203 1>, - <204 1>, <205 1>, <206 1>, - <207 1>, <208 1>, <209 1>, - <210 1>, <211 1>, <212 1>, - <213 1>, <214 1>, <215 1>, - <216 1>, <217 1>, <218 1>, - <219 1>, <220 1>, <221 1>, - <222 1>, <223 1>, <224 1>, - <225 1>, <226 1>, <227 1>, - <228 1>, <229 1>, <230 1>, - <231 1>, <232 1>, <233 1>, - <234 1>, <235 1>; + interrupts = <192 IRQ_TYPE_NONE>, + <193 IRQ_TYPE_NONE>, + <194 IRQ_TYPE_NONE>, + <195 IRQ_TYPE_NONE>, + <196 IRQ_TYPE_NONE>, + <197 IRQ_TYPE_NONE>, + <198 IRQ_TYPE_NONE>, + <199 IRQ_TYPE_NONE>, + <200 IRQ_TYPE_NONE>, + <201 IRQ_TYPE_NONE>, + <202 IRQ_TYPE_NONE>, + <203 IRQ_TYPE_NONE>, + <204 IRQ_TYPE_NONE>, + <205 IRQ_TYPE_NONE>, + <206 IRQ_TYPE_NONE>, + <207 IRQ_TYPE_NONE>, + <208 IRQ_TYPE_NONE>, + <209 IRQ_TYPE_NONE>, + <210 IRQ_TYPE_NONE>, + <211 IRQ_TYPE_NONE>, + <212 IRQ_TYPE_NONE>, + <213 IRQ_TYPE_NONE>, + <214 IRQ_TYPE_NONE>, + <215 IRQ_TYPE_NONE>, + <216 IRQ_TYPE_NONE>, + <217 IRQ_TYPE_NONE>, + <218 IRQ_TYPE_NONE>, + <219 IRQ_TYPE_NONE>, + <220 IRQ_TYPE_NONE>, + <221 IRQ_TYPE_NONE>, + <222 IRQ_TYPE_NONE>, + <223 IRQ_TYPE_NONE>, + <224 IRQ_TYPE_NONE>, + <225 IRQ_TYPE_NONE>, + <226 IRQ_TYPE_NONE>, + <227 IRQ_TYPE_NONE>, + <228 IRQ_TYPE_NONE>, + <229 IRQ_TYPE_NONE>, + <230 IRQ_TYPE_NONE>, + <231 IRQ_TYPE_NONE>, + <232 IRQ_TYPE_NONE>, + <233 IRQ_TYPE_NONE>, + <234 IRQ_TYPE_NONE>, + <235 IRQ_TYPE_NONE>; gpio-controller; #gpio-cells = <2>; @@ -187,9 +217,18 @@ #gpio-cells = <2>; interrupt-parent = <&pmicintc>; interrupts = - <128 1>, <129 1>, <130 1>, <131 1>, - <132 1>, <133 1>, <134 1>, <135 1>, - <136 1>, <137 1>, <138 1>, <139 1>; + <128 IRQ_TYPE_NONE>, + <129 IRQ_TYPE_NONE>, + <130 IRQ_TYPE_NONE>, + <131 IRQ_TYPE_NONE>, + <132 IRQ_TYPE_NONE>, + <133 IRQ_TYPE_NONE>, + <134 IRQ_TYPE_NONE>, + <135 IRQ_TYPE_NONE>, + <136 IRQ_TYPE_NONE>, + <137 IRQ_TYPE_NONE>, + <138 IRQ_TYPE_NONE>, + <139 IRQ_TYPE_NONE>; }; pwrkey@1c { -- cgit v1.2.3 From c03a4b24c355bce7758d75ca3a7aad18a8cbefa2 Mon Sep 17 00:00:00 2001 From: John Stultz Date: Mon, 8 Aug 2016 15:34:03 -0700 Subject: device-tree: nexus7: Add IMEM syscon and reboot reason support This patch add the IMEM syscon memory region to the DT, as well as addds support for the magic reboot reason values that are written to the address for each mode. Cc: Rob Herring Cc: Andy Gross Cc: Bjorn Andersson Cc: Stephen Boyd Cc: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index 94e9cbbc6122..b72e09506448 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -273,5 +273,19 @@ vqmmc-supply = <&pm8921_s4>; }; }; + + imem@2a03f000 { + compatible = "syscon", "simple-mfd"; + reg = <0x2a03f000 0x1000>; + + reboot-mode { + compatible = "syscon-reboot-mode"; + offset = <0x65c>; + + mode-normal = <0x77665501>; + mode-bootloader = <0x77665500>; + mode-recovery = <0x77665502>; + }; + }; }; }; -- cgit v1.2.3 From 05b01dd936b46f2c3cfbb10bc89c0ec79c745e5d Mon Sep 17 00:00:00 2001 From: Milo Kim Date: Wed, 24 Aug 2016 22:07:16 +0900 Subject: ARM: dts: exynos: Use 'hpd-gpios' instead of 'hpd-gpio' This patch enables getting a HPD GPIO descriptor quicker. The exynos-hdmi driver uses "hpd" for HDMI hot plug detection. static int hdmi_resources_init(struct hdmi_context *hdata) { ... hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); ... } This calls 'of_find_gpio()' and it generates the GPIO consumer ID by referring GPIO suffix. So 'hpd-gpios' is preferred on getting a GPIO descriptor. However, if the device tree uses 'hpd-gpio', then the exynos-hdmi driver always retries to get a GPIO descriptor because the first GPIO suffix is not 'gpio' but 'gpios'. So you always see the debug message below. of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/soc/hdmi@14530000[0]' Use the preferred property, 'hpd-gpios' instead of 'hpd-gpio'. Acked-by: Rob Herring Reviewed-by: Andrzej Hajda Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Milo Kim Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt | 4 ++-- arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 2 +- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 2 +- arch/arm/boot/dts/exynos5250-spring.dts | 2 +- arch/arm/boot/dts/exynos5420-peach-pit.dts | 2 +- arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 2 +- 11 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt index a2ec4c1c9382..6394ea9e3b9e 100644 --- a/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt +++ b/Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt @@ -9,7 +9,7 @@ Required properties: - reg: physical base address of the hdmi and length of memory mapped region. - interrupts: interrupt number to the cpu. -- hpd-gpio: following information about the hotplug gpio pin. +- hpd-gpios: following information about the hotplug gpio pin. a) phandle of the gpio controller node. b) pin number within the gpio controller. c) optional flags and pull up/down. @@ -56,7 +56,7 @@ Example: compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x100000>; interrupts = <0 95 0>; - hpd-gpio = <&gpx3 7 1>; + hpd-gpios = <&gpx3 7 1>; ddc = <&hdmi_ddc_node>; phy = <&hdmi_phy_node>; samsung,syscon-phandle = <&pmu_system_controller>; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9a75e3effbc9..cf95202fa310 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -269,7 +269,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd>; hdmi-en-supply = <&hdmi_en>; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 58ad48e7b8f7..be644fe6a0fd 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -227,7 +227,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd>; vdd-supply = <&ldo8_reg>; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index ea70603f660d..3d981f32874d 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -152,7 +152,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_LOW>; vdd_osc-supply = <&ldo10_reg>; vdd_pll-supply = <&ldo8_reg>; vdd-supply = <&ldo8_reg>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 381af134c4c8..7f27263728a1 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -116,7 +116,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; }; &i2c_0 { diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index fadbea744e1a..1055d25c0ccc 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -260,7 +260,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; phy = <&hdmiphy>; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 44f4292bfef6..1d52a79b2f18 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -91,7 +91,7 @@ }; &hdmi { - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; phy = <&hdmiphy>; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index fe4e0915c0c6..f6f256fd9b5e 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -179,7 +179,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index ed8f3426911b..29546465d3da 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -130,7 +130,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d04490d40b07..7bb8a370072a 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -250,7 +250,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 5ec71e2400fd..51a8bca4691c 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -179,7 +179,7 @@ &hdmi { status = "okay"; - hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; -- cgit v1.2.3 From 33145fac8e7e9eb0e064cd0cd0032d6786b6420c Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 Aug 2016 15:09:59 +0000 Subject: ARM: dts: bcm283x: Add missing USB clock According to the DWC2 binding an appropriate clock is required. This clock isn't handled by bcm2835 clock driver, so add a fixed clock to the bcm283x DT. Signed-off-by: Stefan Wahren Acked-by: Stephen Warren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm283x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index b98252232d20..547280088299 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -289,6 +289,8 @@ interrupts = <1 9>; #address-cells = <1>; #size-cells = <0>; + clocks = <&clk_usb>; + clock-names = "otg"; }; v3d: v3d@7ec00000 { @@ -316,5 +318,12 @@ clock-frequency = <19200000>; }; + clk_usb: clock@4 { + compatible = "fixed-clock"; + reg = <4>; + #clock-cells = <0>; + clock-output-names = "otg"; + clock-frequency = <480000000>; + }; }; }; -- cgit v1.2.3 From 00a33ec4649e059dfcf81d0f90402fb02db50691 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 Aug 2016 15:10:00 +0000 Subject: ARM: dts: bcm283x: Add dtsi for USB host mode In case dr_mode isn't passed via DT, the dwc2 defaults to OTG mode. But all Raspberry Pi boards here are designed only for host mode. So fix this issue by providing a dtsi file which set the dr_mode to host. Signed-off-by: Stefan Wahren Acked-by: Stephen Warren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/bcm2835-rpi-a-plus.dts | 1 + arch/arm/boot/dts/bcm2835-rpi-a.dts | 1 + arch/arm/boot/dts/bcm2835-rpi-b-plus.dts | 1 + arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts | 1 + arch/arm/boot/dts/bcm2835-rpi-b.dts | 1 + arch/arm/boot/dts/bcm2836-rpi-2-b.dts | 1 + arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi | 3 +++ 7 files changed, 9 insertions(+) create mode 100644 arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index 35ff4e7a4aac..f7f9db355d98 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-a-plus", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 306a84ee9898..8be102f5d826 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -1,6 +1,7 @@ /dts-v1/; #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-a", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index d5fdb8e761a3..35cde65c975e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index bfc4bd9b7733..84df85ea6296 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 0371bb7374b8..8e626a80fe24 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -2,6 +2,7 @@ #include "bcm2835.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9512.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 29e1cfe8eb14..39dccf62ac96 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -2,6 +2,7 @@ #include "bcm2836.dtsi" #include "bcm2835-rpi.dtsi" #include "bcm283x-rpi-smsc9514.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" / { compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; diff --git a/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi b/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi new file mode 100644 index 000000000000..73f4ece8dcd0 --- /dev/null +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-host.dtsi @@ -0,0 +1,3 @@ +&usb { + dr_mode = "host"; +}; -- cgit v1.2.3 From 33fdf6fd764ed7deea87094f30d7d3dc76e154de Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Tue, 26 Jul 2016 18:53:32 +0000 Subject: DT: bindings: bcm: Add Raspberry Pi Zero Signed-off-by: Stefan Wahren Acked-by: Rob Herring Acked-by: Stephen Warren Signed-off-by: Eric Anholt --- Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt index 6ffe08778465..9c97de23919a 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt @@ -38,6 +38,10 @@ Raspberry Pi Compute Module Required root node properties: compatible = "raspberrypi,compute-module", "brcm,bcm2835"; +Raspberry Pi Zero +Required root node properties: +compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + Generic BCM2835 board Required root node properties: compatible = "brcm,bcm2835"; -- cgit v1.2.3 From c8336249c1eeca288919e3286f7dd03ae1d8ceae Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sun, 21 Aug 2016 15:10:03 +0000 Subject: ARM: dts: bcm2835: Add Raspberry Pi Zero The Raspberry Pi Zero is a minified version of model A+. It's notable there is no PWR LED and the ACT LED is inverted. Additionally the Pi Zero is capable of the USB peripheral mode. Signed-off-by: Stefan Wahren Acked-by: Stephen Warren Signed-off-by: Eric Anholt --- arch/arm/boot/dts/Makefile | 3 ++- arch/arm/boot/dts/bcm2835-rpi-zero.dts | 40 ++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/bcm2835-rpi-zero.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..6576e3f000c9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -69,7 +69,8 @@ dtb-$(CONFIG_ARCH_BCM2835) += \ bcm2835-rpi-b-rev2.dtb \ bcm2835-rpi-b-plus.dtb \ bcm2835-rpi-a-plus.dtb \ - bcm2836-rpi-2-b.dtb + bcm2836-rpi-2-b.dtb \ + bcm2835-rpi-zero.dtb dtb-$(CONFIG_ARCH_BCM_5301X) += \ bcm4708-asus-rt-ac56u.dtb \ bcm4708-asus-rt-ac68u.dtb \ diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts new file mode 100644 index 000000000000..60e359fafc5b --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 Stefan Wahren + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "bcm2835.dtsi" +#include "bcm2835-rpi.dtsi" +#include "bcm283x-rpi-usb-host.dtsi" + +/ { + compatible = "raspberrypi,model-zero", "brcm,bcm2835"; + model = "Raspberry Pi Zero"; + + leds { + act { + gpios = <&gpio 47 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpio { + pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = ; + }; +}; + +&hdmi { + hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; +}; -- cgit v1.2.3 From d7b843df13ea3a19580bf5eb109b1fa5a89a338c Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Tue, 23 Aug 2016 21:55:46 +0800 Subject: ARM: dts: sun8i: add NAND controller node for A23/A33 A23/A33 has a NAND controller which can now be used properly. Add a device node for it. The DMA function cannot work because of changed DMA IP block, so it's temporarily removed in the device node. However, with PIO mode it can still work. Tested on an Aoson M751s tablet with Boris Brezillon's "mtd: nand: allow vendor specific detection/initialization" patchset, which is needed for the large-block MLC chip to be recognized correctly. ( http://lists.infradead.org/pipermail/linux-mtd/2016-June/068198.html ) Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 7e05e09e61c7..6d6509c71009 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -239,6 +239,14 @@ "mmc2_sample"; }; + nand_clk: clk@01c20080 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20080 0x4>; + clocks = <&osc24M>, <&pll6 1>; + clock-output-names = "nand"; + }; + usb_clk: clk@01c200cc { #clock-cells = <1>; #reset-cells = <1>; @@ -322,6 +330,19 @@ #size-cells = <0>; }; + nfc: nand@01c03000 { + compatible = "allwinner,sun4i-a10-nand"; + reg = <0x01c03000 0x1000>; + interrupts = ; + clocks = <&ahb1_gates 13>, <&nand_clk>; + clock-names = "ahb", "mod"; + resets = <&ahb1_rst 13>; + reset-names = "ahb"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ehci0: usb@01c1a000 { compatible = "allwinner,sun8i-a23-ehci", "generic-ehci"; reg = <0x01c1a000 0x100>; -- cgit v1.2.3 From 7e84a8d13f97aa4487371c39e2b8918883e0ce3a Mon Sep 17 00:00:00 2001 From: Jason Cooper Date: Mon, 15 Aug 2016 14:51:04 +0000 Subject: ARM: dts: kirkwood: Fix Openblock A6 external GPIO pins By assigning the pin hog to the pinctrl node, we correctly configure the MPPs. However, they are not available to userspace. Fix this by assigning the hogs to the gpio node. After this, the following works as expected: # echo 28 >/sys/class/gpio/export # echo low >/sys/class/gpio/gpio28/direction [gregory.clement@free-electrons.com: fix title] Signed-off-by: Jason Cooper Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/kirkwood-openblocks_a6.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts index 0db0e3edc88f..94e49f32d5f9 100644 --- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts @@ -41,7 +41,7 @@ }; pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>; + pinctrl-0 = <&pmx_dip_switches>; pinctrl-names = "default"; pmx_uart0: pmx-uart0 { @@ -174,3 +174,10 @@ phy-handle = <ðphy0>; }; }; + +&gpio0 { + status = "okay"; + + pinctrl-0 = <&pmx_gpio_header>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From 4c0437d03519c0e32ee3aceda63a7087c9bc1022 Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 24 Aug 2016 11:21:15 +1200 Subject: ARM: dts: armada-38x: Add NAND pinctrl information Add pin control information for the NAND flash interface. This interface is multiplexed with the device bus interface to the function is "dev" not "nand" as one might expect. Signed-off-by: Chris Packham Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-38x.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index c065ecd8d36b..2d7668848c5a 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -263,6 +263,15 @@ marvell,function = "spi1"; }; + nand_pins: nand-pins { + marvell,pins = "mpp22", "mpp34", "mpp23", + "mpp33", "mpp38", "mpp28", + "mpp40", "mpp42", "mpp35", + "mpp36", "mpp25", "mpp30", + "mpp32"; + marvell,function = "dev"; + }; + uart0_pins: uart-pins-0 { marvell,pins = "mpp0", "mpp1"; marvell,function = "ua0"; -- cgit v1.2.3 From 996453571b33ba2ae07211ff9e8a09b28e49aec5 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 24 Aug 2016 22:22:22 +0300 Subject: ARM: dts: blanche: add support for general purpose LEDs Add support for the general purpose LEDs on the Blanche board. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index 3c6f42b9fe9f..f3ea43b7b724 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -159,6 +159,23 @@ }; }; + leds { + compatible = "gpio-leds"; + + led17 { + gpios = <&gpio10 10 GPIO_ACTIVE_HIGH>; + }; + led18 { + gpios = <&gpio10 11 GPIO_ACTIVE_HIGH>; + }; + led19 { + gpios = <&gpio10 12 GPIO_ACTIVE_HIGH>; + }; + led20 { + gpios = <&gpio10 23 GPIO_ACTIVE_HIGH>; + }; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; -- cgit v1.2.3 From 1bc5e139c3eee50171ebb0ad95c6d00d57eba520 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Thu, 11 Aug 2016 10:57:48 +0530 Subject: ARM: dts: AM437X-GP-EVM: AM437X-SK-EVM: Make dcdc3 dcdc5 and dcdc6 enable during suspend dcdc3, dcdc5, dcdc6 supply ddr and rtc respectively. These are required to be on during suspend. Hence set the state accordingly. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 10 ++++++++++ arch/arm/boot/dts/am437x-sk-evm.dts | 27 +++++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 128dbefa77e7..94122de9df72 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -537,7 +537,11 @@ regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; + dcdc5: regulator-dcdc5 { compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; @@ -545,6 +549,9 @@ regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; dcdc6: regulator-dcdc6 { @@ -554,6 +561,9 @@ regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; ldo1: regulator-ldo1 { diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 23e7c9ecb76f..4440b689bd95 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -454,6 +454,9 @@ regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; }; dcdc4: regulator-dcdc4 { @@ -465,6 +468,30 @@ regulator-always-on; }; + dcdc5: regulator-dcdc5 { + compatible = "ti,tps65218-dcdc5"; + regulator-name = "v1_0bat"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + dcdc6: regulator-dcdc6 { + compatible = "ti,tps65218-dcdc6"; + regulator-name = "v1_8bat"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + ldo1: regulator-ldo1 { compatible = "ti,tps65218-ldo1"; regulator-name = "v1_8d"; -- cgit v1.2.3 From 7ec3299175405d694e6c4f97b7136ea4f1f018f5 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 11 Aug 2016 10:57:49 +0530 Subject: ARM: dts: am437x-gp-evm: disable DDR regulator in rtc-only/poweroff mode Without this, the memory will remain active during poweroff consuming extra power. Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 94122de9df72..5bcda26f8626 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -540,6 +540,9 @@ regulator-state-mem { regulator-on-in-suspend; }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; dcdc5: regulator-dcdc5 { -- cgit v1.2.3 From 5a9009f3d6615907683bcaf25e26c4ba73dec320 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 11 Aug 2016 10:57:50 +0530 Subject: ARM: dts: am437x-sk-evm: disable DDR regulator in rtc-only/poweroff mode Without this, the memory will remain active during poweroff consuming extra power. Please note revision 2.1 PMIC seems to fail when DCDC3 disable is attempted, so this is not done on that PMIC revision. The PMIC revision checks in the regulator patches make sure of this. Signed-off-by: Tero Kristo Signed-off-by: Dave Gerlach Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-sk-evm.dts | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 4440b689bd95..2676cfd38f39 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -457,6 +457,9 @@ regulator-state-mem { regulator-on-in-suspend; }; + regulator-state-disk { + regulator-off-in-suspend; + }; }; dcdc4: regulator-dcdc4 { -- cgit v1.2.3 From b9db016a46e734d1d21e0576084143b23f742ff4 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 4 Jul 2016 15:25:10 +0530 Subject: ARM: dts: AM437X-GP-EVM: Remove redundant regulator compatibles With the device tree parsing using the regulator framework there is a no longer a need for separate compatibles for individual regulator nodes. Hence removing them all. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-gp-evm.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index 5bcda26f8626..957840cc7b78 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -513,7 +513,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -522,7 +521,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -531,7 +529,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; @@ -546,7 +543,6 @@ }; dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -558,7 +554,6 @@ }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -570,7 +565,6 @@ }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From c332f79e25545731496f05cd99e1f5c7367b75ca Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 4 Jul 2016 15:25:11 +0530 Subject: ARM: dts: AM437X-SK-EVM: Remove redundant regulator compatibles With the device tree parsing using the regulator framework there is a no longer a need for separate compatibles for individual regulator nodes. Hence removing them all. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-sk-evm.dts | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 2676cfd38f39..319d94205350 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -428,7 +428,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; /* VDD_CORE limits min of OPP50 and max of OPP100 */ regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; @@ -438,7 +437,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; @@ -448,7 +446,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdds_ddr"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; @@ -463,7 +460,6 @@ }; dcdc4: regulator-dcdc4 { - compatible = "ti,tps65218-dcdc4"; regulator-name = "v3_3d"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -496,7 +492,6 @@ }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-name = "v1_8d"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; -- cgit v1.2.3 From 77c09a9e5529febe7d2f72ebb942941a9e16f63c Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 4 Jul 2016 15:25:12 +0530 Subject: ARM: dts: AM437X-CM-T43: Remove redundant regulator compatibles With the device tree parsing using the regulator framework there is a no longer a need for separate compatibles for individual regulator nodes. Hence removing them all. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am437x-cm-t43.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts index 9551c4713173..9e92d480576b 100644 --- a/arch/arm/boot/dts/am437x-cm-t43.dts +++ b/arch/arm/boot/dts/am437x-cm-t43.dts @@ -209,7 +209,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -218,7 +217,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -227,7 +225,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-suspend-enable; regulator-min-microvolt = <1500000>; @@ -237,7 +234,6 @@ }; dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; @@ -246,7 +242,6 @@ }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -255,7 +250,6 @@ }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From 9860f7e920ff812ea580bb4871d3e117e2a81c28 Mon Sep 17 00:00:00 2001 From: Keerthy Date: Mon, 4 Jul 2016 15:25:13 +0530 Subject: ARM: dts: AM43X-EPOS-EVM: Remove redundant regulator compatibles With the device tree parsing using the regulator framework there is a no longer a need for separate compatibles for individual regulator nodes. Hence removing them all. Signed-off-by: Keerthy Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am43x-epos-evm.dts | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index a44580248571..9d35c3f07cad 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -421,7 +421,6 @@ #interrupt-cells = <2>; dcdc1: regulator-dcdc1 { - compatible = "ti,tps65218-dcdc1"; regulator-name = "vdd_core"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1144000>; @@ -430,7 +429,6 @@ }; dcdc2: regulator-dcdc2 { - compatible = "ti,tps65218-dcdc2"; regulator-name = "vdd_mpu"; regulator-min-microvolt = <912000>; regulator-max-microvolt = <1378000>; @@ -439,7 +437,6 @@ }; dcdc3: regulator-dcdc3 { - compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; regulator-min-microvolt = <1500000>; regulator-max-microvolt = <1500000>; @@ -448,7 +445,6 @@ }; dcdc4: regulator-dcdc4 { - compatible = "ti,tps65218-dcdc4"; regulator-name = "vdcdc4"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -457,21 +453,18 @@ }; dcdc5: regulator-dcdc5 { - compatible = "ti,tps65218-dcdc5"; regulator-name = "v1_0bat"; regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; }; dcdc6: regulator-dcdc6 { - compatible = "ti,tps65218-dcdc6"; regulator-name = "v1_8bat"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; ldo1: regulator-ldo1 { - compatible = "ti,tps65218-ldo1"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; -- cgit v1.2.3 From a0b83af0dfd751f88bf5c452e7bbe7efe877da3d Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Mon, 1 Aug 2016 18:36:55 +0530 Subject: ARM: dts: dra7xx: Increase spi-max-frequency to 76.8MHz for QSPI According to AM572x DM SPRS953A, QSPI maximum bus speed can be 76.8MHz. Therefore, increase the spi-max-frequency value of QSPI node to 76.8MHz for DRA74 and DRA72 evm. This improves flash raw read speed by ~2MB/s. Signed-off-by: Vignesh R Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 4 ++-- arch/arm/boot/dts/dra72-evm-common.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index d47c8739bdaa..3350722e10b7 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -664,10 +664,10 @@ &qspi { status = "okay"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi index 9d3cf50ca37e..c94d8d64710d 100644 --- a/arch/arm/boot/dts/dra72-evm-common.dtsi +++ b/arch/arm/boot/dts/dra72-evm-common.dtsi @@ -681,10 +681,10 @@ &qspi { status = "okay"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; m25p80@0 { compatible = "s25fl256s1"; - spi-max-frequency = <64000000>; + spi-max-frequency = <76800000>; reg = <0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <4>; -- cgit v1.2.3 From 504482e565ba85eb3da73ddc57acfc05d10e7db6 Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Tue, 2 Aug 2016 10:51:47 +0530 Subject: ARM: dts: am57xx-idk-common: Enable support for QSPI AM572x IDK has a Spansion s25fl256s1 QSPI flash on the EVM connected to TI QSPI IP over CS0. Hence, add QSPI and flash slave DT nodes. Signed-off-by: Vignesh R Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-idk-common.dtsi | 49 ++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi index 0e63b9dff6e7..03cec62260e1 100644 --- a/arch/arm/boot/dts/am57xx-idk-common.dtsi +++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi @@ -304,3 +304,52 @@ ti,non-removable; max-frequency = <96000000>; }; + +&qspi { + status = "okay"; + + spi-max-frequency = <76800000>; + m25p80@0 { + compatible = "s25fl256s1", "jedec,spi-nor"; + spi-max-frequency = <76800000>; + reg = <0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + #address-cells = <1>; + #size-cells = <1>; + + /* MTD partition table. + * The ROM checks the first four physical blocks + * for a valid file to boot and the flash here is + * 64KiB block size. + */ + partition@0 { + label = "QSPI.SPL"; + reg = <0x00000000 0x000040000>; + }; + partition@1 { + label = "QSPI.u-boot"; + reg = <0x00040000 0x00100000>; + }; + partition@2 { + label = "QSPI.u-boot-spl-os"; + reg = <0x00140000 0x00080000>; + }; + partition@3 { + label = "QSPI.u-boot-env"; + reg = <0x001c0000 0x00010000>; + }; + partition@4 { + label = "QSPI.u-boot-env.backup1"; + reg = <0x001d0000 0x0010000>; + }; + partition@5 { + label = "QSPI.kernel"; + reg = <0x001e0000 0x0800000>; + }; + partition@6 { + label = "QSPI.file-system"; + reg = <0x009e0000 0x01620000>; + }; + }; +}; -- cgit v1.2.3 From 316ba624f150815e5f993d691808968561b42848 Mon Sep 17 00:00:00 2001 From: Stefan Müller-Klieser Date: Wed, 10 Aug 2016 17:12:15 +0200 Subject: ARM: dts: am335x-wega: Add audio support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The wega board has a TLV320AIC3007 connected via McASP0. In the default configuration, no external crystal is mounted. We run a system clock of 25 MHz, so we use the audio codec PLL for audio clock generation. Signed-off-by: Stefan Müller-Klieser Reviewed-by: Peter Ujfalusi Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-wega.dtsi | 62 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/am335x-wega.dtsi b/arch/arm/boot/dts/am335x-wega.dtsi index d5fdf6244af8..02c67365c4e1 100644 --- a/arch/arm/boot/dts/am335x-wega.dtsi +++ b/arch/arm/boot/dts/am335x-wega.dtsi @@ -11,6 +11,10 @@ model = "Phytec AM335x phyBOARD-WEGA"; compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx"; + sound: sound_iface { + compatible = "ti,da830-evm-audio"; + }; + regulators { compatible = "simple-bus"; @@ -24,6 +28,58 @@ }; }; +/* Audio */ +&am33xx_pinmux { + mcasp0_pins: pinmux_mcasp0 { + pinctrl-single,pins = < + AM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */ + AM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */ + AM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */ + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */ + AM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */ + >; + }; +}; + +&i2c0 { + tlv320aic3007: tlv320aic3007@18 { + compatible = "ti,tlv320aic3007"; + reg = <0x18>; + AVDD-supply = <&vcc3v3>; + IOVDD-supply = <&vcc3v3>; + DRVDD-supply = <&vcc3v3>; + DVDD-supply = <&vdig1_reg>; + status = "okay"; + }; +}; + +&mcasp0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */ + tdm-slots = <2>; + serial-dir = < + 2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */ + >; + tx-num-evt = <16>; + rt-num-evt = <16>; + status = "okay"; +}; + +&sound { + ti,model = "AM335x-Wega"; + ti,audio-codec = <&tlv320aic3007>; + ti,mcasp-controller = <&mcasp0>; + ti,audio-routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "LINE1L", "Line In", + "LINE1R", "Line In"; + clocks = <&mcasp0_fck>; + clock-names = "mclk"; + status = "okay"; +}; + /* CAN Busses */ &am33xx_pinmux { dcan1_pins: pinmux_dcan1 { @@ -99,6 +155,12 @@ status = "okay"; }; +/* Power */ +&vdig1_reg { + regulator-boot-on; + regulator-always-on; +}; + /* UARTs */ &am33xx_pinmux { uart0_pins: pinmux_uart0 { -- cgit v1.2.3 From 291f1af53bc0ae67aadeb72a1c1ad675e46e9b01 Mon Sep 17 00:00:00 2001 From: Sekhar Nori Date: Tue, 23 Aug 2016 11:57:41 +0300 Subject: ARM: dts: dra7: workaround silicon limitation i845 Silicon limitation i845 documents how to cope with false disconnection condition on USB2 PHY. Reference: AM572x silicon errata document SPRZ429H, revised January 2016. Using compatible "ti,dra7x-usb2" enables the recommended software workaround for this issue. Use it for USB1 PHY. The workaround is already in place for USB2 PHY. Signed-off-by: Sekhar Nori Signed-off-by: Roger Quadros Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d9bfb94a2992..df0dcbc05b4a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1413,7 +1413,7 @@ ti,hwmods = "ocp2scp1"; usb2_phy1: phy@4a084000 { - compatible = "ti,omap-usb2"; + compatible = "ti,dra7x-usb2", "ti,omap-usb2"; reg = <0x4a084000 0x400>; syscon-phy-power = <&scm_conf 0x300>; clocks = <&usb_phy1_always_on_clk32k>, -- cgit v1.2.3 From 1e03325af6a570ff7e6621b7eb1b3108ca67d8f9 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:52:34 +0200 Subject: ARM: dts: sun8i: Add dt node for esp8089 wifi chip on polaroid-mid2407 The polaroid-mid2407 tablet has an esp8089 wifi chip, add a dt node describing it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index e3004428e7a7..4789aac89955 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -47,4 +47,46 @@ / { model = "Polaroid MID2407PXE03 tablet"; compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2407>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = ; +}; + +&r_pio { + wifi_pwrseq_pin_mid2407: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; }; -- cgit v1.2.3 From b44a0a72dfd5fc5e3194f0c8eeec5b43d33ae792 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:52:35 +0200 Subject: ARM: dts: sun8i: Add dt node for esp8089 wifi chip on polaroid-mid2809 The polaroid-mid2809 tablet has an esp8089 wifi chip, add a dt node describing it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- .../boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index 6d06e24d446b..c9213caf7424 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -47,4 +47,46 @@ / { model = "Polaroid MID2809PXE04 tablet"; compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23"; + + aliases { + ethernet0 = &esp8089; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_mid2809>; + reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL6 */ + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + esp8089: sdio_wifi@1 { + compatible = "esp,esp8089"; + reg = <1>; + esp,crystal-26M-en = <2>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = ; +}; + +&r_pio { + wifi_pwrseq_pin_mid2809: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; }; -- cgit v1.2.3 From 593d5f3a4a25da1f2d974d7ed5f92cd4fe0c8a36 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:42:23 +0200 Subject: ARM: dts: sun4i: Disable ohci1 on ba10-tv-box The ehci1/ohci1 pair on the ba10-tv-box is connected to an USB-2 wifi module soldered on the PCB, so there enabling ohci1 is not necessary. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index f3cb297fd1db..5f98582232d6 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -121,10 +121,6 @@ status = "okay"; }; -&ohci1 { - status = "okay"; -}; - &otg_sram { status = "okay"; }; -- cgit v1.2.3 From 1b09d23d30222988b7871293e36074a87b21ab6b Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:42:24 +0200 Subject: ARM: dts: sun5i: Convert inet-98v-rev2 dts to use reference-design-tablet.dtsi This results in a nice cleanup :) Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts | 164 +------------------------- 1 file changed, 1 insertion(+), 163 deletions(-) diff --git a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts index 1b11ec95ae53..439ae3b537df 100644 --- a/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts +++ b/arch/arm/boot/dts/sun5i-a13-inet-98v-rev2.dts @@ -42,171 +42,9 @@ /dts-v1/; #include "sun5i-a13.dtsi" -#include "sunxi-common-regulators.dtsi" -#include -#include -#include -#include +#include "sun5i-reference-design-tablet.dtsi" / { model = "INet-98V Rev 02"; compatible = "primux,inet98v-rev2", "allwinner,sun5i-a13"; - - aliases { - serial0 = &uart1; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - -}; - -&cpu0 { - cpu-supply = <®_dcdc2>; -}; - -&ehci0 { - status = "okay"; -}; - -&i2c0 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_pins_a>; - status = "okay"; - - axp209: pmic@34 { - reg = <0x34>; - interrupts = <0>; - }; -}; - -#include "axp209.dtsi" - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_a>; - status = "okay"; - - pcf8563: rtc@51 { - compatible = "nxp,pcf8563"; - reg = <0x51>; - }; -}; - -&lradc { - vref-supply = <®_ldo2>; - status = "okay"; - - button@200 { - label = "Volume Up"; - linux,code = ; - channel = <0>; - voltage = <200000>; - }; - - button@400 { - label = "Volume Down"; - linux,code = ; - channel = <0>; - voltage = <400000>; - }; -}; - -&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_inet98fv2>; - vmmc-supply = <®_vcc3v3>; - bus-width = <4>; - cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */ - cd-inverted; - status = "okay"; -}; - -&otg_sram { - status = "okay"; -}; - -&pio { - mmc0_cd_pin_inet98fv2: mmc0_cd_pin@0 { - allwinner,pins = "PG0"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 { - allwinner,pins = "PG1"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; - - usb0_id_detect_pin: usb0_id_detect_pin@0 { - allwinner,pins = "PG2"; - allwinner,function = "gpio_in"; - allwinner,drive = ; - allwinner,pull = ; - }; -}; - -®_dcdc2 { - regulator-always-on; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; - regulator-name = "vdd-cpu"; -}; - -®_dcdc3 { - regulator-always-on; - regulator-min-microvolt = <1250000>; - regulator-max-microvolt = <1250000>; - regulator-name = "vdd-int-pll"; -}; - -®_ldo1 { - regulator-name = "vdd-rtc"; -}; - -®_ldo2 { - regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "avcc"; -}; - -®_ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc-wifi"; -}; - -®_usb0_vbus { - gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */ - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_b>; - status = "okay"; -}; - -&usb_otg { - dr_mode = "otg"; - status = "okay"; -}; - -&usb0_vbus_pin_a { - allwinner,pins = "PG12"; -}; - -&usbphy { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>; - usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */ - usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */ - usb0_vbus-supply = <®_usb0_vbus>; - usb1_vbus-supply = <®_ldo3>; - status = "okay"; }; -- cgit v1.2.3 From cb0db11afe72eb5206ba35cd9afa2868d0550cbe Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:42:25 +0200 Subject: ARM: dts: sun5i: Add dts file for the Empire Electronix M712 tablet Add a dts file for the Empire Electronix M712 tablet, this is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV wifi chip and a DMART06 (1238a4) accelerometer. Note currently the dts for this is somewhat empty. This will change once we add support for the touchscreen and accelerometer. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + .../boot/dts/sun5i-a13-empire-electronix-m712.dts | 51 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) create mode 100644 arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1ec7fe99de33..94d5591188b1 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -727,6 +727,7 @@ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-wobo-i5.dtb \ sun5i-a13-difrnce-dit4350.dtb \ sun5i-a13-empire-electronix-d709.dtb \ + sun5i-a13-empire-electronix-m712.dtb \ sun5i-a13-hsg-h702.dtb \ sun5i-a13-inet-98v-rev2.dtb \ sun5i-a13-olinuxino.dtb \ diff --git a/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts b/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts new file mode 100644 index 000000000000..b1e2afd9de52 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-empire-electronix-m712.dts @@ -0,0 +1,51 @@ +/* + * Copyright 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun5i-a13.dtsi" +#include "sun5i-reference-design-tablet.dtsi" +#include + +/ { + model = "Empire Electronix M712 tablet"; + compatible = "empire-electronix,m712", "allwinner,sun5i-a13"; +}; -- cgit v1.2.3 From c224d20db77b944a7aed1c4f8723508ee409af48 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:42:26 +0200 Subject: ARM: dts: sun8i: Rename reference-design-tablet touchscreen node Rename the reference-design-tablet touchscreen node from gsl1680 to touchscreen, all? tablets seem to use the same power and interrupt gpio-s, but not all tablets use a gsl1680 controller making the gsl1680 name somewhat misleading. Also move the reg and compatible property to the actual tablet dts as they may differ per tablet. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi index f29897c40ae8..08cd00143635 100644 --- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi +++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi @@ -71,15 +71,13 @@ */ clock-frequency = <400000>; - gsl1680: touchscreen@40 { - compatible = "silead,gsl1680"; - reg = <0x40>; + touchscreen: touchscreen@0 { interrupt-parent = <&pio>; interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */ pinctrl-names = "default"; pinctrl-0 = <&ts_power_pin>; power-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */ - /* Most tablets use this touchscreen, but not all */ + /* Tablet dts must provide reg and compatible */ status = "disabled"; }; }; -- cgit v1.2.3 From 06ad11be7a9e13499ff8e55e46f09d22f9ee6fc0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:59:50 +0800 Subject: ARM: dts: sun9i: Add missing #interrupt-cells to R_PIO pinctrl device node The R_PIO device node is missing #interrupt-cells, which causes interrupt parsing to fail to match it as a valid interrupt controller. Add #interrupt-cells to it. Also remove the unnecesary #address-cells and #size-cells. Fixes: 1ac56a6da9e1 ("ARM: dts: sun9i: Add A80 R_PIO pin controller device node") Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi index 24e3cac4f571..3c5214cbe4e6 100644 --- a/arch/arm/boot/dts/sun9i-a80.dtsi +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -898,8 +898,7 @@ resets = <&apbs_rst 0>; gpio-controller; interrupt-controller; - #address-cells = <1>; - #size-cells = <0>; + #interrupt-cells = <3>; #gpio-cells = <3>; r_ir_pins: r_ir { -- cgit v1.2.3 From 01f222dfcf7f301035ed104029bc51710d4ce4e5 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 26 Aug 2016 18:23:56 +0800 Subject: ARM: dts: sun8i: Add dts file for inet-d978_rev2 tablets The inet-d978_rev2 is a pcb used in generic A33 based tablets. It features volume buttons, micro-usb otg, headphone connector and a power button. On the board a Realtek RTL8723BS SDIO Wi-Fi module are soldered, and there is also a accompanied board which has a Goodix GT9271 soldered. As this board is desired to create tablets with a Home key dealed by GT9271, a LED is present at the front panel at the position of the Home key. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 88 ++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 94d5591188b1..7dd4a07c4784 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -784,6 +784,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-q8-tablet.dtb \ sun8i-a33-et-q8-v1.6.dtb \ sun8i-a33-ga10h-v1.1.dtb \ + sun8i-a33-inet-d978-rev2.dtb \ sun8i-a33-ippo-q8h-v1.2.dtb \ sun8i-a33-olinuxino.dtb \ sun8i-a33-q8-tablet.dtb \ diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts new file mode 100644 index 000000000000..0f52cd9dfa41 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -0,0 +1,88 @@ +/* + * Copyright 2015 Hans de Goede + * Copyright 2016 Icenowy Zheng + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-a33.dtsi" +#include "sun8i-reference-design-tablet.dtsi" + +/ { + model = "INet-D978 Rev 02"; + compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pin_d978>; + + home { + label = "d978:blue:home"; + gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */ + }; + }; +}; + +&mmc1_pins_a { + allwinner,pull = ; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + bus-width = <4>; + non-removable; + status = "okay"; + + rtl8723bs: sdio_wifi@1 { + reg = <1>; + }; +}; + +&r_pio { + led_pin_d978: led_pin_d978@0 { + allwinner,pins = "PL5"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; -- cgit v1.2.3 From 143778ebc8c97f74b16feca4da7736cdf69f7a9a Mon Sep 17 00:00:00 2001 From: Guenter Roeck Date: Tue, 5 Jul 2016 09:44:33 -0700 Subject: ARM: dts: lpc4350-hitex-eval: fix binding for SE97 i2c device The 'compatible = "nxp,jc42"' binding only happened to work because the Linux driver is named jc42. The driver now supports generic bindings for JC-42 compatible chips, so use the generic binding instead. Signed-off-by: Guenter Roeck Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index 6c9048d4d03c..c97cba1d26a8 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -424,7 +424,7 @@ /* NXP SE97BTP with temperature sensor + eeprom */ sensor@18 { - compatible = "nxp,jc42"; + compatible = "nxp,se97", "jedec,jc-42.4-temp"; reg = <0x18>; }; -- cgit v1.2.3 From 3ed6d3cb14097218629ace56aa1a2d0a862b3125 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Fri, 6 May 2016 08:57:49 +0200 Subject: ARM: dts: lpc18xx: configure dwmac properly Configure the DWMAC FIFO sizes, burst length and threshold DMA mode on LPC18xx/43xx SoCs. These parameters are needed for correct operation of the Ethernet MAC. The DWMAC on LPC18xx/43xx does not support RSF DMA mode and therefore must use threshold mode. Signed-off-by: Joachim Eastwood --- arch/arm/boot/dts/lpc18xx.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index fdb736c82045..3d828fcfc7c4 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -186,6 +186,10 @@ clock-names = "stmmaceth"; resets = <&rgu 22>; reset-names = "stmmaceth"; + rx-fifo-depth = <256>; + tx-fifo-depth = <256>; + snps,pbl = <4>; /* 32 (8x mode) */ + snps,force_thresh_dma_mode; status = "disabled"; }; -- cgit v1.2.3 From b5ca028fe9ba2090afdbb3a2e8362590adc42a9c Mon Sep 17 00:00:00 2001 From: Christoph Fritz Date: Wed, 17 Aug 2016 11:25:31 +0200 Subject: ARM: dts: imx6sx: document SION necessity of ENET1_REF_CLK1 Signed-off-by: Christoph Fritz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx-pinfunc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h index bb9c6b78cb97..42c4c800feea 100644 --- a/arch/arm/boot/dts/imx6sx-pinfunc.h +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h @@ -308,6 +308,20 @@ #define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0 #define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0 #define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0 +/* + * SION bit is necessary for ENET1_REF_CLK1 (ENET2_REF_CLK2 untested) if it is + * used as clock output of IMX6SX_CLK_ENET_REF (ENET1_TX_CLK) to e.g. supply a + * PHY in RMII mode. This configuration is valid if: + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK is set + * - bit 1 in field IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK unset + * It seems to be a silicon bug that in this configuration ENET1_TX reference + * clock isn't provided automatically. According to i.MX6SX reference manual + * (IOMUXC_GPR_GPR1 field descriptions: ENET1_CLK_SEL, Rev. 0 from 2/2015) it + * should be the case. + * So this might have unwanted side effects for other hardware units that are + * also connected to that pin and using respective function as input (e.g. + * UART1's DTR handling on MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B). + */ #define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1 #define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1 #define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0 -- cgit v1.2.3 From 118e81cb7307934870721312da5443913a14faa2 Mon Sep 17 00:00:00 2001 From: Ken Lin Date: Fri, 12 Aug 2016 13:45:11 -0400 Subject: ARM: dts: imx6q-bx50v3: configure unused pca953x pins At power on, pca953x GPIO pins are configured as input and may cause unexpected interrupts. Configure the unused pins as GPO low to avoid unexpected interrupts. Signed-off-by: Ken Lin Signed-off-by: Akshay Bhat Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-b450v3.dts | 16 +++++++++ arch/arm/boot/dts/imx6q-b650v3.dts | 9 +++++ arch/arm/boot/dts/imx6q-bx50v3.dtsi | 70 +++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts index f0a2be5268e3..78bfc1a307d6 100644 --- a/arch/arm/boot/dts/imx6q-b450v3.dts +++ b/arch/arm/boot/dts/imx6q-b450v3.dts @@ -89,3 +89,19 @@ }; }; }; + +&pca9539 { + P04 { + gpio-hog; + gpios = <4 0>; + output-low; + line-name = "PCA9539-P04"; + }; + + P05 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "PCA9539-P05"; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts index 33cb71acadcc..d85388725426 100644 --- a/arch/arm/boot/dts/imx6q-b650v3.dts +++ b/arch/arm/boot/dts/imx6q-b650v3.dts @@ -89,3 +89,12 @@ }; }; }; + +&pca9539 { + P05 { + gpio-hog; + gpios = <5 0>; + output-low; + line-name = "PCA9539-P05"; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index cf3fd31e3406..e4a415fd899b 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -183,6 +183,76 @@ interrupt-controller; interrupt-parent = <&gpio2>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + P06 { + gpio-hog; + gpios = <6 0>; + output-low; + line-name = "PCA9539-P06"; + }; + + P07 { + gpio-hog; + gpios = <7 0>; + output-low; + line-name = "PCA9539-P07"; + }; + + P10 { + gpio-hog; + gpios = <8 0>; + output-low; + line-name = "PCA9539-P10"; + }; + + P11 { + gpio-hog; + gpios = <9 0>; + output-low; + line-name = "PCA9539-P11"; + }; + + P12 { + gpio-hog; + gpios = <10 0>; + output-low; + line-name = "PCA9539-P12"; + }; + + P13 { + gpio-hog; + gpios = <11 0>; + output-low; + line-name = "PCA9539-P13"; + }; + + P14 { + gpio-hog; + gpios = <12 0>; + output-low; + line-name = "PCA9539-P14"; + }; + + P15 { + gpio-hog; + gpios = <13 0>; + output-low; + line-name = "PCA9539-P15"; + }; + + P16 { + gpio-hog; + gpios = <14 0>; + output-low; + line-name = "PCA9539-P16"; + }; + + P17 { + gpio-hog; + gpios = <15 0>; + output-low; + line-name = "PCA9539-P17"; + }; }; }; -- cgit v1.2.3 From e355e0f6840fc0b407dfd4c71c774b7d617abd69 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 16 Aug 2016 22:46:42 -0300 Subject: ARM: dts: imx6ul-pico-hobbit: Use WDOG_B pin reset imx6ul-pico has WDOG1_B pin connected to the PMIC. Pass the 'fsl,ext-reset-output' property so that the watchdog can trigger a system POR reset via PMIC. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul-pico-hobbit.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 7b18dc4727a9..827d9e8fc74e 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -344,6 +344,12 @@ status = "okay"; }; +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + &iomuxc { pinctrl_brcm_reg: brcmreggrp { fsl,pins = < @@ -534,4 +540,10 @@ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 >; }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; }; -- cgit v1.2.3 From b9dea8613813fac124f6a323a861f9e8c0aef1d8 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 25 Aug 2016 15:05:47 -0300 Subject: ARM: dts: imx7s-warp: Let the codec control MCLK pinctrl sgtl5000 codec needs MCLK clock to be provided so that it can successfully read/write via I2C, so we should better let the codec control the pinctrl for such pin. Thanks to Stefan Agner who provided the fix on Toradex's tree: http://git.toradex.com/cgit/linux-toradex.git/commit/?h=toradex_imx_4.1.15_1.0.0_ga-next&id=0a55a7e5f58d46eef0d4d1d357d89e36d0c32fa4 Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 92d9c8570716..1ff762d180ef 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -199,6 +199,8 @@ reg = <0x0a>; compatible = "fsl,sgtl5000"; clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; VDDA-supply = <&vgen4_reg>; VDDIO-supply = <&vgen4_reg>; VDDD-supply = <&vgen2_reg>; @@ -291,7 +293,12 @@ MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; + + pinctrl_sai1_mclk: sai1mclkgrp { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f >; }; -- cgit v1.2.3 From a305cc2fce217510dd255356d783e2c01cbc3a8f Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 26 Aug 2016 17:38:54 +0200 Subject: ARM: dts: mvebu: fix reference to a390 spi controller The SPI controller in the arch/arm/boot/dts/armada-39x.dtsi file has moved to a different location in the hierarchy, which breaks the overrides in the board specific file: Warning (reg_format): "reg" property in /soc/internal-regs/spi@10680/spi-flash@1 has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1) Warning (avoid_default_addr_size): Relying on default #address-cells value for /soc/internal-regs/spi@10680/spi-flash@1 This changes the board to reference the spi controller by its label (which has not changed) rather than the full path. Signed-off-by: Arnd Bergmann Fixes: 0160a4b68987 ("ARM: dts: mvebu: A37x/XP/38x/39x: Move SPI controller nodes into 'soc' node") Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/armada-390-db.dts | 60 ++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/armada-390-db.dts b/arch/arm/boot/dts/armada-390-db.dts index 9d0d9b2e9bfc..34e279d973c8 100644 --- a/arch/arm/boot/dts/armada-390-db.dts +++ b/arch/arm/boot/dts/armada-390-db.dts @@ -66,36 +66,6 @@ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>; internal-regs { - spi@10680 { - status = "okay"; - pinctrl-0 = <&spi1_pins>; - pinctrl-names = "default"; - - spi-flash@1 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "n25q128a13", - "jedec,spi-nor"; - reg = <0>; /* Chip select 0 */ - spi-max-frequency = <108000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "U-Boot"; - reg = <0 0x400000>; - }; - partition@400000 { - label = "Filesystem"; - reg = <0x400000 0xc00000>; - }; - }; - }; - }; - i2c@11000 { status = "okay"; clock-frequency = <100000>; @@ -173,3 +143,33 @@ }; }; }; + +&spi1 { + status = "okay"; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + + spi-flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q128a13", + "jedec,spi-nor"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <108000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "U-Boot"; + reg = <0 0x400000>; + }; + partition@400000 { + label = "Filesystem"; + reg = <0x400000 0xc00000>; + }; + }; + }; +}; -- cgit v1.2.3 From 51c578efc3f0143f6e8433b32d3e12ac74f03fd6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 26 Aug 2016 16:22:54 +0200 Subject: ARM: dts: imx6sx: Add GPU bindings Add bindings for the Vivante GC400T GPU found in the i.MX6SX. Signed-off-by: Marek Vasut Cc: Fabio Estevam Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 2863c52be6f5..356dc385c96f 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -159,6 +159,16 @@ arm,data-latency = <4 2 3>; }; + gpu: gpu@01800000 { + compatible = "vivante,gc"; + reg = <0x01800000 0x4000>; + interrupts = ; + clocks = <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>, + <&clks IMX6SX_CLK_GPU>; + clock-names = "bus", "core", "shader"; + }; + dma_apbh: dma-apbh@01804000 { compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh"; reg = <0x01804000 0x2000>; @@ -1273,4 +1283,9 @@ status = "disabled"; }; }; + + gpu-subsystem { + compatible = "fsl,imx-gpu-subsystem"; + cores = <&gpu>; + }; }; -- cgit v1.2.3 From 987a2250aa39fe9ed58b1ee7dee9128a82a6d799 Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 28 Aug 2016 22:13:22 -0700 Subject: ARM: dts: imx7-colibri: move SD-card to module level Move SD-card definition to module level. While at it, also disable write-protect since the Colibri standard does not define a pin for SD-Card write-protection. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 4 ---- arch/arm/boot/dts/imx7-colibri.dtsi | 8 ++++++++ 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 1545661df583..373ee19196a6 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -138,10 +138,6 @@ }; &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; keep-power-in-suspend; wakeup-source; status = "okay"; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 0a9d3a822fc0..044b83e355c6 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -251,6 +251,14 @@ dr_mode = "host"; }; +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; -- cgit v1.2.3 From 8e90193567c5776b63dc5f67ad02a294796e3c3d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 28 Aug 2016 22:13:23 -0700 Subject: ARM: dts: imx7-colibri: add basic supply regulators Colibri modules need to be powered using the power pins 3V3 and AVDD_AUDIO. Add fixed regulators which represent this power rails. Potentially, those power rails could be switched on a carrier board. A carrier board device tree could add a own regulator with a GPIO, and reference that regulator in a vin-supply property of those new module level system regulators. This also synchronize the name of the +3.3V regulator with the one used in the Colibri VF50/VF61 device tree. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-colibri.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 044b83e355c6..06fb56720792 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -46,12 +46,18 @@ pwms = <&pwm1 0 5000000>; }; - reg_3p3v: regulator-3p3v { + reg_module_3v3: regulator-module-3v3 { compatible = "regulator-fixed"; - regulator-name = "3P3V"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; reg_vref_1v8: regulator-vref-1v8 { -- cgit v1.2.3 From 3dc3336bafb96dc96337cc3497381756b78dcc6a Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Sun, 28 Aug 2016 22:13:24 -0700 Subject: ARM: dts: imx7-colibri: add Audio support Add audio support via on module I2S SGTL5000 codec. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-colibri.dtsi | 41 ++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 06fb56720792..a9cc65725f19 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -66,6 +66,22 @@ regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx7-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + }; + }; }; &adc1 { @@ -103,6 +119,18 @@ pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; status = "okay"; + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1_mclk>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_DCDC3>; + }; + ad7879@2c { compatible = "adi,ad7879-1"; reg = <0x2c>; @@ -223,6 +251,12 @@ vin-supply = <®_DCDC3>; }; +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + &snvs_pwrkey { status = "disabled"; }; @@ -542,13 +576,18 @@ pinctrl_sai1: sai1-grp { fsl,pins = < - MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f >; }; + + pinctrl_sai1_mclk: sai1grp_mclk { + fsl,pins = < + MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f + >; + }; }; &iomuxc_lpsr { -- cgit v1.2.3 From 0f39c504cd97661068c3ec1014d3cf440bdeec8a Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 29 Aug 2016 22:25:43 +0800 Subject: ARM: dts: imx6ul iomuxc syscon is compatible to imx6q The imx6ul iomuxc syscon is compatible to imx6q, so let's add compatible string 'fsl,imx6q-iomuxc-gpr' for imx6ul iomuxc syscon node. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 33b95d78831a..acc948654b82 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -644,7 +644,8 @@ }; gpr: iomuxc-gpr@020e4000 { - compatible = "fsl,imx6ul-iomuxc-gpr", "syscon"; + compatible = "fsl,imx6ul-iomuxc-gpr", + "fsl,imx6q-iomuxc-gpr", "syscon"; reg = <0x020e4000 0x4000>; }; -- cgit v1.2.3 From 547868f5bc5c7e41ea18c2e5fe5947f13e6199b2 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sat, 27 Aug 2016 21:19:25 -0500 Subject: ARM: dts: Add LogicPD DM37/AM37 Torpedo and SOM-LV Support is in the device tree, but they are not mentioned here. Signed-off-by: Adam Ford Signed-off-by: Tony Lindgren --- Documentation/devicetree/bindings/arm/omap/omap.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/omap/omap.txt b/Documentation/devicetree/bindings/arm/omap/omap.txt index 94b57f247615..f53e2ee65e35 100644 --- a/Documentation/devicetree/bindings/arm/omap/omap.txt +++ b/Documentation/devicetree/bindings/arm/omap/omap.txt @@ -180,3 +180,9 @@ Boards: - DRA722 EVM: Software Development Board for DRA722 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7" + +- DM3730 Logic PD Torpedo + Wireless: Commercial System on Module with WiFi and Bluetooth + compatible = "logicpd,dm3730-torpedo-devkit", "ti,omap3630", "ti,omap3" + +- DM3730 Logic PD SOM-LV: Commercial System on Module with WiFi and Bluetooth + compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3" -- cgit v1.2.3 From 9a58485ebc92ff8d66428f9eadae2a2e47f3ee9c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Aug 2016 03:27:42 +0900 Subject: ARM: dts: uniphier: remove a whitespace after tabs A trivial codying style fix. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 03f60ec340b5..be4e3b0514dc 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -141,7 +141,7 @@ reg = <0x5f800000 0x2000>; pinctrl: pinctrl { - /* specify compatible in each SoC DTSI */ + /* specify compatible in each SoC DTSI */ }; }; }; -- cgit v1.2.3 From 77896e4d05af6a9330c5410a4d45cc72fd030f1c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 30 Aug 2016 14:02:41 +0900 Subject: ARM: dts: uniphier: match DT names to other projects and documents All UniPhier device trees have the common prefix "uniphier-", so "ph1-" is just making names longer. Recent documents and other projects are not using PH1- prefixes any more. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/Makefile | 18 +- arch/arm/boot/dts/uniphier-ld4-ref.dts | 102 +++++++++ arch/arm/boot/dts/uniphier-ld4.dtsi | 187 ++++++++++++++++ arch/arm/boot/dts/uniphier-ld6b-ref.dts | 96 ++++++++ arch/arm/boot/dts/uniphier-ld6b.dtsi | 68 ++++++ arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts | 101 --------- arch/arm/boot/dts/uniphier-ph1-ld4.dtsi | 186 --------------- arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts | 95 -------- arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi | 67 ------ arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts | 113 ---------- arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts | 103 --------- arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts | 108 --------- arch/arm/boot/dts/uniphier-ph1-pro4.dtsi | 204 ----------------- arch/arm/boot/dts/uniphier-ph1-pro5.dtsi | 198 ---------------- arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts | 110 --------- arch/arm/boot/dts/uniphier-ph1-sld3.dtsi | 260 --------------------- arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts | 105 --------- arch/arm/boot/dts/uniphier-ph1-sld8.dtsi | 185 --------------- arch/arm/boot/dts/uniphier-pro4-ace.dts | 114 ++++++++++ arch/arm/boot/dts/uniphier-pro4-ref.dts | 104 +++++++++ arch/arm/boot/dts/uniphier-pro4-sanji.dts | 109 +++++++++ arch/arm/boot/dts/uniphier-pro4.dtsi | 205 +++++++++++++++++ arch/arm/boot/dts/uniphier-pro5.dtsi | 199 +++++++++++++++++ arch/arm/boot/dts/uniphier-proxstream2-gentil.dts | 88 -------- arch/arm/boot/dts/uniphier-proxstream2-vodka.dts | 78 ------- arch/arm/boot/dts/uniphier-proxstream2.dtsi | 209 ----------------- arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 90 ++++++++ arch/arm/boot/dts/uniphier-pxs2-vodka.dts | 79 +++++++ arch/arm/boot/dts/uniphier-pxs2.dtsi | 210 +++++++++++++++++ arch/arm/boot/dts/uniphier-sld3-ref.dts | 111 +++++++++ arch/arm/boot/dts/uniphier-sld3.dtsi | 261 ++++++++++++++++++++++ arch/arm/boot/dts/uniphier-sld8-ref.dts | 106 +++++++++ arch/arm/boot/dts/uniphier-sld8.dtsi | 186 +++++++++++++++ 33 files changed, 2236 insertions(+), 2219 deletions(-) create mode 100644 arch/arm/boot/dts/uniphier-ld4-ref.dts create mode 100644 arch/arm/boot/dts/uniphier-ld4.dtsi create mode 100644 arch/arm/boot/dts/uniphier-ld6b-ref.dts create mode 100644 arch/arm/boot/dts/uniphier-ld6b.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-ld4.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-pro4.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-pro5.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-sld3.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts delete mode 100644 arch/arm/boot/dts/uniphier-ph1-sld8.dtsi create mode 100644 arch/arm/boot/dts/uniphier-pro4-ace.dts create mode 100644 arch/arm/boot/dts/uniphier-pro4-ref.dts create mode 100644 arch/arm/boot/dts/uniphier-pro4-sanji.dts create mode 100644 arch/arm/boot/dts/uniphier-pro4.dtsi create mode 100644 arch/arm/boot/dts/uniphier-pro5.dtsi delete mode 100644 arch/arm/boot/dts/uniphier-proxstream2-gentil.dts delete mode 100644 arch/arm/boot/dts/uniphier-proxstream2-vodka.dts delete mode 100644 arch/arm/boot/dts/uniphier-proxstream2.dtsi create mode 100644 arch/arm/boot/dts/uniphier-pxs2-gentil.dts create mode 100644 arch/arm/boot/dts/uniphier-pxs2-vodka.dts create mode 100644 arch/arm/boot/dts/uniphier-pxs2.dtsi create mode 100644 arch/arm/boot/dts/uniphier-sld3-ref.dts create mode 100644 arch/arm/boot/dts/uniphier-sld3.dtsi create mode 100644 arch/arm/boot/dts/uniphier-sld8-ref.dts create mode 100644 arch/arm/boot/dts/uniphier-sld8.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..1dd472278870 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -836,15 +836,15 @@ dtb-$(CONFIG_ARCH_U8500) += \ ste-ccu8540.dtb \ ste-ccu9540.dtb dtb-$(CONFIG_ARCH_UNIPHIER) += \ - uniphier-ph1-ld4-ref.dtb \ - uniphier-ph1-ld6b-ref.dtb \ - uniphier-ph1-pro4-ace.dtb \ - uniphier-ph1-pro4-ref.dtb \ - uniphier-ph1-pro4-sanji.dtb \ - uniphier-ph1-sld3-ref.dtb \ - uniphier-ph1-sld8-ref.dtb \ - uniphier-proxstream2-gentil.dtb \ - uniphier-proxstream2-vodka.dtb + uniphier-ld4-ref.dtb \ + uniphier-ld6b-ref.dtb \ + uniphier-pro4-ace.dtb \ + uniphier-pro4-ref.dtb \ + uniphier-pro4-sanji.dtb \ + uniphier-pxs2-gentil.dtb \ + uniphier-pxs2-vodka.dtb \ + uniphier-sld3-ref.dtb \ + uniphier-sld8-ref.dtb dtb-$(CONFIG_ARCH_VERSATILE) += \ versatile-ab.dtb \ versatile-pb.dtb diff --git a/arch/arm/boot/dts/uniphier-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ld4-ref.dts new file mode 100644 index 000000000000..110031bc0e7e --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ld4-ref.dts @@ -0,0 +1,102 @@ +/* + * Device Tree Source for UniPhier LD4 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ld4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD4 Reference Board"; + compatible = "socionext,uniphier-ld4-ref", "socionext,uniphier-ld4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +ðsc { + interrupts = <0 49 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi new file mode 100644 index 000000000000..298fb388c1a3 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -0,0 +1,187 @@ +/* + * Device Tree Source for UniPhier LD4 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-ld4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; + +}; + +&refclk { + clock-frequency = <24576000>; +}; + +&serial3 { + interrupts = <0 29 4>; +}; + +&pinctrl { + compatible = "socionext,uniphier-ld4-pinctrl"; +}; diff --git a/arch/arm/boot/dts/uniphier-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ld6b-ref.dts new file mode 100644 index 000000000000..c05d631dcf02 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ld6b-ref.dts @@ -0,0 +1,96 @@ +/* + * Device Tree Source for UniPhier LD6b Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-ld6b.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier LD6b Reference Board"; + compatible = "socionext,uniphier-ld6b-ref", "socionext,uniphier-ld6b"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +ðsc { + interrupts = <0 52 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ld6b.dtsi new file mode 100644 index 000000000000..905c77d499eb --- /dev/null +++ b/arch/arm/boot/dts/uniphier-ld6b.dtsi @@ -0,0 +1,68 @@ +/* + * Device Tree Source for UniPhier LD6b SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * LD6b consists of two silicon dies: D-chip and A-chip. + * The D-chip (digital chip) is the same as the PXs2 die. + * Reuse the PXs2 device tree with some properties overridden. + */ +/include/ "uniphier-pxs2.dtsi" + +/ { + compatible = "socionext,uniphier-ld6b"; +}; + +/* UART3 unavailable: the pads are not wired to the package balls */ +&serial3 { + status = "disabled"; +}; + +/* + * LD6b and PXs2 have completely different packages, + * which makes the pinctrl driver unshareable. + */ +&pinctrl { + compatible = "socionext,uniphier-ld6b-pinctrl"; +}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts deleted file mode 100644 index ec94b7a661f2..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-ld4-ref.dts +++ /dev/null @@ -1,101 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD4 Reference Board"; - compatible = "socionext,ph1-ld4-ref", "socionext,ph1-ld4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi deleted file mode 100644 index debad7ffef05..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD4 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-ld4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; - -}; - -&refclk { - clock-frequency = <24576000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&pinctrl { - compatible = "socionext,uniphier-ld4-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts b/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts deleted file mode 100644 index b8134c6e094b..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-ld6b-ref.dts +++ /dev/null @@ -1,95 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-ld6b.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-LD6b Reference Board"; - compatible = "socionext,ph1-ld6b-ref", "socionext,ph1-ld6b"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 52 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi deleted file mode 100644 index 19c107c66bae..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-LD6b SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/* - * PH1-LD6b consists of two silicon dies: D-chip and A-chip. - * The D-chip (digital chip) is the same as the ProXstream2 die. - * Reuse the ProXstream2 device tree with some properties overridden. - */ -/include/ "uniphier-proxstream2.dtsi" - -/ { - compatible = "socionext,ph1-ld6b"; -}; - -/* UART3 unavailable: the pads are not wired to the package balls */ -&serial3 { - status = "disabled"; -}; - -/* - * PH1-LD6b and ProXstream2 have completely different packages, - * which makes the pinctrl driver unshareable. - */ -&pinctrl { - compatible = "socionext,uniphier-ld6b-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts b/arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts deleted file mode 100644 index d34358632bec..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-pro4-ace.dts +++ /dev/null @@ -1,113 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Ace Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Ace Board"; - compatible = "socionext,ph1-pro4-ace", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts b/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts deleted file mode 100644 index 95f631a3de35..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-pro4-ref.dts +++ /dev/null @@ -1,103 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Reference Board"; - compatible = "socionext,ph1-pro4-ref", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x40000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -ðsc { - interrupts = <0 50 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts deleted file mode 100644 index 7c3a1fcc9f3c..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-pro4-sanji.dts +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 Sanji Board - * - * Copyright (C) 2016 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-pro4.dtsi" - -/ { - model = "UniPhier PH1-Pro4 Sanji Board"; - compatible = "socionext,ph1-pro4-sanji", "socionext,ph1-pro4"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c1 { - status = "okay"; -}; - -&i2c2 { - status = "okay"; -}; - -&i2c3 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi deleted file mode 100644 index 7b9da0852005..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi +++ /dev/null @@ -1,204 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro4 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro4"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(768 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - usb2: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; - - usb3: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro4-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi deleted file mode 100644 index 7e4aa2fde719..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi +++ /dev/null @@ -1,198 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-Pro5 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-pro5"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; - interrupts = <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - next-level-cache = <&l3>; - }; - - l3: l3-cache@500c8000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(2 * 1024 * 1024)>; - cache-sets = <512>; - cache-line-size = <256>; - cache-level = <3>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* i2c4 does not exist */ - - /* chip-internal connection for DMD */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <20000000>; -}; - -&pinctrl { - compatible = "socionext,uniphier-pro5-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts deleted file mode 100644 index acb420492b36..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-sld3-ref.dts +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld3.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD3 Reference Board"; - compatible = "socionext,ph1-sld3-ref", "socionext,ph1-sld3"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000 - 0xc0000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; -}; - -ðsc { - interrupts = <0 49 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial1 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; - -&usb3 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi deleted file mode 100644 index 03292f443305..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-sld3.dtsi +++ /dev/null @@ -1,260 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD3 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "skeleton.dtsi" - -/ { - compatible = "socionext,ph1-sld3"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - }; - - clocks { - refclk: ref { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24576000>; - }; - - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; - - soc { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - interrupt-parent = <&intc>; - - timer@20000200 { - compatible = "arm,cortex-a9-global-timer"; - reg = <0x20000200 0x20>; - interrupts = <1 11 0x304>; - clocks = <&arm_timer_clk>; - }; - - timer@20000600 { - compatible = "arm,cortex-a9-twd-timer"; - reg = <0x20000600 0x20>; - interrupts = <1 13 0x304>; - clocks = <&arm_timer_clk>; - }; - - intc: interrupt-controller@20001000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x20001000 0x1000>, - <0x20000100 0x100>; - }; - - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, - <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(512 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - serial0: serial@54006800 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006800 0x40>; - interrupts = <0 33 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - serial1: serial@54006900 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006900 0x40>; - interrupts = <0 35 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - serial2: serial@54006a00 { - compatible = "socionext,uniphier-uart"; - status = "disabled"; - reg = <0x54006a00 0x40>; - interrupts = <0 37 4>; - clocks = <&uart_clk>; - fifo-size = <64>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58600000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58600000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 1>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - system_bus: system-bus@58c00000 { - compatible = "socionext,uniphier-system-bus"; - status = "disabled"; - reg = <0x58c00000 0x400>; - #address-cells = <2>; - #size-cells = <1>; - }; - - smpctrl@59800000 { - compatible = "socionext,uniphier-smpctrl"; - reg = <0x59801000 0x400>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - }; - - usb3: usb@5a830100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a830100 0x100>; - interrupts = <0 83 4>; - }; - }; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts b/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts deleted file mode 100644 index d594f40e7f76..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-sld8-ref.dts +++ /dev/null @@ -1,105 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 Reference Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-ph1-sld8.dtsi" -/include/ "uniphier-ref-daughter.dtsi" -/include/ "uniphier-support-card.dtsi" - -/ { - model = "UniPhier PH1-sLD8 Reference Board"; - compatible = "socionext,ph1-sld8-ref", "socionext,ph1-sld8"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial0; - serial1 = &serial1; - serial2 = &serial2; - serial3 = &serial3; - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - }; -}; - -ðsc { - interrupts = <0 48 4>; -}; - -&serial0 { - status = "okay"; -}; - -&serial2 { - status = "okay"; -}; - -&serial3 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -}; - -&usb2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi deleted file mode 100644 index 467f9d8e9873..000000000000 --- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Device Tree Source for UniPhier PH1-sLD8 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,ph1-sld8"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>; - cache-unified; - cache-size = <(256 * 1024)>; - cache-sets = <256>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58400000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58400000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58480000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58480000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c2: i2c@58500000 { - compatible = "socionext,uniphier-i2c"; - reg = <0x58500000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 43 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; - clock-frequency = <400000>; - }; - - i2c3: i2c@58580000 { - compatible = "socionext,uniphier-i2c"; - status = "disabled"; - reg = <0x58580000 0x40>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; - clock-frequency = <100000>; - }; - - usb0: usb@5a800100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a800100 0x100>; - interrupts = <0 80 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0>; - }; - - usb1: usb@5a810100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a810100 0x100>; - interrupts = <0 81 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb1>; - }; - - usb2: usb@5a820100 { - compatible = "socionext,uniphier-ehci", "generic-ehci"; - status = "disabled"; - reg = <0x5a820100 0x100>; - interrupts = <0 82 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb2>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&serial3 { - interrupts = <0 29 4>; -}; - -&pinctrl { - compatible = "socionext,uniphier-sld8-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-pro4-ace.dts b/arch/arm/boot/dts/uniphier-pro4-ace.dts new file mode 100644 index 000000000000..0ab0a40c041e --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro4-ace.dts @@ -0,0 +1,114 @@ +/* + * Device Tree Source for UniPhier Pro4 Ace Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Ace Board"; + compatible = "socionext,uniphier-pro4-ace", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64"; + reg = <0x54>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4-ref.dts b/arch/arm/boot/dts/uniphier-pro4-ref.dts new file mode 100644 index 000000000000..9e92e60d25ce --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro4-ref.dts @@ -0,0 +1,104 @@ +/* + * Device Tree Source for UniPhier Pro4 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier Pro4 Reference Board"; + compatible = "socionext,uniphier-pro4-ref", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +ðsc { + interrupts = <0 50 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4-sanji.dts b/arch/arm/boot/dts/uniphier-pro4-sanji.dts new file mode 100644 index 000000000000..dc4ea8832ce2 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro4-sanji.dts @@ -0,0 +1,109 @@ +/* + * Device Tree Source for UniPhier Pro4 Sanji Board + * + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-pro4.dtsi" + +/ { + model = "UniPhier Pro4 Sanji Board"; + compatible = "socionext,uniphier-pro4-sanji", "socionext,uniphier-pro4"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64"; + reg = <0x54>; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi new file mode 100644 index 000000000000..fd450f342c49 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -0,0 +1,205 @@ +/* + * Device Tree Source for UniPhier Pro4 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pro4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(768 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + usb2: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; + + usb3: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&pinctrl { + compatible = "socionext,uniphier-pro4-pinctrl"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi new file mode 100644 index 000000000000..9f9fd8c89b72 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -0,0 +1,199 @@ +/* + * Device Tree Source for UniPhier Pro5 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pro5"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <73728000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; + interrupts = <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + next-level-cache = <&l3>; + }; + + l3: l3-cache@500c8000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(2 * 1024 * 1024)>; + cache-sets = <512>; + cache-line-size = <256>; + cache-level = <3>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* i2c4 does not exist */ + + /* chip-internal connection for DMD */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; +}; + +&refclk { + clock-frequency = <20000000>; +}; + +&pinctrl { + compatible = "socionext,uniphier-pro5-pinctrl"; +}; diff --git a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts deleted file mode 100644 index 98d895b7af1d..000000000000 --- a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Gentil Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Gentil Board"; - compatible = "socionext,proxstream2-gentil", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c2 = &i2c2; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - eeprom@54 { - compatible = "st,24c64"; - reg = <0x54>; - }; -}; - -&i2c2 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts b/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts deleted file mode 100644 index 1fb8bd7bb686..000000000000 --- a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 Vodka Board - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/dts-v1/; -/include/ "uniphier-proxstream2.dtsi" - -/ { - model = "UniPhier ProXstream2 Vodka Board"; - compatible = "socionext,proxstream2-vodka", "socionext,proxstream2"; - - memory { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - aliases { - serial0 = &serial2; - serial1 = &serial0; - serial2 = &serial1; - i2c0 = &i2c0; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; -}; - -&serial2 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi deleted file mode 100644 index d00d6f5c2668..000000000000 --- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi +++ /dev/null @@ -1,209 +0,0 @@ -/* - * Device Tree Source for UniPhier ProXstream2 SoC - * - * Copyright (C) 2015 Masahiro Yamada - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) any later version. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ - -/include/ "uniphier-common32.dtsi" - -/ { - compatible = "socionext,proxstream2"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&l2>; - }; - - cpu@1 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&l2>; - }; - - cpu@2 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&l2>; - }; - - cpu@3 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&l2>; - }; - }; - - clocks { - arm_timer_clk: arm_timer_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - }; -}; - -&soc { - l2: l2-cache@500c0000 { - compatible = "socionext,uniphier-system-cache"; - reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; - interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; - cache-unified; - cache-size = <(1280 * 1024)>; - cache-sets = <512>; - cache-line-size = <128>; - cache-level = <2>; - }; - - i2c0: i2c@58780000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58780000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 41 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c1: i2c@58781000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58781000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 42 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c2: i2c@58782000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58782000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - interrupts = <0 43 4>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - i2c3: i2c@58783000 { - compatible = "socionext,uniphier-fi2c"; - status = "disabled"; - reg = <0x58783000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 44 4>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; - clock-frequency = <100000>; - }; - - /* chip-internal connection for DMD */ - i2c4: i2c@58784000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58784000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 45 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for STM */ - i2c5: i2c@58785000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58785000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 25 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; - - /* chip-internal connection for HDMI */ - i2c6: i2c@58786000 { - compatible = "socionext,uniphier-fi2c"; - reg = <0x58786000 0x80>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <0 26 4>; - clocks = <&i2c_clk>; - clock-frequency = <400000>; - }; -}; - -&refclk { - clock-frequency = <25000000>; -}; - -&pinctrl { - compatible = "socionext,uniphier-pxs2-pinctrl"; -}; diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts new file mode 100644 index 000000000000..373818ace086 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts @@ -0,0 +1,90 @@ +/* + * Device Tree Source for UniPhier PXs2 Gentil Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Gentil Board"; + compatible = "socionext,uniphier-pxs2-gentil", + "socionext,uniphier-pxs2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + eeprom@54 { + compatible = "st,24c64"; + reg = <0x54>; + }; +}; + +&i2c2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pxs2-vodka.dts b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts new file mode 100644 index 000000000000..51a3eacddfc6 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pxs2-vodka.dts @@ -0,0 +1,79 @@ +/* + * Device Tree Source for UniPhier PXs2 Vodka Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-pxs2.dtsi" + +/ { + model = "UniPhier PXs2 Vodka Board"; + compatible = "socionext,uniphier-pxs2-vodka", "socionext,uniphier-pxs2"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial2; + serial1 = &serial0; + serial2 = &serial1; + i2c0 = &i2c0; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + }; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi new file mode 100644 index 000000000000..6d702d2d7757 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -0,0 +1,210 @@ +/* + * Device Tree Source for UniPhier PXs2 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-pxs2"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&l2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&l2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <88900000>; + }; + + i2c_clk: i2c_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; + cache-unified; + cache-size = <(1280 * 1024)>; + cache-sets = <512>; + cache-line-size = <128>; + cache-level = <2>; + }; + + i2c0: i2c@58780000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58780000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58781000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58781000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58782000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58782000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + interrupts = <0 43 4>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58783000 { + compatible = "socionext,uniphier-fi2c"; + status = "disabled"; + reg = <0x58783000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58784000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58784000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for STM */ + i2c5: i2c@58785000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58785000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 25 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; + + /* chip-internal connection for HDMI */ + i2c6: i2c@58786000 { + compatible = "socionext,uniphier-fi2c"; + reg = <0x58786000 0x80>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 26 4>; + clocks = <&i2c_clk>; + clock-frequency = <400000>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&pinctrl { + compatible = "socionext,uniphier-pxs2-pinctrl"; +}; diff --git a/arch/arm/boot/dts/uniphier-sld3-ref.dts b/arch/arm/boot/dts/uniphier-sld3-ref.dts new file mode 100644 index 000000000000..ac792ae07ae0 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-sld3-ref.dts @@ -0,0 +1,111 @@ +/* + * Device Tree Source for UniPhier sLD3 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-sld3.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier sLD3 Reference Board"; + compatible = "socionext,uniphier-sld3-ref", "socionext,uniphier-sld3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000 + 0xc0000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + }; +}; + +ðsc { + interrupts = <0 49 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&usb3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi new file mode 100644 index 000000000000..f33caf4ef12d --- /dev/null +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -0,0 +1,261 @@ +/* + * Device Tree Source for UniPhier sLD3 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "socionext,uniphier-sld3"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,uniphier-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + clocks { + refclk: ref { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24576000>; + }; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <36864000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&intc>; + + timer@20000200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x20000200 0x20>; + interrupts = <1 11 0x304>; + clocks = <&arm_timer_clk>; + }; + + timer@20000600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x20000600 0x20>; + interrupts = <1 13 0x304>; + clocks = <&arm_timer_clk>; + }; + + intc: interrupt-controller@20001000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x20001000 0x1000>, + <0x20000100 0x100>; + }; + + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, + <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(512 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + serial0: serial@54006800 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006800 0x40>; + interrupts = <0 33 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial1: serial@54006900 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006900 0x40>; + interrupts = <0 35 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + serial2: serial@54006a00 { + compatible = "socionext,uniphier-uart"; + status = "disabled"; + reg = <0x54006a00 0x40>; + interrupts = <0 37 4>; + clocks = <&uart_clk>; + fifo-size = <64>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c4: i2c@58600000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58600000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 45 1>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + system_bus: system-bus@58c00000 { + compatible = "socionext,uniphier-system-bus"; + status = "disabled"; + reg = <0x58c00000 0x400>; + #address-cells = <2>; + #size-cells = <1>; + }; + + smpctrl@59800000 { + compatible = "socionext,uniphier-smpctrl"; + reg = <0x59801000 0x400>; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + }; + + usb3: usb@5a830100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a830100 0x100>; + interrupts = <0 83 4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/uniphier-sld8-ref.dts b/arch/arm/boot/dts/uniphier-sld8-ref.dts new file mode 100644 index 000000000000..a8291f988066 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-sld8-ref.dts @@ -0,0 +1,106 @@ +/* + * Device Tree Source for UniPhier sLD8 Reference Board + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "uniphier-sld8.dtsi" +/include/ "uniphier-ref-daughter.dtsi" +/include/ "uniphier-support-card.dtsi" + +/ { + model = "UniPhier sLD8 Reference Board"; + compatible = "socionext,uniphier-sld8-ref", "socionext,uniphier-sld8"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + aliases { + serial0 = &serial0; + serial1 = &serial1; + serial2 = &serial2; + serial3 = &serial3; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + }; +}; + +ðsc { + interrupts = <0 48 4>; +}; + +&serial0 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi new file mode 100644 index 000000000000..8bab1df6c854 --- /dev/null +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -0,0 +1,186 @@ +/* + * Device Tree Source for UniPhier sLD8 SoC + * + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "uniphier-common32.dtsi" + +/ { + compatible = "socionext,uniphier-sld8"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&l2>; + }; + }; + + clocks { + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + uart_clk: uart_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <80000000>; + }; + + iobus_clk: iobus_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + }; +}; + +&soc { + l2: l2-cache@500c0000 { + compatible = "socionext,uniphier-system-cache"; + reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; + interrupts = <0 174 4>, <0 175 4>; + cache-unified; + cache-size = <(256 * 1024)>; + cache-sets = <256>; + cache-line-size = <128>; + cache-level = <2>; + }; + + i2c0: i2c@58400000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58400000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + i2c1: i2c@58480000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58480000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 42 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + /* chip-internal connection for DMD */ + i2c2: i2c@58500000 { + compatible = "socionext,uniphier-i2c"; + reg = <0x58500000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 43 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clocks = <&iobus_clk>; + clock-frequency = <400000>; + }; + + i2c3: i2c@58580000 { + compatible = "socionext,uniphier-i2c"; + status = "disabled"; + reg = <0x58580000 0x40>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0 44 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clocks = <&iobus_clk>; + clock-frequency = <100000>; + }; + + usb0: usb@5a800100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a800100 0x100>; + interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + }; + + usb1: usb@5a810100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a810100 0x100>; + interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + }; + + usb2: usb@5a820100 { + compatible = "socionext,uniphier-ehci", "generic-ehci"; + status = "disabled"; + reg = <0x5a820100 0x100>; + interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + }; +}; + +&refclk { + clock-frequency = <25000000>; +}; + +&serial3 { + interrupts = <0 29 4>; +}; + +&pinctrl { + compatible = "socionext,uniphier-sld8-pinctrl"; +}; -- cgit v1.2.3 From 3bdba5ac181a2e9eb76bb7673bb11ab5b9783f63 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 29 Aug 2016 03:27:42 +0900 Subject: ARM: dts: uniphier: switch over to PSCI Use PSCI for enable-method instead of SoC specific implementation. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 5 +++++ arch/arm/boot/dts/uniphier-ld4.dtsi | 1 + arch/arm/boot/dts/uniphier-pro4.dtsi | 3 ++- arch/arm/boot/dts/uniphier-pro5.dtsi | 3 ++- arch/arm/boot/dts/uniphier-pxs2.dtsi | 5 ++++- arch/arm/boot/dts/uniphier-sld3.dtsi | 8 +++++++- arch/arm/boot/dts/uniphier-sld8.dtsi | 1 + 7 files changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index be4e3b0514dc..7fa6edb73e2b 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -45,6 +45,11 @@ /include/ "skeleton.dtsi" / { + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 298fb388c1a3..72f8c3579e16 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -56,6 +56,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index fd450f342c49..109046d0e41a 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -51,12 +51,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -64,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 9f9fd8c89b72..ce8e549df94f 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -51,12 +51,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -64,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 6d702d2d7757..63c12e8ea029 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -51,12 +51,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -64,6 +64,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -71,6 +72,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -78,6 +80,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index f33caf4ef12d..55f9afa2ee1b 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -51,12 +51,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - enable-method = "socionext,uniphier-smp"; cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; @@ -64,10 +64,16 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + clocks { refclk: ref { #clock-cells = <0>; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 8bab1df6c854..6191051ffc66 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -56,6 +56,7 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + enable-method = "psci"; next-level-cache = <&l2>; }; }; -- cgit v1.2.3 From 6c6b3c33eb2b7fa2d5b4cc66c8116e9315fdbd9b Mon Sep 17 00:00:00 2001 From: Vignesh R Date: Wed, 24 Aug 2016 13:28:59 +0530 Subject: ARM: dts: am335x-icev2: Add nodes for gpio-decoder AM335x ICE board has a rotary-switch connected to PCA9536 I2C GPIO expander. The position of the rotary-switch is reflected by status of GPIO lines. Add gpio-decoder node to read these GPIO line status via gpio-decoder driver and report it as an input event to the system. Signed-off-by: Vignesh R Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-icev2.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index bc0190e4f10f..426022ee85c7 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -139,6 +139,15 @@ default-state = "off"; }; }; + gpio-decoder { + compatible = "gpio-decoder"; + gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, + <&pca9536 2 GPIO_ACTIVE_HIGH>, + <&pca9536 1 GPIO_ACTIVE_HIGH>, + <&pca9536 0 GPIO_ACTIVE_HIGH>; + linux,axis = <0>; /* ABS_X */ + decoder-max-value = <9>; + }; }; &am33xx_pinmux { -- cgit v1.2.3 From bed596da1eecc77c2ce391f74fd879e3a5327add Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Wed, 10 Aug 2016 18:03:18 +0530 Subject: ARM: dts: DRA7: Add "linux,pci-domain" property for pci dt nodes Since DRA7 has multiple PCIe Rootcomplex, add "linux,pci-domain" property to assign a PCI domain number to each of the host bridges. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index df0dcbc05b4a..fbd5a3e49955 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -301,6 +301,7 @@ 0x82000000 0 0x20013000 0x13000 0 0xffed000>; #interrupt-cells = <1>; num-lanes = <1>; + linux,pci-domain = <0>; ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; @@ -336,6 +337,7 @@ 0x82000000 0 0x30013000 0x13000 0 0xffed000>; #interrupt-cells = <1>; num-lanes = <1>; + linux,pci-domain = <1>; ti,hwmods = "pcie2"; phys = <&pcie2_phy>; phy-names = "pcie-phy0"; -- cgit v1.2.3 From ad0561d46476c34b45be636117cb78ada3586dec Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 30 Aug 2016 19:13:09 +0900 Subject: ARM: dts: uniphier: use clock/reset controllers The UniPhier reset controller driver has been merged. Enable it. Also, replace the fixed-rate clocks with the dedicated clock drivers. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 53 +++++++++++++++++++++++++--- arch/arm/boot/dts/uniphier-ld4.dtsi | 51 ++++++++++++++++++--------- arch/arm/boot/dts/uniphier-pro4.dtsi | 53 ++++++++++++++++++---------- arch/arm/boot/dts/uniphier-pro5.dtsi | 48 +++++++++++++++---------- arch/arm/boot/dts/uniphier-pxs2.dtsi | 50 ++++++++++++++++---------- arch/arm/boot/dts/uniphier-sld3.dtsi | 60 +++++++++++++++++++++----------- arch/arm/boot/dts/uniphier-sld8.dtsi | 51 ++++++++++++++++++--------- 7 files changed, 254 insertions(+), 112 deletions(-) diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index 7fa6edb73e2b..c46a58a99010 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -1,7 +1,8 @@ /* * Device Tree Source commonly used by UniPhier ARM SoCs * - * Copyright (C) 2015 Masahiro Yamada + * Copyright (C) 2015-2016 Socionext Inc. + * Author: Masahiro Yamada * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual @@ -71,7 +72,7 @@ interrupts = <0 33 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - clocks = <&uart_clk>; + clocks = <&peri_clk 0>; }; serial1: serial@54006900 { @@ -81,7 +82,7 @@ interrupts = <0 35 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - clocks = <&uart_clk>; + clocks = <&peri_clk 1>; }; serial2: serial@54006a00 { @@ -91,7 +92,7 @@ interrupts = <0 37 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - clocks = <&uart_clk>; + clocks = <&peri_clk 2>; }; serial3: serial@54006b00 { @@ -101,7 +102,7 @@ interrupts = <0 177 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - clocks = <&uart_clk>; + clocks = <&peri_clk 3>; }; system_bus: system-bus@58c00000 { @@ -119,6 +120,34 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + #clock-cells = <1>; + }; + + mio_rst: reset { + #reset-cells = <1>; + }; + }; + + perictrl@59820000 { + compatible = "socionext,uniphier-perictrl", + "simple-mfd", "syscon"; + reg = <0x59820000 0x200>; + + peri_clk: clock { + #clock-cells = <1>; + }; + + peri_rst: reset { + #reset-cells = <1>; + }; + }; + timer@60000200 { compatible = "arm,cortex-a9-global-timer"; reg = <0x60000200 0x20>; @@ -149,6 +178,20 @@ /* specify compatible in each SoC DTSI */ }; }; + + sysctrl@61840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0x61840000 0x4000>; + + sys_clk: clock { + #clock-cells = <1>; + }; + + sys_rst: reset { + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 72f8c3579e16..95f342c9d9c1 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -67,18 +67,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; }; @@ -103,7 +91,7 @@ interrupts = <0 41 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -116,7 +104,7 @@ interrupts = <0 42 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -129,7 +117,7 @@ interrupts = <0 43 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 6>; clock-frequency = <400000>; }; @@ -142,7 +130,7 @@ interrupts = <0 44 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -153,6 +141,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb1: usb@5a810100 { @@ -162,6 +152,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; usb2: usb@5a820100 { @@ -171,6 +163,8 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; }; }; @@ -183,6 +177,31 @@ interrupts = <0 29 4>; }; +&mio_clk { + compatible = "socionext,uniphier-ld4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-ld4-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-ld4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-ld4-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-ld4-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-ld4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-ld4-reset"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index 109046d0e41a..ba700267ad66 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -75,18 +75,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -111,7 +99,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -124,7 +112,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -137,7 +125,7 @@ interrupts = <0 43 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -150,7 +138,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -163,7 +151,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -174,7 +162,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; @@ -185,6 +173,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb3: usb@5a810100 { @@ -194,6 +184,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb3>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; }; @@ -201,6 +193,31 @@ clock-frequency = <25000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pro4-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro4-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro4-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro4-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pro4-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pro4-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro4-reset"; +}; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index ce8e549df94f..2c49c3614bda 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -75,18 +75,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <73728000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -123,7 +111,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -136,7 +124,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -149,7 +137,7 @@ interrupts = <0 43 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -162,7 +150,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -175,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -186,7 +174,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; }; @@ -195,6 +183,30 @@ clock-frequency = <20000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pro5-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pro5-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pro5-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pro5-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pro5-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pro5-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pro5-reset"; +}; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index 63c12e8ea029..8789cd518933 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -91,18 +91,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <88900000>; - }; - - i2c_clk: i2c_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; }; }; @@ -127,7 +115,7 @@ interrupts = <0 41 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -140,7 +128,7 @@ interrupts = <0 42 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -153,7 +141,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; interrupts = <0 43 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 6>; clock-frequency = <100000>; }; @@ -166,7 +154,7 @@ interrupts = <0 44 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -177,7 +165,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 45 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 8>; clock-frequency = <400000>; }; @@ -188,7 +176,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 25 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 9>; clock-frequency = <400000>; }; @@ -199,7 +187,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 26 4>; - clocks = <&i2c_clk>; + clocks = <&peri_clk 10>; clock-frequency = <400000>; }; }; @@ -208,6 +196,30 @@ clock-frequency = <25000000>; }; +&mio_clk { + compatible = "socionext,uniphier-pxs2-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-pxs2-mio-reset"; +}; + +&peri_clk { + compatible = "socionext,uniphier-pxs2-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-pxs2-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-pxs2-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-pxs2-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-pxs2-reset"; +}; diff --git a/arch/arm/boot/dts/uniphier-sld3.dtsi b/arch/arm/boot/dts/uniphier-sld3.dtsi index 55f9afa2ee1b..5fa96c939b5c 100644 --- a/arch/arm/boot/dts/uniphier-sld3.dtsi +++ b/arch/arm/boot/dts/uniphier-sld3.dtsi @@ -86,18 +86,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <36864000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; soc { @@ -146,7 +134,7 @@ status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -155,7 +143,7 @@ status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -164,7 +152,7 @@ status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; - clocks = <&uart_clk>; + clocks = <&sys_clk 0>; fifo-size = <64>; }; @@ -175,7 +163,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -186,7 +174,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 42 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -197,7 +185,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 43 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -208,7 +196,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 44 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <100000>; }; @@ -219,7 +207,7 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 45 1>; - clocks = <&iobus_clk>; + clocks = <&sys_clk 1>; clock-frequency = <400000>; }; @@ -236,6 +224,22 @@ reg = <0x59801000 0x400>; }; + mioctrl@59810000 { + compatible = "socionext,uniphier-mioctrl", + "simple-mfd", "syscon"; + reg = <0x59810000 0x800>; + + mio_clk: clock { + compatible = "socionext,uniphier-sld3-mio-clock"; + #clock-cells = <1>; + }; + + mio_rst: reset { + compatible = "socionext,uniphier-sld3-mio-reset"; + #reset-cells = <1>; + }; + }; + usb0: usb@5a800100 { compatible = "socionext,uniphier-ehci", "generic-ehci"; status = "disabled"; @@ -263,5 +267,21 @@ reg = <0x5a830100 0x100>; interrupts = <0 83 4>; }; + + sysctrl@f1840000 { + compatible = "socionext,uniphier-sysctrl", + "simple-mfd", "syscon"; + reg = <0xf1840000 0x4000>; + + sys_clk: clock { + compatible = "socionext,uniphier-sld3-clock"; + #clock-cells = <1>; + }; + + sys_rst: reset { + compatible = "socionext,uniphier-sld3-reset"; + #reset-cells = <1>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 6191051ffc66..d8cf0e7e11ea 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -67,18 +67,6 @@ compatible = "fixed-clock"; clock-frequency = <50000000>; }; - - uart_clk: uart_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <80000000>; - }; - - iobus_clk: iobus_clk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <100000000>; - }; }; }; @@ -103,7 +91,7 @@ interrupts = <0 41 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c0>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 4>; clock-frequency = <100000>; }; @@ -116,7 +104,7 @@ interrupts = <0 42 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 5>; clock-frequency = <100000>; }; @@ -129,7 +117,7 @@ interrupts = <0 43 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 6>; clock-frequency = <400000>; }; @@ -142,7 +130,7 @@ interrupts = <0 44 1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; - clocks = <&iobus_clk>; + clocks = <&peri_clk 7>; clock-frequency = <100000>; }; @@ -153,6 +141,8 @@ interrupts = <0 80 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb0>; + clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; + resets = <&mio_rst 7>, <&mio_rst 8>, <&mio_rst 12>, <&sys_rst 8>; }; usb1: usb@5a810100 { @@ -162,6 +152,8 @@ interrupts = <0 81 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb1>; + clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; + resets = <&mio_rst 7>, <&mio_rst 9>, <&mio_rst 13>, <&sys_rst 8>; }; usb2: usb@5a820100 { @@ -171,6 +163,8 @@ interrupts = <0 82 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usb2>; + clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; + resets = <&mio_rst 7>, <&mio_rst 10>, <&mio_rst 14>, <&sys_rst 8>; }; }; @@ -182,6 +176,31 @@ interrupts = <0 29 4>; }; +&mio_clk { + compatible = "socionext,uniphier-sld8-mio-clock"; +}; + +&mio_rst { + compatible = "socionext,uniphier-sld8-mio-reset"; + resets = <&sys_rst 7>; +}; + +&peri_clk { + compatible = "socionext,uniphier-sld8-peri-clock"; +}; + +&peri_rst { + compatible = "socionext,uniphier-sld8-peri-reset"; +}; + &pinctrl { compatible = "socionext,uniphier-sld8-pinctrl"; }; + +&sys_clk { + compatible = "socionext,uniphier-sld8-clock"; +}; + +&sys_rst { + compatible = "socionext,uniphier-sld8-reset"; +}; -- cgit v1.2.3 From cb1659377c7d5ba68d756b64465d74cfcc14556a Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Wed, 31 Aug 2016 05:01:06 +0900 Subject: ARM: dts: uniphier: add specific compatible to SoC-Glue node This is a simple MFD, but add a specific compatible just in case. Signed-off-by: Masahiro Yamada --- arch/arm/boot/dts/uniphier-common32.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi index c46a58a99010..8c8a85176b64 100644 --- a/arch/arm/boot/dts/uniphier-common32.dtsi +++ b/arch/arm/boot/dts/uniphier-common32.dtsi @@ -171,7 +171,8 @@ }; soc-glue@5f800000 { - compatible = "simple-mfd", "syscon"; + compatible = "socionext,uniphier-soc-glue", + "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; pinctrl: pinctrl { -- cgit v1.2.3 From d7ec05cbd10a7c2e45353394a1937641beb3142c Mon Sep 17 00:00:00 2001 From: Milo Kim Date: Wed, 31 Aug 2016 15:08:47 +0900 Subject: ARM: dts: exynos: Enable HDMI for Arndale Octa board * GPIO for HDMI hot plug detect GPX3_7 is used. The HPD awareness is done when the GPIO is active high. * Enable HDMI block in Exynos5420 HDMI VDD and PLL consume 1.0V LDO6 (PVDD_ANAIP_1V0) and HDMI oscillator requires 1.8V LDO7 (PVDD_ANAIP_1V8). * Support HDMI display data channel I2C #2 is assigned for the HDMI DDC. It enables the EDID access. Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Rob Herring Cc: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Milo Kim Reviewed-by: Andrzej Hajda Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 39a3b81478fd..d2ad48e19572 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -70,6 +70,15 @@ status = "disabled"; }; +&hdmi { + hpd-gpios = <&gpx3 7 GPIO_ACTIVE_HIGH>; + vdd_osc-supply = <&ldo7_reg>; + vdd_pll-supply = <&ldo6_reg>; + vdd-supply = <&ldo6_reg>; + ddc = <&i2c_2>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -347,6 +356,10 @@ }; }; +&i2c_2 { + status = "okay"; +}; + &mmc_0 { status = "okay"; broken-cd; -- cgit v1.2.3 From dbb9c1963285d5d1d3a8c12ad72ddacbd46fc845 Mon Sep 17 00:00:00 2001 From: "J.D. Schroeder" Date: Tue, 30 Aug 2016 17:58:00 +0300 Subject: ARM: dts: dra7: Fix clock data for gmac_gmii_ref_clk_div This commit fixes the clock data inside the DRA7xx clocks device tree structure for the gmac_gmii_ref_clk_div clock. This clock is actually the GMAC_MAIN_CLK and has nothing to do with the register at address 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is set to 1 in order to use the GMAC_RMII_CLK instead of the GMAC_RMII_HS_CLK, the kernel generates a clock divider warning: WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0() gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to have the parent of dpll_gmac_m2_ck always divided by 2 the warning is resolved and the clock tree is fixed up. Additionally, a new clock called rmii_50mhz_clk_mux is defined that does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the source clock for the RMII_50MHZ_CLK. Cc: Lokesh Vutla Signed-off-by: J.D. Schroeder Reviewed-by: Trenton Andres Signed-off-by: Grygorii Strashko Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 8378b44ee567..3f0c61dcd8eb 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1718,13 +1718,20 @@ reg = <0x0c00>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div@13d0 { + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 { #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&dpll_gmac_m2_ck>; + compatible = "ti,mux-clock"; + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>; ti,bit-shift = <24>; reg = <0x13d0>; - ti,dividers = <2>; + }; + + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&dpll_gmac_m2_ck>; + clock-mult = <1>; + clock-div = <2>; }; gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { -- cgit v1.2.3 From c097338ebd3f7a0920dbe1a5d9bf276207f7b024 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Tue, 30 Aug 2016 17:58:01 +0300 Subject: ARM: dts: dra7: cpsw: fix clocks tree Current clocks tree definition for CPSW/CPTS doesn't correspond TRM for dra7/am57 SoCs. CPTS: has to be sourced from gmac_rft_clk_mux clock CPSW: DPLL_GMAC -> CLKOUT_M2 -> GMAC_250M_CLK -> 1/2 -> -> GMAC_MAIN_CLK (125 MHZ) Hence, correct clock tree for GMAC_MAIN_CLK and use proper clock for CPTS. This also require updating of CPTS clock multiplier. Signed-off-by: Grygorii Strashko Reviewed-by: Mugunthan V N Acked-by: Tero Kristo Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 4 ++-- arch/arm/boot/dts/dra7xx-clocks.dtsi | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index fbd5a3e49955..1c1c3c20f267 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1719,7 +1719,7 @@ mac: ethernet@48484000 { compatible = "ti,dra7-cpsw","ti,cpsw"; ti,hwmods = "gmac"; - clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; + clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>; clock-names = "fck", "cpts"; cpdma_channels = <8>; ale_entries = <1024>; @@ -1728,7 +1728,7 @@ mac_control = <0x20>; slaves = <2>; active_slave = <0>; - cpts_clock_mult = <0x80000000>; + cpts_clock_mult = <0x784CFE14>; cpts_clock_shift = <29>; reg = <0x48484000 0x1000 0x48485200 0x2E00>; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 3f0c61dcd8eb..3330738e4c6e 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1003,6 +1003,14 @@ ti,index-power-of-two; }; + gmac_main_clk: gmac_main_clk { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&gmac_250m_dclk_div>; + clock-mult = <1>; + clock-div = <2>; + }; + l3init_480m_dclk_div: l3init_480m_dclk_div@1ac { #clock-cells = <0>; compatible = "ti,divider-clock"; @@ -1726,14 +1734,6 @@ reg = <0x13d0>; }; - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clocks = <&dpll_gmac_m2_ck>; - clock-mult = <1>; - clock-div = <2>; - }; - gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 { #clock-cells = <0>; compatible = "ti,mux-clock"; -- cgit v1.2.3 From 35852c68b2b216845da4f303c0b8c39547022f89 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:15 +0200 Subject: ARM: am335x: Add missing memory node in sl50 board The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" But the sl50 board doesn't have a, so removing the skeleton.dtsi inclusion from am33xx.dtsi will cause a change in the compiled DTB. The board has 512 MiB of RAM and its starting address is 0x80000000, so add a proper memory device node in the DTS. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-sl50.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index f802adb23ff9..e3be7a6bf8f1 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -19,6 +19,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + chosen { stdout-path = &uart0; }; -- cgit v1.2.3 From 766a1fe78fc3e4c0cc688340ff319b3b0863fb03 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:16 +0200 Subject: ARM: omap3: Add missing memory node in overo and torpedo boards The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" But these boards don't have a memory node defined, so removing the skeleton.dtsi inclusion from omap3.dtsi will cause a change in the compiled DTB. Add a dummy memory node so the compiled DTB doesn't change if the skeleton.dtsi is removed from omap3.dtsi. Eventually the correct starting addresses and sizes should be used but I didn't find that information. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 5 +++++ arch/arm/boot/dts/omap3-overo-base.dtsi | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 1c2c74655416..5a63a8d8e177 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -13,6 +13,11 @@ }; }; + memory { + device_type = "memory"; + reg = <0 0>; + }; + leds { compatible = "gpio-leds"; user0 { diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 3e946cac55f3..91b2e423c7c0 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -11,6 +11,12 @@ */ / { + + memory { + device_type = "memory"; + reg = <0 0>; + }; + pwmleds { compatible = "pwm-leds"; -- cgit v1.2.3 From d1f3156fc8c77fb08ef616b115634cba7f9b8a29 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:17 +0200 Subject: ARM: dts: omap2: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 578fa2a54dce..4f793a025a72 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -12,11 +12,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,omap2430", "ti,omap2420", "ti,omap2"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart1; -- cgit v1.2.3 From 008a2ebcd677ec8039bb38b9f50b351a75244d90 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:18 +0200 Subject: ARM: dts: omap3: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 16cf2fdfec75..353d818ce5a6 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -12,11 +12,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,omap3430", "ti,omap3"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; -- cgit v1.2.3 From da6269e7e3dd98c435d3f9124f858bb48969e306 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:19 +0200 Subject: ARM: dts: omap4: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 3fdc51cd0fad..0ced079b7ae3 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -10,11 +10,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,omap4430", "ti,omap4"; interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; -- cgit v1.2.3 From 76a8548ea987708117705d061b150306df993a32 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:20 +0200 Subject: ARM: dts: omap5: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 84c10195e79b..71a8f5492c8b 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -11,8 +11,6 @@ #include #include -#include "skeleton.dtsi" - / { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From f8bf01611c99532c509b8c2ddc72ba7d014f6996 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:21 +0200 Subject: ARM: dts: am33xx: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 98748c61ed99..eeef6bc8e410 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -11,11 +11,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,am33xx"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c0; -- cgit v1.2.3 From 76155b378c5908c28ba4d4b8b8e97f4ee46da5a2 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:22 +0200 Subject: ARM: dts: dm814x: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm814x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 68e412c9863c..ff90a6ce6bdc 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -7,11 +7,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,dm814"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; -- cgit v1.2.3 From 06bfb9c19957e0b8be0ffc32107d96624a5549ba Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:23 +0200 Subject: ARM: dts: dm816x: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm816x.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 44e39c743b53..f1e0f771ff29 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -7,11 +7,11 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,dm816"; interrupt-parent = <&intc>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c1; -- cgit v1.2.3 From 55871eb6e2ccde1a18e043ad5cadd683f04387d9 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:24 +0200 Subject: ARM: dts: dra7: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 1c1c3c20f267..147df90d2126 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -10,8 +10,6 @@ #include #include -#include "skeleton.dtsi" - #define MAX_SOURCES 400 / { -- cgit v1.2.3 From 75813028bbd7caed9382dd45e3f4bb1de38b9002 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:25 +0200 Subject: ARM: dts: am4372: Remove skeleton.dtsi usage The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it shouldn't have functional changes. Since no am4372 based board had a memory node defined, a dummy node is added so the compiled DTB memory node is the same than before. Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index d8689878d67b..dda607d254ae 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -11,12 +11,16 @@ #include #include -#include "skeleton.dtsi" - / { compatible = "ti,am4372", "ti,am43"; interrupt-parent = <&wakeupgen>; + #address-cells = <1>; + #size-cells = <1>; + memory { + device_type = "memory"; + reg = <0 0>; + }; aliases { i2c0 = &i2c0; -- cgit v1.2.3 From 101ace8d1336ce95a596adf1a11f12226979ff9f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:26 +0200 Subject: ARM: dts: omap2: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap2420-h4.dts | 2 +- arch/arm/boot/dts/omap2420-n8x0-common.dtsi | 2 +- arch/arm/boot/dts/omap2430-sdp.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts index 34cdecb4fdda..9265c0b9c3f3 100644 --- a/arch/arm/boot/dts/omap2420-h4.dts +++ b/arch/arm/boot/dts/omap2420-h4.dts @@ -13,7 +13,7 @@ model = "TI OMAP2420 H4 board"; compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index db95aadcca70..7e5ffc583c90 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -1,7 +1,7 @@ #include "omap2420.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts index 6b36ede58488..4f7d9d7c00c7 100644 --- a/arch/arm/boot/dts/omap2430-sdp.dts +++ b/arch/arm/boot/dts/omap2430-sdp.dts @@ -13,7 +13,7 @@ model = "TI OMAP2430 SDP"; compatible = "ti,omap2430-sdp", "ti,omap2430", "ti,omap2"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; -- cgit v1.2.3 From 81777ff9dde770d585e9c50c76218211ad157dca Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:27 +0200 Subject: ARM: dts: omap3: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/logicpd-torpedo-som.dtsi | 2 +- arch/arm/boot/dts/omap3-beagle-xm.dts | 2 +- arch/arm/boot/dts/omap3-beagle.dts | 2 +- arch/arm/boot/dts/omap3-cm-t3x.dtsi | 2 +- arch/arm/boot/dts/omap3-devkit8000-common.dtsi | 2 +- arch/arm/boot/dts/omap3-evm-37xx.dts | 2 +- arch/arm/boot/dts/omap3-evm.dts | 2 +- arch/arm/boot/dts/omap3-gta04.dtsi | 2 +- arch/arm/boot/dts/omap3-igep.dtsi | 2 +- arch/arm/boot/dts/omap3-ldp.dts | 2 +- arch/arm/boot/dts/omap3-lilly-a83x.dtsi | 2 +- arch/arm/boot/dts/omap3-n900.dts | 2 +- arch/arm/boot/dts/omap3-n950-n9.dtsi | 2 +- arch/arm/boot/dts/omap3-overo-base.dtsi | 2 +- arch/arm/boot/dts/omap3-pandora-common.dtsi | 2 +- arch/arm/boot/dts/omap3-sniper.dts | 2 +- arch/arm/boot/dts/omap3-tao3530.dtsi | 2 +- arch/arm/boot/dts/omap3-zoom3.dts | 2 +- arch/arm/boot/dts/omap3430-sdp.dts | 2 +- 19 files changed, 19 insertions(+), 19 deletions(-) diff --git a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi index 5a63a8d8e177..731ec37aed5b 100644 --- a/arch/arm/boot/dts/logicpd-torpedo-som.dtsi +++ b/arch/arm/boot/dts/logicpd-torpedo-som.dtsi @@ -13,7 +13,7 @@ }; }; - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 8ffde06281ad..85e297ed0ea1 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index a19d907d4850..4be85ce59dd1 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index 6a0df13fa0f3..57b9a028a49a 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -4,7 +4,7 @@ / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi index 586010179752..f330c69cc683 100644 --- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi +++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi @@ -10,7 +10,7 @@ #include "omap34xx.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index ed449827c3d3..4f9a76544602 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -15,7 +15,7 @@ model = "TI OMAP37XX EVM (TMDSEVM3730)"; compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts index e10dcd0fa539..99b2bfcd1059 100644 --- a/arch/arm/boot/dts/omap3-evm.dts +++ b/arch/arm/boot/dts/omap3-evm.dts @@ -14,7 +14,7 @@ model = "TI OMAP35XX EVM (TMDSEVM3530)"; compatible = "ti,omap3-evm", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index c09a0574af90..5563e2533ebd 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -21,7 +21,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index f4f2ce46d681..54c4c07bbe4a 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -13,7 +13,7 @@ #include "omap36xx.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index 2f353dadfa40..e28fe13cb007 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -15,7 +15,7 @@ model = "TI OMAP3430 LDP (Zoom1 Labrador)"; compatible = "ti,omap3-ldp", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index eff816e0bc0a..fa611a5e4850 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -17,7 +17,7 @@ bootargs = "console=ttyO0,115200n8 vt.global_cursor_default=0 consoleblank=0"; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 2a6078a8422c..87ca50b53002 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -54,7 +54,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 284849008fc5..5d8c4b4a4205 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -24,7 +24,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/omap3-overo-base.dtsi b/arch/arm/boot/dts/omap3-overo-base.dtsi index 91b2e423c7c0..401fae838fe9 100644 --- a/arch/arm/boot/dts/omap3-overo-base.dtsi +++ b/arch/arm/boot/dts/omap3-overo-base.dtsi @@ -12,7 +12,7 @@ / { - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi index af30d4d99307..53e007abdc71 100644 --- a/arch/arm/boot/dts/omap3-pandora-common.dtsi +++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi @@ -18,7 +18,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3-sniper.dts b/arch/arm/boot/dts/omap3-sniper.dts index 78a1184cb312..bc4498e77bc9 100644 --- a/arch/arm/boot/dts/omap3-sniper.dts +++ b/arch/arm/boot/dts/omap3-sniper.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi index 644d3c8ea66a..dc80886b5329 100644 --- a/arch/arm/boot/dts/omap3-tao3530.dtsi +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -26,7 +26,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/omap3-zoom3.dts b/arch/arm/boot/dts/omap3-zoom3.dts index c29b41dc7b95..45e2ce0803de 100644 --- a/arch/arm/boot/dts/omap3-zoom3.dts +++ b/arch/arm/boot/dts/omap3-zoom3.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index a0dc8d854142..abd6921143be 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -13,7 +13,7 @@ model = "TI OMAP3430 SDP"; compatible = "ti,omap3430-sdp", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; -- cgit v1.2.3 From 742ae1f945c14dfb3de73484e30a33ee1122ecda Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:28 +0200 Subject: ARM: dts: omap4: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-duovero.dtsi | 2 +- arch/arm/boot/dts/omap4-kc1.dts | 2 +- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 +- arch/arm/boot/dts/omap4-sdp.dts | 2 +- arch/arm/boot/dts/omap4-var-som-om44.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi index a90b582e4c3f..ec0bd9779e1a 100644 --- a/arch/arm/boot/dts/omap4-duovero.dtsi +++ b/arch/arm/boot/dts/omap4-duovero.dtsi @@ -12,7 +12,7 @@ model = "Gumstix Duovero"; compatible = "gumstix,omap4-duovero", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/omap4-kc1.dts b/arch/arm/boot/dts/omap4-kc1.dts index 2251bd54e4e6..e3763ac75719 100644 --- a/arch/arm/boot/dts/omap4-kc1.dts +++ b/arch/arm/boot/dts/omap4-kc1.dts @@ -13,7 +13,7 @@ model = "Amazon Kindle Fire (first generation)"; compatible = "amazon,omap4-kc1", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index f8f13952cfeb..d48e45bd4b3d 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -8,7 +8,7 @@ #include "elpida_ecb240abacn.dtsi" / { - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts index 10d73a784050..d728ec963111 100644 --- a/arch/arm/boot/dts/omap4-sdp.dts +++ b/arch/arm/boot/dts/omap4-sdp.dts @@ -14,7 +14,7 @@ model = "TI OMAP4 SDP board"; compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi index 873cfc87260c..758b6eb7ae43 100644 --- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi +++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi @@ -12,7 +12,7 @@ model = "Variscite VAR-SOM-OM44"; compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; -- cgit v1.2.3 From bfa130bbacda4f3418aa4898c81f9013319ee3b7 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:29 +0200 Subject: ARM: dts: omap5: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-cm-t54.dts | 2 +- arch/arm/boot/dts/omap5-igep0050.dts | 2 +- arch/arm/boot/dts/omap5-uevm.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index fe724da3ec0d..c9390fa9c362 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -11,7 +11,7 @@ model = "CompuLab CM-T54"; compatible = "compulab,omap5-cm-t54", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x7F000000>; /* 2048 MB */ }; diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index f75ce02fb398..7aa2b0c813ab 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -13,7 +13,7 @@ model = "IGEPv5"; compatible = "isee,omap5-igep0050", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x7f000000>; /* 2032 MB */ }; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index a51e60518eb6..5230ca00913a 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -13,7 +13,7 @@ model = "TI OMAP5 uEVM board"; compatible = "ti,omap5-uevm", "ti,omap5"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x7F000000>; /* 2032 MB */ }; -- cgit v1.2.3 From 278cb79cc113a56467b93244ac3812bc049eb20a Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:30 +0200 Subject: ARM: dts: am335x: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-baltos.dtsi | 2 +- arch/arm/boot/dts/am335x-bone-common.dtsi | 2 +- arch/arm/boot/dts/am335x-chilisom.dtsi | 2 +- arch/arm/boot/dts/am335x-cm-t335.dts | 2 +- arch/arm/boot/dts/am335x-evm.dts | 2 +- arch/arm/boot/dts/am335x-evmsk.dts | 2 +- arch/arm/boot/dts/am335x-icev2.dts | 2 +- arch/arm/boot/dts/am335x-igep0033.dtsi | 2 +- arch/arm/boot/dts/am335x-lxm.dts | 2 +- arch/arm/boot/dts/am335x-nano.dts | 2 +- arch/arm/boot/dts/am335x-pepper.dts | 2 +- arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +- arch/arm/boot/dts/am335x-shc.dts | 2 +- arch/arm/boot/dts/am335x-sl50.dts | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi index df0dd2a54b00..dd45d172a892 100644 --- a/arch/arm/boot/dts/am335x-baltos.dtsi +++ b/arch/arm/boot/dts/am335x-baltos.dtsi @@ -24,7 +24,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index 8d21aca69f37..007b5e5a51a9 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -13,7 +13,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index 1d647358f1c1..f9ee5859c154 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/am335x-cm-t335.dts b/arch/arm/boot/dts/am335x-cm-t335.dts index 4c0d6d7a37c2..947c81b7aaaf 100644 --- a/arch/arm/boot/dts/am335x-cm-t335.dts +++ b/arch/arm/boot/dts/am335x-cm-t335.dts @@ -17,7 +17,7 @@ model = "CompuLab CM-T335"; compatible = "compulab,cm-t335", "ti,am33xx"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x8000000>; /* 128 MB */ }; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 944914e5b15a..3cf896a2a204 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index c9b11107803d..0e5e8dcdcc24 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -27,7 +27,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts index 426022ee85c7..85e04c205542 100644 --- a/arch/arm/boot/dts/am335x-icev2.dts +++ b/arch/arm/boot/dts/am335x-icev2.dts @@ -19,7 +19,7 @@ model = "TI AM3359 ICE-V2"; compatible = "ti,am3359-icev2", "ti,am33xx"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index df95818b4f67..a5769a8f5fc8 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts index 6594ce7449f3..1d6c6fa703e4 100644 --- a/arch/arm/boot/dts/am335x-lxm.dts +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index 71e082ca3f34..483d585c8908 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts index ddfdf3ca3d66..30e2f8770aaf 100644 --- a/arch/arm/boot/dts/am335x-pepper.dts +++ b/arch/arm/boot/dts/am335x-pepper.dts @@ -20,7 +20,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi index 29c2ea7950f6..75e24add3f13 100644 --- a/arch/arm/boot/dts/am335x-phycore-som.dtsi +++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi @@ -25,7 +25,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am335x-shc.dts b/arch/arm/boot/dts/am335x-shc.dts index f9a15afb66c7..bf8727a19ece 100644 --- a/arch/arm/boot/dts/am335x-shc.dts +++ b/arch/arm/boot/dts/am335x-shc.dts @@ -102,7 +102,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; diff --git a/arch/arm/boot/dts/am335x-sl50.dts b/arch/arm/boot/dts/am335x-sl50.dts index e3be7a6bf8f1..b0dfa6f14cd5 100644 --- a/arch/arm/boot/dts/am335x-sl50.dts +++ b/arch/arm/boot/dts/am335x-sl50.dts @@ -19,7 +19,7 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x20000000>; /* 512 MB */ }; -- cgit v1.2.3 From a60b9f45cc08f7710b7731ac13bc431b87b1c328 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:31 +0200 Subject: ARM: dts: am3517: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am3517-craneboard.dts | 2 +- arch/arm/boot/dts/am3517-evm.dts | 2 +- arch/arm/boot/dts/am3517_mt_ventoux.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts index f9d8f3948c4a..083ff5073435 100644 --- a/arch/arm/boot/dts/am3517-craneboard.dts +++ b/arch/arm/boot/dts/am3517-craneboard.dts @@ -15,7 +15,7 @@ model = "TI AM3517 CraneBoard (TMDSEVM3517)"; compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts index b4127c6493a2..0e4a125f78e3 100644 --- a/arch/arm/boot/dts/am3517-evm.dts +++ b/arch/arm/boot/dts/am3517-evm.dts @@ -13,7 +13,7 @@ model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)"; compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; diff --git a/arch/arm/boot/dts/am3517_mt_ventoux.dts b/arch/arm/boot/dts/am3517_mt_ventoux.dts index fdf5ce63c8e6..3395783c5b4e 100644 --- a/arch/arm/boot/dts/am3517_mt_ventoux.dts +++ b/arch/arm/boot/dts/am3517_mt_ventoux.dts @@ -13,7 +13,7 @@ model = "TeeJet Mt.Ventoux"; compatible = "teejet,mt_ventoux", "ti,omap3"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB */ }; -- cgit v1.2.3 From 9194cf4daa93652a5ebdf410e91708169c5bb04f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:32 +0200 Subject: ARM: dts: am4372: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am4372.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index dda607d254ae..a275fa956813 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -17,7 +17,7 @@ #address-cells = <1>; #size-cells = <1>; - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; -- cgit v1.2.3 From 0b086802cbed1fa06916d68c3d89f8be3fd6c2ac Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:33 +0200 Subject: ARM: dts: am572x: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am572x-idk.dts | 2 +- arch/arm/boot/dts/am57xx-beagle-x15.dts | 2 +- arch/arm/boot/dts/am57xx-cl-som-am57x.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts index e3acb99703e1..87bbc66f0f21 100644 --- a/arch/arm/boot/dts/am572x-idk.dts +++ b/arch/arm/boot/dts/am572x-idk.dts @@ -18,7 +18,7 @@ compatible = "ti,am5728-idk", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 8b115e1b48a3..9067ca092dc5 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -23,7 +23,7 @@ display0 = &hdmi0; }; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; }; diff --git a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts index 832d766cd31e..203266f88480 100644 --- a/arch/arm/boot/dts/am57xx-cl-som-am57x.dts +++ b/arch/arm/boot/dts/am57xx-cl-som-am57x.dts @@ -19,7 +19,7 @@ model = "CompuLab CL-SOM-AM57x"; compatible = "compulab,cl-som-am57x", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB - minimal configuration */ }; -- cgit v1.2.3 From c5ee1b486fc1f5ce6cbbf718b630ea6dfa3bec5d Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:34 +0200 Subject: ARM: dts: dm8148: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm8148-evm.dts | 2 +- arch/arm/boot/dts/dm8148-t410.dts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/dm8148-evm.dts b/arch/arm/boot/dts/dm8148-evm.dts index 376b85381e8c..d6657b3bae84 100644 --- a/arch/arm/boot/dts/dm8148-evm.dts +++ b/arch/arm/boot/dts/dm8148-evm.dts @@ -12,7 +12,7 @@ model = "DM8148 EVM"; compatible = "ti,dm8148-evm", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; diff --git a/arch/arm/boot/dts/dm8148-t410.dts b/arch/arm/boot/dts/dm8148-t410.dts index b1ce1398b3ed..63883b3479f9 100644 --- a/arch/arm/boot/dts/dm8148-t410.dts +++ b/arch/arm/boot/dts/dm8148-t410.dts @@ -11,7 +11,7 @@ model = "HP t410 Smart Zero Client"; compatible = "hp,t410", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; -- cgit v1.2.3 From f193a5ab3c1bdd539058c892cd495662f7b984a3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:35 +0200 Subject: ARM: dts: dm8168: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dm8168-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts index 1380922827be..0bf55fa72dea 100644 --- a/arch/arm/boot/dts/dm8168-evm.dts +++ b/arch/arm/boot/dts/dm8168-evm.dts @@ -12,7 +12,7 @@ model = "DM8168 EVM"; compatible = "ti,dm8168-evm", "ti,dm8168"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000 /* 1 GB */ 0xc0000000 0x40000000>; /* 1 GB */ -- cgit v1.2.3 From 387117c1272746266ca97844ac106b04ac3500e3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:36 +0200 Subject: ARM: dts: dra62x: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra62x-j5eco-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/dra62x-j5eco-evm.dts b/arch/arm/boot/dts/dra62x-j5eco-evm.dts index 68e31d122762..155eb32ee213 100644 --- a/arch/arm/boot/dts/dra62x-j5eco-evm.dts +++ b/arch/arm/boot/dts/dra62x-j5eco-evm.dts @@ -12,7 +12,7 @@ model = "DRA62x J5 Eco EVM"; compatible = "ti,dra62x-j5eco-evm", "ti,dra62x", "ti,dm8148"; - memory { + memory@80000000 { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ }; -- cgit v1.2.3 From 5c4d9f0d49b0c3beda734687248fc74542566ee9 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 31 Aug 2016 12:35:37 +0200 Subject: ARM: dts: dra7: Add missing unit name to memory nodes This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7-evm.dts | 2 +- arch/arm/boot/dts/dra72-evm-revc.dts | 2 +- arch/arm/boot/dts/dra72-evm.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index 3350722e10b7..132f2be10889 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -16,7 +16,7 @@ model = "TI DRA742"; compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ }; diff --git a/arch/arm/boot/dts/dra72-evm-revc.dts b/arch/arm/boot/dts/dra72-evm-revc.dts index f9cfd3bb4dc2..064b322a7a04 100644 --- a/arch/arm/boot/dts/dra72-evm-revc.dts +++ b/arch/arm/boot/dts/dra72-evm-revc.dts @@ -11,7 +11,7 @@ / { model = "TI DRA722 Rev C EVM"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x80000000>; /* 2GB */ }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index cc1d32ca4a8a..e3a9b6985693 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -9,7 +9,7 @@ / { model = "TI DRA722"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; /* 1024 MB */ }; -- cgit v1.2.3 From a37b7a5a86d5455d9b1dc840de1946312fa51b23 Mon Sep 17 00:00:00 2001 From: Milo Kim Date: Wed, 31 Aug 2016 17:25:18 +0900 Subject: ARM: dts: sun8i: Add PWM controller node in H3 Acked-by: Chen-Yu Tsai Signed-off-by: Milo Kim Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index fdf9fdbda267..6d83b8674201 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -389,6 +389,14 @@ interrupts = ; }; + pwm: pwm@01c21400 { + compatible = "allwinner,sun8i-h3-pwm"; + reg = <0x01c21400 0x8>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@01c28000 { compatible = "snps,dw-apb-uart"; reg = <0x01c28000 0x400>; -- cgit v1.2.3 From 644978440c7f621281a7b068b92a12250e8d4793 Mon Sep 17 00:00:00 2001 From: Grygorii Strashko Date: Wed, 31 Aug 2016 16:29:59 -0400 Subject: ARM: dts: keystone: specify usb mode explicitly The USB OTG mode is not supported by Kestone 2 devices, as result, the USB devices enumeration and detection will not work properly when kernel is built with CONFIG_USB_DWC3_DUAL_ROLE=y (default for multi platform build): - it's required to load gadget drivers manually to make host mode work and this confuses current Keystone 2 users - device mode is not working, because port can't detect and switch to peripheral/host mode dynamically. Hence, specify usb mode explicitly in DT: usb0 = "host" for all KS2 devices and usb1 = "peripheral" for K2E. Cc: Sekhar Nori Cc: Roger Quadros Signed-off-by: Grygorii Strashko Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2e-evm.dts | 12 ++++++++++-- arch/arm/boot/dts/keystone-k2e.dtsi | 4 ++-- arch/arm/boot/dts/keystone-k2hk-evm.dts | 6 +++++- arch/arm/boot/dts/keystone-k2l-evm.dts | 6 +++++- arch/arm/boot/dts/keystone.dtsi | 4 ++-- 5 files changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/keystone-k2e-evm.dts b/arch/arm/boot/dts/keystone-k2e-evm.dts index 4c32ebc1425a..ae1ebe7ee021 100644 --- a/arch/arm/boot/dts/keystone-k2e-evm.dts +++ b/arch/arm/boot/dts/keystone-k2e-evm.dts @@ -47,18 +47,26 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &usb1_phy { status = "okay"; }; -&usb1 { +&keystone_usb1 { status = "okay"; }; +&usb1 { + dr_mode = "peripheral"; +}; + &i2c0 { dtt@50 { compatible = "at,24c1024"; diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi index 9a51b8c88581..497c417db5b6 100644 --- a/arch/arm/boot/dts/keystone-k2e.dtsi +++ b/arch/arm/boot/dts/keystone-k2e.dtsi @@ -61,7 +61,7 @@ status = "disabled"; }; - usb1: usb@25000000 { + keystone_usb1: usb@25000000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -74,7 +74,7 @@ dma-ranges; status = "disabled"; - dwc3@25010000 { + usb1: dwc3@25010000 { compatible = "synopsys,dwc3"; reg = <0x25010000 0x70000>; interrupts = ; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index b38b3441818b..2156ff92d08f 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -83,10 +83,14 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &aemif { cs0 { #address-cells = <2>; diff --git a/arch/arm/boot/dts/keystone-k2l-evm.dts b/arch/arm/boot/dts/keystone-k2l-evm.dts index 7f9c2e94d605..056b42f99d7a 100644 --- a/arch/arm/boot/dts/keystone-k2l-evm.dts +++ b/arch/arm/boot/dts/keystone-k2l-evm.dts @@ -32,10 +32,14 @@ status = "okay"; }; -&usb { +&keystone_usb0 { status = "okay"; }; +&usb0 { + dr_mode = "host"; +}; + &i2c0 { dtt@50 { compatible = "at,24c1024"; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 00cb314d5e4d..b93b33f0124a 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -196,7 +196,7 @@ status = "disabled"; }; - usb: usb@2680000 { + keystone_usb0: usb@2680000 { compatible = "ti,keystone-dwc3"; #address-cells = <1>; #size-cells = <1>; @@ -209,7 +209,7 @@ dma-ranges; status = "disabled"; - dwc3@2690000 { + usb0: dwc3@2690000 { compatible = "synopsys,dwc3"; reg = <0x2690000 0x70000>; interrupts = ; -- cgit v1.2.3 From 08fa198ded16cb0ec573c10f2f4a8523b319b2c6 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 31 Aug 2016 16:29:59 -0400 Subject: ARM: dts: keystone-k2g: Add device state controller node Add the device state controller node as a syscon node to the K2G SoC. This module provides similar device control functionality as that on the existing K2 SoCs. One example usage would be the boot address programming of the DSP processor sub-system. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 3372615b885c..fe17dc402a23 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -83,6 +83,11 @@ pinctrl-single,function-mask = <0x001b0007>; }; + devctrl: device-state-control@02620000 { + compatible = "ti,keystone-devctrl", "syscon"; + reg = <0x02620000 0x1000>; + }; + uart0: serial@02530c00 { compatible = "ns16550a"; current-speed = <115200>; -- cgit v1.2.3 From 0884b1b3382ffe1fd5b639192c9272a82cbe2349 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 31 Aug 2016 16:29:59 -0400 Subject: ARM: dts: keystone-k2g: Add keystone IRQ controller node Add the Keystone IRQ controller IP node on K2G SoC. This allows the ARM CorePac core to receive interrupts from remote processor devices (eg: DSP) on the SoC. The IP is identical in functionality to that of the equivalent nodes on existing K2 SoCs. The only difference is the ARM INTC interrupt id/event number. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index fe17dc402a23..eccda9cf06dc 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -98,5 +98,13 @@ clock-frequency = <200000000>; status = "disabled"; }; + + kirq0: keystone_irq@026202a0 { + compatible = "ti,keystone-irq"; + interrupts = ; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; }; }; -- cgit v1.2.3 From e0f0b54c026c9665cbb88303481a0f984190e056 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Wed, 31 Aug 2016 16:29:59 -0400 Subject: ARM: dts: keystone-k2g: Add DSP GPIO controller node Add the DSP GPIO controller node on K2G SoC. This is used to send interrupts to the only DSP processor subsystem present on the SoC. The IP is identical to that of the equivalent nodes on existing K2 SoCs. Signed-off-by: Andrew F. Davis Signed-off-by: Suman Anna Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index eccda9cf06dc..025ad12bd086 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -106,5 +106,12 @@ #interrupt-cells = <1>; ti,syscon-dev = <&devctrl 0x2a0>; }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; }; }; -- cgit v1.2.3 From 11b897a2f7c6d6be93f9f6754438f96eed9236df Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Wed, 31 Aug 2016 16:32:04 -0400 Subject: ARM: dts: keystone-k2g: Add Message Manager node Introduce the message manager node for the A15 queues on which Linux runs. The Message Manager is primarily used for communication with Power Management controller on K2G. Signed-off-by: Nishanth Menon Signed-off-by: Santosh Shilimkar --- arch/arm/boot/dts/keystone-k2g.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi index 025ad12bd086..2919c5190653 100644 --- a/arch/arm/boot/dts/keystone-k2g.dtsi +++ b/arch/arm/boot/dts/keystone-k2g.dtsi @@ -113,5 +113,17 @@ #gpio-cells = <2>; gpio,syscon-dev = <&devctrl 0x240>; }; + + msgmgr: msgmgr@02a00000 { + compatible = "ti,k2g-message-manager"; + #mbox-cells = <2>; + reg-names = "queue_proxy_region", + "queue_state_debug_region"; + reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; + interrupt-names = "rx_005", + "rx_057"; + interrupts = , + ; + }; }; }; -- cgit v1.2.3 From 47aabaf5a87be6caa9df34a131cb96e3a801b5e9 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Wed, 31 Aug 2016 15:25:18 +0200 Subject: ARM: dts: exynos: Add all required FIMC-IS clocks to exynos4x12 FIMC-IS blocks must control 3 more clocks ("gicisp", "mcuctl_isp" and "pwm_isp") to make the hardware fully operational. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4x12.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index c452499ae8c9..3394bdcf10ae 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -157,7 +157,9 @@ <&clock CLK_MOUT_MPLL_USER_T>, <&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>, <&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>, - <&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>, + <&clock CLK_GICISP>, <&clock CLK_MCUCTL_ISP>, + <&clock CLK_PWM_ISP>, + <&clock CLK_DIV_ISP0>, <&clock CLK_DIV_ISP1>, <&clock CLK_DIV_MCUISP0>, <&clock CLK_DIV_MCUISP1>, <&clock CLK_UART_ISP_SCLK>, @@ -167,6 +169,7 @@ clock-names = "lite0", "lite1", "ppmuispx", "ppmuispmx", "mpll", "isp", "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", "ispdiv0", "ispdiv1", "mcuispdiv0", "mcuispdiv1", "uart", "aclk200", "div_aclk200", "aclk400mcuisp", -- cgit v1.2.3 From 91e723c609e2a971e28a403160bfd0f97b509c97 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:50 +0200 Subject: ARM: dts: exynos: Add missing memory node for Exynos5440 boards The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" But these boards don't have a memory node defined, so removing the skeleton.dtsi inclusion in exynos5440.dtsi will cause a change in the compiled DTB. Add a dummy memory node so the compiled DTB does not change if the skeleton.dtsi is removed from exynos5440.dtsi. Eventually the correct starting addresses and sizes should be used but I didn't find that information. Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5440-sd5v1.dts | 6 ++++++ arch/arm/boot/dts/exynos5440-ssdk5440.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index a98501bab6fc..afd21a41e05b 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts @@ -20,6 +20,12 @@ bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; + /* FIXME: set reg property with correct start address and size */ + memory { + device_type = "memory"; + reg = <0 0>; + }; + fixed-rate-clocks { xtal { compatible = "samsung,clock-xtal"; diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index 6a0d802e87c8..bdb3bf622e2f 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -21,6 +21,12 @@ bootargs = "root=/dev/sda2 rw rootwait ignore_loglevel earlyprintk no_console_suspend mem=2048M@0x80000000 mem=6144M@0x100000000 console=ttySAC0,115200"; }; + /* FIXME: set reg property with correct start address and size */ + memory { + device_type = "memory"; + reg = <0 0>; + }; + fixed-rate-clocks { xtal { compatible = "samsung,clock-xtal"; -- cgit v1.2.3 From 33c3de7e6b3bb836957b32ff7195ff92e4437d74 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:51 +0200 Subject: ARM: dts: exynos: Remove skeleton.dtsi usage for Exynos3 The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 1 + arch/arm/boot/dts/exynos3250-monk.dts | 1 + arch/arm/boot/dts/exynos3250-rinato.dts | 1 + arch/arm/boot/dts/exynos3250.dtsi | 3 ++- 4 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index 130e946f1414..bedc13bef5d9 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -25,6 +25,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 8c8906266310..249fcfd5b297 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -28,6 +28,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index a92181368e5b..ae125ece061d 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -28,6 +28,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 70e3aceab3a9..e9d2556c0dfd 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -17,7 +17,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos4-cpu-thermal.dtsi" #include "exynos-syscon-restart.dtsi" #include @@ -25,6 +24,8 @@ / { compatible = "samsung,exynos3250"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; -- cgit v1.2.3 From 1354835a8911afd0e02514b530539b0d42b0a8ec Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:52 +0200 Subject: ARM: dts: exynos: Remove skeleton.dtsi usage for Exynos4 The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4.dtsi | 3 ++- arch/arm/boot/dts/exynos4210-origen.dts | 1 + arch/arm/boot/dts/exynos4210-smdkv310.dts | 1 + arch/arm/boot/dts/exynos4210-trats.dts | 1 + arch/arm/boot/dts/exynos4210-universal_c210.dts | 1 + arch/arm/boot/dts/exynos4412-odroidu3.dts | 1 + arch/arm/boot/dts/exynos4412-odroidx.dts | 1 + arch/arm/boot/dts/exynos4412-odroidx2.dts | 1 + arch/arm/boot/dts/exynos4412-origen.dts | 1 + arch/arm/boot/dts/exynos4412-smdk4412.dts | 1 + arch/arm/boot/dts/exynos4412-tiny4412.dts | 1 + arch/arm/boot/dts/exynos4412-trats2.dts | 1 + arch/arm/boot/dts/exynos4415.dtsi | 3 ++- 13 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 32f22e12c70b..5f034eb5a5e2 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -21,11 +21,12 @@ #include #include -#include "skeleton.dtsi" #include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { spi0 = &spi_0; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index be2751eebaf8..6b2c41a87a3e 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -25,6 +25,7 @@ compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 0x60000000 0x10000000 diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 847fae3dd1f1..3c759baeadcc 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -24,6 +24,7 @@ compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 79d983036560..5f7ddb0627fb 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -21,6 +21,7 @@ compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 0x60000000 0x10000000 diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index cf95202fa310..30d938e17c9f 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -21,6 +21,7 @@ compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index d73aa6c58fe3..cc1b87e09534 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -19,6 +19,7 @@ compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 2af235151301..518ca57837be 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -19,6 +19,7 @@ compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x3FF00000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index 3e3584270e00..92cdeea1cfb3 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -18,6 +18,7 @@ compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 26a36fed9652..9156a35a6117 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -23,6 +23,7 @@ compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 231ffbdbf9d0..2e868c4c307e 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -21,6 +21,7 @@ compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 4840bbdaa9ec..ad60f3840e24 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -24,6 +24,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 129e973a06a6..e1380bae8ee3 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -31,6 +31,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi index 28b04b6795c9..3c40f8a956dd 100644 --- a/arch/arm/boot/dts/exynos4415.dtsi +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -16,13 +16,14 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include #include / { compatible = "samsung,exynos4415"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; -- cgit v1.2.3 From 12676ee1a46f13a9b8c3eaf6df686964783e66da Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:53 +0200 Subject: ARM: dts: exynos: Remove skeleton.dtsi usage for Exynos5 The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" The disassembled DTB are almost the same besides an empty chosen node being removed and nodes reordered, so it should not have functional changes. Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5.dtsi | 3 ++- arch/arm/boot/dts/exynos5250-arndale.dts | 1 + arch/arm/boot/dts/exynos5250-smdk5250.dts | 1 + arch/arm/boot/dts/exynos5250-snow-common.dtsi | 1 + arch/arm/boot/dts/exynos5250-spring.dts | 1 + arch/arm/boot/dts/exynos5260-xyref5260.dts | 1 + arch/arm/boot/dts/exynos5260.dtsi | 4 ++-- arch/arm/boot/dts/exynos5410-odroidxu.dts | 1 + arch/arm/boot/dts/exynos5410-smdk5410.dts | 1 + arch/arm/boot/dts/exynos5420-arndale-octa.dts | 1 + arch/arm/boot/dts/exynos5420-peach-pit.dts | 1 + arch/arm/boot/dts/exynos5420-smdk5420.dts | 1 + arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 + arch/arm/boot/dts/exynos5440.dtsi | 3 ++- arch/arm/boot/dts/exynos54xx.dtsi | 1 - arch/arm/boot/dts/exynos5800-peach-pi.dts | 1 + 16 files changed, 18 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index cab91782e20c..8f06609879f5 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -13,11 +13,12 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos-syscon-restart.dtsi" / { interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { i2c0 = &i2c_0; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 3d981f32874d..54397c7e8d7c 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -21,6 +21,7 @@ compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 7f27263728a1..b85b78a57299 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -23,6 +23,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 1055d25c0ccc..5324eb488e30 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -20,6 +20,7 @@ }; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 1d52a79b2f18..bdc55fa7c576 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -21,6 +21,7 @@ compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 3daef94bee38..d7f62918ed4b 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -17,6 +17,7 @@ compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index 36da38e29000..a86a4898d077 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -9,13 +9,13 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" - #include / { compatible = "samsung,exynos5260", "samsung,exynos5"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { pinctrl0 = &pinctrl_0; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index 3912969ec223..bf1612c0d4a4 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -22,6 +22,7 @@ compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x40000000 0x7ea00000>; }; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 777fcf2edd79..6ea1ac4cf1e7 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -17,6 +17,7 @@ compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index d2ad48e19572..10483a230538 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -23,6 +23,7 @@ compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index f6f256fd9b5e..cd0c44b0bfa5 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -80,6 +80,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 29546465d3da..3a744d5611ea 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -20,6 +20,7 @@ compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; memory { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 7bb8a370072a..05ae7284bb1b 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -22,6 +22,7 @@ / { memory { + device_type = "memory"; reg = <0x40000000 0x7EA00000>; }; diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index fd176819b4bf..e6bffd13cedd 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -10,12 +10,13 @@ */ #include -#include "skeleton.dtsi" / { compatible = "samsung,exynos5440", "samsung,exynos5"; interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &serial_0; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 06a604911e87..9d31cdce1959 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -14,7 +14,6 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include "exynos5.dtsi" / { diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 51a8bca4691c..72f89c8803d4 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -80,6 +80,7 @@ }; memory { + device_type = "memory"; reg = <0x20000000 0x80000000>; }; -- cgit v1.2.3 From 2458ff00876bcae594d65511badb8623d1109916 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:54 +0200 Subject: ARM: dts: exynos: Add missing unit name to memory nodes in Exynos3 DTS This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos3250-artik5.dtsi | 2 +- arch/arm/boot/dts/exynos3250-monk.dts | 2 +- arch/arm/boot/dts/exynos3250-rinato.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-artik5.dtsi b/arch/arm/boot/dts/exynos3250-artik5.dtsi index bedc13bef5d9..a70819b1b739 100644 --- a/arch/arm/boot/dts/exynos3250-artik5.dtsi +++ b/arch/arm/boot/dts/exynos3250-artik5.dtsi @@ -24,7 +24,7 @@ stdout-path = &serial_2; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 249fcfd5b297..66f04f6ba6bb 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -27,7 +27,7 @@ i2c7 = &i2c_max77836; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index ae125ece061d..3967ee5f7752 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -27,7 +27,7 @@ i2c7 = &i2c_max77836; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x1ff00000>; }; -- cgit v1.2.3 From 824e4133fadec876e9ec6430866e3573439934f7 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:55 +0200 Subject: ARM: dts: exynos: Add missing unit name to memory nodes in Exynos4 DTS This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos4210-origen.dts | 2 +- arch/arm/boot/dts/exynos4210-smdkv310.dts | 2 +- arch/arm/boot/dts/exynos4210-trats.dts | 2 +- arch/arm/boot/dts/exynos4210-universal_c210.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidu3.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos4412-odroidx2.dts | 2 +- arch/arm/boot/dts/exynos4412-origen.dts | 2 +- arch/arm/boot/dts/exynos4412-smdk4412.dts | 2 +- arch/arm/boot/dts/exynos4412-tiny4412.dts | 2 +- arch/arm/boot/dts/exynos4412-trats2.dts | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 6b2c41a87a3e..a2c6a13fe67b 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -24,7 +24,7 @@ model = "Insignal Origen evaluation board based on Exynos4210"; compatible = "insignal,origen", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 3c759baeadcc..af6ef3e6214d 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -23,7 +23,7 @@ model = "Samsung smdkv310 evaluation board based on Exynos4210"; compatible = "samsung,smdkv310", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index 5f7ddb0627fb..0ca1b4d355f2 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -20,7 +20,7 @@ model = "Samsung Trats based on Exynos4210"; compatible = "samsung,trats", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000 diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 30d938e17c9f..f1172be318cd 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -20,7 +20,7 @@ model = "Samsung Universal C210 based on Exynos4210 rev0"; compatible = "samsung,universal_c210", "samsung,exynos4210", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x10000000 0x50000000 0x10000000>; diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index cc1b87e09534..99634c54dca9 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -18,7 +18,7 @@ model = "Hardkernel ODROID-U3 board based on Exynos4412"; compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 518ca57837be..d0a07673ae8b 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -18,7 +18,7 @@ model = "Hardkernel ODROID-X board based on Exynos4412"; compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x3FF00000>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index 92cdeea1cfb3..4d228858f172 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -17,7 +17,7 @@ model = "Hardkernel ODROID-X2 board based on Exynos4412"; compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7FF00000>; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 9156a35a6117..54a9f6906ed2 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -22,7 +22,7 @@ model = "Insignal Origen evaluation board based on Exynos4412"; compatible = "insignal,origen4412", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 2e868c4c307e..2e208d84ff6a 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -20,7 +20,7 @@ model = "Samsung SMDK evaluation board based on Exynos4412"; compatible = "samsung,smdk4412", "samsung,exynos4412", "samsung,exynos4"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index ad60f3840e24..5504398e6e37 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -23,7 +23,7 @@ stdout-path = &serial_0; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index e1380bae8ee3..41ecd6d465a7 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -30,7 +30,7 @@ i2c12 = &i2c_max77693_fuel; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x40000000>; }; -- cgit v1.2.3 From a0eb109598863442a1663817721c437d2679fa0e Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 1 Sep 2016 11:06:56 +0200 Subject: ARM: dts: exynos: Add missing unit name to memory nodes in Exynos5 DTS This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250-arndale.dts | 2 +- arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 2 +- arch/arm/boot/dts/exynos5250-spring.dts | 2 +- arch/arm/boot/dts/exynos5260-xyref5260.dts | 2 +- arch/arm/boot/dts/exynos5410-odroidxu.dts | 2 +- arch/arm/boot/dts/exynos5410-smdk5410.dts | 2 +- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 2 +- arch/arm/boot/dts/exynos5420-peach-pit.dts | 2 +- arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 2 +- arch/arm/boot/dts/exynos5440-sd5v1.dts | 2 +- arch/arm/boot/dts/exynos5440-ssdk5440.dts | 2 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 54397c7e8d7c..6098dacd09f1 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -20,7 +20,7 @@ model = "Insignal Arndale evaluation board based on EXYNOS5250"; compatible = "insignal,arndale", "samsung,exynos5250", "samsung,exynos5"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index b85b78a57299..124e7bf1ed97 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -22,7 +22,7 @@ aliases { }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index 5324eb488e30..9ddf5d2701c2 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -19,7 +19,7 @@ i2c104 = &i2c_104; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index bdc55fa7c576..103d8f94e1da 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -20,7 +20,7 @@ model = "Google Spring"; compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index d7f62918ed4b..d75685cad627 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -16,7 +16,7 @@ model = "SAMSUNG XYREF5260 board based on EXYNOS5260"; compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5"; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index bf1612c0d4a4..8bc924457af6 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -21,7 +21,7 @@ model = "Hardkernel Odroid XU"; compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7ea00000>; }; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 6ea1ac4cf1e7..5e36bddb0509 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -16,7 +16,7 @@ model = "Samsung SMDK5410 board based on EXYNOS5410"; compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5"; - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 10483a230538..c5923fae4e8e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -22,7 +22,7 @@ model = "Insignal Arndale Octa evaluation board based on EXYNOS5420"; compatible = "insignal,arndale-octa", "samsung,exynos5420", "samsung,exynos5"; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index cd0c44b0bfa5..bc76dfdc57e6 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -79,7 +79,7 @@ }; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 3a744d5611ea..b9192ef11257 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -19,7 +19,7 @@ model = "Samsung SMDK5420 board based on EXYNOS5420"; compatible = "samsung,smdk5420", "samsung,exynos5420", "samsung,exynos5"; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index 05ae7284bb1b..0747c6fdadf8 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -21,7 +21,7 @@ #include "exynos-mfc-reserved-memory.dtsi" / { - memory { + memory@40000000 { device_type = "memory"; reg = <0x40000000 0x7EA00000>; }; diff --git a/arch/arm/boot/dts/exynos5440-sd5v1.dts b/arch/arm/boot/dts/exynos5440-sd5v1.dts index afd21a41e05b..ad6f533b3f40 100644 --- a/arch/arm/boot/dts/exynos5440-sd5v1.dts +++ b/arch/arm/boot/dts/exynos5440-sd5v1.dts @@ -21,7 +21,7 @@ }; /* FIXME: set reg property with correct start address and size */ - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; diff --git a/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/arch/arm/boot/dts/exynos5440-ssdk5440.dts index bdb3bf622e2f..92bd2c6f7631 100644 --- a/arch/arm/boot/dts/exynos5440-ssdk5440.dts +++ b/arch/arm/boot/dts/exynos5440-ssdk5440.dts @@ -22,7 +22,7 @@ }; /* FIXME: set reg property with correct start address and size */ - memory { + memory@0 { device_type = "memory"; reg = <0 0>; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 72f89c8803d4..9fafe10d9e4e 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -79,7 +79,7 @@ }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x80000000>; }; -- cgit v1.2.3 From 3b879a5008660f1401a5fc7add9c45fa4c5efdec Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH407: Move pio20 node to fix kernel warning cat /sys/kernel/debug/pinctrl/921f080.pin-controller-front1/pingroups leads to the kernel warning: [ 86.083560] st-pinctrl 921f080.pin-controller-front1: failed to get pin(-517) name [ 86.091192] ------------[ cut here ]------------ [ 86.095897] WARNING: CPU: 0 PID: 1579 at drivers/pinctrl/core.c:1414 pinctrl_groups_show+0x144/0x16c [ 86.105072] Modules linked in: [ 86.108127] CPU: 0 PID: 1579 Comm: cat Tainted: G W 4.6.0-00011-g9ba82e2-dirty #5 [ 86.116728] Hardware name: STiH415/416 SoC with Flattened Device Tree [ 86.123194] [] (unwind_backtrace) from [] (show_stack+0x10/0x14) [ 86.130943] [] (show_stack) from [] (dump_stack+0x98/0xac) [ 86.138167] [] (dump_stack) from [] (__warn+0xe8/0x100) [ 86.145121] [] (__warn) from [] (warn_slowpath_null+0x20/0x28) [ 86.152681] [] (warn_slowpath_null) from [] (pinctrl_groups_show+0x144/0x16c) [ 86.161550] [] (pinctrl_groups_show) from [] (seq_read+0x1ec/0x4c0) [ 86.169553] [] (seq_read) from [] (__vfs_read+0x20/0xd0) [ 86.176592] [] (__vfs_read) from [] (vfs_read+0x7c/0x104) [ 86.183716] [] (vfs_read) from [] (SyS_read+0x44/0x9c) [ 86.190585] [] (SyS_read) from [] (ret_fast_syscall+0x0/0x3c) [ 86.198158] ---[ end trace 1aa2e3ae820eeb3e ]--- Move the pincontroller pio20 node above the tsin4 node, which referred to it, fix this warning. Signed-off-by: Patrice Chotard Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index a538ae52d32b..bd53c74e6d59 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -916,6 +916,15 @@ interrupt-names = "irqmux"; ranges = <0 0x09210000 0x10000>; + pio20: pio@09210000 { + gpio-controller; + #gpio-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x100>; + st,bank-name = "PIO20"; + }; + tsin4 { pinctrl_tsin4_serial_alt1: tsin4_serial_alt1 { st,pins { @@ -927,15 +936,6 @@ }; }; }; - - pio20: pio@09210000 { - gpio-controller; - #gpio-cells = <1>; - interrupt-controller; - #interrupt-cells = <2>; - reg = <0x0 0x100>; - st,bank-name = "PIO20"; - }; }; pin-controller-rear { -- cgit v1.2.3 From 70bc0f3a904dac95becce94e28ed6b132c39febb Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH410: Add thermal node Signed-off-by: Patrice Chotard [Lee: Changed node name and added the unit address] Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih410.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 18ed1ad10d32..7590721e9e97 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -227,5 +227,13 @@ clock-names = "bdisp"; clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; + + thermal@91a0000 { + compatible = "st,stih407-thermal"; + reg = <0x91a0000 0x28>; + clock-names = "thermal"; + clocks = <&clk_sysin>; + interrupts = ; + }; }; }; -- cgit v1.2.3 From d5f102edde54e089b0de0faf40a7f6fb2619b0f1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH407-pinctrl: Add i2c2_alt2_1 node Add missing pin muxing for I2C2 alternate 2. This i2c2 pin muxing is dedicated for 96board high speed expansion connector. Signed-off-by: Patrice Chotard [Lee: Correct spacing between nodes] Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index bd53c74e6d59..e05be3ccd740 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -523,6 +523,13 @@ scl = <&pio15 5 ALT2 BIDIR>; }; }; + + pinctrl_i2c2_alt2_1: i2c2-alt2-1 { + st,pins { + sda = <&pio12 6 ALT2 BIDIR>; + scl = <&pio12 5 ALT2 BIDIR>; + }; + }; }; i2c3 { -- cgit v1.2.3 From 8f416dcd2c06580b12db3ba3f8379350660f2ddf Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH407: Move non-removable property to board file Due to 96board which uses mmc0 node for SD card, the non-removable property must be moved from STiH407-family to board file for B2120 and B2199 boards. Signed-off-by: Patrice Chotard Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 1 - arch/arm/boot/dts/stih418-b2199.dts | 1 + arch/arm/boot/dts/stihxxx-b2120.dtsi | 1 + 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index d294e82447a2..59fea05b1e8a 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -553,7 +553,6 @@ clock-names = "mmc"; clocks = <&clk_s_c0_flexgen CLK_MMC_0>; bus-width = <8>; - non-removable; }; mmc1: sdhci@09080000 { diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 772d2bb07e5f..7c45e75b4c96 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -86,6 +86,7 @@ sd-uhs-sdr50; sd-uhs-sdr104; sd-uhs-ddr50; + non-removable; }; miphy28lp_phy: miphy28lp@9b22000 { diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 133375bc8aa5..0b0dd024f72d 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -65,6 +65,7 @@ }; mmc0: sdhci@09060000 { + non-removable; status = "okay"; }; -- cgit v1.2.3 From c3df8e211eae7c1ecc7cc7eefa23f7901bfbdd89 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH407-pinctrl: Add pinctrl_rgmii1_mdio_1 node On 96board, we can't reuse rgmii1-mdio as the pin pio1 3 ( mdint ) is dedicated for user led green 1. So create rgmii1_mdio_1 for 96board on which only mdio and mdc pins are useful. Signed-off-by: Patrice Chotard Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index e05be3ccd740..3e7a56dd17ff 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -230,6 +230,13 @@ }; }; + pinctrl_rgmii1_mdio_1: rgmii1-mdio-1 { + st,pins { + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + }; + }; + pinctrl_mii1: mii1 { st,pins { txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; -- cgit v1.2.3 From ecb8af45906526f019e88a1de3b1052f13cc7951 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STiH407-family: Add ports-implemented property in sata nodes Despite ST AHCI version = 1.3, reading HOST_PORTS_IMPL returns 0. So force HOST_PORTS_IMPL to 1 by using ports-implemented DT property. Signed-off-by: Patrice Chotard Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 59fea05b1e8a..55ecfbea905d 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -607,6 +607,8 @@ clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + ports-implemented = <0x1>; + status = "disabled"; }; @@ -630,6 +632,8 @@ clock-names = "ahci_clk"; clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; + ports-implemented = <0x1>; + status = "disabled"; }; -- cgit v1.2.3 From 76c1c9cf3659057fabbe8a18e04a2121c5d3b433 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Mon, 15 Aug 2016 14:17:00 +0200 Subject: ARM: dts: STi: Introduce B2260 board B2260 board is the STMicroelectronics 96Board based on STiH410 soc : - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU with PCB soldered antenna - Ethernet 1000-BaseT - Sata - HDMI - 2 x USB2 type A - micro USB2 type AB - SD card slot - High speed connector (SD/I2C/USB interfaces) - Slow speed connector (UART/I2C/GPIO/SPI/PCM interfaces) Signed-off-by: Patrice Chotard Signed-off-by: Lee Jones Reviewed-by: Peter Griffin --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stih410-b2260.dts | 190 ++++++++++++++++++++++++++++++++++++ 2 files changed, 191 insertions(+) create mode 100644 arch/arm/boot/dts/stih410-b2260.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..f23a5b375f17 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -686,6 +686,7 @@ dtb-$(CONFIG_ARCH_SPEAR6XX) += \ dtb-$(CONFIG_ARCH_STI) += \ stih407-b2120.dtb \ stih410-b2120.dtb \ + stih410-b2260.dtb \ stih415-b2000.dtb \ stih415-b2020.dtb \ stih416-b2000.dtb \ diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts new file mode 100644 index 000000000000..94e064f193b2 --- /dev/null +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2016 STMicroelectronics (R&D) Limited. + * Author: Patrice Chotard + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "stih410.dtsi" +#include + +/ { + model = "STiH410 B2260"; + compatible = "st,stih410-b2260", "st,stih410"; + + chosen { + bootargs = "console=ttyAS1,115200"; + linux,stdout-path = &uart1; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x40000000>; + }; + + aliases { + ttyAS1 = &uart1; + ethernet0 = ðernet0; + }; + + soc { + + leds { + compatible = "gpio-leds"; + user_green_1 { + label = "User_green_1"; + gpios = <&pio1 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user_green_2 { + label = "User_green_2"; + gpios = <&pio4 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user_green_3 { + label = "User_green_3"; + gpios = <&pio2 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + user_green_4 { + label = "User_green_4"; + gpios = <&pio2 5 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + /* Low speed expansion connector */ + uart0: serial@9830000 { + label = "LS-UART0"; + status = "okay"; + }; + + /* Low speed expansion connector */ + uart1: serial@9831000 { + label = "LS-UART1"; + status = "okay"; + }; + + /* Low speed expansion connector */ + spi0: spi@9844000 { + label = "LS-SPI0"; + cs-gpio = <&pio30 3 0>; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c0: i2c@9840000 { + label = "LS-I2C0"; + status = "okay"; + }; + + /* Low speed expansion connector */ + i2c1: i2c@9841000 { + label = "LS-I2C1"; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c2: i2c@9842000 { + label = "HS-I2C2"; + pinctrl-0 = <&pinctrl_i2c2_alt2_1>; + status = "okay"; + }; + + /* high speed expansion connector */ + i2c3: i2c@9843000 { + label = "HS-I2C3"; + pinctrl-0 = <&pinctrl_i2c3_alt3_0>; + status = "okay"; + }; + + mmc0: sdhci@09060000 { + pinctrl-0 = <&pinctrl_sd0>; + bus-width = <4>; + status = "okay"; + }; + + /* high speed expansion connector */ + mmc1: sdhci@09080000 { + status = "okay"; + }; + + pwm0: pwm@9810000 { + status = "okay"; + }; + + pwm1: pwm@9510000 { + status = "okay"; + }; + + usb2_picophy1: phy2 { + status = "okay"; + }; + + usb2_picophy2: phy3 { + status = "okay"; + }; + + ohci0: usb@9a03c00 { + status = "okay"; + }; + + ehci0: usb@9a03e00 { + status = "okay"; + }; + + ohci1: usb@9a83c00 { + status = "okay"; + }; + + ehci1: usb@9a83e00 { + status = "okay"; + }; + + ethernet0: dwmac@9630000 { + phy-mode = "rgmii"; + pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; + + snps,phy-bus-name = "stmmac"; + snps,phy-bus-id = <0>; + snps,phy-addr = <0>; + snps,reset-gpio = <&pio0 7 0>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 1000000>; + + status = "okay"; + }; + + /* SSC11 to HDMI */ + hdmiddc: i2c@9541000 { + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + status = "okay"; + }; + + sti-display-subsystem { + sti_hdmi: sti-hdmi@8d04000 { + status = "okay"; + }; + }; + + miphy28lp_phy: miphy28lp@9b22000 { + + phy_port1: port@9b2a000 { + st,osc-force-ext; + }; + }; + + sata1: sata@9b28000 { + status = "okay"; + }; + }; +}; -- cgit v1.2.3 From 4e6ee33684eb6eaa124230c92d35f2988cb98bc4 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 10 Aug 2016 15:12:00 +0200 Subject: ARM: dts: STiH407-pinctrl: Update gpio-cells to 2 This patch allows to use second parameter to the gpio specifier, which is used to specify whether the gpio is active high or low. Signed-off-by: Patrice Chotard Acked-by: Linus Walleij --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 52 +++++++++++++++++----------------- 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 3e7a56dd17ff..4be681aaf773 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -58,7 +58,7 @@ pio0: gpio@09610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -66,7 +66,7 @@ }; pio1: gpio@09611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -74,7 +74,7 @@ }; pio2: gpio@09612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -82,7 +82,7 @@ }; pio3: gpio@09613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -90,7 +90,7 @@ }; pio4: gpio@09614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -99,7 +99,7 @@ pio5: gpio@09615000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -380,7 +380,7 @@ pio10: pio@09200000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -388,7 +388,7 @@ }; pio11: pio@09201000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -396,7 +396,7 @@ }; pio12: pio@09202000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -404,7 +404,7 @@ }; pio13: pio@09203000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -412,7 +412,7 @@ }; pio14: pio@09204000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -420,7 +420,7 @@ }; pio15: pio@09205000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -428,7 +428,7 @@ }; pio16: pio@09206000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -436,7 +436,7 @@ }; pio17: pio@09207000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -444,7 +444,7 @@ }; pio18: pio@09208000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x100>; @@ -452,7 +452,7 @@ }; pio19: pio@09209000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x9000 0x100>; @@ -932,7 +932,7 @@ pio20: pio@09210000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -965,7 +965,7 @@ pio30: gpio@09220000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x100>; @@ -973,7 +973,7 @@ }; pio31: gpio@09221000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -981,7 +981,7 @@ }; pio32: gpio@09222000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -989,7 +989,7 @@ }; pio33: gpio@09223000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -997,7 +997,7 @@ }; pio34: gpio@09224000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -1005,7 +1005,7 @@ }; pio35: gpio@09225000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -1104,7 +1104,7 @@ pio40: gpio@09230000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -1112,7 +1112,7 @@ }; pio41: gpio@09231000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -1120,7 +1120,7 @@ }; pio42: gpio@09232000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; -- cgit v1.2.3 From c3ee7e9d136d789bf33aa1e6c07b40d7a9721ec0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 10 Aug 2016 15:13:00 +0200 Subject: ARM: dts: STiH418-B2199: Update gpio specifier - Remove useless gpio-cells - Update second parameter by using GPIO_ACTIVE_HIGH/LOW instead of hardcoded value Signed-off-by: Patrice Chotard Acked-by: Linus Walleij --- arch/arm/boot/dts/stih418-b2199.dts | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stih418-b2199.dts b/arch/arm/boot/dts/stih418-b2199.dts index 7c45e75b4c96..438e54c585b1 100644 --- a/arch/arm/boot/dts/stih418-b2199.dts +++ b/arch/arm/boot/dts/stih418-b2199.dts @@ -8,6 +8,7 @@ */ /dts-v1/; #include "stih418.dtsi" +#include / { model = "STiH418 B2199"; compatible = "st,stih418-b2199", "st,stih418"; @@ -35,14 +36,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <2>; label = "Front Panel LED"; - gpios = <&pio4 1 0>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; -- cgit v1.2.3 From ba5ba11906d5462993f5fd4e3da4d234505427a0 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 10 Aug 2016 15:13:00 +0200 Subject: ARM: dts: STiH41x-b2020: Update gpio specifier - Remove useless gpio-cells - Update second parameter by using GPIO_ACTIVE_HIGH/LOW instead of hardcoded value Signed-off-by: Patrice Chotard Acked-by: Linus Walleij --- arch/arm/boot/dts/stih41x-b2020.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index 487d7d87dbef..322e0e95176c 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -7,6 +7,7 @@ * publishhed by the Free Software Foundation. */ #include "stih41x-b2020x.dtsi" +#include / { memory{ device_type = "memory"; @@ -30,13 +31,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio4 1>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&pio4 7>; + gpios = <&pio4 7 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; -- cgit v1.2.3 From e286492e4d3f1f1d561850ed8829233d679873e0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 16 Aug 2016 10:46:30 -0700 Subject: ARM: dts: msm8974: honami: Add touchscreen Add the i2c2 and rmi4 nodes to enable the Synaptics touchscreen found in the Honami. Signed-off-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../boot/dts/qcom-msm8974-sony-xperia-honami.dts | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 3fb4dada6b0d..0d414ef9d3d0 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -311,6 +311,45 @@ pinctrl-0 = <&blsp1_uart2_pin_a>; }; + i2c@f9924000 { + status = "ok"; + + clock-frequency = <355000>; + qcom,src-freq = <50000000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + synaptics@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + + interrupts-extended = <&msmgpio 61 IRQ_TYPE_EDGE_FALLING>; + + #address-cells = <1>; + #size-cells = <0>; + + vdd-supply = <&pm8941_l22>; + vio-supply = <&pm8941_lvs3>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_pin>; + + syna,startup-delay-ms = <10>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + touchscreen-inverted-x; + syna,sensor-type = <1>; + }; + }; + }; + pinctrl@fd510000 { blsp1_uart2_pin_a: blsp1-uart2-pin-active { rx { @@ -330,6 +369,16 @@ }; }; + i2c2_pins: i2c2 { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + + drive-strength = <2>; + bias-disable; + }; + }; + sdhc1_pin_a: sdhc1-pin-active { clk { pins = "sdc1_clk"; @@ -366,6 +415,16 @@ }; }; + ts_int_pin: touch-int { + pin { + pins = "gpio61"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; }; dma-controller@f9944000 { -- cgit v1.2.3 From c59ffb519357537f632eeea8bd35372cfab10474 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 17 Aug 2016 10:48:44 +0530 Subject: arm: dts: msm8974: Add thermal zones, tsens and qfprom nodes Add thermal zones, tsens and qfprom nodes Acked-by: Eduardo Valentin Acked-by: Rob Herring Signed-off-by: Rajendra Nayak Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 103 ++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 4d0cfeb4c2e6..03a9f661e155 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -131,6 +131,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -287,6 +369,27 @@ reg = <0xf9011000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From c8c876898b2ba09d06151d027485107bb470878f Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 17 Aug 2016 10:48:45 +0530 Subject: arm: dts: apq8064: Add thermal zones, tsens and qfprom nodes TSENS is part of GCC, hence add TSENS properties as part of GCC node. Also add thermal zones and qfprom nodes. Update GCC bindings doc to mention the possibility of optional TSENS properties that can be part of GCC node. Acked-by: Eduardo Valentin Acked-by: Rob Herring Signed-off-by: Rajendra Nayak Signed-off-by: Andy Gross --- .../devicetree/bindings/clock/qcom,gcc.txt | 16 ++++ arch/arm/boot/dts/qcom-apq8064.dtsi | 103 +++++++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.txt b/Documentation/devicetree/bindings/clock/qcom,gcc.txt index 9a60fde32b02..ea893cbef73d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc.txt +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.txt @@ -22,6 +22,11 @@ Required properties : Optional properties : - #power-domain-cells : shall contain 1 +- Qualcomm TSENS (thermal sensor device) on some devices can +be part of GCC and hence the TSENS properties can also be +part of the GCC/clock-controller node. +For more details on the TSENS properties please refer +Documentation/devicetree/bindings/thermal/qcom-tsens.txt Example: clock-controller@900000 { @@ -31,3 +36,14 @@ Example: #reset-cells = <1>; #power-domain-cells = <1>; }; + +Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 7e43416e250f..1dbe697b2e90 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -87,6 +87,92 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 7>; + coefficients = <1199 0>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 8>; + coefficients = <1132 0>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 9>; + coefficients = <1199 0>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&gcc 10>; + coefficients = <1132 0>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 10 0x304>; @@ -649,11 +735,28 @@ }; }; + qfprom: qfprom@700000 { + compatible = "qcom,qfprom"; + reg = <0x00700000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + tsens_calib: calib { + reg = <0x404 0x10>; + }; + tsens_backup: backup_calib { + reg = <0x414 0x10>; + }; + }; + gcc: clock-controller@900000 { compatible = "qcom,gcc-apq8064"; reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; #clock-cells = <1>; #reset-cells = <1>; + #thermal-sensor-cells = <1>; }; lcc: clock-controller@28000000 { -- cgit v1.2.3 From 226366b95a95f85226c6ce77813e2afb940dca41 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 17 Aug 2016 10:48:46 +0530 Subject: arm: dts: apq8084: Add thermal zones, tsens and qfprom nodes Add thermal zones, tsens and qfprom nodes Acked-by: Eduardo Valentin Acked-by: Rob Herring Signed-off-by: Rajendra Nayak Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8084.dtsi | 103 ++++++++++++++++++++++++++++++++++++ 1 file changed, 103 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index 7c2df062a025..39eb7a4ed16a 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -94,6 +94,88 @@ }; }; + thermal-zones { + cpu-thermal0 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 5>; + + trips { + cpu_alert0: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 6>; + + trips { + cpu_alert1: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit1: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 7>; + + trips { + cpu_alert2: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit2: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + cpu-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + + thermal-sensors = <&tsens 8>; + + trips { + cpu_alert3: trip0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit3: trip1 { + temperature = <110000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + cpu-pmu { compatible = "qcom,krait-pmu"; interrupts = <1 7 0xf04>; @@ -150,6 +232,27 @@ reg = <0xf9011000 0x1000>; }; + qfprom: qfprom@fc4bc000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "qcom,qfprom"; + reg = <0xfc4bc000 0x1000>; + tsens_calib: calib@d0 { + reg = <0xd0 0x18>; + }; + tsens_backup: backup@440 { + reg = <0x440 0x10>; + }; + }; + + tsens: thermal-sensor@fc4a8000 { + compatible = "qcom,msm8974-tsens"; + reg = <0xfc4a8000 0x2000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #thermal-sensor-cells = <1>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 20fac0ce3c17093435a48773a419da3a0b588f5a Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Fri, 19 Aug 2016 10:46:47 +0200 Subject: ARM: dts: add PM8058 LEDs to the APQ8060 Dragonboard This adds the PM8058 LEDs as used in the platform. Cc: linux-arm-msm@vger.kernel.org Cc: linux-leds@vger.kernel.org Cc: Andy Gross Cc: Stephen Boyd Cc: Jacek Anaszewski Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij Acked-by: Jacek Anaszewski Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-apq8060-dragonboard.dts | 39 ++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 0abc93e5bb00..6c0038398ef2 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -239,6 +239,45 @@ }; }; }; + + led@48 { + /* + * The keypad LED @0x48 is routed to + * the sensor board where it is + * connected to an infrared LED + * SFH4650 (60mW, @850nm) next to the + * ambient light and proximity sensor + * Capella Microsystems CM3605. + */ + compatible = "qcom,pm8058-keypad-led"; + reg = <0x48>; + label = "pm8058:infrared:proximitysensor"; + default-state = "off"; + }; + led@131 { + compatible = "qcom,pm8058-led"; + reg = <0x131>; + label = "pm8058:red"; + default-state = "off"; + }; + led@132 { + /* + * This is actually green too on my + * board, but documented as yellow. + */ + compatible = "qcom,pm8058-led"; + reg = <0x132>; + label = "pm8058:yellow"; + default-state = "off"; + linux,default-trigger = "mmc0"; + }; + led@133 { + compatible = "qcom,pm8058-led"; + reg = <0x133>; + label = "pm8058:green"; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; }; }; -- cgit v1.2.3 From 0485ef8e045e2f295098bfa0f12e1b2cc243431c Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 29 Jul 2016 11:39:08 +0530 Subject: ARM: dts: qcom: msm8974: Add fixed regulator node for vph-pwr-reg Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- arch/arm/boot/dts/qcom-msm8974.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 03a9f661e155..d41154273827 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -727,4 +727,14 @@ }; }; }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; }; -- cgit v1.2.3 From 73bae19c3a3fde589b4508f3bfcc68d2f4b06f39 Mon Sep 17 00:00:00 2001 From: Bhushan Shah Date: Fri, 29 Jul 2016 11:39:07 +0530 Subject: ARM: dts: msm8974: Move vreg_boost node from the honami to msm8974 vreg_boost is Qualcomm platform specific and is also used in hammerhead device. Cc: Andy Gross Cc: Bjorn Andersson Cc: David Brown Cc: Rob Herring Cc: Mark Rutland Cc: Russell King Cc: linux-arm-msm@vger.kernel.org Cc: linux-soc@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Bhushan Shah Reviewed-by: Bjorn Andersson Signed-off-by: Andy Gross --- .../boot/dts/qcom-msm8974-sony-xperia-honami.dts | 22 ---------------------- arch/arm/boot/dts/qcom-msm8974.dtsi | 17 +++++++++++++++++ arch/arm/boot/dts/qcom-pm8941.dtsi | 5 +++++ 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts index 0d414ef9d3d0..e7c1577d56f4 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -257,23 +257,6 @@ }; }; }; - - vreg_boost: vreg-boost { - compatible = "regulator-fixed"; - - regulator-name = "vreg-boost"; - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3150000>; - - regulator-always-on; - regulator-boot-on; - - gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; - enable-active-high; - - pinctrl-names = "default"; - pinctrl-0 = <&boost_bypass_n_pin>; - }; }; &soc { @@ -446,11 +429,6 @@ }; gpios@c000 { - boost_bypass_n_pin: boost-bypass { - pins = "gpio21"; - function = "normal"; - }; - gpio_keys_pin_a: gpio-keys-active { pins = "gpio2", "gpio3", "gpio4", "gpio5"; function = "normal"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index d41154273827..d2109475bdfd 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -2,6 +2,7 @@ #include #include +#include #include "skeleton.dtsi" / { @@ -728,6 +729,22 @@ }; }; + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-names = "default"; + pinctrl-0 = <&boost_bypass_n_pin>; + }; vreg_vph_pwr: vreg-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph-pwr"; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index d95edb6f6265..f8eb5e31c920 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -88,6 +88,11 @@ <0 0xe1 0 IRQ_TYPE_NONE>, <0 0xe2 0 IRQ_TYPE_NONE>, <0 0xe3 0 IRQ_TYPE_NONE>; + + boost_bypass_n_pin: boost-bypass { + pins = "gpio21"; + function = "normal"; + }; }; pm8941_mpps: mpps@a000 { -- cgit v1.2.3 From 5eb3fcf341f673de111fd88b867b411ff31c63ea Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 4 Sep 2016 16:33:10 +0800 Subject: ARM: dts: rockchip: enable usbotg for Popemtal-rk3288 board Enable USB OTG port on RK3288 Popmetal board, So we can run some usb gadget functions like Android adb on this board. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-popmetal.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index dda8d259bb6d..acb0b1013a6c 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -525,3 +525,7 @@ &usbphy { status = "okay"; }; + +&usb_otg { + status = "okay"; +}; -- cgit v1.2.3 From a58e4e608bc88735581fdd9861676e522fa3c20d Mon Sep 17 00:00:00 2001 From: Michael Trimarchi Date: Tue, 30 Aug 2016 18:46:21 +0530 Subject: ARM: dts: imx6ul-geam: Add Engicam IMX6UL GEA M6UL initial support IMX6UL GEA M6UL modules are system on module solutions manufactured by Engicam with following characteristics: Processor Freescale i.MX 6UltraLite MCIMX6G2, 528 MHz RAM 128MB, 16-bit DDR3 NAND SLC 256MB Power supply Single 5V MAX LCD RES up to WXGA, 1366x768 and more info at http://www.engicam.com/prodotti/embedded/som/sodimm/gea-m6ul Cc: Sascha Hauer Cc: Fabio Estevam Signed-off-by: Matteo Lisi Signed-off-by: Michael Trimarchi Signed-off-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6ul-geam-kit.dts | 101 ++++++++++ arch/arm/boot/dts/imx6ul-geam.dtsi | 361 ++++++++++++++++++++++++++++++++++ 3 files changed, 463 insertions(+) create mode 100644 arch/arm/boot/dts/imx6ul-geam-kit.dts create mode 100644 arch/arm/boot/dts/imx6ul-geam.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 606a8b632d27..5dcc2394fbad 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -411,6 +411,7 @@ dtb-$(CONFIG_SOC_IMX6SX) += \ imx6sx-sdb.dtb dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-14x14-evk.dtb \ + imx6ul-geam-kit.dtb \ imx6ul-pico-hobbit.dtb \ imx6ul-tx6ul-0010.dtb \ imx6ul-tx6ul-0011.dtb \ diff --git a/arch/arm/boot/dts/imx6ul-geam-kit.dts b/arch/arm/boot/dts/imx6ul-geam-kit.dts new file mode 100644 index 000000000000..4c4af76143e3 --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-geam-kit.dts @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include +#include "imx6ul-geam.dtsi" + +/ { + model = "Engicam GEAM6UL"; + compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: display { + bits-per-pixel = <16>; + bus-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <28000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <30>; + hback-porch = <30>; + hsync-len = <64>; + vback-porch = <5>; + vfront-porch = <5>; + vsync-len = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + status = "okay"; +}; + +&tsc { + measure-delay-time = <0x1ffff>; + pre-charge-time = <0x1fff>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ul-geam.dtsi b/arch/arm/boot/dts/imx6ul-geam.dtsi new file mode 100644 index 000000000000..64eb9ed59b9c --- /dev/null +++ b/arch/arm/boot/dts/imx6ul-geam.dtsi @@ -0,0 +1,361 @@ +/* + * Copyright (C) 2016 Amarula Solutions B.V. + * Copyright (C) 2016 Engicam S.r.l. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include "imx6ul.dtsi" + +/ { + memory { + reg = <0x80000000 0x08000000>; + }; + + chosen { + stdout-path = &uart1; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3p3v>; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3p3v>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + clock_frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + display = <&display0>; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <4>; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* ENET_nRST */ + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1 + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1 + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_lcdif_ctrl: lcdifctrlgrp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdifdatgrp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pin = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17070 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x10070 + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17070 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17070 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17070 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17070 + >; + }; +}; -- cgit v1.2.3 From c2bf95899a36eff42f843e342533226a6202db0c Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Tue, 30 Aug 2016 17:23:02 -0300 Subject: ARM: dts: imx7s-warp: Enable I2C2 device support Enable I2C2 device support. Signed-off-by: Vanessa Maegima Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 1ff762d180ef..b35d1014cd5a 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -188,6 +188,13 @@ }; }; +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + &i2c4 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -280,6 +287,13 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + pinctrl_i2c4: i2c4grp { fsl,pins = < MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f -- cgit v1.2.3 From d142a20700ca73430bcacfa6f8df3331142049d9 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Tue, 30 Aug 2016 17:23:03 -0300 Subject: ARM: dts: imx7s-warp: Add User Button support Add User Button at GPIO7_1. Tested by evtest. Signed-off-by: Vanessa Maegima Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index b35d1014cd5a..df74f0c9f102 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -54,6 +54,19 @@ reg = <0x80000000 0x20000000>; }; + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pinctrl_gpio>; + autorepeat; + + back { + label = "Back"; + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + linux,code = ; + wakeup-source; + }; + }; + reg_brcm: regulator-brcm { compatible = "regulator-fixed"; enable-active-high; @@ -280,6 +293,12 @@ >; }; + pinctrl_gpio: gpiogrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f -- cgit v1.2.3 From 9fa7a2a4f9d90901e845fb4cafe815d08c2981c5 Mon Sep 17 00:00:00 2001 From: Vanessa Maegima Date: Tue, 30 Aug 2016 17:23:04 -0300 Subject: ARM: dts: imx7s-warp: Add Bluetooth support WaRP7 has a BCM43430 Bluetooth chip. Add support for it. Signed-off-by: Vanessa Maegima Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index df74f0c9f102..0345267f3390 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -79,6 +79,18 @@ startup-delay-us = <200000>; }; + reg_bt: regulator-bt { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_reg>; + enable-active-high; + gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; + regulator-name = "bt_reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -250,6 +262,15 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "peripheral"; status = "okay"; @@ -293,6 +314,12 @@ >; }; + pinctrl_bt_reg: btreggrp { + fsl,pins = < + MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */ + >; + }; + pinctrl_gpio: gpiogrp { fsl,pins = < MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14 @@ -342,6 +369,15 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79 + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX7D_PAD_SD1_CMD__SD1_CMD 0x59 -- cgit v1.2.3 From 9369554d73c79396772c5e20dd19c75249a4ecbe Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 4 Sep 2016 16:34:27 +0800 Subject: ARM: dts: rockchip: fix L3G4200D i2c address on PopMetal-RK3288 board The i2c address of the three-axis digital gyroscope L3G4200D should be 0x69 according to hardware design. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-popmetal.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index acb0b1013a6c..d94e210d294b 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -389,10 +389,10 @@ pinctrl-0 = <&comp_int>; }; - l3g4200d: l3g4200d@68 { + l3g4200d: l3g4200d@69 { compatible = "st,l3g4200d-gyro"; st,drdy-int-pin = <2>; - reg = <0x6b>; + reg = <0x69>; }; mma8452: mma8452@1d { -- cgit v1.2.3 From 4314f4b6720d96b0504da30112b6d42d13c3e50f Mon Sep 17 00:00:00 2001 From: Andy Yan Date: Sun, 4 Sep 2016 16:34:27 +0800 Subject: ARM: dts: rockchip: Add sensor-supplies on PopMetal-RK3288 board Add power supply reference for L3G3200D and the 3-axis Electronic Compass AK8963. Signed-off-by: Andy Yan Signed-off-by: Heiko Stuebner --- arch/arm/boot/dts/rk3288-popmetal.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts index d94e210d294b..56dd377d5658 100644 --- a/arch/arm/boot/dts/rk3288-popmetal.dts +++ b/arch/arm/boot/dts/rk3288-popmetal.dts @@ -387,12 +387,16 @@ interrupts = <1 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&comp_int>; + vdd-supply = <&vcc_io>; + vid-supply = <&vcc_io>; }; l3g4200d: l3g4200d@69 { compatible = "st,l3g4200d-gyro"; st,drdy-int-pin = <2>; reg = <0x69>; + vdd-supply = <&vcc_io>; + vddio-supply = <&vcc_io>; }; mma8452: mma8452@1d { -- cgit v1.2.3 From 19635b0c13a0eb3bc6f5352134b8b4846ab88afe Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 Sep 2016 13:05:17 +0200 Subject: ARM: dts: sun8i: Orange Pi Plus dts is for the Plus and Plus 2 Update the sun8i-h3-orangepi-plus.dts model string to reflect that it is valid for both the Orange Pi Plus and the Orange Pi Plus 2. This is also meant to help users realize that it is not valid for the new Orange Pi Plus 2E, which will get its own dts. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index b0cb41787e09..bb585918cf54 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -44,7 +44,7 @@ #include "sun8i-h3-orangepi-2.dts" / { - model = "Xunlong Orange Pi Plus"; + model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; reg_usb3_vbus: usb3-vbus { -- cgit v1.2.3 From 2ea3c34bc2ee83d2ae9701d5194054be62a05105 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 3 Sep 2016 13:05:18 +0200 Subject: ARM: dts: sun8i: Add dts file for the Orange Pi Plus2E SBC The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. Note currently the dts is pretty much empty (except for including the pc-plus dts), I've a local patch which enables the emac actually making this dts different from the pc-plus one, but that needs the h3 emac driver to get merged first. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 53 ++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7dd4a07c4784..bb906f23d161 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -798,6 +798,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-h3-orangepi-pc.dtb \ sun8i-h3-orangepi-pc-plus.dtb \ sun8i-h3-orangepi-plus.dtb \ + sun8i-h3-orangepi-plus2e.dtb \ sun8i-r16-parrot.dtb dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts new file mode 100644 index 000000000000..5851a47a3089 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts @@ -0,0 +1,53 @@ +/* + * Copyright (C) 2016 Hans de Goede + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * The Orange Pi Plus 2E is an extended version of the Orange Pi PC Plus, + * with 2G RAM and an external gbit ethernet phy. + */ + +#include "sun8i-h3-orangepi-pc-plus.dts" + +/ { + model = "Xunlong Orange Pi Plus 2E"; + compatible = "xunlong,orangepi-plus2e", "allwinner,sun8i-h3"; +}; -- cgit v1.2.3 From e6835b3e7bc6552faab1667d44e8a6786f60c590 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 26 Aug 2016 23:20:05 +0300 Subject: ARM: dts: document Wheat board Document the Wheat device tree bindings, listing it as a supported board. This allows to use checkpatch.pl to validate .dts files referring to the Wheat board. Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Acked-by: Rob Herring Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 1df32d339da5..90cf237ee558 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -69,3 +69,5 @@ Boards: compatible = "renesas,salvator-x", "renesas,r8a7796"; - SILK (RTP0RC7794LCB00011S) compatible = "renesas,silk", "renesas,r8a7794" + - Wheat + compatible = "renesas,wheat", "renesas,r8a7792" -- cgit v1.2.3 From 5f45cec40402188a269dd56e9a1a569cc4849014 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 26 Aug 2016 23:21:42 +0300 Subject: ARM: dts: wheat: initial device tree Add the initial device tree for the R8A7792 SoC based Wheat board. The Wheat board itself has no serial ports wired up, the USB serial chips are situated on a separate debug board and one of them is connected to SCFI0 -- include unconditional support for it, so that the serial console can work. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7792-wheat.dts | 50 +++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7792-wheat.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..d289ec733d2e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -659,6 +659,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ r8a7791-koelsch.dtb \ r8a7791-porter.dtb \ r8a7792-blanche.dtb \ + r8a7792-wheat.dtb \ r8a7793-gose.dtb \ r8a7794-alt.dtb \ r8a7794-silk.dtb \ diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts new file mode 100644 index 000000000000..22ae14ffc917 --- /dev/null +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -0,0 +1,50 @@ +/* + * Device Tree Source for the Wheat board + * + * Copyright (C) 2016 Renesas Electronics Corporation + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7792.dtsi" + +/ { + model = "Wheat"; + compatible = "renesas,wheat", "renesas,r8a7792"; + + aliases { + serial0 = &scif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From 1d9a17dd3f98e3e8d5484224bc9e96f6cb30288b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Fri, 26 Aug 2016 23:23:13 +0300 Subject: ARM: dts: wheat: add Ethernet support R8A7792 SoC doesn't have the EtherMAC core, so SMSC LAN89218 Ethernet chip was used instead on the Wheat debug board; this chip is compatible with SMSC LAN9115 for which there's a (device tree aware) driver. Describe the chip in the Wheat device tree unconditionally (the driver should fail the probe if the debug board isn't connected); enable DHCP and NFS root in the command line for the kernel boot... Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 38 ++++++++++++++++++++++++++++++++++++- 1 file changed, 37 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 22ae14ffc917..e214d707f81d 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -21,7 +21,7 @@ }; chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; @@ -29,6 +29,31 @@ device_type = "memory"; reg = <0 0x40000000 0 0x40000000>; }; + + d3_3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ethernet@18000000 { + compatible = "smsc,lan89218", "smsc,lan9115"; + reg = <0 0x18000000 0 0x100>; + phy-mode = "mii"; + interrupt-parent = <&irqc>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + smsc,irq-push-pull; + smsc,save-mac-address; + reg-io-width = <4>; + vddvario-supply = <&d3_3v>; + vdd33a-supply = <&d3_3v>; + + pinctrl-0 = <&lan89218_pins>; + pinctrl-names = "default"; + }; }; &extal_clk { @@ -40,6 +65,17 @@ groups = "scif0_data"; function = "scif0"; }; + + lan89218_pins: lan89218 { + intc { + groups = "intc_irq0"; + function = "intc"; + }; + lbsc { + groups = "lbsc_ex_cs0"; + function = "lbsc"; + }; + }; }; &scif0 { -- cgit v1.2.3 From 16a304d8297245e4bc0e863395b8fea593d81e09 Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Mon, 29 Aug 2016 14:14:29 -0400 Subject: ARM: dts: Add RSKRZA1 DT bindings documentation Add RSKRZA1 Device tree bindings Documentation, listing it as a supported board. This allows to use checkpatch to validate DTSes referring to the RSKRZA1 board. Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt index 90cf237ee558..5484c31d555f 100644 --- a/Documentation/devicetree/bindings/arm/shmobile.txt +++ b/Documentation/devicetree/bindings/arm/shmobile.txt @@ -63,6 +63,8 @@ Boards: compatible = "renesas,marzen", "renesas,r8a7779" - Porter (M2-LCDP) compatible = "renesas,porter", "renesas,r8a7791" + - RSKRZA1 (YR0K77210C000BE) + compatible = "renesas,rskrza1", "renesas,r7s72100" - Salvator-X (RTP0RC7795SIPB0010S) compatible = "renesas,salvator-x", "renesas,r8a7795"; - Salvator-X -- cgit v1.2.3 From e83c05a7160681f554476e9d44b7b77053efc21a Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Mon, 29 Aug 2016 14:13:22 -0400 Subject: ARM: dts: rskrza1: initial device tree Add the initial device tree for the RZ/A1 based development board (RSK). Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r7s72100-rskrza1.dts | 52 ++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/arm/boot/dts/r7s72100-rskrza1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d289ec733d2e..80193b3a450b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -651,6 +651,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ + r7s72100-rskrza1.dtb \ r8a73a4-ape6evm.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts new file mode 100644 index 000000000000..aabfa0459dc1 --- /dev/null +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -0,0 +1,52 @@ +/* + * Device Tree Source for the RZ/A1H RSK board + * + * Copyright (C) 2016 Renesas Electronics + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r7s72100.dtsi" + +/ { + model = "RSKRZA1"; + compatible = "renesas,rskrza1", "renesas,r7s72100"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@8000000 { + device_type = "memory"; + reg = <0x08000000 0x02000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&extal_clk { + clock-frequency = <13330000>; +}; + +&usb_x1_clk { + clock-frequency = <48000000>; +}; + +&mtu2 { + status = "okay"; +}; + +&scif2 { + status = "okay"; +}; -- cgit v1.2.3 From 969244f9c72057b2c32b650b2d75a04d612c603c Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 1 Sep 2016 21:40:10 -0400 Subject: ARM: dts: r7s72100: add ethernet clock to device tree Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 9 +++++++++ include/dt-bindings/clock/r7s72100-clock.h | 3 +++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index e8e2a5d71976..6d29e8ffa0d9 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -108,6 +108,15 @@ clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7"; }; + mstp7_clks: mstp7_clks@fcfe0430 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xfcfe0430 4>; + clocks = <&p0_clk>; + clock-indices = ; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks@fcfe0438 { #clock-cells = <1>; compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/include/dt-bindings/clock/r7s72100-clock.h b/include/dt-bindings/clock/r7s72100-clock.h index 5128f4d94f44..3cd813896d08 100644 --- a/include/dt-bindings/clock/r7s72100-clock.h +++ b/include/dt-bindings/clock/r7s72100-clock.h @@ -25,6 +25,9 @@ #define R7S72100_CLK_SCIF6 1 #define R7S72100_CLK_SCIF7 0 +/* MSTP7 */ +#define R7S72100_CLK_ETHER 4 + /* MSTP9 */ #define R7S72100_CLK_I2C0 7 #define R7S72100_CLK_I2C1 6 -- cgit v1.2.3 From e54824019155a609eb3547ce07721c96d9e790ac Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 1 Sep 2016 21:40:11 -0400 Subject: ARM: dts: r7s72100: add ethernet to device tree Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index 6d29e8ffa0d9..fb9ef9ca120e 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -428,4 +428,17 @@ power-domains = <&cpg_clocks>; status = "disabled"; }; + + ether: ethernet@e8203000 { + compatible = "renesas,ether-r7s72100"; + reg = <0xe8203000 0x800>, + <0xe8204800 0x200>; + interrupts = ; + clocks = <&mstp7_clks R7S72100_CLK_ETHER>; + power-domains = <&cpg_clocks>; + phy-mode = "mii"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; -- cgit v1.2.3 From 0aa8d831e75ec8b6c003943ece980535ab6cc94f Mon Sep 17 00:00:00 2001 From: Chris Brandt Date: Thu, 1 Sep 2016 21:40:12 -0400 Subject: ARM: dts: rskrza1: add ethernet DT support Signed-off-by: Chris Brandt Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-rskrza1.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-rskrza1.dts b/arch/arm/boot/dts/r7s72100-rskrza1.dts index aabfa0459dc1..e5dea5bb4032 100644 --- a/arch/arm/boot/dts/r7s72100-rskrza1.dts +++ b/arch/arm/boot/dts/r7s72100-rskrza1.dts @@ -47,6 +47,15 @@ status = "okay"; }; +ðer { + status = "okay"; + renesas,no-ether-link; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + &scif2 { status = "okay"; }; -- cgit v1.2.3 From 059baea1d33a64e752af201140ef122e29f2a19a Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sun, 4 Sep 2016 22:55:37 +0300 Subject: ARM: dts: r8a7794: fix PWM clock parent When removing the non-existing thermal clock I forgot to remove its parent from the node's "clocks" property -- this led to a wrong PWM clock's parent clock. Fixes: 2a29f9d6fea8 ("ARM: dts: r8a7794: add MSTP5 clocks") Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 611ec6df5cf6..9365580a194f 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -1251,7 +1251,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&p_clk>; #clock-cells = <1>; clock-indices = ; -- cgit v1.2.3 From 4ea71e6df8c22f90665394476c433cad3b4394b6 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Mon, 29 Aug 2016 23:11:26 +0300 Subject: ARM: dts: wheat: add CAN support Define the Wheat board dependent part of the CAN0/1 device nodes... Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index e214d707f81d..65d13c83d424 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -76,6 +76,16 @@ function = "lbsc"; }; }; + + can0_pins: can0 { + groups = "can0_data"; + function = "can0"; + }; + + can1_pins: can1 { + groups = "can1_data"; + function = "can1"; + }; }; &scif0 { @@ -84,3 +94,17 @@ status = "okay"; }; + +&can0 { + pinctrl-0 = <&can0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&can1 { + pinctrl-0 = <&can1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit v1.2.3 From 0c157ad23bb02fbda8b9cee82941d7c5ecac26f1 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Wed, 31 Aug 2016 01:24:41 +0300 Subject: ARM: dts: wheat: add SDHI0 support Define the Wheat board dependent part of the SDHI0 (connected to the micro-SD slot) device node along with the necessary voltage regulator. Signed-off-by: Sergei Shtylyov Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 65d13c83d424..ff37de35c57c 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r8a7792.dtsi" +#include / { model = "Wheat"; @@ -54,6 +55,17 @@ pinctrl-0 = <&lan89218_pins>; pinctrl-names = "default"; }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio11 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; }; &extal_clk { @@ -86,6 +98,11 @@ groups = "can1_data"; function = "can1"; }; + + sdhi0_pins: sdhi0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + }; }; &scif0 { @@ -108,3 +125,12 @@ status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; -- cgit v1.2.3 From 4719d8f9356a9ea8287ebdac04d759482524e67c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Sep 2016 01:07:28 +0300 Subject: ARM: dts: r8a7792: add QSPI clock Describe the QSPI clock in the R8A7792 device tree. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index ff47755fb01e..6ff3e365d56a 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -860,6 +860,7 @@ clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, + <&cpg_clocks R8A7792_CLK_QSPI>, <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; #clock-cells = <1>; @@ -870,6 +871,7 @@ R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 + R8A7792_CLK_QSPI_MOD R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 @@ -879,8 +881,9 @@ "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", "gpio11", "gpio10", "can1", "can0", - "gpio9", "gpio8", "i2c5", "i2c4", - "i2c3", "i2c2", "i2c1", "i2c0"; + "qspi_mod", "gpio9", "gpio8", + "i2c5", "i2c4", "i2c3", "i2c2", + "i2c1", "i2c0"; }; }; -- cgit v1.2.3 From c9acea6efdd7b08bf80a3721a44970252935621b Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Sep 2016 01:08:45 +0300 Subject: ARM: dts: r8a7792: add QSPI support Define the generic R8A7792 part of the QSPI device node. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 6ff3e365d56a..713141d38b3e 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -25,6 +25,7 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + spi0 = &qspi; vin0 = &vin0; vin1 = &vin1; vin2 = &vin2; @@ -556,6 +557,21 @@ status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7792", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + du: display@feb00000 { compatible = "renesas,du-r8a7792"; reg = <0 0xfeb00000 0 0x40000>; -- cgit v1.2.3 From 621efefc9b3135408de818c01528bc3adacd557c Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 26 Aug 2016 16:52:36 +0200 Subject: ARM: dts: sun8i-q8-common: Add support for SDIO wifi controllers Most of the sun8i q8 boards have an SDIO wifi controller, on the variants which use an USB wifi controller, this will result in a couple of error msg-s in dmesg when proving the sdio bus and an used mmc controller. The best way to deal with wifi on this boards really is to simply let the kernel auto-detect usb or sdio wifi controllers, so we will just have to live with the few errors in dmesg. This has been tested on a23 based q8 tablets with ESP8089, RTL8703AS and RTL8189FTV wifi controllers. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-q8-common.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi index 60fa9585022b..29f837a47771 100644 --- a/arch/arm/boot/dts/sun8i-q8-common.dtsi +++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi @@ -42,10 +42,59 @@ #include "sunxi-reference-design-tablet.dtsi" #include "sun8i-reference-design-tablet.dtsi" +/ { + aliases { + serial0 = &r_uart; + /* Make u-boot set mac-address for wifi without an eeprom */ + ethernet0 = &sdio_wifi; + }; + + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-simple"; + /* + * Q8 boards use various PL# pins as wifi-en. On other boards + * these may be connected to a wifi module output pin. To avoid + * short-circuits we configure these as inputs with pull-ups via + * pinctrl, instead of listing them as active-low reset-gpios. + */ + pinctrl-names = "default"; + pinctrl-0 = <&wifi_pwrseq_pin_q8>; + /* The esp8089 needs 200 ms after driving wifi-en high */ + post-power-on-delay-ms = <200>; + }; +}; + &ehci0 { status = "okay"; }; +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_a>; + vmmc-supply = <®_dldo1>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + status = "okay"; + + sdio_wifi: sdio_wifi@1 { + reg = <1>; + }; +}; + +&mmc1_pins_a { + allwinner,pull = ; +}; + +&r_pio { + wifi_pwrseq_pin_q8: wifi_pwrseq_pin@0 { + allwinner,pins = "PL6", "PL7", "PL11"; + allwinner,function = "gpio_in"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; -- cgit v1.2.3 From 6d2ce1c01cc6a6506e7206d58ffed2aa4caed5e7 Mon Sep 17 00:00:00 2001 From: James Pettigrew Date: Tue, 6 Sep 2016 08:15:56 +1000 Subject: ARM: dts: sun8i: Add dts file for the NanoPi NEO SBC The NanoPi NEO is a minimal H3 based SBC. It comes with 256/512M RAM, a micro SD slot, 10/100Mbit ethernet and a single USB-A port. Signed-off-by: James Pettigrew Reviewed-by: Rask Ingemann Lambertsen Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 125 ++++++++++++++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bb906f23d161..d5b7d9003bd2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -792,6 +792,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a83t-allwinner-h8homlet-v2.dtb \ sun8i-a83t-cubietruck-plus.dtb \ sun8i-h3-bananapi-m2-plus.dtb \ + sun8i-h3-nanopi-neo.dtb \ sun8i-h3-orangepi-2.dtb \ sun8i-h3-orangepi-lite.dtb \ sun8i-h3-orangepi-one.dtb \ diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts new file mode 100644 index 000000000000..3d64cafc1e90 --- /dev/null +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts @@ -0,0 +1,125 @@ +/* + * Copyright (C) 2016 James Pettigrew + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "sun8i-h3.dtsi" +#include "sunxi-common-regulators.dtsi" + +#include +#include + +/ { + model = "FriendlyARM NanoPi NEO"; + compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_opc>, <&leds_r_opc>; + + pwr { + label = "nanopi:green:pwr"; + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */ + default-state = "on"; + }; + + status { + label = "nanopi:blue:status"; + gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */ + }; + }; +}; + +&ehci3 { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */ + cd-inverted; + status = "okay"; +}; + +&ohci3 { + status = "okay"; +}; + +&pio { + leds_opc: led-pins { + allwinner,pins = "PA10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&r_pio { + leds_r_opc: led-pins { + allwinner,pins = "PL10"; + allwinner,function = "gpio_out"; + allwinner,drive = ; + allwinner,pull = ; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; +}; + +&usbphy { + /* USB VBUS is always on */ + status = "okay"; +}; -- cgit v1.2.3 From accfb2f19d185628858dc0c063c69c8b75b32724 Mon Sep 17 00:00:00 2001 From: James Pettigrew Date: Tue, 6 Sep 2016 08:15:57 +1000 Subject: devicetree: Add vendor prefix for FriendlyARM Guangzhou FriendlyARM Computer Tech Co., Ltd is a Chinese ARM board vendor. Signed-off-by: James Pettigrew Reviewed-by: Rask Ingemann Lambertsen Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..7b6bda3b4189 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -98,6 +98,7 @@ ezchip EZchip Semiconductor fcs Fairchild Semiconductor firefly Firefly focaltech FocalTech Systems Co.,Ltd +friendlyarm Guangzhou FriendlyARM Computer Tech Co., Ltd fsl Freescale Semiconductor ge General Electric Company geekbuying GeekBuying -- cgit v1.2.3 From d9c12685c69cd97037a347f3489b2a354c341a66 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 4 Aug 2016 11:52:24 +0200 Subject: ARM: dts: STiH415-pinctrl: update gpio-cells to 2 This patch allows to use second parameter to the gpio specifier, which is used to specify whether the gpio is active high or low. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih415-pinctrl.dtsi | 54 +++++++++++++++++----------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 3791ad95dbaf..bd028ce98b61 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -54,7 +54,7 @@ pio0: gpio@fe610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -62,7 +62,7 @@ }; pio1: gpio@fe611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -70,7 +70,7 @@ }; pio2: gpio@fe612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -78,7 +78,7 @@ }; pio3: gpio@fe613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -86,7 +86,7 @@ }; pio4: gpio@fe614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -208,7 +208,7 @@ pio5: gpio@fee00000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -216,7 +216,7 @@ }; pio6: gpio@fee01000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -224,7 +224,7 @@ }; pio7: gpio@fee02000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -232,7 +232,7 @@ }; pio8: gpio@fee03000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -240,7 +240,7 @@ }; pio9: gpio@fee04000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -248,7 +248,7 @@ }; pio10: gpio@fee05000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -256,7 +256,7 @@ }; pio11: gpio@fee06000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -264,7 +264,7 @@ }; pio12: gpio@fee07000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -303,7 +303,7 @@ pio13: gpio@fe820000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -311,7 +311,7 @@ }; pio14: gpio@fe821000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -319,7 +319,7 @@ }; pio15: gpio@fe822000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -327,7 +327,7 @@ }; pio16: gpio@fe823000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -335,7 +335,7 @@ }; pio17: gpio@fe824000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -343,7 +343,7 @@ }; pio18: gpio@fe825000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -465,7 +465,7 @@ pio100: gpio@fd6b0000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -473,7 +473,7 @@ }; pio101: gpio@fd6b1000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -481,7 +481,7 @@ }; pio102: gpio@fd6b2000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -502,7 +502,7 @@ pio103: gpio@fd330000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -510,7 +510,7 @@ }; pio104: gpio@fd331000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -518,7 +518,7 @@ }; pio105: gpio@fd332000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -526,7 +526,7 @@ }; pio106: gpio@fd333000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -534,7 +534,7 @@ }; pio107: gpio@fd334000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; -- cgit v1.2.3 From 973b932450b7a7e14de654bf32ceae37a5943ca1 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 4 Aug 2016 11:51:17 +0200 Subject: ARM: dts: STiH416-pinctrl: update gpio-cells to 2 This patch allows to use second parameter to the gpio specifier, which is used to specify whether the gpio is active high or low. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 60 +++++++++++++++++----------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 051fc16f3706..48474ccb460b 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -58,7 +58,7 @@ pio0: gpio@fe610000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -66,7 +66,7 @@ }; pio1: gpio@fe611000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -74,7 +74,7 @@ }; pio2: gpio@fe612000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -82,7 +82,7 @@ }; pio3: gpio@fe613000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -90,7 +90,7 @@ }; pio4: gpio@fe614000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -98,7 +98,7 @@ }; pio40: gpio@fe615000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -254,7 +254,7 @@ pio5: gpio@fee00000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -262,7 +262,7 @@ }; pio6: gpio@fee01000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -270,7 +270,7 @@ }; pio7: gpio@fee02000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -278,7 +278,7 @@ }; pio8: gpio@fee03000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -286,7 +286,7 @@ }; pio9: gpio@fee04000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -294,7 +294,7 @@ }; pio10: gpio@fee05000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -302,7 +302,7 @@ }; pio11: gpio@fee06000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x100>; @@ -310,7 +310,7 @@ }; pio12: gpio@fee07000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x100>; @@ -318,7 +318,7 @@ }; pio30: gpio@fee08000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x100>; @@ -326,7 +326,7 @@ }; pio31: gpio@fee09000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x9000 0x100>; @@ -404,7 +404,7 @@ pio13: gpio@fe820000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -412,7 +412,7 @@ }; pio14: gpio@fe821000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -420,7 +420,7 @@ }; pio15: gpio@fe822000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -428,7 +428,7 @@ }; pio16: gpio@fe823000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -436,7 +436,7 @@ }; pio17: gpio@fe824000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; @@ -444,7 +444,7 @@ }; pio18: gpio@fe825000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x100>; @@ -605,7 +605,7 @@ pio100: gpio@fd6b0000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -613,7 +613,7 @@ }; pio101: gpio@fd6b1000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -621,7 +621,7 @@ }; pio102: gpio@fd6b2000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -642,7 +642,7 @@ pio103: gpio@fd330000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0 0x100>; @@ -650,7 +650,7 @@ }; pio104: gpio@fd331000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x100>; @@ -658,7 +658,7 @@ }; pio105: gpio@fd332000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x100>; @@ -666,7 +666,7 @@ }; pio106: gpio@fd333000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x100>; @@ -675,7 +675,7 @@ pio107: gpio@fd334000 { gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x100>; -- cgit v1.2.3 From 2402850faca9cf56209cb9eff73c6203c90cf0c5 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 4 Aug 2016 11:44:32 +0200 Subject: ARM: dts: STiHxxx-b2120: update gpio specifier Remove useless gpio-cells Add second parameter to indicate if gpio is active high or low. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stihxxx-b2120.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 0b0dd024f72d..80ec40d3d987 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -18,14 +18,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <2>; label = "Front Panel LED"; - gpios = <&pio4 1 0>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; -- cgit v1.2.3 From 5984d65342965466594670693a40cc2edc834ba4 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 4 Aug 2016 11:50:21 +0200 Subject: ARM: dts: STiH41x-b2000: update gpio specifier Remove useless gpio-cells Add second parameter to indicate if gpio is active high or low. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih41x-b2000.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index 5f91f455f05b..9bfa0674b452 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -7,6 +7,8 @@ * publishhed by the Free Software Foundation. */ #include +#include + / { memory{ @@ -33,9 +35,8 @@ leds { compatible = "gpio-leds"; fp_led { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio105 7>; + gpios = <&pio105 7 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; -- cgit v1.2.3 From e9dacbf2bd7f4d05fec80311fa47920d9243b46c Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 4 Aug 2016 11:52:01 +0200 Subject: ARM: dts: STiH416-b2020e: update gpio specifier Remove useless gpio-cells Add second parameter to indicate if gpio is active high or low. Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih416-b2020e.dts | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts index f1ceee192a0e..de320cd067de 100644 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ b/arch/arm/boot/dts/stih416-b2020e.dts @@ -9,6 +9,7 @@ /dts-v1/; #include "stih416.dtsi" #include "stih41x-b2020.dtsi" +#include / { model = "STiH416 B2020 REV-E"; compatible = "st,stih416-b2020", "st,stih416"; @@ -17,13 +18,12 @@ leds { compatible = "gpio-leds"; red { - #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&pio4 1>; + gpios = <&pio4 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&pio1 3>; + gpios = <&pio1 3 GPIO_ACTIVE_HIGH>; default-state = "off"; }; }; -- cgit v1.2.3 From 65086c218ba093817cf9e06bd18a2bb4c40dd2fd Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH407: Supply PWM Capture IRQ Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih407-family.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 55ecfbea905d..c7a10bf0e02f 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -670,6 +670,7 @@ compatible = "st,sti-pwm"; #pwm-cells = <2>; reg = <0x9810000 0x68>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default>; clock-names = "pwm"; -- cgit v1.2.3 From 30a2366cb06ecfe46db80d01ecb1443a123622b0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH407: Declare PWM Capture data lines via Pinctrl Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 4be681aaf773..2cc7e03f342c 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -296,10 +296,12 @@ pinctrl_pwm1_chan0_default: pwm1-0-default { st,pins { pwm-out = <&pio3 0 ALT1 OUT>; + pwm-capturein = <&pio3 2 ALT1 IN>; }; }; pinctrl_pwm1_chan1_default: pwm1-1-default { st,pins { + pwm-capturein = <&pio4 3 ALT1 IN>; pwm-out = <&pio4 4 ALT1 OUT>; }; }; @@ -1044,6 +1046,7 @@ pwm0 { pinctrl_pwm0_chan0_default: pwm0-0-default { st,pins { + pwm-capturein = <&pio31 0 ALT1 IN>; pwm-out = <&pio31 1 ALT1 OUT>; }; }; -- cgit v1.2.3 From 230e68acd16e9f31d29899f5b17e4aa1d7dd3e77 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH416: Supply PWM Capture IRQs Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 9e3170ccd18c..d43f706dfd72 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -474,6 +474,7 @@ status = "disabled"; #pwm-cells = <2>; reg = <0xfed10000 0x68>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm0_chan0_default @@ -492,6 +493,7 @@ status = "disabled"; #pwm-cells = <2>; reg = <0xfe510000 0x68>; + interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1_chan0_default -- cgit v1.2.3 From 65bb4990b4cb2fa30908f7df7ac8e511158ac235 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH416: Declare PWM Capture data lines via Pinctrl Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416-pinctrl.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index 48474ccb460b..9c97f7e651a0 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -221,11 +221,14 @@ pinctrl_pwm1_chan0_default: pwm1-0-default { st,pins { pwm-out = <&pio3 0 ALT1 OUT>; + pwm-capturein = <&pio3 2 ALT1 IN>; + }; }; pinctrl_pwm1_chan1_default: pwm1-1-default { st,pins { pwm-out = <&pio4 4 ALT1 OUT>; + pwm-capturein = <&pio4 3 ALT1 IN>; }; }; pinctrl_pwm1_chan2_default: pwm1-2-default { @@ -337,6 +340,7 @@ pinctrl_pwm0_chan0_default: pwm0-0-default { st,pins { pwm-out = <&pio9 7 ALT2 OUT>; + pwm-capturein = <&pio9 6 ALT2 IN>; }; }; }; @@ -576,6 +580,7 @@ pinctrl_pwm0_chan1_default: pwm0-1-default { st,pins { pwm-out = <&pio13 2 ALT2 OUT>; + pwm-capturein = <&pio13 1 ALT2 IN>; }; }; pinctrl_pwm0_chan2_default: pwm0-2-default { -- cgit v1.2.3 From 5b1dd98064f6521f1a871e8db5410d8d2d6d4026 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH416: Define PWM Capture clock Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index d43f706dfd72..dbc2f517901b 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -482,8 +482,9 @@ &pinctrl_pwm0_chan2_default &pinctrl_pwm0_chan3_default>; - clock-names = "pwm"; - clocks = <&clk_sysin>; + clock-names = "pwm", "capture"; + clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; + st,pwm-num-chan = <4>; }; -- cgit v1.2.3 From 994834bc7e185d3bb8a21aabd29dd302fd719016 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 16 Aug 2016 11:34:00 +0200 Subject: ARM: dts: STiH416: Define the number of PWM Capture channels Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih416.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index dbc2f517901b..fe1f9cf770e4 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -486,6 +486,7 @@ clocks = <&clk_sysin>, <&clk_s_a0_ls CLK_ICN_REG>; st,pwm-num-chan = <4>; + st,capture-num-chan = <2>; }; /* SBC PWM Module */ -- cgit v1.2.3 From 05b23ebc2bd9b85fcc1891c2bd20b1949861ea77 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Mon, 29 Aug 2016 23:33:56 +0200 Subject: ARM: dts: armv7-m: remove skeleton.dtsi include MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove skeleton.dtsi from the common ARM Cortex-M dtsi. This will allow us to remove skeleton.dtsi on a per platform basis and get rid of the unit address warning on the memory nodes without getting duplicate memory nodes. See 3ebee5a2e141 ("arm64: dts: kill skeleton.dtsi") for additional reasons not to use the skeleton.dtsi. Signed-off-by: Joachim Eastwood Acked-by: Rob Herring Acked-by: Vladimir Murzin Acked-by: Stefan Agner Acked-by: Uwe Kleine-König Acked-by: Alexandre TORGUE --- arch/arm/boot/dts/armv7-m.dtsi | 2 -- arch/arm/boot/dts/efm32gg.dtsi | 2 ++ arch/arm/boot/dts/lpc18xx.dtsi | 1 + arch/arm/boot/dts/mps2.dtsi | 1 + arch/arm/boot/dts/stm32f429.dtsi | 1 + arch/arm/boot/dts/vf610m4.dtsi | 1 + 6 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/armv7-m.dtsi b/arch/arm/boot/dts/armv7-m.dtsi index 16331aa79775..ba332e399be4 100644 --- a/arch/arm/boot/dts/armv7-m.dtsi +++ b/arch/arm/boot/dts/armv7-m.dtsi @@ -1,5 +1,3 @@ -#include "skeleton.dtsi" - / { nvic: interrupt-controller@e000e100 { compatible = "arm,armv7m-nvic"; diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi index c747983771c7..d9dbf7f2090c 100644 --- a/arch/arm/boot/dts/efm32gg.dtsi +++ b/arch/arm/boot/dts/efm32gg.dtsi @@ -4,6 +4,8 @@ * Documentation available from * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf */ + +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "dt-bindings/clock/efm32-cmu.h" diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 3d828fcfc7c4..e956ea8aff16 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -11,6 +11,7 @@ * */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "dt-bindings/clock/lpc18xx-cgu.h" diff --git a/arch/arm/boot/dts/mps2.dtsi b/arch/arm/boot/dts/mps2.dtsi index e3fed8d34558..efb8a03cb970 100644 --- a/arch/arm/boot/dts/mps2.dtsi +++ b/arch/arm/boot/dts/mps2.dtsi @@ -42,6 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" / { diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index 35df462559ca..8e69328c00e4 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -45,6 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include diff --git a/arch/arm/boot/dts/vf610m4.dtsi b/arch/arm/boot/dts/vf610m4.dtsi index 9ffe2eb68ed4..9f2c731839f2 100644 --- a/arch/arm/boot/dts/vf610m4.dtsi +++ b/arch/arm/boot/dts/vf610m4.dtsi @@ -42,6 +42,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "vfxxx.dtsi" -- cgit v1.2.3 From 0555a6be0691f14b48371d5359bab4ccc73023ef Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Mon, 29 Aug 2016 23:37:24 +0200 Subject: ARM: dts: lpc18xx: remove skeleton.dtsi include and fix unit address warnings Removale of skeleton.dtsi allows us also to fix the following warning from the dts compiler: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name by adding proper unit addresses to the memory nodes. Signed-off-by: Joachim Eastwood Acked-by: Rob Herring --- arch/arm/boot/dts/lpc18xx.dtsi | 4 +++- arch/arm/boot/dts/lpc4337-ciaa.dts | 2 +- arch/arm/boot/dts/lpc4350-hitex-eval.dts | 2 +- arch/arm/boot/dts/lpc4357-ea4357-devkit.dts | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index e956ea8aff16..7cae9c5e27db 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -11,7 +11,6 @@ * */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "dt-bindings/clock/lpc18xx-cgu.h" @@ -21,6 +20,9 @@ #define LPC_GPIO(port, pin) (port * 32 + pin) / { + #address-cells = <1>; + #size-cells = <1>; + cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/lpc4337-ciaa.dts b/arch/arm/boot/dts/lpc4337-ciaa.dts index 5cfadb06c8df..7c16d639a1b4 100644 --- a/arch/arm/boot/dts/lpc4337-ciaa.dts +++ b/arch/arm/boot/dts/lpc4337-ciaa.dts @@ -30,7 +30,7 @@ stdout-path = &uart2; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x0800000>; /* 8 MB */ }; diff --git a/arch/arm/boot/dts/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/lpc4350-hitex-eval.dts index c97cba1d26a8..874c75d44013 100644 --- a/arch/arm/boot/dts/lpc4350-hitex-eval.dts +++ b/arch/arm/boot/dts/lpc4350-hitex-eval.dts @@ -33,7 +33,7 @@ stdout-path = &uart0; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x800000>; /* 8 MB */ }; diff --git a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts index 1919be4dab2b..9b5fad622522 100644 --- a/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts +++ b/arch/arm/boot/dts/lpc4357-ea4357-devkit.dts @@ -33,7 +33,7 @@ stdout-path = &uart0; }; - memory { + memory@28000000 { device_type = "memory"; reg = <0x28000000 0x2000000>; /* 32 MB */ }; -- cgit v1.2.3 From 836407462244cc4d8b1172f1f835035801692a77 Mon Sep 17 00:00:00 2001 From: Joachim Eastwood Date: Mon, 29 Aug 2016 23:58:29 +0200 Subject: ARM: dts: efm32: remove skeleton.dtsi include and fix unit address warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Removale of skeleton.dtsi allows us also to fix the following warning from the dts compiler: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name by adding proper unit addresses to the memory nodes. Also add missing device_type to the memory node while at it. Signed-off-by: Joachim Eastwood Acked-by: Rob Herring Acked-by: Uwe Kleine-König --- arch/arm/boot/dts/efm32gg-dk3750.dts | 5 +++-- arch/arm/boot/dts/efm32gg.dtsi | 4 +++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/efm32gg-dk3750.dts b/arch/arm/boot/dts/efm32gg-dk3750.dts index 504cf45d3cb8..98fc667d22c7 100644 --- a/arch/arm/boot/dts/efm32gg-dk3750.dts +++ b/arch/arm/boot/dts/efm32gg-dk3750.dts @@ -16,7 +16,8 @@ bootargs = "console=ttyefm4,115200 init=/linuxrc ignore_loglevel ihash_entries=64 dhash_entries=64 earlyprintk uclinux.physaddr=0x8c400000 root=/dev/mtdblock0"; }; - memory { + memory@88000000 { + device_type = "memory"; reg = <0x88000000 0x400000>; }; @@ -74,7 +75,7 @@ status = "ok"; }; - boardfpga: boardfpga { + boardfpga: boardfpga@80000000 { compatible = "efm32board"; reg = <0x80000000 0x400>; irq-gpios = <&gpio 64 1>; diff --git a/arch/arm/boot/dts/efm32gg.dtsi b/arch/arm/boot/dts/efm32gg.dtsi index d9dbf7f2090c..b78c57e51ed5 100644 --- a/arch/arm/boot/dts/efm32gg.dtsi +++ b/arch/arm/boot/dts/efm32gg.dtsi @@ -5,11 +5,13 @@ * http://www.silabs.com/Support%20Documents/TechnicalDocs/EFM32GG-RM.pdf */ -#include "skeleton.dtsi" #include "armv7-m.dtsi" #include "dt-bindings/clock/efm32-cmu.h" / { + #address-cells = <1>; + #size-cells = <1>; + aliases { i2c0 = &i2c0; i2c1 = &i2c1; -- cgit v1.2.3 From e678114f86edc40f394a82231c239c8cdfb4191c Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Sat, 3 Sep 2016 01:09:26 +0300 Subject: ARM: dts: wheat: add QSPI support Define the Wheat board dependent part of the QSPI device node. Add device nodes for Spansion S25FL512S SPI flash and MTD partitions on it. Based on the original (and large) patch by Vladimir Barinov . Signed-off-by: Sergei Shtylyov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index ff37de35c57c..0ec4bc606c61 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -103,6 +103,11 @@ groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; }; + + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data4"; + function = "qspi"; + }; }; &scif0 { @@ -134,3 +139,41 @@ cd-gpios = <&gpio11 11 GPIO_ACTIVE_LOW>; status = "okay"; }; + +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "spansion,s25fl512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <30000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + spi-cpol; + spi-cpha; + m25p,fast-read; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "loader"; + reg = <0x00000000 0x00040000>; + read-only; + }; + partition@40000 { + label = "user"; + reg = <0x00040000 0x00400000>; + read-only; + }; + partition@440000 { + label = "flash"; + reg = <0x00440000 0x03bc0000>; + }; + }; + }; +}; -- cgit v1.2.3 From fa8f4aba72e6d619c003dab60f58ab6c7410e465 Mon Sep 17 00:00:00 2001 From: Sergei Shtylyov Date: Tue, 6 Sep 2016 00:33:05 +0300 Subject: ARM: dts: wheat: add support for tactile switches Add support for the tactile switches SW2/3 (on the debug board) as a virtual keyboard like it was done with the Blanche board). Signed-off-by: Sergei Shtylyov Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-wheat.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index 0ec4bc606c61..6dbb94114a93 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -12,6 +12,7 @@ /dts-v1/; #include "r8a7792.dtsi" #include +#include / { model = "Wheat"; @@ -56,6 +57,25 @@ pinctrl-names = "default"; }; + keyboard { + compatible = "gpio-keys"; + + key-a { + linux,code = ; + label = "SW2"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + }; + key-b { + linux,code = ; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio11 2 GPIO_ACTIVE_LOW>; + }; + }; + vcc_sdhi0: regulator-vcc-sdhi0 { compatible = "regulator-fixed"; -- cgit v1.2.3 From 5a3dbab2040a6934a5f8fc2e072948a198f414db Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Wed, 7 Sep 2016 11:22:57 +0200 Subject: ARM: dts: STiH410-b2260: add USB3 node Allow to use the mico USB port which is driven by USB3 IP Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih410-b2260.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index 94e064f193b2..d5d8d08a504c 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -147,6 +147,10 @@ status = "okay"; }; + st_dwc3: dwc3@8f94000 { + status = "okay"; + }; + ethernet0: dwmac@9630000 { phy-mode = "rgmii"; pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>; -- cgit v1.2.3 From a29c830a28721bb684c212206b2bab6dc53d0cb4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 22 Aug 2016 17:36:33 +0200 Subject: ARM: dts: meson8b: Add Meson8b PWM Controller nodes Signed-off-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index fc4080de4b7b..41fd53671859 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -162,6 +162,27 @@ reg = <0xc1108000 0x4>, <0xc1104000 0x460>; }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc1108550 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_cd: pwm@8650 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc1108650 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0xc11086c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; + pinctrl_cbus: pinctrl@c1109880 { compatible = "amlogic,meson8b-cbus-pinctrl"; reg = <0xc1109880 0x10>; -- cgit v1.2.3 From bbfd09d95466833f58ee487fd67be0ce7276be93 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Thu, 8 Sep 2016 09:36:19 +0200 Subject: ARM: dts: STiH410-b2260: add clk_ignore_unused in bootargs This allows to make the board boot even if clock handling by all drivers is not properly done. Reported-by: Peter Griffin Signed-off-by: Patrice Chotard --- arch/arm/boot/dts/stih410-b2260.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih410-b2260.dts b/arch/arm/boot/dts/stih410-b2260.dts index d5d8d08a504c..ef2ff2f518f6 100644 --- a/arch/arm/boot/dts/stih410-b2260.dts +++ b/arch/arm/boot/dts/stih410-b2260.dts @@ -15,7 +15,7 @@ compatible = "st,stih410-b2260", "st,stih410"; chosen { - bootargs = "console=ttyAS1,115200"; + bootargs = "console=ttyAS1,115200 clk_ignore_unused"; linux,stdout-path = &uart1; }; -- cgit v1.2.3 From 8266b4ae7135d324f100fc76c1364f63029005dd Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Mon, 5 Sep 2016 12:11:16 +0200 Subject: devicetree: Add vendor prefix for Inverse Path Inverse Path is an information security consulting company: https://inversepath.com Signed-off-by: Andrej Rosano Acked-by: Rob Herring Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..3003f33d4c72 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -135,6 +135,7 @@ innolux Innolux Corporation intel Intel Corporation intercontrol Inter Control Group invensense InvenSense Inc. +inversepath Inverse Path isee ISEE 2007 S.L. isil Intersil issi Integrated Silicon Solutions Inc. -- cgit v1.2.3 From 17028ca2a5030a2e97f87b3290f814ba860480c0 Mon Sep 17 00:00:00 2001 From: Andrej Rosano Date: Mon, 5 Sep 2016 12:11:17 +0200 Subject: ARM: dts: imx53: add support for USB armory board Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on NXP i.MX53 SoC. https://inversepath.com/usbarmory Signed-off-by: Andrej Rosano Tested-by: Vagrant Cascadian Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx53-usbarmory.dts | 224 ++++++++++++++++++++++++++++++++++ 2 files changed, 225 insertions(+) create mode 100644 arch/arm/boot/dts/imx53-usbarmory.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5dcc2394fbad..f79cac25afa8 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -315,6 +315,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-smd.dtb \ imx53-tx53-x03x.dtb \ imx53-tx53-x13x.dtb \ + imx53-usbarmory.dtb \ imx53-voipac-bsb.dtb dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-apf6dev.dtb \ diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts new file mode 100644 index 000000000000..6782d7fc5961 --- /dev/null +++ b/arch/arm/boot/dts/imx53-usbarmory.dts @@ -0,0 +1,224 @@ +/* + * USB armory MkI device tree file + * https://inversepath.com/usbarmory + * + * Copyright (C) 2015, Inverse Path + * Andrej Rosano + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "imx53.dtsi" + +/ { + model = "Inverse Path USB armory"; + compatible = "inversepath,imx53-usbarmory", "fsl,imx53"; +}; + +/ { + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x70000000 0x20000000>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user { + label = "LED"; + gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +/* + * Not every i.MX53 P/N supports clock > 800MHz. + * As USB armory does not mount a specific P/N set a safe clock upper limit. + */ +&cpu0 { + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + >; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&iomuxc { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_i2c1_pmic: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x80 + MX53_PAD_EIM_D28__I2C1_SDA 0x80 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_DISP0_DAT6__GPIO4_27 0x1e4 + >; + }; + + /* + * UART mode pin header configration + * 3 - GPIO5[26], pull-down 100K + * 4 - GPIO5[27], pull-down 100K + * 5 - TX, pull-up 100K + * 6 - RX, pull-up 100K + * 7 - GPIO5[30], pull-down 100K + */ + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_CSI0_DAT8__GPIO5_26 0xc0 + MX53_PAD_CSI0_DAT9__GPIO5_27 0xc0 + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4 + MX53_PAD_CSI0_DAT12__GPIO5_30 0xc0 + >; + }; +}; + +&i2c1 { + pinctrl-0 = <&pinctrl_i2c1_pmic>; + status = "okay"; + + ltc3589: pmic@34 { + compatible = "lltc,ltc3589-2"; + reg = <0x34>; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <591930>; + regulator-max-microvolt = <1224671>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456803>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3_reg: sw3 { + regulator-min-microvolt = <1341250>; + regulator-max-microvolt = <2775000>; + lltc,fb-voltage-divider = <270000 100000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + bb_out_reg: bb-out { + regulator-min-microvolt = <3387341>; + regulator-max-microvolt = <3387341>; + lltc,fb-voltage-divider = <511000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + regulator-min-microvolt = <1306329>; + regulator-max-microvolt = <1306329>; + lltc,fb-voltage-divider = <100000 158000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + regulator-min-microvolt = <704123>; + regulator-max-microvolt = <1456806>; + lltc,fb-voltage-divider = <180000 191000>; + regulator-ramp-delay = <7000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3_reg: ldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3200000>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; -- cgit v1.2.3 From 9e2ce1953c7fe380b2e3e9749c32847087964f18 Mon Sep 17 00:00:00 2001 From: Meng Yi Date: Tue, 6 Sep 2016 17:45:34 +0800 Subject: ARM: dts: ls1021a: Add of_graph dt nodes to describe the panel add of_graph dt nodes to describe the panel, and removed "fsl,panel" property Signed-off-by: Meng Yi Acked-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-twr.dts | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts index 75ecaed32ae5..a8b148ad1dd2 100644 --- a/arch/arm/boot/dts/ls1021a-twr.dts +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -108,12 +108,23 @@ panel: panel { compatible = "nec,nl4827hc19-05b"; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; }; }; &dcu { - fsl,panel = <&panel>; status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &dspi1 { -- cgit v1.2.3 From 78eb28a86df16d0dfb62c75e81b374e39a0b803d Mon Sep 17 00:00:00 2001 From: Stefan Agner Date: Tue, 6 Sep 2016 11:46:57 -0700 Subject: ARM: dts: vf610-colibri: use of_graph dt nodes to describe the panel The fsl,panel property is deprecated and we should use the new of_graph dt bindings to describe the relationship between the DCU controller and the panel. Signed-off-by: Stefan Agner Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf-colibri-eval-v3.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index a8a8e434fb27..1e0b823f7e8f 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -53,6 +53,12 @@ panel: panel { compatible = "edt,et057090dhu"; backlight = <&bl>; + + port { + panel_in: endpoint { + remote-endpoint = <&dcu_out>; + }; + }; }; reg_3v3: regulator-3v3 { @@ -91,8 +97,13 @@ &dcu0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dcu0_1>; - fsl,panel = <&panel>; status = "okay"; + + port { + dcu_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; }; &dspi1 { -- cgit v1.2.3 From f8979757f17ca2dcd423a0604bfe21048824409c Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Thu, 8 Sep 2016 11:28:15 +0200 Subject: ARM: dts: imx35: add iim module to imx35.dtsi MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is a prerequisite to remove the static mappings for imx35 devicetree based machines. Signed-off-by: Uwe Kleine-König Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 490b7b44f1e7..f812d586c5ce 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -309,6 +309,13 @@ status = "disabled"; }; + iim@53ff0000 { + compatible = "fsl,imx35-iim"; + reg = <0x53ff0000 0x4000>; + interrupts = <19>; + clocks = <&clks 80>; + }; + usbotg: usb@53ff4000 { compatible = "fsl,imx35-usb", "fsl,imx27-usb"; reg = <0x53ff4000 0x0200>; -- cgit v1.2.3 From bb728d662bed0fe91b152550e640cb3f6caa972c Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Fri, 9 Sep 2016 05:02:36 +0300 Subject: ARM: dts: add gpio-ranges property to iMX GPIO controllers To establish a connection between GPIO controllers and pin multiplexor controller add gpio-ranges properties to all GPIO controllers found on iMX50, iMX6Q/D, iMX6DL/S, iMX6SL, iMX6SX, iMX6UL and iMX7D/S SoCs. The change was done after human parsing of output from % gawk -n '{ sub(/.*__/, ""); if ($1 ~ "^GPIO") print $1, $2/4}' imxXX-pinfunc.h | sort -n Signed-off-by: Vladimir Zapolskiy Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 10 ++++++++ arch/arm/boot/dts/imx6dl.dtsi | 53 +++++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6q.dtsi | 37 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6sl.dtsi | 47 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6sx.dtsi | 7 ++++++ arch/arm/boot/dts/imx6ul.dtsi | 6 +++++ arch/arm/boot/dts/imx7s.dtsi | 7 ++++++ 7 files changed, 167 insertions(+) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index e2457138311f..8fe8beeb68a4 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -227,6 +227,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 151 28>; }; gpio2: gpio@53f88000 { @@ -237,6 +238,10 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 75 8>, <&iomuxc 8 100 8>, + <&iomuxc 16 83 1>, <&iomuxc 17 85 1>, + <&iomuxc 18 87 1>, <&iomuxc 19 84 1>, + <&iomuxc 20 88 1>, <&iomuxc 21 86 1>; }; gpio3: gpio@53f8c000 { @@ -247,6 +252,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 108 32>; }; gpio4: gpio@53f90000 { @@ -257,6 +263,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 8 8>, <&iomuxc 8 45 12>, + <&iomuxc 20 140 11>; }; wdog1: wdog@53f98000 { @@ -346,6 +354,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 57 18>, <&iomuxc 18 89 11>; }; gpio6: gpio@53fe0000 { @@ -356,6 +365,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 27 18>, <&iomuxc 18 16 11>; }; i2c3: i2c@53fec000 { diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index 9a4c22c2dade..1ade1951e620 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -111,6 +111,59 @@ }; }; +&gpio1 { + gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, + <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, + <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, + <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, + <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, + <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, + <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, + <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, + <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, + <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, + <&iomuxc 28 113 4>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, + <&iomuxc 16 81 16>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, + <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, + <&iomuxc 11 151 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, + <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, + <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, + <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, + <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, + <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, + <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, + <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, + <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, + <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, + <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, + <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, + <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; +}; + &gpt { compatible = "fsl,imx6dl-gpt"; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index c30c8368cae0..e9a5d0b8c7b0 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -209,6 +209,43 @@ }; }; +&gpio1 { + gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>, + <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>, + <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>, + <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>, + <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>, + <&iomuxc 22 116 10>; +}; + +&gpio2 { + gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>, + <&iomuxc 31 44 1>; +}; + +&gpio3 { + gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>; +}; + +&gpio4 { + gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>; +}; + +&gpio5 { + gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>, + <&iomuxc 5 103 13>, <&iomuxc 18 150 14>; +}; + +&gpio6 { + gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>, + <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>, + <&iomuxc 31 86 1>; +}; + +&gpio7 { + gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>; +}; + &hdmi { compatible = "fsl,imx6q-hdmi"; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 542515089b1e..02378db3f5fc 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -375,6 +375,12 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, + <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, + <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, + <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, + <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, + <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; }; gpio2: gpio@020a0000 { @@ -386,6 +392,13 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, + <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, + <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, + <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, + <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, + <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, + <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; }; gpio3: gpio@020a4000 { @@ -397,6 +410,14 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, + <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, + <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, + <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, + <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, + <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, + <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, + <&iomuxc 31 102 1>; }; gpio4: gpio@020a8000 { @@ -408,6 +429,21 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, + <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, + <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, + <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, + <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, + <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, + <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, + <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, + <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, + <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, + <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, + <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, + <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, + <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, + <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; }; gpio5: gpio@020ac000 { @@ -419,6 +455,17 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, + <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, + <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, + <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, + <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, + <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, + <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, + <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, + <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, + <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, + <&iomuxc 21 161 1>; }; kpp: kpp@020b8000 { diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 356dc385c96f..1a473e83efbf 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -448,6 +448,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 5 26>; }; gpio2: gpio@020a0000 { @@ -459,6 +460,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 31 20>; }; gpio3: gpio@020a4000 { @@ -470,6 +472,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 51 29>; }; gpio4: gpio@020a8000 { @@ -481,6 +484,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 80 32>; }; gpio5: gpio@020ac000 { @@ -492,6 +496,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 112 24>; }; gpio6: gpio@020b0000 { @@ -503,6 +508,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 136 12>, <&iomuxc 12 158 11>; }; gpio7: gpio@020b4000 { @@ -514,6 +520,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 148 10>, <&iomuxc 10 169 2>; }; kpp: kpp@020b8000 { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index acc948654b82..c5c05fdccc78 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -411,6 +411,8 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, + <&iomuxc 16 33 16>; }; gpio2: gpio@020a0000 { @@ -422,6 +424,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; }; gpio3: gpio@020a4000 { @@ -433,6 +436,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 65 29>; }; gpio4: gpio@020a8000 { @@ -444,6 +448,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; }; gpio5: gpio@020ac000 { @@ -455,6 +460,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; }; fec2: ethernet@020b4000 { diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index bb7102cae899..0d7d5ac6257b 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -321,6 +321,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; }; gpio2: gpio@30210000 { @@ -332,6 +333,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 13 32>; }; gpio3: gpio@30220000 { @@ -343,6 +345,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 45 29>; }; gpio4: gpio@30230000 { @@ -354,6 +357,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 74 24>; }; gpio5: gpio@30240000 { @@ -365,6 +369,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 98 18>; }; gpio6: gpio@30250000 { @@ -376,6 +381,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 116 23>; }; gpio7: gpio@30260000 { @@ -387,6 +393,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 139 16>; }; wdog1: wdog@30280000 { -- cgit v1.2.3 From 390aafe324e930a640deae6c2e029f7a79650df8 Mon Sep 17 00:00:00 2001 From: Jean-Christophe Trotin Date: Mon, 25 Jul 2016 09:57:30 +0200 Subject: ARM: dts: STiH410: Add hva dt nodes Add the hva (multi-format video encoder for STMicroelectronics SoC) dt nodes for the hva device, defining register address, interrupt and clock. Signed-off-by: Jean-Christophe TROTIN --- arch/arm/boot/dts/stih410.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 7590721e9e97..6850f5861dc3 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -228,6 +228,16 @@ clocks = <&clk_s_c0_flexgen CLK_IC_BDISP_0>; }; + hva@8c85000 { + compatible = "st,st-hva"; + reg = <0x8c85000 0x400>, <0x6000000 0x40000>; + reg-names = "hva_registers", "hva_esram"; + interrupts = , + ; + clock-names = "clk_hva"; + clocks = <&clk_s_c0_flexgen CLK_HVA>; + }; + thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; -- cgit v1.2.3 From c4ad72560df11961d3e57fb0fadfe88a9863c9ad Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 Sep 2016 10:48:38 +0200 Subject: ARM: dts: fix RealView EB SMSC ethernet version The ethernet version in the earlier RealView EB variants is LAN91C111 and not LAN9118 according to ARM DUI 0303E "RealView Emulation Baseboard User Guide" page 3-57. Make sure that this is used for the base variant of the board. As the DT bindings for LAN91C111 does not specify any power supplies, these need to be deleted from the DTS file. Fixes: 2440d29d2ae2 ("ARM: dts: realview: support all the RealView EB board variants") Signed-off-by: Linus Walleij --- arch/arm/boot/dts/arm-realview-eb.dtsi | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm-realview-eb.dtsi index 1c6a040218e3..e2e9599596e2 100644 --- a/arch/arm/boot/dts/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm-realview-eb.dtsi @@ -51,14 +51,6 @@ regulator-boot-on; }; - veth: fixedregulator@0 { - compatible = "regulator-fixed"; - regulator-name = "veth"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - xtal24mhz: xtal24mhz@24M { #clock-cells = <0>; compatible = "fixed-clock"; @@ -134,16 +126,15 @@ bank-width = <4>; }; - /* SMSC 9118 ethernet with PHY and EEPROM */ + /* SMSC LAN91C111 ethernet with PHY and EEPROM */ ethernet: ethernet@4e000000 { - compatible = "smsc,lan9118", "smsc,lan9115"; + compatible = "smsc,lan91c111"; reg = <0x4e000000 0x10000>; - phy-mode = "mii"; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vdd33a-supply = <&veth>; - vddvario-supply = <&veth>; + /* + * This means the adapter can be accessed with 8, 16 or + * 32 bit reads/writes. + */ + reg-io-width = <7>; }; usb: usb@4f000000 { -- cgit v1.2.3 From 6a29fa31cdcf9e2ddf74406bd084067b4917edcd Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 Sep 2016 11:17:14 +0200 Subject: ARM: dts: add device tree for the RealView EB Rev D The RealView EB baseboard revision D is a special case as it appears to be undocumented in ARM official documents, while the Linux kernel still contains special code for handling it. commit be4f3c8691492934c8ee03dbecb3a3a865ac6cd6 "Add RealView/EB support for the LAN9118 Ethernet chip" adds support for the SMSC LAN9118 chip used on the D revision of the baseboard, but no other traces of hardware deviations for this variant can be found. This creates a separate top-level .dts file especially for this board version, so that it gets registered with the right type of ethernet controller. The ethernet controller modifications are then put into a separate .dtsi file so it can be overlaid on other EB variants using the revision D baseboard. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/arm-realview-eb-bbrevd.dts | 29 +++++++++++++++++ arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi | 45 +++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) create mode 100644 arch/arm/boot/dts/arm-realview-eb-bbrevd.dts create mode 100644 arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..6d3519fa07c3 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -608,6 +608,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb \ arm-realview-pb11mp.dtb \ arm-realview-eb.dtb \ + arm-realview-eb-bbrevd.dtb \ arm-realview-eb-11mp.dtb \ arm-realview-eb-11mp-revb.dtb \ arm-realview-eb-a9mp.dtb \ diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts new file mode 100644 index 000000000000..f533c8b49d97 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dts @@ -0,0 +1,29 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/* This derives from the Realview Baseboard, and overlays the new ethernet */ +#include "arm-realview-eb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi new file mode 100644 index 000000000000..a79e1d1d30a7 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-bbrevd.dtsi @@ -0,0 +1,45 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/ { + /* Introduce a fixed regulator for the new ethernet controller */ + veth: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "veth"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +/* + * The revision D has a different ethernet controller that the elder boards: + * the older board uses LAN91C111 but the new one uses LAN9118. + */ +ðernet { + compatible = "smsc,lan9118", "smsc,lan9115"; + phy-mode = "mii"; + smsc,irq-active-high; + smsc,irq-push-pull; + vdd33a-supply = <&veth>; + vddvario-supply = <&veth>; +}; -- cgit v1.2.3 From 5809938c5c9200b68fdcaba4f89880829d510c00 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 Sep 2016 17:00:45 +0200 Subject: ARM: dts: split RealView EB 11MPCore variants There used to be two versions of the RealView EB 11MPCore: - arm-realview-eb-11mp.dts: the most common variant supported by QEMU with the revision C core tile - arm-realview-eb-revb.dts: for the variant with the elder revision B core tile. As it turns out that there are also a few variants of the baseboard, unrelated to the coretile, and that these can of course be mounted on top of each other in all permutations, we create: - arm-realview-eb-11mp.dts: the most common variant supported by QEMU with the pre-revision D baseboard and the revision C core tile. - arm-realview-eb-11mp-bbrevd.dts: the revision D baseboard with the common revision C core tile. - arm-realview-eb-11mp-ctrevb.dts: the pre-revision D baseboard with the revision B core tile. - arm-realview-eb-11mp-bbrevd-ctrevb.dts: the revision D baseboard with the revision B core time. Or as a table: | Core tile: C | Core tile: B -----------+----------------------------+----------------------------------- Baseboard: | | pre-D |arm-realvie-eb-11mp | arm-realview-eb-11mp-ctrevb -----------+----------------------------+----------------------------------- Baseboard: | | D |arm-realview-eb-11mp-bbrevd | arm-realview-eb-11mp-bbrevd-ctrevb -----------+----------------------------+----------------------------------- Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 4 +- .../dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts | 32 ++++++++ arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts | 28 +++++++ arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts | 93 ++++++++++++++++++++++ arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts | 93 ---------------------- arch/arm/boot/dts/arm-realview-eb-11mp.dts | 2 +- 6 files changed, 157 insertions(+), 95 deletions(-) create mode 100644 arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts create mode 100644 arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts create mode 100644 arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts delete mode 100644 arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 6d3519fa07c3..2ec6f6236165 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -610,7 +610,9 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-eb.dtb \ arm-realview-eb-bbrevd.dtb \ arm-realview-eb-11mp.dtb \ - arm-realview-eb-11mp-revb.dtb \ + arm-realview-eb-11mp-bbrevd.dtb \ + arm-realview-eb-11mp-ctrevb.dtb \ + arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ arm-realview-eb-a9mp.dtb \ arm-realview-pba8.dtb \ arm-realview-pbx-a9.dtb diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts new file mode 100644 index 000000000000..e18769df9fd9 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd-ctrevb.dts @@ -0,0 +1,32 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp-ctrevb.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/* + * This is the EB with the new Revision D baseboard with SMSC9118 ethernet and + * the Rev B core tile. + */ +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Core Tile Rev B"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts new file mode 100644 index 000000000000..26b1c69e9f43 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-11mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView Emulation Baseboard Rev D with ARM11MPCore Rev C Core Tile"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts new file mode 100644 index 000000000000..e68527b0d552 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-11mp-ctrevb.dts @@ -0,0 +1,93 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-11mp.dts" + +/ { + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; +}; + +/* + * The revision B has a distinctly different layout of the syscon, so + * append a specific compatible-string. + */ +&syscon { + compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; +}; + +&intc { + reg = <0x10101000 0x1000>, + <0x10100100 0x100>; +}; + +&L2 { + reg = <0x10102000 0x1000>; +}; + +&scu { + reg = <0x10100000 0x100>; +}; + +&twd_timer { + reg = <0x10100600 0x20>; +}; + +&twd_wdog { + reg = <0x10100620 0x20>; +}; + +/* + * On revision B, we cannot reach the secondary interrupt + * controller, as a result, some peripherals that are dependent + * on their IRQ cannot be reached, so disable them. + */ +&intc_second { + status = "disabled"; +}; + +&gpio0 { + status = "disabled"; +}; + +&gpio1 { + status = "disabled"; +}; + +&gpio2 { + status = "disabled"; +}; + +&serial2 { + status = "disabled"; +}; + +&serial3 { + status = "disabled"; +}; + +&ssp { + status = "disabled"; +}; + +&wdog { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts b/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts deleted file mode 100644 index e68527b0d552..000000000000 --- a/arch/arm/boot/dts/arm-realview-eb-11mp-revb.dts +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright 2016 Linaro Ltd - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ - -#include "arm-realview-eb-11mp.dts" - -/ { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev B"; -}; - -/* - * The revision B has a distinctly different layout of the syscon, so - * append a specific compatible-string. - */ -&syscon { - compatible = "arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon", "simple-mfd"; -}; - -&intc { - reg = <0x10101000 0x1000>, - <0x10100100 0x100>; -}; - -&L2 { - reg = <0x10102000 0x1000>; -}; - -&scu { - reg = <0x10100000 0x100>; -}; - -&twd_timer { - reg = <0x10100600 0x20>; -}; - -&twd_wdog { - reg = <0x10100620 0x20>; -}; - -/* - * On revision B, we cannot reach the secondary interrupt - * controller, as a result, some peripherals that are dependent - * on their IRQ cannot be reached, so disable them. - */ -&intc_second { - status = "disabled"; -}; - -&gpio0 { - status = "disabled"; -}; - -&gpio1 { - status = "disabled"; -}; - -&gpio2 { - status = "disabled"; -}; - -&serial2 { - status = "disabled"; -}; - -&serial3 { - status = "disabled"; -}; - -&ssp { - status = "disabled"; -}; - -&wdog { - status = "disabled"; -}; diff --git a/arch/arm/boot/dts/arm-realview-eb-11mp.dts b/arch/arm/boot/dts/arm-realview-eb-11mp.dts index 87ff602a2a2d..aac1edd4b227 100644 --- a/arch/arm/boot/dts/arm-realview-eb-11mp.dts +++ b/arch/arm/boot/dts/arm-realview-eb-11mp.dts @@ -24,7 +24,7 @@ #include "arm-realview-eb-mp.dtsi" / { - model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C"; + model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile"; arm,hbi = <0x146>; /* -- cgit v1.2.3 From b4e54510b51ae666ed7cef291bba0f86ad3d8e20 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Thu, 8 Sep 2016 22:50:39 +0200 Subject: ARM: dts: add RealView EB rev D A9 MPCore variant The Cortex A9 MPCore tile can be mounted on top of the revision D variant of the RealView EB, so create another variant of the DTS file for this. arm-realview-eb-a9mp = mounted on pre-revision D baseboard arm-realview-eb-a9mp-bbrevd = mounted on the revision D baseboard Signed-off-by: Linus Walleij --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts | 28 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 2ec6f6236165..0f911bdc4282 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -614,6 +614,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-eb-11mp-ctrevb.dtb \ arm-realview-eb-11mp-bbrevd-ctrevb.dtb \ arm-realview-eb-a9mp.dtb \ + arm-realview-eb-a9mp-bbrevd.dtb \ arm-realview-pba8.dtb \ arm-realview-pbx-a9.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ diff --git a/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts b/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts new file mode 100644 index 000000000000..42efac7496ef --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-eb-a9mp-bbrevd.dts @@ -0,0 +1,28 @@ +/* + * Copyright 2016 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "arm-realview-eb-a9mp.dts" +#include "arm-realview-eb-bbrevd.dtsi" + +/ { + model = "ARM RealView EB Baseboard Rev D Cortex A9 MPCore"; +}; -- cgit v1.2.3 From 6d996f361bb83de25867347af230d6807de1caa7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 10 Feb 2016 09:34:32 +0100 Subject: ARM: dts: add STMPE PWM to the NHK15 device tree This adds the STMPE PWM to the NHK15 device tree. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index d35aa88791ad..3ec5c653ad56 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -140,6 +140,10 @@ 0x03020067 // Up 0x0303006c>; // Down }; + stmpe0_pwm: stmpe_pwm { + compatible = "st,stmpe-pwm"; + #pwm-cells = <2>; + }; }; stmpe1: stmpe2401@44 { compatible = "st,stmpe2401"; @@ -183,4 +187,24 @@ wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; }; }; + + bl: backlight { + compatible = "pwm-backlight"; + pwms = <&stmpe0_pwm 0 500000>; + pwm-names = "backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 8 9 + 10 11 12 13 14 15 16 17 18 19 + 20 21 22 23 24 25 26 27 28 29 + 30 31 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 48 49 + 50 51 52 53 54 55 56 57 58 59 + 60 61 62 63 64 65 66 67 68 69 + 70 71 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 88 89 + 90 91 92 93 94 95 96 97 98 99 + 100 + >; + default-brightness-level = <100>; + }; }; -- cgit v1.2.3 From ee376dfac67d0fc3e3359c2b5c8ed5186e8a5616 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sat, 9 Jan 2016 23:09:21 +0100 Subject: dt-bindings: add vendor TPO TPO was a merger on June 5 2006 of Toppoly Optoelectronics and Philips Mobile Display Systems. They manufactured small and medium mobile displays. Acked-by: Rob Herring Signed-off-by: Linus Walleij --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 1992aa97d45a..65b7bbbc893f 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -270,6 +270,7 @@ toshiba Toshiba Corporation toumaz Toumaz tplink TP-LINK Technologies Co., Ltd. tpk TPK U.S.A. LLC +tpo TPO tronfy Tronfy tronsmart Tronsmart truly Truly Semiconductors Limited -- cgit v1.2.3 From 4a9b8e4df51df8f21c2dacf54bcefa258beb5e8b Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Jan 2016 22:35:43 +0100 Subject: dt-bindings: Add TPO TPG110 binding This adds device tree bindings for the TPO TPG110 panel found mounted in the Nomadik NHK8815. Acked-by: Rob Herring Signed-off-by: Linus Walleij --- .../bindings/display/panel/tpo,tpg110.txt | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt diff --git a/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt new file mode 100644 index 000000000000..f5e3c6f2095a --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/tpo,tpg110.txt @@ -0,0 +1,47 @@ +TPO TPG110 Panel +================ + +This binding builds on the DPI bindings, adding a few properties +as a superset of a DPI. See panel-dpi.txt for the required DPI +bindings. + +Required properties: +- compatible : "tpo,tpg110" +- grestb-gpios : panel reset GPIO +- scen-gpios : serial control enable GPIO +- scl-gpios : serial control clock line GPIO +- sda-gpios : serial control data line GPIO + +Required nodes: +- Video port for DPI input, see panel-dpi.txt +- Panel timing for DPI setup, see panel-dpi.txt + +Example +------- + +panel { + compatible = "tpo,tpg110", "panel-dpi"; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <33200000>; + hactive = <800>; + hback-porch = <216>; + hfront-porch = <40>; + hsync-len = <1>; + vactive = <480>; + vback-porch = <35>; + vfront-porch = <10>; + vsync-len = <1>; + }; +}; -- cgit v1.2.3 From 6f101946cb0acb7a36a773bb2aaf2c0f768f2ebc Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 10 Jan 2016 22:34:07 +0100 Subject: ARM: nomadik: select MFD_SYSCON Since the Power Management Unit is using syscon to access a set of necessary hardware muxing, let's select MFD_SYSCON for the Nomadik subarchitecture. Signed-off-by: Linus Walleij --- arch/arm/mach-nomadik/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig index b7e9801fdaa4..3ae45b8d7b0a 100644 --- a/arch/arm/mach-nomadik/Kconfig +++ b/arch/arm/mach-nomadik/Kconfig @@ -7,6 +7,7 @@ menuconfig ARCH_NOMADIK select CLKSRC_NOMADIK_MTU_SCHED_CLOCK select CPU_ARM926T select GPIOLIB + select MFD_SYSCON select MIGHT_HAVE_CACHE_L2X0 select PINCTRL select PINCTRL_NOMADIK -- cgit v1.2.3 From 6fb2de9d9f1b34fed21d7c88a008b8822f5dd4c7 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Sun, 10 Jan 2016 22:32:43 +0100 Subject: ARM: dts: add PMU to the NHK15 device tree The so-called Nomadik Power Mangament Unit is actually a set of some power management registers and some miscellaneous system control stuff like muxing of entire hardware units. Add this as a system controller. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index d2d532a9d783..80a3c9ccccd9 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -168,6 +168,12 @@ }; }; + /* Power Management Unit */ + pmu: pmu@101e9000 { + compatible = "stericsson,nomadik-pmu", "syscon"; + reg = <0x101e0000 0x1000>; + }; + src: src@101e0000 { compatible = "stericsson,nomadik-src"; reg = <0x101e0000 0x1000>; -- cgit v1.2.3 From 17470b7da11c137267c74ff0d2d4cca56f595c60 Mon Sep 17 00:00:00 2001 From: Linus Walleij Date: Wed, 27 Jan 2016 22:03:23 +0100 Subject: ARM: dts: add the CLCD LCD display to the NHK15 This adds the TPG110 TDO43MTEA2 24-bit RGB LCD panel and sets up the Nomadik device tree to activate the CLCD and connect it to this panel. Signed-off-by: Linus Walleij --- arch/arm/boot/dts/ste-nomadik-nhk15.dts | 44 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/ste-nomadik-stn8815.dtsi | 22 +++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts index 3ec5c653ad56..1ec46a794a4d 100644 --- a/arch/arm/boot/dts/ste-nomadik-nhk15.dts +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -176,6 +176,50 @@ }; amba { + clcd@10120000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&clcd_24bit_mux>; + port { + nomadik_clcd_pads: endpoint { + remote-endpoint = <&nomadik_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <16 8 0>; + }; + }; + + /* + * WVGA connector 21 + * WVGA (800x480): 4.3" TPG110 TDO43MTEA2 24-bit RGB + * with TPO touch screen. + */ + panel { + compatible = "tpo,tpg110", "panel-dpi"; + grestb-gpios = <&stmpe_gpio44 5 GPIO_ACTIVE_LOW>; + scen-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; + scl-gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; + sda-gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; + backlight = <&bl>; + + port { + nomadik_clcd_panel: endpoint { + remote-endpoint = <&nomadik_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <33200000>; + hactive = <800>; + hback-porch = <216>; + hfront-porch = <40>; + hsync-len = <1>; + vactive = <480>; + vback-porch = <35>; + vfront-porch = <10>; + vsync-len = <1>; + }; + }; + }; + /* Activate RX/TX and CTS/RTS on UART 0 */ uart0: uart@101fd000 { pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index 80a3c9ccccd9..adb1c0998b81 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -166,6 +166,18 @@ }; }; }; + clcd { + /* + * This should be activated to use the additional + * 8 lines for bits 16 thru 23 from the CLCD block. + */ + clcd_24bit_mux: clcd_mux { + clcd_24bit_mux { + function = "clcd"; + groups = "clcd_16_23_b_1"; + }; + }; + }; }; /* Power Management Unit */ @@ -732,6 +744,16 @@ #size-cells = <1>; ranges; + clcd@10120000 { + compatible = "arm,pl110", "arm,primecell"; + reg = <0x10120000 0x1000>; + interrupt-names = "combined"; + interrupts = <14>; + clocks = <&clcdclk>, <&hclkclcd>; + clock-names = "clcdclk", "apb_pclk"; + status = "disabled"; + }; + vica: intc@10140000 { compatible = "arm,versatile-vic"; interrupt-controller; -- cgit v1.2.3 From d09ea47ac8dbd391d8d1103ffe841c75f0c1d8e7 Mon Sep 17 00:00:00 2001 From: Lars Persson Date: Tue, 23 Aug 2016 16:00:50 +0200 Subject: ARM: dts: artpec: use clock binding header Use defines from the clock binding header as clock indexes. Signed-off-by: Lars Persson Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/artpec6.dtsi | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 3fac4c4d0007..db41b52ecccf 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -41,6 +41,7 @@ */ #include +#include #include "skeleton.dtsi" / { @@ -109,14 +110,14 @@ compatible = "arm,cortex-a9-global-timer"; reg = <0xfaf00200 0x20>; interrupts = ; - clocks = <&clkctrl 1>; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; }; timer@faf00600 { compatible = "arm,cortex-a9-twd-timer"; reg = <0xfaf00600 0x20>; interrupts = ; - clocks = <&clkctrl 1>; + clocks = <&clkctrl ARTPEC6_CLK_CPU_PERIPH>; status = "disabled"; }; @@ -157,7 +158,7 @@ ethernet: ethernet@f8010000 { clock-names = "phy_ref_clk", "apb_pclk"; clocks = <ð_phy_ref_clk>, - <&clkctrl 4>; + <&clkctrl ARTPEC6_CLK_ETH_ACLK>; compatible = "snps,dwc-qos-ethernet-4.10"; interrupt-parent = <&intc>; interrupts = ; @@ -175,8 +176,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8036000 0x1000>; interrupts = ; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -184,8 +185,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8037000 0x1000>; interrupts = ; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -193,8 +194,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8038000 0x1000>; interrupts = ; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; @@ -202,8 +203,8 @@ compatible = "arm,pl011", "arm,primecell"; reg = <0xf8039000 0x1000>; interrupts = ; - clocks = <&clkctrl 13>, - <&clkctrl 12>; + clocks = <&clkctrl ARTPEC6_CLK_UART_REFCLK>, + <&clkctrl ARTPEC6_CLK_UART_PCLK>; clock-names = "uart_clk", "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From 1b875160af6ca08bcb63d0201f38cca98e16601c Mon Sep 17 00:00:00 2001 From: Lars Persson Date: Tue, 23 Aug 2016 16:00:51 +0200 Subject: ARM: dts: artpec: use optimized pl310 settings Use the cache settings that were determined to give best performance on artpec-6 typical workloads. Signed-off-by: Lars Persson Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/artpec6.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index db41b52ecccf..4e40d5550c6a 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -137,6 +137,13 @@ arm,data-latency = <1 1 1>; arm,tag-latency = <1 1 1>; arm,filter-ranges = <0x0 0x80000000>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <0>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,prefetch-offset = <0>; + arm,prefetch-drop = <1>; }; pmu { -- cgit v1.2.3 From 92467a5fd55974bae4209da4543d621df605db5e Mon Sep 17 00:00:00 2001 From: Lars Persson Date: Tue, 23 Aug 2016 16:00:52 +0200 Subject: ARM: dts: artpec: set irq affinity on pmu interrupts The irq affinity is required for pmu interrupts. Signed-off-by: Lars Persson Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/artpec6.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi index 4e40d5550c6a..3489019cc0dc 100644 --- a/arch/arm/boot/dts/artpec6.dtsi +++ b/arch/arm/boot/dts/artpec6.dtsi @@ -150,6 +150,7 @@ compatible = "arm,cortex-a9-pmu"; interrupts = , ; + interrupt-affinity = <&cpu0>, <&cpu1>; interrupt-parent = <&intc>; }; -- cgit v1.2.3 From 9c0da3cc61f1233c2782e2d3d91e3d0707dd4ba5 Mon Sep 17 00:00:00 2001 From: Mark Rutland Date: Fri, 2 Sep 2016 17:34:50 +0100 Subject: ARM: dts: explicitly mark skeleton.dtsi as deprecated As noted in commit 3ebee5a2e141496b ("arm64: dts: kill skeleton.dtsi"), there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely. As there are a large number of existing users, fixing these up will take a while. This patch adds a note to arm's skeleton.dtsi noting that this is the case, to make this more obvious and hopefully minimize new uptake of skeleton.dtsi in the mean time. Signed-off-by: Mark Rutland Acked-by: Rob Herring Cc: Arnd Bergmann Cc: Olof Johansson Signed-off-by: Arnd Bergmann --- arch/arm/boot/dts/skeleton.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/skeleton.dtsi b/arch/arm/boot/dts/skeleton.dtsi index b41d241de2cd..28b81d60b407 100644 --- a/arch/arm/boot/dts/skeleton.dtsi +++ b/arch/arm/boot/dts/skeleton.dtsi @@ -1,4 +1,8 @@ /* + * This file is deprecated, and will be removed once existing users have been + * updated. New dts{,i} files should *not* include skeleton.dtsi, and should + * instead explicitly provide the below nodes only as required. + * * Skeleton device tree; the bare minimum needed to boot; just include and * add a compatible value. The bootloader will typically populate the memory * node. -- cgit v1.2.3 From 84ae49747fe2e2fe47f722f3f6656b2545a6d1ae Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 9 Sep 2016 14:00:37 -0700 Subject: ARM: dts: Configure panda SDIO WLAN wakeirq Otherwise we have delays on noticing interrupts from the WLAN card when idle. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap4-panda-common.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index d48e45bd4b3d..1673689e6705 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -446,6 +446,8 @@ pinctrl-names = "default"; pinctrl-0 = <&wl12xx_pins>; vmmc-supply = <&wl12xx_vmmc>; + interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH + &omap4_pmx_core 0x10e>; non-removable; bus-width = <4>; cap-power-off-card; -- cgit v1.2.3 From 08f9268b2a2e16ad89187a49ac06bfc7e1dc36a6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 11 Sep 2016 21:01:02 -0700 Subject: ARM: dts: ARM: dts: Fix omap5 SDIO dat1 interrupt Few changes to fix issues I've noticed while debugging omap5-uevm wl18xx issues: 1. Move wlcore irq pin muxing under wlcore. This irq could be different from gpio_wk14 on some board variants 2. Don't configure pull on wlcore irq pin. There is a 10k pull up resistor R105 on the device to VDDS_1v8_MAIN 3. The padconf register for wlsdio_data1 is wrong, it's really at 0x1a8 + 2 - 0x40 = 0x16a offset, not at 0x168 as that's for wlsdio_data0 4. Mark the omap5-uevm wlan as compatible with ti,wl1837 as that's what the TDK R078 part seems to be 5. The MMC interrupt for WLAN musb be wakeupgen, not gic Looks like omap5-uevm WLAN behaves better now, but I still seem to have issues with some access points. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 10 ++++++---- arch/arm/boot/dts/omap5-uevm.dts | 4 ++++ 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index d1f5ce3d3651..cb3247f19b9f 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -332,7 +332,7 @@ wlcore_irq_pin: pinmux_wlcore_irq_pin { pinctrl-single,pins = < - OMAP5_IOPAD(0x40, PIN_INPUT_PULLUP | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ + OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */ >; }; }; @@ -355,15 +355,17 @@ non-removable; cap-power-off-card; pinctrl-names = "default"; - pinctrl-0 = <&mmc3_pins &wlcore_irq_pin>; - interrupts-extended = <&gic GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH - &omap5_pmx_core 0x168>; + pinctrl-0 = <&mmc3_pins>; + interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH + &omap5_pmx_core 0x16a>; #address-cells = <1>; #size-cells = <0>; wlcore: wlcore@2 { compatible = "ti,wl1271"; reg = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&wlcore_irq_pin>; interrupt-parent = <&gpio1>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */ ref-clock-frequency = <26000000>; diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 5230ca00913a..17704479f618 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -61,3 +61,7 @@ OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */ >; }; + +&wlcore { + compatible = "ti,wl1837"; +}; -- cgit v1.2.3 From 952a5db0c0f8ddf9776c84e818769f5c6e97ec38 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 9 Sep 2016 14:04:28 -0700 Subject: ARM: dts: Configure omap5 OTG ID pin The ID pin GPIO comes from the PMIC. Let's configure it as a GPIO for the driver to use, and also make sure the PMIC GPIO pin muxing is correct. The PMIC pad1 and 2 values for omap5-uevm and igepv5 are 0x5a and 0x1b, we only need to clear bit 2 in pad1 register to make the ID pin GPIO work. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 9 +++++++++ arch/arm/boot/dts/omap5.dtsi | 2 +- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index cb3247f19b9f..c61eb2063be8 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -393,14 +393,23 @@ interrupt-controller; #interrupt-cells = <2>; ti,system-power-controller; + ti,mux-pad1 = <0xa1>; + ti,mux-pad2 = <0x1b>; pinctrl-names = "default"; pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; + palmas_gpio: gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + extcon_usb3: palmas_usb { compatible = "ti,palmas-usb-vid"; ti,enable-vbus-detection; ti,enable-id-detection; ti,wakeup; + id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>; }; clk32kgaudio: palmas_clk32k@1 { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 71a8f5492c8b..c2ef1285a3dd 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -863,7 +863,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges; - dwc3@4a030000 { + dwc3: dwc3@4a030000 { compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; interrupts = , -- cgit v1.2.3 From b118c6a6ffa146c1598a53748efca8d299e495dc Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 9 Sep 2016 14:07:29 -0700 Subject: ARM: dts: Add power button support for igepv5 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add power button support for igepv5. Cc: Agustí Fontquerni i Gorchs Cc: Enric Balletbo Serra Cc: Javier Martinez Canillas Cc: Pau Pajuel Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-igep0050.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 7aa2b0c813ab..f24b4498537a 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include #include "omap5-board-common.dtsi" / { @@ -17,6 +18,18 @@ device_type = "memory"; reg = <0x80000000 0x7f000000>; /* 2032 MB */ }; + + gpio_keys { + compatible = "gpio-keys"; + pinctrl-0 = <&power_button_pin>; + pinctrl-names = "default"; + + power-button { + label = "Power Button"; + linux,code = ; + gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + }; + }; }; &hdmi { @@ -58,6 +71,12 @@ OMAP5_IOPAD(0x0fa, PIN_INPUT | MUX_MODE0) /* i2c4_sda */ >; }; + + power_button_pin: pinctrl_power_button_pin { + pinctrl-single,pins = < + OMAP5_IOPAD(0x086, PIN_INPUT | MUX_MODE6) /* gpio4_118 */ + >; + }; }; &tpd12s015 { -- cgit v1.2.3 From e7ee0bc6ae1eb6b3db3c81956e7123ef9a28cd35 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Sun, 11 Sep 2016 13:50:57 -0700 Subject: ARM: dts: Fix LEDs for igepv5 The LEDs on igepv5 are on the GPIO expander unlike on omap5-uevm. Configuration copied from git.isee.biz git tree except fixed for red and blue mapping. Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-board-common.dtsi | 10 ---------- arch/arm/boot/dts/omap5-igep0050.dts | 19 +++++++++++++++++++ arch/arm/boot/dts/omap5-uevm.dts | 10 ++++++++++ 3 files changed, 29 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi index c61eb2063be8..6365635fea5c 100644 --- a/arch/arm/boot/dts/omap5-board-common.dtsi +++ b/arch/arm/boot/dts/omap5-board-common.dtsi @@ -77,16 +77,6 @@ reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */ }; - leds { - compatible = "gpio-leds"; - led1 { - label = "omap5:blue:usr1"; - gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - }; - tpd12s015: encoder { compatible = "ti,tpd12s015"; diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index f24b4498537a..eceab970eba4 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -30,6 +30,25 @@ gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; }; }; + + leds { + compatible = "gpio-leds"; + led@1 { + label = "board:green:usr0"; + gpios = <&tca6416 1 0>; + default-state = "off"; + }; + led@2 { + label = "board:red:usr1"; + gpios = <&tca6416 2 0>; + default-state = "off"; + }; + led@3 { + label = "board:blue:usr1"; + gpios = <&tca6416 3 0>; + default-state = "off"; + }; + }; }; &hdmi { diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 17704479f618..6966b77976ba 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -17,6 +17,16 @@ device_type = "memory"; reg = <0x80000000 0x7F000000>; /* 2032 MB */ }; + + leds { + compatible = "gpio-leds"; + led1 { + label = "omap5:blue:usr1"; + gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */ + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + }; }; &hdmi { -- cgit v1.2.3 From d20f997b4d1f3fc41703c95e4f4bb4ebca90da42 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Sep 2016 12:14:44 -0500 Subject: ARM: dts: am57xx-beagle-x15: Remove pinmux configurations for erratum i869 Pinmuxing for DRA7x/AM57x family of processors need to be done in IO isolation as part of initial bootloader executed from SRAM. This is done as part of iodelay configuration sequence and is required due to the limitations introduced by erratum ID: i869[1] (IO Glitches can occur when changing IO settings) and elaborated in the Technical Reference Manual[2] 18.4.6.1.7 Isolation Requirements. Only peripheral that is permitted for dynamic pin mux configuration is MMC and DCAN. MMC is permitted to change to accommodate the requirements for varied speeds (which require IO-delay support in kernel as well). DCAN is a result of i893[1] (DCAN initialization sequence). However, since we don't use DCAN on X15, with the exception of MMC, all other pin mux configurations are removed from the dts. [1] http://www.ti.com/lit/pdf/sprz429 [2] http://www.ti.com/lit/pdf/sprui30 Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15.dts | 222 +------------------------------- 1 file changed, 1 insertion(+), 221 deletions(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index 9067ca092dc5..ef21da558ea3 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -59,8 +59,6 @@ leds { compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins_default>; led0 { label = "beagle-x15:usr0"; @@ -116,9 +114,6 @@ tpd12s015: encoder { compatible = "ti,tpd12s015"; - pinctrl-names = "default"; - pinctrl-0 = <&tpd12s015_pins>; - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ @@ -173,43 +168,6 @@ }; &dra7_pmx_core { - leds_pins_default: leds_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37a8, PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ - DRA7XX_CORE_IOPAD(0x37ac, PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ - DRA7XX_CORE_IOPAD(0x37c0, PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ - DRA7XX_CORE_IOPAD(0x37c4, PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ - >; - }; - - i2c1_pins_default: i2c1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ - DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ - >; - }; - - hdmi_pins: pinmux_hdmi_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3808, PIN_INPUT | MUX_MODE1) /* i2c2_sda.hdmi1_ddc_scl */ - DRA7XX_CORE_IOPAD(0x380c, PIN_INPUT | MUX_MODE1) /* i2c2_scl.hdmi1_ddc_sda */ - >; - }; - - i2c3_pins_default: i2c3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x36a4, PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ - DRA7XX_CORE_IOPAD(0x36a8, PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ - >; - }; - - uart3_pins_default: uart3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */ - DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */ - >; - }; - mmc1_pins_default: mmc1_pins_default { pinctrl-single,pins = < DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ @@ -236,154 +194,9 @@ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ >; }; - - cpsw_pins_default: cpsw_pins_default { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */ - DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */ - DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */ - DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */ - DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */ - DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */ - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */ - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */ - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */ - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */ - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */ - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */ - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */ - DRA7XX_CORE_IOPAD(0x359c, PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */ - DRA7XX_CORE_IOPAD(0x35a0, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */ - DRA7XX_CORE_IOPAD(0x35a4, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */ - DRA7XX_CORE_IOPAD(0x35a8, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */ - DRA7XX_CORE_IOPAD(0x35ac, PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */ - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */ - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */ - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */ - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */ - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */ - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */ - >; - - }; - - cpsw_pins_sleep: cpsw_pins_sleep { - pinctrl-single,pins = < - /* Slave 1 */ - DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15) - - /* Slave 2 */ - DRA7XX_CORE_IOPAD(0x3598, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x359c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35a8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35ac, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b4, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35b8, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35bc, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c0, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x35c4, PIN_INPUT | MUX_MODE15) - >; - }; - - davinci_mdio_pins_default: davinci_mdio_pins_default { - pinctrl-single,pins = < - /* MDIO */ - DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */ - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */ - >; - }; - - davinci_mdio_pins_sleep: davinci_mdio_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15) - >; - }; - - tps659038_pins_default: tps659038_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ - >; - }; - - tmp102_pins_default: tmp102_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37c8, PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ - >; - }; - - mcp79410_pins_default: mcp79410_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3824, PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3680, PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ - >; - }; - - tpd12s015_pins: pinmux_tpd12s015_pins { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT | MUX_MODE14) /* gpio7_10 CT_CP_HPD */ - DRA7XX_CORE_IOPAD(0x37b8, PIN_INPUT_PULLDOWN | MUX_MODE14) /* gpio7_12 HPD */ - DRA7XX_CORE_IOPAD(0x3770, PIN_OUTPUT | MUX_MODE14) /* gpio6_28 LS_OE */ - >; - }; - - clkout2_pins_default: clkout2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3694, PIN_OUTPUT_PULLDOWN | MUX_MODE9) /* xref_clk0.clkout2 */ - >; - }; - - clkout2_pins_sleep: clkout2_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3694, PIN_INPUT | MUX_MODE15) /* xref_clk0.clkout2 */ - >; - }; - - mcasp3_pins_default: mcasp3_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_aclkx.mcasp3_aclkx */ - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_fsx.mcasp3_fsx */ - DRA7XX_CORE_IOPAD(0x372c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr0.mcasp3_axr0 */ - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp3_axr1.mcasp3_axr1 */ - >; - }; - - mcasp3_pins_sleep: mcasp3_pins_sleep { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x3724, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3728, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x372c, PIN_INPUT | MUX_MODE15) - DRA7XX_CORE_IOPAD(0x3730, PIN_INPUT | MUX_MODE15) - >; - }; }; - &i2c1 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_pins_default>; clock-frequency = <400000>; tps659038: tps659038@58 { @@ -392,9 +205,6 @@ interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&tps659038_pins_default>; - #interrupt-cells = <2>; interrupt-controller; @@ -556,8 +366,6 @@ tmp102: tmp102@48 { compatible = "ti,tmp102"; reg = <0x48>; - pinctrl-names = "default"; - pinctrl-0 = <&tmp102_pins_default>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; #thermal-sensor-cells = <1>; @@ -567,9 +375,6 @@ #sound-dai-cells = <0>; compatible = "ti,tlv320aic3104"; reg = <0x18>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&clkout2_pins_default>; - pinctrl-1 = <&clkout2_pins_sleep>; assigned-clocks = <&clkoutmux2_clk_mux>; assigned-clock-parents = <&sys_clk2_dclk_div>; @@ -590,8 +395,6 @@ &i2c3 { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_pins_default>; clock-frequency = <400000>; mcp_rtc: rtc@6f { @@ -601,9 +404,6 @@ <&dra7_pmx_core 0x424>; interrupt-names = "irq", "wakeup"; - pinctrl-names = "default"; - pinctrl-0 = <&mcp79410_pins_default>; - vcc-supply = <&vdd_3v3>; wakeup-source; }; @@ -623,16 +423,10 @@ status = "okay"; interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <&dra7_pmx_core 0x3f8>; - - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins_default>; }; &mac { status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&cpsw_pins_default>; - pinctrl-1 = <&cpsw_pins_sleep>; dual_emac; }; @@ -648,12 +442,6 @@ dual_emac_res_vlan = <2>; }; -&davinci_mdio { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&davinci_mdio_pins_default>; - pinctrl-1 = <&davinci_mdio_pins_sleep>; -}; - &mmc1 { status = "okay"; @@ -669,7 +457,7 @@ status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins_default>; + pinctrl-0 = <&mmc1_pins_default>; vmmc-supply = <&vdd_3v3>; bus-width = <8>; @@ -691,8 +479,6 @@ &usb1 { dr_mode = "host"; - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; }; &omap_dwc3_2 { @@ -768,9 +554,6 @@ status = "ok"; vdda-supply = <&ldo4_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_pins>; - port { hdmi_out: endpoint { remote-endpoint = <&tpd12s015_in>; @@ -784,9 +567,6 @@ &mcasp3 { #sound-dai-cells = <0>; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&mcasp3_pins_default>; - pinctrl-1 = <&mcasp3_pins_sleep>; assigned-clocks = <&mcasp3_ahclkx_mux>; assigned-clock-parents = <&sys_clkin2>; status = "okay"; -- cgit v1.2.3 From 0af28cc92690d8c231ddf003452282e885993c08 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Fri, 2 Sep 2016 12:14:45 -0500 Subject: ARM: dts: am57xx-beagle-x15: Add support for rev B1 Latest update to the BeagleBoard-X15 platform (revision B1)[1] updates for allowing UHS SD cards to function with the split of supply to SD card from a dedicated LDO. As a result of this, AM57xx BeagleBoard-X15 now uses gpio2_30 instead of gpio6_28 for HDMI because HDMI_LS_OE should now be switched from GPIO6_28(Y9) to GPIO2_30 (AG8) to avoid a 1.8V GPIO toggling a 3.3V SoC input when the SD card is in UHS 1.8V mode. NOTE: For UHS mode to function, we need full fledged IODelay support in kernel to be functional. IODelay support is yet to be added. Further, It does not make much sense to spin off a new board compatible flag since there is no real functional benefit for the same. Note: Even though production version is supposed to be B1, there is over ~200 boards of previous version (A2)[2] out there which continue to get supported with the existing dts file (to maintain compatibility with existing bootloaders for A2) and the production board is now supported as revb1. [1] https://github.com/beagleboard/beagleboard-x15/blob/master/BEAGLEBOARD_X15_REV_B1.pdf [2] http://marc.info/?l=linux-arm-kernel&m=147273929820708&w=2 Tested-by: Tomi Valkeinen Signed-off-by: Nishanth Menon Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 596 ++++++++++++++++++++++++ arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 24 + arch/arm/boot/dts/am57xx-beagle-x15.dts | 592 +---------------------- 4 files changed, 628 insertions(+), 585 deletions(-) create mode 100644 arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi create mode 100644 arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..b8d9840895c2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -570,6 +570,7 @@ dtb-$(CONFIG_SOC_OMAP5) += \ omap5-uevm.dtb dtb-$(CONFIG_SOC_DRA7XX) += \ am57xx-beagle-x15.dtb \ + am57xx-beagle-x15-revb1.dtb \ am57xx-cl-som-am57x.dtb \ am57xx-sbc-am57x.dtb \ am572x-idk.dtb \ diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi new file mode 100644 index 000000000000..ec85ff9004e8 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -0,0 +1,596 @@ +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include "am57xx-commercial-grade.dtsi" +#include +#include + +/ { + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + rtc2 = &rtc; + display0 = &hdmi0; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + aic_dvdd: fixedregulator-aic_dvdd { + compatible = "regulator-fixed"; + regulator-name = "aic_dvdd_fixed"; + vin-supply = <&vdd_3v3>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "disk-activity"; + default-state = "off"; + }; + }; + + gpio_fan: gpio_fan { + /* Based on 5v 500mA AFB02505HHB */ + compatible = "gpio-fan"; + gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0>, + <13000 1>; + #cooling-cells = <2>; + }; + + hdmi0: connector { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tpd12s015_out>; + }; + }; + }; + + tpd12s015: encoder { + compatible = "ti,tpd12s015"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tpd12s015_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + + port@1 { + reg = <1>; + + tpd12s015_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + }; + }; + }; + }; + + sound0: sound0 { + compatible = "simple-audio-card"; + simple-audio-card,name = "BeagleBoard-X15"; + simple-audio-card,widgets = + "Line", "Line Out", + "Line", "Line In"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "MIC2L", "Line In", + "MIC2R", "Line In"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&sound0_master>; + simple-audio-card,frame-master = <&sound0_master>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp3>; + }; + + sound0_master: simple-audio-card,codec { + sound-dai = <&tlv320aic3104>; + clocks = <&clkout2_clk>; + }; + }; +}; + +&dra7_pmx_core { + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; +}; +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD / VDDSHV8 */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHYA */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_1V8_PHYB */ + regulator-name = "ldo4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + + tps659038_gpio: tps659038_gpio { + compatible = "ti,palmas-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + extcon_usb2: tps659038_usb { + compatible = "ti,palmas-usb-vid"; + ti,enable-vbus-detection; + vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; + }; + + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + #thermal-sensor-cells = <1>; + }; + + tlv320aic3104: tlv320aic3104@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3104"; + reg = <0x18>; + assigned-clocks = <&clkoutmux2_clk_mux>; + assigned-clock-parents = <&sys_clk2_dclk_div>; + + status = "okay"; + adc-settle-ms = <40>; + + AVDD-supply = <&vdd_3v3>; + IOVDD-supply = <&vdd_3v3>; + DRVDD-supply = <&vdd_3v3>; + DVDD-supply = <&aic_dvdd>; + }; + + eeprom: eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, + <&dra7_pmx_core 0x424>; + interrupt-names = "irq", "wakeup"; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3f8>; +}; + +&mac { + status = "okay"; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <1>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + bus-width = <4>; + cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; +}; + +&omap_dwc3_2 { + extcon = <&extcon_usb2>; +}; + +&usb2 { + /* + * Stand alone usage is peripheral only. + * However, with some resistor modifications + * this port can be used via expansion connectors + * as "host" or "dual-role". If so, provide + * the necessary dr_mode override in the expansion + * board's DT. + */ + dr_mode = "peripheral"; +}; + +&cpu_trips { + cpu_alert1: cpu_alert1 { + temperature = <50000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; +}; + +&cpu_cooling_maps { + map1 { + trip = <&cpu_alert1>; + cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; +}; + +&thermal_zones { + board_thermal: board_thermal { + polling-delay-passive = <1250>; /* milliseconds */ + polling-delay = <1500>; /* milliseconds */ + + /* sensor ID */ + thermal-sensors = <&tmp102 0>; + + board_trips: trips { + board_alert0: board_alert { + temperature = <40000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "active"; + }; + + board_crit: board_crit { + temperature = <105000>; /* millicelsius */ + hysteresis = <0>; /* millicelsius */ + type = "critical"; + }; + }; + + board_cooling_maps: cooling-maps { + map0 { + trip = <&board_alert0>; + cooling-device = + <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +&dss { + status = "ok"; + + vdda_video-supply = <&ldoln_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo4_reg>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&tpd12s015_in>; + }; + }; +}; + +&pcie1 { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; +}; + +&mcasp3 { + #sound-dai-cells = <0>; + assigned-clocks = <&mcasp3_ahclkx_mux>; + assigned-clock-parents = <&sys_clkin2>; + status = "okay"; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializers */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 1 2 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; + +&mailbox5 { + status = "okay"; + mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { + status = "okay"; + }; + mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { + status = "okay"; + }; +}; + +&mailbox6 { + status = "okay"; + mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { + status = "okay"; + }; + mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts new file mode 100644 index 000000000000..ca85570629fd --- /dev/null +++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "am57xx-beagle-x15-common.dtsi" + +/ { + model = "TI AM5728 BeagleBoard-X15 rev B1"; +}; + +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ +}; + +&mmc1 { + vmmc-supply = <&vdd_3v3>; + vmmc-aux-supply = <&ldo1_reg>; +}; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts index ef21da558ea3..8c66f2efd283 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15.dts +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -1,602 +1,24 @@ /* - * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -/dts-v1/; -#include "dra74x.dtsi" -#include "am57xx-commercial-grade.dtsi" -#include -#include +#include "am57xx-beagle-x15-common.dtsi" / { + /* NOTE: This describes the "original" pre-production A2 revision */ model = "TI AM5728 BeagleBoard-X15"; - compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; - - aliases { - rtc0 = &mcp_rtc; - rtc1 = &tps659038_rtc; - rtc2 = &rtc; - display0 = &hdmi0; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x80000000>; - }; - - vdd_3v3: fixedregulator-vdd_3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3"; - vin-supply = <®en1>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - aic_dvdd: fixedregulator-aic_dvdd { - compatible = "regulator-fixed"; - regulator-name = "aic_dvdd_fixed"; - vin-supply = <&vdd_3v3>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vtt_fixed: fixedregulator-vtt { - /* TPS51200 */ - compatible = "regulator-fixed"; - regulator-name = "vtt_fixed"; - vin-supply = <&smps3_reg>; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - enable-active-high; - gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; - }; - - leds { - compatible = "gpio-leds"; - - led0 { - label = "beagle-x15:usr0"; - gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - default-state = "off"; - }; - - led1 { - label = "beagle-x15:usr1"; - gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "cpu0"; - default-state = "off"; - }; - - led2 { - label = "beagle-x15:usr2"; - gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "mmc0"; - default-state = "off"; - }; - - led3 { - label = "beagle-x15:usr3"; - gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "disk-activity"; - default-state = "off"; - }; - }; - - gpio_fan: gpio_fan { - /* Based on 5v 500mA AFB02505HHB */ - compatible = "gpio-fan"; - gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = <0 0>, - <13000 1>; - #cooling-cells = <2>; - }; - - hdmi0: connector { - compatible = "hdmi-connector"; - label = "hdmi"; - - type = "a"; - - port { - hdmi_connector_in: endpoint { - remote-endpoint = <&tpd12s015_out>; - }; - }; - }; - - tpd12s015: encoder { - compatible = "ti,tpd12s015"; - - gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ - <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ - <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tpd12s015_in: endpoint { - remote-endpoint = <&hdmi_out>; - }; - }; - - port@1 { - reg = <1>; - - tpd12s015_out: endpoint { - remote-endpoint = <&hdmi_connector_in>; - }; - }; - }; - }; - - sound0: sound0 { - compatible = "simple-audio-card"; - simple-audio-card,name = "BeagleBoard-X15"; - simple-audio-card,widgets = - "Line", "Line Out", - "Line", "Line In"; - simple-audio-card,routing = - "Line Out", "LLOUT", - "Line Out", "RLOUT", - "MIC2L", "Line In", - "MIC2R", "Line In"; - simple-audio-card,format = "dsp_b"; - simple-audio-card,bitclock-master = <&sound0_master>; - simple-audio-card,frame-master = <&sound0_master>; - simple-audio-card,bitclock-inversion; - - simple-audio-card,cpu { - sound-dai = <&mcasp3>; - }; - - sound0_master: simple-audio-card,codec { - sound-dai = <&tlv320aic3104>; - clocks = <&clkout2_clk>; - }; - }; -}; - -&dra7_pmx_core { - mmc1_pins_default: mmc1_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ - DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ - DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ - DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ - DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ - DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ - DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ - >; - }; - - mmc2_pins_default: mmc2_pins_default { - pinctrl-single,pins = < - DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ - DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ - DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ - DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ - DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ - DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ - DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ - DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ - DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ - DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ - >; - }; -}; -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - - tps659038: tps659038@58 { - compatible = "ti,tps659038"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - #interrupt-cells = <2>; - interrupt-controller; - - ti,system-power-controller; - - tps659038_pmic { - compatible = "ti,tps659038-pmic"; - - regulators { - smps12_reg: smps12 { - /* VDD_MPU */ - regulator-name = "smps12"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps3_reg: smps3 { - /* VDD_DDR */ - regulator-name = "smps3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - smps45_reg: smps45 { - /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ - regulator-name = "smps45"; - regulator-min-microvolt = < 850000>; - regulator-max-microvolt = <1250000>; - regulator-always-on; - regulator-boot-on; - }; - - smps6_reg: smps6 { - /* VDD_CORE */ - regulator-name = "smps6"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1150000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS7 unused */ - - smps8_reg: smps8 { - /* VDD_1V8 */ - regulator-name = "smps8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - /* SMPS9 unused */ - - ldo1_reg: ldo1 { - /* VDD_SD / VDDSHV8 */ - regulator-name = "ldo1"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ldo2 { - /* VDD_SHV5 */ - regulator-name = "ldo2"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo3_reg: ldo3 { - /* VDDA_1V8_PHYA */ - regulator-name = "ldo3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo4_reg: ldo4 { - /* VDDA_1V8_PHYB */ - regulator-name = "ldo4"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldo9_reg: ldo9 { - /* VDD_RTC */ - regulator-name = "ldo9"; - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - regulator-boot-on; - }; - - ldoln_reg: ldoln { - /* VDDA_1V8_PLL */ - regulator-name = "ldoln"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - ldousb_reg: ldousb { - /* VDDA_3V_USB: VDDA_USBHS33 */ - regulator-name = "ldousb"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - }; - - regen1: regen1 { - /* VDD_3V3_ON */ - regulator-name = "regen1"; - regulator-boot-on; - regulator-always-on; - }; - }; - }; - - tps659038_rtc: tps659038_rtc { - compatible = "ti,palmas-rtc"; - interrupt-parent = <&tps659038>; - interrupts = <8 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - }; - - tps659038_pwr_button: tps659038_pwr_button { - compatible = "ti,palmas-pwrbutton"; - interrupt-parent = <&tps659038>; - interrupts = <1 IRQ_TYPE_EDGE_FALLING>; - wakeup-source; - ti,palmas-long-press-seconds = <12>; - }; - - tps659038_gpio: tps659038_gpio { - compatible = "ti,palmas-gpio"; - gpio-controller; - #gpio-cells = <2>; - }; - - extcon_usb2: tps659038_usb { - compatible = "ti,palmas-usb-vid"; - ti,enable-vbus-detection; - vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; - }; - - }; - - tmp102: tmp102@48 { - compatible = "ti,tmp102"; - reg = <0x48>; - interrupt-parent = <&gpio7>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - #thermal-sensor-cells = <1>; - }; - - tlv320aic3104: tlv320aic3104@18 { - #sound-dai-cells = <0>; - compatible = "ti,tlv320aic3104"; - reg = <0x18>; - assigned-clocks = <&clkoutmux2_clk_mux>; - assigned-clock-parents = <&sys_clk2_dclk_div>; - - status = "okay"; - adc-settle-ms = <40>; - - AVDD-supply = <&vdd_3v3>; - IOVDD-supply = <&vdd_3v3>; - DRVDD-supply = <&vdd_3v3>; - DVDD-supply = <&aic_dvdd>; - }; - - eeprom: eeprom@50 { - compatible = "at,24c32"; - reg = <0x50>; - }; }; -&i2c3 { - status = "okay"; - clock-frequency = <400000>; - - mcp_rtc: rtc@6f { - compatible = "microchip,mcp7941x"; - reg = <0x6f>; - interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, - <&dra7_pmx_core 0x424>; - interrupt-names = "irq", "wakeup"; - - vcc-supply = <&vdd_3v3>; - wakeup-source; - }; -}; - -&gpio7 { - ti,no-reset-on-init; - ti,no-idle-on-init; -}; - -&cpu0 { - cpu0-supply = <&smps12_reg>; - voltage-tolerance = <1>; -}; - -&uart3 { - status = "okay"; - interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, - <&dra7_pmx_core 0x3f8>; -}; - -&mac { - status = "okay"; - dual_emac; -}; - -&cpsw_emac0 { - phy_id = <&davinci_mdio>, <1>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <1>; -}; - -&cpsw_emac1 { - phy_id = <&davinci_mdio>, <2>; - phy-mode = "rgmii"; - dual_emac_res_vlan = <2>; +&tpd12s015 { + gpios = <&gpio7 10 GPIO_ACTIVE_HIGH>, /* gpio7_10, CT CP HPD */ + <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */ + <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ }; &mmc1 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - vmmc-supply = <&ldo1_reg>; - bus-width = <4>; - cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */ -}; - -&mmc2 { - status = "okay"; - - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; - - vmmc-supply = <&vdd_3v3>; - bus-width = <8>; - ti,non-removable; - cap-mmc-dual-data-rate; -}; - -&sata { - status = "okay"; -}; - -&usb2_phy1 { - phy-supply = <&ldousb_reg>; -}; - -&usb2_phy2 { - phy-supply = <&ldousb_reg>; -}; - -&usb1 { - dr_mode = "host"; -}; - -&omap_dwc3_2 { - extcon = <&extcon_usb2>; -}; - -&usb2 { - /* - * Stand alone usage is peripheral only. - * However, with some resistor modifications - * this port can be used via expansion connectors - * as "host" or "dual-role". If so, provide - * the necessary dr_mode override in the expansion - * board's DT. - */ - dr_mode = "peripheral"; -}; - -&cpu_trips { - cpu_alert1: cpu_alert1 { - temperature = <50000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; -}; - -&cpu_cooling_maps { - map1 { - trip = <&cpu_alert1>; - cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; -}; - -&thermal_zones { - board_thermal: board_thermal { - polling-delay-passive = <1250>; /* milliseconds */ - polling-delay = <1500>; /* milliseconds */ - - /* sensor ID */ - thermal-sensors = <&tmp102 0>; - - board_trips: trips { - board_alert0: board_alert { - temperature = <40000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "active"; - }; - - board_crit: board_crit { - temperature = <105000>; /* millicelsius */ - hysteresis = <0>; /* millicelsius */ - type = "critical"; - }; - }; - - board_cooling_maps: cooling-maps { - map0 { - trip = <&board_alert0>; - cooling-device = - <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -&dss { - status = "ok"; - - vdda_video-supply = <&ldoln_reg>; -}; - -&hdmi { - status = "ok"; - vdda-supply = <&ldo4_reg>; - - port { - hdmi_out: endpoint { - remote-endpoint = <&tpd12s015_in>; - }; - }; -}; - -&pcie1 { - gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -&mcasp3 { - #sound-dai-cells = <0>; - assigned-clocks = <&mcasp3_ahclkx_mux>; - assigned-clock-parents = <&sys_clkin2>; - status = "okay"; - - op-mode = <0>; /* MCASP_IIS_MODE */ - tdm-slots = <2>; - /* 4 serializers */ - serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ - 1 2 0 0 - >; - tx-num-evt = <32>; - rx-num-evt = <32>; -}; - -&mailbox5 { - status = "okay"; - mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { - status = "okay"; - }; - mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { - status = "okay"; - }; -}; - -&mailbox6 { - status = "okay"; - mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { - status = "okay"; - }; - mbox_dsp2_ipc3x: mbox_dsp2_ipc3x { - status = "okay"; - }; }; -- cgit v1.2.3 From 98cc4544d65c8d879a39cfc38703e9f4d078a3e9 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 13 Sep 2016 16:10:56 -0700 Subject: ARM: dts: Add support for more than 2GB of memory for omap5 Some omap5 variants have more than 2GB of memory available as optional models. Let's update the dts files to use two address cells similar to what dra7 is using with commit dae320ec3173 ("ARM: dts: DRA7: change address-cells and size-cells"). Acked-by: Lokesh Vutla Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-cm-t54.dts | 2 +- arch/arm/boot/dts/omap5-igep0050.dts | 2 +- arch/arm/boot/dts/omap5-uevm.dts | 2 +- arch/arm/boot/dts/omap5.dtsi | 22 +++++++++++----------- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index c9390fa9c362..b153f604932a 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -13,7 +13,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2048 MB */ + reg = <0 0x80000000 0 0x7f000000>; /* 2048 MB */ }; aliases { diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index eceab970eba4..44e03b9be1f1 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -16,7 +16,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7f000000>; /* 2032 MB */ + reg = <0x0 0x80000000 0 0x7f000000>; /* 2032 MB */ }; gpio_keys { diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts index 6966b77976ba..53d31a87b44b 100644 --- a/arch/arm/boot/dts/omap5-uevm.dts +++ b/arch/arm/boot/dts/omap5-uevm.dts @@ -15,7 +15,7 @@ memory@80000000 { device_type = "memory"; - reg = <0x80000000 0x7F000000>; /* 2032 MB */ + reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */ }; leds { diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index c2ef1285a3dd..25262118ec3d 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -12,8 +12,8 @@ #include / { - #address-cells = <1>; - #size-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; compatible = "ti,omap5"; interrupt-parent = <&wakeupgen>; @@ -90,10 +90,10 @@ compatible = "arm,cortex-a15-gic"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48211000 0x1000>, - <0x48212000 0x1000>, - <0x48214000 0x2000>, - <0x48216000 0x2000>; + reg = <0 0x48211000 0 0x1000>, + <0 0x48212000 0 0x1000>, + <0 0x48214000 0 0x2000>, + <0 0x48216000 0 0x2000>; interrupt-parent = <&gic>; }; @@ -101,7 +101,7 @@ compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; interrupt-controller; #interrupt-cells = <3>; - reg = <0x48281000 0x1000>; + reg = <0 0x48281000 0 0x1000>; interrupt-parent = <&gic>; }; @@ -129,11 +129,11 @@ compatible = "ti,omap5-l3-noc", "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0 0 0 0xc0000000>; ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; - reg = <0x44000000 0x2000>, - <0x44800000 0x3000>, - <0x45000000 0x4000>; + reg = <0 0x44000000 0 0x2000>, + <0 0x44800000 0 0x3000>, + <0 0x45000000 0 0x4000>; interrupts = , ; -- cgit v1.2.3 From 399ce40b4729ad3dcbca62ccb8af4b3ae84073b0 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: STi: DT: STiH407: Add FDMA driver dt nodes. These nodes are required to get the fdma driver working on STiH407 based silicon. Signed-off-by: Peter Griffin Acked-by: Lee Jones --- arch/arm/boot/dts/stih407-family.dtsi | 52 +++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index c7a10bf0e02f..2b9322acfdfa 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -825,5 +825,57 @@ clock-frequency = <600000000>; st,syscfg = <&syscfg_core 0x224>; }; + + /* fdma audio */ + fdma0: dma-controller@8e20000 { + compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; + reg = <0x8e20000 0x8000>, + <0x8e30000 0x3000>, + <0x8e37000 0x1000>, + <0x8e38000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma app */ + fdma1: dma-controller@8e40000 { + compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; + reg = <0x8e40000 0x8000>, + <0x8e50000 0x3000>, + <0x8e57000 0x1000>, + <0x8e58000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + }; + + /* fdma free running */ + fdma2: dma-controller@8e60000 { + compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; + reg = <0x8e60000 0x8000>, + <0x8e70000 0x3000>, + <0x8e77000 0x1000>, + <0x8e78000 0x8000>; + reg-names = "slimcore", "dmem", "peripherals", "imem"; + interrupts = ; + dma-channels = <16>; + #dma-cells = <3>; + clocks = <&clk_s_c0_flexgen CLK_FDMA>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>, + <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, + <&clk_s_c0_flexgen CLK_EXT2F_A9>; + }; }; }; -- cgit v1.2.3 From 6548defe72eb14c250dbc927b320660854a95aaa Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: DT: STiH407: Add i2s_out pinctrl configuration This patch adds the pinctrl config for the i2s_out pins used by the uniperif player IP. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin Acked-by: Lee Jones --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index 2cc7e03f342c..d50f6b3187f3 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -1084,6 +1084,29 @@ }; }; + i2s_out { + pinctrl_i2s_8ch_out: i2s_8ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + data1 = <&pio34 0 ALT1 OUT>; + data2 = <&pio34 1 ALT1 OUT>; + data3 = <&pio34 2 ALT1 OUT>; + }; + }; + + pinctrl_i2s_2ch_out: i2s_2ch_out{ + st,pins { + mclk = <&pio33 5 ALT1 OUT>; + lrclk = <&pio33 7 ALT1 OUT>; + sclk = <&pio33 6 ALT1 OUT>; + data0 = <&pio33 4 ALT1 OUT>; + }; + }; + }; + serial3 { pinctrl_serial3: serial3-0 { st,pins { -- cgit v1.2.3 From d4fe226c7ff3af3c707e766e98af06ebe6626e5e Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: DT: STiH407: Add i2s_in pinctrl configuration This patch adds the pinctrl config for the i2s_in pins used by the uniperif reader IP. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin Acked-by: Lee Jones --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index d50f6b3187f3..d7ad21c5d2a6 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -1107,6 +1107,30 @@ }; }; + i2s_in { + pinctrl_i2s_8ch_in: i2s_8ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + data1 = <&pio33 0 ALT1 IN>; + data2 = <&pio33 1 ALT1 IN>; + data3 = <&pio33 2 ALT1 IN>; + data4 = <&pio33 3 ALT1 IN>; + }; + }; + + pinctrl_i2s_2ch_in: i2s_2ch_in{ + st,pins { + mclk = <&pio32 5 ALT1 IN>; + lrclk = <&pio32 7 ALT1 IN>; + sclk = <&pio32 6 ALT1 IN>; + data0 = <&pio32 4 ALT1 IN>; + }; + }; + }; + serial3 { pinctrl_serial3: serial3-0 { st,pins { -- cgit v1.2.3 From 857d477feb5d9a62ba8fb3a06bf2ad200bc7f4ad Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: DT: STiH407: Add spdif_out pinctrl config This patch adds the pinctrl config for the spidf out pins used by the sasg codec IP. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin Acked-by: Lee Jones --- arch/arm/boot/dts/stih407-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi index d7ad21c5d2a6..c325cc059ae4 100644 --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi @@ -1131,6 +1131,14 @@ }; }; + spdif_out { + pinctrl_spdif_out: spdif_out{ + st,pins { + spdif_out = <&pio34 7 ALT1 OUT>; + }; + }; + }; + serial3 { pinctrl_serial3: serial3-0 { st,pins { -- cgit v1.2.3 From 9cf807f6023683d770bf0153af9fe5265ae2bdfd Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: STi: DT: STiH407: Add sti-sasg-codec dt node This patch adds the dt node for the internal audio codec IP. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 2b9322acfdfa..c345da67f8d5 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -877,5 +877,12 @@ <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, <&clk_s_c0_flexgen CLK_EXT2F_A9>; }; + + sti_sasg_codec: sti-sasg-codec { + compatible = "st,stih407-sas-codec"; + #sound-dai-cells = <1>; + status = "disabled"; + st,syscfg = <&syscfg_core>; + }; }; }; -- cgit v1.2.3 From 271739b6d81b00c358a306d9fc06b7ee86d742ea Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: STi: DT: STiH407: Add uniperif player dt nodes This patch adds the DT nodes for the uniperif player IP blocks found on STiH407 family silicon. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 80 +++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index c345da67f8d5..ea47e1602e0a 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -884,5 +884,85 @@ status = "disabled"; st,syscfg = <&syscfg_core>; }; + + sti_uni_player0: sti-uni-player@8d80000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; + assigned-clock-rates = <50000000>; + reg = <0x8d80000 0x158>; + interrupts = ; + dmas = <&fdma0 2 0 1>; + dai-name = "Uni Player #0 (HDMI)"; + dma-names = "tx"; + st,uniperiph-id = <0>; + st,version = <5>; + st,mode = "HDMI"; + + status = "disabled"; + }; + + sti_uni_player1: sti-uni-player@8d81000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; + assigned-clock-rates = <50000000>; + reg = <0x8d81000 0x158>; + interrupts = ; + dmas = <&fdma0 3 0 1>; + dai-name = "Uni Player #1 (PIO)"; + dma-names = "tx"; + st,uniperiph-id = <1>; + st,version = <5>; + st,mode = "PCM"; + + status = "disabled"; + }; + + sti_uni_player2: sti-uni-player@8d82000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; + assigned-clock-rates = <50000000>; + reg = <0x8d82000 0x158>; + interrupts = ; + dmas = <&fdma0 4 0 1>; + dai-name = "Uni Player #1 (DAC)"; + dma-names = "tx"; + st,uniperiph-id = <2>; + st,version = <5>; + st,mode = "PCM"; + + status = "disabled"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + compatible = "st,sti-uni-player"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; + assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; + assigned-clock-rates = <50000000>; + reg = <0x8d85000 0x158>; + interrupts = ; + dmas = <&fdma0 7 0 1>; + dma-names = "tx"; + dai-name = "Uni Player #1 (PIO)"; + st,uniperiph-id = <3>; + st,version = <5>; + st,mode = "SPDIF"; + + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 67f1ff404bdd50e46910b352be830d797fa51ec1 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: STi: DT: STiH407: Add uniperif reader dt nodes This patch adds the DT node for the uniperif reader IP block found on STiH407 family silicon. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stih407-family.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index ea47e1602e0a..55cb99f3f954 100644 --- a/arch/arm/boot/dts/stih407-family.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -964,5 +964,33 @@ status = "disabled"; }; + + sti_uni_reader0: sti-uni-reader@8d83000 { + compatible = "st,sti-uni-reader"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d83000 0x158>; + interrupts = ; + dmas = <&fdma0 5 0 1>; + dma-names = "rx"; + dai-name = "Uni Reader #0 (PCM IN)"; + st,version = <3>; + + status = "disabled"; + }; + + sti_uni_reader1: sti-uni-reader@8d84000 { + compatible = "st,sti-uni-reader"; + #sound-dai-cells = <0>; + st,syscfg = <&syscfg_core>; + reg = <0x8d84000 0x158>; + interrupts = ; + dmas = <&fdma0 6 0 1>; + dma-names = "rx"; + dai-name = "Uni Reader #1 (HDMI RX)"; + st,version = <3>; + + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 443fd7c92f5a000796b02683157d17b2575450e1 Mon Sep 17 00:00:00 2001 From: Peter Griffin Date: Mon, 5 Sep 2016 15:16:00 +0200 Subject: ARM: DT: STi: stihxxx-b2120: Add DT nodes for STi audio card This patch enables the uniperif players 2 & 3 for b2120 boards and also adds the "simple-audio-card" device node to interconnect the SoC sound device and the codec. Signed-off-by: Arnaud Pouliquen Signed-off-by: Peter Griffin --- arch/arm/boot/dts/stihxxx-b2120.dtsi | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 80ec40d3d987..ed2b7a99ecff 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -134,5 +134,50 @@ dvb-card = ; }; }; + + sti_uni_player2: sti-uni-player@8d82000 { + status = "okay"; + }; + + sti_uni_player3: sti-uni-player@8d85000 { + status = "okay"; + }; + + sti_sasg_codec: sti-sasg-codec { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif_out>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "sti audio card"; + status = "okay"; + + simple-audio-card,dai-link@0 { + /* DAC */ + format = "i2s"; + mclk-fs = <256>; + cpu { + sound-dai = <&sti_uni_player2>; + }; + + codec { + sound-dai = <&sti_sasg_codec 1>; + }; + }; + simple-audio-card,dai-link@1 { + /* SPDIF */ + format = "left_j"; + mclk-fs = <128>; + cpu { + sound-dai = <&sti_uni_player3>; + }; + + codec { + sound-dai = <&sti_sasg_codec 0>; + }; + }; + }; }; }; -- cgit v1.2.3 From ab48eb533270e23aef28f572c6838c1c760ad8df Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 5 Sep 2016 22:00:10 +0300 Subject: dt-binding: mrvl-gpio: remove orion-gpio description The Orion GPIO controller binding description in mrvl-gpio.txt is obsolete, and duplicates the description in gpio-mvebu.txt. Signed-off-by: Baruch Siach Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/gpio/mrvl-gpio.txt | 23 ---------------------- 1 file changed, 23 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt index 98d198396956..c3d016532d8e 100644 --- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt +++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt @@ -44,26 +44,3 @@ Example for a PXA3xx platform: interrupt-controller; #interrupt-cells = <0x2>; }; - -* Marvell Orion GPIO Controller - -Required properties: -- compatible : Should be "marvell,orion-gpio" -- reg : Address and length of the register set for controller. -- gpio-controller : So we know this is a gpio controller. -- ngpio : How many gpios this controller has. -- interrupts : Up to 4 Interrupts for the controller. - -Optional properties: -- mask-offset : For SMP Orions, offset for Nth CPU - -Example: - - gpio0: gpio@10100 { - compatible = "marvell,orion-gpio"; - #gpio-cells = <2>; - gpio-controller; - reg = <0x10100 0x40>; - ngpio = <32>; - interrupts = <35>, <36>, <37>, <38>; - }; -- cgit v1.2.3 From 220ece397c45f7cbcf6ebed7df5aa52e2506ac26 Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Thu, 19 May 2016 22:34:03 +0100 Subject: ARM: dts: orion5x: Add required properties for orion-wdt to DT node orion-wdt refuses to start without these properties defined, so lift definitions out of kirkwood/dove.dtsi [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/orion5x.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi index e1b6d2a2ac49..fbccfbbab223 100644 --- a/arch/arm/boot/dts/orion5x.dtsi +++ b/arch/arm/boot/dts/orion5x.dtsi @@ -144,9 +144,10 @@ wdt: wdt@20300 { compatible = "marvell,orion-wdt"; - reg = <0x20300 0x28>; + reg = <0x20300 0x28>, <0x20108 0x4>; interrupt-parent = <&bridge_intc>; interrupts = <3>; + clocks = <&core_clk 0>; status = "okay"; }; -- cgit v1.2.3 From 96b5a5452859ede1e19b1118d2dcaea3e2366cae Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Thu, 19 May 2016 22:36:29 +0100 Subject: dt-bindings: arm: add DT binding for Marvell Orion5x SoC family Copy the format for kirkwood/dove to orion5x [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin Reviewed-by: Andrew Lunn Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell/marvell,orion5x.txt | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt new file mode 100644 index 000000000000..a88801141fca --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -0,0 +1,23 @@ +Marvell Orion SoC Family Device Tree Bindings +--------------------------------------------- + +Boards with a SoC of the Marvell Orion family, eg 88f5181 + +* Required root node properties: +compatible: must contain "marvell,orion5x" + +In addition, the above compatible shall be extended with the specific +SoC. Currently known SoC compatibles are: + +"marvell,orion5x-88f5182" + +And in addition, the compatible shall be extended with the specific +board. Currently known boards are: + +"buffalo,lsgl" +"buffalo,lswsgl" +"buffalo,lswtgl" +"lacie,ethernet-disk-mini-v2" +"lacie,d2-network" +"marvell,rd-88f5182-nas" +"maxtor,shared-storage-2" -- cgit v1.2.3 From 91762fab3082938d8b4aee986eeeca4f0a4fba5d Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Thu, 19 May 2016 22:43:36 +0100 Subject: ARM: dts: arm: orion5x: Add DT include for mv88f5181 Common definitions for the SoC for board definitions to use. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin Reviewed-by: Andrew Lunn Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell/marvell,orion5x.txt | 1 + arch/arm/boot/dts/orion5x-mv88f5181.dtsi | 49 ++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-mv88f5181.dtsi diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt index a88801141fca..ff3c120d1987 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -9,6 +9,7 @@ compatible: must contain "marvell,orion5x" In addition, the above compatible shall be extended with the specific SoC. Currently known SoC compatibles are: +"marvell,orion5x-88f5181" "marvell,orion5x-88f5182" And in addition, the compatible shall be extended with the specific diff --git a/arch/arm/boot/dts/orion5x-mv88f5181.dtsi b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi new file mode 100644 index 000000000000..f667012b26ca --- /dev/null +++ b/arch/arm/boot/dts/orion5x-mv88f5181.dtsi @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2016 Jamie Lentin + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include "orion5x.dtsi" + +/ { + compatible = "marvell,orion5x-88f5181", "marvell,orion5x"; + + soc { + compatible = "marvell,orion5x-88f5181-mbus", "simple-bus"; + + internal-regs { + pinctrl: pinctrl@10000 { + compatible = "marvell,88f5181-pinctrl"; + reg = <0x10000 0x8>, <0x10050 0x4>; + }; + + core_clk: core-clocks@10030 { + compatible = "marvell,mv88f5181-core-clock"; + reg = <0x10010 0x4>; + #clock-cells = <1>; + }; + + mbusc: mbus-controller@20000 { + compatible = "marvell,mbus-controller"; + reg = <0x20000 0x100>, <0x1500 0x20>; + }; + }; + }; +}; + +&pinctrl { + pmx_ge: pmx-ge { + marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19"; + marvell,function = "ge"; + }; +}; + +ð { + pinctrl-0 = <&pmx_ge>; + pinctrl-names = "default"; +}; -- cgit v1.2.3 From b6114633fb21c83af21ac26254f7951664f9697b Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Wed, 14 Sep 2016 16:47:26 +0200 Subject: ARM: dts: orion5x: Add description for Netgear WNR854T This is a router based on the mv88f5181 chipset. http://www.netgear.com/support/product/WNR854T.aspx http://wiki.openwrt.org/toh/netgear/wnr854t [gregory.clement@free-electrons.com: - extract dt part from "arm: orion5x: Add DT-based support for Netgear WNR854T" - squashed "arm: orion5x: Alias uart0 to serial0 for all orion5x" into this commit and move serial0 alias from dtsi to dts] Signed-off-by: Jamie Lentin Signed-off-by: Gregory CLEMENT --- .../bindings/arm/marvell/marvell,orion5x.txt | 1 + arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 200 +++++++++++++++++++++ 3 files changed, 202 insertions(+) create mode 100644 arch/arm/boot/dts/orion5x-netgear-wnr854t.dts diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt index ff3c120d1987..748a8f287462 100644 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt @@ -22,3 +22,4 @@ board. Currently known boards are: "lacie,d2-network" "marvell,rd-88f5182-nas" "maxtor,shared-storage-2" +"netgear,wnr854t" diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faacd52370d2..4588b3c54493 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -584,6 +584,7 @@ dtb-$(CONFIG_ARCH_ORION5X) += \ orion5x-linkstation-lswtgl.dtb \ orion5x-lswsgl.dtb \ orion5x-maxtor-shared-storage-2.dtb \ + orion5x-netgear-wnr854t.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += \ prima2-evb.dtb diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts new file mode 100644 index 000000000000..86a3cb1610ee --- /dev/null +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2016 Jamie Lentin + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include +#include +#include "orion5x-mv88f5181.dtsi" + +/ { + model = "Netgear WNR854-t"; + compatible = "netgear,wnr854t", "marvell,orion5x-88f5181", + "marvell,orion5x"; + aliases { + serial0 = &uart0; + }; + + memory { + reg = <0x00000000 0x2000000>; /* 32 MB */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + soc { + ranges = , + , + ; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-0 = <&pmx_reset_button>; + pinctrl-names = "default"; + + reset { + label = "Reset Button"; + linux,code = ; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pmx_power_led &pmx_power_led_blink &pmx_wan_led>; + pinctrl-names = "default"; + + led@0 { + label = "wnr854t:green:power"; + gpios = <&gpio0 0 GPIO_ACTIVE_LOW>; + }; + + led@1 { + label = "wnr854t:blink:power"; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; + }; + + led@2 { + label = "wnr854t:green:wan"; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&devbus_bootcs { + status = "okay"; + + devbus,keep-config; + + flash@0 { + compatible = "cfi-flash"; + reg = <0 0x800000>; + bank-width = <2>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "kernel"; + reg = <0x0 0x100000>; + }; + + partition@100000 { + label = "rootfs"; + reg = <0x100000 0x660000>; + }; + + partition@760000 { + label = "uboot_env"; + reg = <0x760000 0x20000>; + }; + + partition@780000 { + label = "uboot"; + reg = <0x780000 0x80000>; + read-only; + }; + }; + }; +}; + +&mdio { + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + dsa,member = <0 0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan3"; + }; + + port@1 { + reg = <1>; + label = "lan4"; + }; + + port@2 { + reg = <2>; + label = "wan"; + }; + + port@3 { + reg = <3>; + label = "cpu"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + }; + + port@7 { + reg = <7>; + label = "lan2"; + }; + }; + }; +}; + +ð { + status = "okay"; + + ethernet-port@0 { + /* Hardwired to DSA switch */ + speed = <1000>; + duplex = <1>; + }; +}; + +&pinctrl { + pinctrl-0 = <&pmx_pci_gpios>; + pinctrl-names = "default"; + + pmx_power_led: pmx-power-led { + marvell,pins = "mpp0"; + marvell,function = "gpio"; + }; + + pmx_reset_button: pmx-reset-button { + marvell,pins = "mpp1"; + marvell,function = "gpio"; + }; + + pmx_power_led_blink: pmx-power-led-blink { + marvell,pins = "mpp2"; + marvell,function = "gpio"; + }; + + pmx_wan_led: pmx-wan-led { + marvell,pins = "mpp3"; + marvell,function = "gpio"; + }; + + pmx_pci_gpios: pmx-pci-gpios { + marvell,pins = "mpp4"; + marvell,function = "gpio"; + }; +}; + +&uart0 { + /* Pin 1: Tx, Pin 7: Rx, Pin 8: Gnd */ + status = "okay"; +}; -- cgit v1.2.3 From d30363364811e956816cb586936269ecb9a30299 Mon Sep 17 00:00:00 2001 From: Jamie Lentin Date: Sat, 6 Aug 2016 11:10:13 +0100 Subject: ARM: dts: orion5x: Configure WNR854T ethernet PHY LEDs The default PHY configuration disables most of the LEDs. The following configures the ethernet activity LEDs as Netgear intended. [gregory.clement@free-electrons.com: fix commit title] Signed-off-by: Jamie Lentin Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm/boot/dts/orion5x-netgear-wnr854t.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts index 86a3cb1610ee..9f6ae4e1de06 100644 --- a/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/orion5x-netgear-wnr854t.dts @@ -124,31 +124,82 @@ port@0 { reg = <0>; label = "lan3"; + phy-handle = <&lan3phy>; }; port@1 { reg = <1>; label = "lan4"; + phy-handle = <&lan4phy>; }; port@2 { reg = <2>; label = "wan"; + phy-handle = <&wanphy>; }; port@3 { reg = <3>; label = "cpu"; + ethernet = <ðport>; }; port@5 { reg = <5>; label = "lan1"; + phy-handle = <&lan1phy>; }; port@7 { reg = <7>; label = "lan2"; + phy-handle = <&lan2phy>; + }; + }; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + lan3phy: ethernet-phy@0 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan4phy: ethernet-phy@1 { + /* Marvell 88E1121R (port 2) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + wanphy: ethernet-phy@2 { + /* Marvell 88E1121R (port 1) */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <2>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan1phy: ethernet-phy@5 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <5>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; + }; + + lan2phy: ethernet-phy@7 { + /* Marvell 88E1112 */ + compatible = "ethernet-phy-id0141.0cb0", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + marvell,reg-init = <3 16 0 0x1777 3 17 0 0x15>; }; }; }; -- cgit v1.2.3 From 3868b42f367d7a8d4246db03388fddc1d4db428f Mon Sep 17 00:00:00 2001 From: "H. Nikolaus Schaller" Date: Mon, 5 Sep 2016 11:16:38 +0200 Subject: ARM: dts: omap3-gta04: reduce panel backlight PWM frequency to 83Hz This helps to get 100% intensity closer to "always on". It compensates for an effect of dmtimer which at 100% still emits short "off" impulses and the startup-time of the DC/DC converter makes backlight intensity not reach full scale. The lower the PWM frequency is, the smaller is this effect. Signed-off-by: H. Nikolaus Schaller Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi index 5563e2533ebd..b3a8b1f24499 100644 --- a/arch/arm/boot/dts/omap3-gta04.dtsi +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -102,7 +102,7 @@ backlight { compatible = "pwm-backlight"; - pwms = <&pwm11 0 2000000 0>; + pwms = <&pwm11 0 12000000 0>; pwm-names = "backlight"; brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>; default-brightness-level = <9>; /* => 90 */ -- cgit v1.2.3 From e3659351da0976f47b2fa1c225ddaf411b9dbb51 Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 14 Sep 2016 16:26:53 -0700 Subject: Revert "ARM: dts: am335x-boneblack: Enable 1GHz OPP for cpu" This reverts commit c36e6ec904876de1935b1d74d2d711e6f5ceb572. The original commit updated the cpufreq operating points tables for am335x-boneblack but was merged before the driver making use of the node was merged, which breaks the existing cpufreq implementation on the system, so revert the patch until the ti-cpufreq driver is merged. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-boneblack.dts | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index ca721670bd91..55c0e954b146 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -33,17 +33,6 @@ status = "okay"; }; -&cpu0_opp_table { - /* - * All PG 2.0 silicon may not support 1GHz but some of the early - * BeagleBone Blacks have PG 2.0 silicon which is guaranteed - * to support 1GHz OPP so enable it for PG 2.0 on this board. - */ - oppnitro@1000000000 { - opp-supported-hw = <0x06 0x0100>; - }; -}; - &am33xx_pinmux { nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins { pinctrl-single,pins = < -- cgit v1.2.3 From 0f416d1317dd4ef9d758ddc3e13cde23aa909c2d Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 14 Sep 2016 16:26:53 -0700 Subject: Revert "ARM: dts: am33xx: Move to operating-points-v2 table and ti-cpufreq driver" This reverts commit 4317be1162108bcdf50dc53dfb48eac94dcff25c. The original commit updated the cpufreq operating points tables for am33xx but was merged before the driver making use of the node was merged, which breaks the existing cpufreq implementation on the system, so revert the patch until the ti-cpufreq driver is merged. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am33xx.dtsi | 88 +++++++------------------------------------ 1 file changed, 13 insertions(+), 75 deletions(-) diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 98748c61ed99..9e214bfd32d2 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -45,9 +45,19 @@ device_type = "cpu"; reg = <0>; - operating-points-v2 = <&cpu0_opp_table>; - ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>; - ti,syscon-rev = <&scm_conf 0x600>; + /* + * To consider voltage drop between PMIC and SoC, + * tolerance value is reduced to 2% from 4% and + * voltage value is increased as a precaution. + */ + operating-points = < + /* kHz uV */ + 720000 1285000 + 600000 1225000 + 500000 1125000 + 275000 1125000 + >; + voltage-tolerance = <2>; /* 2 percentage */ clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -56,78 +66,6 @@ }; }; - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - - /* - * The three following nodes are marked with opp-suspend - * because the can not be enabled simultaneously on a - * single SoC. - */ - opp50@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <950000 931000 969000>; - opp-supported-hw = <0x06 0x0010>; - opp-suspend; - }; - - opp100@275000000 { - opp-hz = /bits/ 64 <275000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0x00FF>; - opp-suspend; - }; - - opp100@300000000 { - opp-hz = /bits/ 64 <300000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0020>; - opp-suspend; - }; - - opp100@500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp100@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1100000 1078000 1122000>; - opp-supported-hw = <0x06 0x0040>; - }; - - opp120@600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - opp120@720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1200000 1176000 1224000>; - opp-supported-hw = <0x06 0x0080>; - }; - - oppturbo@720000000 { - opp-hz = /bits/ 64 <720000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x01 0xFFFF>; - }; - - oppturbo@800000000 { - opp-hz = /bits/ 64 <800000000>; - opp-microvolt = <1260000 1234800 1285200>; - opp-supported-hw = <0x06 0x0100>; - }; - - oppnitro@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1325000 1298500 1351500>; - opp-supported-hw = <0x04 0x0200>; - }; - }; - pmu { compatible = "arm,cortex-a8-pmu"; interrupts = <3>; -- cgit v1.2.3 From a8dc7cb3e310a7ca4d4e06fe020d1b24b7f7ee3c Mon Sep 17 00:00:00 2001 From: Dave Gerlach Date: Wed, 14 Sep 2016 16:26:53 -0700 Subject: Revert "ARM: dts: dra7: Move to operating-points-v2 table" This reverts commit f80bc97fd0a9711ef11bdb3e63c2c01115a82c47. The original commit updated the cpufreq operating points tables for dra7xx but was merged before the driver making use of the node was merged, which breaks the existing cpufreq implementation on the system, so revert the patch until the ti-cpufreq driver is merged. Signed-off-by: Dave Gerlach Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/dra7.dtsi | 26 +++++--------------------- arch/arm/boot/dts/dra74x.dtsi | 1 - 2 files changed, 5 insertions(+), 22 deletions(-) diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d9bfb94a2992..a0fbbf18d50c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -82,9 +82,11 @@ compatible = "arm,cortex-a15"; reg = <0>; - operating-points-v2 = <&cpu0_opp_table>; - ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>; - ti,syscon-rev = <&scm_wkup 0x204>; + operating-points = < + /* kHz uV */ + 1000000 1060000 + 1176000 1160000 + >; clocks = <&dpll_mpu_ck>; clock-names = "cpu"; @@ -98,24 +100,6 @@ }; }; - cpu0_opp_table: opp_table0 { - compatible = "operating-points-v2"; - opp-shared; - - opp_nom@1000000000 { - opp-hz = /bits/ 64 <1000000000>; - opp-microvolt = <1060000 850000 1150000>; - opp-supported-hw = <0xFF 0x01>; - opp-suspend; - }; - - opp_od@1176000000 { - opp-hz = /bits/ 64 <1176000000>; - opp-microvolt = <1160000 885000 1160000>; - opp-supported-hw = <0xFF 0x02>; - }; - }; - /* * The soc node represents the soc top level view. It is used for IPs * that are not memory mapped in the MPU view or for the MPU itself. diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index 8987b3e180a1..0a78347e6615 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -17,7 +17,6 @@ device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; - operating-points-v2 = <&cpu0_opp_table>; }; }; -- cgit v1.2.3 From 9304af1b9ffa95dcb37d642852f8c67b98ea349a Mon Sep 17 00:00:00 2001 From: Karl Beldan Date: Thu, 8 Sep 2016 11:33:24 -0700 Subject: ARM: dts: da850-lcdk: Add NAND to DT This adds DT support for the NAND connected to the SoC AEMIF. Passed torture hashing a 40MB file on top of UBIFS using subpages. Signed-off-by: Karl Beldan [khilman: add back default partitions from an earlier patch] Signed-off-by: Kevin Hilman Signed-off-by: Sekhar Nori --- arch/arm/boot/dts/da850-lcdk.dts | 83 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts index 7563260e95d1..7b8ab21fed6c 100644 --- a/arch/arm/boot/dts/da850-lcdk.dts +++ b/arch/arm/boot/dts/da850-lcdk.dts @@ -63,6 +63,27 @@ 0x04 0x00000110 0x00000ff0 >; }; + + nand_pins: nand_pins { + pinctrl-single,bits = < + /* EMA_WAIT[0], EMA_OE, EMA_WE, EMA_CS[3] */ + 0x1c 0x10110010 0xf0ff00f0 + /* + * EMA_D[0], EMA_D[1], EMA_D[2], + * EMA_D[3], EMA_D[4], EMA_D[5], + * EMA_D[6], EMA_D[7] + */ + 0x24 0x11111111 0xffffffff + /* + * EMA_D[8], EMA_D[9], EMA_D[10], + * EMA_D[11], EMA_D[12], EMA_D[13], + * EMA_D[14], EMA_D[15] + */ + 0x20 0x11111111 0xffffffff + /* EMA_A[1], EMA_A[2] */ + 0x30 0x01100000 0x0ff00000 + >; + }; }; &serial2 { @@ -136,3 +157,65 @@ tx-num-evt = <32>; rx-num-evt = <32>; }; + +&aemif { + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>; + status = "okay"; + cs3 { + #address-cells = <2>; + #size-cells = <1>; + clock-ranges; + ranges; + + ti,cs-chipselect = <3>; + + nand@2000000,0 { + compatible = "ti,davinci-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0x02000000 0x02000000 + 1 0x00000000 0x00008000>; + + ti,davinci-chipselect = <1>; + ti,davinci-mask-ale = <0>; + ti,davinci-mask-cle = <0>; + ti,davinci-mask-chipsel = <0>; + + ti,davinci-nand-buswidth = <16>; + ti,davinci-ecc-mode = "hw"; + ti,davinci-ecc-bits = <4>; + ti,davinci-nand-use-bbt; + + /* + * The OMAP-L132/L138 Bootloader doc SPRAB41E reads: + * "To boot from NAND Flash, the AIS should be written + * to NAND block 1 (NAND block 0 is not used by default)". + * The same doc mentions that for ROM "Silicon Revision 2.1", + * "Updated NAND boot mode to offer boot from block 0 or block 1". + * However the limitaion is left here by default for compatibility + * with older silicon and because it needs new boot pin settings + * not possible in stock LCDK. + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot env"; + reg = <0 0x020000>; + }; + partition@0x020000 { + /* The LCDK defaults to booting from this partition */ + label = "u-boot"; + reg = <0x020000 0x080000>; + }; + partition@0x0a0000 { + label = "free space"; + reg = <0x0a0000 0>; + }; + }; + }; + }; +}; -- cgit v1.2.3 From 0574cb14398c312f4eaea8d518c63ce62f20ecbc Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Thu, 15 Sep 2016 14:10:59 -0500 Subject: ARM: dts: am57xx-beagle-x15-common: Fix wrong pinctrl selection for mmc2 Commit d20f997b4d1f ("ARM: dts: am57xx-beagle-x15: Remove pinmux configurations for erratum i869") fat fingered a change in which basically replaced mmc2_pinctrl_default with mmc1_pinctrl_default. And kernel dutifully reports conflict of usage. [...] pinctrl-single 4a003400.pinmux: pin 4a00376c.0 already requested by 4809c000.mmc; cannot claim for 480b4000.mmc pinctrl-single 4a003400.pinmux: pin-219 (480b4000.mmc) status -22 pinctrl-single 4a003400.pinmux: could not request pin 219 (4a00376c.0) from group mmc1_pins_default on device pinctrl-single omap_hsmmc 480b4000.mmc: Error applying setting, reverse things back omap_hsmmc 480b4000.mmc: could not initialize pin control state [...] But, thanks to the fact that we were in fact setting all the muxes in U-Boot, all the MMC devices were still properly detected. Fix the typo. Fixes: d20f997b4d1f ("ARM: dts: am57xx-beagle-x15: Remove pinmux configurations for erratum i869") Reported-by: Tony Lindgren Signed-off-by: Nishanth Menon [tony@atomide.com: removed timestamps and wrapped description] Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi index ec85ff9004e8..6df7829a2c15 100644 --- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi +++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi @@ -451,7 +451,7 @@ status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins_default>; + pinctrl-0 = <&mmc2_pins_default>; vmmc-supply = <&vdd_3v3>; bus-width = <8>; -- cgit v1.2.3 From 80555b6f7f8bdc370585c024601bec65ff260852 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 8 Sep 2016 11:26:00 -0400 Subject: ARM: dts: s5p: Remove skeleton.dtsi inclusion for S5PV210 The skeleton.dtsi file was removed in ARM64 for different reasons as explained in commit ("3ebee5a2e141 arm64: dts: kill skeleton.dtsi"). These also applies to ARM and it will also allow to get rid of the following DTC warnings in the future: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/s5pv210.dtsi b/arch/arm/boot/dts/s5pv210.dtsi index ffc36bd24d2f..a853918be43f 100644 --- a/arch/arm/boot/dts/s5pv210.dtsi +++ b/arch/arm/boot/dts/s5pv210.dtsi @@ -19,11 +19,13 @@ * published by the Free Software Foundation. */ -#include "skeleton.dtsi" #include #include / { + #address-cells = <1>; + #size-cells = <1>; + aliases { csis0 = &csis0; fimc0 = &fimc0; -- cgit v1.2.3 From 5271d002709e8ca27232ab031f35e0df1d0fe4ed Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 8 Sep 2016 11:26:01 -0400 Subject: ARM: dts: s5p: Add missing unit name to memory nodes for S5PV210 boards This patch fixes the following DTC warnings: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Javier Martinez Canillas Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/s5pv210-aquila.dts | 2 +- arch/arm/boot/dts/s5pv210-goni.dts | 2 +- arch/arm/boot/dts/s5pv210-smdkc110.dts | 2 +- arch/arm/boot/dts/s5pv210-smdkv210.dts | 2 +- arch/arm/boot/dts/s5pv210-torbreck.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index da24ab570b0e..d763c5b4c65d 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC2,115200n8 root=/dev/mmcblk1p5 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@30000000 { device_type = "memory"; reg = <0x30000000 0x05000000 0x40000000 0x18000000>; diff --git a/arch/arm/boot/dts/s5pv210-goni.dts b/arch/arm/boot/dts/s5pv210-goni.dts index 0a33d402138e..c56f51ee7897 100644 --- a/arch/arm/boot/dts/s5pv210-goni.dts +++ b/arch/arm/boot/dts/s5pv210-goni.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p5 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@30000000 { device_type = "memory"; reg = <0x30000000 0x05000000 0x40000000 0x10000000 diff --git a/arch/arm/boot/dts/s5pv210-smdkc110.dts b/arch/arm/boot/dts/s5pv210-smdkc110.dts index 1eedab7ffe94..5d14da911aa5 100644 --- a/arch/arm/boot/dts/s5pv210-smdkc110.dts +++ b/arch/arm/boot/dts/s5pv210-smdkc110.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/s5pv210-smdkv210.dts b/arch/arm/boot/dts/s5pv210-smdkv210.dts index 9eb6aff3e38f..75398318ed57 100644 --- a/arch/arm/boot/dts/s5pv210-smdkv210.dts +++ b/arch/arm/boot/dts/s5pv210-smdkv210.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/s5pv210-torbreck.dts b/arch/arm/boot/dts/s5pv210-torbreck.dts index 622599fd2cfa..7cb50bcee888 100644 --- a/arch/arm/boot/dts/s5pv210-torbreck.dts +++ b/arch/arm/boot/dts/s5pv210-torbreck.dts @@ -29,7 +29,7 @@ bootargs = "console=ttySAC0,115200n8 root=/dev/mmcblk0p1 rw rootwait ignore_loglevel earlyprintk"; }; - memory { + memory@20000000 { device_type = "memory"; reg = <0x20000000 0x20000000>; }; -- cgit v1.2.3 From 665c8ec1222a6ede0615e9bcca914d1834da12de Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:26:00 +0200 Subject: ARM: dts: STiH4xx: Simplify clock binding of STiH4xx platforms This patch simplifies the clock binding because we had too much detail. Signed-off-by: Gabriel Fernandez --- arch/arm/boot/dts/stih407-clock.dtsi | 18 +++++++++--------- arch/arm/boot/dts/stih410-clock.dtsi | 16 ++++++++-------- arch/arm/boot/dts/stih418-clock.dtsi | 16 ++++++++-------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index ad45f5e8fac7..38a56d7edab3 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -42,7 +42,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -55,7 +55,7 @@ */ clk_m_a9: clk-m-a9@92b0000 { #clock-cells = <0>; - compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + compatible = "st,stih407-clkgen-a9-mux"; reg = <0x92b0000 0x10000>; clocks = <&clockgen_a9_pll 0>, @@ -96,7 +96,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -117,7 +117,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -134,7 +134,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -143,7 +143,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -199,7 +199,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -233,7 +233,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -287,7 +287,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index fd5049682181..e8f4d4421e62 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + compatible = "st,stih407-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -122,7 +122,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -140,7 +140,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -150,7 +150,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -218,7 +218,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -254,7 +254,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -308,7 +308,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index ae6d9978ea19..0fd0fa54132c 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -44,7 +44,7 @@ clockgen_a9_pll: clockgen-a9-pll { #clock-cells = <1>; - compatible = "st,stih418-plls-c28-a9", "st,clkgen-plls-c32"; + compatible = "st,stih418-clkgen-plla9"; clocks = <&clk_sysin>; @@ -98,7 +98,7 @@ clk_s_a0_pll: clk-s-a0-pll { #clock-cells = <1>; - compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -120,7 +120,7 @@ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-C", "st,quadfs"; + compatible = "st,quadfs-pll"; reg = <0x9103000 0x1000>; clocks = <&clk_sysin>; @@ -137,7 +137,7 @@ clk_s_c0_pll0: clk-s-c0-pll0 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_0", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll0"; clocks = <&clk_sysin>; @@ -146,7 +146,7 @@ clk_s_c0_pll1: clk-s-c0-pll1 { #clock-cells = <1>; - compatible = "st,plls-c32-cx_1", "st,clkgen-plls-c32"; + compatible = "st,clkgen-pll1"; clocks = <&clk_sysin>; @@ -212,7 +212,7 @@ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9104000 0x1000>; clocks = <&clk_sysin>; @@ -248,7 +248,7 @@ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9106000 0x1000>; clocks = <&clk_sysin>; @@ -309,7 +309,7 @@ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { #clock-cells = <1>; - compatible = "st,stih407-quadfs660-D", "st,quadfs"; + compatible = "st,quadfs"; reg = <0x9107000 0x1000>; clocks = <&clk_sysin>; -- cgit v1.2.3 From ee7ff1b4afb0c2298e37b5169ec74e21cd077c85 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:26:00 +0200 Subject: ARM: dts: STiH407: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH407 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 38a56d7edab3..c4a8f1cb3195 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -216,7 +216,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 66ac420ab324faba09995a11c7faff7009d8d681 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH410 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index e8f4d4421e62..aec2aa736c8c 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -235,7 +235,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 97e7abdb8910df3ecebcbd0805f69535df71da82 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH418: Enable clock propagation for audio clocks This patch is used in the clock driver to apply a clock propagation flag on the audio clocks of STiH418 Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index 0fd0fa54132c..a1835833ca64 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -229,7 +229,7 @@ clk_s_d0_flexgen: clk-s-d0-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-audio", "st,flexgen"; clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_quadfs 1>, -- cgit v1.2.3 From 295971d01f4d5a248d33f95bf20ed423aed19199 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH407: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH407 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index c4a8f1cb3195..13029c03d7c6 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -256,7 +256,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From 9bc4ec59ab48ec2acd40c14afe227e074a485849 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH410 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi index aec2aa736c8c..8598effd6c01 100644 --- a/arch/arm/boot/dts/stih410-clock.dtsi +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -277,7 +277,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From 3b8b9f7fd25d28b323f58ac67cf577d7bf0cc6bb Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH418: Enable synchronous clock mode for video clocks This patch enables the synchronous clock mode for video clocks on STiH418 board. Signed-off-by: Olivier Bideau Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih418-clock.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stih418-clock.dtsi b/arch/arm/boot/dts/stih418-clock.dtsi index a1835833ca64..ee6614b79f7d 100644 --- a/arch/arm/boot/dts/stih418-clock.dtsi +++ b/arch/arm/boot/dts/stih418-clock.dtsi @@ -271,7 +271,7 @@ clk_s_d2_flexgen: clk-s-d2-flexgen { #clock-cells = <1>; - compatible = "st,flexgen"; + compatible = "st,flexgen-video", "st,flexgen"; clocks = <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 1>, -- cgit v1.2.3 From a0bfc7d068f685565f15f5f1e113eb293b68980b Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STi: STiH407: clock configuration to address 720p and 1080p It is necessary to properly configure these clocks in order to address 720p and 1080p HDMI resolution. Signed-off-by: Vincent Abriou Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih407.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index d60f0d8add26..291ffacbd2e0 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -16,7 +16,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -26,14 +29,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; -- cgit v1.2.3 From 3a74152ce62e7ec1b8a5604b10e40d2a66d8f43b Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Mon, 29 Aug 2016 14:27:00 +0200 Subject: ARM: dts: STiH410: clock configuration to address 720p and 1080p It is necessary to properly configure these clocks in order to address 720p and 1080p HDMI resolution. Signed-off-by: Vincent Abriou Signed-off-by: Gabriel Fernandez Acked-by: Peter Griffin --- arch/arm/boot/dts/stih410.dtsi | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index 6850f5861dc3..2d231300bf27 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -103,7 +103,10 @@ #size-cells = <1>; assigned-clocks = <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_flexgen CLK_COMPO_DVP>, + <&clk_s_c0_flexgen CLK_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, <&clk_s_d2_flexgen CLK_PIX_GDP1>, @@ -113,14 +116,21 @@ assigned-clock-parents = <0>, <0>, + <0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_pll1 0>, <&clk_s_d2_quadfs 0>, - <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>, <&clk_s_d2_quadfs 0>; - assigned-clock-rates = <297000000>, <297000000>; + assigned-clock-rates = <297000000>, + <108000000>, + <0>, + <400000000>, + <400000000>; ranges; -- cgit v1.2.3 From 5db7e3bb87df9fc2a6d6cbc3384ff073070c8d1b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:04 +0200 Subject: pinctrl: dt-bindings: samsung: Add header with values used for configuration Hard-coded pinctrl configuration values are scattered through DTS files. The numbers are difficult to decode by human, especially without the datasheet. Additionally the drive strength differs between S3C64xx, S5PV210 and Exynos SoC families increasing the confusion. The header will help making this more readable and maintainable. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- MAINTAINERS | 2 ++ include/dt-bindings/pinctrl/samsung.h | 57 +++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 include/dt-bindings/pinctrl/samsung.h diff --git a/MAINTAINERS b/MAINTAINERS index 20bb1d00098c..f5755866b960 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9236,6 +9236,8 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers) S: Maintained F: drivers/pinctrl/samsung/ +F: include/dt-bindings/pinctrl/samsung.h +F: Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt PIN CONTROLLER - SINGLE M: Tony Lindgren diff --git a/include/dt-bindings/pinctrl/samsung.h b/include/dt-bindings/pinctrl/samsung.h new file mode 100644 index 000000000000..6276eb785e2b --- /dev/null +++ b/include/dt-bindings/pinctrl/samsung.h @@ -0,0 +1,57 @@ +/* + * Samsung's Exynos pinctrl bindings + * + * Copyright (c) 2016 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * Author: Krzysztof Kozlowski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +#ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ +#define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ + +#define EXYNOS_PIN_PULL_NONE 0 +#define EXYNOS_PIN_PULL_DOWN 1 +#define EXYNOS_PIN_PULL_UP 3 + +#define S3C64XX_PIN_PULL_NONE 0 +#define S3C64XX_PIN_PULL_DOWN 1 +#define S3C64XX_PIN_PULL_UP 2 + +/* Pin function in power down mode */ +#define EXYNOS_PIN_PDN_OUT0 0 +#define EXYNOS_PIN_PDN_OUT1 1 +#define EXYNOS_PIN_PDN_INPUT 2 +#define EXYNOS_PIN_PDN_PREV 3 + +/* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ +#define EXYNOS4_PIN_DRV_LV1 0 +#define EXYNOS4_PIN_DRV_LV2 2 +#define EXYNOS4_PIN_DRV_LV3 1 +#define EXYNOS4_PIN_DRV_LV4 3 + +/* Drive strengths for Exynos5260 */ +#define EXYNOS5260_PIN_DRV_LV1 0 +#define EXYNOS5260_PIN_DRV_LV2 1 +#define EXYNOS5260_PIN_DRV_LV4 2 +#define EXYNOS5260_PIN_DRV_LV6 3 + +/* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ +#define EXYNOS5420_PIN_DRV_LV1 0 +#define EXYNOS5420_PIN_DRV_LV2 1 +#define EXYNOS5420_PIN_DRV_LV3 2 +#define EXYNOS5420_PIN_DRV_LV4 3 + +#define EXYNOS_PIN_FUNC_INPUT 0 +#define EXYNOS_PIN_FUNC_OUTPUT 1 +#define EXYNOS_PIN_FUNC_2 2 +#define EXYNOS_PIN_FUNC_3 3 +#define EXYNOS_PIN_FUNC_4 4 +#define EXYNOS_PIN_FUNC_5 5 +#define EXYNOS_PIN_FUNC_6 6 +#define EXYNOS_PIN_FUNC_F 0xf + +#endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ -- cgit v1.2.3 From c0fee590160637e1306dd4bc1018e89ff99ef00d Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:05 +0200 Subject: pinctrl: dt-bindings: samsung: Update documentation with new macros Update examples in Samsung pinctrl dt-bindings with new macros coming from header file. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij Acked-by: Rob Herring --- .../bindings/pinctrl/samsung-pinctrl.txt | 44 +++++++++++----------- 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt index 6db16b90873a..d49e22d2a8b5 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/samsung-pinctrl.txt @@ -229,6 +229,8 @@ Example: A pin-controller node with pin banks: Example 1: A pin-controller node with pin groups. + #include + pinctrl_0: pinctrl@11400000 { compatible = "samsung,exynos4210-pinctrl"; reg = <0x11400000 0x1000>; @@ -238,53 +240,53 @@ Example 1: A pin-controller node with pin groups. uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus8: sd4-bus-width8 { part-1 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; part-2 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <4>; - samsung,pin-pud = <4>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; }; -- cgit v1.2.3 From 90c6e35383dd02ef68a71f8373bdc9fbd0684a26 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:06 +0200 Subject: ARM: dts: exynos: Use common macros for pinctrl configuration Replace duplicated macros in each DTSI file with a common macro coming from header. Include the header in each pinctrl DTSI so further changes could use it. Although PIN_FUNC_SPC_2 does not bring much information about the function itself, it still is more descriptive then hard-coded number <2>. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 76 +++++++++++------------- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 21 +++---- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 96 +++++++++++++++---------------- arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 2 + arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 2 + 8 files changed, 96 insertions(+), 107 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index 40ea7de44933..ed22d94f4fe5 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -12,58 +12,46 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 - -#define PIN_DRV_LV1 0 -#define PIN_DRV_LV2 2 -#define PIN_DRV_LV3 1 -#define PIN_DRV_LV4 3 - -#define PIN_PDN_OUT0 0 -#define PIN_PDN_OUT1 1 -#define PIN_PDN_INPUT 2 -#define PIN_PDN_PREV 3 - -#define PIN_IN(_pin, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <0>; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ +#include + +#define PIN_IN(_pin, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = ; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ } -#define PIN_OUT(_pin, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <1>; \ - samsung,pin-pud = <0>; \ - samsung,pin-drv = ; \ +#define PIN_OUT(_pin, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = ; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ } -#define PIN_OUT_SET(_pin, _val, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <1>; \ - samsung,pin-pud = <0>; \ - samsung,pin-drv = ; \ - samsung,pin-val = <_val>; \ +#define PIN_OUT_SET(_pin, _val, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = ; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ + samsung,pin-val = <_val>; \ } -#define PIN_CFG(_pin, _sel, _pull, _drv) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-function = <_sel>; \ - samsung,pin-pud = ; \ - samsung,pin-drv = ; \ +#define PIN_CFG(_pin, _sel, _pull, _drv) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-function = <_sel>; \ + samsung,pin-pud = ; \ + samsung,pin-drv = ; \ } -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ } &pinctrl_0 { diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 9331c6252eff..cc65537ff79b 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -14,6 +14,8 @@ * published by the Free Software Foundation. */ +#include + / { pinctrl@11400000 { gpa0: gpa0 { diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi index 75af9c56123e..63714445dddb 100644 --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -11,6 +11,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl_0 { gpa0: gpa0 { gpio-controller; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 856b29254374..b5ded0ccce07 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -12,20 +12,13 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 - -#define PIN_PDN_OUT0 0 -#define PIN_PDN_OUT1 1 -#define PIN_PDN_INPUT 2 -#define PIN_PDN_PREV 3 - -#define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ - samsung,pins = #_pin; \ - samsung,pin-con-pdn = ; \ - samsung,pin-pud-pdn = ; \ +#include + +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = ; \ + samsung,pin-pud-pdn = ; \ } / { diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index 880917e508b2..d1a4ea0fb838 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl_0 { gpa0: gpa0 { gpio-controller; diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index f6ee55ea0708..39c046758029 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -12,9 +12,7 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 3 +#include &pinctrl_0 { gpa0: gpa0 { @@ -188,56 +186,56 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; uart1_data: uart1-data { samsung,pins = "gpa1-0", "gpa1-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa1-2", "gpa1-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; uart2_data: uart2-data { samsung,pins = "gpa1-4", "gpa1-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; usb3_vbus0_en: usb3-vbus0-en { samsung,pins = "gpa2-4"; samsung,pin-function = <1>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; @@ -245,7 +243,7 @@ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; @@ -253,105 +251,105 @@ samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; spdif1_bus: spdif1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c0_hs_bus: i2c0-hs-bus { samsung,pins = "gpb3-0", "gpb3-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpb3-4", "gpb3-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpb3-6", "gpb3-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb4-0", "gpb4-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb4-2", "gpb4-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c6_bus: i2c6-bus { samsung,pins = "gpb4-4", "gpb4-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c7_bus: i2c7-bus { samsung,pins = "gpb4-6", "gpb4-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c8_bus: i2c8-bus { samsung,pins = "gpb5-0", "gpb5-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c9_bus: i2c9-bus { samsung,pins = "gpb5-2", "gpb5-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c10_bus: i2c10-bus { samsung,pins = "gpb5-4", "gpb5-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; i2c11_bus: i2c11-bus { samsung,pins = "gpb5-6", "gpb5-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; @@ -360,7 +358,7 @@ "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; @@ -368,35 +366,35 @@ samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <0>; }; }; @@ -445,112 +443,112 @@ sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpc0-6"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd1_clk: sd1-clk { samsung,pins = "gpc1-0"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc1-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd1_bus8: sd1-bus-width8 { samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; samsung,pin-drv = <3>; }; }; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index b58a0f29f42c..bf43792efe27 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -9,6 +9,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl_0 { gpa0: gpa0 { gpio-controller; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index 14beb7e07323..cf7d2986780a 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -12,6 +12,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl_0 { gpy7: gpy7 { gpio-controller; -- cgit v1.2.3 From 2aea3de8640cc8ce1977be99d2260fa507cb1a68 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:07 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos3250 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 270 +++++++++++++++--------------- 1 file changed, 135 insertions(+), 135 deletions(-) diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index ed22d94f4fe5..ec331169c3d9 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -113,158 +113,158 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; mipi0_clk: mipi0-clk { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -396,164 +396,164 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpk0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From 4b1a9e358693bbef0b5a1a5787e35490022957b9 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:08 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos4210 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 454 ++++++++++++------------ arch/arm/boot/dts/exynos4210-smdkv310.dts | 12 +- arch/arm/boot/dts/exynos4210-universal_c210.dts | 8 +- 3 files changed, 237 insertions(+), 237 deletions(-) diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index cc65537ff79b..8046340e50ac 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -148,245 +148,245 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart_audio_a: uart-audio-a { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart_audio_b: uart-audio-b { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-6", "gpb-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_sync: lcd-sync { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_en: lcd-en { samsung,pins = "gpe3-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data16: lcd-data-width16 { @@ -394,9 +394,9 @@ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data18: lcd-data-width18 { @@ -405,9 +405,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data24: lcd-data-width24 { @@ -417,9 +417,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -571,263 +571,263 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = <4>; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint0: ext-int0 { samsung,pins = "gpx0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint8: ext-int8 { samsung,pins = "gpx1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint15: ext-int15 { samsung,pins = "gpx1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint16: ext-int16 { samsung,pins = "gpx2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint31: ext-int31 { samsung,pins = "gpx3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_cec: hdmi-cec { samsung,pins = "gpx3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -840,17 +840,17 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm0_bus: pcm0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; - samsung,pin-function = <0x3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index 847fae3dd1f1..a998ca48dba3 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -136,17 +136,17 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index 9a75e3effbc9..fa1e2c044aac 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -521,16 +521,16 @@ &pinctrl_1 { hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; - samsung,pin-pud = <0>; + samsung,pin-pud = ; }; }; &pinctrl_0 { i2c_ddc_bus: i2c-ddc-bus { samsung,pins = "gpe4-2", "gpe4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From c35bc3f9fa7340187d7b0fc5790623c76c2ceb54 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:09 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos4x12 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 14 +- arch/arm/boot/dts/exynos4412-odroidx.dts | 2 +- arch/arm/boot/dts/exynos4412-origen.dts | 12 +- arch/arm/boot/dts/exynos4412-smdk4412.dts | 12 +- arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 504 ++++++++++++------------ 5 files changed, 272 insertions(+), 272 deletions(-) diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index 58ad48e7b8f7..ef5cc29b90b1 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -163,26 +163,26 @@ /* RSTN signal for eMMC */ &sd1_cd { - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-pud = ; + samsung,pin-drv = ; }; &pinctrl_1 { gpio_power_key: power_key { samsung,pins = "gpx1-3"; - samsung,pin-pud = <0>; + samsung,pin-pud = ; }; max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_hpd: hdmi-hpd { samsung,pins = "gpx3-7"; - samsung,pin-pud = <1>; + samsung,pin-pud = ; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 2af235151301..d82d85857349 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -83,7 +83,7 @@ &pinctrl_1 { gpio_home_key: home_key { samsung,pins = "gpx2-2"; - samsung,pin-pud = <0>; + samsung,pin-pud = ; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index 26a36fed9652..96f8e94b4ac0 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -500,16 +500,16 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts index 231ffbdbf9d0..a20b71918405 100644 --- a/arch/arm/boot/dts/exynos4412-smdk4412.dts +++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts @@ -115,17 +115,17 @@ &pinctrl_1 { keypad_rows: keypad-rows { samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_cols: keypad-cols { samsung,pins = "gpx1-0", "gpx1-1", "gpx1-2", "gpx1-3", "gpx1-4", "gpx1-5", "gpx1-6", "gpx1-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index b5ded0ccce07..a56bf9b1a412 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -129,245 +129,245 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart_audio_a: uart-audio-a { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart_audio_b: uart-audio-b { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; mipi0_clk: mipi0-clk { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; mipi1_clk: mipi1-clk { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data16: lcd-data-width16 { @@ -375,9 +375,9 @@ "gpf1-3", "gpf1-6", "gpf1-7", "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data18: lcd-data-width18 { @@ -386,9 +386,9 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data24: lcd-data-width24 { @@ -398,39 +398,39 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_ldi: lcd-ldi { samsung,pins = "gpf3-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -606,284 +606,284 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint0: ext-int0 { samsung,pins = "gpx0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint8: ext-int8 { samsung,pins = "gpx1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint15: ext-int15 { samsung,pins = "gpx1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint16: ext-int16 { samsung,pins = "gpx2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint31: ext-int31 { samsung,pins = "gpx3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_cec: hdmi-cec { samsung,pins = "gpx3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -899,17 +899,17 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm0_bus: pcm0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4"; - samsung,pin-function = <0x3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -964,9 +964,9 @@ "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7", "gpv4-0", "gpv4-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; }; -- cgit v1.2.3 From 040611c87c7fdd1aad4885b1f95b88c07fd6c84f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:10 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos4415 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 286 +++++++++++++++--------------- 1 file changed, 143 insertions(+), 143 deletions(-) diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi index 63714445dddb..f54aee53b6ec 100644 --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -96,180 +96,180 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <0x2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -394,120 +394,120 @@ sd0_clk: sd0-clk { samsung,pins = "gpk0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpk0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; samsung,pin-drv = <4>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; samsung,pin-drv = <4>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; samsung,pin-drv = <4>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; samsung,pin-drv = <4>; }; @@ -515,44 +515,44 @@ samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpm2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpm2-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c0: fimc-is-i2c0 { samsung,pins = "gpm4-0", "gpm4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_i2c1: fimc-is-i2c1 { samsung,pins = "gpm4-2", "gpm4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; fimc_is_uart: fimc-is-uart { samsung,pins = "gpm3-5", "gpm3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -568,8 +568,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From d953f1fb14d2573499a7584a091a724c5923d5b3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:11 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos5250 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 402 +++++++++++++------------- arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +- arch/arm/boot/dts/exynos5250-snow-common.dtsi | 76 ++--- arch/arm/boot/dts/exynos5250-snow-rev5.dts | 6 +- arch/arm/boot/dts/exynos5250-snow.dts | 6 +- arch/arm/boot/dts/exynos5250-spring.dts | 72 ++--- 6 files changed, 284 insertions(+), 284 deletions(-) diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi index d1a4ea0fb838..2f6ab32b5954 100644 --- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi @@ -202,392 +202,392 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ac97_bus: ac97-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spdif_bus: spdif-bus { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_hs_bus: i2c0-hs-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc2-3", "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpc3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc3-3", "gpc3-4", "gpc3-5", "gpc3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_clk: sd3-clk { samsung,pins = "gpc4-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cmd: sd3-cmd { samsung,pins = "gpc4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cd: sd3-cd { samsung,pins = "gpc4-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpc4-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpc4-3", "gpc4-4", "gpc4-5", "gpc4-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpd0-2", "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; dp_hpd: dp_hpd { samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -668,52 +668,52 @@ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c2_bus: cam-i2c2-bus { samsung,pins = "gpe0-6", "gpe1-0"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_bayrgb_bus: cam-bayrgb-bus { @@ -722,18 +722,18 @@ "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", "gpg2-0", "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a: cam-port-a { samsung,pins = "gph0-0", "gph0-1", "gph0-2", "gph0-3", "gph1-0", "gph1-1", "gph1-2", "gph1-3", "gph1-4", "gph1-5", "gph1-6", "gph1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -783,9 +783,9 @@ "gpv0-4", "gpv0-5", "gpv0-6", "gpv0-7", "gpv1-0", "gpv1-1", "gpv1-2", "gpv1-3", "gpv1-4", "gpv1-5", "gpv1-6", "gpv1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; c2c_txd: c2c-txd { @@ -793,9 +793,9 @@ "gpv2-4", "gpv2-5", "gpv2-6", "gpv2-7", "gpv3-0", "gpv3-1", "gpv3-2", "gpv3-3", "gpv3-4", "gpv3-5", "gpv3-6", "gpv3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -811,8 +811,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 381af134c4c8..8b39980a7c8b 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -416,8 +416,8 @@ &pinctrl_0 { max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi index fadbea744e1a..10263d0ab892 100644 --- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi +++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi @@ -440,7 +440,7 @@ * double-pulling gets us out of spec in some cases. */ &i2c2_bus { - samsung,pin-pud = <0>; + samsung,pin-pud = ; }; &i2c_2 { @@ -572,81 +572,81 @@ &pinctrl_0 { wifi_en: wifi-en { samsung,pins = "gpx0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; wifi_rst: wifi-rst { samsung,pins = "gpx0-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ec_irq: ec-irq { samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb3_vbus_en: usb3-vbus-en { samsung,pins = "gpx2-7"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lid_irq: lid-irq { samsung,pins = "gpx3-5"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_1 { arb_their_claim: arb-their-claim { samsung,pins = "gpe0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; arb_our_claim: arb-our-claim { samsung,pins = "gpf0-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -657,16 +657,16 @@ }; &sd3_bus4 { - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; &sd3_clk { - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; &sd3_cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-pud = ; + samsung,pin-drv = ; }; &spi_1 { diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index f811dc800660..90560c316f64 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -40,8 +40,8 @@ &pinctrl_0 { max98090_irq: max98090-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index 995c7ce6c12b..df48f2cc96f7 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -36,8 +36,8 @@ &pinctrl_0 { max98095_en: max98095-en { samsung,pins = "gpx1-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts index 44f4292bfef6..4ec0d67bdfc3 100644 --- a/arch/arm/boot/dts/exynos5250-spring.dts +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -357,7 +357,7 @@ * double-pulling gets us out of spec in some cases. */ &i2c2_bus { - samsung,pin-pud = <0>; + samsung,pin-pud = ; }; &i2c_2 { @@ -460,92 +460,92 @@ &pinctrl_0 { s5m8767_dvs: s5m8767-dvs { samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; dp_hpd_gpio: dp-hpd-gpio { samsung,pins = "gpc3-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-3"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ec_irq: ec-irq { samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; s5m8767_ds: s5m8767-ds { samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; s5m8767_irq: s5m8767-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lid_irq: lid-irq { samsung,pins = "gpx3-5"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_1 { hsic_reset: hsic-reset { samsung,pins = "gpe1-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &sd1_bus4 { - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; &sd1_cd { - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; &sd1_clk { - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; &sd1_cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-pud = ; + samsung,pin-drv = ; }; &spi_1 { -- cgit v1.2.3 From bad96a019d2867b6043ffcdcf211d92c40027c0f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:12 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos5260 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 184 ++++++++++++++--------------- arch/arm/boot/dts/exynos5260-xyref5260.dts | 6 +- 2 files changed, 95 insertions(+), 95 deletions(-) diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi index 39c046758029..1b911a219a27 100644 --- a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi @@ -185,217 +185,217 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; usb3_vbus0_en: usb3-vbus0-en { samsung,pins = "gpa2-4"; - samsung,pin-function = <1>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; spdif1_bus: spdif1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c0_hs_bus: i2c0-hs-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c1_hs_bus: i2c1-hs-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c2_hs_bus: i2c2-hs-bus { samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c3_hs_bus: i2c3-hs-bus { samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c4_bus: i2c4-bus { samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c5_bus: i2c5-bus { samsung,pins = "gpb4-2", "gpb4-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c6_bus: i2c6-bus { samsung,pins = "gpb4-4", "gpb4-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c7_bus: i2c7-bus { samsung,pins = "gpb4-6", "gpb4-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c8_bus: i2c8-bus { samsung,pins = "gpb5-0", "gpb5-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c9_bus: i2c9-bus { samsung,pins = "gpb5-2", "gpb5-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c10_bus: i2c10-bus { samsung,pins = "gpb5-4", "gpb5-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; i2c11_bus: i2c11-bus { samsung,pins = "gpb5-6", "gpb5-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_gpio_a: cam-gpio-a { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <0>; + samsung,pin-drv = ; }; }; @@ -442,114 +442,114 @@ sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd0_rdqs: sd0-rdqs { samsung,pins = "gpc0-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpc1-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc1-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd1_bus8: sd1-bus-width8 { samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <3>; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 3daef94bee38..ccbdc8ad3da3 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -42,9 +42,9 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From 17dcc16fbd0336a78e980a08d565ad5059f87c53 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:13 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos5410 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos5410-odroidxu.dts | 30 ++--- arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 180 +++++++++++++++--------------- arch/arm/boot/dts/exynos5410-smdk5410.dts | 10 +- 3 files changed, 110 insertions(+), 110 deletions(-) diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index d9499310a301..d35f5affb564 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -476,38 +476,38 @@ &pinctrl_0 { emmc_nrst_pin: emmc-nrst { samsung,pins = "gpd1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpx0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpx0-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; samsung,pin-val = <1>; }; max77802_irq: max77802-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi index bf43792efe27..a083d23fdee3 100644 --- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi @@ -282,212 +282,212 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_hs_bus: i2c4-hs-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_hs_bus: i2c5-hs-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_hs_bus: i2c6-hs-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_hs_bus: i2c7-hs-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 777fcf2edd79..7a67bc02291d 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -66,8 +66,8 @@ srom_ctl: srom-ctl { samsung,pins = "gpy0-3", "gpy0-4", "gpy0-5", "gpy1-0", "gpy1-1", "gpy1-2", "gpy1-3"; - samsung,pin-function = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-drv = ; }; srom_ebi: srom-ebi { @@ -77,9 +77,9 @@ "gpy5-4", "gpy5-5", "gpy5-6", "gpy5-7", "gpy6-0", "gpy6-1", "gpy6-2", "gpy6-3", "gpy6-4", "gpy6-5", "gpy6-6", "gpy6-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From a2f2bc384e8df20b881625e6a92726d5b9f39d6b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:14 +0200 Subject: ARM: dts: exynos: Use macros for pinctrl configuration on exynos542x/exynos5800 Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos5420-arndale-octa.dts | 6 +- arch/arm/boot/dts/exynos5420-peach-pit.dts | 126 ++++---- arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 354 ++++++++++----------- arch/arm/boot/dts/exynos5420-smdk5420.dts | 18 +- arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 18 +- arch/arm/boot/dts/exynos5800-peach-pi.dts | 126 ++++---- 6 files changed, 324 insertions(+), 324 deletions(-) diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 39a3b81478fd..657ffbb096c1 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -378,9 +378,9 @@ &pinctrl_0 { s2mps11_irq: s2mps11-irq { samsung,pins = "gpx3-2"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index fe4e0915c0c6..58a4d335be74 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -753,171 +753,171 @@ wifi_en: wifi-en { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; max98090_irq: max98090-irq { samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ mask_tpm_reset: mask-tpm-reset { samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; samsung,pin-val = <0>; }; tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ec_irq: ec-irq { samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; max77802_irq: max77802-irq { samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lid_irq: lid-irq { samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_1 { /* Adjust WiFi drive strengths lower for EMI */ sd1_clk: sd1-clk { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; }; &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_3 { /* Drive SPI lines at x2 for better integrity */ spi2-bus { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; /* Drive SPI chip select at x2 for better integrity */ ec_spi_cs: ec-spi-cs { samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_selb: pmic-selb { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi index cf7d2986780a..3924b4fafe72 100644 --- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi @@ -63,9 +63,9 @@ dp_hpd: dp_hpd { samsung,pins = "gpx0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -155,135 +155,135 @@ sd0_clk: sd0-clk { samsung,pins = "gpc0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpc0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpc0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpc0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_rclk: sd0-rclk { samsung,pins = "gpc0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <1>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpc1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpc1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpc1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_int: sd1-int { samsung,pins = "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpc1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpc1-4", "gpc1-5", "gpc1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus8: sd1-bus-width8 { samsung,pins = "gpd1-4", "gpd1-5", "gpd1-6", "gpd1-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpc2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpc2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -356,52 +356,52 @@ samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_gpio_b: cam-gpio-b { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3", "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c2_bus: cam-i2c2-bus { samsung,pins = "gpf0-4", "gpf0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_spi1_bus: cam-spi1-bus { samsung,pins = "gpe0-4", "gpe0-5", "gpf0-2", "gpf0-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c1_bus: cam-i2c1-bus { samsung,pins = "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_i2c0_bus: cam-i2c0-bus { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_spi0_bus: cam-spi0-bus { samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_bayrgb_bus: cam-bayrgb-bus { @@ -410,9 +410,9 @@ "gpg1-0", "gpg1-1", "gpg1-2", "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6", "gpg1-7", "gpg2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -491,216 +491,216 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c3_bus: i2c3-bus { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-4", "gpa1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpa2-0", "gpa2-1", "gpa2-2", "gpa2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c4_hs_bus: i2c4-hs-bus { samsung,pins = "gpa2-0", "gpa2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c5_hs_bus: i2c5-hs-bus { samsung,pins = "gpa2-2", "gpa2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3", "gpb0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpb1-0", "gpb1-1", "gpb1-2", "gpb1-3", "gpb1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spdif_bus: spdif-bus { samsung,pins = "gpb1-0", "gpb1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpb1-1", "gpb1-3", "gpb1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c6_hs_bus: i2c6-hs-bus { samsung,pins = "gpb1-3", "gpb1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpb2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpb2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpb2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpb2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c7_hs_bus: i2c7-hs-bus { samsung,pins = "gpb2-2", "gpb2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb3-0", "gpb3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpb3-2", "gpb3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c8_hs_bus: i2c8-hs-bus { samsung,pins = "gpb3-4", "gpb3-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c9_hs_bus: i2c9-hs-bus { samsung,pins = "gpb3-6", "gpb3-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c10_hs_bus: i2c10-hs-bus { samsung,pins = "gpb4-0", "gpb4-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; @@ -716,8 +716,8 @@ i2s0_bus: i2s0-bus { samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", "gpz-4", "gpz-5", "gpz-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index ed8f3426911b..0ce48659d136 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -386,25 +386,25 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_2 { usb300_vbus_en: usb300-vbus-en { samsung,pins = "gpg0-5"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gpg1-4"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi index d56253049ccb..9a4ece18e965 100644 --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi @@ -548,25 +548,25 @@ &pinctrl_0 { hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; s2mps11_irq: s2mps11-irq { samsung,pins = "gpx0-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_1 { emmc_nrst_pin: emmc-nrst { samsung,pins = "gpd1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index 5ec71e2400fd..2a218aae3484 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -722,171 +722,171 @@ wifi_en: wifi-en { samsung,pins = "gpx0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; max98091_irq: max98091-irq { samsung,pins = "gpx0-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; /* We need GPX0_6 to be low at sleep time; just keep it low always */ mask_tpm_reset: mask-tpm-reset { samsung,pins = "gpx0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; samsung,pin-val = <0>; }; tpm_irq: tpm-irq { samsung,pins = "gpx1-0"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; trackpad_irq: trackpad-irq { samsung,pins = "gpx1-1"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ec_irq: ec-irq { samsung,pins = "gpx1-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; tps65090_irq: tps65090-irq { samsung,pins = "gpx2-5"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; dp_hpd_gpio: dp_hpd_gpio { samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; max77802_irq: max77802-irq { samsung,pins = "gpx3-1"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lid_irq: lid-irq { samsung,pins = "gpx3-4"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_1: pmic-dvs-1 { samsung,pins = "gpy7-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_1 { /* Adjust WiFi drive strengths lower for EMI */ sd1_clk: sd1-clk { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; sd1_bus8: sd1-bus-width8 { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; }; &pinctrl_2 { pmic_dvs_2: pmic-dvs-2 { samsung,pins = "gpj4-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_dvs_3: pmic-dvs-3 { samsung,pins = "gpj4-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; &pinctrl_3 { /* Drive SPI lines at x2 for better integrity */ spi2-bus { - samsung,pin-drv = <2>; + samsung,pin-drv = ; }; /* Drive SPI chip select at x2 for better integrity */ ec_spi_cs: ec-spi-cs { samsung,pins = "gpb1-2"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <2>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb300_vbus_en: usb300-vbus-en { samsung,pins = "gph0-0"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; usb301_vbus_en: usb301-vbus-en { samsung,pins = "gph0-1"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pmic_selb: pmic-selb { samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", "gph0-6"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From f7061ffb44116490f282f130a220ca2d10849248 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:15 +0200 Subject: ARM: dts: exynos: Fix mismatched value for SD4 pull up/down configuration on exynos4210 The pinctrl pull up/down register on exynos4210 is 2-bit wide for each pin and it accepts only values of 0, 1 and 3. The pins sd4-bus-width8 were configured with value of 4. The driver does not validate the value so this overflow effectively set a bit 1 in adjacent pins thus configuring them to pull down. The author's intention was probably to set drive strength of 4x. All other bus-widths pins are configured with pull up and drive strength of 4x. Fix this one with same pattern. Fixes: 87711d8c7c70 ("ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoC") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Reviewed-by: Bartlomiej Zolnierkiewicz Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi index 8046340e50ac..d9b6d25e4abe 100644 --- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi @@ -649,7 +649,7 @@ sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = ; - samsung,pin-pud = <4>; + samsung,pin-pud = ; samsung,pin-drv = ; }; -- cgit v1.2.3 From 5e49773f8703a0b376cdcfd6b26fadf18485f26b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:16 +0200 Subject: ARM: dts: exynos: Fix mismatched values of SD drive strengh configuration on exynos4415 The pinctrl drive strength register on exynos4415 is 2-bit wide for each pin. The pins for SD2 were configured with value of 4. The driver does not validate the value so this overflow effectively set a bit 1 in adjacent pins thus configuring them to drive strength 2x. The author's intention was probably to set drive strength of 4x. All other SD pins are configured with drive strength of 4x. Fix these with same pattern. Fixes: 9246e7ff24c5 ("ARM: dts: Add dts files for exynos4415 SoC") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Reviewed-by: Bartlomiej Zolnierkiewicz Acked-by: Linus Walleij --- arch/arm/boot/dts/exynos4415-pinctrl.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi index f54aee53b6ec..76cfd872ead3 100644 --- a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -480,14 +480,14 @@ samsung,pins = "gpk2-0"; samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <4>; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <4>; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { @@ -501,14 +501,14 @@ samsung,pins = "gpk2-3"; samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <4>; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = ; samsung,pin-pud = ; - samsung,pin-drv = <4>; + samsung,pin-drv = ; }; cam_port_b_io: cam-port-b-io { -- cgit v1.2.3 From 68175d5dd7c5476da66922c2513b29ea6c669741 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:17 +0200 Subject: ARM: dts: s3c64xx: Use common macros for pinctrl configuration Replace duplicated macros in each DTSI file with a common macro coming from header. Include the header in each pinctrl DTSI so further changes could use it. Although PIN_FUNC_SPC_2 does not bring much information about the function itself, it still is more descriptive then hard-coded number <2>. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/s3c6410-mini6410.dts | 4 +- arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 180 ++++++++++++++++----------------- 2 files changed, 91 insertions(+), 93 deletions(-) diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index a25debb50401..f4afda3594f8 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -201,13 +201,13 @@ &pinctrl0 { gpio_leds: gpio-leds { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-pud = ; + samsung,pin-pud = ; }; gpio_keys: gpio-keys { samsung,pins = "gpn-0", "gpn-1", "gpn-2", "gpn-3", "gpn-4", "gpn-5", "gpl-11", "gpl-12"; - samsung,pin-pud = ; + samsung,pin-pud = ; }; }; diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index b1197d8b04de..93810d992c3f 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -12,9 +12,7 @@ * published by the Free Software Foundation. */ -#define PIN_PULL_NONE 0 -#define PIN_PULL_DOWN 1 -#define PIN_PULL_UP 2 +#include &pinctrl0 { /* @@ -139,219 +137,219 @@ uart0_data: uart0-data { samsung,pins = "gpa-0", "gpa-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa-2", "gpa-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; uart1_data: uart1-data { samsung,pins = "gpa-4", "gpa-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa-6", "gpa-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; uart2_data: uart2-data { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; uart3_data: uart3-data { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; ext_dma_0: ext-dma-0 { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; ext_dma_1: ext-dma-1 { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; irda_data_0: irda-data-0 { samsung,pins = "gpb-0", "gpb-1"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; irda_data_1: irda-data-1 { samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; irda_sdbw: irda-sdbw { samsung,pins = "gpb-4"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb-5", "gpb-6"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2c1_bus: i2c1-bus { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; samsung,pin-function = <6>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; spi0_bus: spi0-bus { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; spi0_cs: spi0-cs { samsung,pins = "gpc-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; spi1_bus: spi1-bus { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; spi1_cs: spi1-cs { samsung,pins = "gpc-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpg-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd0_clk: sd0-clk { samsung,pins = "gpg-0"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd0_bus1: sd0-bus1 { samsung,pins = "gpg-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd0_bus4: sd0-bus4 { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd0_cd: sd0-cd { samsung,pins = "gpg-6"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gph-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_clk: sd1-clk { samsung,pins = "gph-0"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_bus1: sd1-bus1 { samsung,pins = "gph-2"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_bus4: sd1-bus4 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_bus8: sd1-bus8 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd1_cd: sd1-cd { samsung,pins = "gpg-6"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc-5"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd2_bus1: sd2-bus1 { samsung,pins = "gph-6"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; sd2_bus4: sd2-bus4 { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s0_bus: i2s0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s0_cdclk: i2s0-cdclk { samsung,pins = "gpd-1"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s1_cdclk: i2s1-cdclk { samsung,pins = "gpe-1"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s2_bus: i2s2-bus { @@ -359,50 +357,50 @@ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; samsung,pin-function = <5>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; i2s2_cdclk: i2s2-cdclk { /* S3C6410-only */ samsung,pins = "gph-7"; samsung,pin-function = <5>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pcm0_bus: pcm0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pcm0_extclk: pcm0-extclk { samsung,pins = "gpd-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pcm1_extclk: pcm1-extclk { samsung,pins = "gpe-1"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; ac97_bus_0: ac97-bus-0 { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; ac97_bus_1: ac97-bus-1 { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; cam_port: cam-port { @@ -410,242 +408,242 @@ "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; cam_rst: cam-rst { samsung,pins = "gpf-3"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; cam_field: cam-field { /* S3C6410-only */ samsung,pins = "gpb-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pwm_extclk: pwm-extclk { samsung,pins = "gpf-13"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pwm0_out: pwm0-out { samsung,pins = "gpf-14"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; pwm1_out: pwm1-out { samsung,pins = "gpf-15"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; clkout0: clkout-0 { samsung,pins = "gpf-14"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col0_0: keypad-col0-0 { samsung,pins = "gph-0"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col1_0: keypad-col1-0 { samsung,pins = "gph-1"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col2_0: keypad-col2-0 { samsung,pins = "gph-2"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col3_0: keypad-col3-0 { samsung,pins = "gph-3"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col4_0: keypad-col4-0 { samsung,pins = "gph-4"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col5_0: keypad-col5-0 { samsung,pins = "gph-5"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col6_0: keypad-col6-0 { samsung,pins = "gph-6"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col7_0: keypad-col7-0 { samsung,pins = "gph-7"; samsung,pin-function = <4>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col0_1: keypad-col0-1 { samsung,pins = "gpl-0"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col1_1: keypad-col1-1 { samsung,pins = "gpl-1"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col2_1: keypad-col2-1 { samsung,pins = "gpl-2"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col3_1: keypad-col3-1 { samsung,pins = "gpl-3"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col4_1: keypad-col4-1 { samsung,pins = "gpl-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col5_1: keypad-col5-1 { samsung,pins = "gpl-5"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col6_1: keypad-col6-1 { samsung,pins = "gpl-6"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_col7_1: keypad-col7-1 { samsung,pins = "gpl-7"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row0_0: keypad-row0-0 { samsung,pins = "gpk-8"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row1_0: keypad-row1-0 { samsung,pins = "gpk-9"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row2_0: keypad-row2-0 { samsung,pins = "gpk-10"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row3_0: keypad-row3-0 { samsung,pins = "gpk-11"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row4_0: keypad-row4-0 { samsung,pins = "gpk-12"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row5_0: keypad-row5-0 { samsung,pins = "gpk-13"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row6_0: keypad-row6-0 { samsung,pins = "gpk-14"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row7_0: keypad-row7-0 { samsung,pins = "gpk-15"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row0_1: keypad-row0-1 { samsung,pins = "gpn-0"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row1_1: keypad-row1-1 { samsung,pins = "gpn-1"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row2_1: keypad-row2-1 { samsung,pins = "gpn-2"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row3_1: keypad-row3-1 { samsung,pins = "gpn-3"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row4_1: keypad-row4-1 { samsung,pins = "gpn-4"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row5_1: keypad-row5-1 { samsung,pins = "gpn-5"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row6_1: keypad-row6-1 { samsung,pins = "gpn-6"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; keypad_row7_1: keypad-row7-1 { samsung,pins = "gpn-7"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; lcd_data16: lcd-data-width16 { @@ -654,7 +652,7 @@ "gpi-13", "gpi-14", "gpi-15", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; lcd_data18: lcd-data-width18 { @@ -664,7 +662,7 @@ "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; lcd_data24: lcd-data-width24 { @@ -675,13 +673,13 @@ "gpj-0", "gpj-1", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; samsung,pin-function = <2>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; hsi_bus: hsi-bus { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; samsung,pin-function = <3>; - samsung,pin-pud = ; + samsung,pin-pud = ; }; }; -- cgit v1.2.3 From 293fea6f71dcb5c68b47f253c6f77ef5c030e2c3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:18 +0200 Subject: ARM: dts: s5pv210: Use macros for pinctrl configuration Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/s5pv210-aquila.dts | 4 +- arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 476 +++++++++++++++++---------------- 2 files changed, 241 insertions(+), 239 deletions(-) diff --git a/arch/arm/boot/dts/s5pv210-aquila.dts b/arch/arm/boot/dts/s5pv210-aquila.dts index da24ab570b0e..f6cb82f36aae 100644 --- a/arch/arm/boot/dts/s5pv210-aquila.dts +++ b/arch/arm/boot/dts/s5pv210-aquila.dts @@ -387,7 +387,7 @@ &pinctrl0 { t_flash_detect: t-flash-detect { samsung,pins = "gph3-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; }; }; diff --git a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi index 8c714088e3c6..9a3e851e2e22 100644 --- a/arch/arm/boot/dts/s5pv210-pinctrl.dtsi +++ b/arch/arm/boot/dts/s5pv210-pinctrl.dtsi @@ -19,6 +19,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl0 { gpa0: gpa0 { gpio-controller; @@ -270,559 +272,559 @@ uart0_data: uart0-data { samsung,pins = "gpa0-0", "gpa0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa0-2", "gpa0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_data: uart1-data { samsung,pins = "gpa0-4", "gpa0-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa0-6", "gpa0-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_data: uart2-data { samsung,pins = "gpa1-0", "gpa1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart3_data: uart3-data { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; uart_audio: uart-audio { samsung,pins = "gpa1-2", "gpa1-3"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi0_bus: spi0-bus { samsung,pins = "gpb-0", "gpb-2", "gpb-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi1_bus: spi1-bus { samsung,pins = "gpb-4", "gpb-6", "gpb-7"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s0_bus: i2s0-bus { samsung,pins = "gpi-0", "gpi-1", "gpi-2", "gpi-3", "gpi-4", "gpi-5", "gpi-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; ac97_bus: ac97-bus { samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", "gpc0-4"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2s2_bus: i2s2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pcm2_bus: pcm2-bus { samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spdif_bus: spdif-bus { samsung,pins = "gpc1-0", "gpc1-1"; - samsung,pin-function = <4>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; spi2_bus: spi2-bus { samsung,pins = "gpc1-1", "gpc1-2", "gpc1-3", "gpc1-4"; - samsung,pin-function = <5>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpd1-0", "gpd1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c1_bus: i2c1-bus { samsung,pins = "gpd1-2", "gpd1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; i2c2_bus: i2c2-bus { samsung,pins = "gpd1-4", "gpd1-5"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm0_out: pwm0-out { samsung,pins = "gpd0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm1_out: pwm1-out { samsung,pins = "gpd0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm2_out: pwm2-out { samsung,pins = "gpd0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; pwm3_out: pwm3-out { samsung,pins = "gpd0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row0: keypad-row-0 { samsung,pins = "gph3-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row1: keypad-row-1 { samsung,pins = "gph3-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row2: keypad-row-2 { samsung,pins = "gph3-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row3: keypad-row-3 { samsung,pins = "gph3-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row4: keypad-row-4 { samsung,pins = "gph3-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row5: keypad-row-5 { samsung,pins = "gph3-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row6: keypad-row-6 { samsung,pins = "gph3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_row7: keypad-row-7 { samsung,pins = "gph3-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col0: keypad-col-0 { samsung,pins = "gph2-0"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col1: keypad-col-1 { samsung,pins = "gph2-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col2: keypad-col-2 { samsung,pins = "gph2-2"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col3: keypad-col-3 { samsung,pins = "gph2-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col4: keypad-col-4 { samsung,pins = "gph2-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col5: keypad-col-5 { samsung,pins = "gph2-5"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col6: keypad-col-6 { samsung,pins = "gph2-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; keypad_col7: keypad-col-7 { samsung,pins = "gph2-7"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_clk: sd0-clk { samsung,pins = "gpg0-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpg0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_cd: sd0-cd { samsung,pins = "gpg0-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpg0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpg0-3", "gpg0-4", "gpg0-5", "gpg0-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_clk: sd1-clk { samsung,pins = "gpg1-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpg1-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_cd: sd1-cd { samsung,pins = "gpg1-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpg1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpg1-3", "gpg1-4", "gpg1-5", "gpg1-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_clk: sd2-clk { samsung,pins = "gpg2-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpg2-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_cd: sd2-cd { samsung,pins = "gpg2-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpg2-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpg2-3", "gpg2-4", "gpg2-5", "gpg2-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <3>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_clk: sd3-clk { samsung,pins = "gpg3-0"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cmd: sd3-cmd { samsung,pins = "gpg3-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_cd: sd3-cd { samsung,pins = "gpg3-2"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpg3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpg3-3", "gpg3-4", "gpg3-5", "gpg3-6"; - samsung,pin-function = <2>; - samsung,pin-pud = <2>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint0: ext-int0 { samsung,pins = "gph0-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint8: ext-int8 { samsung,pins = "gph1-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint15: ext-int15 { samsung,pins = "gph1-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint16: ext-int16 { samsung,pins = "gph2-0"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; eint31: ext-int31 { samsung,pins = "gph3-7"; - samsung,pin-function = <0xf>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_io: cam-port-a-io { samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3", "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7", "gpe1-0", "gpe1-1", "gpe1-2", "gpe1-4"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_active: cam-port-a-clk-active { samsung,pins = "gpe1-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_a_clk_idle: cam-port-a-clk-idle { samsung,pins = "gpe1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_io: cam-port-b-io { samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_active: cam-port-b-clk-active { samsung,pins = "gpj1-3"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <3>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; cam_port_b_clk_idle: cam-port-b-clk-idle { samsung,pins = "gpj1-3"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpd0-0", "gpd0-1"; - samsung,pin-function = <3>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_sync: lcd-sync { samsung,pins = "gpf0-0", "gpf0-1"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_clk: lcd-clk { samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; lcd_data24: lcd-data-width24 { @@ -832,8 +834,8 @@ "gpf2-0", "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4", "gpf2-5", "gpf2-6", "gpf2-7", "gpf3-0", "gpf3-1", "gpf3-2", "gpf3-3"; - samsung,pin-function = <2>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; }; }; -- cgit v1.2.3 From 930f2910dc770dd7690bb51988101821c17de2d8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:19 +0200 Subject: ARM: dts: s3c2416: Use macros for pinctrl configuration Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/s3c2416-pinctrl.dtsi | 38 ++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi index 527e3193817f..6274359fb323 100644 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi @@ -8,6 +8,8 @@ * published by the Free Software Foundation. */ +#include + &pinctrl_0 { /* * Pin banks @@ -83,91 +85,91 @@ uart0_data: uart0-data { samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart1_data: uart1-data { samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart2_data: uart2-data { samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart2_fctl: uart2-fctl { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; uart3_data: uart3-data { samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; extuart_clk: extuart-clk { samsung,pins = "gph-12"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; spi0_bus: spi0-bus { samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd0_clk: sd0-clk { samsung,pins = "gpe-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpe-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd0_bus1: sd0-bus1 { samsung,pins = "gpe-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd0_bus4: sd0-bus4 { samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gpl-8"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd1_clk: sd1-clk { samsung,pins = "gpl-9"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd1_bus1: sd1-bus1 { samsung,pins = "gpl-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; sd1_bus4: sd1-bus4 { samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; }; }; -- cgit v1.2.3 From d13799237dee34e1b9cd377f0ced7bee24ac810f Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 4 Sep 2016 13:04:20 +0200 Subject: ARM: dts: s3c64xx: Use macros for pinctrl configuration Usage of DTS macros instead of hard-coded numbers makes code easier to read. One does not have to remember which value means pull-up/down or specific driver strength. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Acked-by: Linus Walleij --- arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 176 ++++++++++++++++----------------- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi index 93810d992c3f..4e8e802b4ee1 100644 --- a/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi +++ b/arch/arm/boot/dts/s3c64xx-pinctrl.dtsi @@ -136,219 +136,219 @@ uart0_data: uart0-data { samsung,pins = "gpa-0", "gpa-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; uart0_fctl: uart0-fctl { samsung,pins = "gpa-2", "gpa-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; uart1_data: uart1-data { samsung,pins = "gpa-4", "gpa-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; uart1_fctl: uart1-fctl { samsung,pins = "gpa-6", "gpa-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; uart2_data: uart2-data { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; uart3_data: uart3-data { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; ext_dma_0: ext-dma-0 { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; ext_dma_1: ext-dma-1 { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; irda_data_0: irda-data-0 { samsung,pins = "gpb-0", "gpb-1"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; irda_data_1: irda-data-1 { samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; irda_sdbw: irda-sdbw { samsung,pins = "gpb-4"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2c0_bus: i2c0-bus { samsung,pins = "gpb-5", "gpb-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2c1_bus: i2c1-bus { /* S3C6410-only */ samsung,pins = "gpb-2", "gpb-3"; - samsung,pin-function = <6>; + samsung,pin-function = ; samsung,pin-pud = ; }; spi0_bus: spi0-bus { samsung,pins = "gpc-0", "gpc-1", "gpc-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; spi0_cs: spi0-cs { samsung,pins = "gpc-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; spi1_bus: spi1-bus { samsung,pins = "gpc-4", "gpc-5", "gpc-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; spi1_cs: spi1-cs { samsung,pins = "gpc-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd0_cmd: sd0-cmd { samsung,pins = "gpg-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd0_clk: sd0-clk { samsung,pins = "gpg-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd0_bus1: sd0-bus1 { samsung,pins = "gpg-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd0_bus4: sd0-bus4 { samsung,pins = "gpg-2", "gpg-3", "gpg-4", "gpg-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd0_cd: sd0-cd { samsung,pins = "gpg-6"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_cmd: sd1-cmd { samsung,pins = "gph-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_clk: sd1-clk { samsung,pins = "gph-0"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_bus1: sd1-bus1 { samsung,pins = "gph-2"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_bus4: sd1-bus4 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_bus8: sd1-bus8 { samsung,pins = "gph-2", "gph-3", "gph-4", "gph-5", "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd1_cd: sd1-cd { samsung,pins = "gpg-6"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd2_cmd: sd2-cmd { samsung,pins = "gpc-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd2_clk: sd2-clk { samsung,pins = "gpc-5"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd2_bus1: sd2-bus1 { samsung,pins = "gph-6"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; sd2_bus4: sd2-bus4 { samsung,pins = "gph-6", "gph-7", "gph-8", "gph-9"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2s0_bus: i2s0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2s0_cdclk: i2s0-cdclk { samsung,pins = "gpd-1"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2s1_bus: i2s1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2s1_cdclk: i2s1-cdclk { samsung,pins = "gpe-1"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; @@ -356,50 +356,50 @@ /* S3C6410-only */ samsung,pins = "gpc-4", "gpc-5", "gpc-6", "gph-6", "gph-8", "gph-9"; - samsung,pin-function = <5>; + samsung,pin-function = ; samsung,pin-pud = ; }; i2s2_cdclk: i2s2-cdclk { /* S3C6410-only */ samsung,pins = "gph-7"; - samsung,pin-function = <5>; + samsung,pin-function = ; samsung,pin-pud = ; }; pcm0_bus: pcm0-bus { samsung,pins = "gpd-0", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; pcm0_extclk: pcm0-extclk { samsung,pins = "gpd-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; pcm1_bus: pcm1-bus { samsung,pins = "gpe-0", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; pcm1_extclk: pcm1-extclk { samsung,pins = "gpe-1"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; ac97_bus_0: ac97-bus-0 { samsung,pins = "gpd-0", "gpd-1", "gpd-2", "gpd-3", "gpd-4"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; ac97_bus_1: ac97-bus-1 { samsung,pins = "gpe-0", "gpe-1", "gpe-2", "gpe-3", "gpe-4"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; @@ -407,242 +407,242 @@ samsung,pins = "gpf-0", "gpf-1", "gpf-2", "gpf-4", "gpf-5", "gpf-6", "gpf-7", "gpf-8", "gpf-9", "gpf-10", "gpf-11", "gpf-12"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; cam_rst: cam-rst { samsung,pins = "gpf-3"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; cam_field: cam-field { /* S3C6410-only */ samsung,pins = "gpb-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; pwm_extclk: pwm-extclk { samsung,pins = "gpf-13"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; pwm0_out: pwm0-out { samsung,pins = "gpf-14"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; pwm1_out: pwm1-out { samsung,pins = "gpf-15"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; clkout0: clkout-0 { samsung,pins = "gpf-14"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col0_0: keypad-col0-0 { samsung,pins = "gph-0"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col1_0: keypad-col1-0 { samsung,pins = "gph-1"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col2_0: keypad-col2-0 { samsung,pins = "gph-2"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col3_0: keypad-col3-0 { samsung,pins = "gph-3"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col4_0: keypad-col4-0 { samsung,pins = "gph-4"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col5_0: keypad-col5-0 { samsung,pins = "gph-5"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col6_0: keypad-col6-0 { samsung,pins = "gph-6"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col7_0: keypad-col7-0 { samsung,pins = "gph-7"; - samsung,pin-function = <4>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col0_1: keypad-col0-1 { samsung,pins = "gpl-0"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col1_1: keypad-col1-1 { samsung,pins = "gpl-1"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col2_1: keypad-col2-1 { samsung,pins = "gpl-2"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col3_1: keypad-col3-1 { samsung,pins = "gpl-3"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col4_1: keypad-col4-1 { samsung,pins = "gpl-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col5_1: keypad-col5-1 { samsung,pins = "gpl-5"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col6_1: keypad-col6-1 { samsung,pins = "gpl-6"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_col7_1: keypad-col7-1 { samsung,pins = "gpl-7"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row0_0: keypad-row0-0 { samsung,pins = "gpk-8"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row1_0: keypad-row1-0 { samsung,pins = "gpk-9"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row2_0: keypad-row2-0 { samsung,pins = "gpk-10"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row3_0: keypad-row3-0 { samsung,pins = "gpk-11"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row4_0: keypad-row4-0 { samsung,pins = "gpk-12"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row5_0: keypad-row5-0 { samsung,pins = "gpk-13"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row6_0: keypad-row6-0 { samsung,pins = "gpk-14"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row7_0: keypad-row7-0 { samsung,pins = "gpk-15"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row0_1: keypad-row0-1 { samsung,pins = "gpn-0"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row1_1: keypad-row1-1 { samsung,pins = "gpn-1"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row2_1: keypad-row2-1 { samsung,pins = "gpn-2"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row3_1: keypad-row3-1 { samsung,pins = "gpn-3"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row4_1: keypad-row4-1 { samsung,pins = "gpn-4"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row5_1: keypad-row5-1 { samsung,pins = "gpn-5"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row6_1: keypad-row6-1 { samsung,pins = "gpn-6"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; keypad_row7_1: keypad-row7-1 { samsung,pins = "gpn-7"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; lcd_ctrl: lcd-ctrl { samsung,pins = "gpj-8", "gpj-9", "gpj-10", "gpj-11"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; @@ -651,7 +651,7 @@ "gpi-7", "gpi-10", "gpi-11", "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; @@ -661,7 +661,7 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; @@ -672,14 +672,14 @@ "gpi-12", "gpi-13", "gpi-14", "gpi-15", "gpj-0", "gpj-1", "gpj-2", "gpj-3", "gpj-4", "gpj-5", "gpj-6", "gpj-7"; - samsung,pin-function = <2>; + samsung,pin-function = ; samsung,pin-pud = ; }; hsi_bus: hsi-bus { samsung,pins = "gpk-0", "gpk-1", "gpk-2", "gpk-3", "gpk-4", "gpk-5", "gpk-6", "gpk-7"; - samsung,pin-function = <3>; + samsung,pin-function = ; samsung,pin-pud = ; }; }; -- cgit v1.2.3 From f91f0f246632d2a8ee63dbbffaa5163fb5432c74 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 16 Sep 2016 14:50:11 +0300 Subject: ARM: dts: am335x-evm: Add blue-and-red-wiring -property to lcdc node Add blue-and-red-wiring -property to lcdc node. The am335x-evm has blue and red wires crossed to get 24-bit RGB (and 16-bit BGR) support. After this patch am335x-evm supports BGR565, RGB888, and XRGB8888 color formats. See details in Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt. Signed-off-by: Jyri Sarha Reviewed-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evm.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index 3cf896a2a204..e82432c79f85 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -497,6 +497,8 @@ &lcdc { status = "okay"; + + blue-and-red-wiring = "crossed"; }; &elm { -- cgit v1.2.3 From 5dffb684e090aa83ff054647ab4ba89a81986690 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 16 Sep 2016 14:50:12 +0300 Subject: ARM: dts: am335x-evmsk: Whitespace cleanup of lcdc related nodes Whitespace cleanup of lcdc related nodes. Do all indentation and alignment with tabs instead of spaces. Signed-off-by: Jyri Sarha Reviewed-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 40 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index 0e5e8dcdcc24..ef56b07068b3 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -170,29 +170,29 @@ pinctrl-1 = <&lcd_pins_sleep>; status = "okay"; panel-info { - ac-bias = <255>; - ac-bias-intrpt = <0>; - dma-burst-sz = <16>; - bpp = <32>; - fdd = <0x80>; - sync-edge = <0>; - sync-ctrl = <1>; - raster-order = <0>; - fifo-th = <0>; + ac-bias = <255>; + ac-bias-intrpt = <0>; + dma-burst-sz = <16>; + bpp = <32>; + fdd = <0x80>; + sync-edge = <0>; + sync-ctrl = <1>; + raster-order = <0>; + fifo-th = <0>; }; display-timings { 480x272 { - hactive = <480>; - vactive = <272>; - hback-porch = <43>; - hfront-porch = <8>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; - vsync-len = <10>; + hactive = <480>; + vactive = <272>; + hback-porch = <43>; + hfront-porch = <8>; + hsync-len = <4>; + vback-porch = <12>; + vfront-porch = <4>; + vsync-len = <10>; clock-frequency = <9000000>; - hsync-active = <0>; - vsync-active = <0>; + hsync-active = <0>; + vsync-active = <0>; }; }; }; @@ -711,5 +711,5 @@ }; &lcdc { - status = "okay"; + status = "okay"; }; -- cgit v1.2.3 From 3dc4674a603093ddcd013a54f759d75aa15de032 Mon Sep 17 00:00:00 2001 From: Jyri Sarha Date: Fri, 16 Sep 2016 14:50:13 +0300 Subject: ARM: dts: am335x-evmsk: Add blue-and-red-wiring -property to lcdc node Add blue-and-red-wiring -property to lcdc node. The am335x-evmsk has blue and red wires crossed to get 24-bit RGB (and 16-bit BGR) support. After this patch am335x-evmsk supports BGR565, RGB888, and XRGB8888 color formats. See details in Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt. Signed-off-by: Jyri Sarha Reviewed-by: Tomi Valkeinen Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/am335x-evmsk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts index ef56b07068b3..975c36e332a2 100644 --- a/arch/arm/boot/dts/am335x-evmsk.dts +++ b/arch/arm/boot/dts/am335x-evmsk.dts @@ -712,4 +712,6 @@ &lcdc { status = "okay"; + + blue-and-red-wiring = "crossed"; }; -- cgit v1.2.3 From d6c91b99baeece562ca1aaf26396d32655197477 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 20 Sep 2016 11:37:35 -0700 Subject: ARM: dts: Fix igepv5 power button GPIO direction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It should be GPIO_ACTIVE_LOW instead of GPIO_ACTIVE_HIGH as pointed out by Pau Pajuel . Cc: Agustí Fontquerni i Gorchs Cc: Enric Balletbo Serra Cc: Javier Martinez Canillas Cc: Pau Pajuel Fixes: b118c6a6ffa1 ("ARM: dts: Add power button support for igepv5") Signed-off-by: Tony Lindgren --- arch/arm/boot/dts/omap5-igep0050.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 44e03b9be1f1..1810ae75d73c 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -27,7 +27,7 @@ power-button { label = "Power Button"; linux,code = ; - gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>; + gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; }; }; -- cgit v1.2.3 From ce385a5e7a85c023af2e013101d4fe2240beec21 Mon Sep 17 00:00:00 2001 From: Ladislav Michl Date: Tue, 20 Sep 2016 14:09:03 +0200 Subject: ARM: dts: omap5-igep0050.dts: Use tabs for indentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit And here's another nitpick ;-) Cc: Agustí Fontquerni i Gorchs Cc: Enric Balletbo Serra Cc: Javier Martinez Canillas Cc: Pau Pajuel Fixes: b118c6a6ffa1 ("ARM: dts: Add power button support for igepv5") Signed-off-by: Ladislav Michl --- arch/arm/boot/dts/omap5-igep0050.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/omap5-igep0050.dts b/arch/arm/boot/dts/omap5-igep0050.dts index 1810ae75d73c..8fc19218057e 100644 --- a/arch/arm/boot/dts/omap5-igep0050.dts +++ b/arch/arm/boot/dts/omap5-igep0050.dts @@ -20,7 +20,7 @@ }; gpio_keys { - compatible = "gpio-keys"; + compatible = "gpio-keys"; pinctrl-0 = <&power_button_pin>; pinctrl-names = "default"; -- cgit v1.2.3 From 684da56f7cf08012f23eb57ecd8846cf0f77a93b Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 6 Jul 2016 14:41:39 +0800 Subject: arm: dts: berlin2: enable all wdt nodes unconditionally After commit f29a72c24ad4 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index ae81009741ff..15c857aa796e 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -447,7 +447,6 @@ reg = <0x2000 0x100>; clocks = <&refclk>; interrupts = <1>; - status = "disabled"; }; wdt2: watchdog@3000 { @@ -455,7 +454,6 @@ reg = <0x3000 0x100>; clocks = <&refclk>; interrupts = <2>; - status = "disabled"; }; sm_gpio1: gpio@5000 { -- cgit v1.2.3 From b009cb358e0ea736972e97e3873f26f39a9b9697 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 6 Jul 2016 14:41:40 +0800 Subject: arm: dts: berlin2q: enable all wdt nodes unconditionally After commit f29a72c24ad4 ("watchdog: dw_wdt: Convert to use watchdog infrastructure"), the dw_wdt driver can support multiple variants, so unconditionally enable all dw_wdt nodes now. Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 2c34bfb13632..7e61d04da769 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -525,7 +525,6 @@ reg = <0x2000 0x100>; clocks = <&refclk>; interrupts = <1>; - status = "disabled"; }; wdt2: watchdog@3000 { @@ -533,7 +532,6 @@ reg = <0x3000 0x100>; clocks = <&refclk>; interrupts = <2>; - status = "disabled"; }; sm_gpio1: gpio@5000 { -- cgit v1.2.3 From 2702d6161f5a58e4f7d2478b16c3b4065f744943 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:04 +0800 Subject: ARM: dts: berlin2q: Remove skeleton.dtsi inclusion As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2q. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 7e61d04da769..464a52853cba 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -37,11 +37,11 @@ #include #include -#include "skeleton.dtsi" - / { model = "Marvell Armada 1500 pro (BG2-Q) SoC"; compatible = "marvell,berlin2q", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; -- cgit v1.2.3 From 7283af5f6f70113518882ef31e28189b1380aa73 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:05 +0800 Subject: ARM: dts: berlin2cd: Remove skeleton.dtsi inclusion As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2cd. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index 6d06b6118d83..d2bf390f5d30 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -39,13 +39,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include / { model = "Marvell Armada 1500-mini (BG2CD) SoC"; compatible = "marvell,berlin2cd", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; -- cgit v1.2.3 From 2653c8cbdfbc1d51bdb3d1a0e421c88e32fb18ea Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:06 +0800 Subject: ARM: dts: berlin2: Remove skeleton.dtsi inclusion As noted in [1], "there are a number of problems with skeleton.dtsi, and it would be prefereable to remove it entirely." This patch is to remove skeleton.dtsi inclusion from berlin2. [1] http://www.spinics.net/lists/arm-kernel/msg528080.html Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 15c857aa796e..c57aa2837799 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -39,13 +39,14 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include "skeleton.dtsi" #include #include / { model = "Marvell Armada 1500 (BG2) SoC"; compatible = "marvell,berlin2", "marvell,berlin"; + #address-cells = <1>; + #size-cells = <1>; aliases { serial0 = &uart0; -- cgit v1.2.3 From 32473612f83a1807d26a019a3b0532ce22f81838 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:07 +0800 Subject: ARM: dts: berlin2q: Add missing unit name to /soc node This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 464a52853cba..e548229697fc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -99,7 +99,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 2df5b049688d78358429cf2e167912e1176fb3f2 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:08 +0800 Subject: ARM: dts: berlin2cd: Add missing unit name to /soc node This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index d2bf390f5d30..4fe1574d08c3 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -79,7 +79,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From a6942e9faa8f998d5dc88b062ec0e0ce730f570a Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:09 +0800 Subject: ARM: dts: berlin2: Add missing unit name to /soc node This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index c57aa2837799..425c48971abe 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -90,7 +90,7 @@ clock-frequency = <25000000>; }; - soc { + soc@f7000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From 7d88dd60fe6416d8fedc427b81f2da639ae3f1be Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:10 +0800 Subject: ARM: dts: berlin2q-marvell-dmp: add missing unit name to /memory node This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index 33b28757b8f6..f485308840ab 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -43,7 +43,7 @@ model = "Marvell BG2-Q DMP"; compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin"; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x80000000>; }; -- cgit v1.2.3 From f415c5e3d04ee61ef15d52da952929ed21c2bd7f Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Tue, 6 Sep 2016 16:40:11 +0800 Subject: ARM: dts: chromecast: add missing unit name to /memory node This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2cd-google-chromecast.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts index 8ba8b50ce997..ca24def0ce13 100644 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -50,7 +50,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; -- cgit v1.2.3 From 9a0af838c202572801dc344294eb0a2875f60ab7 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Wed, 28 Sep 2016 21:36:37 +0200 Subject: ARM: dts: sony-nsz-gs7: add missing unit name to /memory node This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts index 3c0907b87fd6..1c475796d17f 100644 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -49,7 +49,7 @@ stdout-path = "serial0:115200n8"; }; - memory { + memory@0 { device_type = "memory"; reg = <0x00000000 0x40000000>; /* 1 GB */ }; -- cgit v1.2.3