From 94da1e2eff319994eefc7d04de7c911f64146e88 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:04:46 +0100 Subject: [WATCHDOG 01/57] Clean acquirewdt and check for BKL dependancies This brings the file into line with coding style. Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/acquirewdt.c | 119 ++++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 61 deletions(-) diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 85269c365a10..269ada2f1fc3 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -58,39 +58,46 @@ #include /* For standard types (like size_t) */ #include /* For the -ENODEV/... values */ #include /* For printk/panic/... */ -#include /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */ +#include /* For MODULE_ALIAS_MISCDEV + (WATCHDOG_MINOR) */ #include /* For the watchdog specific items */ #include /* For file operations */ #include /* For io-port access */ #include /* For platform_driver framework */ #include /* For __init/__exit/... */ -#include /* For copy_to_user/put_user/... */ -#include /* For inb/outb/... */ +#include /* For copy_to_user/put_user/... */ +#include /* For inb/outb/... */ /* Module information */ #define DRV_NAME "acquirewdt" #define PFX DRV_NAME ": " #define WATCHDOG_NAME "Acquire WDT" -#define WATCHDOG_HEARTBEAT 0 /* There is no way to see what the correct time-out period is */ +/* There is no way to see what the correct time-out period is */ +#define WATCHDOG_HEARTBEAT 0 /* internal variables */ -static struct platform_device *acq_platform_device; /* the watchdog platform device */ +/* the watchdog platform device */ +static struct platform_device *acq_platform_device; static unsigned long acq_is_open; static char expect_close; /* module parameters */ -static int wdt_stop = 0x43; /* You must set this - there is no sane way to probe for this board. */ +/* You must set this - there is no sane way to probe for this board. */ +static int wdt_stop = 0x43; module_param(wdt_stop, int, 0); MODULE_PARM_DESC(wdt_stop, "Acquire WDT 'stop' io port (default 0x43)"); -static int wdt_start = 0x443; /* You must set this - there is no sane way to probe for this board. */ +/* You must set this - there is no sane way to probe for this board. */ +static int wdt_start = 0x443; module_param(wdt_start, int, 0); MODULE_PARM_DESC(wdt_start, "Acquire WDT 'start' io port (default 0x443)"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Watchdog Operations @@ -112,18 +119,18 @@ static void acq_stop(void) * /dev/watchdog handling */ -static ssize_t acq_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t acq_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) { + if (count) { if (!nowayout) { size_t i; - /* note: just in case someone wrote the magic character * five months ago... */ expect_close = 0; - - /* scan to see whether or not we got the magic character */ + /* scan to see whether or not we got the + magic character */ for (i = 0; i != count; i++) { char c; if (get_user(c, buf + i)) @@ -132,64 +139,55 @@ static ssize_t acq_write(struct file *file, const char __user *buf, size_t count expect_close = 42; } } - - /* Well, anyhow someone wrote to us, we should return that favour */ + /* Well, anyhow someone wrote to us, we should + return that favour */ acq_keepalive(); } return count; } -static int acq_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int options, retval = -EINVAL; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = - { + static struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = WATCHDOG_NAME, }; - switch(cmd) - { + switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: - return put_user(0, p); + return put_user(0, p); case WDIOC_KEEPALIVE: - acq_keepalive(); - return 0; + acq_keepalive(); + return 0; case WDIOC_GETTIMEOUT: return put_user(WATCHDOG_HEARTBEAT, p); case WDIOC_SETOPTIONS: { - if (get_user(options, p)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) - { - acq_stop(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) - { - acq_keepalive(); - retval = 0; - } - - return retval; + if (get_user(options, p)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + acq_stop(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + acq_keepalive(); + retval = 0; + } + return retval; } - default: - return -ENOTTY; + return -ENOTTY; } } @@ -211,7 +209,8 @@ static int acq_close(struct inode *inode, struct file *file) if (expect_close == 42) { acq_stop(); } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); acq_keepalive(); } clear_bit(0, &acq_is_open); @@ -227,7 +226,7 @@ static const struct file_operations acq_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = acq_write, - .ioctl = acq_ioctl, + .unlocked_ioctl = acq_ioctl, .open = acq_open, .release = acq_close, }; @@ -248,32 +247,29 @@ static int __devinit acq_probe(struct platform_device *dev) if (wdt_stop != wdt_start) { if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", - wdt_stop); + printk(KERN_ERR PFX + "I/O address 0x%04x already in use\n", wdt_stop); ret = -EIO; goto out; } } if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", + printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", wdt_start); ret = -EIO; goto unreg_stop; } - ret = misc_register(&acq_miscdev); if (ret != 0) { - printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto unreg_regions; } - - printk (KERN_INFO PFX "initialized. (nowayout=%d)\n", - nowayout); + printk(KERN_INFO PFX "initialized. (nowayout=%d)\n", nowayout); return 0; - unreg_regions: release_region(wdt_start, 1); unreg_stop: @@ -286,9 +282,9 @@ out: static int __devexit acq_remove(struct platform_device *dev) { misc_deregister(&acq_miscdev); - release_region(wdt_start,1); - if(wdt_stop != wdt_start) - release_region(wdt_stop,1); + release_region(wdt_start, 1); + if (wdt_stop != wdt_start) + release_region(wdt_stop, 1); return 0; } @@ -313,18 +309,19 @@ static int __init acq_init(void) { int err; - printk(KERN_INFO "WDT driver for Acquire single board computer initialising.\n"); + printk(KERN_INFO + "WDT driver for Acquire single board computer initialising.\n"); err = platform_driver_register(&acquirewdt_driver); if (err) return err; - acq_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); + acq_platform_device = platform_device_register_simple(DRV_NAME, + -1, NULL, 0); if (IS_ERR(acq_platform_device)) { err = PTR_ERR(acq_platform_device); goto unreg_platform_driver; } - return 0; unreg_platform_driver: -- cgit v1.2.3 From b6b4d9b8d07e34f745871d3109c84894db29041b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:04:51 +0100 Subject: [WATCHDOG 02/57] clean up and check advantech watchdog Clean up the advantech watchdog code and inspect for BKL problems Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/advantechwdt.c | 135 ++++++++++++++++++---------------------- 1 file changed, 62 insertions(+), 73 deletions(-) diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index 8121cc247343..220d238ee427 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -72,35 +72,35 @@ MODULE_PARM_DESC(wdt_start, "Advantech WDT 'start' io port (default 0x443)"); static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=63, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) "."); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. 1<= timeout <=63, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) "."); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Watchdog Operations */ -static void -advwdt_ping(void) +static void advwdt_ping(void) { /* Write a watchdog value */ outb_p(timeout, wdt_start); } -static void -advwdt_disable(void) +static void advwdt_disable(void) { inb_p(wdt_stop); } -static int -advwdt_set_heartbeat(int t) +static int advwdt_set_heartbeat(int t) { - if ((t < 1) || (t > 63)) + if (t < 1 || t > 63) return -EINVAL; - timeout = t; return 0; } @@ -109,8 +109,8 @@ advwdt_set_heartbeat(int t) * /dev/watchdog handling */ -static ssize_t -advwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t advwdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -131,9 +131,7 @@ advwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *pp return count; } -static int -advwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int new_timeout; void __user *argp = (void __user *)arg; @@ -146,57 +144,50 @@ advwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: - return put_user(0, p); + return put_user(0, p); case WDIOC_KEEPALIVE: - advwdt_ping(); - break; + advwdt_ping(); + break; case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if (advwdt_set_heartbeat(new_timeout)) - return -EINVAL; - advwdt_ping(); - /* Fall */ - + if (get_user(new_timeout, p)) + return -EFAULT; + if (advwdt_set_heartbeat(new_timeout)) + return -EINVAL; + advwdt_ping(); + /* Fall */ case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - + return put_user(timeout, p); case WDIOC_SETOPTIONS: { - int options, retval = -EINVAL; - - if (get_user(options, p)) - return -EFAULT; + int options, retval = -EINVAL; - if (options & WDIOS_DISABLECARD) { - advwdt_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - advwdt_ping(); - retval = 0; - } - - return retval; + if (get_user(options, p)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + advwdt_disable(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + advwdt_ping(); + retval = 0; + } + return retval; } - default: - return -ENOTTY; + return -ENOTTY; } return 0; } -static int -advwdt_open(struct inode *inode, struct file *file) +static int advwdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(0, &advwdt_is_open)) return -EBUSY; @@ -214,7 +205,8 @@ advwdt_close(struct inode *inode, struct file *file) if (adv_expect_close == 42) { advwdt_disable(); } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); advwdt_ping(); } clear_bit(0, &advwdt_is_open); @@ -230,7 +222,7 @@ static const struct file_operations advwdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = advwdt_write, - .ioctl = advwdt_ioctl, + .unlocked_ioctl = advwdt_ioctl, .open = advwdt_open, .release = advwdt_close, }; @@ -245,23 +237,24 @@ static struct miscdevice advwdt_miscdev = { * Init & exit routines */ -static int __devinit -advwdt_probe(struct platform_device *dev) +static int __devinit advwdt_probe(struct platform_device *dev) { int ret; if (wdt_stop != wdt_start) { if (!request_region(wdt_stop, 1, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", - wdt_stop); + printk(KERN_ERR PFX + "I/O address 0x%04x already in use\n", + wdt_stop); ret = -EIO; goto out; } } if (!request_region(wdt_start, 1, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", - wdt_start); + printk(KERN_ERR PFX + "I/O address 0x%04x already in use\n", + wdt_start); ret = -EIO; goto unreg_stop; } @@ -269,20 +262,19 @@ advwdt_probe(struct platform_device *dev) /* Check that the heartbeat value is within it's range ; if not reset to the default */ if (advwdt_set_heartbeat(timeout)) { advwdt_set_heartbeat(WATCHDOG_TIMEOUT); - printk (KERN_INFO PFX "timeout value must be 1<=x<=63, using %d\n", - timeout); + printk(KERN_INFO PFX + "timeout value must be 1<=x<=63, using %d\n", timeout); } ret = misc_register(&advwdt_miscdev); if (ret != 0) { - printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto unreg_regions; } - - printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", + printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); - out: return ret; unreg_regions: @@ -293,8 +285,7 @@ unreg_stop: goto out; } -static int __devexit -advwdt_remove(struct platform_device *dev) +static int __devexit advwdt_remove(struct platform_device *dev) { misc_deregister(&advwdt_miscdev); release_region(wdt_start,1); @@ -304,8 +295,7 @@ advwdt_remove(struct platform_device *dev) return 0; } -static void -advwdt_shutdown(struct platform_device *dev) +static void advwdt_shutdown(struct platform_device *dev) { /* Turn the WDT off if we have a soft shutdown */ advwdt_disable(); @@ -321,8 +311,7 @@ static struct platform_driver advwdt_driver = { }, }; -static int __init -advwdt_init(void) +static int __init advwdt_init(void) { int err; @@ -332,7 +321,8 @@ advwdt_init(void) if (err) return err; - advwdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); + advwdt_platform_device = platform_device_register_simple(DRV_NAME, + -1, NULL, 0); if (IS_ERR(advwdt_platform_device)) { err = PTR_ERR(advwdt_platform_device); goto unreg_platform_driver; @@ -345,8 +335,7 @@ unreg_platform_driver: return err; } -static void __exit -advwdt_exit(void) +static void __exit advwdt_exit(void) { platform_device_unregister(advwdt_platform_device); platform_driver_unregister(&advwdt_driver); -- cgit v1.2.3 From 173d95bc2e68baf73eb89fb9ef1cc63a66f581a5 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:04:57 +0100 Subject: [WATCHDOG 03/57] ali: watchdog locking and style Clean up and check locking Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/alim1535_wdt.c | 186 ++++++++++++++++----------------- drivers/watchdog/alim7101_wdt.c | 224 +++++++++++++++++++++------------------- 2 files changed, 209 insertions(+), 201 deletions(-) diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index 2b1fbdb2fcf7..88760cb5ec13 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c @@ -19,8 +19,8 @@ #include #include -#include -#include +#include +#include #define WATCHDOG_NAME "ALi_M1535" #define PFX WATCHDOG_NAME ": " @@ -30,17 +30,21 @@ static unsigned long ali_is_open; static char ali_expect_release; static struct pci_dev *ali_pci; -static u32 ali_timeout_bits; /* stores the computed timeout */ +static u32 ali_timeout_bits; /* stores the computed timeout */ static DEFINE_SPINLOCK(ali_lock); /* Guards the hardware */ /* module parameters */ static int timeout = WATCHDOG_TIMEOUT; module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (0= 18000) { timeout = WATCHDOG_TIMEOUT; - printk(KERN_INFO PFX "timeout value must be 0 #include -#include -#include +#include +#include #include #define OUR_NAME "alim7101_wdt" @@ -60,13 +60,17 @@ */ #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ -static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +/* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +static int timeout = WATCHDOG_TIMEOUT; module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1<=timeout<=3600, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); -static int use_gpio = 0; /* Use the pic (for a1d revision alim7101) */ +static int use_gpio; /* Use the pic (for a1d revision alim7101) */ module_param(use_gpio, int, 0); -MODULE_PARM_DESC(use_gpio, "Use the gpio watchdog. (required by old cobalt boards)"); +MODULE_PARM_DESC(use_gpio, + "Use the gpio watchdog (required by old cobalt boards)."); static void wdt_timer_ping(unsigned long); static DEFINE_TIMER(timer, wdt_timer_ping, 0, 1); @@ -77,8 +81,9 @@ static struct pci_dev *alim7101_pmu; static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" - __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Whack the dog @@ -89,23 +94,26 @@ static void wdt_timer_ping(unsigned long data) /* If we got a heartbeat pulse within the WDT_US_INTERVAL * we agree to ping the WDT */ - char tmp; + char tmp; - if(time_before(jiffies, next_heartbeat)) - { + if (time_before(jiffies, next_heartbeat)) { /* Ping the WDT (this is actually a disarm/arm sequence) */ pci_read_config_byte(alim7101_pmu, 0x92, &tmp); - pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); - pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp | ALI_WDT_ARM)); + pci_write_config_byte(alim7101_pmu, + ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); + pci_write_config_byte(alim7101_pmu, + ALI_7101_WDT, (tmp | ALI_WDT_ARM)); if (use_gpio) { - pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); - pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp - | 0x20); - pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp - & ~0x20); + pci_read_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, &tmp); + pci_write_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, tmp | 0x20); + pci_write_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, tmp & ~0x20); } } else { - printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); + printk(KERN_WARNING PFX + "Heartbeat lost! Will not ping the watchdog\n"); } /* Re-set the timer interval */ mod_timer(&timer, jiffies + WDT_INTERVAL); @@ -121,17 +129,23 @@ static void wdt_change(int writeval) pci_read_config_byte(alim7101_pmu, ALI_7101_WDT, &tmp); if (writeval == WDT_ENABLE) { - pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp | ALI_WDT_ARM)); + pci_write_config_byte(alim7101_pmu, + ALI_7101_WDT, (tmp | ALI_WDT_ARM)); if (use_gpio) { - pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); - pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp & ~0x20); + pci_read_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, &tmp); + pci_write_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, tmp & ~0x20); } } else { - pci_write_config_byte(alim7101_pmu, ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); + pci_write_config_byte(alim7101_pmu, + ALI_7101_WDT, (tmp & ~ALI_WDT_ARM)); if (use_gpio) { - pci_read_config_byte(alim7101_pmu, ALI_7101_GPIO_O, &tmp); - pci_write_config_byte(alim7101_pmu, ALI_7101_GPIO_O, tmp | 0x20); + pci_read_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, &tmp); + pci_write_config_byte(alim7101_pmu, + ALI_7101_GPIO_O, tmp | 0x20); } } } @@ -169,10 +183,11 @@ static void wdt_keepalive(void) * /dev/watchdog handling */ -static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) +static ssize_t fop_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) { + if (count) { if (!nowayout) { size_t ofs; @@ -195,119 +210,116 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou return count; } -static int fop_open(struct inode * inode, struct file * file) +static int fop_open(struct inode *inode, struct file *file) { /* Just in case we're already talking to someone... */ - if(test_and_set_bit(0, &wdt_is_open)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; /* Good, fire up the show */ wdt_startup(); return nonseekable_open(inode, file); } -static int fop_close(struct inode * inode, struct file * file) +static int fop_close(struct inode *inode, struct file *file) { - if(wdt_expect_close == 42) + if (wdt_expect_close == 42) wdt_turnoff(); else { /* wim: shouldn't there be a: del_timer(&timer); */ - printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); + printk(KERN_CRIT PFX + "device file closed unexpectedly. Will not stop the WDT!\n"); } clear_bit(0, &wdt_is_open); wdt_expect_close = 0; return 0; } -static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = - { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "ALiM7101", }; - switch(cmd) + switch (cmd) { + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETOPTIONS: { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; - - if(get_user(new_options, p)) - return -EFAULT; - - if(new_options & WDIOS_DISABLECARD) { - wdt_turnoff(); - retval = 0; - } - - if(new_options & WDIOS_ENABLECARD) { - wdt_startup(); - retval = 0; - } + int new_options, retval = -EINVAL; - return retval; + if (get_user(new_options, p)) + return -EFAULT; + if (new_options & WDIOS_DISABLECARD) { + wdt_turnoff(); + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_timeout; - - if(get_user(new_timeout, p)) - return -EFAULT; - - if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ - return -EINVAL; - - timeout = new_timeout; - wdt_keepalive(); - /* Fall through */ + if (new_options & WDIOS_ENABLECARD) { + wdt_startup(); + retval = 0; } - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - default: - return -ENOTTY; + return retval; + } + case WDIOC_SETTIMEOUT: + { + int new_timeout; + + if (get_user(new_timeout, p)) + return -EFAULT; + /* arbitrary upper limit */ + if (new_timeout < 1 || new_timeout > 3600) + return -EINVAL; + timeout = new_timeout; + wdt_keepalive(); + /* Fall through */ + } + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); + default: + return -ENOTTY; } } static const struct file_operations wdt_fops = { - .owner= THIS_MODULE, - .llseek= no_llseek, - .write= fop_write, - .open= fop_open, - .release= fop_close, - .ioctl= fop_ioctl, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = fop_write, + .open = fop_open, + .release = fop_close, + .unlocked_ioctl = fop_ioctl, }; static struct miscdevice wdt_miscdev = { - .minor=WATCHDOG_MINOR, - .name="watchdog", - .fops=&wdt_fops, + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &wdt_fops, }; /* * Notifier for system down */ -static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) +static int wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) { - if (code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt_turnoff(); - if (code==SYS_RESTART) { + if (code == SYS_RESTART) { /* - * Cobalt devices have no way of rebooting themselves other than - * getting the watchdog to pull reset, so we restart the watchdog on - * reboot with no heartbeat + * Cobalt devices have no way of rebooting themselves other + * than getting the watchdog to pull reset, so we restart the + * watchdog on reboot with no heartbeat */ wdt_change(WDT_ENABLE); printk(KERN_INFO PFX "Watchdog timer is now enabled with no heartbeat - should reboot in ~1 second.\n"); @@ -320,8 +332,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void * turn the timebomb registers off. */ -static struct notifier_block wdt_notifier= -{ +static struct notifier_block wdt_notifier = { .notifier_call = wdt_notify_sys, }; @@ -354,7 +365,8 @@ static int __init alim7101_wdt_init(void) ali1543_south = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL); if (!ali1543_south) { - printk(KERN_INFO PFX "ALi 1543 South-Bridge not present - WDT not set\n"); + printk(KERN_INFO PFX + "ALi 1543 South-Bridge not present - WDT not set\n"); goto err_out; } pci_read_config_byte(ali1543_south, 0x5e, &tmp); @@ -363,24 +375,25 @@ static int __init alim7101_wdt_init(void) if (!use_gpio) { printk(KERN_INFO PFX "Detected old alim7101 revision 'a1d'. If this is a cobalt board, set the 'use_gpio' module parameter.\n"); goto err_out; - } + } nowayout = 1; } else if ((tmp & 0x1e) != 0x12 && (tmp & 0x1e) != 0x00) { printk(KERN_INFO PFX "ALi 1543 South-Bridge does not have the correct revision number (???1001?) - WDT not set\n"); goto err_out; } - if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ - { + if (timeout < 1 || timeout > 3600) { + /* arbitrary upper limit */ timeout = WATCHDOG_TIMEOUT; - printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", - timeout); + printk(KERN_INFO PFX + "timeout value must be 1 <= x <= 3600, using %d\n", + timeout); } rc = register_reboot_notifier(&wdt_notifier); if (rc) { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - rc); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", rc); goto err_out; } @@ -391,9 +404,8 @@ static int __init alim7101_wdt_init(void) goto err_out_reboot; } - if (nowayout) { + if (nowayout) __module_get(THIS_MODULE); - } printk(KERN_INFO PFX "WDT driver for ALi M7101 initialised. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); -- cgit v1.2.3 From fbd4714907cd54ba74b8d35228813a060ae0176a Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:07 +0100 Subject: [WATCHDOG 04/57] AR7 watchdog Fix locking Use unlocked_ioctl Remove semaphores Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ar7_wdt.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index 2eb48c0df32c..ef7b0d67095e 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -69,7 +69,8 @@ struct ar7_wdt { u32 prescale; }; -static struct semaphore open_semaphore; +static unsigned long wdt_is_open; +static spinlock_t wdt_lock; static unsigned expect_close; /* XXX currently fixed, allows max margin ~68.72 secs */ @@ -154,8 +155,10 @@ static void ar7_wdt_update_margin(int new_margin) u32 change; change = new_margin * (ar7_vbus_freq() / prescale_value); - if (change < 1) change = 1; - if (change > 0xffff) change = 0xffff; + if (change < 1) + change = 1; + if (change > 0xffff) + change = 0xffff; ar7_wdt_change(change); margin = change * prescale_value / ar7_vbus_freq(); printk(KERN_INFO DRVNAME @@ -179,7 +182,7 @@ static void ar7_wdt_disable_wdt(void) static int ar7_wdt_open(struct inode *inode, struct file *file) { /* only allow one at a time */ - if (down_trylock(&open_semaphore)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; ar7_wdt_enable_wdt(); expect_close = 0; @@ -195,9 +198,7 @@ static int ar7_wdt_release(struct inode *inode, struct file *file) "will not disable the watchdog timer\n"); else if (!nowayout) ar7_wdt_disable_wdt(); - - up(&open_semaphore); - + clear_bit(0, &wdt_is_open); return 0; } @@ -222,7 +223,9 @@ static ssize_t ar7_wdt_write(struct file *file, const char *data, if (len) { size_t i; + spin_lock(&wdt_lock); ar7_wdt_kick(1); + spin_unlock(&wdt_lock); expect_close = 0; for (i = 0; i < len; ++i) { @@ -237,8 +240,8 @@ static ssize_t ar7_wdt_write(struct file *file, const char *data, return len; } -static int ar7_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long ar7_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { static struct watchdog_info ident = { .identity = LONGNAME, @@ -269,8 +272,10 @@ static int ar7_wdt_ioctl(struct inode *inode, struct file *file, if (new_margin < 1) return -EINVAL; + spin_lock(&wdt_lock); ar7_wdt_update_margin(new_margin); ar7_wdt_kick(1); + spin_unlock(&wdt_lock); case WDIOC_GETTIMEOUT: if (put_user(margin, (int *)arg)) @@ -282,7 +287,7 @@ static int ar7_wdt_ioctl(struct inode *inode, struct file *file, static const struct file_operations ar7_wdt_fops = { .owner = THIS_MODULE, .write = ar7_wdt_write, - .ioctl = ar7_wdt_ioctl, + .unlocked_ioctl = ar7_wdt_ioctl, .open = ar7_wdt_open, .release = ar7_wdt_release, }; @@ -297,6 +302,8 @@ static int __init ar7_wdt_init(void) { int rc; + spin_lock_init(&wdt_lock); + ar7_wdt_get_regs(); if (!request_mem_region(ar7_regs_wdt, sizeof(struct ar7_wdt), @@ -312,8 +319,6 @@ static int __init ar7_wdt_init(void) ar7_wdt_prescale(prescale_value); ar7_wdt_update_margin(margin); - sema_init(&open_semaphore, 1); - rc = register_reboot_notifier(&ar7_wdt_notifier); if (rc) { printk(KERN_ERR DRVNAME -- cgit v1.2.3 From a6be8e5ff95e12190fd5e5158eb553255677292f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:13 +0100 Subject: [WATCHDOG 05/57] atp watchdog Switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/at32ap700x_wdt.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c index ae0fca5e8749..c5dc5e912fb2 100644 --- a/drivers/watchdog/at32ap700x_wdt.c +++ b/drivers/watchdog/at32ap700x_wdt.c @@ -212,8 +212,8 @@ static struct watchdog_info at32_wdt_info = { /* * Handle commands from user-space. */ -static int at32_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long at32_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int ret = -ENOTTY; int time; @@ -298,7 +298,7 @@ static ssize_t at32_wdt_write(struct file *file, const char __user *data, static const struct file_operations at32_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = at32_wdt_ioctl, + .unlocked_ioctl = at32_wdt_ioctl, .open = at32_wdt_open, .release = at32_wdt_close, .write = at32_wdt_write, @@ -391,7 +391,6 @@ static int __exit at32_wdt_remove(struct platform_device *pdev) wdt = NULL; platform_set_drvdata(pdev, NULL); } - return 0; } -- cgit v1.2.3 From 2760600da2a13d5a2a335ba012d0f3ad5df4c098 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:19 +0100 Subject: [WATCHDOG 06/57] at91: watchdog to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/at91rm9200_wdt.c | 108 +++++++++++++++++++------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/drivers/watchdog/at91rm9200_wdt.c b/drivers/watchdog/at91rm9200_wdt.c index 9ff9a9565320..bb79f649dc7e 100644 --- a/drivers/watchdog/at91rm9200_wdt.c +++ b/drivers/watchdog/at91rm9200_wdt.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include @@ -31,11 +31,14 @@ static int wdt_time = WDT_DEFAULT_TIME; static int nowayout = WATCHDOG_NOWAYOUT; module_param(wdt_time, int, 0); -MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="__MODULE_STRING(WDT_DEFAULT_TIME) ")"); +MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" + __MODULE_STRING(WDT_DEFAULT_TIME) ")"); #ifdef CONFIG_WATCHDOG_NOWAYOUT module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); #endif @@ -46,7 +49,7 @@ static unsigned long at91wdt_busy; /* * Disable the watchdog. */ -static void inline at91_wdt_stop(void) +static inline void at91_wdt_stop(void) { at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN); } @@ -54,16 +57,17 @@ static void inline at91_wdt_stop(void) /* * Enable and reset the watchdog. */ -static void inline at91_wdt_start(void) +static inline void at91_wdt_start(void) { - at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN | (((65536 * wdt_time) >> 8) & AT91_ST_WDV)); + at91_sys_write(AT91_ST_WDMR, AT91_ST_EXTEN | AT91_ST_RSTEN | + (((65536 * wdt_time) >> 8) & AT91_ST_WDV)); at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); } /* * Reload the watchdog timer. (ie, pat the watchdog) */ -static void inline at91_wdt_reload(void) +static inline void at91_wdt_reload(void) { at91_sys_write(AT91_ST_CR, AT91_ST_WDRST); } @@ -89,8 +93,9 @@ static int at91_wdt_open(struct inode *inode, struct file *file) */ static int at91_wdt_close(struct inode *inode, struct file *file) { + /* Disable the watchdog when file is closed */ if (!nowayout) - at91_wdt_stop(); /* Disable the watchdog when file is closed */ + at91_wdt_stop(); clear_bit(0, &at91wdt_busy); return 0; @@ -110,7 +115,8 @@ static int at91_wdt_settimeout(int new_time) if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) return -EINVAL; - /* Set new watchdog time. It will be used when at91_wdt_start() is called. */ + /* Set new watchdog time. It will be used when + at91_wdt_start() is called. */ wdt_time = new_time; return 0; } @@ -123,60 +129,52 @@ static struct watchdog_info at91_wdt_info = { /* * Handle commands from user-space. */ -static int at91_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long at91_wdt_ioct(struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_value; - switch(cmd) { - case WDIOC_KEEPALIVE: - at91_wdt_reload(); /* pat the watchdog */ - return 0; - - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &at91_wdt_info, sizeof(at91_wdt_info)) ? -EFAULT : 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - - if (at91_wdt_settimeout(new_value)) - return -EINVAL; - - /* Enable new time value */ + switch (cmd) { + case WDIOC_KEEPALIVE: + at91_wdt_reload(); /* pat the watchdog */ + return 0; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &at91_wdt_info, + sizeof(at91_wdt_info)) ? -EFAULT : 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_value, p)) + return -EFAULT; + if (at91_wdt_settimeout(new_value)) + return -EINVAL; + /* Enable new time value */ + at91_wdt_start(); + /* Return current value */ + return put_user(wdt_time, p); + case WDIOC_GETTIMEOUT: + return put_user(wdt_time, p); + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_SETOPTIONS: + if (get_user(new_value, p)) + return -EFAULT; + if (new_value & WDIOS_DISABLECARD) + at91_wdt_stop(); + if (new_value & WDIOS_ENABLECARD) at91_wdt_start(); - - /* Return current value */ - return put_user(wdt_time, p); - - case WDIOC_GETTIMEOUT: - return put_user(wdt_time, p); - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - - case WDIOC_SETOPTIONS: - if (get_user(new_value, p)) - return -EFAULT; - - if (new_value & WDIOS_DISABLECARD) - at91_wdt_stop(); - if (new_value & WDIOS_ENABLECARD) - at91_wdt_start(); - return 0; - - default: - return -ENOTTY; + return 0; + default: + return -ENOTTY; } } /* * Pat the watchdog whenever device is written to. */ -static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t at91_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { at91_wdt_reload(); /* pat the watchdog */ return len; @@ -187,7 +185,7 @@ static ssize_t at91_wdt_write(struct file *file, const char *data, size_t len, l static const struct file_operations at91wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = at91_wdt_ioctl, + .unlocked_ioctl = at91_wdt_ioctl, .open = at91_wdt_open, .release = at91_wdt_close, .write = at91_wdt_write, @@ -211,7 +209,8 @@ static int __init at91wdt_probe(struct platform_device *pdev) if (res) return res; - printk("AT91 Watchdog Timer enabled (%d seconds%s)\n", wdt_time, nowayout ? ", nowayout" : ""); + printk(KERN_INFO "AT91 Watchdog Timer enabled (%d seconds%s)\n", + wdt_time, nowayout ? ", nowayout" : ""); return 0; } @@ -265,7 +264,8 @@ static struct platform_driver at91wdt_driver = { static int __init at91_wdt_init(void) { - /* Check that the heartbeat value is within range; if not reset to the default */ + /* Check that the heartbeat value is within range; + if not reset to the default */ if (at91_wdt_settimeout(wdt_time)) { at91_wdt_settimeout(WDT_DEFAULT_TIME); pr_info("at91_wdt: wdt_time value must be 1 <= wdt_time <= 256, using %d\n", wdt_time); -- cgit v1.2.3 From 6f932f18de7f0e22a1bdae5d0040eb5d8e4a6777 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:24 +0100 Subject: [WATCHDOG 07/57] cpu5_wdt: switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/cpu5wdt.c | 144 ++++++++++++++++++++++----------------------- 1 file changed, 70 insertions(+), 74 deletions(-) diff --git a/drivers/watchdog/cpu5wdt.c b/drivers/watchdog/cpu5wdt.c index df72f90123df..ec324e5e1c99 100644 --- a/drivers/watchdog/cpu5wdt.c +++ b/drivers/watchdog/cpu5wdt.c @@ -30,16 +30,16 @@ #include #include #include -#include -#include - +#include +#include #include /* adjustable parameters */ -static int verbose = 0; +static int verbose; static int port = 0x91; static int ticks = 10000; +static spinlock_t cpu5wdt_lock; #define PFX "cpu5wdt: " @@ -70,12 +70,13 @@ static struct { static void cpu5wdt_trigger(unsigned long unused) { - if ( verbose > 2 ) + if (verbose > 2) printk(KERN_DEBUG PFX "trigger at %i ticks\n", ticks); - if( cpu5wdt_device.running ) + if (cpu5wdt_device.running) ticks--; + spin_lock(&cpu5wdt_lock); /* keep watchdog alive */ outb(1, port + CPU5WDT_TRIGGER_REG); @@ -86,6 +87,7 @@ static void cpu5wdt_trigger(unsigned long unused) /* ticks doesn't matter anyway */ complete(&cpu5wdt_device.stop); } + spin_unlock(&cpu5wdt_lock); } @@ -93,14 +95,17 @@ static void cpu5wdt_reset(void) { ticks = cpu5wdt_device.default_ticks; - if ( verbose ) + if (verbose) printk(KERN_DEBUG PFX "reset (%i ticks)\n", (int) ticks); } static void cpu5wdt_start(void) { - if ( !cpu5wdt_device.queue ) { + unsigned long flags; + + spin_lock_irqsave(&cpu5wdt_lock, flags); + if (!cpu5wdt_device.queue) { cpu5wdt_device.queue = 1; outb(0, port + CPU5WDT_TIME_A_REG); outb(0, port + CPU5WDT_TIME_B_REG); @@ -111,18 +116,20 @@ static void cpu5wdt_start(void) } /* if process dies, counter is not decremented */ cpu5wdt_device.running++; + spin_unlock_irqrestore(&cpu5wdt_lock, flags); } static int cpu5wdt_stop(void) { - if ( cpu5wdt_device.running ) - cpu5wdt_device.running = 0; + unsigned long flags; + spin_lock_irqsave(&cpu5wdt_lock, flags); + if (cpu5wdt_device.running) + cpu5wdt_device.running = 0; ticks = cpu5wdt_device.default_ticks; - - if ( verbose ) + spin_unlock_irqrestore(&cpu5wdt_lock, flags); + if (verbose) printk(KERN_CRIT PFX "stop not possible\n"); - return -EIO; } @@ -130,9 +137,8 @@ static int cpu5wdt_stop(void) static int cpu5wdt_open(struct inode *inode, struct file *file) { - if ( test_and_set_bit(0, &cpu5wdt_device.inuse) ) + if (test_and_set_bit(0, &cpu5wdt_device.inuse)) return -EBUSY; - return nonseekable_open(inode, file); } @@ -142,67 +148,58 @@ static int cpu5wdt_release(struct inode *inode, struct file *file) return 0; } -static int cpu5wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; + int __user *p = argp; unsigned int value; - static struct watchdog_info ident = - { + static struct watchdog_info ident = { .options = WDIOF_CARDRESET, .identity = "CPU5 WDT", }; - switch(cmd) { - case WDIOC_KEEPALIVE: - cpu5wdt_reset(); - break; - case WDIOC_GETSTATUS: - value = inb(port + CPU5WDT_STATUS_REG); - value = (value >> 2) & 1; - if ( copy_to_user(argp, &value, sizeof(int)) ) - return -EFAULT; - break; - case WDIOC_GETBOOTSTATUS: - if ( copy_to_user(argp, &value, sizeof(int)) ) - return -EFAULT; - break; - case WDIOC_GETSUPPORT: - if ( copy_to_user(argp, &ident, sizeof(ident)) ) - return -EFAULT; - break; - case WDIOC_SETOPTIONS: - if ( copy_from_user(&value, argp, sizeof(int)) ) - return -EFAULT; - switch(value) { - case WDIOS_ENABLECARD: - cpu5wdt_start(); - break; - case WDIOS_DISABLECARD: - return cpu5wdt_stop(); - default: - return -EINVAL; - } - break; - default: - return -ENOTTY; + switch (cmd) { + case WDIOC_KEEPALIVE: + cpu5wdt_reset(); + break; + case WDIOC_GETSTATUS: + value = inb(port + CPU5WDT_STATUS_REG); + value = (value >> 2) & 1; + return put_user(value, p); + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; + case WDIOC_SETOPTIONS: + if (get_user(value, p)) + return -EFAULT; + if (value & WDIOS_ENABLECARD) + cpu5wdt_start(); + if (value & WDIOS_DISABLECARD) + cpu5wdt_stop(); + break; + default: + return -ENOTTY; } return 0; } -static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { - if ( !count ) + if (!count) return -EIO; - cpu5wdt_reset(); - return count; } static const struct file_operations cpu5wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = cpu5wdt_ioctl, + .unlocked_ioctl = cpu5wdt_ioctl, .open = cpu5wdt_open, .write = cpu5wdt_write, .release = cpu5wdt_release, @@ -221,37 +218,36 @@ static int __devinit cpu5wdt_init(void) unsigned int val; int err; - if ( verbose ) - printk(KERN_DEBUG PFX "port=0x%x, verbose=%i\n", port, verbose); + if (verbose) + printk(KERN_DEBUG PFX + "port=0x%x, verbose=%i\n", port, verbose); - if ( !request_region(port, CPU5WDT_EXTENT, PFX) ) { + init_completion(&cpu5wdt_device.stop); + spin_lock_init(&cpu5wdt_lock); + cpu5wdt_device.queue = 0; + setup_timer(&cpu5wdt_device.timer, cpu5wdt_trigger, 0); + cpu5wdt_device.default_ticks = ticks; + + if (!request_region(port, CPU5WDT_EXTENT, PFX)) { printk(KERN_ERR PFX "request_region failed\n"); err = -EBUSY; goto no_port; } - if ( (err = misc_register(&cpu5wdt_misc)) < 0 ) { - printk(KERN_ERR PFX "misc_register failed\n"); - goto no_misc; - } - /* watchdog reboot? */ val = inb(port + CPU5WDT_STATUS_REG); val = (val >> 2) & 1; - if ( !val ) + if (!val) printk(KERN_INFO PFX "sorry, was my fault\n"); - init_completion(&cpu5wdt_device.stop); - cpu5wdt_device.queue = 0; - - clear_bit(0, &cpu5wdt_device.inuse); - - setup_timer(&cpu5wdt_device.timer, cpu5wdt_trigger, 0); + err = misc_register(&cpu5wdt_misc); + if (err < 0) { + printk(KERN_ERR PFX "misc_register failed\n"); + goto no_misc; + } - cpu5wdt_device.default_ticks = ticks; printk(KERN_INFO PFX "init success\n"); - return 0; no_misc: @@ -267,7 +263,7 @@ static int __devinit cpu5wdt_init_module(void) static void __devexit cpu5wdt_exit(void) { - if ( cpu5wdt_device.queue ) { + if (cpu5wdt_device.queue) { cpu5wdt_device.queue = 0; wait_for_completion(&cpu5wdt_device.stop); } -- cgit v1.2.3 From f78b0a8f27618b492dd2e1a8f5e4ce6f89b3c961 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:30 +0100 Subject: [WATCHDOG 08/57] davinci_wdt: unlocked_ioctl and check locking Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/davinci_wdt.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 1782c79eff06..926b59c41186 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -22,10 +22,10 @@ #include #include #include +#include +#include #include -#include -#include #define MODULE_NAME "DAVINCI-WDT: " @@ -143,9 +143,8 @@ static struct watchdog_info ident = { .identity = "DaVinci Watchdog", }; -static int -davinci_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long davinci_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int ret = -ENOTTY; @@ -184,7 +183,7 @@ static const struct file_operations davinci_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = davinci_wdt_write, - .ioctl = davinci_wdt_ioctl, + .unlocked_ioctl = davinci_wdt_ioctl, .open = davinci_wdt_open, .release = davinci_wdt_release, }; -- cgit v1.2.3 From f339e2ac9d65656e6d18c92b1ddc4a7801373318 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:35 +0100 Subject: [WATCHDOG 09/57] ep93xx_wdt: unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ep93xx_wdt.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index 0e4787a0bb87..cdcdd11173a7 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -28,9 +28,9 @@ #include #include #include +#include #include -#include #define WDT_VERSION "0.3" #define PFX "ep93xx_wdt: " @@ -136,9 +136,8 @@ static struct watchdog_info ident = { .identity = "EP93xx Watchdog", }; -static int -ep93xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long ep93xx_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int ret = -ENOTTY; @@ -174,8 +173,8 @@ static int ep93xx_wdt_release(struct inode *inode, struct file *file) if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) wdt_shutdown(); else - printk(KERN_CRIT PFX "Device closed unexpectedly - " - "timer will not stop\n"); + printk(KERN_CRIT PFX + "Device closed unexpectedly - timer will not stop\n"); clear_bit(WDT_IN_USE, &wdt_status); clear_bit(WDT_OK_TO_CLOSE, &wdt_status); @@ -186,7 +185,7 @@ static int ep93xx_wdt_release(struct inode *inode, struct file *file) static const struct file_operations ep93xx_wdt_fops = { .owner = THIS_MODULE, .write = ep93xx_wdt_write, - .ioctl = ep93xx_wdt_ioctl, + .unlocked_ioctl = ep93xx_wdt_ioctl, .open = ep93xx_wdt_open, .release = ep93xx_wdt_release, }; @@ -243,7 +242,9 @@ module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started"); module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1<=timeout<=3600, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); MODULE_AUTHOR("Ray Lehtiniemi ," "Alessandro Zummo "); -- cgit v1.2.3 From 89ea2429873e69201173f3606ab04d751f737cc4 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:41 +0100 Subject: [WATCHDOG 10/57] eurotechwdt: unlocked_ioctl, code lock check and tidy Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/eurotechwdt.c | 57 ++++++++++++++++++++++++++---------------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index b14e9d1f164d..b94e6ef4c7a7 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c @@ -56,14 +56,15 @@ #include #include #include +#include +#include -#include -#include #include static unsigned long eurwdt_is_open; static int eurwdt_timeout; static char eur_expect_close; +static spinlock_t eurwdt_lock; /* * You must set these - there is no sane way to probe for this board. @@ -78,7 +79,9 @@ static char *ev = "int"; static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Some symbolic names @@ -137,7 +140,8 @@ static void eurwdt_activate_timer(void) { eurwdt_disable_timer(); eurwdt_write_reg(WDT_CTRL_REG, 0x01); /* activate the WDT */ - eurwdt_write_reg(WDT_OUTPIN_CFG, !strcmp("int", ev) ? WDT_EVENT_INT : WDT_EVENT_REBOOT); + eurwdt_write_reg(WDT_OUTPIN_CFG, + !strcmp("int", ev) ? WDT_EVENT_INT : WDT_EVENT_REBOOT); /* Setting interrupt line */ if (irq == 2 || irq > 15 || irq < 0) { @@ -206,21 +210,21 @@ size_t count, loff_t *ppos) for (i = 0; i != count; i++) { char c; - if(get_user(c, buf+i)) + if (get_user(c, buf+i)) return -EFAULT; if (c == 'V') eur_expect_close = 42; } } + spin_lock(&eurwdt_lock); eurwdt_ping(); /* the default timeout */ + spin_unlock(&eurwdt_lock); } - return count; } /** * eurwdt_ioctl: - * @inode: inode of the device * @file: file handle to the device * @cmd: watchdog command * @arg: argument pointer @@ -229,13 +233,14 @@ size_t count, loff_t *ppos) * according to their available features. */ -static int eurwdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long eurwdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "WDT Eurotech CPU-1220/1410", }; @@ -243,7 +248,7 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, int time; int options, retval = -EINVAL; - switch(cmd) { + switch (cmd) { default: return -ENOTTY; @@ -255,7 +260,9 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, return put_user(0, p); case WDIOC_KEEPALIVE: + spin_lock(&eurwdt_lock); eurwdt_ping(); + spin_unlock(&eurwdt_lock); return 0; case WDIOC_SETTIMEOUT: @@ -266,8 +273,10 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, if (time < 0 || time > 255) return -EINVAL; + spin_lock(&eurwdt_lock); eurwdt_timeout = time; eurwdt_set_timeout(time); + spin_unlock(&eurwdt_lock); /* Fall */ case WDIOC_GETTIMEOUT: @@ -276,6 +285,7 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, case WDIOC_SETOPTIONS: if (get_user(options, p)) return -EFAULT; + spin_lock(&eurwdt_lock); if (options & WDIOS_DISABLECARD) { eurwdt_disable_timer(); retval = 0; @@ -285,6 +295,7 @@ static int eurwdt_ioctl(struct inode *inode, struct file *file, eurwdt_ping(); retval = 0; } + spin_unlock(&eurwdt_lock); return retval; } } @@ -322,10 +333,11 @@ static int eurwdt_open(struct inode *inode, struct file *file) static int eurwdt_release(struct inode *inode, struct file *file) { - if (eur_expect_close == 42) { + if (eur_expect_close == 42) eurwdt_disable_timer(); - } else { - printk(KERN_CRIT "eurwdt: Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT + "eurwdt: Unexpected close, not stopping watchdog!\n"); eurwdt_ping(); } clear_bit(0, &eurwdt_is_open); @@ -362,11 +374,11 @@ static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code, static const struct file_operations eurwdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = eurwdt_write, - .ioctl = eurwdt_ioctl, - .open = eurwdt_open, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = eurwdt_write, + .unlocked_ioctl = eurwdt_ioctl, + .open = eurwdt_open, .release = eurwdt_release, }; @@ -419,7 +431,7 @@ static int __init eurwdt_init(void) int ret; ret = request_irq(irq, eurwdt_interrupt, IRQF_DISABLED, "eurwdt", NULL); - if(ret) { + if (ret) { printk(KERN_ERR "eurwdt: IRQ %d is not free.\n", irq); goto out; } @@ -432,10 +444,13 @@ static int __init eurwdt_init(void) ret = register_reboot_notifier(&eurwdt_notifier); if (ret) { - printk(KERN_ERR "eurwdt: can't register reboot notifier (err=%d)\n", ret); + printk(KERN_ERR + "eurwdt: can't register reboot notifier (err=%d)\n", ret); goto outreg; } + spin_lock_init(&eurwdt_lock); + ret = misc_register(&eurwdt_miscdev); if (ret) { printk(KERN_ERR "eurwdt: can't misc_register on minor=%d\n", -- cgit v1.2.3 From 6513e2a03887c6c9bd0b30593827a01ce3f7b542 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:46 +0100 Subject: [WATCHDOG 11/57] hpwdt: couple of include cleanups clean-up includes Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/hpwdt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index 6a63535fc04d..45bf66c72457 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -39,9 +39,9 @@ #include #include #include -#include +#include #include -#include +#include #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 -- cgit v1.2.3 From 2e43ba73d4e2d34ddb9843e30480be3752514c16 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:52 +0100 Subject: [WATCHDOG 12/57] ib700wdt: clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ib700wdt.c | 103 ++++++++++++++++++++++---------------------- 1 file changed, 52 insertions(+), 51 deletions(-) diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 4b89f401691a..805a54b02aa1 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -42,8 +42,8 @@ #include #include -#include -#include +#include +#include #include static struct platform_device *ibwdt_platform_device; @@ -120,7 +120,9 @@ static int wd_margin = WD_TIMO; static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* @@ -165,8 +167,8 @@ ibwdt_set_heartbeat(int t) * /dev/watchdog handling */ -static ssize_t -ibwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t ibwdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -188,77 +190,71 @@ ibwdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppo return count; } -static int -ibwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long ibwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int new_margin; void __user *argp = (void __user *)arg; int __user *p = argp; static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "IB700 WDT", }; switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: - return put_user(0, p); + return put_user(0, p); case WDIOC_KEEPALIVE: - ibwdt_ping(); - break; + ibwdt_ping(); + break; case WDIOC_SETTIMEOUT: - if (get_user(new_margin, p)) - return -EFAULT; - if (ibwdt_set_heartbeat(new_margin)) - return -EINVAL; - ibwdt_ping(); - /* Fall */ + if (get_user(new_margin, p)) + return -EFAULT; + if (ibwdt_set_heartbeat(new_margin)) + return -EINVAL; + ibwdt_ping(); + /* Fall */ case WDIOC_GETTIMEOUT: - return put_user(wd_times[wd_margin], p); + return put_user(wd_times[wd_margin], p); case WDIOC_SETOPTIONS: { - int options, retval = -EINVAL; + int options, retval = -EINVAL; - if (get_user(options, p)) - return -EFAULT; + if (get_user(options, p)) + return -EFAULT; - if (options & WDIOS_DISABLECARD) { - ibwdt_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - ibwdt_ping(); - retval = 0; - } - - return retval; + if (options & WDIOS_DISABLECARD) { + ibwdt_disable(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + ibwdt_ping(); + retval = 0; + } + return retval; } - default: - return -ENOTTY; + return -ENOTTY; } return 0; } -static int -ibwdt_open(struct inode *inode, struct file *file) +static int ibwdt_open(struct inode *inode, struct file *file) { - if (test_and_set_bit(0, &ibwdt_is_open)) { + if (test_and_set_bit(0, &ibwdt_is_open)) return -EBUSY; - } if (nowayout) __module_get(THIS_MODULE); @@ -273,7 +269,8 @@ ibwdt_close(struct inode *inode, struct file *file) if (expect_close == 42) { ibwdt_disable(); } else { - printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); + printk(KERN_CRIT PFX + "WDT device closed unexpectedly. WDT will not stop!\n"); ibwdt_ping(); } clear_bit(0, &ibwdt_is_open); @@ -289,7 +286,7 @@ static const struct file_operations ibwdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = ibwdt_write, - .ioctl = ibwdt_ioctl, + .unlocked_ioctl = ibwdt_ioctl, .open = ibwdt_open, .release = ibwdt_close, }; @@ -310,21 +307,23 @@ static int __devinit ibwdt_probe(struct platform_device *dev) #if WDT_START != WDT_STOP if (!request_region(WDT_STOP, 1, "IB700 WDT")) { - printk (KERN_ERR PFX "STOP method I/O %X is not available.\n", WDT_STOP); + printk(KERN_ERR PFX "STOP method I/O %X is not available.\n", + WDT_STOP); res = -EIO; goto out_nostopreg; } #endif if (!request_region(WDT_START, 1, "IB700 WDT")) { - printk (KERN_ERR PFX "START method I/O %X is not available.\n", WDT_START); + printk(KERN_ERR PFX "START method I/O %X is not available.\n", + WDT_START); res = -EIO; goto out_nostartreg; } res = misc_register(&ibwdt_miscdev); if (res) { - printk (KERN_ERR PFX "failed to register misc device\n"); + printk(KERN_ERR PFX "failed to register misc device\n"); goto out_nomisc; } return 0; @@ -342,9 +341,9 @@ out_nostopreg: static int __devexit ibwdt_remove(struct platform_device *dev) { misc_deregister(&ibwdt_miscdev); - release_region(WDT_START,1); + release_region(WDT_START, 1); #if WDT_START != WDT_STOP - release_region(WDT_STOP,1); + release_region(WDT_STOP, 1); #endif return 0; } @@ -369,13 +368,15 @@ static int __init ibwdt_init(void) { int err; - printk(KERN_INFO PFX "WDT driver for IB700 single board computer initialising.\n"); + printk(KERN_INFO PFX + "WDT driver for IB700 single board computer initialising.\n"); err = platform_driver_register(&ibwdt_driver); if (err) return err; - ibwdt_platform_device = platform_device_register_simple(DRV_NAME, -1, NULL, 0); + ibwdt_platform_device = platform_device_register_simple(DRV_NAME, + -1, NULL, 0); if (IS_ERR(ibwdt_platform_device)) { err = PTR_ERR(ibwdt_platform_device); goto unreg_platform_driver; -- cgit v1.2.3 From 0829291ea4a25c3c2ca4fba34aa38a1ee1e0b94b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:05:57 +0100 Subject: [WATCHDOG 13/57] i6300esb: Style, unlocked_ioctl, cleanup Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/i6300esb.c | 342 +++++++++++++++++++++----------------------- 1 file changed, 167 insertions(+), 175 deletions(-) diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index ca44fd9b19bb..01a283f7a271 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -38,9 +38,8 @@ #include #include #include - -#include -#include +#include +#include /* Module and version information */ #define ESB_VERSION "0.03" @@ -59,17 +58,17 @@ #define ESB_RELOAD_REG BASEADDR + 0x0c /* Reload register */ /* Lock register bits */ -#define ESB_WDT_FUNC ( 0x01 << 2 ) /* Watchdog functionality */ -#define ESB_WDT_ENABLE ( 0x01 << 1 ) /* Enable WDT */ -#define ESB_WDT_LOCK ( 0x01 << 0 ) /* Lock (nowayout) */ +#define ESB_WDT_FUNC (0x01 << 2) /* Watchdog functionality */ +#define ESB_WDT_ENABLE (0x01 << 1) /* Enable WDT */ +#define ESB_WDT_LOCK (0x01 << 0) /* Lock (nowayout) */ /* Config register bits */ -#define ESB_WDT_REBOOT ( 0x01 << 5 ) /* Enable reboot on timeout */ -#define ESB_WDT_FREQ ( 0x01 << 2 ) /* Decrement frequency */ -#define ESB_WDT_INTTYPE ( 0x11 << 0 ) /* Interrupt type on timer1 timeout */ +#define ESB_WDT_REBOOT (0x01 << 5) /* Enable reboot on timeout */ +#define ESB_WDT_FREQ (0x01 << 2) /* Decrement frequency */ +#define ESB_WDT_INTTYPE (0x11 << 0) /* Interrupt type on timer1 timeout */ /* Reload register bits */ -#define ESB_WDT_RELOAD ( 0x01 << 8 ) /* prevent timeout */ +#define ESB_WDT_RELOAD (0x01 << 8) /* prevent timeout */ /* Magic constants */ #define ESB_UNLOCK1 0x80 /* Step 1 to unlock reset registers */ @@ -84,14 +83,20 @@ static unsigned short triggered; /* The status of the watchdog upon boot */ static char esb_expect_close; /* module parameters */ -#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat (1 Date: Mon, 19 May 2008 14:06:03 +0100 Subject: [WATCHDOG 14/57] ibmasr: coding style, locking verify There is a new #if 0 section here which is a suggested fix for the horrible PCI hack in the existing code. Would be good if someone with a box that uses this device could test it. Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ibmasr.c | 149 +++++++++++++++++++++++++++------------------- 1 file changed, 87 insertions(+), 62 deletions(-) diff --git a/drivers/watchdog/ibmasr.c b/drivers/watchdog/ibmasr.c index 94155f6136c2..6824bf80b37e 100644 --- a/drivers/watchdog/ibmasr.c +++ b/drivers/watchdog/ibmasr.c @@ -19,9 +19,8 @@ #include #include #include - -#include -#include +#include +#include enum { @@ -70,10 +69,13 @@ static char asr_expect_close; static unsigned int asr_type, asr_base, asr_length; static unsigned int asr_read_addr, asr_write_addr; static unsigned char asr_toggle_mask, asr_disable_mask; +static spinlock_t asr_lock; -static void asr_toggle(void) +static void __asr_toggle(void) { - unsigned char reg = inb(asr_read_addr); + unsigned char reg; + + reg = inb(asr_read_addr); outb(reg & ~asr_toggle_mask, asr_write_addr); reg = inb(asr_read_addr); @@ -83,12 +85,21 @@ static void asr_toggle(void) outb(reg & ~asr_toggle_mask, asr_write_addr); reg = inb(asr_read_addr); + spin_unlock(&asr_lock); +} + +static void asr_toggle(void) +{ + spin_lock(&asr_lock); + __asr_toggle(); + spin_unlock(&asr_lock); } static void asr_enable(void) { unsigned char reg; + spin_lock(&asr_lock); if (asr_type == ASMTYPE_TOPAZ) { /* asr_write_addr == asr_read_addr */ reg = inb(asr_read_addr); @@ -99,17 +110,21 @@ static void asr_enable(void) * First make sure the hardware timer is reset by toggling * ASR hardware timer line. */ - asr_toggle(); + __asr_toggle(); reg = inb(asr_read_addr); outb(reg & ~asr_disable_mask, asr_write_addr); } reg = inb(asr_read_addr); + spin_unlock(&asr_lock); } static void asr_disable(void) { - unsigned char reg = inb(asr_read_addr); + unsigned char reg; + + spin_lock(&asr_lock); + reg = inb(asr_read_addr); if (asr_type == ASMTYPE_TOPAZ) /* asr_write_addr == asr_read_addr */ @@ -122,6 +137,7 @@ static void asr_disable(void) outb(reg | asr_disable_mask, asr_write_addr); } reg = inb(asr_read_addr); + spin_unlock(&asr_lock); } static int __init asr_get_base_address(void) @@ -133,7 +149,8 @@ static int __init asr_get_base_address(void) switch (asr_type) { case ASMTYPE_TOPAZ: - /* SELECT SuperIO CHIP FOR QUERYING (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ + /* SELECT SuperIO CHIP FOR QUERYING + (WRITE 0x07 TO BOTH 0x2E and 0x2F) */ outb(0x07, 0x2e); outb(0x07, 0x2f); @@ -154,14 +171,26 @@ static int __init asr_get_base_address(void) case ASMTYPE_JASPER: type = "Jaspers "; - - /* FIXME: need to use pci_config_lock here, but it's not exported */ +#if 0 + u32 r; + /* Suggested fix */ + pdev = pci_get_bus_and_slot(0, DEVFN(0x1f, 0)); + if (pdev == NULL) + return -ENODEV; + pci_read_config_dword(pdev, 0x58, &r); + asr_base = r & 0xFFFE; + pci_dev_put(pdev); +#else + /* FIXME: need to use pci_config_lock here, + but it's not exported */ /* spin_lock_irqsave(&pci_config_lock, flags);*/ /* Select the SuperIO chip in the PCI I/O port register */ outl(0x8000f858, 0xcf8); + /* BUS 0, Slot 1F, fnc 0, offset 58 */ + /* * Read the base address for the SuperIO chip. * Only the lower 16 bits are valid, but the address is word @@ -170,7 +199,7 @@ static int __init asr_get_base_address(void) asr_base = inl(0xcfc) & 0xfffe; /* spin_unlock_irqrestore(&pci_config_lock, flags);*/ - +#endif asr_read_addr = asr_write_addr = asr_base + JASPER_ASR_REG_OFFSET; asr_toggle_mask = JASPER_ASR_TOGGLE_MASK; @@ -241,11 +270,10 @@ static ssize_t asr_write(struct file *file, const char __user *buf, return count; } -static int asr_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { static const struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | + .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .identity = "IBM ASR" }; @@ -254,53 +282,45 @@ static int asr_ioctl(struct inode *inode, struct file *file, int heartbeat; switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident)) ? - -EFAULT : 0; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - - case WDIOC_KEEPALIVE: + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + asr_toggle(); + return 0; + /* + * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT + * and WDIOC_GETTIMEOUT always returns 256. + */ + case WDIOC_GETTIMEOUT: + heartbeat = 256; + return put_user(heartbeat, p); + case WDIOC_SETOPTIONS: + { + int new_options, retval = -EINVAL; + if (get_user(new_options, p)) + return -EFAULT; + if (new_options & WDIOS_DISABLECARD) { + asr_disable(); + retval = 0; + } + if (new_options & WDIOS_ENABLECARD) { + asr_enable(); asr_toggle(); - return 0; - - /* - * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT - * and WDIOC_GETTIMEOUT always returns 256. - */ - case WDIOC_GETTIMEOUT: - heartbeat = 256; - return put_user(heartbeat, p); - - case WDIOC_SETOPTIONS: { - int new_options, retval = -EINVAL; - - if (get_user(new_options, p)) - return -EFAULT; - - if (new_options & WDIOS_DISABLECARD) { - asr_disable(); - retval = 0; - } - - if (new_options & WDIOS_ENABLECARD) { - asr_enable(); - asr_toggle(); - retval = 0; - } - - return retval; + retval = 0; } + return retval; + } + default: + return -ENOTTY; } - - return -ENOTTY; } static int asr_open(struct inode *inode, struct file *file) { - if(test_and_set_bit(0, &asr_is_open)) + if (test_and_set_bit(0, &asr_is_open)) return -EBUSY; asr_toggle(); @@ -314,7 +334,8 @@ static int asr_release(struct inode *inode, struct file *file) if (asr_expect_close == 42) asr_disable(); else { - printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT PFX + "unexpected close, not stopping watchdog!\n"); asr_toggle(); } clear_bit(0, &asr_is_open); @@ -323,12 +344,12 @@ static int asr_release(struct inode *inode, struct file *file) } static const struct file_operations asr_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = asr_write, - .ioctl = asr_ioctl, - .open = asr_open, - .release = asr_release, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = asr_write, + .unlocked_ioctl = asr_ioctl, + .open = asr_open, + .release = asr_release, }; static struct miscdevice asr_miscdev = { @@ -367,6 +388,8 @@ static int __init ibmasr_init(void) if (!asr_type) return -ENODEV; + spin_lock_init(&asr_lock); + rc = asr_get_base_address(); if (rc) return rc; @@ -395,7 +418,9 @@ module_init(ibmasr_init); module_exit(ibmasr_exit); module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); MODULE_DESCRIPTION("IBM Automatic Server Restart driver"); MODULE_AUTHOR("Andrey Panin"); -- cgit v1.2.3 From 9b9dbcca3fa13acd64dbb9258bfe997809d6073b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:08 +0100 Subject: [WATCHDOG 15/57] indydog: Clean up and tidy Switch to unlocked_ioctl as well Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/indydog.c | 114 ++++++++++++++++++++++++--------------------- 1 file changed, 62 insertions(+), 52 deletions(-) diff --git a/drivers/watchdog/indydog.c b/drivers/watchdog/indydog.c index 788245bdaa7f..0bffea37404e 100644 --- a/drivers/watchdog/indydog.c +++ b/drivers/watchdog/indydog.c @@ -1,7 +1,8 @@ /* * IndyDog 0.3 A Hardware Watchdog Device for SGI IP22 * - * (c) Copyright 2002 Guido Guenther , All Rights Reserved. + * (c) Copyright 2002 Guido Guenther , + * All Rights Reserved. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -22,32 +23,42 @@ #include #include #include -#include +#include #include #define PFX "indydog: " -static int indydog_alive; +static unsigned long indydog_alive; +static spinlock_t indydog_lock; #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static void indydog_start(void) { - u32 mc_ctrl0 = sgimc->cpuctrl0; + u32 mc_ctrl0; + spin_lock(&indydog_lock); + mc_ctrl0 = sgimc->cpuctrl0; mc_ctrl0 = sgimc->cpuctrl0 | SGIMC_CCTRL0_WDOG; sgimc->cpuctrl0 = mc_ctrl0; + spin_unlock(&indydog_lock); } static void indydog_stop(void) { - u32 mc_ctrl0 = sgimc->cpuctrl0; + u32 mc_ctrl0; + spin_lock(&indydog_lock); + + mc_ctrl0 = sgimc->cpuctrl0; mc_ctrl0 &= ~SGIMC_CCTRL0_WDOG; sgimc->cpuctrl0 = mc_ctrl0; + spin_unlock(&indydog_lock); printk(KERN_INFO PFX "Stopped watchdog timer.\n"); } @@ -62,7 +73,7 @@ static void indydog_ping(void) */ static int indydog_open(struct inode *inode, struct file *file) { - if (indydog_alive) + if (test_and_set_bit(0, &indydog_alive)) return -EBUSY; if (nowayout) @@ -84,23 +95,21 @@ static int indydog_release(struct inode *inode, struct file *file) * Lock it in if it's a module and we defined ...NOWAYOUT */ if (!nowayout) indydog_stop(); /* Turn the WDT off */ - - indydog_alive = 0; - + clear_bit(0, &indydog_alive); return 0; } -static ssize_t indydog_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t indydog_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { /* Refresh the timer. */ - if (len) { + if (len) indydog_ping(); - } return len; } -static int indydog_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long indydog_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int options, retval = -EINVAL; static struct watchdog_info ident = { @@ -111,42 +120,40 @@ static int indydog_ioctl(struct inode *inode, struct file *file, }; switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - if (copy_to_user((struct watchdog_info *)arg, - &ident, sizeof(ident))) - return -EFAULT; - return 0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0,(int *)arg); - case WDIOC_KEEPALIVE: - indydog_ping(); - return 0; - case WDIOC_GETTIMEOUT: - return put_user(WATCHDOG_TIMEOUT,(int *)arg); - case WDIOC_SETOPTIONS: - { - if (get_user(options, (int *)arg)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - indydog_stop(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - indydog_start(); - retval = 0; - } - - return retval; + case WDIOC_GETSUPPORT: + if (copy_to_user((struct watchdog_info *)arg, + &ident, sizeof(ident))) + return -EFAULT; + return 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, (int *)arg); + case WDIOC_KEEPALIVE: + indydog_ping(); + return 0; + case WDIOC_GETTIMEOUT: + return put_user(WATCHDOG_TIMEOUT, (int *)arg); + case WDIOC_SETOPTIONS: + { + if (get_user(options, (int *)arg)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + indydog_stop(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + indydog_start(); + retval = 0; } + return retval; + } + default: + return -ENOTTY; } } -static int indydog_notify_sys(struct notifier_block *this, unsigned long code, void *unused) +static int indydog_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) indydog_stop(); /* Turn the WDT off */ @@ -158,7 +165,7 @@ static const struct file_operations indydog_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = indydog_write, - .ioctl = indydog_ioctl, + .unlocked_ioctl = indydog_ioctl, .open = indydog_open, .release = indydog_release, }; @@ -180,17 +187,20 @@ static int __init watchdog_init(void) { int ret; + spin_lock_init(&indydog_lock); + ret = register_reboot_notifier(&indydog_notifier); if (ret) { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - ret); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); return ret; } ret = misc_register(&indydog_miscdev); if (ret) { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); unregister_reboot_notifier(&indydog_notifier); return ret; } -- cgit v1.2.3 From 02e3814e193ff798676793016851bc222366dc6a Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:14 +0100 Subject: [WATCHDOG 16/57] iop: watchdog switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/iop_wdt.c | 46 ++++++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/watchdog/iop_wdt.c b/drivers/watchdog/iop_wdt.c index bbbd91af754d..e54c888d2afe 100644 --- a/drivers/watchdog/iop_wdt.c +++ b/drivers/watchdog/iop_wdt.c @@ -37,6 +37,7 @@ static int nowayout = WATCHDOG_NOWAYOUT; static unsigned long wdt_status; static unsigned long boot_status; +static spinlock_t wdt_lock; #define WDT_IN_USE 0 #define WDT_OK_TO_CLOSE 1 @@ -68,8 +69,10 @@ static void wdt_enable(void) /* Arm and enable the Timer to starting counting down from 0xFFFF.FFFF * Takes approx. 10.7s to timeout */ + spin_lock(&wdt_lock); write_wdtcr(IOP_WDTCR_EN_ARM); write_wdtcr(IOP_WDTCR_EN); + spin_unlock(&wdt_lock); } /* returns 0 if the timer was successfully disabled */ @@ -77,9 +80,11 @@ static int wdt_disable(void) { /* Stop Counting */ if (wdt_supports_disable()) { + spin_lock(&wdt_lock); write_wdtcr(IOP_WDTCR_DIS_ARM); write_wdtcr(IOP_WDTCR_DIS); clear_bit(WDT_ENABLED, &wdt_status); + spin_unlock(&wdt_lock); printk(KERN_INFO "WATCHDOG: Disabled\n"); return 0; } else @@ -92,16 +97,12 @@ static int iop_wdt_open(struct inode *inode, struct file *file) return -EBUSY; clear_bit(WDT_OK_TO_CLOSE, &wdt_status); - wdt_enable(); - set_bit(WDT_ENABLED, &wdt_status); - return nonseekable_open(inode, file); } -static ssize_t -iop_wdt_write(struct file *file, const char *data, size_t len, +static ssize_t iop_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) { if (len) { @@ -121,41 +122,39 @@ iop_wdt_write(struct file *file, const char *data, size_t len, } wdt_enable(); } - return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, .identity = "iop watchdog", }; -static int -iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long iop_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int options; int ret = -ENOTTY; + int __user *argp = (int __user *)arg; switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user - ((struct watchdog_info *)arg, &ident, sizeof ident)) + if (copy_to_user(argp, &ident, sizeof ident)) ret = -EFAULT; else ret = 0; break; case WDIOC_GETSTATUS: - ret = put_user(0, (int *)arg); + ret = put_user(0, argp); break; case WDIOC_GETBOOTSTATUS: - ret = put_user(boot_status, (int *)arg); + ret = put_user(boot_status, argp); break; case WDIOC_GETTIMEOUT: - ret = put_user(iop_watchdog_timeout(), (int *)arg); + ret = put_user(iop_watchdog_timeout(), argp); break; case WDIOC_KEEPALIVE: @@ -177,14 +176,12 @@ iop_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, } else ret = 0; } - if (options & WDIOS_ENABLECARD) { wdt_enable(); ret = 0; } break; } - return ret; } @@ -214,7 +211,7 @@ static const struct file_operations iop_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = iop_wdt_write, - .ioctl = iop_wdt_ioctl, + .unlocked_ioctl = iop_wdt_ioctl, .open = iop_wdt_open, .release = iop_wdt_release, }; @@ -229,10 +226,8 @@ static int __init iop_wdt_init(void) { int ret; - ret = misc_register(&iop_wdt_miscdev); - if (ret == 0) - printk("iop watchdog timer: timeout %lu sec\n", - iop_watchdog_timeout()); + spin_lock_init(&wdt_lock); + /* check if the reset was caused by the watchdog timer */ boot_status = (read_rcsr() & IOP_RCSR_WDT) ? WDIOF_CARDRESET : 0; @@ -242,6 +237,13 @@ static int __init iop_wdt_init(void) */ write_wdtsr(IOP13XX_WDTCR_IB_RESET); + /* Register after we have the device set up so we cannot race + with an open */ + ret = misc_register(&iop_wdt_miscdev); + if (ret == 0) + printk("iop watchdog timer: timeout %lu sec\n", + iop_watchdog_timeout()); + return ret; } -- cgit v1.2.3 From 30abcec14573e3462f18d63f4a8f154a23689f1b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:19 +0100 Subject: [WATCHDOG 17/57] it8712f: unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/it8712f_wdt.c | 77 +++++++++++++++--------------------------- 1 file changed, 27 insertions(+), 50 deletions(-) diff --git a/drivers/watchdog/it8712f_wdt.c b/drivers/watchdog/it8712f_wdt.c index 445b7e812112..51bfd5721833 100644 --- a/drivers/watchdog/it8712f_wdt.c +++ b/drivers/watchdog/it8712f_wdt.c @@ -30,9 +30,8 @@ #include #include #include - -#include -#include +#include +#include #define NAME "it8712f_wdt" @@ -50,7 +49,7 @@ static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); -static struct semaphore it8712f_wdt_sem; +static unsigned long wdt_open; static unsigned expect_close; static spinlock_t io_lock; static unsigned char revision; @@ -86,22 +85,19 @@ static unsigned short address; #define WDT_OUT_PWROK 0x10 #define WDT_OUT_KRST 0x40 -static int -superio_inb(int reg) +static int superio_inb(int reg) { outb(reg, REG); return inb(VAL); } -static void -superio_outb(int val, int reg) +static void superio_outb(int val, int reg) { outb(reg, REG); outb(val, VAL); } -static int -superio_inw(int reg) +static int superio_inw(int reg) { int val; outb(reg++, REG); @@ -111,15 +107,13 @@ superio_inw(int reg) return val; } -static inline void -superio_select(int ldn) +static inline void superio_select(int ldn) { outb(LDN, REG); outb(ldn, VAL); } -static inline void -superio_enter(void) +static inline void superio_enter(void) { spin_lock(&io_lock); outb(0x87, REG); @@ -128,22 +122,19 @@ superio_enter(void) outb(0x55, REG); } -static inline void -superio_exit(void) +static inline void superio_exit(void) { outb(0x02, REG); outb(0x02, VAL); spin_unlock(&io_lock); } -static inline void -it8712f_wdt_ping(void) +static inline void it8712f_wdt_ping(void) { inb(address); } -static void -it8712f_wdt_update_margin(void) +static void it8712f_wdt_update_margin(void) { int config = WDT_OUT_KRST | WDT_OUT_PWROK; int units = margin; @@ -165,8 +156,7 @@ it8712f_wdt_update_margin(void) superio_outb(units, WDT_TIMEOUT); } -static int -it8712f_wdt_get_status(void) +static int it8712f_wdt_get_status(void) { if (superio_inb(WDT_CONTROL) & 0x01) return WDIOF_CARDRESET; @@ -174,8 +164,7 @@ it8712f_wdt_get_status(void) return 0; } -static void -it8712f_wdt_enable(void) +static void it8712f_wdt_enable(void) { printk(KERN_DEBUG NAME ": enabling watchdog timer\n"); superio_enter(); @@ -190,8 +179,7 @@ it8712f_wdt_enable(void) it8712f_wdt_ping(); } -static void -it8712f_wdt_disable(void) +static void it8712f_wdt_disable(void) { printk(KERN_DEBUG NAME ": disabling watchdog timer\n"); @@ -207,8 +195,7 @@ it8712f_wdt_disable(void) superio_exit(); } -static int -it8712f_wdt_notify(struct notifier_block *this, +static int it8712f_wdt_notify(struct notifier_block *this, unsigned long code, void *unused) { if (code == SYS_HALT || code == SYS_POWER_OFF) @@ -222,9 +209,8 @@ static struct notifier_block it8712f_wdt_notifier = { .notifier_call = it8712f_wdt_notify, }; -static ssize_t -it8712f_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) +static ssize_t it8712f_wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) { /* check for a magic close character */ if (len) { @@ -245,9 +231,8 @@ it8712f_wdt_write(struct file *file, const char __user *data, return len; } -static int -it8712f_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -302,19 +287,16 @@ it8712f_wdt_ioctl(struct inode *inode, struct file *file, } } -static int -it8712f_wdt_open(struct inode *inode, struct file *file) +static int it8712f_wdt_open(struct inode *inode, struct file *file) { /* only allow one at a time */ - if (down_trylock(&it8712f_wdt_sem)) + if (test_and_set_bit(0, &wdt_open)) return -EBUSY; it8712f_wdt_enable(); - return nonseekable_open(inode, file); } -static int -it8712f_wdt_release(struct inode *inode, struct file *file) +static int it8712f_wdt_release(struct inode *inode, struct file *file) { if (expect_close != 42) { printk(KERN_WARNING NAME @@ -324,7 +306,7 @@ it8712f_wdt_release(struct inode *inode, struct file *file) it8712f_wdt_disable(); } expect_close = 0; - up(&it8712f_wdt_sem); + clear_bit(0, &wdt_open); return 0; } @@ -333,7 +315,7 @@ static const struct file_operations it8712f_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = it8712f_wdt_write, - .ioctl = it8712f_wdt_ioctl, + .unlocked_ioctl = it8712f_wdt_ioctl, .open = it8712f_wdt_open, .release = it8712f_wdt_release, }; @@ -344,8 +326,7 @@ static struct miscdevice it8712f_wdt_miscdev = { .fops = &it8712f_wdt_fops, }; -static int __init -it8712f_wdt_find(unsigned short *address) +static int __init it8712f_wdt_find(unsigned short *address) { int err = -ENODEV; int chip_type; @@ -387,8 +368,7 @@ exit: return err; } -static int __init -it8712f_wdt_init(void) +static int __init it8712f_wdt_init(void) { int err = 0; @@ -404,8 +384,6 @@ it8712f_wdt_init(void) it8712f_wdt_disable(); - sema_init(&it8712f_wdt_sem, 1); - err = register_reboot_notifier(&it8712f_wdt_notifier); if (err) { printk(KERN_ERR NAME ": unable to register reboot notifier\n"); @@ -430,8 +408,7 @@ out: return err; } -static void __exit -it8712f_wdt_exit(void) +static void __exit it8712f_wdt_exit(void) { misc_deregister(&it8712f_wdt_miscdev); unregister_reboot_notifier(&it8712f_wdt_notifier); -- cgit v1.2.3 From 0e6fa3fb38e2c89ba9abce9a8b74867f07d20d19 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:25 +0100 Subject: [WATCHDOG 18/57] iTCO: unlocked_ioctl, coding style and cleanup Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/iTCO_vendor.h | 15 ++ drivers/watchdog/iTCO_vendor_support.c | 53 +++--- drivers/watchdog/iTCO_wdt.c | 296 ++++++++++++++++----------------- 3 files changed, 189 insertions(+), 175 deletions(-) create mode 100644 drivers/watchdog/iTCO_vendor.h diff --git a/drivers/watchdog/iTCO_vendor.h b/drivers/watchdog/iTCO_vendor.h new file mode 100644 index 000000000000..9e27e6422f66 --- /dev/null +++ b/drivers/watchdog/iTCO_vendor.h @@ -0,0 +1,15 @@ +/* iTCO Vendor Specific Support hooks */ +#ifdef CONFIG_ITCO_VENDOR_SUPPORT +extern void iTCO_vendor_pre_start(unsigned long, unsigned int); +extern void iTCO_vendor_pre_stop(unsigned long); +extern void iTCO_vendor_pre_keepalive(unsigned long, unsigned int); +extern void iTCO_vendor_pre_set_heartbeat(unsigned int); +extern int iTCO_vendor_check_noreboot_on(void); +#else +#define iTCO_vendor_pre_start(acpibase, heartbeat) {} +#define iTCO_vendor_pre_stop(acpibase) {} +#define iTCO_vendor_pre_keepalive(acpibase, heartbeat) {} +#define iTCO_vendor_pre_set_heartbeat(heartbeat) {} +#define iTCO_vendor_check_noreboot_on() 1 + /* 1=check noreboot; 0=don't check */ +#endif diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c index cafc465f2ae3..09e9534ac2e4 100644 --- a/drivers/watchdog/iTCO_vendor_support.c +++ b/drivers/watchdog/iTCO_vendor_support.c @@ -32,7 +32,9 @@ #include /* For __init/__exit/... */ #include /* For io-port access */ -#include /* For inb/outb/... */ +#include /* For inb/outb/... */ + +#include "iTCO_vendor.h" /* iTCO defines */ #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ @@ -40,10 +42,12 @@ #define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ /* List of vendor support modes */ -#define SUPERMICRO_OLD_BOARD 1 /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ -#define SUPERMICRO_NEW_BOARD 2 /* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ +/* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ +#define SUPERMICRO_OLD_BOARD 1 +/* SuperMicro Pentium 4 / Xeon 4 / EMT64T Era Systems */ +#define SUPERMICRO_NEW_BOARD 2 -static int vendorsupport = 0; +static int vendorsupport; module_param(vendorsupport, int, 0); MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (none), 1=SuperMicro Pent3, 2=SuperMicro Pent4+"); @@ -143,34 +147,35 @@ static void supermicro_old_pre_keepalive(unsigned long acpibase) */ /* I/O Port's */ -#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ -#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ +#define SM_REGINDEX 0x2e /* SuperMicro ICH4+ Register Index */ +#define SM_DATAIO 0x2f /* SuperMicro ICH4+ Register Data I/O */ /* Control Register's */ -#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ -#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ +#define SM_CTLPAGESW 0x07 /* SuperMicro ICH4+ Control Page Switch */ +#define SM_CTLPAGE 0x08 /* SuperMicro ICH4+ Control Page Num */ -#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ +#define SM_WATCHENABLE 0x30 /* Watchdog enable: Bit 0: 0=off, 1=on */ -#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ +#define SM_WATCHPAGE 0x87 /* Watchdog unlock control page */ -#define SM_ENDWATCH 0xAA /* Watchdog lock control page */ +#define SM_ENDWATCH 0xAA /* Watchdog lock control page */ -#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ - /* (Bit 3: 0 = seconds, 1 = minutes */ +#define SM_COUNTMODE 0xf5 /* Watchdog count mode select */ + /* (Bit 3: 0 = seconds, 1 = minutes */ -#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ +#define SM_WATCHTIMER 0xf6 /* 8-bits, Watchdog timer counter (RW) */ -#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ - /* Bit 6: timer is reset by kbd interrupt */ - /* Bit 7: timer is reset by mouse interrupt */ +#define SM_RESETCONTROL 0xf7 /* Watchdog reset control */ + /* Bit 6: timer is reset by kbd interrupt */ + /* Bit 7: timer is reset by mouse interrupt */ static void supermicro_new_unlock_watchdog(void) { - outb(SM_WATCHPAGE, SM_REGINDEX); /* Write 0x87 to port 0x2e twice */ + /* Write 0x87 to port 0x2e twice */ outb(SM_WATCHPAGE, SM_REGINDEX); - - outb(SM_CTLPAGESW, SM_REGINDEX); /* Switch to watchdog control page */ + outb(SM_WATCHPAGE, SM_REGINDEX); + /* Switch to watchdog control page */ + outb(SM_CTLPAGESW, SM_REGINDEX); outb(SM_CTLPAGE, SM_DATAIO); } @@ -192,7 +197,7 @@ static void supermicro_new_pre_start(unsigned int heartbeat) outb(val, SM_DATAIO); /* Write heartbeat interval to WDOG */ - outb (SM_WATCHTIMER, SM_REGINDEX); + outb(SM_WATCHTIMER, SM_REGINDEX); outb((heartbeat & 255), SM_DATAIO); /* Make sure keyboard/mouse interrupts don't interfere */ @@ -277,7 +282,7 @@ EXPORT_SYMBOL(iTCO_vendor_pre_set_heartbeat); int iTCO_vendor_check_noreboot_on(void) { - switch(vendorsupport) { + switch (vendorsupport) { case SUPERMICRO_OLD_BOARD: return 0; default: @@ -288,13 +293,13 @@ EXPORT_SYMBOL(iTCO_vendor_check_noreboot_on); static int __init iTCO_vendor_init_module(void) { - printk (KERN_INFO PFX "vendor-support=%d\n", vendorsupport); + printk(KERN_INFO PFX "vendor-support=%d\n", vendorsupport); return 0; } static void __exit iTCO_vendor_exit_module(void) { - printk (KERN_INFO PFX "Module Unloaded\n"); + printk(KERN_INFO PFX "Module Unloaded\n"); } module_init(iTCO_vendor_init_module); diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index 95ba985bd341..c9ca8f691d81 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -66,7 +66,8 @@ #include /* For standard types (like size_t) */ #include /* For the -ENODEV/... values */ #include /* For printk/panic/... */ -#include /* For MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR) */ +#include /* For MODULE_ALIAS_MISCDEV + (WATCHDOG_MINOR) */ #include /* For the watchdog specific items */ #include /* For __init/__exit/... */ #include /* For file operations */ @@ -74,9 +75,10 @@ #include /* For pci functions */ #include /* For io-port access */ #include /* For spin_lock/spin_unlock/... */ +#include /* For copy_to_user/put_user/... */ +#include /* For inb/outb/... */ -#include /* For copy_to_user/put_user/... */ -#include /* For inb/outb/... */ +#include "iTCO_vendor.h" /* TCO related info */ enum iTCO_chipsets { @@ -140,7 +142,7 @@ static struct { {"ICH9DH", 2}, {"ICH9DO", 2}, {"631xESB/632xESB", 2}, - {NULL,0} + {NULL, 0} }; #define ITCO_PCI_DEVICE(dev, data) \ @@ -159,32 +161,32 @@ static struct { * functions that probably will be registered by other drivers. */ static struct pci_device_id iTCO_wdt_pci_tbl[] = { - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5 )}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0, TCO_ICH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0, TCO_ICH0)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0, TCO_ICH2)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10, TCO_ICH2M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0, TCO_ICH3)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12, TCO_ICH3M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0, TCO_ICH4)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12, TCO_ICH4M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0, TCO_CICH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0, TCO_ICH5)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1, TCO_6300ESB)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M )}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0, TCO_ICH6)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1, TCO_ICH6M)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2, TCO_ICH6W)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0, TCO_ICH7)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1, TCO_ICH7M)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31, TCO_ICH7MDH)}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8 )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M )}, - { ITCO_PCI_DEVICE(0x2918, TCO_ICH9 )}, - { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH )}, - { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO )}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0, TCO_ICH8)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1, TCO_ICH8ME)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2, TCO_ICH8DH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3, TCO_ICH8DO)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4, TCO_ICH8M)}, + { ITCO_PCI_DEVICE(0x2918, TCO_ICH9)}, + { ITCO_PCI_DEVICE(0x2916, TCO_ICH9R)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2, TCO_ICH9DH)}, + { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4, TCO_ICH9DO)}, { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x2671, TCO_631XESB)}, { ITCO_PCI_DEVICE(0x2672, TCO_631XESB)}, @@ -203,13 +205,15 @@ static struct pci_device_id iTCO_wdt_pci_tbl[] = { { ITCO_PCI_DEVICE(0x267f, TCO_631XESB)}, { 0, }, /* End of list */ }; -MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl); +MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl); /* Address definitions for the TCO */ -#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 /* TCO base address */ -#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 /* SMI Control and Enable Register */ +/* TCO base address */ +#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60 +/* SMI Control and Enable Register */ +#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30 -#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Current Value */ +#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */ #define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */ #define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */ #define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */ @@ -222,15 +226,21 @@ MODULE_DEVICE_TABLE (pci, iTCO_wdt_pci_tbl); /* internal variables */ static unsigned long is_active; static char expect_release; -static struct { /* this is private data for the iTCO_wdt device */ - unsigned int iTCO_version; /* TCO version/generation */ - unsigned long ACPIBASE; /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ - unsigned long __iomem *gcs; /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2) */ - spinlock_t io_lock; /* the lock for io operations */ - struct pci_dev *pdev; /* the PCI-device */ +static struct { /* this is private data for the iTCO_wdt device */ + /* TCO version/generation */ + unsigned int iTCO_version; + /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */ + unsigned long ACPIBASE; + /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/ + unsigned long __iomem *gcs; + /* the lock for io operations */ + spinlock_t io_lock; + /* the PCI-device */ + struct pci_dev *pdev; } iTCO_wdt_private; -static struct platform_device *iTCO_wdt_platform_device; /* the watchdog platform device */ +/* the watchdog platform device */ +static struct platform_device *iTCO_wdt_platform_device; /* module parameters */ #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ @@ -240,22 +250,9 @@ MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2driver_data].iTCO_version; + iTCO_wdt_private.iTCO_version = + iTCO_chipset_info[ent->driver_data].iTCO_version; iTCO_wdt_private.ACPIBASE = base_address; iTCO_wdt_private.pdev = pdev; - /* Get the Memory-Mapped GCS register, we need it for the NO_REBOOT flag (TCO v2) */ - /* To get access to it you have to read RCBA from PCI Config space 0xf0 - and use it as base. GCS = RCBA + ICH6_GCS(0x3410). */ + /* Get the Memory-Mapped GCS register, we need it for the + NO_REBOOT flag (TCO v2). To get access to it you have to + read RCBA from PCI Config space 0xf0 and use it as base. + GCS = RCBA + ICH6_GCS(0x3410). */ if (iTCO_wdt_private.iTCO_version == 2) { pci_read_config_dword(pdev, 0xf0, &base_address); RCBA = base_address & 0xffffc000; - iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410),4); + iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4); } /* Check chipset's NO_REBOOT bit */ @@ -657,8 +646,8 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device /* Set the TCO_EN bit in SMI_EN register */ if (!request_region(SMI_EN, 4, "iTCO_wdt")) { - printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", - SMI_EN ); + printk(KERN_ERR PFX + "I/O address 0x%04lx already in use\n", SMI_EN); ret = -EIO; goto out; } @@ -667,18 +656,20 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device outl(val32, SMI_EN); release_region(SMI_EN, 4); - /* The TCO I/O registers reside in a 32-byte range pointed to by the TCOBASE value */ - if (!request_region (TCOBASE, 0x20, "iTCO_wdt")) { - printk (KERN_ERR PFX "I/O address 0x%04lx already in use\n", + /* The TCO I/O registers reside in a 32-byte range pointed to + by the TCOBASE value */ + if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) { + printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n", TCOBASE); ret = -EIO; goto out; } - printk(KERN_INFO PFX "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", - iTCO_chipset_info[ent->driver_data].name, - iTCO_chipset_info[ent->driver_data].iTCO_version, - TCOBASE); + printk(KERN_INFO PFX + "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n", + iTCO_chipset_info[ent->driver_data].name, + iTCO_chipset_info[ent->driver_data].iTCO_version, + TCOBASE); /* Clear out the (probably old) status */ outb(0, TCO1_STS); @@ -687,27 +678,29 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev, const struct pci_device /* Make sure the watchdog is not running */ iTCO_wdt_stop(); - /* Check that the heartbeat value is within it's range ; if not reset to the default */ + /* Check that the heartbeat value is within it's range; + if not reset to the default */ if (iTCO_wdt_set_heartbeat(heartbeat)) { iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT); - printk(KERN_INFO PFX "heartbeat value must be 2 Date: Mon, 19 May 2008 14:06:30 +0100 Subject: [WATCHDOG 19/57] bfin: watchdog cleanup and unlocked_ioctl Scan, tidy and check for unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/bfin_wdt.c | 147 +++++++++++++++++++++----------------------- 1 file changed, 71 insertions(+), 76 deletions(-) diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 03b3e3d91e7c..2b92818cc664 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args) #define stampit() stamp("here i am") @@ -148,7 +148,8 @@ static int bfin_wdt_set_timeout(unsigned long t) int run = bfin_wdt_running(); bfin_wdt_stop(); bfin_write_WDOG_CNT(cnt); - if (run) bfin_wdt_start(); + if (run) + bfin_wdt_start(); } spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); @@ -191,16 +192,15 @@ static int bfin_wdt_release(struct inode *inode, struct file *file) { stampit(); - if (expect_close == 42) { + if (expect_close == 42) bfin_wdt_stop(); - } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); bfin_wdt_keepalive(); } - expect_close = 0; clear_bit(0, &open_check); - return 0; } @@ -214,7 +214,7 @@ static int bfin_wdt_release(struct inode *inode, struct file *file) * Pings the watchdog on write. */ static ssize_t bfin_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t *ppos) + size_t len, loff_t *ppos) { stampit(); @@ -241,7 +241,6 @@ static ssize_t bfin_wdt_write(struct file *file, const char __user *data, /** * bfin_wdt_ioctl - Query Device - * @inode: inode of device * @file: file handle of device * @cmd: watchdog command * @arg: argument @@ -249,8 +248,8 @@ static ssize_t bfin_wdt_write(struct file *file, const char __user *data, * Query basic information from the device or ping it, as outlined by the * watchdog API. */ -static int bfin_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long bfin_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -258,59 +257,49 @@ static int bfin_wdt_ioctl(struct inode *inode, struct file *file, stampit(); switch (cmd) { - default: - return -ENOTTY; - - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info))) - return -EFAULT; - else - return 0; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p); - - case WDIOC_KEEPALIVE: - bfin_wdt_keepalive(); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &bfin_wdt_info, sizeof(bfin_wdt_info))) + return -EFAULT; + else return 0; - - case WDIOC_SETTIMEOUT: { - int new_timeout; - - if (get_user(new_timeout, p)) - return -EFAULT; - - if (bfin_wdt_set_timeout(new_timeout)) - return -EINVAL; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p); + case WDIOC_KEEPALIVE: + bfin_wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: { + int new_timeout; + + if (get_user(new_timeout, p)) + return -EFAULT; + if (bfin_wdt_set_timeout(new_timeout)) + return -EINVAL; + } + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); + case WDIOC_SETOPTIONS: { + unsigned long flags; + int options, ret = -EINVAL; + + if (get_user(options, p)) + return -EFAULT; + + spin_lock_irqsave(&bfin_wdt_spinlock, flags); + if (options & WDIOS_DISABLECARD) { + bfin_wdt_stop(); + ret = 0; } - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - - case WDIOC_SETOPTIONS: { - unsigned long flags; - int options, ret = -EINVAL; - - if (get_user(options, p)) - return -EFAULT; - - spin_lock_irqsave(&bfin_wdt_spinlock, flags); - - if (options & WDIOS_DISABLECARD) { - bfin_wdt_stop(); - ret = 0; - } - - if (options & WDIOS_ENABLECARD) { - bfin_wdt_start(); - ret = 0; - } - - spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); - - return ret; + if (options & WDIOS_ENABLECARD) { + bfin_wdt_start(); + ret = 0; } + spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); + return ret; + } + default: + return -ENOTTY; } } @@ -323,8 +312,8 @@ static int bfin_wdt_ioctl(struct inode *inode, struct file *file, * Handles specific events, such as turning off the watchdog during a * shutdown event. */ -static int bfin_wdt_notify_sys(struct notifier_block *this, unsigned long code, - void *unused) +static int bfin_wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) { stampit(); @@ -379,12 +368,12 @@ static int bfin_wdt_resume(struct platform_device *pdev) #endif static const struct file_operations bfin_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = bfin_wdt_write, - .ioctl = bfin_wdt_ioctl, - .open = bfin_wdt_open, - .release = bfin_wdt_release, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = bfin_wdt_write, + .unlocked_ioctl = bfin_wdt_ioctl, + .open = bfin_wdt_open, + .release = bfin_wdt_release, }; static struct miscdevice bfin_wdt_miscdev = { @@ -396,8 +385,8 @@ static struct miscdevice bfin_wdt_miscdev = { static struct watchdog_info bfin_wdt_info = { .identity = "Blackfin Watchdog", .options = WDIOF_SETTIMEOUT | - WDIOF_KEEPALIVEPING | - WDIOF_MAGICCLOSE, + WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE, }; static struct notifier_block bfin_wdt_notifier = { @@ -416,14 +405,16 @@ static int __devinit bfin_wdt_probe(struct platform_device *pdev) ret = register_reboot_notifier(&bfin_wdt_notifier); if (ret) { - pr_devinit(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", ret); + pr_devinit(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); return ret; } ret = misc_register(&bfin_wdt_miscdev); if (ret) { - pr_devinit(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + pr_devinit(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); unregister_reboot_notifier(&bfin_wdt_notifier); return ret; } @@ -516,7 +507,11 @@ MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); module_param(timeout, uint, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1<=timeout<=((2^32)/SCLK), default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -- cgit v1.2.3 From 00e9c2059aba0a0d67d144229bac82d403c2f42a Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:36 +0100 Subject: [WATCHDOG 20/57] booke watchdog: clean up and unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/booke_wdt.c | 26 ++++++++++++++------------ 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index c1ba0db48501..4c423d531a89 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c @@ -18,9 +18,9 @@ #include #include #include +#include #include -#include #include /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. @@ -32,7 +32,7 @@ */ #ifdef CONFIG_FSL_BOOKE -#define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz , reset=~40sec */ +#define WDT_PERIOD_DEFAULT 63 /* Ex. wdt_period=28 bus=333Mhz,reset=~40sec */ #else #define WDT_PERIOD_DEFAULT 3 /* Refer to the PPC40x and PPC4xx manuals */ #endif /* for timing information */ @@ -82,16 +82,15 @@ static struct watchdog_info ident = { .identity = "PowerPC Book-E Watchdog", }; -static int booke_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long booke_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { u32 tmp = 0; u32 __user *p = (u32 __user *)arg; switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user((struct watchdog_info __user *)arg, &ident, - sizeof(struct watchdog_info))) + if (copy_to_user(arg, &ident, sizeof(struct watchdog_info))) return -EFAULT; case WDIOC_GETSTATUS: return put_user(ident.options, p); @@ -106,7 +105,8 @@ static int booke_wdt_ioctl(struct inode *inode, struct file *file, case WDIOC_SETTIMEOUT: if (get_user(booke_wdt_period, p)) return -EFAULT; - mtspr(SPRN_TCR, (mfspr(SPRN_TCR)&~WDTP(0))|WDTP(booke_wdt_period)); + mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WDTP(0)) | + WDTP(booke_wdt_period)); return 0; case WDIOC_GETTIMEOUT: return put_user(booke_wdt_period, p); @@ -132,8 +132,9 @@ static int booke_wdt_open(struct inode *inode, struct file *file) if (booke_wdt_enabled == 0) { booke_wdt_enabled = 1; on_each_cpu(__booke_wdt_enable, NULL, 0, 0); - printk(KERN_INFO "PowerPC Book-E Watchdog Timer Enabled " - "(wdt_period=%d)\n", booke_wdt_period); + printk(KERN_INFO + "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n", + booke_wdt_period); } spin_unlock(&booke_wdt_lock); @@ -144,7 +145,7 @@ static const struct file_operations booke_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = booke_wdt_write, - .ioctl = booke_wdt_ioctl, + .unlocked_ioctl = booke_wdt_ioctl, .open = booke_wdt_open, }; @@ -175,8 +176,9 @@ static int __init booke_wdt_init(void) spin_lock(&booke_wdt_lock); if (booke_wdt_enabled == 1) { - printk(KERN_INFO "PowerPC Book-E Watchdog Timer Enabled " - "(wdt_period=%d)\n", booke_wdt_period); + printk(KERN_INFO + "PowerPC Book-E Watchdog Timer Enabled (wdt_period=%d)\n", + booke_wdt_period); on_each_cpu(__booke_wdt_enable, NULL, 0, 0); } spin_unlock(&booke_wdt_lock); -- cgit v1.2.3 From 640b4f685784feafcd99c24582c5eb3ea36c3c60 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:42 +0100 Subject: [WATCHDOG 21/57] ixp2000_wdt: clean up and unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ixp2000_wdt.c | 50 +++++++++++++++++++----------------------- 1 file changed, 23 insertions(+), 27 deletions(-) diff --git a/drivers/watchdog/ixp2000_wdt.c b/drivers/watchdog/ixp2000_wdt.c index dc7548dcaf35..943ceffbd683 100644 --- a/drivers/watchdog/ixp2000_wdt.c +++ b/drivers/watchdog/ixp2000_wdt.c @@ -25,42 +25,45 @@ #include #include #include +#include #include -#include static int nowayout = WATCHDOG_NOWAYOUT; static unsigned int heartbeat = 60; /* (secs) Default is 1 minute */ static unsigned long wdt_status; +static spinlock_t wdt_lock; #define WDT_IN_USE 0 #define WDT_OK_TO_CLOSE 1 static unsigned long wdt_tick_rate; -static void -wdt_enable(void) +static void wdt_enable(void) { + spin_lock(&wdt_lock); ixp2000_reg_write(IXP2000_RESET0, *(IXP2000_RESET0) | WDT_RESET_ENABLE); ixp2000_reg_write(IXP2000_TWDE, WDT_ENABLE); ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); ixp2000_reg_write(IXP2000_T4_CTL, TIMER_DIVIDER_256 | TIMER_ENABLE); + spin_unlock(&wdt_lock); } -static void -wdt_disable(void) +static void wdt_disable(void) { + spin_lock(&wdt_lock); ixp2000_reg_write(IXP2000_T4_CTL, 0); + spin_unlock(&wdt_lock); } -static void -wdt_keepalive(void) +static void wdt_keepalive(void) { + spin_lock(&wdt_lock); ixp2000_reg_write(IXP2000_T4_CLD, heartbeat * wdt_tick_rate); + spin_unlock(&wdt_lock); } -static int -ixp2000_wdt_open(struct inode *inode, struct file *file) +static int ixp2000_wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(WDT_IN_USE, &wdt_status)) return -EBUSY; @@ -72,8 +75,8 @@ ixp2000_wdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static ssize_t -ixp2000_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t ixp2000_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { if (len) { if (!nowayout) { @@ -103,9 +106,8 @@ static struct watchdog_info ident = { .identity = "IXP2000 Watchdog", }; -static int -ixp2000_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long ixp2000_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int ret = -ENOTTY; int time; @@ -151,16 +153,13 @@ ixp2000_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, return ret; } -static int -ixp2000_wdt_release(struct inode *inode, struct file *file) +static int ixp2000_wdt_release(struct inode *inode, struct file *file) { - if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { + if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) wdt_disable(); - } else { + else printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " "timer will not stop\n"); - } - clear_bit(WDT_IN_USE, &wdt_status); clear_bit(WDT_OK_TO_CLOSE, &wdt_status); @@ -168,18 +167,16 @@ ixp2000_wdt_release(struct inode *inode, struct file *file) } -static const struct file_operations ixp2000_wdt_fops = -{ +static const struct file_operations ixp2000_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = ixp2000_wdt_write, - .ioctl = ixp2000_wdt_ioctl, + .unlocked_ioctl = ixp2000_wdt_ioctl, .open = ixp2000_wdt_open, .release = ixp2000_wdt_release, }; -static struct miscdevice ixp2000_wdt_miscdev = -{ +static struct miscdevice ixp2000_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &ixp2000_wdt_fops, @@ -191,9 +188,8 @@ static int __init ixp2000_wdt_init(void) printk(KERN_INFO "Unable to use IXP2000 watchdog due to IXP2800 erratum #25.\n"); return -EIO; } - wdt_tick_rate = (*IXP2000_T1_CLD * HZ) / 256; - + spin_lock_init(&wdt_lock); return misc_register(&ixp2000_wdt_miscdev); } -- cgit v1.2.3 From 20d35f3e50ea7e573f9568b9fce4e98523aaee5d Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:48 +0100 Subject: [WATCHDOG 22/57] ixp4xx_wdt: unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ixp4xx_wdt.c | 41 +++++++++++++++++------------------------ 1 file changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index 5864bb865cfe..24e624c847ae 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c @@ -30,40 +30,40 @@ static int nowayout = WATCHDOG_NOWAYOUT; static int heartbeat = 60; /* (secs) Default is 1 minute */ static unsigned long wdt_status; static unsigned long boot_status; +static spin_lock_t wdt_lock; #define WDT_TICK_RATE (IXP4XX_PERIPHERAL_BUS_CLOCK * 1000000UL) #define WDT_IN_USE 0 #define WDT_OK_TO_CLOSE 1 -static void -wdt_enable(void) +static void wdt_enable(void) { + spin_lock(&wdt_lock); *IXP4XX_OSWK = IXP4XX_WDT_KEY; *IXP4XX_OSWE = 0; *IXP4XX_OSWT = WDT_TICK_RATE * heartbeat; *IXP4XX_OSWE = IXP4XX_WDT_COUNT_ENABLE | IXP4XX_WDT_RESET_ENABLE; *IXP4XX_OSWK = 0; + spin_unlock(&wdt_lock); } -static void -wdt_disable(void) +static void wdt_disable(void) { + spin_lock(&wdt_lock); *IXP4XX_OSWK = IXP4XX_WDT_KEY; *IXP4XX_OSWE = 0; *IXP4XX_OSWK = 0; + spin_unlock(&wdt_lock); } -static int -ixp4xx_wdt_open(struct inode *inode, struct file *file) +static int ixp4xx_wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(WDT_IN_USE, &wdt_status)) return -EBUSY; clear_bit(WDT_OK_TO_CLOSE, &wdt_status); - wdt_enable(); - return nonseekable_open(inode, file); } @@ -87,7 +87,6 @@ ixp4xx_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) } wdt_enable(); } - return len; } @@ -98,9 +97,8 @@ static struct watchdog_info ident = { }; -static int -ixp4xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long ixp4xx_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int ret = -ENOTTY; int time; @@ -145,16 +143,13 @@ ixp4xx_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, return ret; } -static int -ixp4xx_wdt_release(struct inode *inode, struct file *file) +static int ixp4xx_wdt_release(struct inode *inode, struct file *file) { - if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) { + if (test_bit(WDT_OK_TO_CLOSE, &wdt_status)) wdt_disable(); - } else { + else printk(KERN_CRIT "WATCHDOG: Device closed unexpectedly - " "timer will not stop\n"); - } - clear_bit(WDT_IN_USE, &wdt_status); clear_bit(WDT_OK_TO_CLOSE, &wdt_status); @@ -167,7 +162,7 @@ static const struct file_operations ixp4xx_wdt_fops = .owner = THIS_MODULE, .llseek = no_llseek, .write = ixp4xx_wdt_write, - .ioctl = ixp4xx_wdt_ioctl, + .unlocked_ioctl = ixp4xx_wdt_ioctl, .open = ixp4xx_wdt_open, .release = ixp4xx_wdt_release, }; @@ -191,14 +186,12 @@ static int __init ixp4xx_wdt_init(void) return -ENODEV; } - + spin_lock_init(&wdt_lock); + boot_status = (*IXP4XX_OSST & IXP4XX_OSST_TIMER_WARM_RESET) ? + WDIOF_CARDRESET : 0; ret = misc_register(&ixp4xx_wdt_miscdev); if (ret == 0) printk("IXP4xx Watchdog Timer: heartbeat %d sec\n", heartbeat); - - boot_status = (*IXP4XX_OSST & IXP4XX_OSST_TIMER_WARM_RESET) ? - WDIOF_CARDRESET : 0; - return ret; } -- cgit v1.2.3 From f4fabce15bb9b547f934e2b6f0e5e01044108e4d Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:53 +0100 Subject: [WATCHDOG 23/57] ks8695_wdt: clean up, coding style, unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/ks8695_wdt.c | 119 ++++++++++++++++++++++-------------------- 1 file changed, 62 insertions(+), 57 deletions(-) diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c index df5a6b811ccd..6d052b80aa20 100644 --- a/drivers/watchdog/ks8695_wdt.c +++ b/drivers/watchdog/ks8695_wdt.c @@ -19,8 +19,8 @@ #include #include #include -#include -#include +#include +#include #include @@ -31,38 +31,44 @@ static int wdt_time = WDT_DEFAULT_TIME; static int nowayout = WATCHDOG_NOWAYOUT; module_param(wdt_time, int, 0); -MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default="__MODULE_STRING(WDT_DEFAULT_TIME) ")"); +MODULE_PARM_DESC(wdt_time, "Watchdog time in seconds. (default=" + __MODULE_STRING(WDT_DEFAULT_TIME) ")"); #ifdef CONFIG_WATCHDOG_NOWAYOUT module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); #endif static unsigned long ks8695wdt_busy; +static spinlock_t ks8695_lock; /* ......................................................................... */ /* * Disable the watchdog. */ -static void inline ks8695_wdt_stop(void) +static inline void ks8695_wdt_stop(void) { unsigned long tmcon; + spin_lock(&ks8695_lock); /* disable timer0 */ tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + spin_unlock(&ks8695_lock); } /* * Enable and reset the watchdog. */ -static void inline ks8695_wdt_start(void) +static inline void ks8695_wdt_start(void) { unsigned long tmcon; unsigned long tval = wdt_time * CLOCK_TICK_RATE; + spin_lock(&ks8695_lock); /* disable timer0 */ tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); @@ -73,19 +79,22 @@ static void inline ks8695_wdt_start(void) /* re-enable timer0 */ tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + spin_unlock(&ks8695_lock); } /* * Reload the watchdog timer. (ie, pat the watchdog) */ -static void inline ks8695_wdt_reload(void) +static inline void ks8695_wdt_reload(void) { unsigned long tmcon; + spin_lock(&ks8695_lock); /* disable, then re-enable timer0 */ tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON); __raw_writel(tmcon & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); __raw_writel(tmcon | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON); + spin_unlock(&ks8695_lock); } /* @@ -102,7 +111,8 @@ static int ks8695_wdt_settimeout(int new_time) if ((new_time <= 0) || (new_time > WDT_MAX_TIME)) return -EINVAL; - /* Set new watchdog time. It will be used when ks8695_wdt_start() is called. */ + /* Set new watchdog time. It will be used when + ks8695_wdt_start() is called. */ wdt_time = new_time; return 0; } @@ -128,9 +138,9 @@ static int ks8695_wdt_open(struct inode *inode, struct file *file) */ static int ks8695_wdt_close(struct inode *inode, struct file *file) { + /* Disable the watchdog when file is closed */ if (!nowayout) - ks8695_wdt_stop(); /* Disable the watchdog when file is closed */ - + ks8695_wdt_stop(); clear_bit(0, &ks8695wdt_busy); return 0; } @@ -143,60 +153,52 @@ static struct watchdog_info ks8695_wdt_info = { /* * Handle commands from user-space. */ -static int ks8695_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long ks8695_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_value; - switch(cmd) { - case WDIOC_KEEPALIVE: - ks8695_wdt_reload(); /* pat the watchdog */ - return 0; - - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ks8695_wdt_info, sizeof(ks8695_wdt_info)) ? -EFAULT : 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - - if (ks8695_wdt_settimeout(new_value)) - return -EINVAL; - - /* Enable new time value */ + switch (cmd) { + case WDIOC_KEEPALIVE: + ks8695_wdt_reload(); /* pat the watchdog */ + return 0; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ks8695_wdt_info, + sizeof(ks8695_wdt_info)) ? -EFAULT : 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_value, p)) + return -EFAULT; + if (ks8695_wdt_settimeout(new_value)) + return -EINVAL; + /* Enable new time value */ + ks8695_wdt_start(); + /* Return current value */ + return put_user(wdt_time, p); + case WDIOC_GETTIMEOUT: + return put_user(wdt_time, p); + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_SETOPTIONS: + if (get_user(new_value, p)) + return -EFAULT; + if (new_value & WDIOS_DISABLECARD) + ks8695_wdt_stop(); + if (new_value & WDIOS_ENABLECARD) ks8695_wdt_start(); - - /* Return current value */ - return put_user(wdt_time, p); - - case WDIOC_GETTIMEOUT: - return put_user(wdt_time, p); - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - - case WDIOC_SETOPTIONS: - if (get_user(new_value, p)) - return -EFAULT; - - if (new_value & WDIOS_DISABLECARD) - ks8695_wdt_stop(); - if (new_value & WDIOS_ENABLECARD) - ks8695_wdt_start(); - return 0; - - default: - return -ENOTTY; + return 0; + default: + return -ENOTTY; } } /* * Pat the watchdog whenever device is written to. */ -static ssize_t ks8695_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t ks8695_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { ks8695_wdt_reload(); /* pat the watchdog */ return len; @@ -207,7 +209,7 @@ static ssize_t ks8695_wdt_write(struct file *file, const char *data, size_t len, static const struct file_operations ks8695wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = ks8695_wdt_ioctl, + .unlocked_ioctl = ks8695_wdt_ioctl, .open = ks8695_wdt_open, .release = ks8695_wdt_close, .write = ks8695_wdt_write, @@ -231,7 +233,8 @@ static int __init ks8695wdt_probe(struct platform_device *pdev) if (res) return res; - printk("KS8695 Watchdog Timer enabled (%d seconds%s)\n", wdt_time, nowayout ? ", nowayout" : ""); + printk(KERN_INFO "KS8695 Watchdog Timer enabled (%d seconds%s)\n", + wdt_time, nowayout ? ", nowayout" : ""); return 0; } @@ -285,12 +288,14 @@ static struct platform_driver ks8695wdt_driver = { static int __init ks8695_wdt_init(void) { - /* Check that the heartbeat value is within range; if not reset to the default */ + spin_lock_init(&ks8695_lock); + /* Check that the heartbeat value is within range; + if not reset to the default */ if (ks8695_wdt_settimeout(wdt_time)) { ks8695_wdt_settimeout(WDT_DEFAULT_TIME); - pr_info("ks8695_wdt: wdt_time value must be 1 <= wdt_time <= %i, using %d\n", wdt_time, WDT_MAX_TIME); + pr_info("ks8695_wdt: wdt_time value must be 1 <= wdt_time <= %i, using %d\n", + wdt_time, WDT_MAX_TIME); } - return platform_driver_register(&ks8695wdt_driver); } -- cgit v1.2.3 From 325ea4d3a8a90b19d7a076714d0f8f238a5a6a69 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:06:59 +0100 Subject: [WATCHDOG 24/57] machzwd: clean up, coding style, unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/machzwd.c | 108 +++++++++++++++++---------------------------- 1 file changed, 40 insertions(+), 68 deletions(-) diff --git a/drivers/watchdog/machzwd.c b/drivers/watchdog/machzwd.c index 6905135a776c..2dfc27559bf7 100644 --- a/drivers/watchdog/machzwd.c +++ b/drivers/watchdog/machzwd.c @@ -40,9 +40,9 @@ #include #include #include +#include +#include -#include -#include #include /* ports */ @@ -95,7 +95,9 @@ MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); #define PFX "machzwd" @@ -114,7 +116,7 @@ static struct watchdog_info zf_info = { * 3 = GEN_SCI * defaults to GEN_RESET (0) */ -static int action = 0; +static int action; module_param(action, int, 0); MODULE_PARM_DESC(action, "after watchdog resets, generate: 0 = RESET(*) 1 = SMI 2 = NMI 3 = SCI"); @@ -123,10 +125,9 @@ static void zf_ping(unsigned long data); static int zf_action = GEN_RESET; static unsigned long zf_is_open; static char zf_expect_close; -static DEFINE_SPINLOCK(zf_lock); static DEFINE_SPINLOCK(zf_port_lock); static DEFINE_TIMER(zf_timer, zf_ping, 0, 0); -static unsigned long next_heartbeat = 0; +static unsigned long next_heartbeat; /* timeout for user land heart beat (10 seconds) */ @@ -171,13 +172,13 @@ static inline void zf_set_control(unsigned short new) static inline void zf_set_timer(unsigned short new, unsigned char n) { - switch(n){ - case WD1: - zf_writew(COUNTER_1, new); - case WD2: - zf_writeb(COUNTER_2, new > 0xff ? 0xff : new); - default: - return; + switch (n) { + case WD1: + zf_writew(COUNTER_1, new); + case WD2: + zf_writeb(COUNTER_2, new > 0xff ? 0xff : new); + default: + return; } } @@ -241,10 +242,8 @@ static void zf_ping(unsigned long data) zf_writeb(COUNTER_2, 0xff); - if(time_before(jiffies, next_heartbeat)){ - + if (time_before(jiffies, next_heartbeat)) { dprintk("time_before: %ld\n", next_heartbeat - jiffies); - /* * reset event is activated by transition from 0 to 1 on * RESET_WD1 bit and we assume that it is already zero... @@ -261,24 +260,21 @@ static void zf_ping(unsigned long data) spin_unlock_irqrestore(&zf_port_lock, flags); mod_timer(&zf_timer, jiffies + ZF_HW_TIMEO); - }else{ + } else printk(KERN_CRIT PFX ": I will reset your machine\n"); - } } static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { /* See if we got the magic character */ - if(count){ - + if (count) { /* * no need to check for close confirmation * no way to disable watchdog ;) */ if (!nowayout) { size_t ofs; - /* * note: just in case someone wrote the magic character * five months ago... @@ -286,11 +282,11 @@ static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, zf_expect_close = 0; /* now scan */ - for (ofs = 0; ofs != count; ofs++){ + for (ofs = 0; ofs != count; ofs++) { char c; if (get_user(c, buf + ofs)) return -EFAULT; - if (c == 'V'){ + if (c == 'V') { zf_expect_close = 42; dprintk("zf_expect_close = 42\n"); } @@ -303,14 +299,11 @@ static ssize_t zf_write(struct file *file, const char __user *buf, size_t count, */ next_heartbeat = jiffies + ZF_USER_TIMEO; dprintk("user ping at %ld\n", jiffies); - } - return count; } -static int zf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long zf_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -319,55 +312,38 @@ static int zf_ioctl(struct inode *inode, struct file *file, unsigned int cmd, if (copy_to_user(argp, &zf_info, sizeof(zf_info))) return -EFAULT; break; - case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: zf_ping(0); break; - default: return -ENOTTY; } - return 0; } static int zf_open(struct inode *inode, struct file *file) { - spin_lock(&zf_lock); - if(test_and_set_bit(0, &zf_is_open)) { - spin_unlock(&zf_lock); + if (test_and_set_bit(0, &zf_is_open)) return -EBUSY; - } - if (nowayout) __module_get(THIS_MODULE); - - spin_unlock(&zf_lock); - zf_timer_on(); - return nonseekable_open(inode, file); } static int zf_close(struct inode *inode, struct file *file) { - if(zf_expect_close == 42){ + if (zf_expect_close == 42) zf_timer_off(); - } else { + else { del_timer(&zf_timer); printk(KERN_ERR PFX ": device file closed unexpectedly. Will not stop the WDT!\n"); } - - spin_lock(&zf_lock); clear_bit(0, &zf_is_open); - spin_unlock(&zf_lock); - zf_expect_close = 0; - return 0; } @@ -378,23 +354,18 @@ static int zf_close(struct inode *inode, struct file *file) static int zf_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code == SYS_DOWN || code == SYS_HALT){ + if (code == SYS_DOWN || code == SYS_HALT) zf_timer_off(); - } - return NOTIFY_DONE; } - - - static const struct file_operations zf_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = zf_write, - .ioctl = zf_ioctl, - .open = zf_open, - .release = zf_close, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = zf_write, + .unlocked_ioctl = zf_ioctl, + .open = zf_open, + .release = zf_close, }; static struct miscdevice zf_miscdev = { @@ -402,7 +373,7 @@ static struct miscdevice zf_miscdev = { .name = "watchdog", .fops = &zf_fops, }; - + /* * The device needs to learn about soft shutdowns in order to @@ -423,22 +394,23 @@ static int __init zf_init(void) { int ret; - printk(KERN_INFO PFX ": MachZ ZF-Logic Watchdog driver initializing.\n"); + printk(KERN_INFO PFX + ": MachZ ZF-Logic Watchdog driver initializing.\n"); ret = zf_get_ZFL_version(); - if ((!ret) || (ret == 0xffff)) { + if (!ret || ret == 0xffff) { printk(KERN_WARNING PFX ": no ZF-Logic found\n"); return -ENODEV; } - if((action <= 3) && (action >= 0)){ - zf_action = zf_action>>action; - } else + if (action <= 3 && action >= 0) + zf_action = zf_action >> action; + else action = 0; zf_show_action(action); - if(!request_region(ZF_IOBASE, 3, "MachZ ZFL WDT")){ + if (!request_region(ZF_IOBASE, 3, "MachZ ZFL WDT")) { printk(KERN_ERR "cannot reserve I/O ports at %d\n", ZF_IOBASE); ret = -EBUSY; @@ -446,14 +418,14 @@ static int __init zf_init(void) } ret = register_reboot_notifier(&zf_notifier); - if(ret){ + if (ret) { printk(KERN_ERR "can't register reboot notifier (err=%d)\n", ret); goto no_reboot; } ret = misc_register(&zf_miscdev); - if (ret){ + if (ret) { printk(KERN_ERR "can't misc_register on minor=%d\n", WATCHDOG_MINOR); goto no_misc; -- cgit v1.2.3 From 3930964532f8e454910cbe0d9909e98a02d9f552 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:04 +0100 Subject: [WATCHDOG 25/57] mixcomwd: coding style locking, unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/mixcomwd.c | 133 +++++++++++++++++++++----------------------- 1 file changed, 63 insertions(+), 70 deletions(-) diff --git a/drivers/watchdog/mixcomwd.c b/drivers/watchdog/mixcomwd.c index 1adf1d56027d..2248a8187590 100644 --- a/drivers/watchdog/mixcomwd.c +++ b/drivers/watchdog/mixcomwd.c @@ -29,7 +29,8 @@ * - support for one more type board * * Version 0.5 (2001/12/14) Matt Domsch - * - added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT + * - added nowayout module option to override + * CONFIG_WATCHDOG_NOWAYOUT * * Version 0.6 (2002/04/12): Rob Radez * - make mixcomwd_opened unsigned, @@ -53,8 +54,8 @@ #include #include #include -#include -#include +#include +#include /* * We have two types of cards that can be probed: @@ -108,18 +109,19 @@ static char expect_close; static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static void mixcomwd_ping(void) { - outb_p(55,watchdog_port); + outb_p(55, watchdog_port); return; } static void mixcomwd_timerfun(unsigned long d) { mixcomwd_ping(); - mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); } @@ -129,22 +131,22 @@ static void mixcomwd_timerfun(unsigned long d) static int mixcomwd_open(struct inode *inode, struct file *file) { - if(test_and_set_bit(0,&mixcomwd_opened)) { + if (test_and_set_bit(0, &mixcomwd_opened)) return -EBUSY; - } + mixcomwd_ping(); - if (nowayout) { + if (nowayout) /* * fops_get() code via open() has already done * a try_module_get() so it is safe to do the * __module_get(). */ __module_get(THIS_MODULE); - } else { - if(mixcomwd_timer_alive) { + else { + if (mixcomwd_timer_alive) { del_timer(&mixcomwd_timer); - mixcomwd_timer_alive=0; + mixcomwd_timer_alive = 0; } } return nonseekable_open(inode, file); @@ -153,26 +155,27 @@ static int mixcomwd_open(struct inode *inode, struct file *file) static int mixcomwd_release(struct inode *inode, struct file *file) { if (expect_close == 42) { - if(mixcomwd_timer_alive) { - printk(KERN_ERR PFX "release called while internal timer alive"); + if (mixcomwd_timer_alive) { + printk(KERN_ERR PFX + "release called while internal timer alive"); return -EBUSY; } - mixcomwd_timer_alive=1; + mixcomwd_timer_alive = 1; mod_timer(&mixcomwd_timer, jiffies + 5 * HZ); - } else { - printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); - } + } else + printk(KERN_CRIT PFX + "WDT device closed unexpectedly. WDT will not stop!\n"); - clear_bit(0,&mixcomwd_opened); - expect_close=0; + clear_bit(0, &mixcomwd_opened); + expect_close = 0; return 0; } -static ssize_t mixcomwd_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) +static ssize_t mixcomwd_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) { - if(len) - { + if (len) { if (!nowayout) { size_t i; @@ -192,8 +195,8 @@ static ssize_t mixcomwd_write(struct file *file, const char __user *data, size_t return len; } -static int mixcomwd_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mixcomwd_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -204,32 +207,23 @@ static int mixcomwd_ioctl(struct inode *inode, struct file *file, .identity = "MixCOM watchdog", }; - switch(cmd) - { - case WDIOC_GETSTATUS: - status=mixcomwd_opened; - if (!nowayout) { - status|=mixcomwd_timer_alive; - } - if (copy_to_user(p, &status, sizeof(int))) { - return -EFAULT; - } - break; - case WDIOC_GETBOOTSTATUS: - if (copy_to_user(p, &status, sizeof(int))) { - return -EFAULT; - } - break; - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) { - return -EFAULT; - } - break; - case WDIOC_KEEPALIVE: - mixcomwd_ping(); - break; - default: - return -ENOTTY; + switch (cmd) { + case WDIOC_GETSTATUS: + status = mixcomwd_opened; + if (!nowayout) + status |= mixcomwd_timer_alive; + return put_user(status, p); + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; + case WDIOC_KEEPALIVE: + mixcomwd_ping(); + break; + default: + return -ENOTTY; } return 0; } @@ -238,7 +232,7 @@ static const struct file_operations mixcomwd_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = mixcomwd_write, - .ioctl = mixcomwd_ioctl, + .unlocked_ioctl = mixcomwd_ioctl, .open = mixcomwd_open, .release = mixcomwd_release, }; @@ -253,15 +247,14 @@ static int __init checkcard(int port, int card_id) { int id; - if (!request_region(port, 1, "MixCOM watchdog")) { + if (!request_region(port, 1, "MixCOM watchdog")) return 0; - } - id=inb_p(port); - if (card_id==MIXCOM_ID) + id = inb_p(port); + if (card_id == MIXCOM_ID) id &= 0x3f; - if (id!=card_id) { + if (id != card_id) { release_region(port, 1); return 0; } @@ -270,9 +263,7 @@ static int __init checkcard(int port, int card_id) static int __init mixcomwd_init(void) { - int i; - int ret; - int found=0; + int i, ret, found = 0; for (i = 0; !found && mixcomwd_io_info[i].ioport != 0; i++) { if (checkcard(mixcomwd_io_info[i].ioport, @@ -283,20 +274,22 @@ static int __init mixcomwd_init(void) } if (!found) { - printk(KERN_ERR PFX "No card detected, or port not available.\n"); + printk(KERN_ERR PFX + "No card detected, or port not available.\n"); return -ENODEV; } ret = misc_register(&mixcomwd_miscdev); - if (ret) - { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + if (ret) { + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto error_misc_register_watchdog; } - printk(KERN_INFO "MixCOM watchdog driver v%s, watchdog port at 0x%3x\n", - VERSION, watchdog_port); + printk(KERN_INFO + "MixCOM watchdog driver v%s, watchdog port at 0x%3x\n", + VERSION, watchdog_port); return 0; @@ -309,15 +302,15 @@ error_misc_register_watchdog: static void __exit mixcomwd_exit(void) { if (!nowayout) { - if(mixcomwd_timer_alive) { + if (mixcomwd_timer_alive) { printk(KERN_WARNING PFX "I quit now, hardware will" " probably reboot!\n"); del_timer_sync(&mixcomwd_timer); - mixcomwd_timer_alive=0; + mixcomwd_timer_alive = 0; } } misc_deregister(&mixcomwd_miscdev); - release_region(watchdog_port,1); + release_region(watchdog_port, 1); } module_init(mixcomwd_init); -- cgit v1.2.3 From f26ef3dc69467e135e2b9555e44a088aee5c7d8f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:09 +0100 Subject: [WATCHDOG 26/57] mpc watchdog: clean up and locking Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/mpc5200_wdt.c | 20 ++++++++++++-------- drivers/watchdog/mpc83xx_wdt.c | 19 ++++++++++--------- drivers/watchdog/mpc8xx_wdt.c | 37 +++++++++++++++++++------------------ 3 files changed, 41 insertions(+), 35 deletions(-) diff --git a/drivers/watchdog/mpc5200_wdt.c b/drivers/watchdog/mpc5200_wdt.c index 80a91d4cea11..ce1811d5d6b1 100644 --- a/drivers/watchdog/mpc5200_wdt.c +++ b/drivers/watchdog/mpc5200_wdt.c @@ -4,8 +4,8 @@ #include #include #include -#include -#include +#include +#include #include @@ -57,7 +57,8 @@ static int mpc5200_wdt_start(struct mpc5200_wdt *wdt) /* set timeout, with maximum prescaler */ out_be32(&wdt->regs->count, 0x0 | wdt->count); /* enable watchdog */ - out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | GPT_MODE_MS_TIMER); + out_be32(&wdt->regs->mode, GPT_MODE_CE | GPT_MODE_WDT | + GPT_MODE_MS_TIMER); spin_unlock(&wdt->io_lock); return 0; @@ -66,7 +67,8 @@ static int mpc5200_wdt_ping(struct mpc5200_wdt *wdt) { spin_lock(&wdt->io_lock); /* writing A5 to OCPW resets the watchdog */ - out_be32(&wdt->regs->mode, 0xA5000000 | (0xffffff & in_be32(&wdt->regs->mode))); + out_be32(&wdt->regs->mode, 0xA5000000 | + (0xffffff & in_be32(&wdt->regs->mode))); spin_unlock(&wdt->io_lock); return 0; } @@ -92,8 +94,8 @@ static struct watchdog_info mpc5200_wdt_info = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = "mpc5200 watchdog on GPT0", }; -static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mpc5200_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { struct mpc5200_wdt *wdt = file->private_data; int __user *data = (int __user *)arg; @@ -103,7 +105,7 @@ static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, switch (cmd) { case WDIOC_GETSUPPORT: ret = copy_to_user(data, &mpc5200_wdt_info, - sizeof(mpc5200_wdt_info)); + sizeof(mpc5200_wdt_info)); if (ret) ret = -EFAULT; break; @@ -135,6 +137,7 @@ static int mpc5200_wdt_ioctl(struct inode *inode, struct file *file, } return ret; } + static int mpc5200_wdt_open(struct inode *inode, struct file *file) { /* /dev/watchdog can only be opened once */ @@ -167,7 +170,8 @@ static const struct file_operations mpc5200_wdt_fops = { }; /* module operations */ -static int mpc5200_wdt_probe(struct of_device *op, const struct of_device_id *match) +static int mpc5200_wdt_probe(struct of_device *op, + const struct of_device_id *match) { struct mpc5200_wdt *wdt; int err; diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c index b16c5cd972eb..109eea0df2d0 100644 --- a/drivers/watchdog/mpc83xx_wdt.c +++ b/drivers/watchdog/mpc83xx_wdt.c @@ -22,8 +22,8 @@ #include #include #include -#include -#include +#include +#include struct mpc83xx_wdt { __be32 res0; @@ -42,11 +42,13 @@ static struct mpc83xx_wdt __iomem *wd_base; static u16 timeout = 0xffff; module_param(timeout, ushort, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in ticks. (0start, sizeof (struct mpc83xx_wdt)); - + wd_base = ioremap(r->start, sizeof(struct mpc83xx_wdt)); if (wd_base == NULL) { ret = -ENOMEM; goto err_out; diff --git a/drivers/watchdog/mpc8xx_wdt.c b/drivers/watchdog/mpc8xx_wdt.c index 85b5734403a5..1336425acf20 100644 --- a/drivers/watchdog/mpc8xx_wdt.c +++ b/drivers/watchdog/mpc8xx_wdt.c @@ -16,36 +16,35 @@ #include #include #include -#include -#include +#include +#include #include static unsigned long wdt_opened; static int wdt_status; +static spinlock_t wdt_lock; static void mpc8xx_wdt_handler_disable(void) { volatile uint __iomem *piscr; - piscr = (uint *)&((immap_t*)IMAP_ADDR)->im_sit.sit_piscr; + piscr = (uint *)&((immap_t *)IMAP_ADDR)->im_sit.sit_piscr; if (!m8xx_has_internal_rtc) m8xx_wdt_stop_timer(); else out_be32(piscr, in_be32(piscr) & ~(PISCR_PIE | PISCR_PTE)); - printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler deactivated\n"); } static void mpc8xx_wdt_handler_enable(void) { volatile uint __iomem *piscr; - piscr = (uint *)&((immap_t*)IMAP_ADDR)->im_sit.sit_piscr; + piscr = (uint *)&((immap_t *)IMAP_ADDR)->im_sit.sit_piscr; if (!m8xx_has_internal_rtc) m8xx_wdt_install_timer(); else out_be32(piscr, in_be32(piscr) | PISCR_PIE | PISCR_PTE); - printk(KERN_NOTICE "mpc8xx_wdt: keep-alive handler activated\n"); } @@ -53,37 +52,34 @@ static int mpc8xx_wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(0, &wdt_opened)) return -EBUSY; - m8xx_wdt_reset(); mpc8xx_wdt_handler_disable(); - return nonseekable_open(inode, file); } static int mpc8xx_wdt_release(struct inode *inode, struct file *file) { m8xx_wdt_reset(); - #if !defined(CONFIG_WATCHDOG_NOWAYOUT) mpc8xx_wdt_handler_enable(); #endif - clear_bit(0, &wdt_opened); - return 0; } -static ssize_t mpc8xx_wdt_write(struct file *file, const char *data, size_t len, - loff_t * ppos) +static ssize_t mpc8xx_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { - if (len) + if (len) { + spin_lock(&wdt_lock); m8xx_wdt_reset(); - + spin_unlock(&wdt_lock); + } return len; } -static int mpc8xx_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mpc8xx_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int timeout; static struct watchdog_info info = { @@ -112,15 +108,19 @@ static int mpc8xx_wdt_ioctl(struct inode *inode, struct file *file, return -EOPNOTSUPP; case WDIOC_KEEPALIVE: + spin_lock(&wdt_lock); m8xx_wdt_reset(); wdt_status |= WDIOF_KEEPALIVEPING; + spin_unlock(&wdt_lock); break; case WDIOC_SETTIMEOUT: return -EOPNOTSUPP; case WDIOC_GETTIMEOUT: + spin_lock(&wdt_lock); timeout = m8xx_wdt_get_timeout(); + spin_unlock(&wdt_lock); if (put_user(timeout, (int *)arg)) return -EFAULT; break; @@ -136,7 +136,7 @@ static const struct file_operations mpc8xx_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = mpc8xx_wdt_write, - .ioctl = mpc8xx_wdt_ioctl, + .unlocked_ioctl = mpc8xx_wdt_ioctl, .open = mpc8xx_wdt_open, .release = mpc8xx_wdt_release, }; @@ -149,6 +149,7 @@ static struct miscdevice mpc8xx_wdt_miscdev = { static int __init mpc8xx_wdt_init(void) { + spin_lock_init(&wdt_lock); return misc_register(&mpc8xx_wdt_miscdev); } -- cgit v1.2.3 From 83ab1a53f219c8139199633f60ab0ef88ef18c54 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:15 +0100 Subject: [WATCHDOG 27/57] mpcore watchdog: unlocked_ioctl and BKl work Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/mpcore_wdt.c | 53 ++++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 009573b81496..5e58f8b73d00 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -29,9 +29,9 @@ #include #include #include +#include #include -#include struct mpcore_wdt { unsigned long timer_alive; @@ -43,17 +43,20 @@ struct mpcore_wdt { }; static struct platform_device *mpcore_wdt_dev; - extern unsigned int mpcore_timer_rate; #define TIMER_MARGIN 60 static int mpcore_margin = TIMER_MARGIN; module_param(mpcore_margin, int, 0); -MODULE_PARM_DESC(mpcore_margin, "MPcore timer margin in seconds. (0base + TWD_WDOG_INTSTAT)) { - dev_printk(KERN_CRIT, wdt->dev, "Triggered - Reboot ignored.\n"); - + dev_printk(KERN_CRIT, wdt->dev, + "Triggered - Reboot ignored.\n"); /* Clear the interrupt on the watchdog */ writel(1, wdt->base + TWD_WDOG_INTSTAT); - return IRQ_HANDLED; } - return IRQ_NONE; } @@ -96,22 +97,26 @@ static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt) count = (mpcore_timer_rate / 256) * mpcore_margin; /* Reload the counter */ + spin_lock(&wdt_lock); writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD); - wdt->perturb = wdt->perturb ? 0 : 1; + spin_unlock(&wdt_lock); } static void mpcore_wdt_stop(struct mpcore_wdt *wdt) { + spin_lock(&wdt_lock); writel(0x12345678, wdt->base + TWD_WDOG_DISABLE); writel(0x87654321, wdt->base + TWD_WDOG_DISABLE); writel(0x0, wdt->base + TWD_WDOG_CONTROL); + spin_unlock(&wdt_lock); } static void mpcore_wdt_start(struct mpcore_wdt *wdt) { dev_printk(KERN_INFO, wdt->dev, "enabling watchdog.\n"); + spin_lock(&wdt_lock); /* This loads the count register but does NOT start the count yet */ mpcore_wdt_keepalive(wdt); @@ -122,6 +127,7 @@ static void mpcore_wdt_start(struct mpcore_wdt *wdt) /* Enable watchdog - prescale=256, watchdog mode=1, enable=1 */ writel(0x0000FF09, wdt->base + TWD_WDOG_CONTROL); } + spin_unlock(&wdt_lock); } static int mpcore_wdt_set_heartbeat(int t) @@ -164,10 +170,11 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file) * Shut off the timer. * Lock it in if it's a module and we set nowayout */ - if (wdt->expect_close == 42) { + if (wdt->expect_close == 42) mpcore_wdt_stop(wdt); - } else { - dev_printk(KERN_CRIT, wdt->dev, "unexpected close, not stopping watchdog!\n"); + else { + dev_printk(KERN_CRIT, wdt->dev, + "unexpected close, not stopping watchdog!\n"); mpcore_wdt_keepalive(wdt); } clear_bit(0, &wdt->timer_alive); @@ -175,7 +182,8 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file) return 0; } -static ssize_t mpcore_wdt_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t mpcore_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { struct mpcore_wdt *wdt = file->private_data; @@ -210,8 +218,8 @@ static struct watchdog_info ident = { .identity = "MPcore Watchdog", }; -static int mpcore_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { struct mpcore_wdt *wdt = file->private_data; int ret; @@ -301,7 +309,7 @@ static const struct file_operations mpcore_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = mpcore_wdt_write, - .ioctl = mpcore_wdt_ioctl, + .unlocked_ioctl = mpcore_wdt_ioctl, .open = mpcore_wdt_open, .release = mpcore_wdt_release, }; @@ -349,14 +357,17 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev) mpcore_wdt_miscdev.parent = &dev->dev; ret = misc_register(&mpcore_wdt_miscdev); if (ret) { - dev_printk(KERN_ERR, _dev, "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + dev_printk(KERN_ERR, _dev, + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto err_misc; } - ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED, "mpcore_wdt", wdt); + ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED, + "mpcore_wdt", wdt); if (ret) { - dev_printk(KERN_ERR, _dev, "cannot register IRQ%d for watchdog\n", wdt->irq); + dev_printk(KERN_ERR, _dev, + "cannot register IRQ%d for watchdog\n", wdt->irq); goto err_irq; } @@ -415,7 +426,7 @@ static int __init mpcore_wdt_init(void) */ if (mpcore_wdt_set_heartbeat(mpcore_margin)) { mpcore_wdt_set_heartbeat(TIMER_MARGIN); - printk(KERN_INFO "mpcore_margin value must be 0 Date: Mon, 19 May 2008 14:07:21 +0100 Subject: [WATCHDOG 28/57] mtx-1_wdt: clean up, coding style, unlocked ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/mtx-1_wdt.c | 107 +++++++++++++++++++++---------------------- 1 file changed, 52 insertions(+), 55 deletions(-) diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index a8e67383784e..e0b8cdfa5e70 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c @@ -1,7 +1,8 @@ /* * Driver for the MTX-1 Watchdog. * - * (C) Copyright 2005 4G Systems , All Rights Reserved. + * (C) Copyright 2005 4G Systems , + * All Rights Reserved. * http://www.4g-systems.biz * * (C) Copyright 2007 OpenWrt.org, Florian Fainelli @@ -46,12 +47,11 @@ #include #include #include - -#include -#include +#include +#include +#include #include -#include #define MTX1_WDT_INTERVAL (5 * HZ) @@ -59,6 +59,7 @@ static int ticks = 100 * HZ; static struct { struct completion stop; + spinlock_t lock; int running; struct timer_list timer; int queue; @@ -71,6 +72,7 @@ static void mtx1_wdt_trigger(unsigned long unused) { u32 tmp; + spin_lock(&mtx1_wdt_device.lock); if (mtx1_wdt_device.running) ticks--; /* @@ -79,13 +81,13 @@ static void mtx1_wdt_trigger(unsigned long unused) tmp = au_readl(GPIO2_DIR); tmp = (tmp & ~(1 << mtx1_wdt_device.gpio)) | ((~tmp) & (1 << mtx1_wdt_device.gpio)); - au_writel (tmp, GPIO2_DIR); + au_writel(tmp, GPIO2_DIR); if (mtx1_wdt_device.queue && ticks) mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); - else { + else complete(&mtx1_wdt_device.stop); - } + spin_unlock(&mtx1_wdt_device.lock); } static void mtx1_wdt_reset(void) @@ -96,23 +98,25 @@ static void mtx1_wdt_reset(void) static void mtx1_wdt_start(void) { + spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (!mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 1; gpio_set_value(mtx1_wdt_device.gpio, 1); mod_timer(&mtx1_wdt_device.timer, jiffies + MTX1_WDT_INTERVAL); } mtx1_wdt_device.running++; + spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); } static int mtx1_wdt_stop(void) { + spin_lock_irqsave(&mtx1_wdt_device.lock, flags); if (mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 0; gpio_set_value(mtx1_wdt_device.gpio, 0); } - ticks = mtx1_wdt_device.default_ticks; - + spin_unlock_irqrestore(&mtx1_wdt_device.lock, flags); return 0; } @@ -122,7 +126,6 @@ static int mtx1_wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(0, &mtx1_wdt_device.inuse)) return -EBUSY; - return nonseekable_open(inode, file); } @@ -133,54 +136,51 @@ static int mtx1_wdt_release(struct inode *inode, struct file *file) return 0; } -static int mtx1_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +static long mtx1_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; + int __user *p = (int __user *)argp; unsigned int value; - static struct watchdog_info ident = - { + static const struct watchdog_info ident = { .options = WDIOF_CARDRESET, .identity = "MTX-1 WDT", }; - switch(cmd) { - case WDIOC_KEEPALIVE: - mtx1_wdt_reset(); - break; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - if ( copy_to_user(argp, &value, sizeof(int)) ) - return -EFAULT; - break; - case WDIOC_GETSUPPORT: - if ( copy_to_user(argp, &ident, sizeof(ident)) ) - return -EFAULT; - break; - case WDIOC_SETOPTIONS: - if ( copy_from_user(&value, argp, sizeof(int)) ) - return -EFAULT; - switch(value) { - case WDIOS_ENABLECARD: - mtx1_wdt_start(); - break; - case WDIOS_DISABLECARD: - return mtx1_wdt_stop(); - default: - return -EINVAL; - } - break; - default: - return -ENOTTY; + switch (cmd) { + case WDIOC_KEEPALIVE: + mtx1_wdt_reset(); + break; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + put_user(0, p); + break; + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; + case WDIOC_SETOPTIONS: + if (get_user(value, p)) + return -EFAULT; + if (value & WDIOS_ENABLECARD) + mtx1_wdt_start(); + else if (value & WDIOS_DISABLECARD) + mtx1_wdt_stop(); + else + return -EINVAL; + return 0; + default: + return -ENOTTY; } return 0; } -static ssize_t mtx1_wdt_write(struct file *file, const char *buf, size_t count, loff_t *ppos) +static ssize_t mtx1_wdt_write(struct file *file, const char *buf, + size_t count, loff_t *ppos) { if (!count) return -EIO; - mtx1_wdt_reset(); return count; } @@ -188,7 +188,7 @@ static ssize_t mtx1_wdt_write(struct file *file, const char *buf, size_t count, static const struct file_operations mtx1_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .ioctl = mtx1_wdt_ioctl, + .unlocked_ioctl = mtx1_wdt_ioctl, .open = mtx1_wdt_open, .write = mtx1_wdt_write, .release = mtx1_wdt_release @@ -208,29 +208,26 @@ static int mtx1_wdt_probe(struct platform_device *pdev) mtx1_wdt_device.gpio = pdev->resource[0].start; - if ((ret = misc_register(&mtx1_wdt_misc)) < 0) { - printk(KERN_ERR " mtx-1_wdt : failed to register\n"); - return ret; - } - + spin_lock_init(&mtx1_wdt_device.lock); init_completion(&mtx1_wdt_device.stop); mtx1_wdt_device.queue = 0; - clear_bit(0, &mtx1_wdt_device.inuse); - setup_timer(&mtx1_wdt_device.timer, mtx1_wdt_trigger, 0L); - mtx1_wdt_device.default_ticks = ticks; + ret = misc_register(&mtx1_wdt_misc); + if (ret < 0) { + printk(KERN_ERR " mtx-1_wdt : failed to register\n"); + return ret; + } mtx1_wdt_start(); - printk(KERN_INFO "MTX-1 Watchdog driver\n"); - return 0; } static int mtx1_wdt_remove(struct platform_device *pdev) { + /* FIXME: do we need to lock this test ? */ if (mtx1_wdt_device.queue) { mtx1_wdt_device.queue = 0; wait_for_completion(&mtx1_wdt_device.stop); -- cgit v1.2.3 From a86b849868f40f83781f7a7e32e5e5ef939dc570 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:26 +0100 Subject: [WATCHDOG 29/57] mv64x60_wdt: clean up and locking checks Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/mv64x60_wdt.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/watchdog/mv64x60_wdt.c b/drivers/watchdog/mv64x60_wdt.c index b59ca3273967..ac09fe4d9573 100644 --- a/drivers/watchdog/mv64x60_wdt.c +++ b/drivers/watchdog/mv64x60_wdt.c @@ -8,7 +8,7 @@ * and services the watchdog. * * Derived from mpc8xx_wdt.c, with the following copyright. - * + * * 2002 (c) Florian Schirmer This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express @@ -24,8 +24,8 @@ #include #include -#include -#include +#include +#include #define MV64x60_WDT_WDC_OFFSET 0 @@ -61,7 +61,9 @@ static DEFINE_SPINLOCK(mv64x60_wdt_spinlock); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static int mv64x60_wdt_toggle_wdc(int enabled_predicate, int field_shift) { @@ -150,7 +152,7 @@ static int mv64x60_wdt_release(struct inode *inode, struct file *file) } static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, - size_t len, loff_t * ppos) + size_t len, loff_t *ppos) { if (len) { if (!nowayout) { @@ -160,7 +162,7 @@ static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, for (i = 0; i != len; i++) { char c; - if(get_user(c, data + i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -172,8 +174,8 @@ static ssize_t mv64x60_wdt_write(struct file *file, const char __user *data, return len; } -static int mv64x60_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long mv64x60_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int timeout; int options; @@ -240,7 +242,7 @@ static const struct file_operations mv64x60_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = mv64x60_wdt_write, - .ioctl = mv64x60_wdt_ioctl, + .unlocked_ioctl = mv64x60_wdt_ioctl, .open = mv64x60_wdt_open, .release = mv64x60_wdt_release, }; -- cgit v1.2.3 From 12b9df7d21d0eedfaaee925f8f9c9aafb1cafa2f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:32 +0100 Subject: [WATCHDOG 30/57] omap_wdt: locking, unlocked_ioctl, tidy Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/omap_wdt.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 74bc39aa1ce8..ccdf069792d9 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -41,9 +41,9 @@ #include #include -#include -#include -#include +#include +#include +#include #include @@ -54,11 +54,12 @@ module_param(timer_margin, uint, 0); MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); static int omap_wdt_users; -static struct clk *armwdt_ck = NULL; -static struct clk *mpu_wdt_ick = NULL; -static struct clk *mpu_wdt_fck = NULL; +static struct clk *armwdt_ck; +static struct clk *mpu_wdt_ick; +static struct clk *mpu_wdt_fck; static unsigned int wdt_trgr_pattern = 0x1234; +static spinlock_t wdt_lock; static void omap_wdt_ping(void) { @@ -174,22 +175,23 @@ static int omap_wdt_release(struct inode *inode, struct file *file) return 0; } -static ssize_t -omap_wdt_write(struct file *file, const char __user *data, +static ssize_t omap_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) { /* Refresh LOAD_TIME. */ - if (len) + if (len) { + spin_lock(&wdt_lock); omap_wdt_ping(); + spin_unlock(&wdt_lock); + } return len; } -static int -omap_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long omap_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_margin; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .identity = "OMAP Watchdog", .options = WDIOF_SETTIMEOUT, .firmware_version = 0, @@ -211,18 +213,22 @@ omap_wdt_ioctl(struct inode *inode, struct file *file, return put_user(omap_prcm_get_reset_sources(), (int __user *)arg); case WDIOC_KEEPALIVE: + spin_lock(&wdt_lock); omap_wdt_ping(); + spin_unlock(&wdt_lock); return 0; case WDIOC_SETTIMEOUT: if (get_user(new_margin, (int __user *)arg)) return -EFAULT; omap_wdt_adjust_timeout(new_margin); + spin_lock(&wdt_lock); omap_wdt_disable(); omap_wdt_set_timeout(); omap_wdt_enable(); omap_wdt_ping(); + spin_unlock(&wdt_lock); /* Fall */ case WDIOC_GETTIMEOUT: return put_user(timer_margin, (int __user *)arg); @@ -232,7 +238,7 @@ omap_wdt_ioctl(struct inode *inode, struct file *file, static const struct file_operations omap_wdt_fops = { .owner = THIS_MODULE, .write = omap_wdt_write, - .ioctl = omap_wdt_ioctl, + .unlocked_ioctl = omap_wdt_ioctl, .open = omap_wdt_open, .release = omap_wdt_release, }; @@ -373,6 +379,7 @@ static struct platform_driver omap_wdt_driver = { static int __init omap_wdt_init(void) { + spin_lock_init(&wdt_lock); return platform_driver_register(&omap_wdt_driver); } -- cgit v1.2.3 From aee334c23c9a559ce6334bd6ba74a5708b600ada Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:37 +0100 Subject: [WATCHDOG 31/57] pc87413_wdt: clean up, coding style, unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/pc87413_wdt.c | 211 +++++++++++++++++------------------------ 1 file changed, 87 insertions(+), 124 deletions(-) diff --git a/drivers/watchdog/pc87413_wdt.c b/drivers/watchdog/pc87413_wdt.c index 15e4f8887a9e..326f2d2ded3b 100644 --- a/drivers/watchdog/pc87413_wdt.c +++ b/drivers/watchdog/pc87413_wdt.c @@ -31,9 +31,9 @@ #include #include #include +#include +#include -#include -#include #include /* #define DEBUG 1 */ @@ -56,12 +56,12 @@ static int io = 0x2E; /* Address used on Portwell Boards */ -static int timeout = DEFAULT_TIMEOUT; /* timeout value */ -static unsigned long timer_enabled = 0; /* is the timer enabled? */ +static int timeout = DEFAULT_TIMEOUT; /* timeout value */ +static unsigned long timer_enabled; /* is the timer enabled? */ -static char expect_close; /* is the close expected? */ +static char expect_close; /* is the close expected? */ -static DEFINE_SPINLOCK(io_lock);/* to guard the watchdog from io races */ +static DEFINE_SPINLOCK(io_lock); /* to guard us from io races */ static int nowayout = WATCHDOG_NOWAYOUT; @@ -69,7 +69,7 @@ static int nowayout = WATCHDOG_NOWAYOUT; /* Select pins for Watchdog output */ -static inline void pc87413_select_wdt_out (void) +static inline void pc87413_select_wdt_out(void) { unsigned int cr_data = 0; @@ -77,7 +77,7 @@ static inline void pc87413_select_wdt_out (void) outb_p(SIOCFG2, WDT_INDEX_IO_PORT); - cr_data = inb (WDT_DATA_IO_PORT); + cr_data = inb(WDT_DATA_IO_PORT); cr_data |= 0x80; /* Set Bit7 to 1*/ outb_p(SIOCFG2, WDT_INDEX_IO_PORT); @@ -85,8 +85,9 @@ static inline void pc87413_select_wdt_out (void) outb_p(cr_data, WDT_DATA_IO_PORT); #ifdef DEBUG - printk(KERN_INFO DPFX "Select multiple pin,pin55,as WDT output:" - " Bit7 to 1: %d\n", cr_data); + printk(KERN_INFO DPFX + "Select multiple pin,pin55,as WDT output: Bit7 to 1: %d\n", + cr_data); #endif } @@ -94,7 +95,7 @@ static inline void pc87413_select_wdt_out (void) static inline void pc87413_enable_swc(void) { - unsigned int cr_data=0; + unsigned int cr_data = 0; /* Step 2: Enable SWC functions */ @@ -129,12 +130,11 @@ static inline unsigned int pc87413_get_swc_base(void) addr_l = inb(WDT_DATA_IO_PORT); swc_base_addr = (addr_h << 8) + addr_l; - #ifdef DEBUG - printk(KERN_INFO DPFX "Read SWC I/O Base Address: low %d, high %d," - " res %d\n", addr_l, addr_h, swc_base_addr); + printk(KERN_INFO DPFX + "Read SWC I/O Base Address: low %d, high %d, res %d\n", + addr_l, addr_h, swc_base_addr); #endif - return swc_base_addr; } @@ -143,9 +143,7 @@ static inline unsigned int pc87413_get_swc_base(void) static inline void pc87413_swc_bank3(unsigned int swc_base_addr) { /* Step 4: Select Bank3 of SWC */ - outb_p(inb(swc_base_addr + 0x0f) | 0x03, swc_base_addr + 0x0f); - #ifdef DEBUG printk(KERN_INFO DPFX "Select Bank3 of SWC\n"); #endif @@ -157,9 +155,7 @@ static inline void pc87413_programm_wdto(unsigned int swc_base_addr, char pc87413_time) { /* Step 5: Programm WDTO, Twd. */ - outb_p(pc87413_time, swc_base_addr + WDTO); - #ifdef DEBUG printk(KERN_INFO DPFX "Set WDTO to %d minutes\n", pc87413_time); #endif @@ -170,9 +166,7 @@ static inline void pc87413_programm_wdto(unsigned int swc_base_addr, static inline void pc87413_enable_wden(unsigned int swc_base_addr) { /* Step 6: Enable WDEN */ - - outb_p(inb (swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL); - + outb_p(inb(swc_base_addr + WDCTL) | 0x01, swc_base_addr + WDCTL); #ifdef DEBUG printk(KERN_INFO DPFX "Enable WDEN\n"); #endif @@ -182,9 +176,7 @@ static inline void pc87413_enable_wden(unsigned int swc_base_addr) static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr) { /* Enable SW_WD_TREN */ - - outb_p(inb (swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG); - + outb_p(inb(swc_base_addr + WDCFG) | 0x80, swc_base_addr + WDCFG); #ifdef DEBUG printk(KERN_INFO DPFX "Enable SW_WD_TREN\n"); #endif @@ -195,9 +187,7 @@ static inline void pc87413_enable_sw_wd_tren(unsigned int swc_base_addr) static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr) { /* Disable SW_WD_TREN */ - - outb_p(inb (swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG); - + outb_p(inb(swc_base_addr + WDCFG) & 0x7f, swc_base_addr + WDCFG); #ifdef DEBUG printk(KERN_INFO DPFX "pc87413 - Disable SW_WD_TREN\n"); #endif @@ -208,9 +198,7 @@ static inline void pc87413_disable_sw_wd_tren(unsigned int swc_base_addr) static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr) { /* Enable SW_WD_TRG */ - - outb_p(inb (swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL); - + outb_p(inb(swc_base_addr + WDCTL) | 0x80, swc_base_addr + WDCTL); #ifdef DEBUG printk(KERN_INFO DPFX "pc87413 - Enable SW_WD_TRG\n"); #endif @@ -221,9 +209,7 @@ static inline void pc87413_enable_sw_wd_trg(unsigned int swc_base_addr) static inline void pc87413_disable_sw_wd_trg(unsigned int swc_base_addr) { /* Disable SW_WD_TRG */ - - outb_p(inb (swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL); - + outb_p(inb(swc_base_addr + WDCTL) & 0x7f, swc_base_addr + WDCTL); #ifdef DEBUG printk(KERN_INFO DPFX "Disable SW_WD_TRG\n"); #endif @@ -314,8 +300,8 @@ static int pc87413_open(struct inode *inode, struct file *file) /* Reload and activate timer */ pc87413_refresh(); - printk(KERN_INFO MODNAME "Watchdog enabled. Timeout set to" - " %d minute(s).\n", timeout); + printk(KERN_INFO MODNAME + "Watchdog enabled. Timeout set to %d minute(s).\n", timeout); return nonseekable_open(inode, file); } @@ -338,17 +324,15 @@ static int pc87413_release(struct inode *inode, struct file *file) if (expect_close == 42) { pc87413_disable(); - printk(KERN_INFO MODNAME "Watchdog disabled," - " sleeping again...\n"); + printk(KERN_INFO MODNAME + "Watchdog disabled, sleeping again...\n"); } else { - printk(KERN_CRIT MODNAME "Unexpected close, not stopping" - " watchdog!\n"); + printk(KERN_CRIT MODNAME + "Unexpected close, not stopping watchdog!\n"); pc87413_refresh(); } - clear_bit(0, &timer_enabled); expect_close = 0; - return 0; } @@ -386,7 +370,8 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, /* reset expect flag */ expect_close = 0; - /* scan to see whether or not we got the magic character */ + /* scan to see whether or not we got the + magic character */ for (i = 0; i != len; i++) { char c; if (get_user(c, data+i)) @@ -404,7 +389,6 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, /** * pc87413_ioctl: - * @inode: inode of the device * @file: file handle to the device * @cmd: watchdog command * @arg: argument pointer @@ -414,8 +398,8 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, * querying capabilities and current status. */ -static int pc87413_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long pc87413_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_timeout; @@ -426,75 +410,58 @@ static int pc87413_ioctl(struct inode *inode, struct file *file, static struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | - WDIOF_SETTIMEOUT | - WDIOF_MAGICCLOSE, + WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "PC87413(HF/F) watchdog" }; uarg.i = (int __user *)arg; - switch(cmd) { - default: - return -ENOTTY; - - case WDIOC_GETSUPPORT: - return copy_to_user(uarg.ident, &ident, - sizeof(ident)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - return put_user(pc87413_status(), uarg.i); - - case WDIOC_GETBOOTSTATUS: - return put_user(0, uarg.i); - - case WDIOC_KEEPALIVE: - pc87413_refresh(); + switch (cmd) { + case WDIOC_GETSUPPORT: + return copy_to_user(uarg.ident, &ident, + sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + return put_user(pc87413_status(), uarg.i); + case WDIOC_GETBOOTSTATUS: + return put_user(0, uarg.i); + case WDIOC_KEEPALIVE: + pc87413_refresh(); #ifdef DEBUG - printk(KERN_INFO DPFX "keepalive\n"); + printk(KERN_INFO DPFX "keepalive\n"); #endif - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, uarg.i)) - return -EFAULT; - - // the API states this is given in secs - new_timeout /= 60; - - if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) - return -EINVAL; - - timeout = new_timeout; - pc87413_refresh(); - - // fall through and return the new timeout... - - case WDIOC_GETTIMEOUT: - - new_timeout = timeout * 60; - - return put_user(new_timeout, uarg.i); - - case WDIOC_SETOPTIONS: - { - int options, retval = -EINVAL; - - if (get_user(options, uarg.i)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - pc87413_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - pc87413_enable(); - retval = 0; - } - - return retval; + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, uarg.i)) + return -EFAULT; + /* the API states this is given in secs */ + new_timeout /= 60; + if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) + return -EINVAL; + timeout = new_timeout; + pc87413_refresh(); + /* fall through and return the new timeout... */ + case WDIOC_GETTIMEOUT: + new_timeout = timeout * 60; + return put_user(new_timeout, uarg.i); + case WDIOC_SETOPTIONS: + { + int options, retval = -EINVAL; + if (get_user(options, uarg.i)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + pc87413_disable(); + retval = 0; } + if (options & WDIOS_ENABLECARD) { + pc87413_enable(); + retval = 0; + } + return retval; + } + default: + return -ENOTTY; } } @@ -517,10 +484,8 @@ static int pc87413_notify_sys(struct notifier_block *this, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) - { /* Turn the card off */ pc87413_disable(); - } return NOTIFY_DONE; } @@ -530,18 +495,16 @@ static const struct file_operations pc87413_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = pc87413_write, - .ioctl = pc87413_ioctl, + .unlocked_ioctl = pc87413_ioctl, .open = pc87413_open, .release = pc87413_release, }; -static struct notifier_block pc87413_notifier = -{ +static struct notifier_block pc87413_notifier = { .notifier_call = pc87413_notify_sys, }; -static struct miscdevice pc87413_miscdev= -{ +static struct miscdevice pc87413_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &pc87413_fops @@ -561,29 +524,26 @@ static int __init pc87413_init(void) { int ret; - printk(KERN_INFO PFX "Version " VERSION " at io 0x%X\n", WDT_INDEX_IO_PORT); + printk(KERN_INFO PFX "Version " VERSION " at io 0x%X\n", + WDT_INDEX_IO_PORT); /* request_region(io, 2, "pc87413"); */ ret = register_reboot_notifier(&pc87413_notifier); if (ret != 0) { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - ret); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); } ret = misc_register(&pc87413_miscdev); - if (ret != 0) { printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", WATCHDOG_MINOR, ret); unregister_reboot_notifier(&pc87413_notifier); return ret; } - printk(KERN_INFO PFX "initialized. timeout=%d min \n", timeout); - pc87413_enable(); - return 0; } @@ -600,8 +560,7 @@ static int __init pc87413_init(void) static void __exit pc87413_exit(void) { /* Stop the timer before we leave */ - if (!nowayout) - { + if (!nowayout) { pc87413_disable(); printk(KERN_INFO MODNAME "Watchdog disabled.\n"); } @@ -626,8 +585,12 @@ module_param(io, int, 0); MODULE_PARM_DESC(io, MODNAME " I/O port (default: " __MODULE_STRING(io) ")."); module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in minutes (default=" __MODULE_STRING(timeout) ")."); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in minutes (default=" + __MODULE_STRING(timeout) ")."); module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -- cgit v1.2.3 From 261dcc70aae926ba7b9218da7302f0ad2f665b79 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:43 +0100 Subject: [WATCHDOG 32/57] pcwd: clean up, unlocked_ioctl usage Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/pcwd.c | 179 +++++++++++++++++++++++++++--------------------- 1 file changed, 100 insertions(+), 79 deletions(-) diff --git a/drivers/watchdog/pcwd.c b/drivers/watchdog/pcwd.c index 7b41434fac8c..e1259adf09f9 100644 --- a/drivers/watchdog/pcwd.c +++ b/drivers/watchdog/pcwd.c @@ -40,13 +40,15 @@ * fairly useless proc entry. * 990610 removed said useless proc code for the merge * 000403 Removed last traces of proc code. - * 011214 Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT + * 011214 Added nowayout module option to override + * CONFIG_WATCHDOG_NOWAYOUT * Added timeout module option to override default */ /* * A bells and whistles driver is available from http://www.pcwd.de/ - * More info available at http://www.berkprod.com/ or http://www.pcwatchdog.com/ + * More info available at http://www.berkprod.com/ or + * http://www.pcwatchdog.com/ */ #include /* For module specific items */ @@ -65,9 +67,8 @@ #include /* For isa devices */ #include /* For io-port access */ #include /* For spin_lock/spin_unlock/... */ - -#include /* For copy_to_user/put_user/... */ -#include /* For inb/outb/... */ +#include /* For copy_to_user/put_user/... */ +#include /* For inb/outb/... */ /* Module and version information */ #define WATCHDOG_VERSION "1.20" @@ -111,14 +112,16 @@ static int pcwd_ioports[] = { 0x270, 0x350, 0x370, 0x000 }; #define WD_REVC_WTRP 0x01 /* Watchdog Trip status */ #define WD_REVC_HRBT 0x02 /* Watchdog Heartbeat */ #define WD_REVC_TTRP 0x04 /* Temperature Trip status */ -#define WD_REVC_RL2A 0x08 /* Relay 2 activated by on-board processor */ +#define WD_REVC_RL2A 0x08 /* Relay 2 activated by + on-board processor */ #define WD_REVC_RL1A 0x10 /* Relay 1 active */ #define WD_REVC_R2DS 0x40 /* Relay 2 disable */ #define WD_REVC_RLY2 0x80 /* Relay 2 activated? */ /* Port 2 : Control Status #2 */ #define WD_WDIS 0x10 /* Watchdog Disabled */ #define WD_ENTP 0x20 /* Watchdog Enable Temperature Trip */ -#define WD_SSEL 0x40 /* Watchdog Switch Select (1:SW1 <-> 0:SW2) */ +#define WD_SSEL 0x40 /* Watchdog Switch Select + (1:SW1 <-> 0:SW2) */ #define WD_WCMD 0x80 /* Watchdog Command Mode */ /* max. time we give an ISA watchdog card to process a command */ @@ -168,11 +171,15 @@ static int cards_found; static atomic_t open_allowed = ATOMIC_INIT(1); static char expect_close; static int temp_panic; -static struct { /* this is private data for each ISA-PC watchdog card */ + +/* this is private data for each ISA-PC watchdog card */ +static struct { char fw_ver_str[6]; /* The cards firmware version */ int revision; /* The card's revision */ - int supports_temp; /* Wether or not the card has a temperature device */ - int command_mode; /* Wether or not the card is in command mode */ + int supports_temp; /* Whether or not the card has + a temperature device */ + int command_mode; /* Whether or not the card is in + command mode */ int boot_status; /* The card's boot status */ int io_addr; /* The cards I/O address */ spinlock_t io_lock; /* the lock for io operations */ @@ -186,16 +193,20 @@ static struct { /* this is private data for each ISA-PC watchdog card */ #define DEBUG 2 /* print fancy stuff too */ static int debug = QUIET; module_param(debug, int, 0); -MODULE_PARM_DESC(debug, "Debug level: 0=Quiet, 1=Verbose, 2=Debug (default=0)"); +MODULE_PARM_DESC(debug, + "Debug level: 0=Quiet, 1=Verbose, 2=Debug (default=0)"); -#define WATCHDOG_HEARTBEAT 0 /* default heartbeat = delay-time from dip-switches */ +/* default heartbeat = delay-time from dip-switches */ +#define WATCHDOG_HEARTBEAT 0 static int heartbeat = WATCHDOG_HEARTBEAT; module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<=heartbeat<=7200 or 0=delay-time from dip-switches, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2 <= heartbeat <= 7200 or 0=delay-time from dip-switches, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Internal functions @@ -224,7 +235,7 @@ static int send_isa_command(int cmd) if (port0 == last_port0) break; /* Data is stable */ - udelay (250); + udelay(250); } if (debug >= DEBUG) @@ -236,7 +247,7 @@ static int send_isa_command(int cmd) static int set_command_mode(void) { - int i, found=0, count=0; + int i, found = 0, count = 0; /* Set the card into command mode */ spin_lock(&pcwd_private.io_lock); @@ -296,7 +307,8 @@ static inline void pcwd_get_firmware(void) ten = send_isa_command(CMD_ISA_VERSION_TENTH); hund = send_isa_command(CMD_ISA_VERSION_HUNDRETH); minor = send_isa_command(CMD_ISA_VERSION_MINOR); - sprintf(pcwd_private.fw_ver_str, "%c.%c%c%c", one, ten, hund, minor); + sprintf(pcwd_private.fw_ver_str, "%c.%c%c%c", + one, ten, hund, minor); } unset_command_mode(); @@ -305,7 +317,7 @@ static inline void pcwd_get_firmware(void) static inline int pcwd_get_option_switches(void) { - int option_switches=0; + int option_switches = 0; if (set_command_mode()) { /* Get switch settings */ @@ -322,7 +334,9 @@ static void pcwd_show_card_info(void) /* Get some extra info from the hardware (in command/debug/diag mode) */ if (pcwd_private.revision == PCWD_REVISION_A) - printk(KERN_INFO PFX "ISA-PC Watchdog (REV.A) detected at port 0x%04x\n", pcwd_private.io_addr); + printk(KERN_INFO PFX + "ISA-PC Watchdog (REV.A) detected at port 0x%04x\n", + pcwd_private.io_addr); else if (pcwd_private.revision == PCWD_REVISION_C) { pcwd_get_firmware(); printk(KERN_INFO PFX "ISA-PC Watchdog (REV.C) detected at port 0x%04x (Firmware version: %s)\n", @@ -347,12 +361,15 @@ static void pcwd_show_card_info(void) printk(KERN_INFO PFX "Previous reboot was caused by the card\n"); if (pcwd_private.boot_status & WDIOF_OVERHEAT) { - printk(KERN_EMERG PFX "Card senses a CPU Overheat. Panicking!\n"); - printk(KERN_EMERG PFX "CPU Overheat\n"); + printk(KERN_EMERG PFX + "Card senses a CPU Overheat. Panicking!\n"); + printk(KERN_EMERG PFX + "CPU Overheat\n"); } if (pcwd_private.boot_status == 0) - printk(KERN_INFO PFX "No previous trip detected - Cold boot or reset\n"); + printk(KERN_INFO PFX + "No previous trip detected - Cold boot or reset\n"); } static void pcwd_timer_ping(unsigned long data) @@ -361,11 +378,12 @@ static void pcwd_timer_ping(unsigned long data) /* If we got a heartbeat pulse within the WDT_INTERVAL * we agree to ping the WDT */ - if(time_before(jiffies, pcwd_private.next_heartbeat)) { + if (time_before(jiffies, pcwd_private.next_heartbeat)) { /* Ping the watchdog */ spin_lock(&pcwd_private.io_lock); if (pcwd_private.revision == PCWD_REVISION_A) { - /* Rev A cards are reset by setting the WD_WDRST bit in register 1 */ + /* Rev A cards are reset by setting the + WD_WDRST bit in register 1 */ wdrst_stat = inb_p(pcwd_private.io_addr); wdrst_stat &= 0x0F; wdrst_stat |= WD_WDRST; @@ -381,7 +399,8 @@ static void pcwd_timer_ping(unsigned long data) spin_unlock(&pcwd_private.io_lock); } else { - printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); + printk(KERN_WARNING PFX + "Heartbeat lost! Will not ping the watchdog\n"); } } @@ -454,7 +473,7 @@ static int pcwd_keepalive(void) static int pcwd_set_heartbeat(int t) { - if ((t < 2) || (t > 7200)) /* arbitrary upper limit */ + if (t < 2 || t > 7200) /* arbitrary upper limit */ return -EINVAL; heartbeat = t; @@ -470,7 +489,7 @@ static int pcwd_get_status(int *status) { int control_status; - *status=0; + *status = 0; spin_lock(&pcwd_private.io_lock); if (pcwd_private.revision == PCWD_REVISION_A) /* Rev A cards return status information from @@ -494,9 +513,9 @@ static int pcwd_get_status(int *status) if (control_status & WD_T110) { *status |= WDIOF_OVERHEAT; if (temp_panic) { - printk(KERN_INFO PFX "Temperature overheat trip!\n"); + printk(KERN_INFO PFX + "Temperature overheat trip!\n"); kernel_power_off(); - /* or should we just do a: panic(PFX "Temperature overheat trip!\n"); */ } } } else { @@ -506,9 +525,9 @@ static int pcwd_get_status(int *status) if (control_status & WD_REVC_TTRP) { *status |= WDIOF_OVERHEAT; if (temp_panic) { - printk(KERN_INFO PFX "Temperature overheat trip!\n"); + printk(KERN_INFO PFX + "Temperature overheat trip!\n"); kernel_power_off(); - /* or should we just do a: panic(PFX "Temperature overheat trip!\n"); */ } } } @@ -524,18 +543,21 @@ static int pcwd_clear_status(void) spin_lock(&pcwd_private.io_lock); if (debug >= VERBOSE) - printk(KERN_INFO PFX "clearing watchdog trip status\n"); + printk(KERN_INFO PFX + "clearing watchdog trip status\n"); control_status = inb_p(pcwd_private.io_addr + 1); if (debug >= DEBUG) { - printk(KERN_DEBUG PFX "status was: 0x%02x\n", control_status); + printk(KERN_DEBUG PFX "status was: 0x%02x\n", + control_status); printk(KERN_DEBUG PFX "sending: 0x%02x\n", (control_status & WD_REVC_R2DS)); } /* clear reset status & Keep Relay 2 disable state as it is */ - outb_p((control_status & WD_REVC_R2DS), pcwd_private.io_addr + 1); + outb_p((control_status & WD_REVC_R2DS), + pcwd_private.io_addr + 1); spin_unlock(&pcwd_private.io_lock); } @@ -572,8 +594,7 @@ static int pcwd_get_temperature(int *temperature) * /dev/watchdog handling */ -static int pcwd_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long pcwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int rv; int status; @@ -590,12 +611,12 @@ static int pcwd_ioctl(struct inode *inode, struct file *file, .identity = "PCWD", }; - switch(cmd) { + switch (cmd) { default: return -ENOTTY; case WDIOC_GETSUPPORT: - if(copy_to_user(argp, &ident, sizeof(ident))) + if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; return 0; @@ -613,25 +634,22 @@ static int pcwd_ioctl(struct inode *inode, struct file *file, return put_user(temperature, argp); case WDIOC_SETOPTIONS: - if (pcwd_private.revision == PCWD_REVISION_C) - { - if(copy_from_user(&rv, argp, sizeof(int))) + if (pcwd_private.revision == PCWD_REVISION_C) { + if (get_user(rv, argp)) return -EFAULT; - if (rv & WDIOS_DISABLECARD) - { - return pcwd_stop(); + if (rv & WDIOS_DISABLECARD) { + status = pcwd_stop(); + if (status < 0) + return status; } - - if (rv & WDIOS_ENABLECARD) - { - return pcwd_start(); + if (rv & WDIOS_ENABLECARD) { + status = pcwd_start(); + if (status < 0) + return status; } - if (rv & WDIOS_TEMPPANIC) - { temp_panic = 1; - } } return -EINVAL; @@ -682,16 +700,10 @@ static ssize_t pcwd_write(struct file *file, const char __user *buf, size_t len, static int pcwd_open(struct inode *inode, struct file *file) { - if (!atomic_dec_and_test(&open_allowed) ) { - if (debug >= VERBOSE) - printk(KERN_ERR PFX "Attempt to open already opened device.\n"); - atomic_inc( &open_allowed ); + if (test_and_set_bit(0, &open_allowed)) return -EBUSY; - } - if (nowayout) __module_get(THIS_MODULE); - /* Activate */ pcwd_start(); pcwd_keepalive(); @@ -700,14 +712,15 @@ static int pcwd_open(struct inode *inode, struct file *file) static int pcwd_close(struct inode *inode, struct file *file) { - if (expect_close == 42) { + if (expect_close == 42) pcwd_stop(); - } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); pcwd_keepalive(); } expect_close = 0; - atomic_inc( &open_allowed ); + clear_bit(0, &open_allowed); return 0; } @@ -750,7 +763,7 @@ static const struct file_operations pcwd_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = pcwd_write, - .ioctl = pcwd_ioctl, + .unlocked_ioctl = pcwd_ioctl, .open = pcwd_open, .release = pcwd_close, }; @@ -788,7 +801,7 @@ static inline int get_revision(void) * presumes a floating bus reads as 0xff. */ if ((inb(pcwd_private.io_addr + 2) == 0xFF) || (inb(pcwd_private.io_addr + 3) == 0xFF)) - r=PCWD_REVISION_A; + r = PCWD_REVISION_A; spin_unlock(&pcwd_private.io_lock); return r; @@ -803,7 +816,7 @@ static inline int get_revision(void) */ static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) { - int base_addr=pcwd_ioports[id]; + int base_addr = pcwd_ioports[id]; int port0, last_port0; /* Reg 0, in case it's REV A */ int port1, last_port1; /* Register 1 for REV C cards */ int i; @@ -813,7 +826,7 @@ static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) printk(KERN_DEBUG PFX "pcwd_isa_match id=%d\n", id); - if (!request_region (base_addr, 4, "PCWD")) { + if (!request_region(base_addr, 4, "PCWD")) { printk(KERN_INFO PFX "Port 0x%04x unavailable\n", base_addr); return 0; } @@ -842,7 +855,7 @@ static int __devinit pcwd_isa_match(struct device *dev, unsigned int id) } } } - release_region (base_addr, 4); + release_region(base_addr, 4); return retval; } @@ -857,7 +870,8 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) cards_found++; if (cards_found == 1) - printk(KERN_INFO PFX "v%s Ken Hollis (kenji@bitgate.com)\n", WD_VER); + printk(KERN_INFO PFX "v%s Ken Hollis (kenji@bitgate.com)\n", + WD_VER); if (cards_found > 1) { printk(KERN_ERR PFX "This driver only supports 1 device\n"); @@ -875,10 +889,11 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) /* Check card's revision */ pcwd_private.revision = get_revision(); - if (!request_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4, "PCWD")) { + if (!request_region(pcwd_private.io_addr, + (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4, "PCWD")) { printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", pcwd_private.io_addr); - ret=-EIO; + ret = -EIO; goto error_request_region; } @@ -908,26 +923,30 @@ static int __devinit pcwd_isa_probe(struct device *dev, unsigned int id) if (heartbeat == 0) heartbeat = heartbeat_tbl[(pcwd_get_option_switches() & 0x07)]; - /* Check that the heartbeat value is within it's range ; if not reset to the default */ + /* Check that the heartbeat value is within it's range; + if not reset to the default */ if (pcwd_set_heartbeat(heartbeat)) { pcwd_set_heartbeat(WATCHDOG_HEARTBEAT); - printk(KERN_INFO PFX "heartbeat value must be 2<=heartbeat<=7200, using %d\n", - WATCHDOG_HEARTBEAT); + printk(KERN_INFO PFX + "heartbeat value must be 2 <= heartbeat <= 7200, using %d\n", + WATCHDOG_HEARTBEAT); } if (pcwd_private.supports_temp) { ret = misc_register(&temp_miscdev); if (ret) { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - TEMP_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + TEMP_MINOR, ret); goto error_misc_register_temp; } } ret = misc_register(&pcwd_miscdev); if (ret) { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto error_misc_register_watchdog; } @@ -940,7 +959,8 @@ error_misc_register_watchdog: if (pcwd_private.supports_temp) misc_deregister(&temp_miscdev); error_misc_register_temp: - release_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); + release_region(pcwd_private.io_addr, + (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); error_request_region: pcwd_private.io_addr = 0x0000; cards_found--; @@ -964,7 +984,8 @@ static int __devexit pcwd_isa_remove(struct device *dev, unsigned int id) misc_deregister(&pcwd_miscdev); if (pcwd_private.supports_temp) misc_deregister(&temp_miscdev); - release_region(pcwd_private.io_addr, (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); + release_region(pcwd_private.io_addr, + (pcwd_private.revision == PCWD_REVISION_A) ? 2 : 4); pcwd_private.io_addr = 0x0000; cards_found--; -- cgit v1.2.3 From 84ca995c258df70a8914866e8c996845003ff938 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:48 +0100 Subject: [WATCHDOG 33/57] pnx4008_wdt: unlocked_ioctl setup Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/pnx4008_wdt.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 6b8483d3c783..8cd0d53941e7 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c @@ -30,8 +30,8 @@ #include #include -#include -#include +#include +#include #define MODULE_NAME "PNX4008-WDT: " @@ -144,9 +144,8 @@ static int pnx4008_wdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static ssize_t -pnx4008_wdt_write(struct file *file, const char *data, size_t len, - loff_t * ppos) +static ssize_t pnx4008_wdt_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { if (len) { if (!nowayout) { @@ -169,15 +168,14 @@ pnx4008_wdt_write(struct file *file, const char *data, size_t len, return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, .identity = "PNX4008 Watchdog", }; -static int -pnx4008_wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long pnx4008_wdt_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) { int ret = -ENOTTY; int time; @@ -238,7 +236,7 @@ static const struct file_operations pnx4008_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = pnx4008_wdt_write, - .ioctl = pnx4008_wdt_ioctl, + .unlocked_ioctl = pnx4008_wdt_ioctl, .open = pnx4008_wdt_open, .release = pnx4008_wdt_release, }; -- cgit v1.2.3 From 72d5c0505bafae1a393f50e169e20b682d37f28e Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:07:54 +0100 Subject: [WATCHDOG 34/57] rm9k_wdt: clean up Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/rm9k_wdt.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/drivers/watchdog/rm9k_wdt.c b/drivers/watchdog/rm9k_wdt.c index 5c921e471564..c172906b553c 100644 --- a/drivers/watchdog/rm9k_wdt.c +++ b/drivers/watchdog/rm9k_wdt.c @@ -29,10 +29,10 @@ #include #include #include -#include +#include +#include #include #include -#include #include #include @@ -53,10 +53,12 @@ static void wdt_gpi_stop(void); static void wdt_gpi_set_timeout(unsigned int); static int wdt_gpi_open(struct inode *, struct file *); static int wdt_gpi_release(struct inode *, struct file *); -static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t, loff_t *); +static ssize_t wdt_gpi_write(struct file *, const char __user *, size_t, + loff_t *); static long wdt_gpi_ioctl(struct file *, unsigned int, unsigned long); static int wdt_gpi_notify(struct notifier_block *, unsigned long, void *); -static const struct resource *wdt_gpi_get_resource(struct platform_device *, const char *, unsigned int); +static const struct resource *wdt_gpi_get_resource(struct platform_device *, + const char *, unsigned int); static int __init wdt_gpi_probe(struct device *); static int __exit wdt_gpi_remove(struct device *); @@ -68,7 +70,7 @@ static int locked; /* These are set from device resources */ -static void __iomem * wd_regs; +static void __iomem *wd_regs; static unsigned int wd_irq, wd_ctr; @@ -216,7 +218,8 @@ static int wdt_gpi_release(struct inode *inode, struct file *file) if (expect_close) { wdt_gpi_stop(); free_irq(wd_irq, &miscdev); - printk(KERN_INFO "%s: watchdog stopped\n", wdt_gpi_name); + printk(KERN_INFO "%s: watchdog stopped\n", + wdt_gpi_name); } else { printk(KERN_CRIT "%s: unexpected close() -" " watchdog left running\n", @@ -241,8 +244,7 @@ wdt_gpi_write(struct file *f, const char __user *d, size_t s, loff_t *o) return s ? 1 : 0; } -static long -wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) +static long wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) { long res = -ENOTTY; const long size = _IOC_SIZE(cmd); @@ -271,7 +273,8 @@ wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) case WDIOC_GETSUPPORT: wdinfo.options = nowayout ? WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING : - WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE; + WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | + WDIOF_MAGICCLOSE; res = __copy_to_user(argp, &wdinfo, size) ? -EFAULT : size; break; -- cgit v1.2.3 From edef7a93f9414e1d4864150eabb49a618222c2bd Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:00 +0100 Subject: [WATCHDOG 35/57] s3c2410: watchdog cleanup and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/s3c2410_wdt.c | 148 ++++++++++++++++++++++------------------- 1 file changed, 80 insertions(+), 68 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 98532c0e0689..97b4a2e8eb09 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -46,9 +46,8 @@ #include #include #include - -#include -#include +#include +#include #include @@ -65,8 +64,8 @@ static int nowayout = WATCHDOG_NOWAYOUT; static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME; static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; -static int soft_noboot = 0; -static int debug = 0; +static int soft_noboot; +static int debug; module_param(tmr_margin, int, 0); module_param(tmr_atboot, int, 0); @@ -74,24 +73,23 @@ module_param(nowayout, int, 0); module_param(soft_noboot, int, 0); module_param(debug, int, 0); -MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default=" __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); - -MODULE_PARM_DESC(tmr_atboot, "Watchdog is started at boot time if set to 1, default=" __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); - -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); - +MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default=" + __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); +MODULE_PARM_DESC(tmr_atboot, + "Watchdog is started at boot time if set to 1, default=" + __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)"); - MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)"); typedef enum close_state { CLOSE_STATE_NOT, - CLOSE_STATE_ALLOW=0x4021 + CLOSE_STATE_ALLOW = 0x4021 } close_state_t; -static DECLARE_MUTEX(open_lock); - +static unsigned long open_lock; static struct device *wdt_dev; /* platform device attached to */ static struct resource *wdt_mem; static struct resource *wdt_irq; @@ -99,38 +97,58 @@ static struct clk *wdt_clock; static void __iomem *wdt_base; static unsigned int wdt_count; static close_state_t allow_close; +static DEFINE_SPINLOCK(wdt_lock); /* watchdog control routines */ #define DBG(msg...) do { \ if (debug) \ printk(KERN_INFO msg); \ - } while(0) + } while (0) /* functions */ -static int s3c2410wdt_keepalive(void) +static void s3c2410wdt_keepalive(void) { + spin_lock(&wdt_lock); writel(wdt_count, wdt_base + S3C2410_WTCNT); - return 0; + spin_unlock(&wdt_lock); } -static int s3c2410wdt_stop(void) +static void __s3c2410wdt_stop(void) { unsigned long wtcon; + spin_lock(&wdt_lock); wtcon = readl(wdt_base + S3C2410_WTCON); wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); writel(wtcon, wdt_base + S3C2410_WTCON); + spin_unlock(&wdt_lock); +} - return 0; +static void __s3c2410wdt_stop(void) +{ + unsigned long wtcon; + + wtcon = readl(wdt_base + S3C2410_WTCON); + wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); + writel(wtcon, wdt_base + S3C2410_WTCON); +} + +static void s3c2410wdt_stop(void) +{ + spin_lock(&wdt_lock); + __s3c2410wdt_stop(); + spin_unlock(&wdt_lock); } -static int s3c2410wdt_start(void) +static void s3c2410wdt_start(void) { unsigned long wtcon; - s3c2410wdt_stop(); + spin_lock(&wdt_lock); + + __s3c2410wdt_stop(); wtcon = readl(wdt_base + S3C2410_WTCON); wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; @@ -149,6 +167,7 @@ static int s3c2410wdt_start(void) writel(wdt_count, wdt_base + S3C2410_WTDAT); writel(wdt_count, wdt_base + S3C2410_WTCNT); writel(wtcon, wdt_base + S3C2410_WTCON); + spin_unlock(&wdt_lock); return 0; } @@ -211,7 +230,7 @@ static int s3c2410wdt_set_heartbeat(int timeout) static int s3c2410wdt_open(struct inode *inode, struct file *file) { - if(down_trylock(&open_lock)) + if (test_and_set_bit(0, &open_lock)) return -EBUSY; if (nowayout) @@ -231,15 +250,14 @@ static int s3c2410wdt_release(struct inode *inode, struct file *file) * Lock it in if it's a module and we set nowayout */ - if (allow_close == CLOSE_STATE_ALLOW) { + if (allow_close == CLOSE_STATE_ALLOW) s3c2410wdt_stop(); - } else { + else { dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n"); s3c2410wdt_keepalive(); } - allow_close = CLOSE_STATE_NOT; - up(&open_lock); + clear_bit(0, &open_lock); return 0; } @@ -249,7 +267,7 @@ static ssize_t s3c2410wdt_write(struct file *file, const char __user *data, /* * Refresh the timer. */ - if(len) { + if (len) { if (!nowayout) { size_t i; @@ -265,7 +283,6 @@ static ssize_t s3c2410wdt_write(struct file *file, const char __user *data, allow_close = CLOSE_STATE_ALLOW; } } - s3c2410wdt_keepalive(); } return len; @@ -273,48 +290,41 @@ static ssize_t s3c2410wdt_write(struct file *file, const char __user *data, #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE -static struct watchdog_info s3c2410_wdt_ident = { +static const struct watchdog_info s3c2410_wdt_ident = { .options = OPTIONS, .firmware_version = 0, .identity = "S3C2410 Watchdog", }; -static int s3c2410wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_margin; switch (cmd) { - default: - return -ENOTTY; - - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &s3c2410_wdt_ident, - sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - - case WDIOC_KEEPALIVE: - s3c2410wdt_keepalive(); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_margin, p)) - return -EFAULT; - - if (s3c2410wdt_set_heartbeat(new_margin)) - return -EINVAL; - - s3c2410wdt_keepalive(); - return put_user(tmr_margin, p); - - case WDIOC_GETTIMEOUT: - return put_user(tmr_margin, p); + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &s3c2410_wdt_ident, + sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + s3c2410wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_margin, p)) + return -EFAULT; + if (s3c2410wdt_set_heartbeat(new_margin)) + return -EINVAL; + s3c2410wdt_keepalive(); + return put_user(tmr_margin, p); + case WDIOC_GETTIMEOUT: + return put_user(tmr_margin, p); } } @@ -324,7 +334,7 @@ static const struct file_operations s3c2410wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = s3c2410wdt_write, - .ioctl = s3c2410wdt_ioctl, + .unlocked_ioctl = s3c2410wdt_ioctl, .open = s3c2410wdt_open, .release = s3c2410wdt_release, }; @@ -411,14 +421,15 @@ static int s3c2410wdt_probe(struct platform_device *pdev) * not, try the default value */ if (s3c2410wdt_set_heartbeat(tmr_margin)) { - started = s3c2410wdt_set_heartbeat(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); + started = s3c2410wdt_set_heartbeat( + CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); - if (started == 0) { - dev_info(dev,"tmr_margin value out of range, default %d used\n", + if (started == 0) + dev_info(dev, + "tmr_margin value out of range, default %d used\n", CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); - } else { + else dev_info(dev, "default timer value is out of range, cannot start\n"); - } } ret = misc_register(&s3c2410wdt_miscdev); @@ -447,7 +458,7 @@ static int s3c2410wdt_probe(struct platform_device *pdev) (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis", (wtcon & S3C2410_WTCON_INTEN) ? "" : "en"); - + return 0; err_clk: @@ -487,7 +498,7 @@ static int s3c2410wdt_remove(struct platform_device *dev) static void s3c2410wdt_shutdown(struct platform_device *dev) { - s3c2410wdt_stop(); + s3c2410wdt_stop(); } #ifdef CONFIG_PM @@ -540,7 +551,8 @@ static struct platform_driver s3c2410wdt_driver = { }; -static char banner[] __initdata = KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n"; +static char banner[] __initdata = + KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n"; static int __init watchdog_init(void) { -- cgit v1.2.3 From f19e031265dc6e05511308a6ecb9637e335b45b0 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:05 +0100 Subject: [WATCHDOG 36/57] sa1100_wdt: Switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sa1100_wdt.c | 32 +++++++++++++++----------------- 1 file changed, 15 insertions(+), 17 deletions(-) diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index 34a2b3b81800..869d538c02f9 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c @@ -26,13 +26,13 @@ #include #include #include +#include #ifdef CONFIG_ARCH_PXA #include #endif #include -#include #define OSCR_FREQ CLOCK_TICK_RATE @@ -45,7 +45,7 @@ static int boot_status; */ static int sa1100dog_open(struct inode *inode, struct file *file) { - if (test_and_set_bit(1,&sa1100wdt_users)) + if (test_and_set_bit(1, &sa1100wdt_users)) return -EBUSY; /* Activate SA1100 Watchdog timer */ @@ -66,28 +66,27 @@ static int sa1100dog_open(struct inode *inode, struct file *file) static int sa1100dog_release(struct inode *inode, struct file *file) { printk(KERN_CRIT "WATCHDOG: Device closed - timer will not stop\n"); - clear_bit(1, &sa1100wdt_users); - return 0; } -static ssize_t sa1100dog_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) +static ssize_t sa1100dog_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) { if (len) /* Refresh OSMR3 timer. */ OSMR3 = OSCR + pre_margin; - return len; } -static struct watchdog_info ident = { - .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, +static const struct watchdog_info ident = { + .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT + | WDIOF_KEEPALIVEPING, .identity = "SA1100/PXA255 Watchdog", }; -static int sa1100dog_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long sa1100dog_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int ret = -ENOTTY; int time; @@ -134,18 +133,16 @@ static int sa1100dog_ioctl(struct inode *inode, struct file *file, return ret; } -static const struct file_operations sa1100dog_fops = -{ +static const struct file_operations sa1100dog_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = sa1100dog_write, - .ioctl = sa1100dog_ioctl, + .unlocked_ioctl = sa1100dog_ioctl, .open = sa1100dog_open, .release = sa1100dog_release, }; -static struct miscdevice sa1100dog_miscdev = -{ +static struct miscdevice sa1100dog_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &sa1100dog_fops, @@ -167,8 +164,9 @@ static int __init sa1100dog_init(void) ret = misc_register(&sa1100dog_miscdev); if (ret == 0) - printk("SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n", - margin); + printk(KERN_INFO + "SA1100/PXA2xx Watchdog Timer: timer margin %d sec\n", + margin); return ret; } -- cgit v1.2.3 From 1780de41406d783aa57459ba636a09aeda21d180 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:11 +0100 Subject: [WATCHDOG 37/57] sbc60xxwdt: clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sbc60xxwdt.c | 223 +++++++++++++++++++++--------------------- 1 file changed, 110 insertions(+), 113 deletions(-) diff --git a/drivers/watchdog/sbc60xxwdt.c b/drivers/watchdog/sbc60xxwdt.c index ef76f01625e7..e284a5d4fb1b 100644 --- a/drivers/watchdog/sbc60xxwdt.c +++ b/drivers/watchdog/sbc60xxwdt.c @@ -16,19 +16,23 @@ * * 12/4 - 2000 [Initial revision] * 25/4 - 2000 Added /dev/watchdog support - * 09/5 - 2001 [smj@oro.net] fixed fop_write to "return 1" on success + * 09/5 - 2001 [smj@oro.net] fixed fop_write to "return 1" + * on success * 12/4 - 2002 [rob@osinvestor.com] eliminate fop_read * fix possible wdt_is_open race * add CONFIG_WATCHDOG_NOWAYOUT support * remove lock_kernel/unlock_kernel pairs * added KERN_* to printk's * got rid of extraneous comments - * changed watchdog_info to correctly reflect what the driver offers - * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, WDIOC_SETTIMEOUT, - * WDIOC_GETTIMEOUT, and WDIOC_SETOPTIONS ioctls + * changed watchdog_info to correctly reflect what + * the driver offers + * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, + * WDIOC_SETTIMEOUT, WDIOC_GETTIMEOUT, and + * WDIOC_SETOPTIONS ioctls * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces * use module_param - * made timeout (the emulated heartbeat) a module_param + * made timeout (the emulated heartbeat) a + * module_param * made the keepalive ping an internal subroutine * made wdt_stop and wdt_start module params * added extra printk's for startup problems @@ -56,9 +60,9 @@ #include #include #include +#include +#include -#include -#include #include #define OUR_NAME "sbc60xxwdt" @@ -94,13 +98,18 @@ MODULE_PARM_DESC(wdt_start, "SBC60xx WDT 'start' io port (default 0x443)"); */ #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ -static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +static int timeout = WATCHDOG_TIMEOUT; /* in seconds, multiplied by HZ to + get seconds to wait for a ping */ module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1<=timeout<=3600, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static void wdt_timer_ping(unsigned long); static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); @@ -117,15 +126,14 @@ static void wdt_timer_ping(unsigned long data) /* If we got a heartbeat pulse within the WDT_US_INTERVAL * we agree to ping the WDT */ - if(time_before(jiffies, next_heartbeat)) - { + if (time_before(jiffies, next_heartbeat)) { /* Ping the WDT by reading from wdt_start */ inb_p(wdt_start); /* Re-set the timer interval */ mod_timer(&timer, jiffies + WDT_INTERVAL); - } else { - printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); - } + } else + printk(KERN_WARNING PFX + "Heartbeat lost! Will not ping the watchdog\n"); } /* @@ -159,40 +167,40 @@ static void wdt_keepalive(void) * /dev/watchdog handling */ -static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) +static ssize_t fop_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) - { - if (!nowayout) - { + if (count) { + if (!nowayout) { size_t ofs; - /* note: just in case someone wrote the magic character - * five months ago... */ + /* note: just in case someone wrote the + magic character five months ago... */ wdt_expect_close = 0; - /* scan to see whether or not we got the magic character */ - for(ofs = 0; ofs != count; ofs++) - { + /* scan to see whether or not we got the + magic character */ + for (ofs = 0; ofs != count; ofs++) { char c; - if(get_user(c, buf+ofs)) + if (get_user(c, buf+ofs)) return -EFAULT; - if(c == 'V') + if (c == 'V') wdt_expect_close = 42; } } - /* Well, anyhow someone wrote to us, we should return that favour */ + /* Well, anyhow someone wrote to us, we should + return that favour */ wdt_keepalive(); } return count; } -static int fop_open(struct inode * inode, struct file * file) +static int fop_open(struct inode *inode, struct file *file) { /* Just in case we're already talking to someone... */ - if(test_and_set_bit(0, &wdt_is_open)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; if (nowayout) @@ -203,78 +211,72 @@ static int fop_open(struct inode * inode, struct file * file) return nonseekable_open(inode, file); } -static int fop_close(struct inode * inode, struct file * file) +static int fop_close(struct inode *inode, struct file *file) { - if(wdt_expect_close == 42) + if (wdt_expect_close == 42) wdt_turnoff(); else { del_timer(&timer); - printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); + printk(KERN_CRIT PFX + "device file closed unexpectedly. Will not stop the WDT!\n"); } clear_bit(0, &wdt_is_open); wdt_expect_close = 0; return 0; } -static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident= - { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "SBC60xx", }; - switch(cmd) + switch (cmd) { + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident))? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETOPTIONS: { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; - - if(get_user(new_options, p)) - return -EFAULT; - - if(new_options & WDIOS_DISABLECARD) { - wdt_turnoff(); - retval = 0; - } - - if(new_options & WDIOS_ENABLECARD) { - wdt_startup(); - retval = 0; - } - - return retval; + int new_options, retval = -EINVAL; + if (get_user(new_options, p)) + return -EFAULT; + if (new_options & WDIOS_DISABLECARD) { + wdt_turnoff(); + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_timeout; - - if(get_user(new_timeout, p)) - return -EFAULT; - - if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ - return -EINVAL; - - timeout = new_timeout; - wdt_keepalive(); - /* Fall through */ + if (new_options & WDIOS_ENABLECARD) { + wdt_startup(); + retval = 0; } - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); + return retval; + } + case WDIOC_SETTIMEOUT: + { + int new_timeout; + if (get_user(new_timeout, p)) + return -EFAULT; + /* arbitrary upper limit */ + if (new_timeout < 1 || new_timeout > 3600) + return -EINVAL; + + timeout = new_timeout; + wdt_keepalive(); + /* Fall through */ + } + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); } } @@ -284,7 +286,7 @@ static const struct file_operations wdt_fops = { .write = fop_write, .open = fop_open, .release = fop_close, - .ioctl = fop_ioctl, + .unlocked_ioctl = fop_ioctl, }; static struct miscdevice wdt_miscdev = { @@ -300,7 +302,7 @@ static struct miscdevice wdt_miscdev = { static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt_turnoff(); return NOTIFY_DONE; } @@ -310,8 +312,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, * turn the timebomb registers off. */ -static struct notifier_block wdt_notifier= -{ +static struct notifier_block wdt_notifier = { .notifier_call = wdt_notify_sys, }; @@ -324,23 +325,22 @@ static void __exit sbc60xxwdt_unload(void) unregister_reboot_notifier(&wdt_notifier); if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) - release_region(wdt_stop,1); - release_region(wdt_start,1); + release_region(wdt_stop, 1); + release_region(wdt_start, 1); } static int __init sbc60xxwdt_init(void) { int rc = -EBUSY; - if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ - { + if (timeout < 1 || timeout > 3600) { /* arbitrary upper limit */ timeout = WATCHDOG_TIMEOUT; - printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", - timeout); - } + printk(KERN_INFO PFX + "timeout value must be 1 <= x <= 3600, using %d\n", + timeout); + } - if (!request_region(wdt_start, 1, "SBC 60XX WDT")) - { + if (!request_region(wdt_start, 1, "SBC 60XX WDT")) { printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", wdt_start); rc = -EIO; @@ -348,33 +348,30 @@ static int __init sbc60xxwdt_init(void) } /* We cannot reserve 0x45 - the kernel already has! */ - if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) - { - if (!request_region(wdt_stop, 1, "SBC 60XX WDT")) - { - printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", - wdt_stop); + if (wdt_stop != 0x45 && wdt_stop != wdt_start) { + if (!request_region(wdt_stop, 1, "SBC 60XX WDT")) { + printk(KERN_ERR PFX + "I/O address 0x%04x already in use\n", + wdt_stop); rc = -EIO; goto err_out_region1; } } rc = register_reboot_notifier(&wdt_notifier); - if (rc) - { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", rc); goto err_out_region2; } rc = misc_register(&wdt_miscdev); - if (rc) - { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - wdt_miscdev.minor, rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + wdt_miscdev.minor, rc); goto err_out_reboot; } - printk(KERN_INFO PFX "WDT driver for 60XX single board computer initialised. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); @@ -383,10 +380,10 @@ static int __init sbc60xxwdt_init(void) err_out_reboot: unregister_reboot_notifier(&wdt_notifier); err_out_region2: - if ((wdt_stop != 0x45) && (wdt_stop != wdt_start)) - release_region(wdt_stop,1); + if (wdt_stop != 0x45 && wdt_stop != wdt_start) + release_region(wdt_stop, 1); err_out_region1: - release_region(wdt_start,1); + release_region(wdt_start, 1); err_out: return rc; } -- cgit v1.2.3 From 619a8a2bb1d0c3f8270da4496a30f1e83e6eab5e Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:16 +0100 Subject: [WATCHDOG 38/57] stg7240_wdt: unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sbc7240_wdt.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/watchdog/sbc7240_wdt.c b/drivers/watchdog/sbc7240_wdt.c index 4c8cefbd8627..abccbe265249 100644 --- a/drivers/watchdog/sbc7240_wdt.c +++ b/drivers/watchdog/sbc7240_wdt.c @@ -27,10 +27,10 @@ #include #include #include +#include +#include #include -#include #include -#include #define SBC7240_PREFIX "sbc7240_wdt: " @@ -159,7 +159,7 @@ static int fop_close(struct inode *inode, struct file *file) return 0; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING| WDIOF_SETTIMEOUT| WDIOF_MAGICCLOSE, @@ -168,14 +168,12 @@ static struct watchdog_info ident = { }; -static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user - ((void __user *)arg, &ident, sizeof(ident)) - ? -EFAULT : 0; + return copy_to_user((void __user *)arg, &ident, sizeof(ident)) + ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, (int __user *)arg); @@ -225,7 +223,7 @@ static const struct file_operations wdt_fops = { .write = fop_write, .open = fop_open, .release = fop_close, - .ioctl = fop_ioctl, + .unlocked_ioctl = fop_ioctl, }; static struct miscdevice wdt_miscdev = { -- cgit v1.2.3 From 9f53c8de1aef08cad678dcda0f85fd8914ad7666 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:22 +0100 Subject: [WATCHDOG 39/57] sbc8360: clean up Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sbc8360.c | 30 ++++++++++++------------------ 1 file changed, 12 insertions(+), 18 deletions(-) diff --git a/drivers/watchdog/sbc8360.c b/drivers/watchdog/sbc8360.c index 2ee2677f3648..c66fa6694fc3 100644 --- a/drivers/watchdog/sbc8360.c +++ b/drivers/watchdog/sbc8360.c @@ -48,13 +48,12 @@ #include #include #include +#include +#include -#include -#include #include static unsigned long sbc8360_is_open; -static DEFINE_SPINLOCK(sbc8360_lock); static char expect_close; #define PFX "sbc8360: " @@ -204,7 +203,8 @@ module_param(timeout, int, 0); MODULE_PARM_DESC(timeout, "Index into timeout table (0-63) (default=27 (60s))"); module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, - "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Kernel methods. @@ -232,8 +232,8 @@ static void sbc8360_ping(void) } /* Userspace pings kernel driver, or requests clean close */ -static ssize_t sbc8360_write(struct file *file, const char __user * buf, - size_t count, loff_t * ppos) +static ssize_t sbc8360_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -257,16 +257,12 @@ static ssize_t sbc8360_write(struct file *file, const char __user * buf, static int sbc8360_open(struct inode *inode, struct file *file) { - spin_lock(&sbc8360_lock); - if (test_and_set_bit(0, &sbc8360_is_open)) { - spin_unlock(&sbc8360_lock); + if (test_and_set_bit(0, &sbc8360_is_open)) return -EBUSY; - } if (nowayout) __module_get(THIS_MODULE); /* Activate and ping once to start the countdown */ - spin_unlock(&sbc8360_lock); sbc8360_activate(); sbc8360_ping(); return nonseekable_open(inode, file); @@ -274,16 +270,14 @@ static int sbc8360_open(struct inode *inode, struct file *file) static int sbc8360_close(struct inode *inode, struct file *file) { - spin_lock(&sbc8360_lock); if (expect_close == 42) outb(0, SBC8360_ENABLE); else printk(KERN_CRIT PFX - "SBC8360 device closed unexpectedly. SBC8360 will not stop!\n"); + "SBC8360 device closed unexpectedly. SBC8360 will not stop!\n"); clear_bit(0, &sbc8360_is_open); expect_close = 0; - spin_unlock(&sbc8360_lock); return 0; } @@ -382,13 +376,13 @@ static int __init sbc8360_init(void) return 0; - out_nomisc: +out_nomisc: unregister_reboot_notifier(&sbc8360_notifier); - out_noreboot: +out_noreboot: release_region(SBC8360_BASETIME, 1); - out_nobasetimereg: +out_nobasetimereg: release_region(SBC8360_ENABLE, 1); - out: +out: return res; } -- cgit v1.2.3 From f4f6f65a554d4a11e544070c39eea7c2ecc3ebfb Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:27 +0100 Subject: [WATCHDOG 40/57] sbc_epx_c3_wdt: switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sbc_epx_c3.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/watchdog/sbc_epx_c3.c b/drivers/watchdog/sbc_epx_c3.c index 82cbd8809a69..70ff9cbc8e9b 100644 --- a/drivers/watchdog/sbc_epx_c3.c +++ b/drivers/watchdog/sbc_epx_c3.c @@ -25,8 +25,8 @@ #include #include #include -#include -#include +#include +#include #define PFX "epx_c3: " static int epx_c3_alive; @@ -100,12 +100,12 @@ static ssize_t epx_c3_write(struct file *file, const char __user *data, return len; } -static int epx_c3_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long epx_c3_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int options, retval = -EINVAL; int __user *argp = (void __user *)arg; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, .firmware_version = 0, @@ -158,7 +158,7 @@ static const struct file_operations epx_c3_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = epx_c3_write, - .ioctl = epx_c3_ioctl, + .unlocked_ioctl = epx_c3_ioctl, .open = epx_c3_open, .release = epx_c3_release, }; -- cgit v1.2.3 From df3c9de3dee539c6b18a9c0797b37f6cb90c6ccb Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:33 +0100 Subject: [WATCHDOG 41/57] sb_wdog: Clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sb_wdog.c | 78 ++++++++++++++++++++++++---------------------- 1 file changed, 40 insertions(+), 38 deletions(-) diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index b94431433695..c8b544ce77fb 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -57,6 +57,7 @@ #include #include +static DEFINE_SPINLOCK(sbwd_lock); /* * set the initial count value of a timer @@ -65,8 +66,10 @@ */ void sbwdog_set(char __iomem *wdog, unsigned long t) { + spin_lock(&sbwd_lock); __raw_writeb(0, wdog - 0x10); __raw_writeq(t & 0x7fffffUL, wdog); + spin_unlock(&sbwd_lock); } /* @@ -77,7 +80,9 @@ void sbwdog_set(char __iomem *wdog, unsigned long t) */ void sbwdog_pet(char __iomem *wdog) { + spin_lock(&sbwd_lock); __raw_writeb(__raw_readb(wdog) | 1, wdog); + spin_unlock(&sbwd_lock); } static unsigned long sbwdog_gate; /* keeps it to one thread only */ @@ -86,8 +91,9 @@ static char __iomem *user_dog = (char __iomem *)(IO_BASE + (A_SCD_WDOG_CFG_1)); static unsigned long timeout = 0x7fffffUL; /* useconds: 8.3ish secs. */ static int expect_close; -static struct watchdog_info ident = { - .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, +static const struct watchdog_info ident = { + .options = WDIOF_CARDRESET | WDIOF_SETTIMEOUT | + WDIOF_KEEPALIVEPING, .identity = "SiByte Watchdog", }; @@ -97,9 +103,8 @@ static struct watchdog_info ident = { static int sbwdog_open(struct inode *inode, struct file *file) { nonseekable_open(inode, file); - if (test_and_set_bit(0, &sbwdog_gate)) { + if (test_and_set_bit(0, &sbwdog_gate)) return -EBUSY; - } __module_get(THIS_MODULE); /* @@ -120,8 +125,9 @@ static int sbwdog_release(struct inode *inode, struct file *file) __raw_writeb(0, user_dog); module_put(THIS_MODULE); } else { - printk(KERN_CRIT "%s: Unexpected close, not stopping watchdog!\n", - ident.identity); + printk(KERN_CRIT + "%s: Unexpected close, not stopping watchdog!\n", + ident.identity); sbwdog_pet(user_dog); } clear_bit(0, &sbwdog_gate); @@ -147,12 +153,10 @@ static ssize_t sbwdog_write(struct file *file, const char __user *data, for (i = 0; i != len; i++) { char c; - if (get_user(c, data + i)) { + if (get_user(c, data + i)) return -EFAULT; - } - if (c == 'V') { + if (c == 'V') expect_close = 42; - } } sbwdog_pet(user_dog); } @@ -160,8 +164,8 @@ static ssize_t sbwdog_write(struct file *file, const char __user *data, return len; } -static int sbwdog_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long sbwdog_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int ret = -ENOTTY; unsigned long time; @@ -180,9 +184,8 @@ static int sbwdog_ioctl(struct inode *inode, struct file *file, case WDIOC_SETTIMEOUT: ret = get_user(time, p); - if (ret) { + if (ret) break; - } time *= 1000000; if (time > 0x7fffffUL) { @@ -226,18 +229,16 @@ sbwdog_notify_sys(struct notifier_block *this, unsigned long code, void *erf) return NOTIFY_DONE; } -static const struct file_operations sbwdog_fops = -{ +static const struct file_operations sbwdog_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = sbwdog_write, - .ioctl = sbwdog_ioctl, + .unlocked_ioctl = sbwdog_ioctl, .open = sbwdog_open, .release = sbwdog_release, }; -static struct miscdevice sbwdog_miscdev = -{ +static struct miscdevice sbwdog_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &sbwdog_fops, @@ -267,13 +268,12 @@ irqreturn_t sbwdog_interrupt(int irq, void *addr) /* * if it's the second watchdog timer, it's for those users */ - if (wd_cfg_reg == user_dog) { + if (wd_cfg_reg == user_dog) printk(KERN_CRIT "%s in danger of initiating system reset in %ld.%01ld seconds\n", ident.identity, wd_init / 1000000, (wd_init / 100000) % 10); - } else { + else cfg |= 1; - } __raw_writeb(cfg, wd_cfg_reg); @@ -289,28 +289,31 @@ static int __init sbwdog_init(void) */ ret = register_reboot_notifier(&sbwdog_notifier); if (ret) { - printk (KERN_ERR "%s: cannot register reboot notifier (err=%d)\n", - ident.identity, ret); + printk(KERN_ERR + "%s: cannot register reboot notifier (err=%d)\n", + ident.identity, ret); return ret; } /* * get the resources */ - ret = misc_register(&sbwdog_miscdev); - if (ret == 0) { - printk(KERN_INFO "%s: timeout is %ld.%ld secs\n", ident.identity, - timeout / 1000000, (timeout / 100000) % 10); - } ret = request_irq(1, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, ident.identity, (void *)user_dog); if (ret) { - printk(KERN_ERR "%s: failed to request irq 1 - %d\n", ident.identity, - ret); - misc_deregister(&sbwdog_miscdev); + printk(KERN_ERR "%s: failed to request irq 1 - %d\n", + ident.identity, ret); + return ret; } + ret = misc_register(&sbwdog_miscdev); + if (ret == 0) { + printk(KERN_INFO "%s: timeout is %ld.%ld secs\n", + ident.identity, + timeout / 1000000, (timeout / 100000) % 10); + } else + free_irq(1, (void *)user_dog); return ret; } @@ -327,7 +330,7 @@ MODULE_DESCRIPTION("SiByte Watchdog"); module_param(timeout, ulong, 0); MODULE_PARM_DESC(timeout, - "Watchdog timeout in microseconds (max/default 8388607 or 8.3ish secs)"); + "Watchdog timeout in microseconds (max/default 8388607 or 8.3ish secs)"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); @@ -336,16 +339,15 @@ MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); * example code that can be put in a platform code area to utilize the * first watchdog timer for the kernels own purpose. - void -platform_wd_setup(void) +void platform_wd_setup(void) { int ret; - ret = request_irq(0, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, + ret = request_irq(1, sbwdog_interrupt, IRQF_DISABLED | IRQF_SHARED, "Kernel Watchdog", IOADDR(A_SCD_WDOG_CFG_0)); if (ret) { - printk(KERN_CRIT "Watchdog IRQ zero(0) failed to be requested - %d\n", - ret); + printk(KERN_CRIT + "Watchdog IRQ zero(0) failed to be requested - %d\n", ret); } } -- cgit v1.2.3 From d14bccaadaa49b651fabcd1298b6ea07db3af552 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:38 +0100 Subject: [WATCHDOG 42/57] sc1200_wdt: clean up, fix locking and use unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sc1200wdt.c | 203 ++++++++++++++++++++++++------------------- 1 file changed, 114 insertions(+), 89 deletions(-) diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index 35cddff7020f..7e5c9cc97dee 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c @@ -15,14 +15,18 @@ * * Changelog: * 20020220 Zwane Mwaikambo Code based on datasheet, no hardware. - * 20020221 Zwane Mwaikambo Cleanups as suggested by Jeff Garzik and Alan Cox. + * 20020221 Zwane Mwaikambo Cleanups as suggested by Jeff Garzik + * and Alan Cox. * 20020222 Zwane Mwaikambo Added probing. * 20020225 Zwane Mwaikambo Added ISAPNP support. * 20020412 Rob Radez Broke out start/stop functions - * Return proper status instead of temperature warning - * Add WDIOC_GETBOOTSTATUS and WDIOC_SETOPTIONS ioctls + * Return proper status instead of + * temperature warning + * Add WDIOC_GETBOOTSTATUS and + * WDIOC_SETOPTIONS ioctls * Fix CONFIG_WATCHDOG_NOWAYOUT - * 20020530 Joel Becker Add Matt Domsch's nowayout module option + * 20020530 Joel Becker Add Matt Domsch's nowayout module + * option * 20030116 Adam Belay Updated to the latest pnp code * */ @@ -39,9 +43,8 @@ #include #include #include - -#include -#include +#include +#include #define SC1200_MODULE_VER "build 20020303" #define SC1200_MODULE_NAME "sc1200wdt" @@ -72,7 +75,7 @@ static char banner[] __initdata = KERN_INFO PFX SC1200_MODULE_VER; static int timeout = 1; static int io = -1; static int io_len = 2; /* for non plug and play */ -static struct semaphore open_sem; +static unsigned long open_flag; static char expect_close; static DEFINE_SPINLOCK(sc1200wdt_lock); /* io port access serialisation */ @@ -81,7 +84,8 @@ static int isapnp = 1; static struct pnp_dev *wdt_dev; module_param(isapnp, int, 0); -MODULE_PARM_DESC(isapnp, "When set to 0 driver ISA PnP support will be disabled"); +MODULE_PARM_DESC(isapnp, + "When set to 0 driver ISA PnP support will be disabled"); #endif module_param(io, int, 0); @@ -91,26 +95,40 @@ MODULE_PARM_DESC(timeout, "range is 0-255 minutes, default is 1"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* Read from Data Register */ -static inline void sc1200wdt_read_data(unsigned char index, unsigned char *data) +static inline void __sc1200wdt_read_data(unsigned char index, + unsigned char *data) { - spin_lock(&sc1200wdt_lock); outb_p(index, PMIR); *data = inb(PMDR); - spin_unlock(&sc1200wdt_lock); } +static void sc1200wdt_read_data(unsigned char index, unsigned char *data) +{ + spin_lock(&sc1200wdt_lock); + __sc1200wdt_read_data(index, data); + spin_unlock(&sc1200wdt_lock); +} /* Write to Data Register */ -static inline void sc1200wdt_write_data(unsigned char index, unsigned char data) +static inline void __sc1200wdt_write_data(unsigned char index, + unsigned char data) { - spin_lock(&sc1200wdt_lock); outb_p(index, PMIR); outb(data, PMDR); +} + +static inline void sc1200wdt_write_data(unsigned char index, + unsigned char data) +{ + spin_lock(&sc1200wdt_lock); + __sc1200wdt_write_data(index, data); spin_unlock(&sc1200wdt_lock); } @@ -118,13 +136,16 @@ static inline void sc1200wdt_write_data(unsigned char index, unsigned char data) static void sc1200wdt_start(void) { unsigned char reg; + spin_lock(&sc1200wdt_lock); - sc1200wdt_read_data(WDCF, ®); + __sc1200wdt_read_data(WDCF, ®); /* assert WDO when any of the following interrupts are triggered too */ reg |= (KBC_IRQ | MSE_IRQ | UART1_IRQ | UART2_IRQ); - sc1200wdt_write_data(WDCF, reg); + __sc1200wdt_write_data(WDCF, reg); /* set the timeout and get the ball rolling */ - sc1200wdt_write_data(WDTO, timeout); + __sc1200wdt_write_data(WDTO, timeout); + + spin_unlock(&sc1200wdt_lock); } @@ -144,14 +165,15 @@ static inline int sc1200wdt_status(void) * KEEPALIVEPING which is a bit of a kludge because there's nothing * else for enabled/disabled status */ - return (ret & 0x01) ? 0 : WDIOF_KEEPALIVEPING; /* bits 1 - 7 are undefined */ + return (ret & 0x01) ? 0 : WDIOF_KEEPALIVEPING; + /* bits 1 - 7 are undefined */ } static int sc1200wdt_open(struct inode *inode, struct file *file) { /* allow one at a time */ - if (down_trylock(&open_sem)) + if (test_and_set_bit(0, &open_flag)) return -EBUSY; if (timeout > MAX_TIMEOUT) @@ -164,71 +186,71 @@ static int sc1200wdt_open(struct inode *inode, struct file *file) } -static int sc1200wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) +static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_timeout; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, .firmware_version = 0, .identity = "PC87307/PC97307", }; switch (cmd) { - default: - return -ENOTTY; - - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof ident)) - return -EFAULT; - return 0; - case WDIOC_GETSTATUS: - return put_user(sc1200wdt_status(), p); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof ident)) + return -EFAULT; + return 0; - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); + case WDIOC_GETSTATUS: + return put_user(sc1200wdt_status(), p); - case WDIOC_KEEPALIVE: - sc1200wdt_write_data(WDTO, timeout); - return 0; + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - - /* the API states this is given in secs */ - new_timeout /= 60; - if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) - return -EINVAL; - - timeout = new_timeout; - sc1200wdt_write_data(WDTO, timeout); - /* fall through and return the new timeout */ - - case WDIOC_GETTIMEOUT: - return put_user(timeout * 60, p); + case WDIOC_KEEPALIVE: + sc1200wdt_write_data(WDTO, timeout); + return 0; + + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + /* the API states this is given in secs */ + new_timeout /= 60; + if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) + return -EINVAL; + timeout = new_timeout; + sc1200wdt_write_data(WDTO, timeout); + /* fall through and return the new timeout */ - case WDIOC_SETOPTIONS: - { - int options, retval = -EINVAL; + case WDIOC_GETTIMEOUT: + return put_user(timeout * 60, p); - if (get_user(options, p)) - return -EFAULT; + case WDIOC_SETOPTIONS: + { + int options, retval = -EINVAL; - if (options & WDIOS_DISABLECARD) { - sc1200wdt_stop(); - retval = 0; - } + if (get_user(options, p)) + return -EFAULT; - if (options & WDIOS_ENABLECARD) { - sc1200wdt_start(); - retval = 0; - } + if (options & WDIOS_DISABLECARD) { + sc1200wdt_stop(); + retval = 0; + } - return retval; + if (options & WDIOS_ENABLECARD) { + sc1200wdt_start(); + retval = 0; } + + return retval; + } + default: + return -ENOTTY; } } @@ -240,16 +262,18 @@ static int sc1200wdt_release(struct inode *inode, struct file *file) printk(KERN_INFO PFX "Watchdog disabled\n"); } else { sc1200wdt_write_data(WDTO, timeout); - printk(KERN_CRIT PFX "Unexpected close!, timeout = %d min(s)\n", timeout); + printk(KERN_CRIT PFX + "Unexpected close!, timeout = %d min(s)\n", timeout); } - up(&open_sem); + clear_bit(0, &open_flag); expect_close = 0; return 0; } -static ssize_t sc1200wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) +static ssize_t sc1200wdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) { if (len) { if (!nowayout) { @@ -275,7 +299,8 @@ static ssize_t sc1200wdt_write(struct file *file, const char __user *data, size_ } -static int sc1200wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) +static int sc1200wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) sc1200wdt_stop(); @@ -284,23 +309,20 @@ static int sc1200wdt_notify_sys(struct notifier_block *this, unsigned long code, } -static struct notifier_block sc1200wdt_notifier = -{ +static struct notifier_block sc1200wdt_notifier = { .notifier_call = sc1200wdt_notify_sys, }; -static const struct file_operations sc1200wdt_fops = -{ +static const struct file_operations sc1200wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = sc1200wdt_write, - .ioctl = sc1200wdt_ioctl, + .unlocked_ioctl = sc1200wdt_ioctl, .open = sc1200wdt_open, .release = sc1200wdt_release, }; -static struct miscdevice sc1200wdt_miscdev = -{ +static struct miscdevice sc1200wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &sc1200wdt_fops, @@ -312,14 +334,14 @@ static int __init sc1200wdt_probe(void) /* The probe works by reading the PMC3 register's default value of 0x0e * there is one caveat, if the device disables the parallel port or any * of the UARTs we won't be able to detect it. - * Nb. This could be done with accuracy by reading the SID registers, but - * we don't have access to those io regions. + * NB. This could be done with accuracy by reading the SID registers, + * but we don't have access to those io regions. */ unsigned char reg; sc1200wdt_read_data(PMC3, ®); - reg &= 0x0f; /* we don't want the UART busy bits */ + reg &= 0x0f; /* we don't want the UART busy bits */ return (reg == 0x0e) ? 0 : -ENODEV; } @@ -332,7 +354,8 @@ static struct pnp_device_id scl200wdt_pnp_devices[] = { {.id = ""}, }; -static int scl200wdt_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id *dev_id) +static int scl200wdt_pnp_probe(struct pnp_dev *dev, + const struct pnp_device_id *dev_id) { /* this driver only supports one card at a time */ if (wdt_dev || !isapnp) @@ -347,13 +370,14 @@ static int scl200wdt_pnp_probe(struct pnp_dev * dev, const struct pnp_device_id return -EBUSY; } - printk(KERN_INFO "scl200wdt: PnP device found at io port %#x/%d\n", io, io_len); + printk(KERN_INFO "scl200wdt: PnP device found at io port %#x/%d\n", + io, io_len); return 0; } -static void scl200wdt_pnp_remove(struct pnp_dev * dev) +static void scl200wdt_pnp_remove(struct pnp_dev *dev) { - if (wdt_dev){ + if (wdt_dev) { release_region(io, io_len); wdt_dev = NULL; } @@ -375,8 +399,6 @@ static int __init sc1200wdt_init(void) printk("%s\n", banner); - sema_init(&open_sem, 1); - #if defined CONFIG_PNP if (isapnp) { ret = pnp_register_driver(&scl200wdt_pnp_driver); @@ -410,13 +432,16 @@ static int __init sc1200wdt_init(void) ret = register_reboot_notifier(&sc1200wdt_notifier); if (ret) { - printk(KERN_ERR PFX "Unable to register reboot notifier err = %d\n", ret); + printk(KERN_ERR PFX + "Unable to register reboot notifier err = %d\n", ret); goto out_io; } ret = misc_register(&sc1200wdt_miscdev); if (ret) { - printk(KERN_ERR PFX "Unable to register miscdev on minor %d\n", WATCHDOG_MINOR); + printk(KERN_ERR PFX + "Unable to register miscdev on minor %d\n", + WATCHDOG_MINOR); goto out_rbt; } @@ -446,7 +471,7 @@ static void __exit sc1200wdt_exit(void) unregister_reboot_notifier(&sc1200wdt_notifier); #if defined CONFIG_PNP - if(isapnp) + if (isapnp) pnp_unregister_driver(&scl200wdt_pnp_driver); else #endif -- cgit v1.2.3 From ff94806057fba557abd6295f7313f5f9e972a48f Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:44 +0100 Subject: [WATCHDOG 43/57] sc520_wdt: Clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sc520_wdt.c | 161 +++++++++++++++++++++++-------------------- 1 file changed, 86 insertions(+), 75 deletions(-) diff --git a/drivers/watchdog/sc520_wdt.c b/drivers/watchdog/sc520_wdt.c index 2847324a2be2..525555a8779c 100644 --- a/drivers/watchdog/sc520_wdt.c +++ b/drivers/watchdog/sc520_wdt.c @@ -64,9 +64,9 @@ #include #include #include +#include +#include -#include -#include #include #define OUR_NAME "sc520_wdt" @@ -91,13 +91,18 @@ */ #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ -static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +/* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +static int timeout = WATCHDOG_TIMEOUT; module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1 <= timeout <= 3600, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * AMD Elan SC520 - Watchdog Timer Registers @@ -136,8 +141,7 @@ static void wdt_timer_ping(unsigned long data) /* If we got a heartbeat pulse within the WDT_US_INTERVAL * we agree to ping the WDT */ - if(time_before(jiffies, next_heartbeat)) - { + if (time_before(jiffies, next_heartbeat)) { /* Ping the WDT */ spin_lock(&wdt_spinlock); writew(0xAAAA, wdtmrctl); @@ -146,9 +150,9 @@ static void wdt_timer_ping(unsigned long data) /* Re-set the timer interval */ mod_timer(&timer, jiffies + WDT_INTERVAL); - } else { - printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); - } + } else + printk(KERN_WARNING PFX + "Heartbeat lost! Will not ping the watchdog\n"); } /* @@ -162,7 +166,7 @@ static void wdt_config(int writeval) /* buy some time (ping) */ spin_lock_irqsave(&wdt_spinlock, flags); - dummy=readw(wdtmrctl); /* ensure write synchronization */ + dummy = readw(wdtmrctl); /* ensure write synchronization */ writew(0xAAAA, wdtmrctl); writew(0x5555, wdtmrctl); /* unlock WDT = make WDT configuration register writable one time */ @@ -219,10 +223,11 @@ static int wdt_set_heartbeat(int t) * /dev/watchdog handling */ -static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) +static ssize_t fop_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) { + if (count) { if (!nowayout) { size_t ofs; @@ -231,25 +236,26 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou wdt_expect_close = 0; /* now scan */ - for(ofs = 0; ofs != count; ofs++) { + for (ofs = 0; ofs != count; ofs++) { char c; if (get_user(c, buf + ofs)) return -EFAULT; - if(c == 'V') + if (c == 'V') wdt_expect_close = 42; } } - /* Well, anyhow someone wrote to us, we should return that favour */ + /* Well, anyhow someone wrote to us, we should + return that favour */ wdt_keepalive(); } return count; } -static int fop_open(struct inode * inode, struct file * file) +static int fop_open(struct inode *inode, struct file *file) { /* Just in case we're already talking to someone... */ - if(test_and_set_bit(0, &wdt_is_open)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; if (nowayout) __module_get(THIS_MODULE); @@ -259,12 +265,13 @@ static int fop_open(struct inode * inode, struct file * file) return nonseekable_open(inode, file); } -static int fop_close(struct inode * inode, struct file * file) +static int fop_close(struct inode *inode, struct file *file) { - if(wdt_expect_close == 42) { + if (wdt_expect_close == 42) wdt_turnoff(); - } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); wdt_keepalive(); } clear_bit(0, &wdt_is_open); @@ -272,63 +279,63 @@ static int fop_close(struct inode * inode, struct file * file) return 0; } -static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static int fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "SC520", }; - switch(cmd) + switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; - - if(get_user(new_options, p)) - return -EFAULT; - - if(new_options & WDIOS_DISABLECARD) { - wdt_turnoff(); - retval = 0; - } + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETOPTIONS: + { + int new_options, retval = -EINVAL; - if(new_options & WDIOS_ENABLECARD) { - wdt_startup(); - retval = 0; - } + if (get_user(new_options, p)) + return -EFAULT; + + if (new_options & WDIOS_DISABLECARD) { + wdt_turnoff(); + retval = 0; + } - return retval; + if (new_options & WDIOS_ENABLECARD) { + wdt_startup(); + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_timeout; - if(get_user(new_timeout, p)) - return -EFAULT; + return retval; + } + case WDIOC_SETTIMEOUT: + { + int new_timeout; - if(wdt_set_heartbeat(new_timeout)) - return -EINVAL; + if (get_user(new_timeout, p)) + return -EFAULT; - wdt_keepalive(); - /* Fall through */ - } - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); + if (wdt_set_heartbeat(new_timeout)) + return -EINVAL; + + wdt_keepalive(); + /* Fall through */ + } + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); } } @@ -354,7 +361,7 @@ static struct miscdevice wdt_miscdev = { static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt_turnoff(); return NOTIFY_DONE; } @@ -383,11 +390,13 @@ static int __init sc520_wdt_init(void) { int rc = -EBUSY; - /* Check that the timeout value is within it's range ; if not reset to the default */ + /* Check that the timeout value is within it's range ; + if not reset to the default */ if (wdt_set_heartbeat(timeout)) { wdt_set_heartbeat(WATCHDOG_TIMEOUT); - printk(KERN_INFO PFX "timeout value must be 1<=timeout<=3600, using %d\n", - WATCHDOG_TIMEOUT); + printk(KERN_INFO PFX + "timeout value must be 1 <= timeout <= 3600, using %d\n", + WATCHDOG_TIMEOUT); } wdtmrctl = ioremap((unsigned long)(MMCR_BASE + OFFS_WDTMRCTL), 2); @@ -399,20 +408,22 @@ static int __init sc520_wdt_init(void) rc = register_reboot_notifier(&wdt_notifier); if (rc) { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - rc); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", rc); goto err_out_ioremap; } rc = misc_register(&wdt_miscdev); if (rc) { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, rc); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, rc); goto err_out_notifier; } - printk(KERN_INFO PFX "WDT driver for SC520 initialised. timeout=%d sec (nowayout=%d)\n", - timeout,nowayout); + printk(KERN_INFO PFX + "WDT driver for SC520 initialised. timeout=%d sec (nowayout=%d)\n", + timeout, nowayout); return 0; -- cgit v1.2.3 From 9b748ed03cabf533a815e5ffc50108a21c98e40c Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:49 +0100 Subject: [WATCHDOG 44/57] scx200_wdt: clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sc520_wdt.c | 4 +-- drivers/watchdog/scx200_wdt.c | 59 ++++++++++++++++++++++--------------------- 2 files changed, 32 insertions(+), 31 deletions(-) diff --git a/drivers/watchdog/sc520_wdt.c b/drivers/watchdog/sc520_wdt.c index 525555a8779c..01de239f49e8 100644 --- a/drivers/watchdog/sc520_wdt.c +++ b/drivers/watchdog/sc520_wdt.c @@ -279,7 +279,7 @@ static int fop_close(struct inode *inode, struct file *file) return 0; } -static int fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -345,7 +345,7 @@ static const struct file_operations wdt_fops = { .write = fop_write, .open = fop_open, .release = fop_close, - .ioctl = fop_ioctl, + .unlocked_ioctl = fop_ioctl, }; static struct miscdevice wdt_miscdev = { diff --git a/drivers/watchdog/scx200_wdt.c b/drivers/watchdog/scx200_wdt.c index d55882bca319..7c1de94704f3 100644 --- a/drivers/watchdog/scx200_wdt.c +++ b/drivers/watchdog/scx200_wdt.c @@ -27,9 +27,8 @@ #include #include #include - -#include -#include +#include +#include #define NAME "scx200_wdt" @@ -47,8 +46,9 @@ module_param(nowayout, int, 0); MODULE_PARM_DESC(nowayout, "Disable watchdog shutdown on close"); static u16 wdto_restart; -static struct semaphore open_semaphore; static char expect_close; +static unsigned long open_lock; +static DEFINE_SPINLOCK(scx_lock); /* Bits of the WDCNFG register */ #define W_ENABLE 0x00fa /* Enable watchdog */ @@ -59,7 +59,9 @@ static char expect_close; static void scx200_wdt_ping(void) { + spin_lock(&scx_lock); outw(wdto_restart, scx200_cb_base + SCx200_WDT_WDTO); + spin_unlock(&scx_lock); } static void scx200_wdt_update_margin(void) @@ -73,9 +75,11 @@ static void scx200_wdt_enable(void) printk(KERN_DEBUG NAME ": enabling watchdog timer, wdto_restart = %d\n", wdto_restart); + spin_lock(&scx_lock); outw(0, scx200_cb_base + SCx200_WDT_WDTO); outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); outw(W_ENABLE, scx200_cb_base + SCx200_WDT_WDCNFG); + spin_unlock(&scx_lock); scx200_wdt_ping(); } @@ -84,15 +88,17 @@ static void scx200_wdt_disable(void) { printk(KERN_DEBUG NAME ": disabling watchdog timer\n"); + spin_lock(&scx_lock); outw(0, scx200_cb_base + SCx200_WDT_WDTO); outb(SCx200_WDT_WDSTS_WDOVF, scx200_cb_base + SCx200_WDT_WDSTS); outw(W_DISABLE, scx200_cb_base + SCx200_WDT_WDCNFG); + spin_unlock(&scx_lock); } static int scx200_wdt_open(struct inode *inode, struct file *file) { /* only allow one at a time */ - if (down_trylock(&open_semaphore)) + if (test_and_set_bit(0, &open_lock)) return -EBUSY; scx200_wdt_enable(); @@ -101,13 +107,12 @@ static int scx200_wdt_open(struct inode *inode, struct file *file) static int scx200_wdt_release(struct inode *inode, struct file *file) { - if (expect_close != 42) { + if (expect_close != 42) printk(KERN_WARNING NAME ": watchdog device closed unexpectedly, will not disable the watchdog timer\n"); - } else if (!nowayout) { + else if (!nowayout) scx200_wdt_disable(); - } expect_close = 0; - up(&open_semaphore); + clear_bit(0, &open_lock); return 0; } @@ -122,8 +127,7 @@ static int scx200_wdt_notify_sys(struct notifier_block *this, return NOTIFY_DONE; } -static struct notifier_block scx200_wdt_notifier = -{ +static struct notifier_block scx200_wdt_notifier = { .notifier_call = scx200_wdt_notify_sys, }; @@ -131,8 +135,7 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, size_t len, loff_t *ppos) { /* check for a magic close character */ - if (len) - { + if (len) { size_t i; scx200_wdt_ping(); @@ -152,15 +155,15 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, return 0; } -static int scx200_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long scx200_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .identity = "NatSemi SCx200 Watchdog", .firmware_version = 1, - .options = (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING), + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, }; int new_margin; @@ -168,7 +171,7 @@ static int scx200_wdt_ioctl(struct inode *inode, struct file *file, default: return -ENOTTY; case WDIOC_GETSUPPORT: - if(copy_to_user(argp, &ident, sizeof(ident))) + if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; return 0; case WDIOC_GETSTATUS: @@ -195,18 +198,18 @@ static int scx200_wdt_ioctl(struct inode *inode, struct file *file, } static const struct file_operations scx200_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = scx200_wdt_write, - .ioctl = scx200_wdt_ioctl, - .open = scx200_wdt_open, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = scx200_wdt_write, + .unlocked_ioctl = scx200_wdt_ioctl, + .open = scx200_wdt_open, .release = scx200_wdt_release, }; static struct miscdevice scx200_wdt_miscdev = { .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &scx200_wdt_fops, + .name = "watchdog", + .fops = &scx200_wdt_fops, }; static int __init scx200_wdt_init(void) @@ -229,8 +232,6 @@ static int __init scx200_wdt_init(void) scx200_wdt_update_margin(); scx200_wdt_disable(); - sema_init(&open_semaphore, 1); - r = register_reboot_notifier(&scx200_wdt_notifier); if (r) { printk(KERN_ERR NAME ": unable to register reboot notifier"); @@ -263,7 +264,7 @@ module_exit(scx200_wdt_cleanup); /* Local variables: - compile-command: "make -k -C ../.. SUBDIRS=drivers/char modules" - c-basic-offset: 8 + compile-command: "make -k -C ../.. SUBDIRS=drivers/char modules" + c-basic-offset: 8 End: */ -- cgit v1.2.3 From 70b814ec1a484279a51bf9f7193551b996627247 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:08:55 +0100 Subject: [WATCHDOG 45/57] shwdt: coding style, cleanup, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/shwdt.c | 139 ++++++++++++++++++++++++++++------------------- 1 file changed, 82 insertions(+), 57 deletions(-) diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 1277f7e9cc54..60f0036aaca6 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -28,9 +28,9 @@ #include #include #include -#include -#include -#include +#include +#include +#include #define PFX "shwdt: " @@ -72,6 +72,7 @@ static struct watchdog_info sh_wdt_info; static char shwdt_expect_close; static DEFINE_TIMER(timer, sh_wdt_ping, 0, 0); static unsigned long next_heartbeat; +static DEFINE_SPINLOCK(shwdt_lock); #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */ static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */ @@ -86,6 +87,9 @@ static int nowayout = WATCHDOG_NOWAYOUT; static void sh_wdt_start(void) { __u8 csr; + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); mod_timer(&timer, next_ping_period(clock_division_ratio)); @@ -123,6 +127,7 @@ static void sh_wdt_start(void) csr &= ~RSTCSR_RSTS; sh_wdt_write_rstcsr(csr); #endif + spin_unlock_irqrestore(&wdt_lock, flags); } /** @@ -132,12 +137,16 @@ static void sh_wdt_start(void) static void sh_wdt_stop(void) { __u8 csr; + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); del_timer(&timer); csr = sh_wdt_read_csr(); csr &= ~WTCSR_TME; sh_wdt_write_csr(csr); + spin_unlock_irqrestore(&wdt_lock, flags); } /** @@ -146,7 +155,11 @@ static void sh_wdt_stop(void) */ static inline void sh_wdt_keepalive(void) { + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); next_heartbeat = jiffies + (heartbeat * HZ); + spin_unlock_irqrestore(&wdt_lock, flags); } /** @@ -155,10 +168,14 @@ static inline void sh_wdt_keepalive(void) */ static int sh_wdt_set_heartbeat(int t) { - if (unlikely((t < 1) || (t > 3600))) /* arbitrary upper limit */ + unsigned long flags; + + if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */ return -EINVAL; + spin_lock_irqsave(&wdt_lock, flags); heartbeat = t; + spin_unlock_irqrestore(&wdt_lock, flags); return 0; } @@ -170,6 +187,9 @@ static int sh_wdt_set_heartbeat(int t) */ static void sh_wdt_ping(unsigned long data) { + unsigned long flags; + + spin_lock_irqsave(&wdt_lock, flags); if (time_before(jiffies, next_heartbeat)) { __u8 csr; @@ -183,6 +203,7 @@ static void sh_wdt_ping(unsigned long data) } else printk(KERN_WARNING PFX "Heartbeat lost! Will not ping " "the watchdog\n"); + spin_unlock_irqrestore(&wdt_lock, flags); } /** @@ -310,7 +331,6 @@ static int sh_wdt_mmap(struct file *file, struct vm_area_struct *vma) /** * sh_wdt_ioctl - Query Device - * @inode: inode of device * @file: file handle of device * @cmd: watchdog command * @arg: argument @@ -318,53 +338,51 @@ static int sh_wdt_mmap(struct file *file, struct vm_area_struct *vma) * Query basic information from the device or ping it, as outlined by the * watchdog API. */ -static int sh_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long sh_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_heartbeat; int options, retval = -EINVAL; switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user((struct watchdog_info *)arg, - &sh_wdt_info, - sizeof(sh_wdt_info)) ? -EFAULT : 0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, (int *)arg); - case WDIOC_KEEPALIVE: - sh_wdt_keepalive(); - return 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_heartbeat, (int *)arg)) - return -EFAULT; - - if (sh_wdt_set_heartbeat(new_heartbeat)) - return -EINVAL; - - sh_wdt_keepalive(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, (int *)arg); - case WDIOC_SETOPTIONS: - if (get_user(options, (int *)arg)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - sh_wdt_stop(); - retval = 0; - } + case WDIOC_GETSUPPORT: + return copy_to_user((struct watchdog_info *)arg, + &sh_wdt_info, sizeof(sh_wdt_info)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, (int *)arg); + case WDIOC_KEEPALIVE: + sh_wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_heartbeat, (int *)arg)) + return -EFAULT; - if (options & WDIOS_ENABLECARD) { - sh_wdt_start(); - retval = 0; - } + if (sh_wdt_set_heartbeat(new_heartbeat)) + return -EINVAL; - return retval; - default: - return -ENOTTY; - } + sh_wdt_keepalive(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, (int *)arg); + case WDIOC_SETOPTIONS: + if (get_user(options, (int *)arg)) + return -EFAULT; + + if (options & WDIOS_DISABLECARD) { + sh_wdt_stop(); + retval = 0; + } + + if (options & WDIOS_ENABLECARD) { + sh_wdt_start(); + retval = 0; + } + return retval; + default: + return -ENOTTY; + } return 0; } @@ -390,13 +408,13 @@ static const struct file_operations sh_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = sh_wdt_write, - .ioctl = sh_wdt_ioctl, + .unlocked_ioctl = sh_wdt_ioctl, .open = sh_wdt_open, .release = sh_wdt_close, .mmap = sh_wdt_mmap, }; -static struct watchdog_info sh_wdt_info = { +static const struct watchdog_info sh_wdt_info = { .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, @@ -422,30 +440,33 @@ static int __init sh_wdt_init(void) { int rc; - if ((clock_division_ratio < 0x5) || (clock_division_ratio > 0x7)) { + if (clock_division_ratio < 0x5 || clock_division_ratio > 0x7) { clock_division_ratio = WTCSR_CKS_4096; - printk(KERN_INFO PFX "clock_division_ratio value must " - "be 0x5<=x<=0x7, using %d\n", clock_division_ratio); + printk(KERN_INFO PFX + "clock_division_ratio value must be 0x5<=x<=0x7, using %d\n", + clock_division_ratio); } rc = sh_wdt_set_heartbeat(heartbeat); if (unlikely(rc)) { heartbeat = WATCHDOG_HEARTBEAT; - printk(KERN_INFO PFX "heartbeat value must " - "be 1<=x<=3600, using %d\n", heartbeat); + printk(KERN_INFO PFX + "heartbeat value must be 1<=x<=3600, using %d\n", + heartbeat); } rc = register_reboot_notifier(&sh_wdt_notifier); if (unlikely(rc)) { - printk(KERN_ERR PFX "Can't register reboot notifier (err=%d)\n", - rc); + printk(KERN_ERR PFX + "Can't register reboot notifier (err=%d)\n", rc); return rc; } rc = misc_register(&sh_wdt_miscdev); if (unlikely(rc)) { - printk(KERN_ERR PFX "Can't register miscdev on " - "minor=%d (err=%d)\n", sh_wdt_miscdev.minor, rc); + printk(KERN_ERR PFX + "Can't register miscdev on minor=%d (err=%d)\n", + sh_wdt_miscdev.minor, rc); unregister_reboot_notifier(&sh_wdt_notifier); return rc; } @@ -476,10 +497,14 @@ module_param(clock_division_ratio, int, 0); MODULE_PARM_DESC(clock_division_ratio, "Clock division ratio. Valid ranges are from 0x5 (1.31ms) to 0x7 (5.25ms). (default=" __MODULE_STRING(clock_division_ratio) ")"); module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (1<=heartbeat<=3600, default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); +MODULE_PARM_DESC(heartbeat, + "Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default=" + __MODULE_STRING(WATCHDOG_HEARTBEAT) ")"); module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); module_init(sh_wdt_init); module_exit(sh_wdt_exit); -- cgit v1.2.3 From 598467938dd8bcdcd4d88e9102c609f4caa9d9ef Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:00 +0100 Subject: [WATCHDOG 46/57] smsc37b787_wdt: coding style, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/smsc37b787_wdt.c | 442 +++++++++++++++++++------------------- 1 file changed, 222 insertions(+), 220 deletions(-) diff --git a/drivers/watchdog/smsc37b787_wdt.c b/drivers/watchdog/smsc37b787_wdt.c index 5d2b5ba61414..b7c6394b7d70 100644 --- a/drivers/watchdog/smsc37b787_wdt.c +++ b/drivers/watchdog/smsc37b787_wdt.c @@ -18,7 +18,7 @@ * History: * 2003 - Created version 1.0 for Linux 2.4.x. * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE - * features. Released version 1.1 + * features. Released version 1.1 * * Theory of operation: * @@ -55,9 +55,9 @@ #include #include #include +#include +#include -#include -#include #include /* enable support for minutes as units? */ @@ -71,15 +71,15 @@ #define UNIT_MINUTE 1 #define MODNAME "smsc37b787_wdt: " -#define VERSION "1.1" +#define VERSION "1.1" -#define IOPORT 0x3F0 +#define IOPORT 0x3F0 #define IOPORT_SIZE 2 -#define IODEV_NO 8 +#define IODEV_NO 8 -static int unit = UNIT_SECOND; /* timer's unit */ -static int timeout = 60; /* timeout value: default is 60 "units" */ -static unsigned long timer_enabled = 0; /* is the timer enabled? */ +static int unit = UNIT_SECOND; /* timer's unit */ +static int timeout = 60; /* timeout value: default is 60 "units" */ +static unsigned long timer_enabled; /* is the timer enabled? */ static char expect_close; /* is the close expected? */ @@ -93,114 +93,121 @@ static int nowayout = WATCHDOG_NOWAYOUT; static inline void open_io_config(void) { - outb(0x55, IOPORT); + outb(0x55, IOPORT); mdelay(1); - outb(0x55, IOPORT); + outb(0x55, IOPORT); } /* lock the IO chip */ static inline void close_io_config(void) { - outb(0xAA, IOPORT); + outb(0xAA, IOPORT); } /* select the IO device */ static inline void select_io_device(unsigned char devno) { - outb(0x07, IOPORT); - outb(devno, IOPORT+1); + outb(0x07, IOPORT); + outb(devno, IOPORT+1); } /* write to the control register */ static inline void write_io_cr(unsigned char reg, unsigned char data) { - outb(reg, IOPORT); - outb(data, IOPORT+1); + outb(reg, IOPORT); + outb(data, IOPORT+1); } /* read from the control register */ static inline char read_io_cr(unsigned char reg) { - outb(reg, IOPORT); - return inb(IOPORT+1); + outb(reg, IOPORT); + return inb(IOPORT+1); } /* -- Medium level functions ------------------------------------*/ static inline void gpio_bit12(unsigned char reg) { - // -- General Purpose I/O Bit 1.2 -- - // Bit 0, In/Out: 0 = Output, 1 = Input - // Bit 1, Polarity: 0 = No Invert, 1 = Invert - // Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable - // Bit 3/4, Function select: 00 = GPI/O, 01 = WDT, 10 = P17, - // 11 = Either Edge Triggered Intr. 2 - // Bit 5/6 (Reserved) - // Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain - write_io_cr(0xE2, reg); + /* -- General Purpose I/O Bit 1.2 -- + * Bit 0, In/Out: 0 = Output, 1 = Input + * Bit 1, Polarity: 0 = No Invert, 1 = Invert + * Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable + * Bit 3/4, Function select: 00 = GPI/O, 01 = WDT, 10 = P17, + * 11 = Either Edge Triggered Intr. 2 + * Bit 5/6 (Reserved) + * Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain + */ + write_io_cr(0xE2, reg); } static inline void gpio_bit13(unsigned char reg) { - // -- General Purpose I/O Bit 1.3 -- - // Bit 0, In/Out: 0 = Output, 1 = Input - // Bit 1, Polarity: 0 = No Invert, 1 = Invert - // Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable - // Bit 3, Function select: 0 = GPI/O, 1 = LED - // Bit 4-6 (Reserved) - // Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain - write_io_cr(0xE3, reg); + /* -- General Purpose I/O Bit 1.3 -- + * Bit 0, In/Out: 0 = Output, 1 = Input + * Bit 1, Polarity: 0 = No Invert, 1 = Invert + * Bit 2, Group Enable Intr.: 0 = Disable, 1 = Enable + * Bit 3, Function select: 0 = GPI/O, 1 = LED + * Bit 4-6 (Reserved) + * Bit 7, Output Type: 0 = Push Pull Bit, 1 = Open Drain + */ + write_io_cr(0xE3, reg); } static inline void wdt_timer_units(unsigned char new_units) { - // -- Watchdog timer units -- - // Bit 0-6 (Reserved) - // Bit 7, WDT Time-out Value Units Select - // (0 = Minutes, 1 = Seconds) - write_io_cr(0xF1, new_units); + /* -- Watchdog timer units -- + * Bit 0-6 (Reserved) + * Bit 7, WDT Time-out Value Units Select + * (0 = Minutes, 1 = Seconds) + */ + write_io_cr(0xF1, new_units); } static inline void wdt_timeout_value(unsigned char new_timeout) { - // -- Watchdog Timer Time-out Value -- - // Bit 0-7 Binary coded units (0=Disabled, 1..255) - write_io_cr(0xF2, new_timeout); + /* -- Watchdog Timer Time-out Value -- + * Bit 0-7 Binary coded units (0=Disabled, 1..255) + */ + write_io_cr(0xF2, new_timeout); } static inline void wdt_timer_conf(unsigned char conf) { - // -- Watchdog timer configuration -- - // Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon Gameport I/O - // Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. - // Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr. - // Bit 3 Reset the timer - // (Wrong in SMsC documentation? Given as: PowerLED Timout Enabled) - // Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled, - // 0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15) - write_io_cr(0xF3, conf); + /* -- Watchdog timer configuration -- + * Bit 0 Joystick enable: 0* = No Reset, 1 = Reset WDT upon + * Gameport I/O + * Bit 1 Keyboard enable: 0* = No Reset, 1 = Reset WDT upon KBD Intr. + * Bit 2 Mouse enable: 0* = No Reset, 1 = Reset WDT upon Mouse Intr + * Bit 3 Reset the timer + * (Wrong in SMsC documentation? Given as: PowerLED Timout + * Enabled) + * Bit 4-7 WDT Interrupt Mapping: (0000* = Disabled, + * 0001=IRQ1, 0010=(Invalid), 0011=IRQ3 to 1111=IRQ15) + */ + write_io_cr(0xF3, conf); } static inline void wdt_timer_ctrl(unsigned char reg) { - // -- Watchdog timer control -- - // Bit 0 Status Bit: 0 = Timer counting, 1 = Timeout occured - // Bit 1 Power LED Toggle: 0 = Disable Toggle, 1 = Toggle at 1 Hz - // Bit 2 Force Timeout: 1 = Forces WD timeout event (self-cleaning) - // Bit 3 P20 Force Timeout enabled: - // 0 = P20 activity does not generate the WD timeout event - // 1 = P20 Allows rising edge of P20, from the keyboard - // controller, to force the WD timeout event. - // Bit 4 (Reserved) - // -- Soft power management -- - // Bit 5 Stop Counter: 1 = Stop software power down counter - // set via register 0xB8, (self-cleaning) - // (Upon read: 0 = Counter running, 1 = Counter stopped) - // Bit 6 Restart Counter: 1 = Restart software power down counter - // set via register 0xB8, (self-cleaning) - // Bit 7 SPOFF: 1 = Force software power down (self-cleaning) - - write_io_cr(0xF4, reg); + /* -- Watchdog timer control -- + * Bit 0 Status Bit: 0 = Timer counting, 1 = Timeout occured + * Bit 1 Power LED Toggle: 0 = Disable Toggle, 1 = Toggle at 1 Hz + * Bit 2 Force Timeout: 1 = Forces WD timeout event (self-cleaning) + * Bit 3 P20 Force Timeout enabled: + * 0 = P20 activity does not generate the WD timeout event + * 1 = P20 Allows rising edge of P20, from the keyboard + * controller, to force the WD timeout event. + * Bit 4 (Reserved) + * -- Soft power management -- + * Bit 5 Stop Counter: 1 = Stop software power down counter + * set via register 0xB8, (self-cleaning) + * (Upon read: 0 = Counter running, 1 = Counter stopped) + * Bit 6 Restart Counter: 1 = Restart software power down counter + * set via register 0xB8, (self-cleaning) + * Bit 7 SPOFF: 1 = Force software power down (self-cleaning) + */ + write_io_cr(0xF4, reg); } /* -- Higher level functions ------------------------------------*/ @@ -209,33 +216,34 @@ static inline void wdt_timer_ctrl(unsigned char reg) static void wb_smsc_wdt_initialize(void) { - unsigned char old; + unsigned char old; spin_lock(&io_lock); - open_io_config(); - select_io_device(IODEV_NO); + open_io_config(); + select_io_device(IODEV_NO); - // enable the watchdog - gpio_bit13(0x08); // Select pin 80 = LED not GPIO - gpio_bit12(0x0A); // Set pin 79 = WDT not GPIO/Output/Polarity=Invert + /* enable the watchdog */ + gpio_bit13(0x08); /* Select pin 80 = LED not GPIO */ + gpio_bit12(0x0A); /* Set pin 79 = WDT not + GPIO/Output/Polarity=Invert */ + /* disable the timeout */ + wdt_timeout_value(0); - // disable the timeout - wdt_timeout_value(0); + /* reset control register */ + wdt_timer_ctrl(0x00); - // reset control register - wdt_timer_ctrl(0x00); - - // reset configuration register + /* reset configuration register */ wdt_timer_conf(0x00); - // read old (timer units) register - old = read_io_cr(0xF1) & 0x7F; - if (unit == UNIT_SECOND) old |= 0x80; // set to seconds + /* read old (timer units) register */ + old = read_io_cr(0xF1) & 0x7F; + if (unit == UNIT_SECOND) + old |= 0x80; /* set to seconds */ - // set the watchdog timer units - wdt_timer_units(old); + /* set the watchdog timer units */ + wdt_timer_units(old); - close_io_config(); + close_io_config(); spin_unlock(&io_lock); } @@ -244,23 +252,23 @@ static void wb_smsc_wdt_initialize(void) static void wb_smsc_wdt_shutdown(void) { spin_lock(&io_lock); - open_io_config(); - select_io_device(IODEV_NO); + open_io_config(); + select_io_device(IODEV_NO); - // disable the watchdog - gpio_bit13(0x09); - gpio_bit12(0x09); + /* disable the watchdog */ + gpio_bit13(0x09); + gpio_bit12(0x09); - // reset watchdog config register + /* reset watchdog config register */ wdt_timer_conf(0x00); - // reset watchdog control register - wdt_timer_ctrl(0x00); + /* reset watchdog control register */ + wdt_timer_ctrl(0x00); - // disable timeout - wdt_timeout_value(0x00); + /* disable timeout */ + wdt_timeout_value(0x00); - close_io_config(); + close_io_config(); spin_unlock(&io_lock); } @@ -269,16 +277,16 @@ static void wb_smsc_wdt_shutdown(void) static void wb_smsc_wdt_set_timeout(unsigned char new_timeout) { spin_lock(&io_lock); - open_io_config(); - select_io_device(IODEV_NO); + open_io_config(); + select_io_device(IODEV_NO); - // set Power LED to blink, if we enable the timeout - wdt_timer_ctrl((new_timeout == 0) ? 0x00 : 0x02); + /* set Power LED to blink, if we enable the timeout */ + wdt_timer_ctrl((new_timeout == 0) ? 0x00 : 0x02); - // set timeout value - wdt_timeout_value(new_timeout); + /* set timeout value */ + wdt_timeout_value(new_timeout); - close_io_config(); + close_io_config(); spin_unlock(&io_lock); } @@ -286,32 +294,32 @@ static void wb_smsc_wdt_set_timeout(unsigned char new_timeout) static unsigned char wb_smsc_wdt_get_timeout(void) { - unsigned char set_timeout; + unsigned char set_timeout; spin_lock(&io_lock); - open_io_config(); - select_io_device(IODEV_NO); - set_timeout = read_io_cr(0xF2); - close_io_config(); + open_io_config(); + select_io_device(IODEV_NO); + set_timeout = read_io_cr(0xF2); + close_io_config(); spin_unlock(&io_lock); - return set_timeout; + return set_timeout; } /* disable watchdog */ static void wb_smsc_wdt_disable(void) { - // set the timeout to 0 to disable the watchdog - wb_smsc_wdt_set_timeout(0); + /* set the timeout to 0 to disable the watchdog */ + wb_smsc_wdt_set_timeout(0); } /* enable watchdog by setting the current timeout */ static void wb_smsc_wdt_enable(void) { - // set the current timeout... - wb_smsc_wdt_set_timeout(timeout); + /* set the current timeout... */ + wb_smsc_wdt_set_timeout(timeout); } /* reset the timer */ @@ -319,14 +327,14 @@ static void wb_smsc_wdt_enable(void) static void wb_smsc_wdt_reset_timer(void) { spin_lock(&io_lock); - open_io_config(); - select_io_device(IODEV_NO); + open_io_config(); + select_io_device(IODEV_NO); - // reset the timer + /* reset the timer */ wdt_timeout_value(timeout); wdt_timer_conf(0x08); - close_io_config(); + close_io_config(); spin_unlock(&io_lock); } @@ -355,7 +363,9 @@ static int wb_smsc_wdt_open(struct inode *inode, struct file *file) /* Reload and activate timer */ wb_smsc_wdt_enable(); - printk(KERN_INFO MODNAME "Watchdog enabled. Timeout set to %d %s.\n", timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); + printk(KERN_INFO MODNAME + "Watchdog enabled. Timeout set to %d %s.\n", + timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); return nonseekable_open(inode, file); } @@ -367,10 +377,12 @@ static int wb_smsc_wdt_release(struct inode *inode, struct file *file) /* Shut off the timer. */ if (expect_close == 42) { - wb_smsc_wdt_disable(); - printk(KERN_INFO MODNAME "Watchdog disabled, sleeping again...\n"); + wb_smsc_wdt_disable(); + printk(KERN_INFO MODNAME + "Watchdog disabled, sleeping again...\n"); } else { - printk(KERN_CRIT MODNAME "Unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT MODNAME + "Unexpected close, not stopping watchdog!\n"); wb_smsc_wdt_reset_timer(); } @@ -392,7 +404,8 @@ static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data, /* reset expect flag */ expect_close = 0; - /* scan to see whether or not we got the magic character */ + /* scan to see whether or not we got the + magic character */ for (i = 0; i != len; i++) { char c; if (get_user(c, data+i)) @@ -410,8 +423,8 @@ static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data, /* ioctl => control interface */ -static int wb_smsc_wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long wb_smsc_wdt_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) { int new_timeout; @@ -420,9 +433,9 @@ static int wb_smsc_wdt_ioctl(struct inode *inode, struct file *file, int __user *i; } uarg; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | - WDIOF_SETTIMEOUT | + WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 0, .identity = "SMsC 37B787 Watchdog" @@ -431,78 +444,62 @@ static int wb_smsc_wdt_ioctl(struct inode *inode, struct file *file, uarg.i = (int __user *)arg; switch (cmd) { - default: - return -ENOTTY; - - case WDIOC_GETSUPPORT: - return copy_to_user(uarg.ident, &ident, - sizeof(ident)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - return put_user(wb_smsc_wdt_status(), uarg.i); - - case WDIOC_GETBOOTSTATUS: - return put_user(0, uarg.i); - - case WDIOC_KEEPALIVE: - wb_smsc_wdt_reset_timer(); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, uarg.i)) - return -EFAULT; - - // the API states this is given in secs - if (unit == UNIT_MINUTE) - new_timeout /= 60; - - if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) - return -EINVAL; - - timeout = new_timeout; - wb_smsc_wdt_set_timeout(timeout); - - // fall through and return the new timeout... - - case WDIOC_GETTIMEOUT: - - new_timeout = timeout; - - if (unit == UNIT_MINUTE) + case WDIOC_GETSUPPORT: + return copy_to_user(uarg.ident, &ident, sizeof(ident)) + ? -EFAULT : 0; + case WDIOC_GETSTATUS: + return put_user(wb_smsc_wdt_status(), uarg.i); + case WDIOC_GETBOOTSTATUS: + return put_user(0, uarg.i); + case WDIOC_KEEPALIVE: + wb_smsc_wdt_reset_timer(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, uarg.i)) + return -EFAULT; + /* the API states this is given in secs */ + if (unit == UNIT_MINUTE) + new_timeout /= 60; + if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) + return -EINVAL; + timeout = new_timeout; + wb_smsc_wdt_set_timeout(timeout); + /* fall through and return the new timeout... */ + case WDIOC_GETTIMEOUT: + new_timeout = timeout; + if (unit == UNIT_MINUTE) new_timeout *= 60; + return put_user(new_timeout, uarg.i); + case WDIOC_SETOPTIONS: + { + int options, retval = -EINVAL; - return put_user(new_timeout, uarg.i); - - case WDIOC_SETOPTIONS: - { - int options, retval = -EINVAL; - - if (get_user(options, uarg.i)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - wb_smsc_wdt_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - wb_smsc_wdt_enable(); - retval = 0; - } + if (get_user(options, uarg.i)) + return -EFAULT; - return retval; + if (options & WDIOS_DISABLECARD) { + wb_smsc_wdt_disable(); + retval = 0; } + if (options & WDIOS_ENABLECARD) { + wb_smsc_wdt_enable(); + retval = 0; + } + return retval; + } + default: + return -ENOTTY; } } /* -- Notifier funtions -----------------------------------------*/ -static int wb_smsc_wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) +static int wb_smsc_wdt_notify_sys(struct notifier_block *this, + unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) - { - // set timeout to 0, to avoid possible race-condition - timeout = 0; + if (code == SYS_DOWN || code == SYS_HALT) { + /* set timeout to 0, to avoid possible race-condition */ + timeout = 0; wb_smsc_wdt_disable(); } return NOTIFY_DONE; @@ -510,23 +507,20 @@ static int wb_smsc_wdt_notify_sys(struct notifier_block *this, unsigned long cod /* -- Module's structures ---------------------------------------*/ -static const struct file_operations wb_smsc_wdt_fops = -{ - .owner = THIS_MODULE, +static const struct file_operations wb_smsc_wdt_fops = { + .owner = THIS_MODULE, .llseek = no_llseek, .write = wb_smsc_wdt_write, - .ioctl = wb_smsc_wdt_ioctl, + .unlocked_ioctl = wb_smsc_wdt_ioctl, .open = wb_smsc_wdt_open, .release = wb_smsc_wdt_release, }; -static struct notifier_block wb_smsc_wdt_notifier = -{ +static struct notifier_block wb_smsc_wdt_notifier = { .notifier_call = wb_smsc_wdt_notify_sys, }; -static struct miscdevice wb_smsc_wdt_miscdev = -{ +static struct miscdevice wb_smsc_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &wb_smsc_wdt_fops, @@ -540,39 +534,44 @@ static int __init wb_smsc_wdt_init(void) { int ret; - printk("SMsC 37B787 watchdog component driver " VERSION " initialising...\n"); + printk(KERN_INFO "SMsC 37B787 watchdog component driver " + VERSION " initialising...\n"); if (!request_region(IOPORT, IOPORT_SIZE, "SMsC 37B787 watchdog")) { - printk(KERN_ERR MODNAME "Unable to register IO port %#x\n", IOPORT); + printk(KERN_ERR MODNAME "Unable to register IO port %#x\n", + IOPORT); ret = -EBUSY; goto out_pnp; } - // set new maximum, if it's too big - if (timeout > MAX_TIMEOUT) - timeout = MAX_TIMEOUT; + /* set new maximum, if it's too big */ + if (timeout > MAX_TIMEOUT) + timeout = MAX_TIMEOUT; - // init the watchdog timer - wb_smsc_wdt_initialize(); + /* init the watchdog timer */ + wb_smsc_wdt_initialize(); ret = register_reboot_notifier(&wb_smsc_wdt_notifier); if (ret) { - printk(KERN_ERR MODNAME "Unable to register reboot notifier err = %d\n", ret); + printk(KERN_ERR MODNAME + "Unable to register reboot notifier err = %d\n", ret); goto out_io; } ret = misc_register(&wb_smsc_wdt_miscdev); if (ret) { - printk(KERN_ERR MODNAME "Unable to register miscdev on minor %d\n", WATCHDOG_MINOR); + printk(KERN_ERR MODNAME + "Unable to register miscdev on minor %d\n", + WATCHDOG_MINOR); goto out_rbt; } - // output info - printk(KERN_INFO MODNAME "Timeout set to %d %s.\n", timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); - printk(KERN_INFO MODNAME "Watchdog initialized and sleeping (nowayout=%d)...\n", nowayout); - - // ret = 0 - + /* output info */ + printk(KERN_INFO MODNAME "Timeout set to %d %s.\n", + timeout, (unit == UNIT_SECOND) ? "second(s)" : "minute(s)"); + printk(KERN_INFO MODNAME + "Watchdog initialized and sleeping (nowayout=%d)...\n", + nowayout); out_clean: return ret; @@ -591,8 +590,7 @@ out_pnp: static void __exit wb_smsc_wdt_exit(void) { /* Stop the timer before we leave */ - if (!nowayout) - { + if (!nowayout) { wb_smsc_wdt_shutdown(); printk(KERN_INFO MODNAME "Watchdog disabled.\n"); } @@ -601,25 +599,29 @@ static void __exit wb_smsc_wdt_exit(void) unregister_reboot_notifier(&wb_smsc_wdt_notifier); release_region(IOPORT, IOPORT_SIZE); - printk("SMsC 37B787 watchdog component driver removed.\n"); + printk(KERN_INFO "SMsC 37B787 watchdog component driver removed.\n"); } module_init(wb_smsc_wdt_init); module_exit(wb_smsc_wdt_exit); MODULE_AUTHOR("Sven Anders "); -MODULE_DESCRIPTION("Driver for SMsC 37B787 watchdog component (Version " VERSION ")"); +MODULE_DESCRIPTION("Driver for SMsC 37B787 watchdog component (Version " + VERSION ")"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); #ifdef SMSC_SUPPORT_MINUTES module_param(unit, int, 0); -MODULE_PARM_DESC(unit, "set unit to use, 0=seconds or 1=minutes, default is 0"); +MODULE_PARM_DESC(unit, + "set unit to use, 0=seconds or 1=minutes, default is 0"); #endif module_param(timeout, int, 0); MODULE_PARM_DESC(timeout, "range is 1-255 units, default is 60"); module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -- cgit v1.2.3 From f92d3749d70265468e28643652c0e32c5a56cd2b Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:06 +0100 Subject: [WATCHDOG 47/57] softdog: clean up, coding style and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/softdog.c | 87 ++++++++++++++++++++++++---------------------- 1 file changed, 46 insertions(+), 41 deletions(-) diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c index 9c3694909243..bb3c75eed9df 100644 --- a/drivers/watchdog/softdog.c +++ b/drivers/watchdog/softdog.c @@ -47,19 +47,22 @@ #include #include #include - -#include +#include #define PFX "SoftDog: " #define TIMER_MARGIN 60 /* Default is 60 seconds */ static int soft_margin = TIMER_MARGIN; /* in seconds */ module_param(soft_margin, int, 0); -MODULE_PARM_DESC(soft_margin, "Watchdog soft_margin in seconds. (0 Date: Mon, 19 May 2008 14:09:12 +0100 Subject: [WATCHDOG 48/57] txx9: Fix locking, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/txx9wdt.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index 57cefef27ce3..b729cc447df3 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c @@ -45,27 +45,34 @@ static unsigned long txx9wdt_alive; static int expect_close; static struct txx9_tmr_reg __iomem *txx9wdt_reg; static struct clk *txx9_imclk; +static DECLARE_LOCK(txx9_lock); static void txx9wdt_ping(void) { + spin_lock(&txx9_lock); __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); + spin_unlock(&txx9_lock); } static void txx9wdt_start(void) { + spin_lock(&txx9_lock); __raw_writel(WD_TIMER_CLK * timeout, &txx9wdt_reg->cpra); __raw_writel(WD_TIMER_CCD, &txx9wdt_reg->ccdr); __raw_writel(0, &txx9wdt_reg->tisr); /* clear pending interrupt */ __raw_writel(TXx9_TMTCR_TCE | TXx9_TMTCR_CCDE | TXx9_TMTCR_TMODE_WDOG, &txx9wdt_reg->tcr); __raw_writel(TXx9_TMWTMR_TWIE | TXx9_TMWTMR_TWC, &txx9wdt_reg->wtmr); + spin_unlock(&txx9_lock); } static void txx9wdt_stop(void) { + spin_lock(&txx9_lock); __raw_writel(TXx9_TMWTMR_WDIS, &txx9wdt_reg->wtmr); __raw_writel(__raw_readl(&txx9wdt_reg->tcr) & ~TXx9_TMTCR_TCE, &txx9wdt_reg->tcr); + spin_unlock(&txx9_lock); } static int txx9wdt_open(struct inode *inode, struct file *file) @@ -120,13 +127,13 @@ static ssize_t txx9wdt_write(struct file *file, const char __user *data, return len; } -static int txx9wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long txx9wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_timeout; - static struct watchdog_info ident = { + static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, @@ -168,18 +175,18 @@ static int txx9wdt_notify_sys(struct notifier_block *this, unsigned long code, } static const struct file_operations txx9wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = txx9wdt_write, - .ioctl = txx9wdt_ioctl, - .open = txx9wdt_open, - .release = txx9wdt_release, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = txx9wdt_write, + .unlocked_ioctl = txx9wdt_ioctl, + .open = txx9wdt_open, + .release = txx9wdt_release, }; static struct miscdevice txx9wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &txx9wdt_fops, + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &txx9wdt_fops, }; static struct notifier_block txx9wdt_notifier = { -- cgit v1.2.3 From 46a3949ddc422882cc27c88d078838cd31885d78 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:18 +0100 Subject: [WATCHDOG 49/57] w83627hf: coding style, clean up and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/w83627hf_wdt.c | 175 +++++++++++++++++++--------------------- 1 file changed, 83 insertions(+), 92 deletions(-) diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index 386492821fc2..70c843f4201a 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -37,9 +37,9 @@ #include #include #include +#include +#include -#include -#include #include #define WATCHDOG_NAME "w83627hf/thf/hg WDT" @@ -57,22 +57,26 @@ MODULE_PARM_DESC(wdt_io, "w83627hf/thf WDT io port (default 0x2E)"); static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) "."); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) "."); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Kernel methods. */ #define WDT_EFER (wdt_io+0) /* Extended Function Enable Registers */ -#define WDT_EFIR (wdt_io+0) /* Extended Function Index Register (same as EFER) */ +#define WDT_EFIR (wdt_io+0) /* Extended Function Index Register + (same as EFER) */ #define WDT_EFDR (WDT_EFIR+1) /* Extended Function Data Register */ -static void -w83627hf_select_wd_register(void) +static void w83627hf_select_wd_register(void) { unsigned char c; outb_p(0x87, WDT_EFER); /* Enter extended function mode */ @@ -93,43 +97,45 @@ w83627hf_select_wd_register(void) outb_p(0x01, WDT_EFDR); /* set bit 0 to activate GPIO2 */ } -static void -w83627hf_unselect_wd_register(void) +static void w83627hf_unselect_wd_register(void) { outb_p(0xAA, WDT_EFER); /* Leave extended function mode */ } /* tyan motherboards seem to set F5 to 0x4C ? * So explicitly init to appropriate value. */ -static void -w83627hf_init(void) + +static void w83627hf_init(void) { unsigned char t; w83627hf_select_wd_register(); outb_p(0xF6, WDT_EFER); /* Select CRF6 */ - t=inb_p(WDT_EFDR); /* read CRF6 */ + t = inb_p(WDT_EFDR); /* read CRF6 */ if (t != 0) { - printk (KERN_INFO PFX "Watchdog already running. Resetting timeout to %d sec\n", timeout); + printk(KERN_INFO PFX + "Watchdog already running. Resetting timeout to %d sec\n", + timeout); outb_p(timeout, WDT_EFDR); /* Write back to CRF6 */ } outb_p(0xF5, WDT_EFER); /* Select CRF5 */ - t=inb_p(WDT_EFDR); /* read CRF5 */ - t&=~0x0C; /* set second mode & disable keyboard turning off watchdog */ + t = inb_p(WDT_EFDR); /* read CRF5 */ + t &= ~0x0C; /* set second mode & disable keyboard + turning off watchdog */ outb_p(t, WDT_EFDR); /* Write back to CRF5 */ outb_p(0xF7, WDT_EFER); /* Select CRF7 */ - t=inb_p(WDT_EFDR); /* read CRF7 */ - t&=~0xC0; /* disable keyboard & mouse turning off watchdog */ + t = inb_p(WDT_EFDR); /* read CRF7 */ + t &= ~0xC0; /* disable keyboard & mouse turning off + watchdog */ outb_p(t, WDT_EFDR); /* Write back to CRF7 */ w83627hf_unselect_wd_register(); } -static void -wdt_ctrl(int timeout) +static void wdt_ctrl(int timeout) { spin_lock(&io_lock); @@ -143,32 +149,28 @@ wdt_ctrl(int timeout) spin_unlock(&io_lock); } -static int -wdt_ping(void) +static int wdt_ping(void) { wdt_ctrl(timeout); return 0; } -static int -wdt_disable(void) +static int wdt_disable(void) { wdt_ctrl(0); return 0; } -static int -wdt_set_heartbeat(int t) +static int wdt_set_heartbeat(int t) { - if ((t < 1) || (t > 255)) + if (t < 1 || t > 255) return -EINVAL; - timeout = t; return 0; } -static ssize_t -wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t wdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -189,72 +191,61 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) return count; } -static int -wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_timeout; static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "W83627HF WDT", }; switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; - + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - + return put_user(0, p); case WDIOC_KEEPALIVE: - wdt_ping(); - break; - + wdt_ping(); + break; case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if (wdt_set_heartbeat(new_timeout)) - return -EINVAL; - wdt_ping(); - /* Fall */ - + if (get_user(new_timeout, p)) + return -EFAULT; + if (wdt_set_heartbeat(new_timeout)) + return -EINVAL; + wdt_ping(); + /* Fall */ case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - + return put_user(timeout, p); case WDIOC_SETOPTIONS: { - int options, retval = -EINVAL; - - if (get_user(options, p)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - wdt_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - wdt_ping(); - retval = 0; - } + int options, retval = -EINVAL; - return retval; + if (get_user(options, p)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + wdt_disable(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + wdt_ping(); + retval = 0; + } + return retval; } - default: - return -ENOTTY; + return -ENOTTY; } return 0; } -static int -wdt_open(struct inode *inode, struct file *file) +static int wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; @@ -266,13 +257,13 @@ wdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int -wdt_close(struct inode *inode, struct file *file) +static int wdt_close(struct inode *inode, struct file *file) { - if (expect_close == 42) { + if (expect_close == 42) wdt_disable(); - } else { - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); wdt_ping(); } expect_close = 0; @@ -284,8 +275,7 @@ wdt_close(struct inode *inode, struct file *file) * Notifier for system down */ -static int -wdt_notify_sys(struct notifier_block *this, unsigned long code, +static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) { @@ -303,7 +293,7 @@ static const struct file_operations wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdt_write, - .ioctl = wdt_ioctl, + .unlocked_ioctl = wdt_ioctl, .open = wdt_open, .release = wdt_close, }; @@ -323,8 +313,7 @@ static struct notifier_block wdt_notifier = { .notifier_call = wdt_notify_sys, }; -static int __init -wdt_init(void) +static int __init wdt_init(void) { int ret; @@ -332,12 +321,13 @@ wdt_init(void) if (wdt_set_heartbeat(timeout)) { wdt_set_heartbeat(WATCHDOG_TIMEOUT); - printk (KERN_INFO PFX "timeout value must be 1<=timeout<=255, using %d\n", - WATCHDOG_TIMEOUT); + printk(KERN_INFO PFX + "timeout value must be 1 <= timeout <= 255, using %d\n", + WATCHDOG_TIMEOUT); } if (!request_region(wdt_io, 1, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", + printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", wdt_io); ret = -EIO; goto out; @@ -347,20 +337,22 @@ wdt_init(void) ret = register_reboot_notifier(&wdt_notifier); if (ret != 0) { - printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - ret); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); goto unreg_regions; } ret = misc_register(&wdt_miscdev); if (ret != 0) { - printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto unreg_reboot; } - printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", - timeout, nowayout); + printk(KERN_INFO PFX + "initialized. timeout=%d sec (nowayout=%d)\n", + timeout, nowayout); out: return ret; @@ -371,12 +363,11 @@ unreg_regions: goto out; } -static void __exit -wdt_exit(void) +static void __exit wdt_exit(void) { misc_deregister(&wdt_miscdev); unregister_reboot_notifier(&wdt_notifier); - release_region(wdt_io,1); + release_region(wdt_io, 1); } module_init(wdt_init); -- cgit v1.2.3 From c1c8dd39f53e56d6a92aa6a2db9940d912d7ee4c Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:23 +0100 Subject: [WATCHDOG 50/57] w83697hf_wdt: cleanup, coding style and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/w83697hf_wdt.c | 148 ++++++++++++++++++++-------------------- 1 file changed, 73 insertions(+), 75 deletions(-) diff --git a/drivers/watchdog/w83697hf_wdt.c b/drivers/watchdog/w83697hf_wdt.c index 528b882420b6..06ddd38675bd 100644 --- a/drivers/watchdog/w83697hf_wdt.c +++ b/drivers/watchdog/w83697hf_wdt.c @@ -36,9 +36,9 @@ #include #include #include +#include +#include -#include -#include #include #define WATCHDOG_NAME "w83697hf/hg WDT" @@ -53,37 +53,43 @@ static DEFINE_SPINLOCK(io_lock); /* You must set this - there is no sane way to probe for this board. */ static int wdt_io = 0x2e; module_param(wdt_io, int, 0); -MODULE_PARM_DESC(wdt_io, "w83697hf/hg WDT io port (default 0x2e, 0 = autodetect)"); +MODULE_PARM_DESC(wdt_io, + "w83697hf/hg WDT io port (default 0x2e, 0 = autodetect)"); static int timeout = WATCHDOG_TIMEOUT; /* in seconds */ module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255 (default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. 1<= timeout <=255 (default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static int early_disable = WATCHDOG_EARLY_DISABLE; module_param(early_disable, int, 0); -MODULE_PARM_DESC(early_disable, "Watchdog gets disabled at boot time (default=" __MODULE_STRING(WATCHDOG_EARLY_DISABLE) ")"); +MODULE_PARM_DESC(early_disable, + "Watchdog gets disabled at boot time (default=" + __MODULE_STRING(WATCHDOG_EARLY_DISABLE) ")"); /* * Kernel methods. */ -#define W83697HF_EFER (wdt_io+0) /* Extended Function Enable Register */ -#define W83697HF_EFIR (wdt_io+0) /* Extended Function Index Register (same as EFER) */ -#define W83697HF_EFDR (wdt_io+1) /* Extended Function Data Register */ +#define W83697HF_EFER (wdt_io + 0) /* Extended Function Enable Register */ +#define W83697HF_EFIR (wdt_io + 0) /* Extended Function Index Register + (same as EFER) */ +#define W83697HF_EFDR (wdt_io + 1) /* Extended Function Data Register */ -static inline void -w83697hf_unlock(void) +static inline void w83697hf_unlock(void) { outb_p(0x87, W83697HF_EFER); /* Enter extended function mode */ outb_p(0x87, W83697HF_EFER); /* Again according to manual */ } -static inline void -w83697hf_lock(void) +static inline void w83697hf_lock(void) { outb_p(0xAA, W83697HF_EFER); /* Leave extended function mode */ } @@ -93,41 +99,36 @@ w83697hf_lock(void) * w83697hf_write_timeout() must be called with the device unlocked. */ -static unsigned char -w83697hf_get_reg(unsigned char reg) +static unsigned char w83697hf_get_reg(unsigned char reg) { outb_p(reg, W83697HF_EFIR); return inb_p(W83697HF_EFDR); } -static void -w83697hf_set_reg(unsigned char reg, unsigned char data) +static void w83697hf_set_reg(unsigned char reg, unsigned char data) { outb_p(reg, W83697HF_EFIR); outb_p(data, W83697HF_EFDR); } -static void -w83697hf_write_timeout(int timeout) +static void w83697hf_write_timeout(int timeout) { - w83697hf_set_reg(0xF4, timeout); /* Write Timeout counter to CRF4 */ + /* Write Timeout counter to CRF4 */ + w83697hf_set_reg(0xF4, timeout); } -static void -w83697hf_select_wdt(void) +static void w83697hf_select_wdt(void) { w83697hf_unlock(); w83697hf_set_reg(0x07, 0x08); /* Switch to logic device 8 (GPIO2) */ } -static inline void -w83697hf_deselect_wdt(void) +static inline void w83697hf_deselect_wdt(void) { w83697hf_lock(); } -static void -w83697hf_init(void) +static void w83697hf_init(void) { unsigned char bbuf; @@ -136,7 +137,9 @@ w83697hf_init(void) bbuf = w83697hf_get_reg(0x29); bbuf &= ~0x60; bbuf |= 0x20; - w83697hf_set_reg(0x29, bbuf); /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ + + /* Set pin 119 to WDTO# mode (= CR29, WDT0) */ + w83697hf_set_reg(0x29, bbuf); bbuf = w83697hf_get_reg(0xF3); bbuf &= ~0x04; @@ -145,8 +148,7 @@ w83697hf_init(void) w83697hf_deselect_wdt(); } -static void -wdt_ping(void) +static void wdt_ping(void) { spin_lock(&io_lock); w83697hf_select_wdt(); @@ -157,8 +159,7 @@ wdt_ping(void) spin_unlock(&io_lock); } -static void -wdt_enable(void) +static void wdt_enable(void) { spin_lock(&io_lock); w83697hf_select_wdt(); @@ -170,8 +171,7 @@ wdt_enable(void) spin_unlock(&io_lock); } -static void -wdt_disable(void) +static void wdt_disable(void) { spin_lock(&io_lock); w83697hf_select_wdt(); @@ -183,8 +183,7 @@ wdt_disable(void) spin_unlock(&io_lock); } -static unsigned char -wdt_running(void) +static unsigned char wdt_running(void) { unsigned char t; @@ -199,18 +198,17 @@ wdt_running(void) return t; } -static int -wdt_set_heartbeat(int t) +static int wdt_set_heartbeat(int t) { - if ((t < 1) || (t > 255)) + if (t < 1 || t > 255) return -EINVAL; timeout = t; return 0; } -static ssize_t -wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t wdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -231,15 +229,14 @@ wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) return count; } -static int -wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; int new_timeout; - static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "W83697HF WDT", }; @@ -295,8 +292,7 @@ wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, return 0; } -static int -wdt_open(struct inode *inode, struct file *file) +static int wdt_open(struct inode *inode, struct file *file) { if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; @@ -308,13 +304,13 @@ wdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int -wdt_close(struct inode *inode, struct file *file) +static int wdt_close(struct inode *inode, struct file *file) { - if (expect_close == 42) { + if (expect_close == 42) wdt_disable(); - } else { - printk (KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + else { + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); wdt_ping(); } expect_close = 0; @@ -326,8 +322,7 @@ wdt_close(struct inode *inode, struct file *file) * Notifier for system down */ -static int -wdt_notify_sys(struct notifier_block *this, unsigned long code, +static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { if (code == SYS_DOWN || code == SYS_HALT) { @@ -345,7 +340,7 @@ static const struct file_operations wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdt_write, - .ioctl = wdt_ioctl, + .unlocked_ioctl = wdt_ioctl, .open = wdt_open, .release = wdt_close, }; @@ -365,36 +360,38 @@ static struct notifier_block wdt_notifier = { .notifier_call = wdt_notify_sys, }; -static int -w83697hf_check_wdt(void) +static int w83697hf_check_wdt(void) { if (!request_region(wdt_io, 2, WATCHDOG_NAME)) { - printk (KERN_ERR PFX "I/O address 0x%x already in use\n", wdt_io); + printk(KERN_ERR PFX + "I/O address 0x%x already in use\n", wdt_io); return -EIO; } - printk (KERN_DEBUG PFX "Looking for watchdog at address 0x%x\n", wdt_io); + printk(KERN_DEBUG PFX + "Looking for watchdog at address 0x%x\n", wdt_io); w83697hf_unlock(); if (w83697hf_get_reg(0x20) == 0x60) { - printk (KERN_INFO PFX "watchdog found at address 0x%x\n", wdt_io); + printk(KERN_INFO PFX + "watchdog found at address 0x%x\n", wdt_io); w83697hf_lock(); return 0; } - w83697hf_lock(); /* Reprotect in case it was a compatible device */ + /* Reprotect in case it was a compatible device */ + w83697hf_lock(); - printk (KERN_INFO PFX "watchdog not found at address 0x%x\n", wdt_io); + printk(KERN_INFO PFX "watchdog not found at address 0x%x\n", wdt_io); release_region(wdt_io, 2); return -EIO; } static int w83697hf_ioports[] = { 0x2e, 0x4e, 0x00 }; -static int __init -wdt_init(void) +static int __init wdt_init(void) { int ret, i, found = 0; - printk (KERN_INFO PFX "WDT driver for W83697HF/HG initializing\n"); + printk(KERN_INFO PFX "WDT driver for W83697HF/HG initializing\n"); if (wdt_io == 0) { /* we will autodetect the W83697HF/HG watchdog */ @@ -409,7 +406,7 @@ wdt_init(void) } if (!found) { - printk (KERN_ERR PFX "No W83697HF/HG could be found\n"); + printk(KERN_ERR PFX "No W83697HF/HG could be found\n"); ret = -EIO; goto out; } @@ -423,25 +420,27 @@ wdt_init(void) if (wdt_set_heartbeat(timeout)) { wdt_set_heartbeat(WATCHDOG_TIMEOUT); - printk (KERN_INFO PFX "timeout value must be 1<=timeout<=255, using %d\n", - WATCHDOG_TIMEOUT); + printk(KERN_INFO PFX + "timeout value must be 1 <= timeout <= 255, using %d\n", + WATCHDOG_TIMEOUT); } ret = register_reboot_notifier(&wdt_notifier); if (ret != 0) { - printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - ret); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); goto unreg_regions; } ret = misc_register(&wdt_miscdev); if (ret != 0) { - printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto unreg_reboot; } - printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", + printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); out: @@ -453,8 +452,7 @@ unreg_regions: goto out; } -static void __exit -wdt_exit(void) +static void __exit wdt_exit(void) { misc_deregister(&wdt_miscdev); unregister_reboot_notifier(&wdt_notifier); -- cgit v1.2.3 From c1cfd1a2ffc5ee58f744b1ceb0887285df187668 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:29 +0100 Subject: [WATCHDOG 51/57] w83877f_wdt: clean up code, coding style, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/w83877f_wdt.c | 199 +++++++++++++++++++++-------------------- 1 file changed, 101 insertions(+), 98 deletions(-) diff --git a/drivers/watchdog/w83877f_wdt.c b/drivers/watchdog/w83877f_wdt.c index f510a3a595e6..75b546d7d8c2 100644 --- a/drivers/watchdog/w83877f_wdt.c +++ b/drivers/watchdog/w83877f_wdt.c @@ -23,13 +23,16 @@ * Added KERN_* tags to printks * add CONFIG_WATCHDOG_NOWAYOUT support * fix possible wdt_is_open race - * changed watchdog_info to correctly reflect what the driver offers - * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, WDIOC_SETTIMEOUT, + * changed watchdog_info to correctly reflect what + * the driver offers + * added WDIOC_GETSTATUS, WDIOC_GETBOOTSTATUS, + * WDIOC_SETTIMEOUT, * WDIOC_GETTIMEOUT, and WDIOC_SETOPTIONS ioctls * 09/8 - 2003 [wim@iguana.be] cleanup of trailing spaces * added extra printk's for startup problems * use module_param - * made timeout (the emulated heartbeat) a module_param + * made timeout (the emulated heartbeat) a + * module_param * made the keepalive ping an internal subroutine * * This WDT driver is different from most other Linux WDT @@ -51,8 +54,8 @@ #include #include #include -#include -#include +#include +#include #include #define OUR_NAME "w83877f_wdt" @@ -80,14 +83,19 @@ */ #define WATCHDOG_TIMEOUT 30 /* 30 sec default timeout */ -static int timeout = WATCHDOG_TIMEOUT; /* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +/* in seconds, will be multiplied by HZ to get seconds to wait for a ping */ +static int timeout = WATCHDOG_TIMEOUT; module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. (1<=timeout<=3600, default=" __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. (1<=timeout<=3600, default=" + __MODULE_STRING(WATCHDOG_TIMEOUT) ")"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static void wdt_timer_ping(unsigned long); static DEFINE_TIMER(timer, wdt_timer_ping, 0, 0); @@ -105,8 +113,7 @@ static void wdt_timer_ping(unsigned long data) /* If we got a heartbeat pulse within the WDT_US_INTERVAL * we agree to ping the WDT */ - if(time_before(jiffies, next_heartbeat)) - { + if (time_before(jiffies, next_heartbeat)) { /* Ping the WDT */ spin_lock(&wdt_spinlock); @@ -118,9 +125,9 @@ static void wdt_timer_ping(unsigned long data) spin_unlock(&wdt_spinlock); - } else { - printk(KERN_WARNING PFX "Heartbeat lost! Will not ping the watchdog\n"); - } + } else + printk(KERN_WARNING PFX + "Heartbeat lost! Will not ping the watchdog\n"); } /* @@ -181,22 +188,21 @@ static void wdt_keepalive(void) * /dev/watchdog handling */ -static ssize_t fop_write(struct file * file, const char __user * buf, size_t count, loff_t * ppos) +static ssize_t fop_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) - { - if (!nowayout) - { + if (count) { + if (!nowayout) { size_t ofs; - /* note: just in case someone wrote the magic character - * five months ago... */ + /* note: just in case someone wrote the magic + character five months ago... */ wdt_expect_close = 0; - /* scan to see whether or not we got the magic character */ - for(ofs = 0; ofs != count; ofs++) - { + /* scan to see whether or not we got the + magic character */ + for (ofs = 0; ofs != count; ofs++) { char c; if (get_user(c, buf + ofs)) return -EFAULT; @@ -211,10 +217,10 @@ static ssize_t fop_write(struct file * file, const char __user * buf, size_t cou return count; } -static int fop_open(struct inode * inode, struct file * file) +static int fop_open(struct inode *inode, struct file *file) { /* Just in case we're already talking to someone... */ - if(test_and_set_bit(0, &wdt_is_open)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; /* Good, fire up the show */ @@ -222,78 +228,78 @@ static int fop_open(struct inode * inode, struct file * file) return nonseekable_open(inode, file); } -static int fop_close(struct inode * inode, struct file * file) +static int fop_close(struct inode *inode, struct file *file) { - if(wdt_expect_close == 42) + if (wdt_expect_close == 42) wdt_turnoff(); else { del_timer(&timer); - printk(KERN_CRIT PFX "device file closed unexpectedly. Will not stop the WDT!\n"); + printk(KERN_CRIT PFX + "device file closed unexpectedly. Will not stop the WDT!\n"); } clear_bit(0, &wdt_is_open); wdt_expect_close = 0; return 0; } -static int fop_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident= - { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT + | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "W83877F", }; - switch(cmd) + switch (cmd) { + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETOPTIONS: { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; - - if(get_user(new_options, p)) - return -EFAULT; - - if(new_options & WDIOS_DISABLECARD) { - wdt_turnoff(); - retval = 0; - } + int new_options, retval = -EINVAL; - if(new_options & WDIOS_ENABLECARD) { - wdt_startup(); - retval = 0; - } + if (get_user(new_options, p)) + return -EFAULT; - return retval; + if (new_options & WDIOS_DISABLECARD) { + wdt_turnoff(); + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_timeout; - if(get_user(new_timeout, p)) - return -EFAULT; + if (new_options & WDIOS_ENABLECARD) { + wdt_startup(); + retval = 0; + } - if(new_timeout < 1 || new_timeout > 3600) /* arbitrary upper limit */ - return -EINVAL; + return retval; + } + case WDIOC_SETTIMEOUT: + { + int new_timeout; - timeout = new_timeout; - wdt_keepalive(); - /* Fall through */ - } - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); + if (get_user(new_timeout, p)) + return -EFAULT; + + /* arbitrary upper limit */ + if (new_timeout < 1 || new_timeout > 3600) + return -EINVAL; + + timeout = new_timeout; + wdt_keepalive(); + /* Fall through */ + } + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); } } @@ -303,7 +309,7 @@ static const struct file_operations wdt_fops = { .write = fop_write, .open = fop_open, .release = fop_close, - .ioctl = fop_ioctl, + .unlocked_ioctl = fop_ioctl, }; static struct miscdevice wdt_miscdev = { @@ -319,7 +325,7 @@ static struct miscdevice wdt_miscdev = { static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt_turnoff(); return NOTIFY_DONE; } @@ -329,8 +335,7 @@ static int wdt_notify_sys(struct notifier_block *this, unsigned long code, * turn the timebomb registers off. */ -static struct notifier_block wdt_notifier= -{ +static struct notifier_block wdt_notifier = { .notifier_call = wdt_notify_sys, }; @@ -342,31 +347,29 @@ static void __exit w83877f_wdt_unload(void) misc_deregister(&wdt_miscdev); unregister_reboot_notifier(&wdt_notifier); - release_region(WDT_PING,1); - release_region(ENABLE_W83877F_PORT,2); + release_region(WDT_PING, 1); + release_region(ENABLE_W83877F_PORT, 2); } static int __init w83877f_wdt_init(void) { int rc = -EBUSY; - if(timeout < 1 || timeout > 3600) /* arbitrary upper limit */ - { + if (timeout < 1 || timeout > 3600) { /* arbitrary upper limit */ timeout = WATCHDOG_TIMEOUT; - printk(KERN_INFO PFX "timeout value must be 1<=x<=3600, using %d\n", - timeout); + printk(KERN_INFO PFX + "timeout value must be 1 <= x <= 3600, using %d\n", + timeout); } - if (!request_region(ENABLE_W83877F_PORT, 2, "W83877F WDT")) - { + if (!request_region(ENABLE_W83877F_PORT, 2, "W83877F WDT")) { printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", ENABLE_W83877F_PORT); rc = -EIO; goto err_out; } - if (!request_region(WDT_PING, 1, "W8387FF WDT")) - { + if (!request_region(WDT_PING, 1, "W8387FF WDT")) { printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", WDT_PING); rc = -EIO; @@ -374,22 +377,22 @@ static int __init w83877f_wdt_init(void) } rc = register_reboot_notifier(&wdt_notifier); - if (rc) - { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", rc); goto err_out_region2; } rc = misc_register(&wdt_miscdev); - if (rc) - { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - wdt_miscdev.minor, rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + wdt_miscdev.minor, rc); goto err_out_reboot; } - printk(KERN_INFO PFX "WDT driver for W83877F initialised. timeout=%d sec (nowayout=%d)\n", + printk(KERN_INFO PFX + "WDT driver for W83877F initialised. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); return 0; @@ -397,9 +400,9 @@ static int __init w83877f_wdt_init(void) err_out_reboot: unregister_reboot_notifier(&wdt_notifier); err_out_region2: - release_region(WDT_PING,1); + release_region(WDT_PING, 1); err_out_region1: - release_region(ENABLE_W83877F_PORT,2); + release_region(ENABLE_W83877F_PORT, 2); err_out: return rc; } -- cgit v1.2.3 From 84af401af831567967250dec9c15680bceede5e4 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:34 +0100 Subject: [WATCHDOG 52/57] w83977f_wdt: clean up, coding style and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/w83977f_wdt.c | 225 ++++++++++++++++++++--------------------- 1 file changed, 111 insertions(+), 114 deletions(-) diff --git a/drivers/watchdog/w83977f_wdt.c b/drivers/watchdog/w83977f_wdt.c index b209bcd7f789..6860a13f5bb9 100644 --- a/drivers/watchdog/w83977f_wdt.c +++ b/drivers/watchdog/w83977f_wdt.c @@ -26,10 +26,10 @@ #include #include #include +#include +#include -#include #include -#include #define WATCHDOG_VERSION "1.00" #define WATCHDOG_NAME "W83977F WDT" @@ -53,13 +53,17 @@ static char expect_close; static DEFINE_SPINLOCK(spinlock); module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout,"Watchdog timeout in seconds (15..7635), default=" __MODULE_STRING(DEFAULT_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds (15..7635), default=" + __MODULE_STRING(DEFAULT_TIMEOUT) ")"); module_param(testmode, int, 0); -MODULE_PARM_DESC(testmode,"Watchdog testmode (1 = no reboot), default=0"); +MODULE_PARM_DESC(testmode, "Watchdog testmode (1 = no reboot), default=0"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Start the watchdog @@ -72,8 +76,8 @@ static int wdt_start(void) spin_lock_irqsave(&spinlock, flags); /* Unlock the SuperIO chip */ - outb_p(UNLOCK_DATA,IO_INDEX_PORT); - outb_p(UNLOCK_DATA,IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); /* * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. @@ -81,50 +85,49 @@ static int wdt_start(void) * F3 is set to enable watchdog LED blink at timeout. * F4 is used to just clear the TIMEOUT'ed state (bit 0). */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); - outb_p(0xF2,IO_INDEX_PORT); - outb_p(timeoutW,IO_DATA_PORT); - outb_p(0xF3,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); - outb_p(0xF4,IO_INDEX_PORT); - outb_p(0x00,IO_DATA_PORT); + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); + outb_p(0xF2, IO_INDEX_PORT); + outb_p(timeoutW, IO_DATA_PORT); + outb_p(0xF3, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); + outb_p(0xF4, IO_INDEX_PORT); + outb_p(0x00, IO_DATA_PORT); /* Set device Aux2 active */ - outb_p(0x30,IO_INDEX_PORT); - outb_p(0x01,IO_DATA_PORT); + outb_p(0x30, IO_INDEX_PORT); + outb_p(0x01, IO_DATA_PORT); - /* + /* * Select device Aux1 (dev=7) to set GP16 as the watchdog output * (in reg E6) and GP13 as the watchdog LED output (in reg E3). * Map GP16 at pin 119. * In test mode watch the bit 0 on F4 to indicate "triggered" or * check watchdog LED on SBC. */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x07,IO_DATA_PORT); - if (!testmode) - { + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x07, IO_DATA_PORT); + if (!testmode) { unsigned pin_map; - outb_p(0xE6,IO_INDEX_PORT); - outb_p(0x0A,IO_DATA_PORT); - outb_p(0x2C,IO_INDEX_PORT); + outb_p(0xE6, IO_INDEX_PORT); + outb_p(0x0A, IO_DATA_PORT); + outb_p(0x2C, IO_INDEX_PORT); pin_map = inb_p(IO_DATA_PORT); pin_map |= 0x10; pin_map &= ~(0x20); - outb_p(0x2C,IO_INDEX_PORT); - outb_p(pin_map,IO_DATA_PORT); + outb_p(0x2C, IO_INDEX_PORT); + outb_p(pin_map, IO_DATA_PORT); } - outb_p(0xE3,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); + outb_p(0xE3, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); /* Set device Aux1 active */ - outb_p(0x30,IO_INDEX_PORT); - outb_p(0x01,IO_DATA_PORT); + outb_p(0x30, IO_INDEX_PORT); + outb_p(0x01, IO_DATA_PORT); /* Lock the SuperIO chip */ - outb_p(LOCK_DATA,IO_INDEX_PORT); + outb_p(LOCK_DATA, IO_INDEX_PORT); spin_unlock_irqrestore(&spinlock, flags); @@ -144,42 +147,41 @@ static int wdt_stop(void) spin_lock_irqsave(&spinlock, flags); /* Unlock the SuperIO chip */ - outb_p(UNLOCK_DATA,IO_INDEX_PORT); - outb_p(UNLOCK_DATA,IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); - /* + /* * Select device Aux2 (device=8) to set watchdog regs F2, F3 and F4. * F2 is reset to its default value (watchdog timer disabled). * F3 is reset to its default state. * F4 clears the TIMEOUT'ed state (bit 0) - back to default. */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); - outb_p(0xF2,IO_INDEX_PORT); - outb_p(0xFF,IO_DATA_PORT); - outb_p(0xF3,IO_INDEX_PORT); - outb_p(0x00,IO_DATA_PORT); - outb_p(0xF4,IO_INDEX_PORT); - outb_p(0x00,IO_DATA_PORT); - outb_p(0xF2,IO_INDEX_PORT); - outb_p(0x00,IO_DATA_PORT); + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); + outb_p(0xF2, IO_INDEX_PORT); + outb_p(0xFF, IO_DATA_PORT); + outb_p(0xF3, IO_INDEX_PORT); + outb_p(0x00, IO_DATA_PORT); + outb_p(0xF4, IO_INDEX_PORT); + outb_p(0x00, IO_DATA_PORT); + outb_p(0xF2, IO_INDEX_PORT); + outb_p(0x00, IO_DATA_PORT); /* - * Select device Aux1 (dev=7) to set GP16 (in reg E6) and + * Select device Aux1 (dev=7) to set GP16 (in reg E6) and * Gp13 (in reg E3) as inputs. */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x07,IO_DATA_PORT); - if (!testmode) - { - outb_p(0xE6,IO_INDEX_PORT); - outb_p(0x01,IO_DATA_PORT); + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x07, IO_DATA_PORT); + if (!testmode) { + outb_p(0xE6, IO_INDEX_PORT); + outb_p(0x01, IO_DATA_PORT); } - outb_p(0xE3,IO_INDEX_PORT); - outb_p(0x01,IO_DATA_PORT); + outb_p(0xE3, IO_INDEX_PORT); + outb_p(0x01, IO_DATA_PORT); /* Lock the SuperIO chip */ - outb_p(LOCK_DATA,IO_INDEX_PORT); + outb_p(LOCK_DATA, IO_INDEX_PORT); spin_unlock_irqrestore(&spinlock, flags); @@ -200,17 +202,17 @@ static int wdt_keepalive(void) spin_lock_irqsave(&spinlock, flags); /* Unlock the SuperIO chip */ - outb_p(UNLOCK_DATA,IO_INDEX_PORT); - outb_p(UNLOCK_DATA,IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); /* Select device Aux2 (device=8) to kick watchdog reg F2 */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); - outb_p(0xF2,IO_INDEX_PORT); - outb_p(timeoutW,IO_DATA_PORT); + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); + outb_p(0xF2, IO_INDEX_PORT); + outb_p(timeoutW, IO_DATA_PORT); /* Lock the SuperIO chip */ - outb_p(LOCK_DATA,IO_INDEX_PORT); + outb_p(LOCK_DATA, IO_INDEX_PORT); spin_unlock_irqrestore(&spinlock, flags); @@ -227,7 +229,7 @@ static int wdt_set_timeout(int t) /* * Convert seconds to watchdog counter time units, rounding up. - * On PCM-5335 watchdog units are 30 seconds/step with 15 sec startup + * On PCM-5335 watchdog units are 30 seconds/step with 15 sec startup * value. This information is supplied in the PCM-5335 manual and was * checked by me on a real board. This is a bit strange because W83977f * datasheet says counter unit is in minutes! @@ -241,7 +243,7 @@ static int wdt_set_timeout(int t) return -EINVAL; /* - * timeout is the timeout in seconds, + * timeout is the timeout in seconds, * timeoutW is the timeout in watchdog counter units. */ timeoutW = tmrval; @@ -261,17 +263,17 @@ static int wdt_get_status(int *status) spin_lock_irqsave(&spinlock, flags); /* Unlock the SuperIO chip */ - outb_p(UNLOCK_DATA,IO_INDEX_PORT); - outb_p(UNLOCK_DATA,IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); + outb_p(UNLOCK_DATA, IO_INDEX_PORT); /* Select device Aux2 (device=8) to read watchdog reg F4 */ - outb_p(DEVICE_REGISTER,IO_INDEX_PORT); - outb_p(0x08,IO_DATA_PORT); - outb_p(0xF4,IO_INDEX_PORT); + outb_p(DEVICE_REGISTER, IO_INDEX_PORT); + outb_p(0x08, IO_DATA_PORT); + outb_p(0xF4, IO_INDEX_PORT); new_status = inb_p(IO_DATA_PORT); /* Lock the SuperIO chip */ - outb_p(LOCK_DATA,IO_INDEX_PORT); + outb_p(LOCK_DATA, IO_INDEX_PORT); spin_unlock_irqrestore(&spinlock, flags); @@ -290,7 +292,7 @@ static int wdt_get_status(int *status) static int wdt_open(struct inode *inode, struct file *file) { /* If the watchdog is alive we don't need to start it again */ - if( test_and_set_bit(0, &timer_alive) ) + if (test_and_set_bit(0, &timer_alive)) return -EBUSY; if (nowayout) @@ -306,13 +308,13 @@ static int wdt_release(struct inode *inode, struct file *file) * Shut off the timer. * Lock it in if it's a module and we set nowayout */ - if (expect_close == 42) - { + if (expect_close == 42) { wdt_stop(); clear_bit(0, &timer_alive); } else { wdt_keepalive(); - printk(KERN_CRIT PFX "unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT PFX + "unexpected close, not stopping watchdog!\n"); } expect_close = 0; return 0; @@ -333,24 +335,22 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ - if(count) - { - if (!nowayout) - { + if (count) { + if (!nowayout) { size_t ofs; - /* note: just in case someone wrote the magic character long ago */ + /* note: just in case someone wrote the + magic character long ago */ expect_close = 0; - /* scan to see whether or not we got the magic character */ - for(ofs = 0; ofs != count; ofs++) - { + /* scan to see whether or not we got the + magic character */ + for (ofs = 0; ofs != count; ofs++) { char c; if (get_user(c, buf + ofs)) return -EFAULT; - if (c == 'V') { + if (c == 'V') expect_close = 42; - } } } @@ -377,8 +377,7 @@ static struct watchdog_info ident = { .identity = WATCHDOG_NAME, }; -static int wdt_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { int status; int new_options, retval = -EINVAL; @@ -390,13 +389,13 @@ static int wdt_ioctl(struct inode *inode, struct file *file, uarg.i = (int __user *)arg; - switch(cmd) - { + switch (cmd) { default: return -ENOTTY; case WDIOC_GETSUPPORT: - return copy_to_user(uarg.ident, &ident, sizeof(ident)) ? -EFAULT : 0; + return copy_to_user(uarg.ident, &ident, + sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: wdt_get_status(&status); @@ -410,7 +409,7 @@ static int wdt_ioctl(struct inode *inode, struct file *file, return 0; case WDIOC_SETOPTIONS: - if (get_user (new_options, uarg.i)) + if (get_user(new_options, uarg.i)) return -EFAULT; if (new_options & WDIOS_DISABLECARD) { @@ -444,23 +443,21 @@ static int wdt_ioctl(struct inode *inode, struct file *file, static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt_stop(); return NOTIFY_DONE; } -static const struct file_operations wdt_fops= -{ +static const struct file_operations wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdt_write, - .ioctl = wdt_ioctl, + .unlocked_ioctl = wdt_ioctl, .open = wdt_open, .release = wdt_release, }; -static struct miscdevice wdt_miscdev= -{ +static struct miscdevice wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &wdt_fops, @@ -474,20 +471,20 @@ static int __init w83977f_wdt_init(void) { int rc; - printk(KERN_INFO PFX DRIVER_VERSION); + printk(KERN_INFO PFX DRIVER_VERSION); /* - * Check that the timeout value is within it's range ; + * Check that the timeout value is within it's range; * if not reset to the default */ if (wdt_set_timeout(timeout)) { wdt_set_timeout(DEFAULT_TIMEOUT); - printk(KERN_INFO PFX "timeout value must be 15<=timeout<=7635, using %d\n", - DEFAULT_TIMEOUT); + printk(KERN_INFO PFX + "timeout value must be 15 <= timeout <= 7635, using %d\n", + DEFAULT_TIMEOUT); } - if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) - { + if (!request_region(IO_INDEX_PORT, 2, WATCHDOG_NAME)) { printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", IO_INDEX_PORT); rc = -EIO; @@ -495,30 +492,30 @@ static int __init w83977f_wdt_init(void) } rc = register_reboot_notifier(&wdt_notifier); - if (rc) - { - printk(KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", rc); goto err_out_region; } rc = misc_register(&wdt_miscdev); - if (rc) - { - printk(KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - wdt_miscdev.minor, rc); + if (rc) { + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + wdt_miscdev.minor, rc); goto err_out_reboot; } - printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", - timeout, nowayout, testmode); + printk(KERN_INFO PFX + "initialized. timeout=%d sec (nowayout=%d testmode=%d)\n", + timeout, nowayout, testmode); return 0; err_out_reboot: unregister_reboot_notifier(&wdt_notifier); err_out_region: - release_region(IO_INDEX_PORT,2); + release_region(IO_INDEX_PORT, 2); err_out: return rc; } @@ -528,7 +525,7 @@ static void __exit w83977f_wdt_exit(void) wdt_stop(); misc_deregister(&wdt_miscdev); unregister_reboot_notifier(&wdt_notifier); - release_region(IO_INDEX_PORT,2); + release_region(IO_INDEX_PORT, 2); } module_init(w83977f_wdt_init); -- cgit v1.2.3 From 694b16b2bd23bbd13163762c29f1e7885fe0da41 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:40 +0100 Subject: [WATCHDOG 53/57] wafer5823wdt: Clean up, coding style, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wafer5823wdt.c | 80 +++++++++++++++++++++++------------------ 1 file changed, 46 insertions(+), 34 deletions(-) diff --git a/drivers/watchdog/wafer5823wdt.c b/drivers/watchdog/wafer5823wdt.c index 9e368091f799..886cbbcf3eed 100644 --- a/drivers/watchdog/wafer5823wdt.c +++ b/drivers/watchdog/wafer5823wdt.c @@ -36,8 +36,8 @@ #include #include #include -#include -#include +#include +#include #define WATCHDOG_NAME "Wafer 5823 WDT" #define PFX WATCHDOG_NAME ": " @@ -61,11 +61,15 @@ static int wdt_start = 0x443; static int timeout = WD_TIMO; /* in seconds */ module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds. 1<= timeout <=255, default=" __MODULE_STRING(WD_TIMO) "."); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in seconds. 1 <= timeout <= 255, default=" + __MODULE_STRING(WD_TIMO) "."); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); static void wafwdt_ping(void) { @@ -90,7 +94,8 @@ wafwdt_stop(void) inb_p(wdt_stop); } -static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t count, loff_t * ppos) +static ssize_t wafwdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { /* See if we got the magic character 'V' and reload the timer */ if (count) { @@ -100,7 +105,8 @@ static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t co /* In case it was set long ago */ expect_close = 0; - /* scan to see whether or not we got the magic character */ + /* scan to see whether or not we got the magic + character */ for (i = 0; i != count; i++) { char c; if (get_user(c, buf + i)) @@ -109,27 +115,29 @@ static ssize_t wafwdt_write(struct file *file, const char __user *buf, size_t co expect_close = 42; } } - /* Well, anyhow someone wrote to us, we should return that favour */ + /* Well, anyhow someone wrote to us, we should + return that favour */ wafwdt_ping(); } return count; } -static int wafwdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long wafwdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_timeout; void __user *argp = (void __user *)arg; int __user *p = argp; - static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, + static const struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = "Wafer 5823 WDT", }; switch (cmd) { case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof (ident))) + if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; break; @@ -194,10 +202,11 @@ static int wafwdt_open(struct inode *inode, struct file *file) static int wafwdt_close(struct inode *inode, struct file *file) { - if (expect_close == 42) { + if (expect_close == 42) wafwdt_stop(); - } else { - printk(KERN_CRIT PFX "WDT device closed unexpectedly. WDT will not stop!\n"); + else { + printk(KERN_CRIT PFX + "WDT device closed unexpectedly. WDT will not stop!\n"); wafwdt_ping(); } clear_bit(0, &wafwdt_is_open); @@ -209,12 +218,11 @@ wafwdt_close(struct inode *inode, struct file *file) * Notifier for system down */ -static int wafwdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) +static int wafwdt_notify_sys(struct notifier_block *this, unsigned long code, + void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Turn the WDT off */ + if (code == SYS_DOWN || code == SYS_HALT) wafwdt_stop(); - } return NOTIFY_DONE; } @@ -226,7 +234,7 @@ static const struct file_operations wafwdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wafwdt_write, - .ioctl = wafwdt_ioctl, + .unlocked_ioctl = wafwdt_ioctl, .open = wafwdt_open, .release = wafwdt_close, }; @@ -250,25 +258,28 @@ static int __init wafwdt_init(void) { int ret; - printk(KERN_INFO "WDT driver for Wafer 5823 single board computer initialising.\n"); + printk(KERN_INFO + "WDT driver for Wafer 5823 single board computer initialising.\n"); if (timeout < 1 || timeout > 255) { timeout = WD_TIMO; - printk (KERN_INFO PFX "timeout value must be 1<=x<=255, using %d\n", - timeout); + printk(KERN_INFO PFX + "timeout value must be 1 <= x <= 255, using %d\n", + timeout); } if (wdt_stop != wdt_start) { - if(!request_region(wdt_stop, 1, "Wafer 5823 WDT")) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", - wdt_stop); + if (!request_region(wdt_stop, 1, "Wafer 5823 WDT")) { + printk(KERN_ERR PFX + "I/O address 0x%04x already in use\n", + wdt_stop); ret = -EIO; goto error; } } - if(!request_region(wdt_start, 1, "Wafer 5823 WDT")) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", + if (!request_region(wdt_start, 1, "Wafer 5823 WDT")) { + printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", wdt_start); ret = -EIO; goto error2; @@ -276,19 +287,20 @@ static int __init wafwdt_init(void) ret = register_reboot_notifier(&wafwdt_notifier); if (ret != 0) { - printk (KERN_ERR PFX "cannot register reboot notifier (err=%d)\n", - ret); + printk(KERN_ERR PFX + "cannot register reboot notifier (err=%d)\n", ret); goto error3; } ret = misc_register(&wafwdt_miscdev); if (ret != 0) { - printk (KERN_ERR PFX "cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); + printk(KERN_ERR PFX + "cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto error4; } - printk (KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", + printk(KERN_INFO PFX "initialized. timeout=%d sec (nowayout=%d)\n", timeout, nowayout); return ret; @@ -307,7 +319,7 @@ static void __exit wafwdt_exit(void) { misc_deregister(&wafwdt_miscdev); unregister_reboot_notifier(&wafwdt_notifier); - if(wdt_stop != wdt_start) + if (wdt_stop != wdt_start) release_region(wdt_stop, 1); release_region(wdt_start, 1); } -- cgit v1.2.3 From dae67a2835149e6518a78c5cf37d6de715c214fc Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:45 +0100 Subject: [WATCHDOG 54/57] wdrtas: clean up, coding style, switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wdrtas.c | 103 ++++++++++++++++++---------------------------- 1 file changed, 41 insertions(+), 62 deletions(-) diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c index 1d64e277567d..20fd6715f25f 100644 --- a/drivers/watchdog/wdrtas.c +++ b/drivers/watchdog/wdrtas.c @@ -35,9 +35,9 @@ #include #include #include +#include #include -#include #define WDRTAS_MAGIC_CHAR 42 #define WDRTAS_SUPPORTED_MASK (WDIOF_SETTIMEOUT | \ @@ -56,7 +56,7 @@ static int wdrtas_nowayout = 0; #endif static atomic_t wdrtas_miscdev_open = ATOMIC_INIT(0); -static char wdrtas_expect_close = 0; +static char wdrtas_expect_close; static int wdrtas_interval; @@ -86,8 +86,8 @@ static char wdrtas_logbuffer[WDRTAS_LOGBUFFER_LEN]; * RTAS function set-indicator (surveillance). The unit of interval is * seconds. */ -static int -wdrtas_set_interval(int interval) + +static int wdrtas_set_interval(int interval) { long result; static int print_msg = 10; @@ -97,7 +97,7 @@ wdrtas_set_interval(int interval) result = rtas_call(wdrtas_token_set_indicator, 3, 1, NULL, WDRTAS_SURVEILLANCE_IND, 0, interval); - if ( (result < 0) && (print_msg) ) { + if (result < 0 && print_msg) { printk(KERN_ERR "wdrtas: setting the watchdog to %i " "timeout failed: %li\n", interval, result); print_msg--; @@ -116,16 +116,14 @@ wdrtas_set_interval(int interval) * as reported by the RTAS function ibm,get-system-parameter. The unit * of the return value is seconds. */ -static int -wdrtas_get_interval(int fallback_value) +static int wdrtas_get_interval(int fallback_value) { long result; char value[4]; result = rtas_call(wdrtas_token_get_sp, 3, 1, NULL, WDRTAS_SP_SPI, (void *)__pa(&value), 4); - if ( (value[0] != 0) || (value[1] != 2) || (value[3] != 0) || - (result < 0) ) { + if (value[0] != 0 || value[1] != 2 || value[3] != 0 || result < 0) { printk(KERN_WARNING "wdrtas: could not get sp_spi watchdog " "timeout (%li). Continuing\n", result); return fallback_value; @@ -141,8 +139,7 @@ wdrtas_get_interval(int fallback_value) * wdrtas_timer_start starts the watchdog by calling the RTAS function * set-interval (surveillance) */ -static void -wdrtas_timer_start(void) +static void wdrtas_timer_start(void) { wdrtas_set_interval(wdrtas_interval); } @@ -153,8 +150,7 @@ wdrtas_timer_start(void) * wdrtas_timer_stop stops the watchdog timer by calling the RTAS function * set-interval (surveillance) */ -static void -wdrtas_timer_stop(void) +static void wdrtas_timer_stop(void) { wdrtas_set_interval(0); } @@ -165,8 +161,7 @@ wdrtas_timer_stop(void) * wdrtas_log_scanned_event prints a message to the log buffer dumping * the results of the last event-scan call */ -static void -wdrtas_log_scanned_event(void) +static void wdrtas_log_scanned_event(void) { int i; @@ -175,13 +170,13 @@ wdrtas_log_scanned_event(void) "%02x %02x %02x %02x %02x %02x %02x %02x " "%02x %02x %02x %02x %02x %02x %02x %02x\n", (i / 16) + 1, (WDRTAS_LOGBUFFER_LEN / 16), - wdrtas_logbuffer[i + 0], wdrtas_logbuffer[i + 1], - wdrtas_logbuffer[i + 2], wdrtas_logbuffer[i + 3], - wdrtas_logbuffer[i + 4], wdrtas_logbuffer[i + 5], - wdrtas_logbuffer[i + 6], wdrtas_logbuffer[i + 7], - wdrtas_logbuffer[i + 8], wdrtas_logbuffer[i + 9], - wdrtas_logbuffer[i + 10], wdrtas_logbuffer[i + 11], - wdrtas_logbuffer[i + 12], wdrtas_logbuffer[i + 13], + wdrtas_logbuffer[i + 0], wdrtas_logbuffer[i + 1], + wdrtas_logbuffer[i + 2], wdrtas_logbuffer[i + 3], + wdrtas_logbuffer[i + 4], wdrtas_logbuffer[i + 5], + wdrtas_logbuffer[i + 6], wdrtas_logbuffer[i + 7], + wdrtas_logbuffer[i + 8], wdrtas_logbuffer[i + 9], + wdrtas_logbuffer[i + 10], wdrtas_logbuffer[i + 11], + wdrtas_logbuffer[i + 12], wdrtas_logbuffer[i + 13], wdrtas_logbuffer[i + 14], wdrtas_logbuffer[i + 15]); } @@ -192,8 +187,7 @@ wdrtas_log_scanned_event(void) * RTAS function event-scan and repeats these calls as long as there are * events available. All events will be dumped. */ -static void -wdrtas_timer_keepalive(void) +static void wdrtas_timer_keepalive(void) { long result; @@ -218,8 +212,7 @@ wdrtas_timer_keepalive(void) * wdrtas_get_temperature returns the current temperature in Fahrenheit. It * uses the RTAS call get-sensor-state, token 3 to do so */ -static int -wdrtas_get_temperature(void) +static int wdrtas_get_temperature(void) { long result; int temperature = 0; @@ -243,8 +236,7 @@ wdrtas_get_temperature(void) * returns a bitmask of defines WDIOF_... as defined in * include/linux/watchdog.h */ -static int -wdrtas_get_status(void) +static int wdrtas_get_status(void) { return 0; /* TODO */ } @@ -255,8 +247,7 @@ wdrtas_get_status(void) * returns a bitmask of defines WDIOF_... as defined in * include/linux/watchdog.h, indicating why the watchdog rebooted the system */ -static int -wdrtas_get_boot_status(void) +static int wdrtas_get_boot_status(void) { return 0; /* TODO */ } @@ -276,8 +267,7 @@ wdrtas_get_boot_status(void) * character 'V'. This character allows the watchdog device to be closed * properly. */ -static ssize_t -wdrtas_write(struct file *file, const char __user *buf, +static ssize_t wdrtas_write(struct file *file, const char __user *buf, size_t len, loff_t *ppos) { int i; @@ -306,7 +296,6 @@ out: /** * wdrtas_ioctl - ioctl function for the watchdog device - * @inode: inode structure * @file: file structure * @cmd: command for ioctl * @arg: argument pointer @@ -315,9 +304,9 @@ out: * * wdrtas_ioctl implements the watchdog API ioctls */ -static int -wdrtas_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) + +static long wdrtas_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int __user *argp = (void __user *)arg; int i; @@ -357,9 +346,9 @@ wdrtas_ioctl(struct inode *inode, struct file *file, wdrtas_timer_keepalive(); wdrtas_timer_start(); } + /* not implemented. Done by H8 if (i & WDIOS_TEMPPANIC) { - /* not implemented. Done by H8 */ - } + } */ return 0; case WDIOC_KEEPALIVE: @@ -399,8 +388,7 @@ wdrtas_ioctl(struct inode *inode, struct file *file, * * function called when watchdog device is opened */ -static int -wdrtas_open(struct inode *inode, struct file *file) +static int wdrtas_open(struct inode *inode, struct file *file) { /* only open once */ if (atomic_inc_return(&wdrtas_miscdev_open) > 1) { @@ -423,8 +411,7 @@ wdrtas_open(struct inode *inode, struct file *file) * * close function. Always succeeds */ -static int -wdrtas_close(struct inode *inode, struct file *file) +static int wdrtas_close(struct inode *inode, struct file *file) { /* only stop watchdog, if this was announced using 'V' before */ if (wdrtas_expect_close == WDRTAS_MAGIC_CHAR) @@ -453,8 +440,7 @@ wdrtas_close(struct inode *inode, struct file *file) * wdrtas_temp_read gives the temperature to the users by copying this * value as one byte into the user space buffer. The unit is Fahrenheit... */ -static ssize_t -wdrtas_temp_read(struct file *file, char __user *buf, +static ssize_t wdrtas_temp_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) { int temperature = 0; @@ -478,8 +464,7 @@ wdrtas_temp_read(struct file *file, char __user *buf, * * function called when temperature device is opened */ -static int -wdrtas_temp_open(struct inode *inode, struct file *file) +static int wdrtas_temp_open(struct inode *inode, struct file *file) { return nonseekable_open(inode, file); } @@ -493,8 +478,7 @@ wdrtas_temp_open(struct inode *inode, struct file *file) * * close function. Always succeeds */ -static int -wdrtas_temp_close(struct inode *inode, struct file *file) +static int wdrtas_temp_close(struct inode *inode, struct file *file) { return 0; } @@ -509,10 +493,10 @@ wdrtas_temp_close(struct inode *inode, struct file *file) * * wdrtas_reboot stops the watchdog in case of a reboot */ -static int -wdrtas_reboot(struct notifier_block *this, unsigned long code, void *ptr) +static int wdrtas_reboot(struct notifier_block *this, + unsigned long code, void *ptr) { - if ( (code==SYS_DOWN) || (code==SYS_HALT) ) + if (code == SYS_DOWN || code == SYS_HALT) wdrtas_timer_stop(); return NOTIFY_DONE; @@ -524,7 +508,7 @@ static const struct file_operations wdrtas_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdrtas_write, - .ioctl = wdrtas_ioctl, + .unlocked_ioctl = wdrtas_ioctl, .open = wdrtas_open, .release = wdrtas_close, }; @@ -562,8 +546,7 @@ static struct notifier_block wdrtas_notifier = { * this watchdog driver. It tolerates, if "get-sensor-state" and * "ibm,get-system-parameter" are not available. */ -static int -wdrtas_get_tokens(void) +static int wdrtas_get_tokens(void) { wdrtas_token_get_sensor_state = rtas_token("get-sensor-state"); if (wdrtas_token_get_sensor_state == RTAS_UNKNOWN_SERVICE) { @@ -603,8 +586,7 @@ wdrtas_get_tokens(void) * wdrtas_register_devs unregisters the watchdog and temperature watchdog * misc devs */ -static void -wdrtas_unregister_devs(void) +static void wdrtas_unregister_devs(void) { misc_deregister(&wdrtas_miscdev); if (wdrtas_token_get_sensor_state != RTAS_UNKNOWN_SERVICE) @@ -619,8 +601,7 @@ wdrtas_unregister_devs(void) * wdrtas_register_devs registers the watchdog and temperature watchdog * misc devs */ -static int -wdrtas_register_devs(void) +static int wdrtas_register_devs(void) { int result; @@ -651,8 +632,7 @@ wdrtas_register_devs(void) * * registers the file handlers and the reboot notifier */ -static int __init -wdrtas_init(void) +static int __init wdrtas_init(void) { if (wdrtas_get_tokens()) return -ENODEV; @@ -680,8 +660,7 @@ wdrtas_init(void) * * unregisters the file handlers and the reboot notifier */ -static void __exit -wdrtas_exit(void) +static void __exit wdrtas_exit(void) { if (!wdrtas_nowayout) wdrtas_timer_stop(); -- cgit v1.2.3 From d0e58eed05f9baf77c4f75e794ae245f6dae240a Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:51 +0100 Subject: [WATCHDOG 55/57] wdt285: switch to unlocked_ioctl and tidy up oddments of coding style Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wdt285.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/watchdog/wdt285.c b/drivers/watchdog/wdt285.c index e4cf661dc890..fea398a4ca32 100644 --- a/drivers/watchdog/wdt285.c +++ b/drivers/watchdog/wdt285.c @@ -26,9 +26,9 @@ #include #include #include +#include +#include -#include -#include #include #include #include @@ -115,8 +115,8 @@ static int watchdog_release(struct inode *inode, struct file *file) return 0; } -static ssize_t -watchdog_write(struct file *file, const char *data, size_t len, loff_t *ppos) +static ssize_t watchdog_write(struct file *file, const char *data, + size_t len, loff_t *ppos) { /* * Refresh the timer. @@ -127,19 +127,18 @@ watchdog_write(struct file *file, const char *data, size_t len, loff_t *ppos) return len; } -static struct watchdog_info ident = { +static const struct watchdog_info ident = { .options = WDIOF_SETTIMEOUT, .identity = "Footbridge Watchdog", }; -static int -watchdog_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long watchdog_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { unsigned int new_margin; int ret = -ENOTTY; - switch(cmd) { + switch (cmd) { case WDIOC_GETSUPPORT: ret = 0; if (copy_to_user((void *)arg, &ident, sizeof(ident))) @@ -148,7 +147,7 @@ watchdog_ioctl(struct inode *inode, struct file *file, unsigned int cmd, case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: - ret = put_user(0,(int *)arg); + ret = put_user(0, (int *)arg); break; case WDIOC_KEEPALIVE: @@ -182,7 +181,7 @@ static const struct file_operations watchdog_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = watchdog_write, - .ioctl = watchdog_ioctl, + .unlocked_ioctl = watchdog_ioctl, .open = watchdog_open, .release = watchdog_release, }; @@ -204,11 +203,13 @@ static int __init footbridge_watchdog_init(void) if (retval < 0) return retval; - printk("Footbridge Watchdog Timer: 0.01, timer margin: %d sec\n", - soft_margin); + printk(KERN_INFO + "Footbridge Watchdog Timer: 0.01, timer margin: %d sec\n", + soft_margin); if (machine_is_cats()) - printk("Warning: Watchdog reset may not work on this machine.\n"); + printk(KERN_WARN + "Warning: Watchdog reset may not work on this machine.\n"); return 0; } @@ -223,7 +224,7 @@ MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); module_param(soft_margin, int, 0); -MODULE_PARM_DESC(soft_margin,"Watchdog timeout in seconds"); +MODULE_PARM_DESC(soft_margin, "Watchdog timeout in seconds"); module_init(footbridge_watchdog_init); module_exit(footbridge_watchdog_exit); -- cgit v1.2.3 From f2b79c6ede54cf07355ac8d8f3044d682cd0c5ca Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Mon, 19 May 2008 14:09:57 +0100 Subject: [WATCHDOG 56/57] wdt977: clean up, coding style and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wdt977.c | 148 +++++++++++++++++++++++----------------------- 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/drivers/watchdog/wdt977.c b/drivers/watchdog/wdt977.c index fb4b876c9fda..bdc28e522f03 100644 --- a/drivers/watchdog/wdt977.c +++ b/drivers/watchdog/wdt977.c @@ -19,7 +19,8 @@ * 07-Jul-2003 Daniele Bellucci: Audit return code of misc_register in * nwwatchdog_init. * 25-Oct-2005 Woody Suwalski: Convert addresses to #defs, add spinlocks - * remove limitiation to be used on Netwinders only + * remove limitiation to be used on + * Netwinders only */ #include @@ -33,11 +34,11 @@ #include #include #include +#include +#include -#include #include #include -#include #define WATCHDOG_VERSION "0.04" #define WATCHDOG_NAME "Wdt977" @@ -45,7 +46,7 @@ #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" #define IO_INDEX_PORT 0x370 /* on some systems it can be 0x3F0 */ -#define IO_DATA_PORT (IO_INDEX_PORT+1) +#define IO_DATA_PORT (IO_INDEX_PORT + 1) #define UNLOCK_DATA 0x87 #define LOCK_DATA 0xAA @@ -62,13 +63,16 @@ static char expect_close; static DEFINE_SPINLOCK(spinlock); module_param(timeout, int, 0); -MODULE_PARM_DESC(timeout,"Watchdog timeout in seconds (60..15300), default=" __MODULE_STRING(DEFAULT_TIMEOUT) ")"); +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (60..15300), default=" + __MODULE_STRING(DEFAULT_TIMEOUT) ")"); module_param(testmode, int, 0); -MODULE_PARM_DESC(testmode,"Watchdog testmode (1 = no reboot), default=0"); +MODULE_PARM_DESC(testmode, "Watchdog testmode (1 = no reboot), default=0"); static int nowayout = WATCHDOG_NOWAYOUT; module_param(nowayout, int, 0); -MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +MODULE_PARM_DESC(nowayout, + "Watchdog cannot be stopped once started (default=" + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); /* * Start the watchdog @@ -95,14 +99,16 @@ static int wdt977_start(void) outb_p(0xF2, IO_INDEX_PORT); outb_p(timeoutM, IO_DATA_PORT); outb_p(0xF3, IO_INDEX_PORT); - outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for kbd/mouse/LED */ + outb_p(0x00, IO_DATA_PORT); /* another setting is 0E for + kbd/mouse/LED */ outb_p(0xF4, IO_INDEX_PORT); outb_p(0x00, IO_DATA_PORT); - /* at last select device Aux1 (dev=7) and set GP16 as a watchdog output */ - /* in test mode watch the bit 1 on F4 to indicate "triggered" */ - if (!testmode) - { + /* At last select device Aux1 (dev=7) and set GP16 as a + * watchdog output. In test mode watch the bit 1 on F4 to + * indicate "triggered" + */ + if (!testmode) { outb_p(DEVICE_REGISTER, IO_INDEX_PORT); outb_p(0x07, IO_DATA_PORT); outb_p(0xE6, IO_INDEX_PORT); @@ -147,7 +153,8 @@ static int wdt977_stop(void) outb_p(0xF2, IO_INDEX_PORT); outb_p(0x00, IO_DATA_PORT); - /* at last select device Aux1 (dev=7) and set GP16 as a watchdog output */ + /* at last select device Aux1 (dev=7) and set + GP16 as a watchdog output */ outb_p(DEVICE_REGISTER, IO_INDEX_PORT); outb_p(0x07, IO_DATA_PORT); outb_p(0xE6, IO_INDEX_PORT); @@ -202,16 +209,18 @@ static int wdt977_set_timeout(int t) tmrval = (t + 59) / 60; if (machine_is_netwinder()) { - /* we have a hw bug somewhere, so each 977 minute is actually only 30sec - * this limits the max timeout to half of device max of 255 minutes... + /* we have a hw bug somewhere, so each 977 minute is actually + * only 30sec. This limits the max timeout to half of device + * max of 255 minutes... */ tmrval += tmrval; } - if ((tmrval < 1) || (tmrval > 255)) + if (tmrval < 1 || tmrval > 255) return -EINVAL; - /* timeout is the timeout in seconds, timeoutM is the timeout in minutes) */ + /* timeout is the timeout in seconds, timeoutM is + the timeout in minutes) */ timeout = t; timeoutM = tmrval; return 0; @@ -243,7 +252,7 @@ static int wdt977_get_status(int *status) spin_unlock_irqrestore(&spinlock, flags); - *status=0; + *status = 0; if (new_status & 1) *status |= WDIOF_CARDRESET; @@ -258,7 +267,7 @@ static int wdt977_get_status(int *status) static int wdt977_open(struct inode *inode, struct file *file) { /* If the watchdog is alive we don't need to start it again */ - if( test_and_set_bit(0,&timer_alive) ) + if (test_and_set_bit(0, &timer_alive)) return -EBUSY; if (nowayout) @@ -274,13 +283,13 @@ static int wdt977_release(struct inode *inode, struct file *file) * Shut off the timer. * Lock it in if it's a module and we set nowayout */ - if (expect_close == 42) - { + if (expect_close == 42) { wdt977_stop(); - clear_bit(0,&timer_alive); + clear_bit(0, &timer_alive); } else { wdt977_keepalive(); - printk(KERN_CRIT PFX "Unexpected close, not stopping watchdog!\n"); + printk(KERN_CRIT PFX + "Unexpected close, not stopping watchdog!\n"); } expect_close = 0; return 0; @@ -301,17 +310,14 @@ static int wdt977_release(struct inode *inode, struct file *file) static ssize_t wdt977_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { - if (count) - { - if (!nowayout) - { + if (count) { + if (!nowayout) { size_t i; /* In case it was set long ago */ expect_close = 0; - for (i = 0; i != count; i++) - { + for (i = 0; i != count; i++) { char c; if (get_user(c, buf + i)) return -EFAULT; @@ -326,6 +332,14 @@ static ssize_t wdt977_write(struct file *file, const char __user *buf, return count; } +static const struct watchdog_info ident = { + .options = WDIOF_SETTIMEOUT | + WDIOF_MAGICCLOSE | + WDIOF_KEEPALIVEPING, + .firmware_version = 1, + .identity = WATCHDOG_NAME, +}; + /* * wdt977_ioctl: * @inode: inode of the device @@ -337,16 +351,8 @@ static ssize_t wdt977_write(struct file *file, const char __user *buf, * according to their available features. */ -static struct watchdog_info ident = { - .options = WDIOF_SETTIMEOUT | - WDIOF_MAGICCLOSE | - WDIOF_KEEPALIVEPING, - .firmware_version = 1, - .identity = WATCHDOG_NAME, -}; - -static int wdt977_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long wdt977_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int status; int new_options, retval = -EINVAL; @@ -358,8 +364,7 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, uarg.i = (int __user *)arg; - switch(cmd) - { + switch (cmd) { default: return -ENOTTY; @@ -379,7 +384,7 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, return 0; case WDIOC_SETOPTIONS: - if (get_user (new_options, uarg.i)) + if (get_user(new_options, uarg.i)) return -EFAULT; if (new_options & WDIOS_DISABLECARD) { @@ -413,23 +418,21 @@ static int wdt977_ioctl(struct inode *inode, struct file *file, static int wdt977_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code==SYS_DOWN || code==SYS_HALT) + if (code == SYS_DOWN || code == SYS_HALT) wdt977_stop(); return NOTIFY_DONE; } -static const struct file_operations wdt977_fops= -{ +static const struct file_operations wdt977_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdt977_write, - .ioctl = wdt977_ioctl, + .unlocked_ioctl = wdt977_ioctl, .open = wdt977_open, .release = wdt977_release, }; -static struct miscdevice wdt977_miscdev= -{ +static struct miscdevice wdt977_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &wdt977_fops, @@ -443,51 +446,48 @@ static int __init wd977_init(void) { int rc; - //if (!machine_is_netwinder()) - // return -ENODEV; - printk(KERN_INFO PFX DRIVER_VERSION); - /* Check that the timeout value is within it's range ; if not reset to the default */ - if (wdt977_set_timeout(timeout)) - { + /* Check that the timeout value is within its range; + if not reset to the default */ + if (wdt977_set_timeout(timeout)) { wdt977_set_timeout(DEFAULT_TIMEOUT); - printk(KERN_INFO PFX "timeout value must be 60 Date: Mon, 19 May 2008 14:10:02 +0100 Subject: [WATCHDOG 57/57] wdt501/pci: Clean up, coding style and switch to unlocked_ioctl Review and switch to unlocked_ioctl Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/wdt.c | 176 +++++++++++++------------- drivers/watchdog/wdt_pci.c | 300 ++++++++++++++++++++++++++------------------- 2 files changed, 265 insertions(+), 211 deletions(-) diff --git a/drivers/watchdog/wdt.c b/drivers/watchdog/wdt.c index 756fb15fdce7..53a6b18bcb9a 100644 --- a/drivers/watchdog/wdt.c +++ b/drivers/watchdog/wdt.c @@ -24,9 +24,10 @@ * Matt Crocker). * Alan Cox : Added wdt= boot option * Alan Cox : Cleaned up copy/user stuff - * Tim Hockin : Added insmod parameters, comment cleanup - * Parameterized timeout - * Tigran Aivazian : Restructured wdt_init() to handle failures + * Tim Hockin : Added insmod parameters, comment + * cleanup, parameterized timeout + * Tigran Aivazian : Restructured wdt_init() to handle + * failures * Joel Becker : Added WDIOC_GET/SETTIMEOUT * Matt Domsch : Added nowayout module option */ @@ -42,9 +43,9 @@ #include #include #include +#include +#include -#include -#include #include #include "wd501p.h" @@ -60,15 +61,19 @@ static char expect_close; static int heartbeat = WD_TIMO; static int wd_heartbeat; module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0 65535)) + if (t < 1 || t > 65535) return -EINVAL; heartbeat = t; @@ -200,7 +211,7 @@ static int wdt_get_status(int *status) new_status = inb_p(WDT_SR); spin_unlock_irqrestore(&wdt_lock, flags); - *status=0; + *status = 0; if (new_status & WDC_SR_ISOI0) *status |= WDIOF_EXTERN1; if (new_status & WDC_SR_ISII1) @@ -266,7 +277,7 @@ static irqreturn_t wdt_interrupt(int irq, void *dev_id) #ifdef CONFIG_WDT_501 if (!(status & WDC_SR_TGOOD)) - printk(KERN_CRIT "Overheat alarm.(%d)\n",inb_p(WDT_RT)); + printk(KERN_CRIT "Overheat alarm.(%d)\n", inb_p(WDT_RT)); if (!(status & WDC_SR_PSUOVER)) printk(KERN_CRIT "PSU over voltage.\n"); if (!(status & WDC_SR_PSUUNDR)) @@ -304,9 +315,10 @@ static irqreturn_t wdt_interrupt(int irq, void *dev_id) * write of data will do, as we we don't define content meaning. */ -static ssize_t wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t wdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { - if(count) { + if (count) { if (!nowayout) { size_t i; @@ -328,7 +340,6 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, size_t count /** * wdt_ioctl: - * @inode: inode of the device * @file: file handle to the device * @cmd: watchdog command * @arg: argument pointer @@ -338,8 +349,7 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, size_t count * querying capabilities and current status. */ -static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -362,32 +372,28 @@ static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, ident.options |= WDIOF_FANFAULT; #endif /* CONFIG_WDT_501 */ - switch(cmd) - { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - - case WDIOC_GETSTATUS: - wdt_get_status(&status); - return put_user(status, p); - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_ping(); - return 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_heartbeat, p)) - return -EFAULT; - - if (wdt_set_heartbeat(new_heartbeat)) - return -EINVAL; - - wdt_ping(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, p); + switch (cmd) { + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + wdt_get_status(&status); + return put_user(status, p); + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdt_ping(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_heartbeat, p)) + return -EFAULT; + if (wdt_set_heartbeat(new_heartbeat)) + return -EINVAL; + wdt_ping(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, p); } } @@ -405,7 +411,7 @@ static int wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, static int wdt_open(struct inode *inode, struct file *file) { - if(test_and_set_bit(0, &wdt_is_open)) + if (test_and_set_bit(0, &wdt_is_open)) return -EBUSY; /* * Activate @@ -432,7 +438,8 @@ static int wdt_release(struct inode *inode, struct file *file) wdt_stop(); clear_bit(0, &wdt_is_open); } else { - printk(KERN_CRIT "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); + printk(KERN_CRIT + "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); wdt_ping(); } expect_close = 0; @@ -451,14 +458,15 @@ static int wdt_release(struct inode *inode, struct file *file) * farenheit. It was designed by an imperial measurement luddite. */ -static ssize_t wdt_temp_read(struct file *file, char __user *buf, size_t count, loff_t *ptr) +static ssize_t wdt_temp_read(struct file *file, char __user *buf, + size_t count, loff_t *ptr) { int temperature; if (wdt_get_temperature(&temperature)) return -EFAULT; - if (copy_to_user (buf, &temperature, 1)) + if (copy_to_user(buf, &temperature, 1)) return -EFAULT; return 1; @@ -506,10 +514,8 @@ static int wdt_temp_release(struct inode *inode, struct file *file) static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if(code==SYS_DOWN || code==SYS_HALT) { - /* Turn the card off */ + if (code == SYS_DOWN || code == SYS_HALT) wdt_stop(); - } return NOTIFY_DONE; } @@ -522,7 +528,7 @@ static const struct file_operations wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdt_write, - .ioctl = wdt_ioctl, + .unlocked_ioctl = wdt_ioctl, .open = wdt_open, .release = wdt_release, }; @@ -576,7 +582,7 @@ static void __exit wdt_exit(void) #endif /* CONFIG_WDT_501 */ unregister_reboot_notifier(&wdt_notifier); free_irq(irq, NULL); - release_region(io,8); + release_region(io, 8); } /** @@ -591,44 +597,49 @@ static int __init wdt_init(void) { int ret; - /* Check that the heartbeat value is within it's range ; if not reset to the default */ + /* Check that the heartbeat value is within it's range; + if not reset to the default */ if (wdt_set_heartbeat(heartbeat)) { wdt_set_heartbeat(WD_TIMO); - printk(KERN_INFO "wdt: heartbeat value must be 0 #include #include +#include +#include -#include -#include #include #define WDT_IS_PCI @@ -73,7 +75,7 @@ /* We can only use 1 card due to the /dev/watchdog restriction */ static int dev_count; -static struct semaphore open_sem; +static unsigned long open_lock; static DEFINE_SPINLOCK(wdtpci_lock); static char expect_close; @@ -86,18 +88,23 @@ static int irq; static int heartbeat = WD_TIMO; static int wd_heartbeat; module_param(heartbeat, int, 0); -MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (0>8, WDT_COUNT0+ctr); + outb(val & 0xFF, WDT_COUNT0 + ctr); + udelay(8); + outb(val >> 8, WDT_COUNT0 + ctr); + udelay(8); } /** @@ -134,23 +144,35 @@ static int wdtpci_start(void) * "pet" the watchdog, as Access says. * This resets the clock outputs. */ - inb_p(WDT_DC); /* Disable watchdog */ - wdtpci_ctr_mode(2,0); /* Program CTR2 for Mode 0: Pulse on Terminal Count */ - outb_p(0, WDT_DC); /* Enable watchdog */ - - inb_p(WDT_DC); /* Disable watchdog */ - outb_p(0, WDT_CLOCK); /* 2.0833MHz clock */ - inb_p(WDT_BUZZER); /* disable */ - inb_p(WDT_OPTONOTRST); /* disable */ - inb_p(WDT_OPTORST); /* disable */ - inb_p(WDT_PROGOUT); /* disable */ - wdtpci_ctr_mode(0,3); /* Program CTR0 for Mode 3: Square Wave Generator */ - wdtpci_ctr_mode(1,2); /* Program CTR1 for Mode 2: Rate Generator */ - wdtpci_ctr_mode(2,1); /* Program CTR2 for Mode 1: Retriggerable One-Shot */ - wdtpci_ctr_load(0,20833); /* count at 100Hz */ - wdtpci_ctr_load(1,wd_heartbeat);/* Heartbeat */ + inb(WDT_DC); /* Disable watchdog */ + udelay(8); + wdtpci_ctr_mode(2, 0); /* Program CTR2 for Mode 0: + Pulse on Terminal Count */ + outb(0, WDT_DC); /* Enable watchdog */ + udelay(8); + inb(WDT_DC); /* Disable watchdog */ + udelay(8); + outb(0, WDT_CLOCK); /* 2.0833MHz clock */ + udelay(8); + inb(WDT_BUZZER); /* disable */ + udelay(8); + inb(WDT_OPTONOTRST); /* disable */ + udelay(8); + inb(WDT_OPTORST); /* disable */ + udelay(8); + inb(WDT_PROGOUT); /* disable */ + udelay(8); + wdtpci_ctr_mode(0, 3); /* Program CTR0 for Mode 3: + Square Wave Generator */ + wdtpci_ctr_mode(1, 2); /* Program CTR1 for Mode 2: + Rate Generator */ + wdtpci_ctr_mode(2, 1); /* Program CTR2 for Mode 1: + Retriggerable One-Shot */ + wdtpci_ctr_load(0, 20833); /* count at 100Hz */ + wdtpci_ctr_load(1, wd_heartbeat);/* Heartbeat */ /* DO NOT LOAD CTR2 on PCI card! -- JPN */ - outb_p(0, WDT_DC); /* Enable watchdog */ + outb(0, WDT_DC); /* Enable watchdog */ + udelay(8); spin_unlock_irqrestore(&wdtpci_lock, flags); return 0; @@ -162,14 +184,15 @@ static int wdtpci_start(void) * Stop the watchdog driver. */ -static int wdtpci_stop (void) +static int wdtpci_stop(void) { unsigned long flags; /* Turn the card off */ spin_lock_irqsave(&wdtpci_lock, flags); - inb_p(WDT_DC); /* Disable watchdog */ - wdtpci_ctr_load(2,0); /* 0 length reset pulses now */ + inb(WDT_DC); /* Disable watchdog */ + udelay(8); + wdtpci_ctr_load(2, 0); /* 0 length reset pulses now */ spin_unlock_irqrestore(&wdtpci_lock, flags); return 0; } @@ -177,20 +200,23 @@ static int wdtpci_stop (void) /** * wdtpci_ping: * - * Reload counter one with the watchdog heartbeat. We don't bother reloading - * the cascade counter. + * Reload counter one with the watchdog heartbeat. We don't bother + * reloading the cascade counter. */ static int wdtpci_ping(void) { unsigned long flags; - /* Write a watchdog value */ spin_lock_irqsave(&wdtpci_lock, flags); - inb_p(WDT_DC); /* Disable watchdog */ - wdtpci_ctr_mode(1,2); /* Re-Program CTR1 for Mode 2: Rate Generator */ - wdtpci_ctr_load(1,wd_heartbeat);/* Heartbeat */ - outb_p(0, WDT_DC); /* Enable watchdog */ + /* Write a watchdog value */ + inb(WDT_DC); /* Disable watchdog */ + udelay(8); + wdtpci_ctr_mode(1, 2); /* Re-Program CTR1 for Mode 2: + Rate Generator */ + wdtpci_ctr_load(1, wd_heartbeat);/* Heartbeat */ + outb(0, WDT_DC); /* Enable watchdog */ + udelay(8); spin_unlock_irqrestore(&wdtpci_lock, flags); return 0; } @@ -199,14 +225,14 @@ static int wdtpci_ping(void) * wdtpci_set_heartbeat: * @t: the new heartbeat value that needs to be set. * - * Set a new heartbeat value for the watchdog device. If the heartbeat value is - * incorrect we keep the old value and return -EINVAL. If successfull we - * return 0. + * Set a new heartbeat value for the watchdog device. If the heartbeat + * value is incorrect we keep the old value and return -EINVAL. + * If successful we return 0. */ static int wdtpci_set_heartbeat(int t) { /* Arbitrary, can't find the card's limits */ - if ((t < 1) || (t > 65535)) + if (t < 1 || t > 65535) return -EINVAL; heartbeat = t; @@ -227,9 +253,14 @@ static int wdtpci_set_heartbeat(int t) static int wdtpci_get_status(int *status) { - unsigned char new_status=inb_p(WDT_SR); + unsigned char new_status; + unsigned long flags; + + spin_lock_irqsave(&wdtpci_lock, flags); + new_status = inb(WDT_SR); + spin_unlock_irqrestore(&wdtpci_lock, flags); - *status=0; + *status = 0; if (new_status & WDC_SR_ISOI0) *status |= WDIOF_EXTERN1; if (new_status & WDC_SR_ISII1) @@ -259,8 +290,12 @@ static int wdtpci_get_status(int *status) static int wdtpci_get_temperature(int *temperature) { - unsigned short c=inb_p(WDT_RT); - + unsigned short c; + unsigned long flags; + spin_lock_irqsave(&wdtpci_lock, flags); + c = inb(WDT_RT); + udelay(8); + spin_unlock_irqrestore(&wdtpci_lock, flags); *temperature = (c * 11 / 15) + 7; return 0; } @@ -282,17 +317,25 @@ static irqreturn_t wdtpci_interrupt(int irq, void *dev_id) * Read the status register see what is up and * then printk it. */ - unsigned char status=inb_p(WDT_SR); + unsigned char status; + + spin_lock(&wdtpci_lock); + + status = inb(WDT_SR); + udelay(8); printk(KERN_CRIT PFX "status %d\n", status); #ifdef CONFIG_WDT_501_PCI - if (!(status & WDC_SR_TGOOD)) - printk(KERN_CRIT PFX "Overheat alarm.(%d)\n",inb_p(WDT_RT)); + if (!(status & WDC_SR_TGOOD)) { + u8 alarm = inb(WDT_RT); + printk(KERN_CRIT PFX "Overheat alarm.(%d)\n", alarm); + udelay(8); + } if (!(status & WDC_SR_PSUOVER)) - printk(KERN_CRIT PFX "PSU over voltage.\n"); + printk(KERN_CRIT PFX "PSU over voltage.\n"); if (!(status & WDC_SR_PSUUNDR)) - printk(KERN_CRIT PFX "PSU under voltage.\n"); + printk(KERN_CRIT PFX "PSU under voltage.\n"); if (tachometer) { if (!(status & WDC_SR_FANGOOD)) printk(KERN_CRIT PFX "Possible fan fault.\n"); @@ -310,6 +353,7 @@ static irqreturn_t wdtpci_interrupt(int irq, void *dev_id) printk(KERN_CRIT PFX "Reset in 5ms.\n"); #endif } + spin_unlock(&wdtpci_lock); return IRQ_HANDLED; } @@ -325,7 +369,8 @@ static irqreturn_t wdtpci_interrupt(int irq, void *dev_id) * write of data will do, as we we don't define content meaning. */ -static ssize_t wdtpci_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) +static ssize_t wdtpci_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { if (count) { if (!nowayout) { @@ -335,7 +380,7 @@ static ssize_t wdtpci_write(struct file *file, const char __user *buf, size_t co for (i = 0; i != count; i++) { char c; - if(get_user(c, buf+i)) + if (get_user(c, buf+i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -343,13 +388,11 @@ static ssize_t wdtpci_write(struct file *file, const char __user *buf, size_t co } wdtpci_ping(); } - return count; } /** * wdtpci_ioctl: - * @inode: inode of the device * @file: file handle to the device * @cmd: watchdog command * @arg: argument pointer @@ -359,8 +402,8 @@ static ssize_t wdtpci_write(struct file *file, const char __user *buf, size_t co * querying capabilities and current status. */ -static int wdtpci_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static long wdtpci_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { int new_heartbeat; int status; @@ -383,33 +426,29 @@ static int wdtpci_ioctl(struct inode *inode, struct file *file, unsigned int cmd ident.options |= WDIOF_FANFAULT; #endif /* CONFIG_WDT_501_PCI */ - switch(cmd) - { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))?-EFAULT:0; - - case WDIOC_GETSTATUS: - wdtpci_get_status(&status); - return put_user(status, p); - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - wdtpci_ping(); - return 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_heartbeat, p)) - return -EFAULT; - - if (wdtpci_set_heartbeat(new_heartbeat)) - return -EINVAL; - - wdtpci_ping(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, p); - } + switch (cmd) { + default: + return -ENOTTY; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + wdtpci_get_status(&status); + return put_user(status, p); + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + wdtpci_ping(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_heartbeat, p)) + return -EFAULT; + if (wdtpci_set_heartbeat(new_heartbeat)) + return -EINVAL; + wdtpci_ping(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, p); + } } /** @@ -426,12 +465,11 @@ static int wdtpci_ioctl(struct inode *inode, struct file *file, unsigned int cmd static int wdtpci_open(struct inode *inode, struct file *file) { - if (down_trylock(&open_sem)) + if (test_and_set_bit(0, &open_lock)) return -EBUSY; - if (nowayout) { + if (nowayout) __module_get(THIS_MODULE); - } /* * Activate */ @@ -460,7 +498,7 @@ static int wdtpci_release(struct inode *inode, struct file *file) wdtpci_ping(); } expect_close = 0; - up(&open_sem); + clear_bit(0, &open_lock); return 0; } @@ -476,14 +514,15 @@ static int wdtpci_release(struct inode *inode, struct file *file) * fahrenheit. It was designed by an imperial measurement luddite. */ -static ssize_t wdtpci_temp_read(struct file *file, char __user *buf, size_t count, loff_t *ptr) +static ssize_t wdtpci_temp_read(struct file *file, char __user *buf, + size_t count, loff_t *ptr) { int temperature; if (wdtpci_get_temperature(&temperature)) return -EFAULT; - if (copy_to_user (buf, &temperature, 1)) + if (copy_to_user(buf, &temperature, 1)) return -EFAULT; return 1; @@ -529,12 +568,10 @@ static int wdtpci_temp_release(struct inode *inode, struct file *file) */ static int wdtpci_notify_sys(struct notifier_block *this, unsigned long code, - void *unused) + void *unused) { - if (code==SYS_DOWN || code==SYS_HALT) { - /* Turn the card off */ + if (code == SYS_DOWN || code == SYS_HALT) wdtpci_stop(); - } return NOTIFY_DONE; } @@ -547,7 +584,7 @@ static const struct file_operations wdtpci_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = wdtpci_write, - .ioctl = wdtpci_ioctl, + .unlocked_ioctl = wdtpci_ioctl, .open = wdtpci_open, .release = wdtpci_release, }; @@ -584,80 +621,85 @@ static struct notifier_block wdtpci_notifier = { }; -static int __devinit wdtpci_init_one (struct pci_dev *dev, - const struct pci_device_id *ent) +static int __devinit wdtpci_init_one(struct pci_dev *dev, + const struct pci_device_id *ent) { int ret = -EIO; dev_count++; if (dev_count > 1) { - printk (KERN_ERR PFX "this driver only supports 1 device\n"); + printk(KERN_ERR PFX "This driver only supports one device\n"); return -ENODEV; } - if (pci_enable_device (dev)) { - printk (KERN_ERR PFX "Not possible to enable PCI Device\n"); + if (pci_enable_device(dev)) { + printk(KERN_ERR PFX "Not possible to enable PCI Device\n"); return -ENODEV; } - if (pci_resource_start (dev, 2) == 0x0000) { - printk (KERN_ERR PFX "No I/O-Address for card detected\n"); + if (pci_resource_start(dev, 2) == 0x0000) { + printk(KERN_ERR PFX "No I/O-Address for card detected\n"); ret = -ENODEV; goto out_pci; } - sema_init(&open_sem, 1); - irq = dev->irq; - io = pci_resource_start (dev, 2); + io = pci_resource_start(dev, 2); - if (request_region (io, 16, "wdt_pci") == NULL) { - printk (KERN_ERR PFX "I/O address 0x%04x already in use\n", io); + if (request_region(io, 16, "wdt_pci") == NULL) { + printk(KERN_ERR PFX "I/O address 0x%04x already in use\n", io); goto out_pci; } - if (request_irq (irq, wdtpci_interrupt, IRQF_DISABLED | IRQF_SHARED, + if (request_irq(irq, wdtpci_interrupt, IRQF_DISABLED | IRQF_SHARED, "wdt_pci", &wdtpci_miscdev)) { - printk (KERN_ERR PFX "IRQ %d is not free\n", irq); + printk(KERN_ERR PFX "IRQ %d is not free\n", irq); goto out_reg; } - printk ("PCI-WDT500/501 (PCI-WDG-CSM) driver 0.10 at 0x%04x (Interrupt %d)\n", - io, irq); + printk(KERN_INFO + "PCI-WDT500/501 (PCI-WDG-CSM) driver 0.10 at 0x%04x (Interrupt %d)\n", + io, irq); - /* Check that the heartbeat value is within it's range ; if not reset to the default */ + /* Check that the heartbeat value is within its range; + if not reset to the default */ if (wdtpci_set_heartbeat(heartbeat)) { wdtpci_set_heartbeat(WD_TIMO); - printk(KERN_INFO PFX "heartbeat value must be 0 Date: Wed, 30 Jul 2008 07:21:46 -0700 Subject: IPoIB/cm: Set correct SG list in ipoib_cm_init_rx_wr() wr->sg_list should be set to the sge pointer passed in, not priv->cm.rx_sge. Reported-by: Hoang-Nam Nguyen Signed-off-by: Roland Dreier --- drivers/infiniband/ulp/ipoib/ipoib_cm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/ulp/ipoib/ipoib_cm.c b/drivers/infiniband/ulp/ipoib/ipoib_cm.c index 0f2d3045061a..7ebc400a4b3d 100644 --- a/drivers/infiniband/ulp/ipoib/ipoib_cm.c +++ b/drivers/infiniband/ulp/ipoib/ipoib_cm.c @@ -337,7 +337,7 @@ static void ipoib_cm_init_rx_wr(struct net_device *dev, sge[i].length = PAGE_SIZE; wr->next = NULL; - wr->sg_list = priv->cm.rx_sge; + wr->sg_list = sge; wr->num_sge = priv->cm.num_frags; } -- cgit v1.2.3 From 52fd8ca6ad4124c15952ded35cfcf6adbd7ae8d4 Mon Sep 17 00:00:00 2001 From: Vegard Nossum Date: Wed, 30 Jul 2008 09:29:06 -0700 Subject: IB/ipath: Use unsigned long for irq flags A few functions in the ipath driver incorrectly use unsigned int to hold irq flags for spin_lock_irqsave(). This patch was generated using the Coccinelle framework with the following semantic patch: The semantic patch I used was this: @@ expression lock; identifier flags; expression subclass; @@ - unsigned int flags; + unsigned long flags; ... <+... ( spin_lock_irqsave(lock, flags) | _spin_lock_irqsave(lock) | spin_unlock_irqrestore(lock, flags) | _spin_unlock_irqrestore(lock, flags) | read_lock_irqsave(lock, flags) | _read_lock_irqsave(lock) | read_unlock_irqrestore(lock, flags) | _read_unlock_irqrestore(lock, flags) | write_lock_irqsave(lock, flags) | _write_lock_irqsave(lock) | write_unlock_irqrestore(lock, flags) | _write_unlock_irqrestore(lock, flags) | spin_lock_irqsave_nested(lock, flags, subclass) | _spin_lock_irqsave_nested(lock, subclass) | spin_unlock_irqrestore(lock, flags) | _spin_unlock_irqrestore(lock, flags) | _raw_spin_lock_flags(lock, flags) | __raw_spin_lock_flags(lock, flags) ) ...+> Cc: Ralph Campbell Cc: Julia Lawall Cc: Alexey Dobriyan Signed-off-by: Vegard Nossum Signed-off-by: Roland Dreier --- drivers/infiniband/hw/ipath/ipath_verbs.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/infiniband/hw/ipath/ipath_verbs.c b/drivers/infiniband/hw/ipath/ipath_verbs.c index 55c718828826..b766e40e9ebf 100644 --- a/drivers/infiniband/hw/ipath/ipath_verbs.c +++ b/drivers/infiniband/hw/ipath/ipath_verbs.c @@ -1021,7 +1021,7 @@ static void sdma_complete(void *cookie, int status) struct ipath_verbs_txreq *tx = cookie; struct ipath_qp *qp = tx->qp; struct ipath_ibdev *dev = to_idev(qp->ibqp.device); - unsigned int flags; + unsigned long flags; enum ib_wc_status ibs = status == IPATH_SDMA_TXREQ_S_OK ? IB_WC_SUCCESS : IB_WC_WR_FLUSH_ERR; @@ -1051,7 +1051,7 @@ static void sdma_complete(void *cookie, int status) static void decrement_dma_busy(struct ipath_qp *qp) { - unsigned int flags; + unsigned long flags; if (atomic_dec_and_test(&qp->s_dma_busy)) { spin_lock_irqsave(&qp->s_lock, flags); @@ -1221,7 +1221,7 @@ static int ipath_verbs_send_pio(struct ipath_qp *qp, unsigned flush_wc; u32 control; int ret; - unsigned int flags; + unsigned long flags; piobuf = ipath_getpiobuf(dd, plen, NULL); if (unlikely(piobuf == NULL)) { -- cgit v1.2.3 From 8401d92ba46a1e859464cbd9c9ee304f6e361da3 Mon Sep 17 00:00:00 2001 From: David Moore Date: Tue, 29 Jul 2008 23:46:25 -0700 Subject: firewire: Preserve response data alignment bug when it is harmless Recently, a bug having to do with the alignment of transaction response data was fixed. However, some apps such as libdc1394 relied on the presence of that bug in order to function correctly. In order to stay compatible with old versions of those apps, this patch preserves the bug in cases where it is harmless to normal operation (such as the single quadlet read) due to a simple duplication of data. This guarantees maximum compatability for those users who are using the old app with the fixed kernel. Signed-off-by: David Moore Signed-off-by: Stefan Richter --- drivers/firewire/fw-cdev.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/firewire/fw-cdev.c b/drivers/firewire/fw-cdev.c index bc81d6fcd2fd..2e6d5848d217 100644 --- a/drivers/firewire/fw-cdev.c +++ b/drivers/firewire/fw-cdev.c @@ -369,22 +369,33 @@ complete_transaction(struct fw_card *card, int rcode, struct response *response = data; struct client *client = response->client; unsigned long flags; + struct fw_cdev_event_response *r = &response->response; - if (length < response->response.length) - response->response.length = length; + if (length < r->length) + r->length = length; if (rcode == RCODE_COMPLETE) - memcpy(response->response.data, payload, - response->response.length); + memcpy(r->data, payload, r->length); spin_lock_irqsave(&client->lock, flags); list_del(&response->resource.link); spin_unlock_irqrestore(&client->lock, flags); - response->response.type = FW_CDEV_EVENT_RESPONSE; - response->response.rcode = rcode; - queue_event(client, &response->event, &response->response, - sizeof(response->response) + response->response.length, - NULL, 0); + r->type = FW_CDEV_EVENT_RESPONSE; + r->rcode = rcode; + + /* + * In the case that sizeof(*r) doesn't align with the position of the + * data, and the read is short, preserve an extra copy of the data + * to stay compatible with a pre-2.6.27 bug. Since the bug is harmless + * for short reads and some apps depended on it, this is both safe + * and prudent for compatibility. + */ + if (r->length <= sizeof(*r) - offsetof(typeof(*r), data)) + queue_event(client, &response->event, r, sizeof(*r), + r->data, r->length); + else + queue_event(client, &response->event, r, sizeof(*r) + r->length, + NULL, 0); } static int ioctl_send_request(struct client *client, void *buffer) -- cgit v1.2.3 From bf9c8c9ddef7ef761ae9747349175adad0ef16ce Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Fri, 1 Aug 2008 14:58:44 -0500 Subject: ALSA: ASoC: fix SNDCTL_DSP_SYNC support in Freescale 8610 sound drivers If an OSS application calls SNDCTL_DSP_SYNC, then ALSA will call the driver's _hw_params and _prepare functions again. On the Freescale MPC8610 DMA ASoC driver, this caused the DMA controller to be unneccessarily re-programmed, and apparently it doesn't like that. The DMA will then not operate when instructed. This patch relocates much of the DMA programming to fsl_dma_open(), which is called only once. Signed-off-by: Timur Tabi Signed-off-by: Takashi Iwai --- sound/soc/fsl/fsl_dma.c | 235 +++++++++++++++++++++++++----------------------- 1 file changed, 124 insertions(+), 111 deletions(-) diff --git a/sound/soc/fsl/fsl_dma.c b/sound/soc/fsl/fsl_dma.c index 7ceea2bba1f5..d2d3da9729f2 100644 --- a/sound/soc/fsl/fsl_dma.c +++ b/sound/soc/fsl/fsl_dma.c @@ -327,14 +327,75 @@ static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai, * fsl_dma_open: open a new substream. * * Each substream has its own DMA buffer. + * + * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link + * descriptors that ping-pong from one period to the next. For example, if + * there are six periods and two link descriptors, this is how they look + * before playback starts: + * + * The last link descriptor + * ____________ points back to the first + * | | + * V | + * ___ ___ | + * | |->| |->| + * |___| |___| + * | | + * | | + * V V + * _________________________________________ + * | | | | | | | The DMA buffer is + * | | | | | | | divided into 6 parts + * |______|______|______|______|______|______| + * + * and here's how they look after the first period is finished playing: + * + * ____________ + * | | + * V | + * ___ ___ | + * | |->| |->| + * |___| |___| + * | | + * |______________ + * | | + * V V + * _________________________________________ + * | | | | | | | + * | | | | | | | + * |______|______|______|______|______|______| + * + * The first link descriptor now points to the third period. The DMA + * controller is currently playing the second period. When it finishes, it + * will jump back to the first descriptor and play the third period. + * + * There are four reasons we do this: + * + * 1. The only way to get the DMA controller to automatically restart the + * transfer when it gets to the end of the buffer is to use chaining + * mode. Basic direct mode doesn't offer that feature. + * 2. We need to receive an interrupt at the end of every period. The DMA + * controller can generate an interrupt at the end of every link transfer + * (aka segment). Making each period into a DMA segment will give us the + * interrupts we need. + * 3. By creating only two link descriptors, regardless of the number of + * periods, we do not need to reallocate the link descriptors if the + * number of periods changes. + * 4. All of the audio data is still stored in a single, contiguous DMA + * buffer, which is what ALSA expects. We're just dividing it into + * contiguous parts, and creating a link descriptor for each one. */ static int fsl_dma_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; struct fsl_dma_private *dma_private; + struct ccsr_dma_channel __iomem *dma_channel; dma_addr_t ld_buf_phys; + u64 temp_link; /* Pointer to next link descriptor */ + u32 mr; unsigned int channel; int ret = 0; + unsigned int i; /* * Reject any DMA buffer whose size is not a multiple of the period @@ -395,68 +456,74 @@ static int fsl_dma_open(struct snd_pcm_substream *substream) snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware); runtime->private_data = dma_private; + /* Program the fixed DMA controller parameters */ + + dma_channel = dma_private->dma_channel; + + temp_link = dma_private->ld_buf_phys + + sizeof(struct fsl_dma_link_descriptor); + + for (i = 0; i < NUM_DMA_LINKS; i++) { + struct fsl_dma_link_descriptor *link = &dma_private->link[i]; + + link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); + link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); + link->next = cpu_to_be64(temp_link); + + temp_link += sizeof(struct fsl_dma_link_descriptor); + } + /* The last link descriptor points to the first */ + dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); + + /* Tell the DMA controller where the first link descriptor is */ + out_be32(&dma_channel->clndar, + CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); + out_be32(&dma_channel->eclndar, + CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); + + /* The manual says the BCR must be clear before enabling EMP */ + out_be32(&dma_channel->bcr, 0); + + /* + * Program the mode register for interrupts, external master control, + * and source/destination hold. Also clear the Channel Abort bit. + */ + mr = in_be32(&dma_channel->mr) & + ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); + + /* + * We want External Master Start and External Master Pause enabled, + * because the SSI is controlling the DMA controller. We want the DMA + * controller to be set up in advance, and then we signal only the SSI + * to start transferring. + * + * We want End-Of-Segment Interrupts enabled, because this will generate + * an interrupt at the end of each segment (each link descriptor + * represents one segment). Each DMA segment is the same thing as an + * ALSA period, so this is how we get an interrupt at the end of every + * period. + * + * We want Error Interrupt enabled, so that we can get an error if + * the DMA controller is mis-programmed somehow. + */ + mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | + CCSR_DMA_MR_EMS_EN; + + /* For playback, we want the destination address to be held. For + capture, set the source address to be held. */ + mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; + + out_be32(&dma_channel->mr, mr); + return 0; } /** - * fsl_dma_hw_params: allocate the DMA buffer and the DMA link descriptors. - * - * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link - * descriptors that ping-pong from one period to the next. For example, if - * there are six periods and two link descriptors, this is how they look - * before playback starts: - * - * The last link descriptor - * ____________ points back to the first - * | | - * V | - * ___ ___ | - * | |->| |->| - * |___| |___| - * | | - * | | - * V V - * _________________________________________ - * | | | | | | | The DMA buffer is - * | | | | | | | divided into 6 parts - * |______|______|______|______|______|______| - * - * and here's how they look after the first period is finished playing: - * - * ____________ - * | | - * V | - * ___ ___ | - * | |->| |->| - * |___| |___| - * | | - * |______________ - * | | - * V V - * _________________________________________ - * | | | | | | | - * | | | | | | | - * |______|______|______|______|______|______| + * fsl_dma_hw_params: continue initializing the DMA links * - * The first link descriptor now points to the third period. The DMA - * controller is currently playing the second period. When it finishes, it - * will jump back to the first descriptor and play the third period. - * - * There are four reasons we do this: - * - * 1. The only way to get the DMA controller to automatically restart the - * transfer when it gets to the end of the buffer is to use chaining - * mode. Basic direct mode doesn't offer that feature. - * 2. We need to receive an interrupt at the end of every period. The DMA - * controller can generate an interrupt at the end of every link transfer - * (aka segment). Making each period into a DMA segment will give us the - * interrupts we need. - * 3. By creating only two link descriptors, regardless of the number of - * periods, we do not need to reallocate the link descriptors if the - * number of periods changes. - * 4. All of the audio data is still stored in a single, contiguous DMA - * buffer, which is what ALSA expects. We're just dividing it into - * contiguous parts, and creating a link descriptor for each one. + * This function obtains hardware parameters about the opened stream and + * programs the DMA controller accordingly. * * Note that due to a quirk of the SSI's STX register, the target address * for the DMA operations depends on the sample size. So we don't program @@ -468,11 +535,8 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, { struct snd_pcm_runtime *runtime = substream->runtime; struct fsl_dma_private *dma_private = runtime->private_data; - struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel; dma_addr_t temp_addr; /* Pointer to next period */ - u64 temp_link; /* Pointer to next link descriptor */ - u32 mr; /* Temporary variable for MR register */ unsigned int i; @@ -490,8 +554,6 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, dma_private->dma_buf_next = dma_private->dma_buf_phys; /* - * Initialize each link descriptor. - * * The actual address in STX0 (destination for playback, source for * capture) is based on the sample size, but we don't know the sample * size in this function, so we'll have to adjust that later. See @@ -507,16 +569,11 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, * buffer itself. */ temp_addr = substream->dma_buffer.addr; - temp_link = dma_private->ld_buf_phys + - sizeof(struct fsl_dma_link_descriptor); for (i = 0; i < NUM_DMA_LINKS; i++) { struct fsl_dma_link_descriptor *link = &dma_private->link[i]; link->count = cpu_to_be32(period_size); - link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); - link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP); - link->next = cpu_to_be64(temp_link); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) link->source_addr = cpu_to_be32(temp_addr); @@ -524,51 +581,7 @@ static int fsl_dma_hw_params(struct snd_pcm_substream *substream, link->dest_addr = cpu_to_be32(temp_addr); temp_addr += period_size; - temp_link += sizeof(struct fsl_dma_link_descriptor); } - /* The last link descriptor points to the first */ - dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys); - - /* Tell the DMA controller where the first link descriptor is */ - out_be32(&dma_channel->clndar, - CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys)); - out_be32(&dma_channel->eclndar, - CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys)); - - /* The manual says the BCR must be clear before enabling EMP */ - out_be32(&dma_channel->bcr, 0); - - /* - * Program the mode register for interrupts, external master control, - * and source/destination hold. Also clear the Channel Abort bit. - */ - mr = in_be32(&dma_channel->mr) & - ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE); - - /* - * We want External Master Start and External Master Pause enabled, - * because the SSI is controlling the DMA controller. We want the DMA - * controller to be set up in advance, and then we signal only the SSI - * to start transfering. - * - * We want End-Of-Segment Interrupts enabled, because this will generate - * an interrupt at the end of each segment (each link descriptor - * represents one segment). Each DMA segment is the same thing as an - * ALSA period, so this is how we get an interrupt at the end of every - * period. - * - * We want Error Interrupt enabled, so that we can get an error if - * the DMA controller is mis-programmed somehow. - */ - mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | - CCSR_DMA_MR_EMS_EN; - - /* For playback, we want the destination address to be held. For - capture, set the source address to be held. */ - mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? - CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE; - - out_be32(&dma_channel->mr, mr); return 0; } -- cgit v1.2.3 From 9b3cbf725fb98733976fd02e2e557f0ae3028df0 Mon Sep 17 00:00:00 2001 From: Isaku Yamahata Date: Mon, 4 Aug 2008 12:02:28 +0900 Subject: [IA64] pv_ops: fix ivt.S paravirtualization Recent kernels are not booting on some HP systems (though it does boot on others). James and Willy reported the problem. James did the bisection to find the commit that caused the problem: 498c5170472ff0c03a29d22dbd33225a0be038f4. [IA64] pvops: paravirtualize ivt.S Two instructions were wrongly paravirtualized such that _FROM_ macro had been used where _TO_ was intended Cc: James Bottomley Cc: "Wilcox, Matthew R" Signed-off-by: Isaku Yamahata Signed-off-by: Tony Luck --- arch/ia64/kernel/ivt.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S index c39627df3cde..416a952b19bd 100644 --- a/arch/ia64/kernel/ivt.S +++ b/arch/ia64/kernel/ivt.S @@ -1243,11 +1243,11 @@ ENTRY(speculation_vector) add r17=r17,r18 // now add the offset ;; - MOV_FROM_IIP(r17) + MOV_TO_IIP(r17, r19) dep r16=0,r16,41,2 // clear EI ;; - MOV_FROM_IPSR(p0, r16) + MOV_TO_IPSR(p0, r16, r19) ;; RFI -- cgit v1.2.3 From 3f44675439b136d51179d31eb5a498383cb38624 Mon Sep 17 00:00:00 2001 From: Roland Dreier Date: Mon, 4 Aug 2008 11:02:14 -0700 Subject: RDMA/cma: Remove padding arrays by using struct sockaddr_storage There are a few places where the RDMA CM code handles IPv6 by doing struct sockaddr addr; u8 pad[sizeof(struct sockaddr_in6) - sizeof(struct sockaddr)]; This is fragile and ugly; handle this in a better way with just struct sockaddr_storage addr; [ Also roll in patch from Aleksey Senin to switch to struct sockaddr_storage and get rid of padding arrays in struct rdma_addr. ] Signed-off-by: Roland Dreier --- drivers/infiniband/core/cma.c | 37 ++++++++++++++++++------------------- drivers/infiniband/core/ucma.c | 14 ++++++-------- include/rdma/rdma_cm.h | 8 ++------ 3 files changed, 26 insertions(+), 33 deletions(-) diff --git a/drivers/infiniband/core/cma.c b/drivers/infiniband/core/cma.c index e980ff3335db..d951896ff7fc 100644 --- a/drivers/infiniband/core/cma.c +++ b/drivers/infiniband/core/cma.c @@ -155,9 +155,7 @@ struct cma_multicast { } multicast; struct list_head list; void *context; - struct sockaddr addr; - u8 pad[sizeof(struct sockaddr_in6) - - sizeof(struct sockaddr)]; + struct sockaddr_storage addr; }; struct cma_work { @@ -786,8 +784,8 @@ static void cma_cancel_operation(struct rdma_id_private *id_priv, cma_cancel_route(id_priv); break; case CMA_LISTEN: - if (cma_any_addr(&id_priv->id.route.addr.src_addr) && - !id_priv->cma_dev) + if (cma_any_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr) + && !id_priv->cma_dev) cma_cancel_listens(id_priv); break; default: @@ -1026,7 +1024,7 @@ static struct rdma_id_private *cma_new_conn_id(struct rdma_cm_id *listen_id, rt->path_rec[1] = *ib_event->param.req_rcvd.alternate_path; ib_addr_set_dgid(&rt->addr.dev_addr, &rt->path_rec[0].dgid); - ret = rdma_translate_ip(&id->route.addr.src_addr, + ret = rdma_translate_ip((struct sockaddr *) &id->route.addr.src_addr, &id->route.addr.dev_addr); if (ret) goto destroy_id; @@ -1064,7 +1062,7 @@ static struct rdma_id_private *cma_new_udp_id(struct rdma_cm_id *listen_id, cma_save_net_info(&id->route.addr, &listen_id->route.addr, ip_ver, port, src, dst); - ret = rdma_translate_ip(&id->route.addr.src_addr, + ret = rdma_translate_ip((struct sockaddr *) &id->route.addr.src_addr, &id->route.addr.dev_addr); if (ret) goto err; @@ -1377,7 +1375,7 @@ static int cma_ib_listen(struct rdma_id_private *id_priv) if (IS_ERR(id_priv->cm_id.ib)) return PTR_ERR(id_priv->cm_id.ib); - addr = &id_priv->id.route.addr.src_addr; + addr = (struct sockaddr *) &id_priv->id.route.addr.src_addr; svc_id = cma_get_service_id(id_priv->id.ps, addr); if (cma_any_addr(addr)) ret = ib_cm_listen(id_priv->cm_id.ib, svc_id, 0, NULL); @@ -1443,7 +1441,7 @@ static void cma_listen_on_dev(struct rdma_id_private *id_priv, dev_id_priv->state = CMA_ADDR_BOUND; memcpy(&id->route.addr.src_addr, &id_priv->id.route.addr.src_addr, - ip_addr_size(&id_priv->id.route.addr.src_addr)); + ip_addr_size((struct sockaddr *) &id_priv->id.route.addr.src_addr)); cma_attach_to_dev(dev_id_priv, cma_dev); list_add_tail(&dev_id_priv->listen_list, &id_priv->listen_list); @@ -1563,13 +1561,14 @@ static int cma_query_ib_route(struct rdma_id_private *id_priv, int timeout_ms, path_rec.pkey = cpu_to_be16(ib_addr_get_pkey(&addr->dev_addr)); path_rec.numb_path = 1; path_rec.reversible = 1; - path_rec.service_id = cma_get_service_id(id_priv->id.ps, &addr->dst_addr); + path_rec.service_id = cma_get_service_id(id_priv->id.ps, + (struct sockaddr *) &addr->dst_addr); comp_mask = IB_SA_PATH_REC_DGID | IB_SA_PATH_REC_SGID | IB_SA_PATH_REC_PKEY | IB_SA_PATH_REC_NUMB_PATH | IB_SA_PATH_REC_REVERSIBLE | IB_SA_PATH_REC_SERVICE_ID; - if (addr->src_addr.sa_family == AF_INET) { + if (addr->src_addr.ss_family == AF_INET) { path_rec.qos_class = cpu_to_be16((u16) id_priv->tos); comp_mask |= IB_SA_PATH_REC_QOS_CLASS; } else { @@ -1848,7 +1847,7 @@ static int cma_resolve_loopback(struct rdma_id_private *id_priv) ib_addr_get_sgid(&id_priv->id.route.addr.dev_addr, &gid); ib_addr_set_dgid(&id_priv->id.route.addr.dev_addr, &gid); - if (cma_zero_addr(&id_priv->id.route.addr.src_addr)) { + if (cma_zero_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr)) { src_in = (struct sockaddr_in *)&id_priv->id.route.addr.src_addr; dst_in = (struct sockaddr_in *)&id_priv->id.route.addr.dst_addr; src_in->sin_family = dst_in->sin_family; @@ -1897,7 +1896,7 @@ int rdma_resolve_addr(struct rdma_cm_id *id, struct sockaddr *src_addr, if (cma_any_addr(dst_addr)) ret = cma_resolve_loopback(id_priv); else - ret = rdma_resolve_ip(&addr_client, &id->route.addr.src_addr, + ret = rdma_resolve_ip(&addr_client, (struct sockaddr *) &id->route.addr.src_addr, dst_addr, &id->route.addr.dev_addr, timeout_ms, addr_handler, id_priv); if (ret) @@ -2021,11 +2020,11 @@ static int cma_use_port(struct idr *ps, struct rdma_id_private *id_priv) * We don't support binding to any address if anyone is bound to * a specific address on the same port. */ - if (cma_any_addr(&id_priv->id.route.addr.src_addr)) + if (cma_any_addr((struct sockaddr *) &id_priv->id.route.addr.src_addr)) return -EADDRNOTAVAIL; hlist_for_each_entry(cur_id, node, &bind_list->owners, node) { - if (cma_any_addr(&cur_id->id.route.addr.src_addr)) + if (cma_any_addr((struct sockaddr *) &cur_id->id.route.addr.src_addr)) return -EADDRNOTAVAIL; cur_sin = (struct sockaddr_in *) &cur_id->id.route.addr.src_addr; @@ -2060,7 +2059,7 @@ static int cma_get_port(struct rdma_id_private *id_priv) } mutex_lock(&lock); - if (cma_any_port(&id_priv->id.route.addr.src_addr)) + if (cma_any_port((struct sockaddr *) &id_priv->id.route.addr.src_addr)) ret = cma_alloc_any_port(ps, id_priv); else ret = cma_use_port(ps, id_priv); @@ -2232,7 +2231,7 @@ static int cma_resolve_ib_udp(struct rdma_id_private *id_priv, req.path = route->path_rec; req.service_id = cma_get_service_id(id_priv->id.ps, - &route->addr.dst_addr); + (struct sockaddr *) &route->addr.dst_addr); req.timeout_ms = 1 << (CMA_CM_RESPONSE_TIMEOUT - 8); req.max_cm_retries = CMA_MAX_CM_RETRIES; @@ -2283,7 +2282,7 @@ static int cma_connect_ib(struct rdma_id_private *id_priv, req.alternate_path = &route->path_rec[1]; req.service_id = cma_get_service_id(id_priv->id.ps, - &route->addr.dst_addr); + (struct sockaddr *) &route->addr.dst_addr); req.qp_num = id_priv->qp_num; req.qp_type = IB_QPT_RC; req.starting_psn = id_priv->seq_num; @@ -2667,7 +2666,7 @@ static int cma_join_ib_multicast(struct rdma_id_private *id_priv, if (ret) return ret; - cma_set_mgid(id_priv, &mc->addr, &rec.mgid); + cma_set_mgid(id_priv, (struct sockaddr *) &mc->addr, &rec.mgid); if (id_priv->id.ps == RDMA_PS_UDP) rec.qkey = cpu_to_be32(RDMA_UDP_QKEY); ib_addr_get_sgid(dev_addr, &rec.port_gid); diff --git a/drivers/infiniband/core/ucma.c b/drivers/infiniband/core/ucma.c index b41dd26bbfa1..3ddacf39b7ba 100644 --- a/drivers/infiniband/core/ucma.c +++ b/drivers/infiniband/core/ucma.c @@ -81,9 +81,7 @@ struct ucma_multicast { u64 uid; struct list_head list; - struct sockaddr addr; - u8 pad[sizeof(struct sockaddr_in6) - - sizeof(struct sockaddr)]; + struct sockaddr_storage addr; }; struct ucma_event { @@ -603,11 +601,11 @@ static ssize_t ucma_query_route(struct ucma_file *file, return PTR_ERR(ctx); memset(&resp, 0, sizeof resp); - addr = &ctx->cm_id->route.addr.src_addr; + addr = (struct sockaddr *) &ctx->cm_id->route.addr.src_addr; memcpy(&resp.src_addr, addr, addr->sa_family == AF_INET ? sizeof(struct sockaddr_in) : sizeof(struct sockaddr_in6)); - addr = &ctx->cm_id->route.addr.dst_addr; + addr = (struct sockaddr *) &ctx->cm_id->route.addr.dst_addr; memcpy(&resp.dst_addr, addr, addr->sa_family == AF_INET ? sizeof(struct sockaddr_in) : sizeof(struct sockaddr_in6)); @@ -913,7 +911,7 @@ static ssize_t ucma_join_multicast(struct ucma_file *file, mc->uid = cmd.uid; memcpy(&mc->addr, &cmd.addr, sizeof cmd.addr); - ret = rdma_join_multicast(ctx->cm_id, &mc->addr, mc); + ret = rdma_join_multicast(ctx->cm_id, (struct sockaddr *) &mc->addr, mc); if (ret) goto err2; @@ -929,7 +927,7 @@ static ssize_t ucma_join_multicast(struct ucma_file *file, return 0; err3: - rdma_leave_multicast(ctx->cm_id, &mc->addr); + rdma_leave_multicast(ctx->cm_id, (struct sockaddr *) &mc->addr); ucma_cleanup_mc_events(mc); err2: mutex_lock(&mut); @@ -975,7 +973,7 @@ static ssize_t ucma_leave_multicast(struct ucma_file *file, goto out; } - rdma_leave_multicast(mc->ctx->cm_id, &mc->addr); + rdma_leave_multicast(mc->ctx->cm_id, (struct sockaddr *) &mc->addr); mutex_lock(&mc->ctx->file->mut); ucma_cleanup_mc_events(mc); list_del(&mc->list); diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h index df7faf09d66f..c6b2962315b3 100644 --- a/include/rdma/rdma_cm.h +++ b/include/rdma/rdma_cm.h @@ -71,12 +71,8 @@ enum rdma_port_space { }; struct rdma_addr { - struct sockaddr src_addr; - u8 src_pad[sizeof(struct sockaddr_in6) - - sizeof(struct sockaddr)]; - struct sockaddr dst_addr; - u8 dst_pad[sizeof(struct sockaddr_in6) - - sizeof(struct sockaddr)]; + struct sockaddr_storage src_addr; + struct sockaddr_storage dst_addr; struct rdma_dev_addr dev_addr; }; -- cgit v1.2.3 From 5f0f66b022ba607db0a083bf5cc13e4a4336e366 Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Mon, 4 Aug 2008 11:04:42 -0700 Subject: RDMA/cxgb3: Fix QP capabilities - Set the stag0 and fastreg capability bits only for kernel qps. - QP_PRIV flag is no longer used, so don't set it. Signed-off-by: Steve Wise Signed-off-by: Roland Dreier --- drivers/infiniband/hw/cxgb3/iwch_qp.c | 23 +++++++---------------- 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c index 9a3be3a9d5dc..893971612eda 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_qp.c +++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c @@ -879,20 +879,13 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp, (qhp->attr.mpa_attr.xmit_marker_enabled << 1) | (qhp->attr.mpa_attr.crc_enabled << 2); - /* - * XXX - The IWCM doesn't quite handle getting these - * attrs set before going into RTS. For now, just turn - * them on always... - */ -#if 0 - init_attr.qpcaps = qhp->attr.enableRdmaRead | - (qhp->attr.enableRdmaWrite << 1) | - (qhp->attr.enableBind << 2) | - (qhp->attr.enable_stag0_fastreg << 3) | - (qhp->attr.enable_stag0_fastreg << 4); -#else - init_attr.qpcaps = 0x1f; -#endif + init_attr.qpcaps = uP_RI_QP_RDMA_READ_ENABLE | + uP_RI_QP_RDMA_WRITE_ENABLE | + uP_RI_QP_BIND_ENABLE; + if (!qhp->ibqp.uobject) + init_attr.qpcaps |= uP_RI_QP_STAG0_ENABLE | + uP_RI_QP_FAST_REGISTER_ENABLE; + init_attr.tcp_emss = qhp->ep->emss; init_attr.ord = qhp->attr.max_ord; init_attr.ird = qhp->attr.max_ird; @@ -900,8 +893,6 @@ static int rdma_init(struct iwch_dev *rhp, struct iwch_qp *qhp, init_attr.qp_dma_size = (1UL << qhp->wq.size_log2); init_attr.rqe_count = iwch_rqes_posted(qhp); init_attr.flags = qhp->attr.mpa_attr.initiator ? MPA_INITIATOR : 0; - if (!qhp->ibqp.uobject) - init_attr.flags |= PRIV_QP; if (peer2peer) { init_attr.rtr_type = RTR_READ; if (init_attr.ord == 0 && qhp->attr.mpa_attr.initiator) -- cgit v1.2.3 From 1c355a6e80fd08e623416138631e240f431385f2 Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Mon, 4 Aug 2008 11:05:43 -0700 Subject: RDMA/cxgb3: Fix up MW access rights - MWs don't have local read/write permissions. - Set the MW_BIND enabled bit if a MR has MW_BIND access. Signed-off-by: Steve Wise Signed-off-by: Roland Dreier --- drivers/infiniband/hw/cxgb3/cxio_hal.c | 6 +++--- drivers/infiniband/hw/cxgb3/iwch_provider.h | 7 +++++++ drivers/infiniband/hw/cxgb3/iwch_qp.c | 2 +- 3 files changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/infiniband/hw/cxgb3/cxio_hal.c b/drivers/infiniband/hw/cxgb3/cxio_hal.c index f6d5747153a5..4dcf08b3fd83 100644 --- a/drivers/infiniband/hw/cxgb3/cxio_hal.c +++ b/drivers/infiniband/hw/cxgb3/cxio_hal.c @@ -725,9 +725,9 @@ static int __cxio_tpt_op(struct cxio_rdev *rdev_p, u32 reset_tpt_entry, V_TPT_STAG_TYPE(type) | V_TPT_PDID(pdid)); BUG_ON(page_size >= 28); tpt.flags_pagesize_qpid = cpu_to_be32(V_TPT_PERM(perm) | - F_TPT_MW_BIND_ENABLE | - V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) | - V_TPT_PAGE_SIZE(page_size)); + ((perm & TPT_MW_BIND) ? F_TPT_MW_BIND_ENABLE : 0) | + V_TPT_ADDR_TYPE((zbva ? TPT_ZBTO : TPT_VATO)) | + V_TPT_PAGE_SIZE(page_size)); tpt.rsvd_pbl_addr = reset_tpt_entry ? 0 : cpu_to_be32(V_TPT_PBL_ADDR(PBL_OFF(rdev_p, pbl_addr)>>3)); tpt.len = cpu_to_be32(len); diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.h b/drivers/infiniband/hw/cxgb3/iwch_provider.h index f5ceca05c435..a237d49bdcc9 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.h +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.h @@ -293,9 +293,16 @@ static inline u32 iwch_ib_to_tpt_access(int acc) return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) | (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0) | (acc & IB_ACCESS_LOCAL_WRITE ? TPT_LOCAL_WRITE : 0) | + (acc & IB_ACCESS_MW_BIND ? TPT_MW_BIND : 0) | TPT_LOCAL_READ; } +static inline u32 iwch_ib_to_tpt_bind_access(int acc) +{ + return (acc & IB_ACCESS_REMOTE_WRITE ? TPT_REMOTE_WRITE : 0) | + (acc & IB_ACCESS_REMOTE_READ ? TPT_REMOTE_READ : 0); +} + enum iwch_mmid_state { IWCH_STAG_STATE_VALID, IWCH_STAG_STATE_INVALID diff --git a/drivers/infiniband/hw/cxgb3/iwch_qp.c b/drivers/infiniband/hw/cxgb3/iwch_qp.c index 893971612eda..3e4585c2318a 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_qp.c +++ b/drivers/infiniband/hw/cxgb3/iwch_qp.c @@ -565,7 +565,7 @@ int iwch_bind_mw(struct ib_qp *qp, wqe->bind.type = TPT_VATO; /* TBD: check perms */ - wqe->bind.perms = iwch_ib_to_tpt_access(mw_bind->mw_access_flags); + wqe->bind.perms = iwch_ib_to_tpt_bind_access(mw_bind->mw_access_flags); wqe->bind.mr_stag = cpu_to_be32(mw_bind->mr->lkey); wqe->bind.mw_stag = cpu_to_be32(mw->rkey); wqe->bind.mw_len = cpu_to_be32(mw_bind->length); -- cgit v1.2.3 From 94567ef16bf38e98a7de214694d327feb3ec42d4 Mon Sep 17 00:00:00 2001 From: Robin Holt Date: Mon, 4 Aug 2008 11:06:16 -0700 Subject: [IA64] Cleanup generated file not ignored by .gitignore arch/ia64/kernel/vmlinux.lds is a generated file. Tell git to ignore it. Signed-off-by: Robin Holt Signed-off-by: Tony Luck --- arch/ia64/kernel/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/ia64/kernel/.gitignore b/arch/ia64/kernel/.gitignore index 98307759a3b8..21cb0da5ded8 100644 --- a/arch/ia64/kernel/.gitignore +++ b/arch/ia64/kernel/.gitignore @@ -1 +1,2 @@ gate.lds +vmlinux.lds -- cgit v1.2.3 From be43324d8b316fe83a7b4027334f2825f1121c2c Mon Sep 17 00:00:00 2001 From: Steve Wise Date: Mon, 4 Aug 2008 11:08:37 -0700 Subject: RDMA/cxgb3: Fix deadlock initializing iw_cxgb3 device Running 'ifconfig up' on the cxgb3 interface with iw_cxgb3 loaded causes a deadlock. The rtnl lock is already held in this path. The function fw_supports_fastreg() was introduced in 2.6.27 to conditionally set the IB_DEVICE_MEM_MGT_EXTENSIONS bit iff the firmware was at 7.0 or greater, and this function also acquires the rtnl lock and which thus causes a deadlock. Further, if iw_cxgb3 is loaded _after_ the nic interface is brought up, then the deadlock does not occur and therefore fw_supports_fastreg() does need to grab the rtnl lock in that path. It turns out this code is all useless anyway. The low level driver will NOT allow the open if the firmware isn't 7.0, so iw_cxgb3 can always set the MEM_MGT_EXTENSIONS bit. Simplify... Signed-off-by: Steve Wise Signed-off-by: Roland Dreier --- drivers/infiniband/hw/cxgb3/iwch_provider.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/drivers/infiniband/hw/cxgb3/iwch_provider.c b/drivers/infiniband/hw/cxgb3/iwch_provider.c index b89640aa6e10..eb778bfd6f66 100644 --- a/drivers/infiniband/hw/cxgb3/iwch_provider.c +++ b/drivers/infiniband/hw/cxgb3/iwch_provider.c @@ -1187,28 +1187,6 @@ static ssize_t show_rev(struct device *dev, struct device_attribute *attr, return sprintf(buf, "%d\n", iwch_dev->rdev.t3cdev_p->type); } -static int fw_supports_fastreg(struct iwch_dev *iwch_dev) -{ - struct ethtool_drvinfo info; - struct net_device *lldev = iwch_dev->rdev.t3cdev_p->lldev; - char *cp, *next; - unsigned fw_maj, fw_min; - - rtnl_lock(); - lldev->ethtool_ops->get_drvinfo(lldev, &info); - rtnl_unlock(); - - next = info.fw_version+1; - cp = strsep(&next, "."); - sscanf(cp, "%i", &fw_maj); - cp = strsep(&next, "."); - sscanf(cp, "%i", &fw_min); - - PDBG("%s maj %u min %u\n", __func__, fw_maj, fw_min); - - return fw_maj > 6 || (fw_maj == 6 && fw_min > 0); -} - static ssize_t show_fw_ver(struct device *dev, struct device_attribute *attr, char *buf) { struct iwch_dev *iwch_dev = container_of(dev, struct iwch_dev, @@ -1325,12 +1303,12 @@ int iwch_register_device(struct iwch_dev *dev) memset(&dev->ibdev.node_guid, 0, sizeof(dev->ibdev.node_guid)); memcpy(&dev->ibdev.node_guid, dev->rdev.t3cdev_p->lldev->dev_addr, 6); dev->ibdev.owner = THIS_MODULE; - dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | IB_DEVICE_MEM_WINDOW; + dev->device_cap_flags = IB_DEVICE_LOCAL_DMA_LKEY | + IB_DEVICE_MEM_WINDOW | + IB_DEVICE_MEM_MGT_EXTENSIONS; /* cxgb3 supports STag 0. */ dev->ibdev.local_dma_lkey = 0; - if (fw_supports_fastreg(dev)) - dev->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; dev->ibdev.uverbs_cmd_mask = (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | -- cgit v1.2.3 From d1339df1f46d10e0396c1470f371b0d1b23295ba Mon Sep 17 00:00:00 2001 From: Robin Holt Date: Sat, 2 Aug 2008 13:29:24 -0500 Subject: [IA64] Allow ia64 to CONFIG_NR_CPUS up to 4096 ia64 has compiled with NR_CPUS=4096 for a couple releases, just forgot to update Kconfig to allow it. Signed-off-by: Robin Holt Signed-off-by: Tony Luck --- arch/ia64/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 451f2ffb137b..977895893ed5 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -321,10 +321,10 @@ config SMP If you don't know what to do here, say N. config NR_CPUS - int "Maximum number of CPUs (2-1024)" - range 2 1024 + int "Maximum number of CPUs (2-4096)" + range 2 4096 depends on SMP - default "1024" + default "4096" help You should set this to the number of CPUs in your system, but keep in mind that a kernel compiled for, e.g., 2 CPUs will boot but -- cgit v1.2.3 From ac0af91ebcaedc1a9e1d2987ecbd22837924e6b9 Mon Sep 17 00:00:00 2001 From: Robin Holt Date: Sat, 2 Aug 2008 13:32:06 -0500 Subject: [IA64] update generic_defconfig for 2.6.27-rc1 This patch updates the generic_defconfig for 2.6.27-rc1 by simply doing a make oldconfig and holding down the carriage return. Signed-off-by: Robin Holt Signed-off-by: Tony Luck --- arch/ia64/configs/generic_defconfig | 503 +++++++++++++++++++++--------------- 1 file changed, 293 insertions(+), 210 deletions(-) diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index 0210545e7f61..3ad1a464fd41 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig @@ -1,20 +1,16 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.22 -# Thu Jul 19 13:55:32 2007 +# Linux kernel version: 2.6.27-rc1 +# Fri Aug 1 19:33:14 2008 # CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y @@ -23,20 +19,27 @@ CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_USER_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=20 -# CONFIG_CPUSETS is not set +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +# CONFIG_USER_NS is not set +# CONFIG_PID_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set @@ -44,6 +47,7 @@ CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y @@ -53,12 +57,30 @@ CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y @@ -68,6 +90,8 @@ CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y # # IO Schedulers @@ -81,6 +105,7 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # # Processor type and features @@ -91,12 +116,16 @@ CONFIG_ZONE_DMA=y CONFIG_QUICKLIST=y CONFIG_MMU=y CONFIG_SWIOTLB=y +CONFIG_IOMMU_HELPER=y CONFIG_RWSEM_XCHGADD_ALGORITHM=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_HUGETLB_PAGE_SIZE_VARIABLE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_DMI=y CONFIG_EFI=y CONFIG_GENERIC_IOMAP=y @@ -107,6 +136,7 @@ CONFIG_IA64_GENERIC=y # CONFIG_IA64_HP_ZX1 is not set # CONFIG_IA64_HP_ZX1_SWIOTLB is not set # CONFIG_IA64_SGI_SN2 is not set +# CONFIG_IA64_SGI_UV is not set # CONFIG_IA64_HP_SIM is not set # CONFIG_ITANIUM is not set CONFIG_MCKINLEY=y @@ -116,22 +146,26 @@ CONFIG_MCKINLEY=y CONFIG_IA64_PAGE_SIZE_64KB=y CONFIG_PGTABLE_3=y # CONFIG_PGTABLE_4 is not set +CONFIG_HZ=250 # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set # CONFIG_HZ_1000 is not set -CONFIG_HZ=250 +# CONFIG_SCHED_HRTICK is not set CONFIG_IA64_L1_CACHE_SHIFT=7 CONFIG_IA64_CYCLONE=y CONFIG_IOSAPIC=y -# CONFIG_IA64_SGI_SN_XP is not set CONFIG_FORCE_MAX_ZONEORDER=17 +# CONFIG_VIRT_CPU_ACCOUNTING is not set CONFIG_SMP=y CONFIG_NR_CPUS=512 CONFIG_HOTPLUG_CPU=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y # CONFIG_SCHED_SMT is not set # CONFIG_PERMIT_BSP_REMOVE is not set +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set @@ -141,6 +175,8 @@ CONFIG_DISCONTIGMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_NEED_MULTIPLE_NODES=y # CONFIG_SPARSEMEM_STATIC is not set +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_MIGRATION=y CONFIG_RESOURCES_64BIT=y @@ -148,6 +184,7 @@ CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_NR_QUICK=1 CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_DISCONTIGMEM_ENABLE=y CONFIG_ARCH_FLATMEM_ENABLE=y @@ -162,12 +199,14 @@ CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID=y CONFIG_HAVE_ARCH_NODEDATA_EXTENSION=y CONFIG_IA32_SUPPORT=y CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y CONFIG_IA64_MCA_RECOVERY=y CONFIG_PERFMON=y CONFIG_IA64_PALINFO=y # CONFIG_IA64_MC_ERR_INJECT is not set CONFIG_SGI_SN=y # CONFIG_IA64_ESI is not set +# CONFIG_IA64_HP_AML_NFW is not set # # SN Devices @@ -179,6 +218,7 @@ CONFIG_CRASH_DUMP=y # # Firmware Drivers # +# CONFIG_FIRMWARE_MEMMAP is not set CONFIG_EFI_VARS=y CONFIG_EFI_PCDP=y CONFIG_DMIID=y @@ -189,14 +229,12 @@ CONFIG_BINFMT_MISC=m # Power management and ACPI # CONFIG_PM=y -CONFIG_PM_LEGACY=y # CONFIG_PM_DEBUG is not set - -# -# ACPI (Advanced Configuration and Power Interface) Support -# CONFIG_ACPI=y CONFIG_ACPI_PROCFS=y +CONFIG_ACPI_PROCFS_POWER=y +CONFIG_ACPI_SYSFS_POWER=y +CONFIG_ACPI_PROC_EVENT=y CONFIG_ACPI_BUTTON=m CONFIG_ACPI_FAN=m # CONFIG_ACPI_DOCK is not set @@ -204,9 +242,11 @@ CONFIG_ACPI_PROCESSOR=m CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=m CONFIG_ACPI_NUMA=y +# CONFIG_ACPI_CUSTOM_DSDT is not set CONFIG_ACPI_BLACKLIST_YEAR=0 # CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_EC=y +# CONFIG_ACPI_PCI_SLOT is not set CONFIG_ACPI_POWER=y CONFIG_ACPI_SYSTEM=y CONFIG_ACPI_CONTAINER=m @@ -225,6 +265,7 @@ CONFIG_PCI_SYSCALL=y # CONFIG_PCIEPORTBUS is not set CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set +CONFIG_PCI_LEGACY=y # CONFIG_PCI_DEBUG is not set CONFIG_HOTPLUG_PCI=m # CONFIG_HOTPLUG_PCI_FAKE is not set @@ -233,15 +274,7 @@ CONFIG_HOTPLUG_PCI_ACPI=m # CONFIG_HOTPLUG_PCI_CPCI is not set # CONFIG_HOTPLUG_PCI_SHPC is not set # CONFIG_HOTPLUG_PCI_SGI is not set - -# -# PCCARD (PCMCIA/CardBus) support -# # CONFIG_PCCARD is not set - -# -# Networking -# CONFIG_NET=y # @@ -254,6 +287,7 @@ CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y @@ -273,6 +307,7 @@ CONFIG_SYN_COOKIES=y CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=m CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set @@ -280,8 +315,6 @@ CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set @@ -298,10 +331,6 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set # @@ -309,6 +338,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set @@ -330,9 +360,12 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set @@ -360,25 +393,35 @@ CONFIG_BLK_DEV_NBD=m CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_SGI_IOC4=y # CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_SGI_XP is not set +# CONFIG_HP_ILO is not set +CONFIG_SGI_GRU=m +# CONFIG_SGI_GRU_DEBUG is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # +CONFIG_IDE_TIMINGS=y +CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=y # CONFIG_IDEDISK_MULTI_MODE is not set CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set CONFIG_BLK_DEV_IDEFLOPPY=y CONFIG_BLK_DEV_IDESCSI=m @@ -390,25 +433,26 @@ CONFIG_IDE_PROC_FS=y # IDE chipset support/bugfixes # # CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set # CONFIG_BLK_DEV_IDEPNP is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_SHARE_IRQ=y CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_ONLYDISK is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_BLK_DEV_AMD74XX is not set CONFIG_BLK_DEV_CMD64X=y # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -425,10 +469,7 @@ CONFIG_BLK_DEV_SGIIOC4=y # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set # CONFIG_BLK_DEV_TC86C001 is not set -# CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support @@ -468,10 +509,8 @@ CONFIG_SCSI_FC_ATTRS=y # CONFIG_SCSI_ISCSI_ATTRS is not set CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set @@ -481,6 +520,8 @@ CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set +# CONFIG_SCSI_DPT_I2O is not set +# CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set @@ -491,6 +532,7 @@ CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set +# CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_STEX is not set CONFIG_SCSI_SYM53C8XX_2=y CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 @@ -505,6 +547,7 @@ CONFIG_SCSI_QLOGIC_1280=y # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m @@ -522,36 +565,52 @@ CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m -# CONFIG_DM_MULTIPATH_EMC is not set -# CONFIG_DM_MULTIPATH_RDAC is not set # CONFIG_DM_DELAY is not set - -# -# Fusion MPT device support -# +# CONFIG_DM_UEVENT is not set CONFIG_FUSION=y CONFIG_FUSION_SPI=y CONFIG_FUSION_FC=m CONFIG_FUSION_SAS=y CONFIG_FUSION_MAX_SGE=128 # CONFIG_FUSION_CTL is not set +# CONFIG_FUSION_LOGGING is not set # # IEEE 1394 (FireWire) support # + +# +# Enable only one of the two stacks, unless you know what you are doing +# # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set CONFIG_DUMMY=m # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set +# CONFIG_VETH is not set # CONFIG_NET_SB1000 is not set # CONFIG_ARCNET is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_HAPPYMEAL is not set @@ -569,13 +628,16 @@ CONFIG_TULIP=m # CONFIG_DM9102 is not set # CONFIG_ULI526X is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set # CONFIG_ADAPTEC_STARFIRE is not set # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set -# CONFIG_DGRS is not set CONFIG_EEPRO100=m CONFIG_E100=m # CONFIG_FEALNX is not set @@ -583,17 +645,21 @@ CONFIG_E100=m # CONFIG_NE2K_PCI is not set # CONFIG_8139CP is not set # CONFIG_8139TOO is not set +# CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set # CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set CONFIG_E1000=y -# CONFIG_E1000_NAPI is not set # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -606,14 +672,20 @@ CONFIG_TIGON3=y # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set # CONFIG_CHELSIO_T3 is not set +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set # CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set # CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # @@ -621,6 +693,7 @@ CONFIG_NETDEV_10000=y # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # # USB Network Adapters @@ -629,7 +702,6 @@ CONFIG_NETDEV_10000=y # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET_MII is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set @@ -637,8 +709,8 @@ CONFIG_NETDEV_10000=y # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set -# CONFIG_SHAPER is not set CONFIG_NETCONSOLE=y +# CONFIG_NETCONSOLE_DYNAMIC is not set CONFIG_NETPOLL=y # CONFIG_NETPOLL_TRAP is not set CONFIG_NET_POLL_CONTROLLER=y @@ -660,7 +732,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set @@ -709,9 +780,11 @@ CONFIG_GAMEPORT=m # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_COMPUTONE is not set # CONFIG_ROCKETPORT is not set @@ -719,15 +792,16 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_DIGIEPCA is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set -# CONFIG_MOXA_SMARTIO_NEW is not set # CONFIG_ISI is not set # CONFIG_SYNCLINKMP is not set # CONFIG_SYNCLINK_GT is not set # CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set +# CONFIG_NOZOMI is not set CONFIG_SGI_SNSC=y CONFIG_SGI_TIOCX=y CONFIG_SGI_MBCS=m @@ -759,76 +833,100 @@ CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set CONFIG_EFI_RTC=y # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -CONFIG_AGP=m -CONFIG_AGP_I460=m -CONFIG_AGP_HP_ZX1=m -CONFIG_AGP_SGI_TIOCA=m -CONFIG_DRM=m -CONFIG_DRM_TDFX=m -CONFIG_DRM_R128=m -CONFIG_DRM_RADEON=m -CONFIG_DRM_MGA=m -CONFIG_DRM_SIS=m -# CONFIG_DRM_VIA is not set -# CONFIG_DRM_SAVAGE is not set CONFIG_RAW_DRIVER=m CONFIG_MAX_RAW_DEVS=256 CONFIG_HPET=y -# CONFIG_HPET_RTC_IRQ is not set CONFIG_HPET_MMAP=y # CONFIG_HANGCHECK_TIMER is not set CONFIG_MMTIMER=y # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set - -# -# SPI support -# # CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set # CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_BATTERY_DS2760 is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set -# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set # CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_THERMAL=m +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set + +# +# Sonics Silicon Backplane +# +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# CONFIG_DAB=y # CONFIG_USB_DABUSB is not set # # Graphics support # +CONFIG_AGP=m +CONFIG_AGP_I460=m +CONFIG_AGP_HP_ZX1=m +CONFIG_AGP_SGI_TIOCA=m +CONFIG_DRM=m +CONFIG_DRM_TDFX=m +CONFIG_DRM_R128=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_MGA=m +CONFIG_DRM_SIS=m +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set -# CONFIG_VGASTATE is not set -# CONFIG_FB is not set # # Console display driver support @@ -836,15 +934,7 @@ CONFIG_DAB=y CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y - -# -# Sound -# CONFIG_SOUND=m - -# -# Advanced Linux Sound Architecture -# CONFIG_SND=m CONFIG_SND_TIMER=m CONFIG_SND_PCM=m @@ -862,22 +952,18 @@ CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y CONFIG_SND_VERBOSE_PRINTK=y # CONFIG_SND_DEBUG is not set - -# -# Generic devices -# +CONFIG_SND_VMASTER=y CONFIG_SND_MPU401_UART=m CONFIG_SND_OPL3_LIB=m CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y CONFIG_SND_DUMMY=m CONFIG_SND_VIRMIDI=m CONFIG_SND_MTPAV=m CONFIG_SND_SERIAL_U16550=m CONFIG_SND_MPU401=m - -# -# PCI devices -# +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALI5451 is not set @@ -886,10 +972,12 @@ CONFIG_SND_MPU401=m # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set # CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set CONFIG_SND_CS4281=m CONFIG_SND_CS46XX=m CONFIG_SND_CS46XX_NEW_DSP=y @@ -912,10 +1000,10 @@ CONFIG_SND_EMU10K1=m # CONFIG_SND_ES1938 is not set # CONFIG_SND_ES1968 is not set CONFIG_SND_FM801=m -# CONFIG_SND_FM801_TEA575X_BOOL is not set # CONFIG_SND_HDA_INTEL is not set # CONFIG_SND_HDSP is not set # CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set # CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1724 is not set # CONFIG_SND_INTEL8X0 is not set @@ -933,29 +1021,19 @@ CONFIG_SND_FM801=m # CONFIG_SND_TRIDENT is not set # CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set -# CONFIG_SND_AC97_POWER_SAVE is not set - -# -# USB devices -# +CONFIG_SND_USB=y # CONFIG_SND_USB_AUDIO is not set # CONFIG_SND_USB_CAIAQ is not set - -# -# System on Chip audio support -# # CONFIG_SND_SOC is not set - -# -# Open Sound System -# # CONFIG_SOUND_PRIME is not set CONFIG_AC97_BUS=m CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set # # USB Input Devices @@ -976,6 +1054,7 @@ CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options @@ -984,17 +1063,17 @@ CONFIG_USB_DEVICEFS=y CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set -# CONFIG_USB_PERSIST is not set # CONFIG_USB_OTG is not set # # USB Host Controller Drivers # +# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_EHCI_HCD=m -# CONFIG_USB_EHCI_SPLIT_ISO is not set # CONFIG_USB_EHCI_ROOT_HUB_TT is not set # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set @@ -1008,6 +1087,7 @@ CONFIG_USB_UHCI_HCD=m # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' @@ -1027,7 +1107,9 @@ CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # @@ -1040,10 +1122,6 @@ CONFIG_USB_MON=y # # USB port drivers # - -# -# USB Serial Converter support -# # CONFIG_USB_SERIAL is not set # @@ -1069,65 +1147,30 @@ CONFIG_USB_MON=y # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set - -# -# USB DSL modem support -# - -# -# USB Gadget Support -# +# CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_GADGET is not set # CONFIG_MMC is not set - -# -# LED devices -# +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# +# CONFIG_ACCESSIBILITY is not set CONFIG_INFINIBAND=m # CONFIG_INFINIBAND_USER_MAD is not set # CONFIG_INFINIBAND_USER_ACCESS is not set CONFIG_INFINIBAND_ADDR_TRANS=y CONFIG_INFINIBAND_MTHCA=m CONFIG_INFINIBAND_MTHCA_DEBUG=y +# CONFIG_INFINIBAND_IPATH is not set # CONFIG_INFINIBAND_AMSO1100 is not set # CONFIG_MLX4_INFINIBAND is not set +# CONFIG_INFINIBAND_NES is not set CONFIG_INFINIBAND_IPOIB=m # CONFIG_INFINIBAND_IPOIB_CM is not set CONFIG_INFINIBAND_IPOIB_DEBUG=y # CONFIG_INFINIBAND_IPOIB_DEBUG_DATA is not set # CONFIG_INFINIBAND_SRP is not set # CONFIG_INFINIBAND_ISER is not set - -# -# Real Time Clock -# # CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Userspace I/O -# +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set # CONFIG_MSPEC is not set @@ -1145,7 +1188,6 @@ CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=y # CONFIG_REISERFS_CHECK is not set @@ -1157,17 +1199,15 @@ CONFIG_REISERFS_FS_SECURITY=y CONFIG_FS_POSIX_ACL=y CONFIG_XFS_FS=y # CONFIG_XFS_QUOTA is not set -# CONFIG_XFS_SECURITY is not set # CONFIG_XFS_POSIX_ACL is not set # CONFIG_XFS_RT is not set +# CONFIG_XFS_DEBUG is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=y CONFIG_AUTOFS4_FS=y # CONFIG_FUSE_FS is not set @@ -1205,7 +1245,6 @@ CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y -CONFIG_RAMFS=y # CONFIG_CONFIGFS_FS is not set # @@ -1220,32 +1259,30 @@ CONFIG_RAMFS=y # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=m CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set CONFIG_NFS_V4=y -CONFIG_NFS_DIRECTIO=y CONFIG_NFSD=m CONFIG_NFSD_V3=y # CONFIG_NFSD_V3_ACL is not set CONFIG_NFSD_V4=y -CONFIG_NFSD_TCP=y CONFIG_LOCKD=m CONFIG_LOCKD_V4=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y CONFIG_SUNRPC=m CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_BIND34 is not set -CONFIG_RPCSEC_GSS_KRB5=y +CONFIG_SUNRPC_XPRT_RDMA=m +CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPCSEC_GSS_SPKM3 is not set CONFIG_SMB_FS=m CONFIG_SMB_NLS_DEFAULT=y @@ -1281,10 +1318,6 @@ CONFIG_SGI_PARTITION=y # CONFIG_KARMA_PARTITION is not set CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -1325,19 +1358,20 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# # CONFIG_DLM is not set +CONFIG_HAVE_KVM=y +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set # # Library routines # CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set -# CONFIG_CRC_ITU_T is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set @@ -1357,17 +1391,13 @@ CONFIG_IRQ_PER_CPU=y # CONFIG_HP_SIMSERIAL is not set # CONFIG_HP_SIMSCSI is not set -# -# Instrumentation Support -# -# CONFIG_PROFILING is not set -# CONFIG_KPROBES is not set - # # Kernel hacking # # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set @@ -1375,10 +1405,14 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 CONFIG_SCHED_DEBUG=y # CONFIG_SCHEDSTATS is not set # CONFIG_TIMER_STATS is not set -# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set @@ -1388,10 +1422,15 @@ CONFIG_DEBUG_MUTEXES=y # CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set -CONFIG_FORCED_INLINING=y +# CONFIG_DEBUG_SG is not set +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_FAULT_INJECTION is not set +# CONFIG_SAMPLES is not set CONFIG_IA64_GRANULE_16MB=y # CONFIG_IA64_GRANULE_64MB is not set # CONFIG_IA64_PRINT_HAZARDS is not set @@ -1405,41 +1444,85 @@ CONFIG_SYSVIPC_COMPAT=y # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set CONFIG_CRYPTO=y + +# +# Crypto core or helper +# CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_MANAGER=m +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# # CONFIG_CRYPTO_HMAC is not set # CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_NULL is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_GF128MUL is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_DES=m -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# # CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_ARC4 is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# # CONFIG_CRYPTO_DEFLATE is not set -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_LZO is not set CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set -- cgit v1.2.3 From 70117b9e866b1fdf7e4e84ffb6f38a7b3e9702f8 Mon Sep 17 00:00:00 2001 From: Alexander Beregalov Date: Mon, 4 Aug 2008 11:12:18 -0700 Subject: IB/ipath: Fix printk format warnings ipath_driver.c:1260: warning: format '%Lx' expects type 'long long unsigned int', but argument 6 has type 'long unsigned int' ipath_driver.c:1459: warning: format '%Lx' expects type 'long long unsigned int', but argument 4 has type 'u64' ipath_intr.c:358: warning: format '%Lx' expects type 'long long unsigned int', but argument 3 has type 'u64' ipath_intr.c:358: warning: format '%Lu' expects type 'long long unsigned int', but argument 6 has type 'u64' ipath_intr.c:1119: warning: format '%Lx' expects type 'long long unsigned int', but argument 5 has type 'u64' ipath_intr.c:1119: warning: format '%Lx' expects type 'long long unsigned int', but argument 3 has type 'u64' ipath_intr.c:1123: warning: format '%Lx' expects type 'long long unsigned int', but argument 3 has type 'u64' ipath_intr.c:1130: warning: format '%Lx' expects type 'long long unsigned int', but argument 4 has type 'u64' ipath_iba7220.c:1032: warning: format '%llx' expects type 'long long unsigned int', but argument 4 has type 'u64' ipath_iba7220.c:1045: warning: format '%llX' expects type 'long long unsigned int', but argument 3 has type 'u64' ipath_iba7220.c:2506: warning: format '%Lu' expects type 'long long unsigned int', but argument 4 has type 'u64' Signed-off-by: Alexander Beregalov Cc: Sean Hefty Cc: Hal Rosenstock Signed-off-by: Roland Dreier --- drivers/infiniband/hw/ipath/ipath_driver.c | 5 +++-- drivers/infiniband/hw/ipath/ipath_iba7220.c | 7 ++++--- drivers/infiniband/hw/ipath/ipath_intr.c | 12 ++++++++---- 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/infiniband/hw/ipath/ipath_driver.c b/drivers/infiniband/hw/ipath/ipath_driver.c index daad09a45910..ad0aab60b051 100644 --- a/drivers/infiniband/hw/ipath/ipath_driver.c +++ b/drivers/infiniband/hw/ipath/ipath_driver.c @@ -1259,7 +1259,7 @@ reloop: */ ipath_cdbg(ERRPKT, "Error Pkt, but no eflags! egrbuf" " %x, len %x hdrq+%x rhf: %Lx\n", - etail, tlen, l, + etail, tlen, l, (unsigned long long) le64_to_cpu(*(__le64 *) rhf_addr)); if (ipath_debug & __IPATH_ERRPKTDBG) { u32 j, *d, dw = rsize-2; @@ -1457,7 +1457,8 @@ static void ipath_reset_availshadow(struct ipath_devdata *dd) 0xaaaaaaaaaaaaaaaaULL); /* All BUSY bits in qword */ if (oldval != dd->ipath_pioavailshadow[i]) ipath_dbg("shadow[%d] was %Lx, now %lx\n", - i, oldval, dd->ipath_pioavailshadow[i]); + i, (unsigned long long) oldval, + dd->ipath_pioavailshadow[i]); } spin_unlock_irqrestore(&ipath_pioavail_lock, flags); } diff --git a/drivers/infiniband/hw/ipath/ipath_iba7220.c b/drivers/infiniband/hw/ipath/ipath_iba7220.c index fb70712ac85c..85b2cd03c4e4 100644 --- a/drivers/infiniband/hw/ipath/ipath_iba7220.c +++ b/drivers/infiniband/hw/ipath/ipath_iba7220.c @@ -1032,7 +1032,7 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd) ipath_cdbg(VERBOSE, "done: xgxs=%llx from %llx\n", (unsigned long long) ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig), - prev_val); + (unsigned long long) prev_val); guid = be64_to_cpu(dd->ipath_guid); @@ -1042,7 +1042,8 @@ static int ipath_7220_bringup_serdes(struct ipath_devdata *dd) ipath_dbg("No GUID for heartbeat, faking %llx\n", (unsigned long long)guid); } else - ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", guid); + ipath_cdbg(VERBOSE, "Wrote %llX to HRTBT_GUID\n", + (unsigned long long) guid); ipath_write_kreg(dd, dd->ipath_kregs->kr_hrtbt_guid, guid); return ret; } @@ -2505,7 +2506,7 @@ done: if (dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) { ipath_dbg("Did not get to DDR INIT (%x) after %Lu msecs\n", ipath_ib_state(dd, dd->ipath_lastibcstat), - jiffies_to_msecs(jiffies)-startms); + (unsigned long long) jiffies_to_msecs(jiffies)-startms); dd->ipath_flags &= ~IPATH_IB_AUTONEG_INPROG; if (dd->ipath_autoneg_tries == IPATH_AUTONEG_TRIES) { dd->ipath_flags |= IPATH_IB_AUTONEG_FAILED; diff --git a/drivers/infiniband/hw/ipath/ipath_intr.c b/drivers/infiniband/hw/ipath/ipath_intr.c index 26900b3b7a4e..6c21b4b5ec71 100644 --- a/drivers/infiniband/hw/ipath/ipath_intr.c +++ b/drivers/infiniband/hw/ipath/ipath_intr.c @@ -356,9 +356,10 @@ static void handle_e_ibstatuschanged(struct ipath_devdata *dd, dd->ipath_cregs->cr_iblinkerrrecovcnt); if (linkrecov != dd->ipath_lastlinkrecov) { ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n", - ibcs, ib_linkstate(dd, ibcs), + (unsigned long long) ibcs, + ib_linkstate(dd, ibcs), ipath_ibcstatus_str[ltstate], - linkrecov); + (unsigned long long) linkrecov); /* and no more until active again */ dd->ipath_lastlinkrecov = 0; ipath_set_linkstate(dd, IPATH_IB_LINKDOWN); @@ -1118,9 +1119,11 @@ irqreturn_t ipath_intr(int irq, void *data) if (unlikely(istat & ~dd->ipath_i_bitsextant)) ipath_dev_err(dd, "interrupt with unknown interrupts %Lx set\n", + (unsigned long long) istat & ~dd->ipath_i_bitsextant); else if (istat & ~INFINIPATH_I_ERROR) /* errors do own printing */ - ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", istat); + ipath_cdbg(VERBOSE, "intr stat=0x%Lx\n", + (unsigned long long) istat); if (istat & INFINIPATH_I_ERROR) { ipath_stats.sps_errints++; @@ -1128,7 +1131,8 @@ irqreturn_t ipath_intr(int irq, void *data) dd->ipath_kregs->kr_errorstatus); if (!estat) dev_info(&dd->pcidev->dev, "error interrupt (%Lx), " - "but no error bits set!\n", istat); + "but no error bits set!\n", + (unsigned long long) istat); else if (estat == -1LL) /* * should we try clearing all, or hope next read -- cgit v1.2.3 From ceffacc1d6041392d1b47750b14bf6845c2372ab Mon Sep 17 00:00:00 2001 From: Robin Holt Date: Sat, 2 Aug 2008 13:35:27 -0500 Subject: [IA64] update generic_defconfig to support sn2. This patch changes the generic_defconfig so it works on all sn2 platforms I have access to. There is only one support configuration which was not tested and that configuration is only a combination of two tested configurations. With this patchset applied, a generic kernel can be booted on either a RHEL 5.2, RHEL5.3, or SLES10 SP1 root and operate. All features needed by SGI's ProPack are also working. I have not tested all features of RHEL or SLES, but they do at least boot. Signed-off-by: Robin Holt Signed-off-by: Tony Luck --- arch/ia64/configs/generic_defconfig | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index 3ad1a464fd41..133089be5f2e 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.27-rc1 -# Fri Aug 1 19:33:14 2008 +# Sat Aug 2 13:24:08 2008 # CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -23,10 +23,17 @@ CONFIG_POSIX_MQUEUE=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=20 -# CONFIG_CGROUPS is not set +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +# CONFIG_CGROUP_NS is not set +# CONFIG_CGROUP_DEVICE is not set +CONFIG_CPUSETS=y # CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUP_CPUACCT is not set +# CONFIG_RESOURCE_COUNTERS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y +CONFIG_PROC_PID_CPUSET=y # CONFIG_RELAY is not set CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set @@ -130,6 +137,7 @@ CONFIG_DMI=y CONFIG_EFI=y CONFIG_GENERIC_IOMAP=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_IA64_UNCACHED_ALLOCATOR=y CONFIG_AUDIT_ARCH=y CONFIG_IA64_GENERIC=y # CONFIG_IA64_DIG is not set @@ -158,7 +166,7 @@ CONFIG_IOSAPIC=y CONFIG_FORCE_MAX_ZONEORDER=17 # CONFIG_VIRT_CPU_ACCOUNTING is not set CONFIG_SMP=y -CONFIG_NR_CPUS=512 +CONFIG_NR_CPUS=4096 CONFIG_HOTPLUG_CPU=y CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y @@ -369,7 +377,8 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_PNP=y @@ -403,7 +412,7 @@ CONFIG_MISC_DEVICES=y CONFIG_SGI_IOC4=y # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_SGI_XP is not set +CONFIG_SGI_XP=m # CONFIG_HP_ILO is not set CONFIG_SGI_GRU=m # CONFIG_SGI_GRU_DEBUG is not set @@ -1172,7 +1181,7 @@ CONFIG_INFINIBAND_IPOIB_DEBUG=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set -# CONFIG_MSPEC is not set +CONFIG_MSPEC=m # # File systems @@ -1375,6 +1384,7 @@ CONFIG_CRC_ITU_T=m CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set +CONFIG_GENERIC_ALLOCATOR=y CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y -- cgit v1.2.3 From 3351ab9b345ba5c2872acbf718cc631df72d3732 Mon Sep 17 00:00:00 2001 From: Jack Steiner Date: Thu, 31 Jul 2008 07:52:50 -0500 Subject: [IA64] Eliminate trailing backquote in IA64_SGI_UV Eliminate trailing backquote in IA64_SGI_UV config. Signed-off-by: Jack Steiner Signed-off-by: Tony Luck --- arch/ia64/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig index 977895893ed5..48e496fe1e75 100644 --- a/arch/ia64/Kconfig +++ b/arch/ia64/Kconfig @@ -171,8 +171,8 @@ config IA64_SGI_SN2 to select this option. If in doubt, select ia64 generic support instead. -config IA64_SGI_UV` - bool "SGI-UV`" +config IA64_SGI_UV + bool "SGI-UV" select NUMA select ACPI_NUMA select SWIOTLB -- cgit v1.2.3 From ee694d6b4106ca09dcf23f839b44efd152a1da82 Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 4 Aug 2008 13:39:28 -0700 Subject: [IA64] Fix uniprocessor build w.r.t. SGI_XP and SGI_GRU The SGI XP and GRU drivers only work on SMP systems ... the Kconfig file only disallowed them for non-SMP X86. Signed-off-by: Tony Luck --- drivers/misc/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 82af385460e4..a726f3b01a6b 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -427,10 +427,10 @@ config ENCLOSURE_SERVICES config SGI_XP tristate "Support communication between SGI SSIs" depends on NET - depends on IA64_GENERIC || IA64_SGI_SN2 || IA64_SGI_UV || (X86_64 && SMP) + depends on (IA64_GENERIC || IA64_SGI_SN2 || IA64_SGI_UV || X86_64) && SMP select IA64_UNCACHED_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 select GENERIC_ALLOCATOR if IA64_GENERIC || IA64_SGI_SN2 - select SGI_GRU if IA64_GENERIC || IA64_SGI_UV || (X86_64 && SMP) + select SGI_GRU if (IA64_GENERIC || IA64_SGI_UV || X86_64) && SMP ---help--- An SGI machine can be divided into multiple Single System Images which act independently of each other and have -- cgit v1.2.3 From bcbd2b65868213c1426654304de3da330cde6b3a Mon Sep 17 00:00:00 2001 From: Tony Luck Date: Mon, 4 Aug 2008 15:47:25 -0700 Subject: [IA64] Update generic config Changes to support a new platform in my lab. Signed-off-by: Tony Luck --- arch/ia64/configs/generic_defconfig | 71 ++++++++++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 4 deletions(-) diff --git a/arch/ia64/configs/generic_defconfig b/arch/ia64/configs/generic_defconfig index 133089be5f2e..9f483976228f 100644 --- a/arch/ia64/configs/generic_defconfig +++ b/arch/ia64/configs/generic_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.27-rc1 -# Sat Aug 2 13:24:08 2008 +# Mon Aug 4 15:38:01 2008 # CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -245,7 +245,8 @@ CONFIG_ACPI_SYSFS_POWER=y CONFIG_ACPI_PROC_EVENT=y CONFIG_ACPI_BUTTON=m CONFIG_ACPI_FAN=m -# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_DOCK=y +# CONFIG_ACPI_BAY is not set CONFIG_ACPI_PROCESSOR=m CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=m @@ -548,6 +549,7 @@ CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 CONFIG_SCSI_SYM53C8XX_MMIO=y +# CONFIG_SCSI_IPR is not set CONFIG_SCSI_QLOGIC_1280=y # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set @@ -557,7 +559,67 @@ CONFIG_SCSI_QLOGIC_1280=y # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set -# CONFIG_ATA is not set +CONFIG_ATA=y +CONFIG_ATA_NONSTANDARD=y +CONFIG_ATA_ACPI=y +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +CONFIG_ATA_PIIX=y +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ACPI is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m @@ -668,7 +730,8 @@ CONFIG_E1000=y # CONFIG_E1000_DISABLE_PACKET_SPLIT is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set -# CONFIG_IGB is not set +CONFIG_IGB=y +# CONFIG_IGB_LRO is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set -- cgit v1.2.3 From e34a8ae79056e6cea4a1ac21119ee3c91f378f99 Mon Sep 17 00:00:00 2001 From: Dan Williams Date: Tue, 5 Aug 2008 10:22:05 -0700 Subject: async_tx: fix missing braces in async_xor_zero_sum Found-by: Yuri Tikhonov Signed-off-by: Dan Williams --- crypto/async_tx/async_xor.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/crypto/async_tx/async_xor.c b/crypto/async_tx/async_xor.c index 65974c6d3d7a..c029d3eb9ef0 100644 --- a/crypto/async_tx/async_xor.c +++ b/crypto/async_tx/async_xor.c @@ -263,11 +263,12 @@ async_xor_zero_sum(struct page *dest, struct page **src_list, if (unlikely(!tx)) { async_tx_quiesce(&depend_tx); - while (!tx) + while (!tx) { dma_async_issue_pending(chan); tx = device->device_prep_dma_zero_sum(chan, dma_src, src_cnt, len, result, dma_prep_flags); + } } async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param); -- cgit v1.2.3 From edc9189c879af8cc8f1bf9746e63c5b014801a8a Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Mon, 28 Jul 2008 15:39:38 -0300 Subject: V4L/DVB (8549a): fix kernel-doc warning, function name, and docbook filename Change function name in kernel-doc and add kernel-doc for parameter @index: Warning(linhead//drivers/media/video/videodev.c:2090): No description found for parameter 'index' Also change source file name in DocBook/videobook.tmpl to match the new source file name. Signed-off-by: Randy Dunlap Signed-off-by: Mauro Carvalho Chehab --- Documentation/DocBook/videobook.tmpl | 2 +- drivers/media/video/v4l2-dev.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/DocBook/videobook.tmpl b/Documentation/DocBook/videobook.tmpl index 89817795e668..0bc25949b668 100644 --- a/Documentation/DocBook/videobook.tmpl +++ b/Documentation/DocBook/videobook.tmpl @@ -1648,7 +1648,7 @@ static struct video_buffer capture_fb; Public Functions Provided -!Edrivers/media/video/videodev.c +!Edrivers/media/video/v4l2-dev.c diff --git a/drivers/media/video/v4l2-dev.c b/drivers/media/video/v4l2-dev.c index 556615fe93de..6f36006aecda 100644 --- a/drivers/media/video/v4l2-dev.c +++ b/drivers/media/video/v4l2-dev.c @@ -222,11 +222,13 @@ int video_register_device(struct video_device *vfd, int type, int nr) EXPORT_SYMBOL(video_register_device); /** - * video_register_device - register video4linux devices + * video_register_device_index - register video4linux devices * @vfd: video device structure we want to register * @type: type of device to register * @nr: which device number (0 == /dev/video0, 1 == /dev/video1, ... * -1 == first free) + * @index: stream number based on parent device; + * -1 if auto assign, requested number otherwise * * The registration code assigns minor numbers based on the type * requested. -ENFILE is returned in all the device slots for this -- cgit v1.2.3 From 738608ae08572bf915c3fcd40e9579fbca06464b Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Mon, 28 Jul 2008 06:41:51 -0300 Subject: V4L/DVB (8550): gspca: Change a bit the init of ov7660 and Sonix JPEG bridges. Set back some values of gspcav1 in init of sonixj sensor ov7660. Add some comments. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/sonixj.c | 46 +++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c index 33a3df1f6915..65452f3b1945 100644 --- a/drivers/media/video/gspca/sonixj.c +++ b/drivers/media/video/gspca/sonixj.c @@ -360,17 +360,15 @@ static const __u8 ov7660_sensor_init[][8] = { {0xa1, 0x21, 0x12, 0x80, 0x00, 0x00, 0x00, 0x10}, /* reset SCCB */ /* (delay 20ms) */ {0xa1, 0x21, 0x12, 0x05, 0x00, 0x00, 0x00, 0x10}, - /* Outformat ?? rawRGB */ + /* Outformat = rawRGB */ {0xa1, 0x21, 0x13, 0xb8, 0x00, 0x00, 0x00, 0x10}, /* init COM8 */ - {0xd1, 0x21, 0x00, 0x01, 0x74, 0x92, 0x00, 0x10}, -/* {0xd1, 0x21, 0x00, 0x01, 0x74, 0x74, 0x00, 0x10}, */ + {0xd1, 0x21, 0x00, 0x01, 0x74, 0x74, 0x00, 0x10}, /* GAIN BLUE RED VREF */ {0xd1, 0x21, 0x04, 0x00, 0x7d, 0x62, 0x00, 0x10}, /* COM 1 BAVE GEAVE AECHH */ {0xb1, 0x21, 0x08, 0x83, 0x01, 0x00, 0x00, 0x10}, /* RAVE COM2 */ {0xd1, 0x21, 0x0c, 0x00, 0x08, 0x04, 0x4f, 0x10}, /* COM 3 4 5 6 */ - {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xf8, 0x10}, -/* {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xff, 0x10}, */ + {0xd1, 0x21, 0x10, 0x7f, 0x40, 0x05, 0xff, 0x10}, /* AECH CLKRC COM7 COM8 */ {0xc1, 0x21, 0x14, 0x2c, 0x00, 0x02, 0x00, 0x10}, /* COM9 COM10 */ {0xd1, 0x21, 0x17, 0x10, 0x60, 0x02, 0x7b, 0x10}, @@ -379,8 +377,8 @@ static const __u8 ov7660_sensor_init[][8] = { {0xb1, 0x21, 0x1e, 0x01, 0x0e, 0x00, 0x00, 0x10}, /* MVFP LAEC */ {0xd1, 0x21, 0x20, 0x07, 0x07, 0x07, 0x07, 0x10}, /* BOS GBOS GROS ROS (BGGR offset) */ - {0xd1, 0x21, 0x24, 0x68, 0x58, 0xd4, 0x80, 0x10}, -/* {0xd1, 0x21, 0x24, 0x78, 0x68, 0xd4, 0x80, 0x10}, */ +/* {0xd1, 0x21, 0x24, 0x68, 0x58, 0xd4, 0x80, 0x10}, */ + {0xd1, 0x21, 0x24, 0x78, 0x68, 0xd4, 0x80, 0x10}, /* AEW AEB VPT BBIAS */ {0xd1, 0x21, 0x28, 0x80, 0x30, 0x00, 0x00, 0x10}, /* GbBIAS RSVD EXHCH EXHCL */ @@ -407,9 +405,9 @@ static const __u8 ov7660_sensor_init[][8] = { {0xd1, 0x21, 0x62, 0x00, 0x00, 0x50, 0x30, 0x10}, /* LCC1 LCC2 LCC3 LCC4 */ {0xa1, 0x21, 0x66, 0x00, 0x00, 0x00, 0x00, 0x10}, /* LCC5 */ - {0xd1, 0x21, 0x67, 0x80, 0x7a, 0x90, 0x80, 0x10}, + {0xd1, 0x21, 0x67, 0x80, 0x7a, 0x90, 0x80, 0x10}, /* MANU */ {0xa1, 0x21, 0x6b, 0x0a, 0x00, 0x00, 0x00, 0x10}, - /* band gap reference [0..3] DBLV */ + /* band gap reference [0:3] DBLV */ {0xd1, 0x21, 0x6c, 0x30, 0x48, 0x80, 0x74, 0x10}, /* gamma curve */ {0xd1, 0x21, 0x70, 0x64, 0x60, 0x5c, 0x58, 0x10}, /* gamma curve */ {0xd1, 0x21, 0x74, 0x54, 0x4c, 0x40, 0x38, 0x10}, /* gamma curve */ @@ -419,37 +417,35 @@ static const __u8 ov7660_sensor_init[][8] = { {0xd1, 0x21, 0x84, 0x6e, 0x77, 0x87, 0x95, 0x10}, /* gamma curve */ {0xc1, 0x21, 0x88, 0xaf, 0xc7, 0xdf, 0x00, 0x10}, /* gamma curve */ {0xc1, 0x21, 0x8b, 0x99, 0x99, 0xcf, 0x00, 0x10}, /* reserved */ - {0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, + {0xb1, 0x21, 0x92, 0x00, 0x00, 0x00, 0x00, 0x10}, /* DM_LNL/H */ /****** (some exchanges in the win trace) ******/ - {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, + {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, /* MVFP */ /* bits[3..0]reserved */ {0xa1, 0x21, 0x1e, 0x01, 0x00, 0x00, 0x00, 0x10}, {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, /* VREF vertical frame ctrl */ {0xa1, 0x21, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10}, - {0xa1, 0x21, 0x10, 0x20, 0x00, 0x00, 0x00, 0x10}, /* 0x20 */ - {0xa1, 0x21, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x10}, - {0xa1, 0x21, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x10}, -/* {0xa1, 0x21, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x10}, */ - {0xa1, 0x21, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x10}, - {0xb1, 0x21, 0x01, 0x78, 0x78, 0x00, 0x00, 0x10}, + {0xa1, 0x21, 0x10, 0x20, 0x00, 0x00, 0x00, 0x10}, /* AECH 0x20 */ + {0xa1, 0x21, 0x2d, 0x00, 0x00, 0x00, 0x00, 0x10}, /* ADVFL */ + {0xa1, 0x21, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x10}, /* ADVFH */ + {0xa1, 0x21, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x10}, /* GAIN */ +/* {0xb1, 0x21, 0x01, 0x78, 0x78, 0x00, 0x00, 0x10}, * BLUE */ /****** (some exchanges in the win trace) ******/ {0xa1, 0x21, 0x93, 0x00, 0x00, 0x00, 0x00, 0x10},/* dummy line hight */ - {0xa1, 0x21, 0x92, 0x25, 0x00, 0x00, 0x00, 0x10},/* dummy line low */ - {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, - {0xa1, 0x21, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x10}, - {0xa1, 0x21, 0x02, 0x90, 0x00, 0x00, 0x00, 0x10}, + {0xa1, 0x21, 0x92, 0x25, 0x00, 0x00, 0x00, 0x10}, /* dummy line low */ + {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, /* EXHCH */ + {0xa1, 0x21, 0x2b, 0x00, 0x00, 0x00, 0x00, 0x10}, /* EXHCL */ +/* {0xa1, 0x21, 0x02, 0x90, 0x00, 0x00, 0x00, 0x10}, * RED */ /****** (some exchanges in the win trace) ******/ -/**********startsensor KO if changed !!****/ +/******!! startsensor KO if changed !!****/ {0xa1, 0x21, 0x93, 0x01, 0x00, 0x00, 0x00, 0x10}, {0xa1, 0x21, 0x92, 0xff, 0x00, 0x00, 0x00, 0x10}, {0xa1, 0x21, 0x2a, 0x00, 0x00, 0x00, 0x00, 0x10}, {0xa1, 0x21, 0x2b, 0xc3, 0x00, 0x00, 0x00, 0x10}, -/* here may start the isoc exchanges */ {} }; -/* reg0x04 reg0x07 reg 0x10 */ -/* expo = (COM1 & 0x02) | (AECHH & 0x2f <<10) [ (AECh << 2) */ +/* reg 0x04 reg 0x07 reg 0x10 */ +/* expo = (COM1 & 0x02) | ((AECHH & 0x2f) << 10) | (AECh << 2) */ static const __u8 ov7648_sensor_init[][8] = { {0xC1, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00}, -- cgit v1.2.3 From b01466e14ce82ff96b74db19ebdaefb34a430a24 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Mon, 28 Jul 2008 07:52:27 -0300 Subject: V4L/DVB (8552): gspca: Bad pixel format in the spca508 subdriver. The pixel format should have been changed in changeset 6de914aaad86. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/spca508.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c index b608a27ad115..6e213cf24cb3 100644 --- a/drivers/media/video/gspca/spca508.c +++ b/drivers/media/video/gspca/spca508.c @@ -63,22 +63,22 @@ static struct ctrl sd_ctrls[] = { }; static struct v4l2_pix_format sif_mode[] = { - {160, 120, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, + {160, 120, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, .bytesperline = 160 * 3, .sizeimage = 160 * 120 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 3}, - {176, 144, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, + {176, 144, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, .bytesperline = 176 * 3, .sizeimage = 176 * 144 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 2}, - {320, 240, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, + {320, 240, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, .bytesperline = 320 * 3, .sizeimage = 320 * 240 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 1}, - {352, 288, V4L2_PIX_FMT_YUYV, V4L2_FIELD_NONE, + {352, 288, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, .bytesperline = 352 * 3, .sizeimage = 352 * 288 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, -- cgit v1.2.3 From 35774f42dc6e765fc1d8a92f36e218f617a17e1a Mon Sep 17 00:00:00 2001 From: Mauro Carvalho Chehab Date: Mon, 28 Jul 2008 18:07:35 -0300 Subject: V4L/DVB (8558): media/video/Kconfig: fix a typo Thanks to Hermann Gausterer for pointing this issue. Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig index d4a6e56a7135..ecbfa1b39b70 100644 --- a/drivers/media/video/Kconfig +++ b/drivers/media/video/Kconfig @@ -630,7 +630,7 @@ config VIDEO_ZORAN_ZR36060 depends on VIDEO_ZORAN help Say Y to support Zoran boards based on 36060 chips. - This includes Iomega Bus, Pinnacle DC10, Linux media Labs 33 + This includes Iomega Buz, Pinnacle DC10, Linux media Labs 33 and 33 R10 and AverMedia 6 boards. config VIDEO_ZORAN_BUZ -- cgit v1.2.3 From 886f8d678a28882c193c2886c7280c0eccd8c9dd Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 28 Jul 2008 16:58:05 -0300 Subject: V4L/DVB (8562): DVB_DRX397XD: remove FW_LOADER select Also for the new DVB_DRX397XD driver the FW_LOADER select and the corresponding dependency on HOTPLUG can be removed. Signed-off-by: Adrian Bunk Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/frontends/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index 574dffe91b68..7dbb4a223c99 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig @@ -135,9 +135,8 @@ config DVB_CX22702 config DVB_DRX397XD tristate "Micronas DRX3975D/DRX3977D based" - depends on DVB_CORE && I2C && HOTPLUG + depends on DVB_CORE && I2C default m if DVB_FE_CUSTOMISE - select FW_LOADER help A DVB-T tuner module. Say Y when you want to support this frontend. -- cgit v1.2.3 From dfb9aff025c4c874f9169e2fd690ce6fee2309fe Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 28 Jul 2008 16:58:19 -0300 Subject: V4L/DVB (8563): fix drivers/media/video/arv.c compilation This patch fixes the following compile errors: <-- snip --> ... CC [M] drivers/media/video/arv.o /home/bunk/linux/kernel-2.6/git/linux-2.6/drivers/media/video/arv.c: In function 'ar_ioctl': /home/bunk/linux/kernel-2.6/git/linux-2.6/drivers/media/video/arv.c:544: error: implicit declaration of function 'video_usercopy' /home/bunk/linux/kernel-2.6/git/linux-2.6/drivers/media/video/arv.c: At top level: /home/bunk/linux/kernel-2.6/git/linux-2.6/drivers/media/video/arv.c:758: error: unknown field 'type' specified in initializer make[4]: *** [drivers/media/video/arv.o] Error 1 <-- snip --> Reported-by: Adrian Bunk Signed-off-by: Adrian Bunk Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/arv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/arv.c b/drivers/media/video/arv.c index 56ebfd5ef6fa..9e436ad3d34b 100644 --- a/drivers/media/video/arv.c +++ b/drivers/media/video/arv.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -755,7 +756,6 @@ static const struct file_operations ar_fops = { static struct video_device ar_template = { .name = "Colour AR VGA", - .type = VID_TYPE_CAPTURE, .fops = &ar_fops, .release = ar_release, .minor = -1, -- cgit v1.2.3 From c2cfcf701881c9a4ef42d5a956f9f2d006c2af8e Mon Sep 17 00:00:00 2001 From: Yoichi Yuasa Date: Tue, 29 Jul 2008 05:30:58 -0300 Subject: V4L/DVB (8564): fix vino driver build error The vino driver needs #include drivers/media/video/vino.c: In function 'vino_ioctl': drivers/media/video/vino.c:4364: error: implicit declaration of function 'video_usercopy' make[3]: *** [drivers/media/video/vino.o] Error 1 Signed-off-by: Yoichi Yuasa Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/vino.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/video/vino.c b/drivers/media/video/vino.c index ef7572cbc4ab..1edda456fc64 100644 --- a/drivers/media/video/vino.c +++ b/drivers/media/video/vino.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include -- cgit v1.2.3 From 0cd6759da646aae9d117df278ce3d5f3cab31904 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Tue, 29 Jul 2008 05:25:28 -0300 Subject: V4L/DVB (8567): gspca: hflip and vflip controls added for ov519 - ov7670 plus init cleanup. The hflip and vflip controls work for ov7670 only. This bridge/sensor inverts blue and red - not fixed. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/ov519.c | 114 ++++++++++++++++++++++++++++++++------ 1 file changed, 98 insertions(+), 16 deletions(-) diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c index 83139efc4629..b825941089b4 100644 --- a/drivers/media/video/gspca/ov519.c +++ b/drivers/media/video/gspca/ov519.c @@ -48,6 +48,8 @@ struct sd { unsigned char brightness; unsigned char contrast; unsigned char colors; + __u8 hflip; + __u8 vflip; char compress; /* Should the next frame be compressed? */ char compress_inited; /* Are compression params uploaded? */ @@ -77,6 +79,10 @@ static int sd_setcontrast(struct gspca_dev *gspca_dev, __s32 val); static int sd_getcontrast(struct gspca_dev *gspca_dev, __s32 *val); static int sd_setcolors(struct gspca_dev *gspca_dev, __s32 val); static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val); +static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val); +static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val); +static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val); +static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val); static struct ctrl sd_ctrls[] = { #define SD_BRIGHTNESS 0 @@ -121,6 +127,35 @@ static struct ctrl sd_ctrls[] = { .set = sd_setcolors, .get = sd_getcolors, }, +/* next controls work with ov7670 only */ + { + { + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .minimum = 0, + .maximum = 1, + .step = 1, +#define HFLIP_DEF 0 + .default_value = HFLIP_DEF, + }, + .set = sd_sethflip, + .get = sd_gethflip, + }, + { + { + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Vflip", + .minimum = 0, + .maximum = 1, + .step = 1, +#define VFLIP_DEF 0 + .default_value = VFLIP_DEF, + }, + .set = sd_setvflip, + .get = sd_getvflip, + }, }; static struct v4l2_pix_format vga_mode[] = { @@ -225,6 +260,7 @@ static struct v4l2_pix_format sif_mode[] = { #define OV7670_REG_VSTART 0x19 /* Vert start high bits */ #define OV7670_REG_VSTOP 0x1a /* Vert stop high bits */ #define OV7670_REG_MVFP 0x1e /* Mirror / vflip */ +#define OV7670_MVFP_VFLIP 0x10 /* vertical flip */ #define OV7670_MVFP_MIRROR 0x20 /* Mirror image */ #define OV7670_REG_AEW 0x24 /* AGC upper limit */ #define OV7670_REG_AEB 0x25 /* AGC lower limit */ @@ -930,7 +966,10 @@ static int ov7xx0_configure(struct sd *sd) { OV7670_REG_EDGE, 0 }, { 0x75, 0x05 }, { 0x76, 0xe1 }, { 0x4c, 0 }, { 0x77, 0x01 }, - { OV7670_REG_COM13, 0xc3 }, { 0x4b, 0x09 }, + { OV7670_REG_COM13, OV7670_COM13_GAMMA + | OV7670_COM13_UVSAT + | 2}, /* was 3 */ + { 0x4b, 0x09 }, { 0xc9, 0x60 }, { OV7670_REG_COM16, 0x38 }, { 0x56, 0x40 }, @@ -957,19 +996,6 @@ static int ov7xx0_configure(struct sd *sd) { 0x79, 0x05 }, { 0xc8, 0x30 }, { 0x79, 0x26 }, - /* Format YUV422 */ - { OV7670_REG_COM7, OV7670_COM7_YUV }, /* Selects YUV mode */ - { OV7670_REG_RGB444, 0 }, /* No RGB444 please */ - { OV7670_REG_COM1, 0 }, - { OV7670_REG_COM15, OV7670_COM15_R00FF }, - { OV7670_REG_COM9, 0x18 }, - /* 4x gain ceiling; 0x8 is reserved bit */ - { 0x4f, 0x80 }, /* "matrix coefficient 1" */ - { 0x50, 0x80 }, /* "matrix coefficient 2" */ - { 0x52, 0x22 }, /* "matrix coefficient 4" */ - { 0x53, 0x5e }, /* "matrix coefficient 5" */ - { 0x54, 0x80 }, /* "matrix coefficient 6" */ - { OV7670_REG_COM13, OV7670_COM13_GAMMA|OV7670_COM13_UVSAT }, }; PDEBUG(D_PROBE, "starting OV7xx0 configuration"); @@ -1375,6 +1401,8 @@ static int sd_config(struct gspca_dev *gspca_dev, sd->brightness = sd_ctrls[SD_BRIGHTNESS].qctrl.default_value; sd->contrast = sd_ctrls[SD_CONTRAST].qctrl.default_value; sd->colors = sd_ctrls[SD_COLOR].qctrl.default_value; + sd->hflip = HFLIP_DEF; + sd->vflip = VFLIP_DEF; return 0; error: PDEBUG(D_ERR, "OV519 Config failed"); @@ -1682,6 +1710,26 @@ static int mode_init_ov_sensor_regs(struct sd *sd, return 0; } +static void sethflip(struct sd *sd) +{ + if (sd->gspca_dev.streaming) + ov51x_stop(sd); + i2c_w_mask(sd, OV7670_REG_MVFP, + OV7670_MVFP_MIRROR * sd->hflip, OV7670_MVFP_MIRROR); + if (sd->gspca_dev.streaming) + ov51x_restart(sd); +} + +static void setvflip(struct sd *sd) +{ + if (sd->gspca_dev.streaming) + ov51x_stop(sd); + i2c_w_mask(sd, OV7670_REG_MVFP, + OV7670_MVFP_VFLIP * sd->vflip, OV7670_MVFP_VFLIP); + if (sd->gspca_dev.streaming) + ov51x_restart(sd); +} + static int set_ov_sensor_window(struct sd *sd, struct ovsensor_window *win) { @@ -1811,7 +1859,8 @@ static int set_ov_sensor_window(struct sd *sd, msleep(10); /* need to sleep between read and write to * same reg! */ i2c_w(sd, OV7670_REG_VREF, v); - + sethflip(sd); + setvflip(sd); } else { i2c_w(sd, 0x17, hwsbase + (win->x >> hwscale)); i2c_w(sd, 0x18, hwebase + ((win->x + win->width) >> hwscale)); @@ -2110,6 +2159,40 @@ static int sd_getcolors(struct gspca_dev *gspca_dev, __s32 *val) return 0; } +static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->hflip = val; + sethflip(sd); + return 0; +} + +static int sd_gethflip(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + + *val = sd->hflip; + return 0; +} + +static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val) +{ + struct sd *sd = (struct sd *) gspca_dev; + + sd->vflip = val; + setvflip(sd); + return 0; +} + +static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val) +{ + struct sd *sd = (struct sd *) gspca_dev; + + *val = sd->vflip; + return 0; +} + /* sub-driver description */ static const struct sd_desc sd_desc = { .name = MODULE_NAME, @@ -2178,4 +2261,3 @@ module_exit(sd_mod_exit); module_param(frame_rate, int, 0644); MODULE_PARM_DESC(frame_rate, "Frame rate (5, 10, 15, 20 or 30 fps)"); - -- cgit v1.2.3 From 8f47a3cefbb275893ce26ade7094599e4b129bb3 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Tue, 29 Jul 2008 14:14:04 -0300 Subject: V4L/DVB (8569): gspca: Set back the old values of Sonix sn9c120 and cleanup source. The values from win traces do not seem to work while the webcams did work with gspca v1. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/sonixj.c | 184 ++++++++++++------------------------- 1 file changed, 59 insertions(+), 125 deletions(-) diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c index 65452f3b1945..b60ff600a757 100644 --- a/drivers/media/video/gspca/sonixj.c +++ b/drivers/media/video/gspca/sonixj.c @@ -148,55 +148,58 @@ static struct v4l2_pix_format vga_mode[] = { /*Data from sn9c102p+hv71331r */ static const __u8 sn_hv7131[] = { -/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 reg9 */ - 0x00, 0x03, 0x64, 0x00, 0x1A, 0x20, 0x20, 0x20, 0xA1, 0x11, -/* rega regb regc regd rege regf reg10 reg11 */ - 0x02, 0x09, 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, /* 00 */ -/* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a reg1b */ - 0x00, 0x01, 0x03, 0x28, 0x1e, 0x41, 0x0a, 0x00, 0x00, 0x00, -/* reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ + 0x00, 0x03, 0x64, 0x00, 0x1a, 0x20, 0x20, 0x20, +/* reg8 reg9 rega regb regc regd rege regf */ + 0xa1, 0x11, 0x02, 0x09, 0x00, 0x00, 0x00, 0x10, +/* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ + 0x03, 0x00, 0x00, 0x01, 0x03, 0x28, 0x1e, 0x41, +/* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ + 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const __u8 sn_mi0360[] = { -/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 reg9 */ - 0x00, 0x61, 0x44, 0x00, 0x1a, 0x20, 0x20, 0x20, 0xb1, 0x5d, -/* rega regb regc regd rege regf reg10 reg11 */ - 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, -/* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a reg1b */ - 0x00, 0x02, 0x0a, 0x28, 0x1e, 0x61, 0x06, 0x00, 0x00, 0x00, -/* reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23 */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ + 0x00, 0x61, 0x44, 0x00, 0x1a, 0x20, 0x20, 0x20, +/* reg8 reg9 rega regb regc regd rege regf */ + 0xb1, 0x5d, 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, +/* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ + 0x03, 0x00, 0x00, 0x02, 0x0a, 0x28, 0x1e, 0x61, +/* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ + 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const __u8 sn_mo4000[] = { -/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 */ - 0x12, 0x23, 0x60, 0x00, 0x1A, 0x00, 0x20, 0x18, 0x81, -/* reg9 rega regb regc regd rege regf reg10 reg11*/ - 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, -/* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a*/ - 0x0b, 0x0f, 0x14, 0x28, 0x1e, 0x40, 0x08, 0x00, 0x00, -/* reg1b reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23*/ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x25, 0x39, 0x4b, - 0x5c, 0x6b, 0x79, 0x87, 0x95, 0xa2, 0xaf, 0xbb, 0xc7, - 0xd3, 0xdf, 0xea, 0xf5 +/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ + 0x12, 0x23, 0x60, 0x00, 0x1a, 0x00, 0x20, 0x18, +/* reg8 reg9 rega regb regc regd rege regf */ + 0x81, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +/* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ + 0x03, 0x00, 0x0b, 0x0f, 0x14, 0x28, 0x1e, 0x40, +/* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const __u8 sn_ov7648[] = { - 0x00, 0x21, 0x62, 0x00, 0x1a, 0x20, 0x20, 0x20, 0xA1, 0x6E, 0x18, 0x65, - 0x00, 0x00, 0x00, 0x10, 0x03, 0x00, 0x00, 0x06, 0x06, 0x28, 0x1E, 0x82, - 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 +/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ + 0x00, 0x21, 0x62, 0x00, 0x1a, 0x20, 0x20, 0x20, +/* reg8 reg9 rega regb regc regd rege regf */ + 0xa1, 0x6e, 0x18, 0x65, 0x00, 0x00, 0x00, 0x10, +/* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ + 0x03, 0x00, 0x00, 0x06, 0x06, 0x28, 0x1e, 0x82, +/* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 }; static const __u8 sn_ov7660[] = { -/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 */ - 0x00, 0x61, 0x40, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x81, -/* reg9 rega regb regc regd rege regf reg10 reg11*/ - 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, -/* reg12 reg13 reg14 reg15 reg16 reg17 reg18 reg19 reg1a*/ - 0x01, 0x01, 0x14, 0x28, 0x1e, 0x00, 0x07, 0x00, 0x00, -/* reg1b reg1c reg1d reg1e reg1f reg20 reg21 reg22 reg23*/ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +/* reg0 reg1 reg2 reg3 reg4 reg5 reg6 reg7 */ + 0x00, 0x61, 0x40, 0x00, 0x1a, 0x20, 0x20, 0x20, +/* reg8 reg9 rega regb regc regd rege regf */ + 0x81, 0x21, 0x07, 0x00, 0x00, 0x00, 0x00, 0x10, +/* reg10 reg11 reg12 reg13 reg14 reg15 reg16 reg17 */ + 0x03, 0x00, 0x01, 0x01, 0x08, 0x28, 0x1e, 0x20, +/* reg18 reg19 reg1a reg1b reg1c reg1d reg1e reg1f */ + 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; /* sequence specific to the sensors - !! index = SENSOR_xxx */ @@ -212,10 +215,6 @@ static const __u8 regsn20[] = { 0x00, 0x2d, 0x46, 0x5a, 0x6c, 0x7c, 0x8b, 0x99, 0xa6, 0xb2, 0xbf, 0xca, 0xd5, 0xe0, 0xeb, 0xf5, 0xff }; -static const __u8 regsn20_sn9c120[] = { - 0x00, 0x25, 0x3c, 0x50, 0x62, 0x72, 0x81, 0x90, - 0x9e, 0xab, 0xb8, 0xc5, 0xd1, 0xdd, 0xe9, 0xf4, 0xff -}; static const __u8 regsn20_sn9c325[] = { 0x0a, 0x3a, 0x56, 0x6c, 0x7e, 0x8d, 0x9a, 0xa4, 0xaf, 0xbb, 0xc5, 0xcd, 0xd5, 0xde, 0xe8, 0xed, 0xf5 @@ -227,21 +226,6 @@ static const __u8 reg84[] = { /* 0x00, 0x00, 0x00, 0x00, 0x00 */ 0xf7, 0x0f, 0x0a, 0x00, 0x00 }; -static const __u8 reg84_sn9c120_1[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0c, 0x00, 0x00 -}; -static const __u8 reg84_sn9c120_2[] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x0c, 0x02, 0x3b -}; -static const __u8 reg84_sn9c120_3[] = { - 0x14, 0x00, 0x27, 0x00, 0x08, 0x00, 0xeb, 0x0f, - 0xd5, 0x0f, 0x42, 0x00, 0x41, 0x00, 0xca, 0x0f, - 0xf5, 0x0f, 0x0c, 0x02, 0x3b -}; static const __u8 reg84_sn9c325[] = { 0x14, 0x00, 0x27, 0x00, 0x07, 0x00, 0xe4, 0x0f, 0xd3, 0x0f, 0x4b, 0x00, 0x48, 0x00, 0xc0, 0x0f, @@ -676,13 +660,12 @@ static int configure_gpio(struct gspca_dev *gspca_dev, const __u8 *reg9a; static const __u8 reg9a_def[] = {0x08, 0x40, 0x20, 0x10, 0x00, 0x04}; - static const __u8 reg9a_sn9c120[] = /* from win trace */ - {0x00, 0x40, 0x38, 0x30, 0x00, 0x20}; static const __u8 reg9a_sn9c325[] = {0x0a, 0x40, 0x38, 0x30, 0x00, 0x20}; + static const __u8 regd4[] = {0x60, 0x00, 0x00}; reg_w1(gspca_dev, 0xf1, 0x00); - reg_w1(gspca_dev, 0x01, sn9c1xx[0]); /*fixme:jfm was [1] en v1*/ + reg_w1(gspca_dev, 0x01, 0x00); /*jfm was sn9c1xx[1] in v1*/ /* configure gpio */ reg_w(gspca_dev, 0x01, &sn9c1xx[1], 2); @@ -692,25 +675,17 @@ static int configure_gpio(struct gspca_dev *gspca_dev, case BRIDGE_SN9C325: reg9a = reg9a_sn9c325; break; - case BRIDGE_SN9C120: - reg9a = reg9a_sn9c120; - break; default: reg9a = reg9a_def; break; } reg_w(gspca_dev, 0x9a, reg9a, 6); - reg_w1(gspca_dev, 0xd4, 0x60); /*fixme:jfm 60 00 00 (3) ? */ + reg_w(gspca_dev, 0xd4, regd4, sizeof regd4); /*fixme:jfm was 60 only*/ reg_w(gspca_dev, 0x03, &sn9c1xx[3], 0x0f); switch (sd->bridge) { - case BRIDGE_SN9C120: /* from win trace */ - reg_w1(gspca_dev, 0x01, 0x61); - reg_w1(gspca_dev, 0x17, 0x20); - reg_w1(gspca_dev, 0x01, 0x60); - break; case BRIDGE_SN9C325: reg_w1(gspca_dev, 0x01, 0x43); reg_w1(gspca_dev, 0x17, 0xae); @@ -819,10 +794,11 @@ static int sd_open(struct gspca_dev *gspca_dev) /* setup a selector by bridge */ reg_w1(gspca_dev, 0xf1, 0x01); - reg_r(gspca_dev, 0x00, 1); /* -> regF1 = 0x00 */ - reg_w1(gspca_dev, 0xf1, gspca_dev->usb_buf[0]); reg_r(gspca_dev, 0x00, 1); + reg_w1(gspca_dev, 0xf1, gspca_dev->usb_buf[0]); + reg_r(gspca_dev, 0x00, 1); /* get sonix chip id */ regF1 = gspca_dev->usb_buf[0]; + PDEBUG(D_PROBE, "Sonix chip id: %02x", regF1); switch (sd->bridge) { case BRIDGE_SN9C102P: if (regF1 != 0x11) @@ -933,15 +909,10 @@ static void setbrightness(struct gspca_dev *gspca_dev) sd->exposure = setexposure(gspca_dev, expo); break; case SENSOR_MI0360: - expo = sd->brightness >> 4; - sd->exposure = setexposure(gspca_dev, expo); - break; case SENSOR_MO4000: expo = sd->brightness >> 4; sd->exposure = setexposure(gspca_dev, expo); break; - case SENSOR_OV7660: - return; /*jfm??*/ } k2 = sd->brightness >> 10; @@ -954,8 +925,6 @@ static void setcontrast(struct gspca_dev *gspca_dev) __u8 k2; __u8 contrast[] = { 0x00, 0x00, 0x28, 0x00, 0x07, 0x00 }; - if (sd->sensor == SENSOR_OV7660) - return; /*jfm??*/ k2 = sd->contrast; contrast[2] = k2; contrast[0] = (k2 + 1) >> 1; @@ -982,15 +951,11 @@ static void sd_start(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; int i; - __u8 data; - __u8 reg1; - __u8 reg17; + __u8 reg1, reg17, reg18; const __u8 *sn9c1xx; int mode; static const __u8 C0[] = { 0x2d, 0x2d, 0x3a, 0x05, 0x04, 0x3f }; static const __u8 CA[] = { 0x28, 0xd8, 0x14, 0xec }; - static const __u8 CA_sn9c120[] = - { 0x14, 0xec, 0x0a, 0xf6 }; /* SN9C120 */ static const __u8 CE[] = { 0x32, 0xdd, 0x2d, 0xdd }; /* MI0360 */ static const __u8 CE_sn9c325[] = { 0x32, 0xdd, 0x32, 0xdd }; /* OV7648 - SN9C325 */ @@ -998,9 +963,7 @@ static void sd_start(struct gspca_dev *gspca_dev) sn9c1xx = sn_tb[(int) sd->sensor]; configure_gpio(gspca_dev, sn9c1xx); -/*fixme:jfm this sequence should appear at end of sd_start */ -/* with - reg_w1(gspca_dev, 0x01, 0x44); */ +/* reg_w1(gspca_dev, 0x01, 0x44); jfm from win trace*/ reg_w1(gspca_dev, 0x15, sn9c1xx[0x15]); reg_w1(gspca_dev, 0x16, sn9c1xx[0x16]); reg_w1(gspca_dev, 0x12, sn9c1xx[0x12]); @@ -1012,20 +975,16 @@ static void sd_start(struct gspca_dev *gspca_dev) reg_w1(gspca_dev, 0xc7, 0x00); reg_w1(gspca_dev, 0xc8, 0x50); reg_w1(gspca_dev, 0xc9, 0x3c); -/*fixme:jfm end of ending sequence */ reg_w1(gspca_dev, 0x18, sn9c1xx[0x18]); switch (sd->bridge) { case BRIDGE_SN9C325: - data = 0xae; - break; - case BRIDGE_SN9C120: - data = 0xa0; + reg17 = 0xae; break; default: - data = 0x60; + reg17 = 0x60; break; } - reg_w1(gspca_dev, 0x17, data); + reg_w1(gspca_dev, 0x17, reg17); reg_w1(gspca_dev, 0x05, sn9c1xx[5]); reg_w1(gspca_dev, 0x07, sn9c1xx[7]); reg_w1(gspca_dev, 0x06, sn9c1xx[6]); @@ -1040,20 +999,6 @@ static void sd_start(struct gspca_dev *gspca_dev) reg_w1(gspca_dev, 0x9a, 0x0a); reg_w1(gspca_dev, 0x99, 0x60); break; - case BRIDGE_SN9C120: - reg_w(gspca_dev, 0x20, regsn20_sn9c120, - sizeof regsn20_sn9c120); - for (i = 0; i < 2; i++) - reg_w(gspca_dev, 0x84, reg84_sn9c120_1, - sizeof reg84_sn9c120_1); - for (i = 0; i < 6; i++) - reg_w(gspca_dev, 0x84, reg84_sn9c120_2, - sizeof reg84_sn9c120_2); - reg_w(gspca_dev, 0x84, reg84_sn9c120_3, - sizeof reg84_sn9c120_3); - reg_w1(gspca_dev, 0x9a, 0x05); - reg_w1(gspca_dev, 0x99, 0x5b); - break; default: reg_w(gspca_dev, 0x20, regsn20, sizeof regsn20); for (i = 0; i < 8; i++) @@ -1103,22 +1048,14 @@ static void sd_start(struct gspca_dev *gspca_dev) /* reg1 = 0x44; */ /* reg1 = 0x46; (done) */ } else { - reg17 = 0xa2; /* 640 */ - reg1 = 0x40; + reg17 = 0x22; /* 640 MCKSIZE */ + reg1 = 0x06; } break; } reg_w(gspca_dev, 0xc0, C0, 6); + reg_w(gspca_dev, 0xca, CA, 4); switch (sd->bridge) { - case BRIDGE_SN9C120: /*jfm ?? */ - reg_w(gspca_dev, 0xca, CA_sn9c120, 4); - break; - default: - reg_w(gspca_dev, 0xca, CA, 4); - break; - } - switch (sd->bridge) { - case BRIDGE_SN9C120: /*jfm ?? */ case BRIDGE_SN9C325: reg_w(gspca_dev, 0xce, CE_sn9c325, 4); break; @@ -1129,14 +1066,13 @@ static void sd_start(struct gspca_dev *gspca_dev) } /* here change size mode 0 -> VGA; 1 -> CIF */ - data = 0x40 | sn9c1xx[0x18] | (mode << 4); - reg_w1(gspca_dev, 0x18, data); + reg18 = sn9c1xx[0x18] | (mode << 4); + reg_w1(gspca_dev, 0x18, reg18 | 0x40); reg_w(gspca_dev, 0x100, qtable4, 0x40); reg_w(gspca_dev, 0x140, qtable4 + 0x40, 0x40); - data = sn9c1xx[0x18] | (mode << 4); - reg_w1(gspca_dev, 0x18, data); + reg_w1(gspca_dev, 0x18, reg18); reg_w1(gspca_dev, 0x17, reg17); reg_w1(gspca_dev, 0x01, reg1); @@ -1164,12 +1100,11 @@ static void sd_stopN(struct gspca_dev *gspca_dev) i2c_w8(gspca_dev, stopmi0360); data = 0x29; break; - case SENSOR_MO4000: - break; case SENSOR_OV7648: data = 0x29; break; default: +/* case SENSOR_MO4000: */ /* case SENSOR_OV7660: */ break; } @@ -1296,6 +1231,7 @@ static unsigned int getexposure(struct gspca_dev *gspca_dev) (hexpo << 10) | (mexpo << 2) | lexpo); return (hexpo << 10) | (mexpo << 2) | lexpo; default: +/* case SENSOR_OV7648: * jfm: is it ok for 7648? */ /* case SENSOR_OV7660: */ /* read sensor exposure */ i2c_r5(gspca_dev, 0x04); @@ -1314,14 +1250,12 @@ static void getbrightness(struct gspca_dev *gspca_dev) /* hardcoded registers seem not readable */ switch (sd->sensor) { case SENSOR_HV7131R: -/* sd->brightness = 0x7fff; */ sd->brightness = getexposure(gspca_dev) >> 4; break; case SENSOR_MI0360: sd->brightness = getexposure(gspca_dev) << 4; break; case SENSOR_MO4000: -/* sd->brightness = 0x1fff; */ sd->brightness = getexposure(gspca_dev) << 4; break; } -- cgit v1.2.3 From 335b3f88f2c3cb101059970f57860503b20d210f Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Wed, 30 Jul 2008 04:53:02 -0300 Subject: V4L/DVB (8571): gspca: Don't use CONFIG_VIDEO_ADV_DEBUG as a compile option. This option is changed to GSPCA_DEBUG and it is set by default in gspca.h. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/conex.c | 4 ++-- drivers/media/video/gspca/etoms.c | 4 ++-- drivers/media/video/gspca/gspca.c | 10 +++++----- drivers/media/video/gspca/gspca.h | 5 ++++- drivers/media/video/gspca/sonixb.c | 2 +- drivers/media/video/gspca/zc3xx.c | 6 +++--- 6 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/media/video/gspca/conex.c b/drivers/media/video/gspca/conex.c index 44b0bffeb20e..cd3a3f5829b2 100644 --- a/drivers/media/video/gspca/conex.c +++ b/drivers/media/video/gspca/conex.c @@ -123,7 +123,7 @@ static void reg_r(struct gspca_dev *gspca_dev, { struct usb_device *dev = gspca_dev->dev; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (len > sizeof gspca_dev->usb_buf) { err("reg_r: buffer overflow"); return; @@ -163,7 +163,7 @@ static void reg_w(struct gspca_dev *gspca_dev, { struct usb_device *dev = gspca_dev->dev; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (len > sizeof gspca_dev->usb_buf) { err("reg_w: buffer overflow"); return; diff --git a/drivers/media/video/gspca/etoms.c b/drivers/media/video/gspca/etoms.c index c8c2f02fcf00..6a4e68286ef4 100644 --- a/drivers/media/video/gspca/etoms.c +++ b/drivers/media/video/gspca/etoms.c @@ -233,7 +233,7 @@ static void reg_r(struct gspca_dev *gspca_dev, { struct usb_device *dev = gspca_dev->dev; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (len > sizeof gspca_dev->usb_buf) { err("reg_r: buffer overflow"); return; @@ -271,7 +271,7 @@ static void reg_w(struct gspca_dev *gspca_dev, { struct usb_device *dev = gspca_dev->dev; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (len > sizeof gspca_dev->usb_buf) { err("reg_w: buffer overflow"); return; diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c index 3a051c925ff6..7f773e378979 100644 --- a/drivers/media/video/gspca/gspca.c +++ b/drivers/media/video/gspca/gspca.c @@ -47,7 +47,7 @@ MODULE_LICENSE("GPL"); static int video_nr = -1; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG int gspca_debug = D_ERR | D_PROBE; EXPORT_SYMBOL(gspca_debug); @@ -677,7 +677,7 @@ static int try_fmt_vid_cap(struct gspca_dev *gspca_dev, w = fmt->fmt.pix.width; h = fmt->fmt.pix.height; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (gspca_debug & D_CONF) PDEBUG_MODE("try fmt cap", fmt->fmt.pix.pixelformat, w, h); #endif @@ -785,7 +785,7 @@ static int dev_open(struct inode *inode, struct file *file) } gspca_dev->users++; file->private_data = gspca_dev; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG /* activate the v4l2 debug */ if (gspca_debug & D_V4L2) gspca_dev->vdev.debug |= 3; @@ -1080,7 +1080,7 @@ static int vidioc_streamon(struct file *file, void *priv, if (ret < 0) goto out; } -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (gspca_debug & D_STREAM) { PDEBUG_MODE("stream on OK", gspca_dev->pixfmt, @@ -1913,7 +1913,7 @@ static void __exit gspca_exit(void) module_init(gspca_init); module_exit(gspca_exit); -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG module_param_named(debug, gspca_debug, int, 0644); MODULE_PARM_DESC(debug, "Debug (bit) 0x01:error 0x02:probe 0x04:config" diff --git a/drivers/media/video/gspca/gspca.h b/drivers/media/video/gspca/gspca.h index 3fd2c4eee204..67e448940eaa 100644 --- a/drivers/media/video/gspca/gspca.h +++ b/drivers/media/video/gspca/gspca.h @@ -9,7 +9,10 @@ #include #include -#ifdef CONFIG_VIDEO_ADV_DEBUG +/* compilation option */ +#define GSPCA_DEBUG 1 + +#ifdef GSPCA_DEBUG /* GSPCA our debug messages */ extern int gspca_debug; #define PDEBUG(level, fmt, args...) \ diff --git a/drivers/media/video/gspca/sonixb.c b/drivers/media/video/gspca/sonixb.c index e18748c5a14d..11210c71f66c 100644 --- a/drivers/media/video/gspca/sonixb.c +++ b/drivers/media/video/gspca/sonixb.c @@ -408,7 +408,7 @@ static void reg_w(struct gspca_dev *gspca_dev, const __u8 *buffer, int len) { -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (len > sizeof gspca_dev->usb_buf) { PDEBUG(D_ERR|D_PACK, "reg_w: buffer overflow"); return; diff --git a/drivers/media/video/gspca/zc3xx.c b/drivers/media/video/gspca/zc3xx.c index 22a994ccb1d5..bc7d0eedcd81 100644 --- a/drivers/media/video/gspca/zc3xx.c +++ b/drivers/media/video/gspca/zc3xx.c @@ -6469,7 +6469,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) NULL, Tgradient_1, Tgradient_2, Tgradient_3, Tgradient_4, Tgradient_5, Tgradient_6 }; -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG __u8 v[16]; #endif @@ -6487,7 +6487,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) else if (g <= 0) g = 1; reg_w(dev, g, 0x0120 + i); /* gamma */ -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (gspca_debug & D_CONF) v[i] = g; #endif @@ -6507,7 +6507,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) g = 1; } reg_w(dev, g, 0x0130 + i); /* gradient */ -#ifdef CONFIG_VIDEO_ADV_DEBUG +#ifdef GSPCA_DEBUG if (gspca_debug & D_CONF) v[i] = g; #endif -- cgit v1.2.3 From 16fca0449997f1d77cd2d45d6c34b015f3853012 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Wed, 30 Jul 2008 05:14:38 -0300 Subject: V4L/DVB (8572): gspca: Webcam 0c45:6143 in documentation. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- Documentation/video4linux/gspca.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/video4linux/gspca.txt b/Documentation/video4linux/gspca.txt index bcaf4ab383be..78a863ab8a5a 100644 --- a/Documentation/video4linux/gspca.txt +++ b/Documentation/video4linux/gspca.txt @@ -226,6 +226,7 @@ sonixj 0c45:6130 Sonix Pccam sonixj 0c45:6138 Sn9c120 Mo4000 sonixj 0c45:613b Surfer SN-206 sonixj 0c45:613c Sonix Pccam168 +sonixj 0c45:6143 Sonix Pccam168 sunplus 0d64:0303 Sunplus FashionCam DXG etoms 102c:6151 Qcam Sangha CIF etoms 102c:6251 Qcam xxxxxx VGA -- cgit v1.2.3 From 01b988b2abdd60cc58c7916c5f91602d2571e0c5 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Wed, 30 Jul 2008 05:33:11 -0300 Subject: V4L/DVB (8573): gspca: Bad scan of frame in spca505/506/508. Bug introduced in changeset 6de914aaad86. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/spca505.c | 2 +- drivers/media/video/gspca/spca506.c | 2 +- drivers/media/video/gspca/spca508.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/video/gspca/spca505.c b/drivers/media/video/gspca/spca505.c index 3c2be80cbd65..9cc178ee203b 100644 --- a/drivers/media/video/gspca/spca505.c +++ b/drivers/media/video/gspca/spca505.c @@ -776,7 +776,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, default: data += 1; len -= 1; - gspca_frame_add(gspca_dev, FIRST_PACKET, frame, + gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len); break; } diff --git a/drivers/media/video/gspca/spca506.c b/drivers/media/video/gspca/spca506.c index 6fe715c80ad2..b4cf36a80df5 100644 --- a/drivers/media/video/gspca/spca506.c +++ b/drivers/media/video/gspca/spca506.c @@ -588,7 +588,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, default: data += 1; len -= 1; - gspca_frame_add(gspca_dev, FIRST_PACKET, frame, + gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len); break; } diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c index 6e213cf24cb3..a27686c8b849 100644 --- a/drivers/media/video/gspca/spca508.c +++ b/drivers/media/video/gspca/spca508.c @@ -1583,7 +1583,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, default: data += 1; len -= 1; - gspca_frame_add(gspca_dev, FIRST_PACKET, frame, + gspca_frame_add(gspca_dev, INTER_PACKET, frame, data, len); break; } -- cgit v1.2.3 From 00b27ce6205be8a943ae63d7bcce5208a9802bc3 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Wed, 30 Jul 2008 05:47:54 -0300 Subject: V4L/DVB (8574): gspca: Bad bytesperlines of pixelformat in spca505/506/508 and vc023x. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/spca505.c | 10 +++++----- drivers/media/video/gspca/spca506.c | 10 +++++----- drivers/media/video/gspca/spca508.c | 8 ++++---- drivers/media/video/gspca/vc032x.c | 4 ++-- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/media/video/gspca/spca505.c b/drivers/media/video/gspca/spca505.c index 9cc178ee203b..eda29d609359 100644 --- a/drivers/media/video/gspca/spca505.c +++ b/drivers/media/video/gspca/spca505.c @@ -61,27 +61,27 @@ static struct ctrl sd_ctrls[] = { static struct v4l2_pix_format vga_mode[] = { {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 160 * 3, + .bytesperline = 160, .sizeimage = 160 * 120 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 5}, {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 176 * 3, + .bytesperline = 176, .sizeimage = 176 * 144 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 4}, {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 320 * 3, + .bytesperline = 320, .sizeimage = 320 * 240 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 2}, {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 352 * 3, + .bytesperline = 352, .sizeimage = 352 * 288 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 1}, {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 640 * 3, + .bytesperline = 640, .sizeimage = 640 * 480 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 0}, diff --git a/drivers/media/video/gspca/spca506.c b/drivers/media/video/gspca/spca506.c index b4cf36a80df5..f622fa75766d 100644 --- a/drivers/media/video/gspca/spca506.c +++ b/drivers/media/video/gspca/spca506.c @@ -112,27 +112,27 @@ static struct ctrl sd_ctrls[] = { static struct v4l2_pix_format vga_mode[] = { {160, 120, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 160 * 3, + .bytesperline = 160, .sizeimage = 160 * 120 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 5}, {176, 144, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 176 * 3, + .bytesperline = 176, .sizeimage = 176 * 144 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 4}, {320, 240, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 320 * 3, + .bytesperline = 320, .sizeimage = 320 * 240 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 2}, {352, 288, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 352 * 3, + .bytesperline = 352, .sizeimage = 352 * 288 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 1}, {640, 480, V4L2_PIX_FMT_SPCA505, V4L2_FIELD_NONE, - .bytesperline = 640 * 3, + .bytesperline = 640, .sizeimage = 640 * 480 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 0}, diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c index a27686c8b849..699340c17dea 100644 --- a/drivers/media/video/gspca/spca508.c +++ b/drivers/media/video/gspca/spca508.c @@ -64,22 +64,22 @@ static struct ctrl sd_ctrls[] = { static struct v4l2_pix_format sif_mode[] = { {160, 120, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, - .bytesperline = 160 * 3, + .bytesperline = 160, .sizeimage = 160 * 120 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 3}, {176, 144, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, - .bytesperline = 176 * 3, + .bytesperline = 176, .sizeimage = 176 * 144 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 2}, {320, 240, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, - .bytesperline = 320 * 3, + .bytesperline = 320, .sizeimage = 320 * 240 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 1}, {352, 288, V4L2_PIX_FMT_SPCA508, V4L2_FIELD_NONE, - .bytesperline = 352 * 3, + .bytesperline = 352, .sizeimage = 352 * 288 * 3 / 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 0}, diff --git a/drivers/media/video/gspca/vc032x.c b/drivers/media/video/gspca/vc032x.c index a4221753e1bf..f4a52956e0d9 100644 --- a/drivers/media/video/gspca/vc032x.c +++ b/drivers/media/video/gspca/vc032x.c @@ -88,12 +88,12 @@ static struct ctrl sd_ctrls[] = { static struct v4l2_pix_format vc0321_mode[] = { {320, 240, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, - .bytesperline = 320 * 2, + .bytesperline = 320, .sizeimage = 320 * 240 * 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 1}, {640, 480, V4L2_PIX_FMT_YUV420, V4L2_FIELD_NONE, - .bytesperline = 640 * 2, + .bytesperline = 640, .sizeimage = 640 * 480 * 2, .colorspace = V4L2_COLORSPACE_SRGB, .priv = 0}, -- cgit v1.2.3 From a674a3b492d8085fd02ee49ed11cb42c63f0f71a Mon Sep 17 00:00:00 2001 From: Eugeniy Meshcheryakov Date: Fri, 1 Aug 2008 08:23:41 -0300 Subject: V4L/DVB (8582): set mts_firmware for em2882 based Pinnacle Hybrid Pro Pinnacle Hybrid Pro (2304:0226) requires mts_firmware flag to have any sound. Without this flag it is useful only for watching silent movies. Signed-off-by: Eugeniy Meshcheryakov Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/em28xx/em28xx-cards.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c index 476ae44a62d2..452da70e719f 100644 --- a/drivers/media/video/em28xx/em28xx-cards.c +++ b/drivers/media/video/em28xx/em28xx-cards.c @@ -1015,6 +1015,7 @@ struct em28xx_board em28xx_boards[] = { .valid = EM28XX_BOARD_NOT_VALIDATED, .vchannels = 3, .tuner_type = TUNER_XC2028, + .mts_firmware = 1, .decoder = EM28XX_TVP5150, .input = { { .type = EM28XX_VMUX_TELEVISION, -- cgit v1.2.3 From 594f5b8b3cce6d3137ebf260b7386520b2534385 Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Fri, 1 Aug 2008 06:37:51 -0300 Subject: V4L/DVB (8602): gspca: Fix small bugs, simplify and cleanup ov519. The hflip and vflip controls work for ov519 - ov7670 only. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/ov519.c | 394 ++++++++++++++------------------------ 1 file changed, 143 insertions(+), 251 deletions(-) diff --git a/drivers/media/video/gspca/ov519.c b/drivers/media/video/gspca/ov519.c index b825941089b4..b4f00ec0885c 100644 --- a/drivers/media/video/gspca/ov519.c +++ b/drivers/media/video/gspca/ov519.c @@ -40,8 +40,7 @@ struct sd { struct gspca_dev gspca_dev; /* !! must be the first item */ /* Determined by sensor type */ - short maxwidth; - short maxheight; + char sif; unsigned char primary_i2c_slave; /* I2C write id of sensor */ @@ -85,7 +84,6 @@ static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val); static int sd_getvflip(struct gspca_dev *gspca_dev, __s32 *val); static struct ctrl sd_ctrls[] = { -#define SD_BRIGHTNESS 0 { { .id = V4L2_CID_BRIGHTNESS, @@ -94,12 +92,12 @@ static struct ctrl sd_ctrls[] = { .minimum = 0, .maximum = 255, .step = 1, - .default_value = 127, +#define BRIGHTNESS_DEF 127 + .default_value = BRIGHTNESS_DEF, }, .set = sd_setbrightness, .get = sd_getbrightness, }, -#define SD_CONTRAST 1 { { .id = V4L2_CID_CONTRAST, @@ -108,21 +106,22 @@ static struct ctrl sd_ctrls[] = { .minimum = 0, .maximum = 255, .step = 1, - .default_value = 127, +#define CONTRAST_DEF 127 + .default_value = CONTRAST_DEF, }, .set = sd_setcontrast, .get = sd_getcontrast, }, -#define SD_COLOR 2 { { .id = V4L2_CID_SATURATION, .type = V4L2_CTRL_TYPE_INTEGER, - .name = "Saturation", + .name = "Color", .minimum = 0, .maximum = 255, .step = 1, - .default_value = 127, +#define COLOR_DEF 127 + .default_value = COLOR_DEF, }, .set = sd_setcolors, .get = sd_getcolors, @@ -161,7 +160,7 @@ static struct ctrl sd_ctrls[] = { static struct v4l2_pix_format vga_mode[] = { {320, 240, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, .bytesperline = 320, - .sizeimage = 320 * 240 * 3 / 8 + 589, + .sizeimage = 320 * 240 * 3 / 8 + 590, .colorspace = V4L2_COLORSPACE_JPEG, .priv = 1}, {640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, @@ -173,12 +172,12 @@ static struct v4l2_pix_format vga_mode[] = { static struct v4l2_pix_format sif_mode[] = { {176, 144, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, .bytesperline = 176, - .sizeimage = 176 * 144 * 3 / 8 + 589, + .sizeimage = 176 * 144 * 3 / 8 + 590, .colorspace = V4L2_COLORSPACE_JPEG, .priv = 1}, {352, 288, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE, .bytesperline = 352, - .sizeimage = 352 * 288 * 3 / 8 + 589, + .sizeimage = 352 * 288 * 3 / 8 + 590, .colorspace = V4L2_COLORSPACE_JPEG, .priv = 0}, }; @@ -294,16 +293,6 @@ static struct v4l2_pix_format sif_mode[] = { #define OV7670_REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */ #define OV7670_REG_BD60MAX 0xab /* 60hz banding step limit */ -struct ovsensor_window { - short x; - short y; - short width; - short height; -/* int format; */ - short quarter; /* Scale width and height down 2x */ - short clockdiv; /* Clock divisor setting */ -}; - static unsigned char ov7670_abs_to_sm(unsigned char v) { if (v > 127) @@ -535,19 +524,6 @@ static int init_ov_sensor(struct sd *sd) return 0; } -/* Switch on standard JPEG compression. Returns 0 for success. */ -static int ov519_init_compression(struct sd *sd) -{ - if (!sd->compress_inited) { - if (reg_w_mask(sd, OV519_SYS_EN_CLK1, 1 << 2, 1 << 2) < 0) { - PDEBUG(D_ERR, "Error switching to compressed mode"); - return -EIO; - } - sd->compress_inited = 1; - } - return 0; -} - /* Set the read and write slave IDs. The "slave" argument is the write slave, * and the read slave will be set to (slave + 1). * This should not be called from outside the i2c I/O functions. @@ -717,21 +693,17 @@ static int ov8xx0_configure(struct sd *sd) return -1; } if ((rc & 3) == 1) { - PDEBUG(D_PROBE, "Sensor is an OV8610"); sd->sensor = SEN_OV8610; } else { PDEBUG(D_ERR, "Unknown image sensor version: %d", rc & 3); return -1; } PDEBUG(D_PROBE, "Writing 8610 registers"); - if (write_i2c_regvals(sd, - norm_8610, - sizeof norm_8610 / sizeof norm_8610[0])) + if (write_i2c_regvals(sd, norm_8610, ARRAY_SIZE(norm_8610))) return -1; /* Set sensor-specific vars */ - sd->maxwidth = 640; - sd->maxheight = 480; +/* sd->sif = 0; already done */ return 0; } @@ -861,7 +833,7 @@ static int ov7xx0_configure(struct sd *sd) { OV7670_REG_COM7, OV7670_COM7_RESET }, { OV7670_REG_TSLB, 0x04 }, /* OV */ { OV7670_REG_COM7, OV7670_COM7_FMT_VGA }, /* VGA */ - { OV7670_REG_CLKRC, 0x1 }, + { OV7670_REG_CLKRC, 0x01 }, /* * Set the hardware window. These values from OV don't entirely * make sense - hstop is less than hstart. But they work... @@ -875,16 +847,12 @@ static int ov7xx0_configure(struct sd *sd) { 0x70, 0x3a }, { 0x71, 0x35 }, { 0x72, 0x11 }, { 0x73, 0xf0 }, { 0xa2, 0x02 }, -/* jfm */ -/* { OV7670_REG_COM10, 0x0 }, */ +/* { OV7670_REG_COM10, 0x0 }, */ /* Gamma curve values */ { 0x7a, 0x20 }, -/* jfm:win 7b=1c */ { 0x7b, 0x10 }, -/* jfm:win 7c=28 */ { 0x7c, 0x1e }, -/* jfm:win 7d=3c */ { 0x7d, 0x35 }, { 0x7e, 0x5a }, { 0x7f, 0x69 }, { 0x80, 0x76 }, { 0x81, 0x80 }, @@ -900,13 +868,11 @@ static int ov7xx0_configure(struct sd *sd) | OV7670_COM8_BFILT }, { OV7670_REG_GAIN, 0 }, { OV7670_REG_AECH, 0 }, { OV7670_REG_COM4, 0x40 }, /* magic reserved bit */ -/* jfm:win 14=38 */ { OV7670_REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */ { OV7670_REG_BD50MAX, 0x05 }, { OV7670_REG_BD60MAX, 0x07 }, { OV7670_REG_AEW, 0x95 }, { OV7670_REG_AEB, 0x33 }, { OV7670_REG_VPT, 0xe3 }, { OV7670_REG_HAECC1, 0x78 }, { OV7670_REG_HAECC2, 0x68 }, -/* jfm:win a1=0b */ { 0xa1, 0x03 }, /* magic */ { OV7670_REG_HAECC3, 0xd8 }, { OV7670_REG_HAECC4, 0xd8 }, { OV7670_REG_HAECC5, 0xf0 }, { OV7670_REG_HAECC6, 0x90 }, @@ -920,8 +886,6 @@ static int ov7xx0_configure(struct sd *sd) /* Almost all of these are magic "reserved" values. */ { OV7670_REG_COM5, 0x61 }, { OV7670_REG_COM6, 0x4b }, { 0x16, 0x02 }, -/* jfm */ -/* { OV7670_REG_MVFP, 0x07|OV7670_MVFP_MIRROR }, */ { OV7670_REG_MVFP, 0x07 }, { 0x21, 0x02 }, { 0x22, 0x91 }, { 0x29, 0x07 }, { 0x33, 0x0b }, @@ -995,17 +959,10 @@ static int ov7xx0_configure(struct sd *sd) { 0x79, 0x03 }, { 0xc8, 0x40 }, { 0x79, 0x05 }, { 0xc8, 0x30 }, { 0x79, 0x26 }, - -}; + }; PDEBUG(D_PROBE, "starting OV7xx0 configuration"); -/* jfm:already done? */ - if (init_ov_sensor(sd) < 0) - PDEBUG(D_ERR, "Failed to read sensor ID"); - else - PDEBUG(D_PROBE, "OV7xx0 initialized"); - /* Detect sensor (sub)type */ rc = i2c_r(sd, OV7610_REG_COM_I); @@ -1051,20 +1008,25 @@ static int ov7xx0_configure(struct sd *sd) return low; } if (high == 0x76) { - if (low == 0x30) { + switch (low) { + case 0x30: PDEBUG(D_PROBE, "Sensor is an OV7630/OV7635"); sd->sensor = SEN_OV7630; - } else if (low == 0x40) { + break; + case 0x40: PDEBUG(D_PROBE, "Sensor is an OV7645"); sd->sensor = SEN_OV7640; /* FIXME */ - } else if (low == 0x45) { + break; + case 0x45: PDEBUG(D_PROBE, "Sensor is an OV7645B"); sd->sensor = SEN_OV7640; /* FIXME */ - } else if (low == 0x48) { + break; + case 0x48: PDEBUG(D_PROBE, "Sensor is an OV7648"); sd->sensor = SEN_OV7640; /* FIXME */ - } else { - PDEBUG(D_PROBE, "Unknown sensor: 0x76%X", low); + break; + default: + PDEBUG(D_PROBE, "Unknown sensor: 0x76%x", low); return -1; } } else { @@ -1076,34 +1038,34 @@ static int ov7xx0_configure(struct sd *sd) return -1; } - if (sd->sensor == SEN_OV7620) { + switch (sd->sensor) { + case SEN_OV7620: PDEBUG(D_PROBE, "Writing 7620 registers"); - if (write_i2c_regvals(sd, norm_7620, - sizeof norm_7620 / sizeof norm_7620[0])) + if (write_i2c_regvals(sd, norm_7620, ARRAY_SIZE(norm_7620))) return -1; - } else if (sd->sensor == SEN_OV7630) { + break; + case SEN_OV7630: PDEBUG(D_ERR, "7630 is not supported by this driver version"); return -1; - } else if (sd->sensor == SEN_OV7640) { + case SEN_OV7640: PDEBUG(D_PROBE, "Writing 7640 registers"); - if (write_i2c_regvals(sd, norm_7640, - sizeof norm_7640 / sizeof norm_7640[0])) + if (write_i2c_regvals(sd, norm_7640, ARRAY_SIZE(norm_7640))) return -1; - } else if (sd->sensor == SEN_OV7670) { + break; + case SEN_OV7670: PDEBUG(D_PROBE, "Writing 7670 registers"); - if (write_i2c_regvals(sd, norm_7670, - sizeof norm_7670 / sizeof norm_7670[0])) + if (write_i2c_regvals(sd, norm_7670, ARRAY_SIZE(norm_7670))) return -1; - } else { + break; + default: PDEBUG(D_PROBE, "Writing 7610 registers"); - if (write_i2c_regvals(sd, norm_7610, - sizeof norm_7610 / sizeof norm_7610[0])) + if (write_i2c_regvals(sd, norm_7610, ARRAY_SIZE(norm_7610))) return -1; + break; } /* Set sensor-specific vars */ - sd->maxwidth = 640; - sd->maxheight = 480; +/* sd->sif = 0; already done */ return 0; } @@ -1257,43 +1219,45 @@ static int ov6xx0_configure(struct sd *sd) /* Ugh. The first two bits are the version bits, but * the entire register value must be used. I guess OVT * underestimated how many variants they would make. */ - if (rc == 0x00) { + switch (rc) { + case 0x00: sd->sensor = SEN_OV6630; PDEBUG(D_ERR, "WARNING: Sensor is an OV66308. Your camera may have"); PDEBUG(D_ERR, "been misdetected in previous driver versions."); - } else if (rc == 0x01) { + break; + case 0x01: sd->sensor = SEN_OV6620; - PDEBUG(D_PROBE, "Sensor is an OV6620"); - } else if (rc == 0x02) { + break; + case 0x02: sd->sensor = SEN_OV6630; PDEBUG(D_PROBE, "Sensor is an OV66308AE"); - } else if (rc == 0x03) { + break; + case 0x03: sd->sensor = SEN_OV6630; PDEBUG(D_PROBE, "Sensor is an OV66308AF"); - } else if (rc == 0x90) { + break; + case 0x90: sd->sensor = SEN_OV6630; PDEBUG(D_ERR, "WARNING: Sensor is an OV66307. Your camera may have"); PDEBUG(D_ERR, "been misdetected in previous driver versions."); - } else { + break; + default: PDEBUG(D_ERR, "FATAL: Unknown sensor version: 0x%02x", rc); return -1; } /* Set sensor-specific vars */ - sd->maxwidth = 352; - sd->maxheight = 288; + sd->sif = 1; if (sd->sensor == SEN_OV6620) { PDEBUG(D_PROBE, "Writing 6x20 registers"); - if (write_i2c_regvals(sd, norm_6x20, - sizeof norm_6x20 / sizeof norm_6x20[0])) + if (write_i2c_regvals(sd, norm_6x20, ARRAY_SIZE(norm_6x20))) return -1; } else { PDEBUG(D_PROBE, "Writing 6x30 registers"); - if (write_i2c_regvals(sd, norm_6x30, - sizeof norm_6x30 / sizeof norm_6x30[0])) + if (write_i2c_regvals(sd, norm_6x30, ARRAY_SIZE(norm_6x30))) return -1; } return 0; @@ -1302,14 +1266,8 @@ static int ov6xx0_configure(struct sd *sd) /* Turns on or off the LED. Only has an effect with OV511+/OV518(+)/OV519 */ static void ov51x_led_control(struct sd *sd, int on) { - PDEBUG(D_STREAM, "LED (%s)", on ? "on" : "off"); - -/* if (sd->bridge == BRG_OV511PLUS) */ -/* reg_w(sd, R511_SYS_LED_CTL, on ? 1 : 0); */ -/* else if (sd->bridge == BRG_OV519) */ - reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */ -/* else if (sd->bclass == BCL_OV518) */ -/* reg_w_mask(sd, R518_GPIO_OUT, on ? 0x02 : 0x00, 0x02); */ +/* PDEBUG(D_STREAM, "LED (%s)", on ? "on" : "off"); */ + reg_w_mask(sd, OV519_GPIO_DATA_OUT0, !on, 1); /* 0 / 1 */ } /* this function is called at probe time */ @@ -1319,11 +1277,8 @@ static int sd_config(struct gspca_dev *gspca_dev, struct sd *sd = (struct sd *) gspca_dev; struct cam *cam; -/* (from ov519_configure) */ static const struct ov_regvals init_519[] = { { 0x5a, 0x6d }, /* EnableSystem */ -/* jfm trace usbsnoop3-1.txt */ -/* jfm 53 = fb */ { 0x53, 0x9b }, { 0x54, 0xff }, /* set bit2 to enable jpeg */ { 0x5d, 0x03 }, @@ -1340,9 +1295,6 @@ static int sd_config(struct gspca_dev *gspca_dev, if (write_regvals(sd, init_519, ARRAY_SIZE(init_519))) goto error; -/* jfm: not seen in windows trace */ - if (ov519_init_compression(sd)) - goto error; ov51x_led_control(sd, 0); /* turn LED off */ /* Test for 76xx */ @@ -1391,16 +1343,16 @@ static int sd_config(struct gspca_dev *gspca_dev, cam = &gspca_dev->cam; cam->epaddr = OV511_ENDPOINT_ADDRESS; - if (sd->maxwidth == 640) { + if (!sd->sif) { cam->cam_mode = vga_mode; - cam->nmodes = sizeof vga_mode / sizeof vga_mode[0]; + cam->nmodes = ARRAY_SIZE(vga_mode); } else { cam->cam_mode = sif_mode; - cam->nmodes = sizeof sif_mode / sizeof sif_mode[0]; + cam->nmodes = ARRAY_SIZE(sif_mode); } - sd->brightness = sd_ctrls[SD_BRIGHTNESS].qctrl.default_value; - sd->contrast = sd_ctrls[SD_CONTRAST].qctrl.default_value; - sd->colors = sd_ctrls[SD_COLOR].qctrl.default_value; + sd->brightness = BRIGHTNESS_DEF; + sd->contrast = CONTRAST_DEF; + sd->colors = COLOR_DEF; sd->hflip = HFLIP_DEF; sd->vflip = VFLIP_DEF; return 0; @@ -1422,8 +1374,7 @@ static int sd_open(struct gspca_dev *gspca_dev) * * Do not put any sensor-specific code in here (including I2C I/O functions) */ -static int ov519_mode_init_regs(struct sd *sd, - int width, int height) +static int ov519_mode_init_regs(struct sd *sd) { static const struct ov_regvals mode_init_519_ov7670[] = { { 0x5d, 0x03 }, /* Turn off suspend mode */ @@ -1469,36 +1420,23 @@ static int ov519_mode_init_regs(struct sd *sd, /* windows reads 0x55 at this point, why? */ }; -/* int hi_res; */ - - PDEBUG(D_CONF, "mode init %dx%d", width, height); - -/* if (width >= 800 && height >= 600) - hi_res = 1; - else - hi_res = 0; */ - -/* if (ov51x_stop(sd) < 0) - return -EIO; */ - /******** Set the mode ********/ if (sd->sensor != SEN_OV7670) { if (write_regvals(sd, mode_init_519, ARRAY_SIZE(mode_init_519))) return -EIO; + if (sd->sensor == SEN_OV7640) { + /* Select 8-bit input mode */ + reg_w_mask(sd, OV519_CAM_DFR, 0x10, 0x10); + } } else { if (write_regvals(sd, mode_init_519_ov7670, ARRAY_SIZE(mode_init_519_ov7670))) return -EIO; } - if (sd->sensor == SEN_OV7640) { - /* Select 8-bit input mode */ - reg_w_mask(sd, OV519_CAM_DFR, 0x10, 0x10); - } - - reg_w(sd, OV519_CAM_H_SIZE, width >> 4); - reg_w(sd, OV519_CAM_V_SIZE, height >> 3); + reg_w(sd, OV519_CAM_H_SIZE, sd->gspca_dev.width >> 4); + reg_w(sd, OV519_CAM_V_SIZE, sd->gspca_dev.height >> 3); reg_w(sd, OV519_CAM_X_OFFSETL, 0x00); reg_w(sd, OV519_CAM_X_OFFSETH, 0x00); reg_w(sd, OV519_CAM_Y_OFFSETL, 0x00); @@ -1513,9 +1451,10 @@ static int ov519_mode_init_regs(struct sd *sd, /* FIXME: These are only valid at the max resolution. */ sd->clockdiv = 0; - if (sd->sensor == SEN_OV7640) { + switch (sd->sensor) { + case SEN_OV7640: switch (sd->frame_rate) { -/*jfm: default was 30 fps */ +/*fixme: default was 30 fps */ case 30: reg_w(sd, 0xa4, 0x0c); reg_w(sd, 0x23, 0xff); @@ -1545,7 +1484,8 @@ static int ov519_mode_init_regs(struct sd *sd, sd->clockdiv = 1; break; } - } else if (sd->sensor == SEN_OV8610) { + break; + case SEN_OV8610: switch (sd->frame_rate) { default: /* 15 fps */ /* case 15: */ @@ -1561,41 +1501,37 @@ static int ov519_mode_init_regs(struct sd *sd, reg_w(sd, 0x23, 0x1b); break; } - sd->clockdiv = 0; - } else if (sd->sensor == SEN_OV7670) { /* guesses, based on 7640 */ + break; + case SEN_OV7670: /* guesses, based on 7640 */ PDEBUG(D_STREAM, "Setting framerate to %d fps", (sd->frame_rate == 0) ? 15 : sd->frame_rate); + reg_w(sd, 0xa4, 0x10); switch (sd->frame_rate) { case 30: - reg_w(sd, 0xa4, 0x10); reg_w(sd, 0x23, 0xff); break; case 20: - reg_w(sd, 0xa4, 0x10); reg_w(sd, 0x23, 0x1b); break; - default: /* 15 fps */ -/* case 15: */ - reg_w(sd, 0xa4, 0x10); + default: +/* case 15: */ reg_w(sd, 0x23, 0xff); sd->clockdiv = 1; break; } + break; } -/* if (ov51x_restart(sd) < 0) - return -EIO; */ - - /* Reset it just for good measure */ -/* if (ov51x_reset(sd, OV511_RESET_NOREGS) < 0) - return -EIO; */ return 0; } -static int mode_init_ov_sensor_regs(struct sd *sd, - struct ovsensor_window *win) +static int mode_init_ov_sensor_regs(struct sd *sd) { - int qvga = win->quarter; + struct gspca_dev *gspca_dev; + int qvga; + + gspca_dev = &sd->gspca_dev; + qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv; /******** Mode (VGA/QVGA) and sensor specific regs ********/ switch (sd->sensor) { @@ -1639,8 +1575,6 @@ static int mode_init_ov_sensor_regs(struct sd *sd, OV7670_COM7_FMT_MASK); break; case SEN_OV6620: - i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20); - break; case SEN_OV6630: i2c_w_mask(sd, 0x14, qvga ? 0x20 : 0x00, 0x20); break; @@ -1649,24 +1583,21 @@ static int mode_init_ov_sensor_regs(struct sd *sd, } /******** Palette-specific regs ********/ -/* Need to do work here for the OV7670 */ - - if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { - /* not valid on the OV6620/OV7620/6630? */ - i2c_w_mask(sd, 0x0e, 0x00, 0x40); - } + if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { + /* not valid on the OV6620/OV7620/6630? */ + i2c_w_mask(sd, 0x0e, 0x00, 0x40); + } - /* The OV518 needs special treatment. Although both the OV518 - * and the OV6630 support a 16-bit video bus, only the 8 bit Y - * bus is actually used. The UV bus is tied to ground. - * Therefore, the OV6630 needs to be in 8-bit multiplexed - * output mode */ + /* The OV518 needs special treatment. Although both the OV518 + * and the OV6630 support a 16-bit video bus, only the 8 bit Y + * bus is actually used. The UV bus is tied to ground. + * Therefore, the OV6630 needs to be in 8-bit multiplexed + * output mode */ - /* OV7640 is 8-bit only */ + /* OV7640 is 8-bit only */ - if (sd->sensor != SEN_OV6630 && sd->sensor != SEN_OV7640) - i2c_w_mask(sd, 0x13, 0x00, 0x20); -/* } */ + if (sd->sensor != SEN_OV6630 && sd->sensor != SEN_OV7640) + i2c_w_mask(sd, 0x13, 0x00, 0x20); /******** Clock programming ********/ /* The OV6620 needs special handling. This prevents the @@ -1675,14 +1606,14 @@ static int mode_init_ov_sensor_regs(struct sd *sd, /* Clock down */ i2c_w(sd, 0x2a, 0x04); - i2c_w(sd, 0x11, win->clockdiv); + i2c_w(sd, 0x11, sd->clockdiv); i2c_w(sd, 0x2a, 0x84); /* This next setting is critical. It seems to improve * the gain or the contrast. The "reserved" bits seem * to have some effect in this case. */ i2c_w(sd, 0x2d, 0x85); - } else if (win->clockdiv >= 0) { - i2c_w(sd, 0x11, win->clockdiv); + } else if (sd->clockdiv >= 0) { + i2c_w(sd, 0x11, sd->clockdiv); } /******** Special Features ********/ @@ -1702,7 +1633,7 @@ static int mode_init_ov_sensor_regs(struct sd *sd, /* is fully tested. */ /* 7620/6620/6630? don't have register 0x35, so play it safe */ if (sd->sensor == SEN_OV7610 || sd->sensor == SEN_OV76BE) { - if (win->width == 640 /*&& win->height == 480*/) + if (!qvga) i2c_w(sd, 0x35, 0x9e); else i2c_w(sd, 0x35, 0x1e); @@ -1710,33 +1641,31 @@ static int mode_init_ov_sensor_regs(struct sd *sd, return 0; } -static void sethflip(struct sd *sd) -{ - if (sd->gspca_dev.streaming) - ov51x_stop(sd); - i2c_w_mask(sd, OV7670_REG_MVFP, - OV7670_MVFP_MIRROR * sd->hflip, OV7670_MVFP_MIRROR); - if (sd->gspca_dev.streaming) - ov51x_restart(sd); -} - -static void setvflip(struct sd *sd) +static void sethvflip(struct sd *sd) { + if (sd->sensor != SEN_OV7670) + return; if (sd->gspca_dev.streaming) ov51x_stop(sd); i2c_w_mask(sd, OV7670_REG_MVFP, - OV7670_MVFP_VFLIP * sd->vflip, OV7670_MVFP_VFLIP); + OV7670_MVFP_MIRROR * sd->hflip + | OV7670_MVFP_VFLIP * sd->vflip, + OV7670_MVFP_MIRROR | OV7670_MVFP_VFLIP); if (sd->gspca_dev.streaming) ov51x_restart(sd); } -static int set_ov_sensor_window(struct sd *sd, - struct ovsensor_window *win) +static int set_ov_sensor_window(struct sd *sd) { + struct gspca_dev *gspca_dev; + int qvga; int hwsbase, hwebase, vwsbase, vwebase, hwscale, vwscale; int ret, hstart, hstop, vstop, vstart; __u8 v; + gspca_dev = &sd->gspca_dev; + qvga = gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv; + /* The different sensor ICs handle setting up of window differently. * IF YOU SET IT WRONG, YOU WILL GET ALL ZERO ISOC DATA FROM OV51x!! */ switch (sd->sensor) { @@ -1781,7 +1710,7 @@ static int set_ov_sensor_window(struct sd *sd, switch (sd->sensor) { case SEN_OV6620: case SEN_OV6630: - if (win->quarter) { /* QCIF */ + if (qvga) { /* QCIF */ hwscale = 0; vwscale = 0; } else { /* CIF */ @@ -1791,7 +1720,7 @@ static int set_ov_sensor_window(struct sd *sd, } break; case SEN_OV8610: - if (win->quarter) { /* QSVGA */ + if (qvga) { /* QSVGA */ hwscale = 1; vwscale = 1; } else { /* SVGA */ @@ -1800,7 +1729,7 @@ static int set_ov_sensor_window(struct sd *sd, } break; default: /* SEN_OV7xx0 */ - if (win->quarter) { /* QVGA */ + if (qvga) { /* QVGA */ hwscale = 1; vwscale = 0; } else { /* VGA */ @@ -1809,7 +1738,7 @@ static int set_ov_sensor_window(struct sd *sd, } } - ret = mode_init_ov_sensor_regs(sd, win); + ret = mode_init_ov_sensor_regs(sd); if (ret < 0) return ret; @@ -1830,7 +1759,7 @@ static int set_ov_sensor_window(struct sd *sd, /* I can hard code this for OV7670s */ /* Yes, these numbers do look odd, but they're tested and work! */ if (sd->sensor == SEN_OV7670) { - if (win->quarter) { /* QVGA from ov7670.c by + if (qvga) { /* QVGA from ov7670.c by * Jonathan Corbet */ hstart = 164; hstop = 20; @@ -1844,76 +1773,45 @@ static int set_ov_sensor_window(struct sd *sd, } /* OV7670 hardware window registers are split across * multiple locations */ - i2c_w(sd, OV7670_REG_HSTART, (hstart >> 3) & 0xff); - i2c_w(sd, OV7670_REG_HSTOP, (hstop >> 3) & 0xff); + i2c_w(sd, OV7670_REG_HSTART, hstart >> 3); + i2c_w(sd, OV7670_REG_HSTOP, hstop >> 3); v = i2c_r(sd, OV7670_REG_HREF); v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x07); msleep(10); /* need to sleep between read and write to * same reg! */ i2c_w(sd, OV7670_REG_HREF, v); - i2c_w(sd, OV7670_REG_VSTART, (vstart >> 2) & 0xff); - i2c_w(sd, OV7670_REG_VSTOP, (vstop >> 2) & 0xff); + i2c_w(sd, OV7670_REG_VSTART, vstart >> 2); + i2c_w(sd, OV7670_REG_VSTOP, vstop >> 2); v = i2c_r(sd, OV7670_REG_VREF); v = (v & 0xc0) | ((vstop & 0x3) << 2) | (vstart & 0x03); msleep(10); /* need to sleep between read and write to * same reg! */ i2c_w(sd, OV7670_REG_VREF, v); - sethflip(sd); - setvflip(sd); + sethvflip(sd); } else { - i2c_w(sd, 0x17, hwsbase + (win->x >> hwscale)); - i2c_w(sd, 0x18, hwebase + ((win->x + win->width) >> hwscale)); - i2c_w(sd, 0x19, vwsbase + (win->y >> vwscale)); - i2c_w(sd, 0x1a, vwebase + ((win->y + win->height) >> vwscale)); + i2c_w(sd, 0x17, hwsbase); + i2c_w(sd, 0x18, hwebase + (sd->gspca_dev.width >> hwscale)); + i2c_w(sd, 0x19, vwsbase); + i2c_w(sd, 0x1a, vwebase + (sd->gspca_dev.height >> vwscale)); } return 0; } -static int ov_sensor_mode_setup(struct sd *sd, - int width, int height) -{ - struct ovsensor_window win; - -/* win.format = mode; */ - - /* Unless subcapture is enabled, - * center the image window and downsample - * if possible to increase the field of view */ - /* NOTE: OV518(+) and OV519 does downsampling on its own */ - win.width = width; - win.height = height; - if (width == sd->maxwidth) - win.quarter = 0; - else - win.quarter = 1; - - /* Center it */ - win.x = (win.width - width) / 2; - win.y = (win.height - height) / 2; - - /* Clock is determined by OV519 frame rate code */ - win.clockdiv = sd->clockdiv; - - PDEBUG(D_CONF, "Setting clock divider to %d", win.clockdiv); - return set_ov_sensor_window(sd, &win); -} - /* -- start the camera -- */ static void sd_start(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; int ret; - - ret = ov519_mode_init_regs(sd, gspca_dev->width, gspca_dev->height); + ret = ov519_mode_init_regs(sd); if (ret < 0) goto out; - ret = ov_sensor_mode_setup(sd, gspca_dev->width, gspca_dev->height); + ret = set_ov_sensor_window(sd); if (ret < 0) goto out; - ret = ov51x_restart((struct sd *) gspca_dev); + ret = ov51x_restart(sd); if (ret < 0) goto out; PDEBUG(D_STREAM, "camera started alt: 0x%02x", gspca_dev->alt); @@ -1987,12 +1885,10 @@ static void setbrightness(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; int val; -/* int was_streaming; */ val = sd->brightness; PDEBUG(D_CONF, "brightness:%d", val); -/* was_streaming = gspca_dev->streaming; - * if (was_streaming) +/* if (gspca_dev->streaming) * ov51x_stop(sd); */ switch (sd->sensor) { case SEN_OV8610: @@ -2010,12 +1906,12 @@ static void setbrightness(struct gspca_dev *gspca_dev) i2c_w(sd, OV7610_REG_BRT, val); break; case SEN_OV7670: -/*jfm - from windblows +/*win trace * i2c_w_mask(sd, OV7670_REG_COM8, 0, OV7670_COM8_AEC); */ i2c_w(sd, OV7670_REG_BRIGHT, ov7670_abs_to_sm(val)); break; } -/* if (was_streaming) +/* if (gspca_dev->streaming) * ov51x_restart(sd); */ } @@ -2023,12 +1919,10 @@ static void setcontrast(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; int val; -/* int was_streaming; */ val = sd->contrast; PDEBUG(D_CONF, "contrast:%d", val); -/* was_streaming = gspca_dev->streaming; - if (was_streaming) +/* if (gspca_dev->streaming) ov51x_stop(sd); */ switch (sd->sensor) { case SEN_OV7610: @@ -2065,7 +1959,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) i2c_w(sd, OV7670_REG_CONTRAS, val >> 1); break; } -/* if (was_streaming) +/* if (gspca_dev->streaming) ov51x_restart(sd); */ } @@ -2073,12 +1967,10 @@ static void setcolors(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; int val; -/* int was_streaming; */ val = sd->colors; PDEBUG(D_CONF, "saturation:%d", val); -/* was_streaming = gspca_dev->streaming; - if (was_streaming) +/* if (gspca_dev->streaming) ov51x_stop(sd); */ switch (sd->sensor) { case SEN_OV8610: @@ -2104,7 +1996,7 @@ static void setcolors(struct gspca_dev *gspca_dev) /* set REG_COM13 values for UV sat auto mode */ break; } -/* if (was_streaming) +/* if (gspca_dev->streaming) ov51x_restart(sd); */ } @@ -2164,7 +2056,7 @@ static int sd_sethflip(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->hflip = val; - sethflip(sd); + sethvflip(sd); return 0; } @@ -2181,7 +2073,7 @@ static int sd_setvflip(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->vflip = val; - setvflip(sd); + sethvflip(sd); return 0; } -- cgit v1.2.3 From cebf3b67f7f80fd69bd1ff5787fee69ab8fd3c2a Mon Sep 17 00:00:00 2001 From: Jean-Francois Moine Date: Sun, 3 Aug 2008 07:52:53 -0300 Subject: V4L/DVB (8604): gspca: Fix of "scheduling while atomic" crash. The crash is due to USB exchanges done at interrupt level. These exchanges, tied to autogain, are now done by the application. Also, there is a fix about autogain start. Concerned subdrivers: etoms, pac7311, sonixj and spca561. Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/etoms.c | 133 +++++++++++++++++++----------------- drivers/media/video/gspca/pac7311.c | 54 +++++++++------ drivers/media/video/gspca/sonixj.c | 57 +++++++++++----- drivers/media/video/gspca/spca561.c | 42 +++++++----- 4 files changed, 171 insertions(+), 115 deletions(-) diff --git a/drivers/media/video/gspca/etoms.c b/drivers/media/video/gspca/etoms.c index 6a4e68286ef4..1dbe92d01e6a 100644 --- a/drivers/media/video/gspca/etoms.c +++ b/drivers/media/video/gspca/etoms.c @@ -461,6 +461,52 @@ static void Et_init2(struct gspca_dev *gspca_dev) reg_w_val(gspca_dev, 0x80, 0x20); /* 0x20; */ } +static void setbrightness(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + int i; + __u8 brightness = sd->brightness; + + for (i = 0; i < 4; i++) + reg_w_val(gspca_dev, ET_O_RED + i, brightness); +} + +static void getbrightness(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + int i; + int brightness = 0; + + for (i = 0; i < 4; i++) { + reg_r(gspca_dev, ET_O_RED + i, 1); + brightness += gspca_dev->usb_buf[0]; + } + sd->brightness = brightness >> 3; +} + +static void setcontrast(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + __u8 RGBG[] = { 0x80, 0x80, 0x80, 0x80, 0x00, 0x00 }; + __u8 contrast = sd->contrast; + + memset(RGBG, contrast, sizeof(RGBG) - 2); + reg_w(gspca_dev, ET_G_RED, RGBG, 6); +} + +static void getcontrast(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + int i; + int contrast = 0; + + for (i = 0; i < 4; i++) { + reg_r(gspca_dev, ET_G_RED + i, 1); + contrast += gspca_dev->usb_buf[0]; + } + sd->contrast = contrast >> 2; +} + static void setcolors(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; @@ -492,6 +538,16 @@ static void getcolors(struct gspca_dev *gspca_dev) } } +static void setautogain(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + if (sd->autogain) + sd->ag_cnt = AG_CNT_START; + else + sd->ag_cnt = -1; +} + static void Et_init1(struct gspca_dev *gspca_dev) { __u8 value; @@ -614,6 +670,7 @@ static int sd_config(struct gspca_dev *gspca_dev, sd->contrast = CONTRAST_DEF; sd->colors = COLOR_DEF; sd->autogain = AUTOGAIN_DEF; + sd->ag_cnt = -1; return 0; } @@ -641,6 +698,8 @@ static void sd_start(struct gspca_dev *gspca_dev) else Et_init2(gspca_dev); + setautogain(gspca_dev); + reg_w_val(gspca_dev, ET_RESET_ALL, 0x08); et_video(gspca_dev, 1); /* video on */ } @@ -658,52 +717,6 @@ static void sd_close(struct gspca_dev *gspca_dev) { } -static void setbrightness(struct gspca_dev *gspca_dev) -{ - struct sd *sd = (struct sd *) gspca_dev; - int i; - __u8 brightness = sd->brightness; - - for (i = 0; i < 4; i++) - reg_w_val(gspca_dev, ET_O_RED + i, brightness); -} - -static void getbrightness(struct gspca_dev *gspca_dev) -{ - struct sd *sd = (struct sd *) gspca_dev; - int i; - int brightness = 0; - - for (i = 0; i < 4; i++) { - reg_r(gspca_dev, ET_O_RED + i, 1); - brightness += gspca_dev->usb_buf[0]; - } - sd->brightness = brightness >> 3; -} - -static void setcontrast(struct gspca_dev *gspca_dev) -{ - struct sd *sd = (struct sd *) gspca_dev; - __u8 RGBG[] = { 0x80, 0x80, 0x80, 0x80, 0x00, 0x00 }; - __u8 contrast = sd->contrast; - - memset(RGBG, contrast, sizeof(RGBG) - 2); - reg_w(gspca_dev, ET_G_RED, RGBG, 6); -} - -static void getcontrast(struct gspca_dev *gspca_dev) -{ - struct sd *sd = (struct sd *) gspca_dev; - int i; - int contrast = 0; - - for (i = 0; i < 4; i++) { - reg_r(gspca_dev, ET_G_RED + i, 1); - contrast += gspca_dev->usb_buf[0]; - } - sd->contrast = contrast >> 2; -} - static __u8 Et_getgainG(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; @@ -733,15 +746,22 @@ static void Et_setgainG(struct gspca_dev *gspca_dev, __u8 gain) #define LIMIT(color) \ (unsigned char)((color > 0xff)?0xff:((color < 0)?0:color)) -static void setautogain(struct gspca_dev *gspca_dev) +static void do_autogain(struct gspca_dev *gspca_dev) { - __u8 luma = 0; + struct sd *sd = (struct sd *) gspca_dev; + __u8 luma; __u8 luma_mean = 128; __u8 luma_delta = 20; __u8 spring = 4; - int Gbright = 0; + int Gbright; __u8 r, g, b; + if (sd->ag_cnt < 0) + return; + if (--sd->ag_cnt >= 0) + return; + sd->ag_cnt = AG_CNT_START; + Gbright = Et_getgainG(gspca_dev); reg_r(gspca_dev, ET_LUMA_CENTER, 4); g = (gspca_dev->usb_buf[0] + gspca_dev->usb_buf[3]) >> 1; @@ -768,7 +788,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, __u8 *data, /* isoc packet */ int len) /* iso packet length */ { - struct sd *sd; int seqframe; seqframe = data[0] & 0x3f; @@ -783,13 +802,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, data, 0); gspca_frame_add(gspca_dev, FIRST_PACKET, frame, data, len); - sd = (struct sd *) gspca_dev; - if (sd->ag_cnt >= 0) { - if (--sd->ag_cnt < 0) { - sd->ag_cnt = AG_CNT_START; - setautogain(gspca_dev); - } - } return; } if (len) { @@ -862,10 +874,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->autogain = val; - if (val) - sd->ag_cnt = AG_CNT_START; - else - sd->ag_cnt = -1; + if (gspca_dev->streaming) + setautogain(gspca_dev); return 0; } @@ -889,6 +899,7 @@ static struct sd_desc sd_desc = { .stop0 = sd_stop0, .close = sd_close, .pkt_scan = sd_pkt_scan, + .dq_callback = do_autogain, }; /* -- module initialisation -- */ diff --git a/drivers/media/video/gspca/pac7311.c b/drivers/media/video/gspca/pac7311.c index ea3d7021f401..815bea6edc44 100644 --- a/drivers/media/video/gspca/pac7311.c +++ b/drivers/media/video/gspca/pac7311.c @@ -31,7 +31,9 @@ MODULE_LICENSE("GPL"); struct sd { struct gspca_dev gspca_dev; /* !! must be the first item */ - int avg_lum; + int lum_sum; + atomic_t avg_lum; + atomic_t do_gain; unsigned char brightness; unsigned char contrast; @@ -271,6 +273,7 @@ static int sd_config(struct gspca_dev *gspca_dev, sd->contrast = CONTRAST_DEF; sd->colors = COLOR_DEF; sd->autogain = AUTOGAIN_DEF; + sd->ag_cnt = -1; return 0; } @@ -311,6 +314,18 @@ static void setcolors(struct gspca_dev *gspca_dev) PDEBUG(D_CONF|D_STREAM, "color: %i", sd->colors); } +static void setautogain(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + if (sd->autogain) { + sd->lum_sum = 0; + sd->ag_cnt = AG_CNT_START; + } else { + sd->ag_cnt = -1; + } +} + /* this function is called at open time */ static int sd_open(struct gspca_dev *gspca_dev) { @@ -320,8 +335,6 @@ static int sd_open(struct gspca_dev *gspca_dev) static void sd_start(struct gspca_dev *gspca_dev) { - struct sd *sd = (struct sd *) gspca_dev; - reg_w(gspca_dev, 0xff, 0x01); reg_w_buf(gspca_dev, 0x0002, "\x48\x0a\x40\x08\x00\x00\x08\x00", 8); reg_w_buf(gspca_dev, 0x000a, "\x06\xff\x11\xff\x5a\x30\x90\x4c", 8); @@ -394,6 +407,7 @@ static void sd_start(struct gspca_dev *gspca_dev) setcontrast(gspca_dev); setbrightness(gspca_dev); setcolors(gspca_dev); + setautogain(gspca_dev); /* set correct resolution */ switch (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].priv) { @@ -431,13 +445,6 @@ static void sd_start(struct gspca_dev *gspca_dev) reg_w(gspca_dev, 0xff, 0x01); reg_w(gspca_dev, 0x78, 0x04); reg_w(gspca_dev, 0x78, 0x05); - - if (sd->autogain) { - sd->ag_cnt = AG_CNT_START; - sd->avg_lum = 0; - } else { - sd->ag_cnt = -1; - } } static void sd_stopN(struct gspca_dev *gspca_dev) @@ -473,13 +480,20 @@ static void sd_close(struct gspca_dev *gspca_dev) reg_w(gspca_dev, 0x78, 0x44); /* Bit_0=start stream, Bit_7=LED */ } -static void setautogain(struct gspca_dev *gspca_dev, int luma) +static void do_autogain(struct gspca_dev *gspca_dev) { + struct sd *sd = (struct sd *) gspca_dev; + int luma; int luma_mean = 128; int luma_delta = 20; __u8 spring = 5; int Gbright; + if (!atomic_read(&sd->do_gain)) + return; + atomic_set(&sd->do_gain, 0); + + luma = atomic_read(&sd->avg_lum); Gbright = reg_r(gspca_dev, 0x02); PDEBUG(D_FRAM, "luma mean %d", luma); if (luma < luma_mean - luma_delta || @@ -523,12 +537,13 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, /* start of frame */ if (sd->ag_cnt >= 0 && p > 28) { - sd->avg_lum += data[p - 23]; + sd->lum_sum += data[p - 23]; if (--sd->ag_cnt < 0) { sd->ag_cnt = AG_CNT_START; - setautogain(gspca_dev, - sd->avg_lum / AG_CNT_START); - sd->avg_lum = 0; + atomic_set(&sd->avg_lum, + sd->lum_sum / AG_CNT_START); + sd->lum_sum = 0; + atomic_set(&sd->do_gain, 1); } } @@ -677,12 +692,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->autogain = val; - if (val) { - sd->ag_cnt = AG_CNT_START; - sd->avg_lum = 0; - } else { - sd->ag_cnt = -1; - } + if (gspca_dev->streaming) + setautogain(gspca_dev); return 0; } @@ -706,6 +717,7 @@ static struct sd_desc sd_desc = { .stop0 = sd_stop0, .close = sd_close, .pkt_scan = sd_pkt_scan, + .dq_callback = do_autogain, }; /* -- module initialisation -- */ diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c index b60ff600a757..245a30ec5fb1 100644 --- a/drivers/media/video/gspca/sonixj.c +++ b/drivers/media/video/gspca/sonixj.c @@ -32,7 +32,7 @@ MODULE_LICENSE("GPL"); struct sd { struct gspca_dev gspca_dev; /* !! must be the first item */ - int avg_lum; + atomic_t avg_lum; unsigned int exposure; unsigned short brightness; @@ -781,6 +781,8 @@ static int sd_config(struct gspca_dev *gspca_dev, sd->contrast = CONTRAST_DEF; sd->colors = COLOR_DEF; sd->autogain = AUTOGAIN_DEF; + sd->ag_cnt = -1; + return 0; } @@ -946,6 +948,22 @@ static void setcolors(struct gspca_dev *gspca_dev) reg_w1(gspca_dev, 0x05, data); } +static void setautogain(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + switch (sd->sensor) { + case SENSOR_HV7131R: + case SENSOR_MO4000: + case SENSOR_MI0360: + if (sd->autogain) + sd->ag_cnt = AG_CNT_START; + else + sd->ag_cnt = -1; + break; + } +} + /* -- start the camera -- */ static void sd_start(struct gspca_dev *gspca_dev) { @@ -1078,6 +1096,7 @@ static void sd_start(struct gspca_dev *gspca_dev) reg_w1(gspca_dev, 0x01, reg1); setbrightness(gspca_dev); setcontrast(gspca_dev); + setautogain(gspca_dev); } static void sd_stopN(struct gspca_dev *gspca_dev) @@ -1124,16 +1143,23 @@ static void sd_close(struct gspca_dev *gspca_dev) { } -static void setautogain(struct gspca_dev *gspca_dev) +static void do_autogain(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; - /* Thanks S., without your advice, autobright should not work :) */ int delta; - int expotimes = 0; + int expotimes; __u8 luma_mean = 130; __u8 luma_delta = 20; - delta = sd->avg_lum; + /* Thanks S., without your advice, autobright should not work :) */ + if (sd->ag_cnt < 0) + return; + if (--sd->ag_cnt >= 0) + return; + sd->ag_cnt = AG_CNT_START; + + delta = atomic_read(&sd->avg_lum); + PDEBUG(D_FRAM, "mean lum %d", delta); if (delta < luma_mean - luma_delta || delta > luma_mean + luma_delta) { switch (sd->sensor) { @@ -1145,8 +1171,9 @@ static void setautogain(struct gspca_dev *gspca_dev) sd->exposure = setexposure(gspca_dev, (unsigned int) (expotimes << 8)); break; - case SENSOR_MO4000: - case SENSOR_MI0360: + default: +/* case SENSOR_MO4000: */ +/* case SENSOR_MI0360: */ expotimes = sd->exposure; expotimes += (luma_mean - delta) >> 6; if (expotimes < 0) @@ -1159,6 +1186,8 @@ static void setautogain(struct gspca_dev *gspca_dev) } } +/* scan the URB packets */ +/* This function is run at interrupt level. */ static void sd_pkt_scan(struct gspca_dev *gspca_dev, struct gspca_frame *frame, /* target */ __u8 *data, /* isoc packet */ @@ -1175,9 +1204,6 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, frame, data, sof + 2); if (sd->ag_cnt < 0) return; - if (--sd->ag_cnt >= 0) - return; - sd->ag_cnt = AG_CNT_START; /* w1 w2 w3 */ /* w4 w5 w6 */ /* w7 w8 */ @@ -1192,9 +1218,7 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, /* w5 */ avg_lum += ((data[sof + 31] << 8) | data[sof + 32]) >> 4; avg_lum >>= 4; - sd->avg_lum = avg_lum; - PDEBUG(D_PACK, "mean lum %d", avg_lum); - setautogain(gspca_dev); + atomic_set(&sd->avg_lum, avg_lum); return; } if (gspca_dev->last_packet_type == LAST_PACKET) { @@ -1321,10 +1345,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->autogain = val; - if (val) - sd->ag_cnt = AG_CNT_START; - else - sd->ag_cnt = -1; + if (gspca_dev->streaming) + setautogain(gspca_dev); return 0; } @@ -1348,6 +1370,7 @@ static const struct sd_desc sd_desc = { .stop0 = sd_stop0, .close = sd_close, .pkt_scan = sd_pkt_scan, + .dq_callback = do_autogain, }; /* -- module initialisation -- */ diff --git a/drivers/media/video/gspca/spca561.c b/drivers/media/video/gspca/spca561.c index a26174508cb9..1073ac3d2ec6 100644 --- a/drivers/media/video/gspca/spca561.c +++ b/drivers/media/video/gspca/spca561.c @@ -644,6 +644,18 @@ static void setcontrast(struct gspca_dev *gspca_dev) } } +static void setautogain(struct gspca_dev *gspca_dev) +{ + struct sd *sd = (struct sd *) gspca_dev; + + if (sd->chip_revision == Rev072A) { + if (sd->autogain) + sd->ag_cnt = AG_CNT_START; + else + sd->ag_cnt = -1; + } +} + static void sd_start(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; @@ -671,6 +683,7 @@ static void sd_start(struct gspca_dev *gspca_dev) reg_w_val(dev, 0x8500, mode); /* mode */ reg_w_val(dev, 0x8700, Clck); /* 0x27 clock */ reg_w_val(dev, 0x8112, 0x10 | 0x20); + setautogain(gspca_dev); break; default: /* case Rev012A: */ @@ -720,18 +733,24 @@ static void sd_close(struct gspca_dev *gspca_dev) reg_w_val(gspca_dev->dev, 0x8114, 0); } -static void setautogain(struct gspca_dev *gspca_dev) +static void do_autogain(struct gspca_dev *gspca_dev) { struct sd *sd = (struct sd *) gspca_dev; - int expotimes = 0; - int pixelclk = 0; - int gainG = 0; + int expotimes; + int pixelclk; + int gainG; __u8 R, Gr, Gb, B; int y; __u8 luma_mean = 110; __u8 luma_delta = 20; __u8 spring = 4; + if (sd->ag_cnt < 0) + return; + if (--sd->ag_cnt >= 0) + return; + sd->ag_cnt = AG_CNT_START; + switch (sd->chip_revision) { case Rev072A: reg_r(gspca_dev, 0x8621, 1); @@ -795,18 +814,10 @@ static void sd_pkt_scan(struct gspca_dev *gspca_dev, __u8 *data, /* isoc packet */ int len) /* iso packet length */ { - struct sd *sd = (struct sd *) gspca_dev; - switch (data[0]) { case 0: /* start of frame */ frame = gspca_frame_add(gspca_dev, LAST_PACKET, frame, data, 0); - if (sd->ag_cnt >= 0) { - if (--sd->ag_cnt < 0) { - sd->ag_cnt = AG_CNT_START; - setautogain(gspca_dev); - } - } data += SPCA561_OFFSET_DATA; len -= SPCA561_OFFSET_DATA; if (data[1] & 0x10) { @@ -944,10 +955,8 @@ static int sd_setautogain(struct gspca_dev *gspca_dev, __s32 val) struct sd *sd = (struct sd *) gspca_dev; sd->autogain = val; - if (val) - sd->ag_cnt = AG_CNT_START; - else - sd->ag_cnt = -1; + if (gspca_dev->streaming) + setautogain(gspca_dev); return 0; } @@ -971,6 +980,7 @@ static const struct sd_desc sd_desc = { .stop0 = sd_stop0, .close = sd_close, .pkt_scan = sd_pkt_scan, + .dq_callback = do_autogain, }; /* -- module initialisation -- */ -- cgit v1.2.3 From fcf5cb2406827fc9d3f3fe260ac883ef72b8bac0 Mon Sep 17 00:00:00 2001 From: Rabin Vincent Date: Sun, 3 Aug 2008 07:58:54 -0300 Subject: V4L/DVB (8605): gspca: Fix of gspca_zc3xx oops - 2.6.27-rc1 Bad mini/max check in setting control values (the gamma in zc3xx could be set to null). Signed-off-by: Rabin Vincent Signed-off-by: Jean-Francois Moine Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/gspca/gspca.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c index 7f773e378979..15d302b28b79 100644 --- a/drivers/media/video/gspca/gspca.c +++ b/drivers/media/video/gspca/gspca.c @@ -904,7 +904,7 @@ static int vidioc_s_ctrl(struct file *file, void *priv, if (ctrl->id != ctrls->qctrl.id) continue; if (ctrl->value < ctrls->qctrl.minimum - && ctrl->value > ctrls->qctrl.maximum) + || ctrl->value > ctrls->qctrl.maximum) return -ERANGE; PDEBUG(D_CONF, "set ctrl [%08x] = %d", ctrl->id, ctrl->value); if (mutex_lock_interruptible(&gspca_dev->usb_lock)) -- cgit v1.2.3 From d483b730681fa527f343dcc859185e06d60ae121 Mon Sep 17 00:00:00 2001 From: Robert Lowery Date: Wed, 30 Jul 2008 19:43:11 -0300 Subject: V4L/DVB (8607): cxusb: fix OOPS and broken tuning regression on FusionHDTV Dual Digital 4 quoting Robert Lowery: I think I've found the cause of the oops. [...] BTW it appears I have fixed my tuning problems with the updated patch below. This reverts a change Mauro made a while back. All is good now :) [...] The good news is that I've got a better patch that definitely works this time and even better, makes use of the standard firmware (rather than the Australian specific one). ...based on an earlier patch by Hans-Frieder Vogt: http://www.linuxtv.org/pipermail/linux-dvb/2008-May/026280.html Signed-off-by: Robert Lowery Signed-off-by: Michael Krufky Signed-off-by: Mauro Carvalho Chehab --- drivers/media/dvb/dvb-usb/cxusb.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/dvb/dvb-usb/cxusb.c b/drivers/media/dvb/dvb-usb/cxusb.c index 578afce6884c..aaa0b6f0b521 100644 --- a/drivers/media/dvb/dvb-usb/cxusb.c +++ b/drivers/media/dvb/dvb-usb/cxusb.c @@ -565,7 +565,8 @@ static int cxusb_lgh064f_tuner_attach(struct dvb_usb_adapter *adap) static int dvico_bluebird_xc2028_callback(void *ptr, int command, int arg) { - struct dvb_usb_device *d = ptr; + struct dvb_usb_adapter *adap = ptr; + struct dvb_usb_device *d = adap->dev; switch (command) { case XC2028_TUNER_RESET: @@ -593,9 +594,9 @@ static int cxusb_dvico_xc3028_tuner_attach(struct dvb_usb_adapter *adap) .callback = dvico_bluebird_xc2028_callback, }; static struct xc2028_ctrl ctl = { - .fname = "xc3028-dvico-au-01.fw", + .fname = "xc3028-v27.fw", .max_len = 64, - .scode_table = XC3028_FE_ZARLINK456, + .demod = XC3028_FE_ZARLINK456, }; fe = dvb_attach(xc2028_attach, adap->fe, &cfg); -- cgit v1.2.3 From 01c1e4ca8ec39d21be0cd9d1b300d479de97298a Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 1 Aug 2008 19:48:51 -0300 Subject: V4L/DVB (8609): media: Clean up platform_driver_unregister() bogosity. So, platform_driver_unregister() doesn't actually have a return value, nor do any of the void __exit routines. It's reassuring to know that people copy and paste blindly. This completely blew up my compiler. Signed-off-by: Paul Mundt Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/pxa_camera.c | 2 +- drivers/media/video/sh_mobile_ceu_camera.c | 2 +- drivers/media/video/soc_camera_platform.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index b15f82c49766..28d8fd0679b4 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c @@ -1198,7 +1198,7 @@ static int __devinit pxa_camera_init(void) static void __exit pxa_camera_exit(void) { - return platform_driver_unregister(&pxa_camera_driver); + platform_driver_unregister(&pxa_camera_driver); } module_init(pxa_camera_init); diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c index f7ca3cb9340a..318754e73132 100644 --- a/drivers/media/video/sh_mobile_ceu_camera.c +++ b/drivers/media/video/sh_mobile_ceu_camera.c @@ -647,7 +647,7 @@ static int __init sh_mobile_ceu_init(void) static void __exit sh_mobile_ceu_exit(void) { - return platform_driver_unregister(&sh_mobile_ceu_driver); + platform_driver_unregister(&sh_mobile_ceu_driver); } module_init(sh_mobile_ceu_init); diff --git a/drivers/media/video/soc_camera_platform.c b/drivers/media/video/soc_camera_platform.c index eefb0327ebb6..1adc257ebdb9 100644 --- a/drivers/media/video/soc_camera_platform.c +++ b/drivers/media/video/soc_camera_platform.c @@ -187,7 +187,7 @@ static int __init soc_camera_platform_module_init(void) static void __exit soc_camera_platform_module_exit(void) { - return platform_driver_unregister(&soc_camera_platform_driver); + platform_driver_unregister(&soc_camera_platform_driver); } module_init(soc_camera_platform_module_init); -- cgit v1.2.3 From 2e521061db61a35dd64ea85a1642f9a9dfde2872 Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Fri, 1 Aug 2008 20:14:50 -0300 Subject: V4L/DVB (8610): Add suspend/resume capabilities to soc_camera. Add suspend/resume hooks to call soc operation specific suspend and resume functions. This ensures the camera chip has been previously resumed, as well as the camera bus. These hooks in camera chip drivers should save/restore chip context between suspend and resume time. Signed-off-by: Robert Jarzmik Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/soc_camera.c | 26 ++++++++++++++++++++++++++ include/media/soc_camera.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c index b6be5ee678b6..66ebe5956a87 100644 --- a/drivers/media/video/soc_camera.c +++ b/drivers/media/video/soc_camera.c @@ -732,10 +732,36 @@ static int soc_camera_remove(struct device *dev) return 0; } +static int soc_camera_suspend(struct device *dev, pm_message_t state) +{ + struct soc_camera_device *icd = to_soc_camera_dev(dev); + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + int ret = 0; + + if (ici->ops->suspend) + ret = ici->ops->suspend(icd, state); + + return ret; +} + +static int soc_camera_resume(struct device *dev) +{ + struct soc_camera_device *icd = to_soc_camera_dev(dev); + struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); + int ret = 0; + + if (ici->ops->resume) + ret = ici->ops->resume(icd); + + return ret; +} + static struct bus_type soc_camera_bus_type = { .name = "soc-camera", .probe = soc_camera_probe, .remove = soc_camera_remove, + .suspend = soc_camera_suspend, + .resume = soc_camera_resume, }; static struct device_driver ic_drv = { diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h index 1de98f150e99..d548de326722 100644 --- a/include/media/soc_camera.h +++ b/include/media/soc_camera.h @@ -14,6 +14,7 @@ #include #include +#include struct soc_camera_device { struct list_head list; @@ -63,6 +64,8 @@ struct soc_camera_host_ops { struct module *owner; int (*add)(struct soc_camera_device *); void (*remove)(struct soc_camera_device *); + int (*suspend)(struct soc_camera_device *, pm_message_t state); + int (*resume)(struct soc_camera_device *); int (*set_fmt_cap)(struct soc_camera_device *, __u32, struct v4l2_rect *); int (*try_fmt_cap)(struct soc_camera_device *, struct v4l2_format *); @@ -111,6 +114,8 @@ struct soc_camera_ops { struct module *owner; int (*probe)(struct soc_camera_device *); void (*remove)(struct soc_camera_device *); + int (*suspend)(struct soc_camera_device *, pm_message_t state); + int (*resume)(struct soc_camera_device *); int (*init)(struct soc_camera_device *); int (*release)(struct soc_camera_device *); int (*start_capture)(struct soc_camera_device *); -- cgit v1.2.3 From 3f6ac497b036533d1a63ba04fdbe710c55e14cda Mon Sep 17 00:00:00 2001 From: Robert Jarzmik Date: Sat, 2 Aug 2008 07:10:04 -0300 Subject: V4L/DVB (8611): Add suspend/resume to pxa_camera driver PXA suspend switches off DMA core, which loses all context of previously assigned descriptors. As pxa_camera driver relies on DMA transfers, setup the lost descriptors on resume and retrigger frame acquisition if needed. Signed-off-by: Robert Jarzmik Signed-off-by: Guennadi Liakhovetski Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/pxa_camera.c | 56 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c index 28d8fd0679b4..ead87ddaf7fb 100644 --- a/drivers/media/video/pxa_camera.c +++ b/drivers/media/video/pxa_camera.c @@ -128,6 +128,8 @@ struct pxa_camera_dev { struct pxa_buffer *active; struct pxa_dma_desc *sg_tail[3]; + + u32 save_cicr[5]; }; static const char *pxa_cam_driver_description = "PXA_Camera"; @@ -997,10 +999,64 @@ static int pxa_camera_querycap(struct soc_camera_host *ici, return 0; } +static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct pxa_camera_dev *pcdev = ici->priv; + int i = 0, ret = 0; + + pcdev->save_cicr[i++] = CICR0; + pcdev->save_cicr[i++] = CICR1; + pcdev->save_cicr[i++] = CICR2; + pcdev->save_cicr[i++] = CICR3; + pcdev->save_cicr[i++] = CICR4; + + if ((pcdev->icd) && (pcdev->icd->ops->suspend)) + ret = pcdev->icd->ops->suspend(pcdev->icd, state); + + return ret; +} + +static int pxa_camera_resume(struct soc_camera_device *icd) +{ + struct soc_camera_host *ici = + to_soc_camera_host(icd->dev.parent); + struct pxa_camera_dev *pcdev = ici->priv; + int i = 0, ret = 0; + + DRCMR68 = pcdev->dma_chans[0] | DRCMR_MAPVLD; + DRCMR69 = pcdev->dma_chans[1] | DRCMR_MAPVLD; + DRCMR70 = pcdev->dma_chans[2] | DRCMR_MAPVLD; + + CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB; + CICR1 = pcdev->save_cicr[i++]; + CICR2 = pcdev->save_cicr[i++]; + CICR3 = pcdev->save_cicr[i++]; + CICR4 = pcdev->save_cicr[i++]; + + if ((pcdev->icd) && (pcdev->icd->ops->resume)) + ret = pcdev->icd->ops->resume(pcdev->icd); + + /* Restart frame capture if active buffer exists */ + if (!ret && pcdev->active) { + /* Reset the FIFOs */ + CIFR |= CIFR_RESET_F; + /* Enable End-Of-Frame Interrupt */ + CICR0 &= ~CICR0_EOFM; + /* Restart the Capture Interface */ + CICR0 |= CICR0_ENB; + } + + return ret; +} + static struct soc_camera_host_ops pxa_soc_camera_host_ops = { .owner = THIS_MODULE, .add = pxa_camera_add_device, .remove = pxa_camera_remove_device, + .suspend = pxa_camera_suspend, + .resume = pxa_camera_resume, .set_fmt_cap = pxa_camera_set_fmt_cap, .try_fmt_cap = pxa_camera_try_fmt_cap, .init_videobuf = pxa_camera_init_videobuf, -- cgit v1.2.3 From 835f09c6594aa98cbfae05c5466a81fda3081d2c Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 30 Jul 2008 18:54:48 -0300 Subject: V4L/DVB (8616): uvcvideo: Add support for two Bison Electronics webcams The Bison Electronics 5986:0300 and 5986:0303 webcams require the UVC_QUIRK_PROBE_MINMAX quirk. Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/uvc/uvc_driver.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c index b3c4d75e8490..7e102034d38d 100644 --- a/drivers/media/video/uvc/uvc_driver.c +++ b/drivers/media/video/uvc/uvc_driver.c @@ -1884,7 +1884,7 @@ static struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_PROBE_MINMAX }, - /* Packard Bell OEM Webcam */ + /* Packard Bell OEM Webcam - Bison Electronics */ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO, .idVendor = 0x5986, @@ -1893,7 +1893,7 @@ static struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_PROBE_MINMAX }, - /* Acer Crystal Eye webcam */ + /* Acer Crystal Eye webcam - Bison Electronics */ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO, .idVendor = 0x5986, @@ -1902,7 +1902,7 @@ static struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_PROBE_MINMAX }, - /* Medion Akoya Mini E1210 */ + /* Medion Akoya Mini E1210 - Bison Electronics */ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO, .idVendor = 0x5986, @@ -1911,7 +1911,7 @@ static struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_PROBE_MINMAX }, - /* Acer OrbiCam - Unknown vendor */ + /* Acer OrbiCam - Bison Electronics */ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE | USB_DEVICE_ID_MATCH_INT_INFO, .idVendor = 0x5986, @@ -1920,6 +1920,24 @@ static struct usb_device_id uvc_ids[] = { .bInterfaceSubClass = 1, .bInterfaceProtocol = 0, .driver_info = UVC_QUIRK_PROBE_MINMAX }, + /* Bison Electronics */ + { .match_flags = USB_DEVICE_ID_MATCH_DEVICE + | USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x5986, + .idProduct = 0x0300, + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 0, + .driver_info = UVC_QUIRK_PROBE_MINMAX }, + /* Clevo M570TU - Bison Electronics */ + { .match_flags = USB_DEVICE_ID_MATCH_DEVICE + | USB_DEVICE_ID_MATCH_INT_INFO, + .idVendor = 0x5986, + .idProduct = 0x0303, + .bInterfaceClass = USB_CLASS_VIDEO, + .bInterfaceSubClass = 1, + .bInterfaceProtocol = 0, + .driver_info = UVC_QUIRK_PROBE_MINMAX }, /* Generic USB Video Class */ { USB_INTERFACE_INFO(USB_CLASS_VIDEO, 1, 0) }, {} -- cgit v1.2.3 From 04793dd041bbb88a39b768b714c725de2c339b51 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Thu, 31 Jul 2008 17:11:12 -0300 Subject: V4L/DVB (8617): uvcvideo: don't use stack-based buffers for USB transfers. Data buffers on the stack are not allowed for USB I/O. Use dynamically allocated buffers instead. Signed-off-by: Bruce Schmid Signed-off-by: Laurent Pinchart Signed-off-by: Mauro Carvalho Chehab --- drivers/media/video/uvc/uvc_ctrl.c | 33 +++++++++++++++++++++------------ drivers/media/video/uvc/uvc_video.c | 33 ++++++++++++++++++++++----------- 2 files changed, 43 insertions(+), 23 deletions(-) diff --git a/drivers/media/video/uvc/uvc_ctrl.c b/drivers/media/video/uvc/uvc_ctrl.c index 626f4ad7e876..6ef3e5297de8 100644 --- a/drivers/media/video/uvc/uvc_ctrl.c +++ b/drivers/media/video/uvc/uvc_ctrl.c @@ -585,13 +585,17 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, struct uvc_control_mapping *mapping; struct uvc_menu_info *menu; unsigned int i; - __u8 data[8]; + __u8 *data; int ret; ctrl = uvc_find_control(video, v4l2_ctrl->id, &mapping); if (ctrl == NULL) return -EINVAL; + data = kmalloc(8, GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + memset(v4l2_ctrl, 0, sizeof *v4l2_ctrl); v4l2_ctrl->id = mapping->id; v4l2_ctrl->type = mapping->v4l2_type; @@ -604,8 +608,8 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, if (ctrl->info->flags & UVC_CONTROL_GET_DEF) { if ((ret = uvc_query_ctrl(video->dev, GET_DEF, ctrl->entity->id, video->dev->intfnum, ctrl->info->selector, - &data, ctrl->info->size)) < 0) - return ret; + data, ctrl->info->size)) < 0) + goto out; v4l2_ctrl->default_value = uvc_get_le_value(data, mapping); } @@ -623,13 +627,15 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, } } - return 0; + ret = 0; + goto out; case V4L2_CTRL_TYPE_BOOLEAN: v4l2_ctrl->minimum = 0; v4l2_ctrl->maximum = 1; v4l2_ctrl->step = 1; - return 0; + ret = 0; + goto out; default: break; @@ -638,26 +644,29 @@ int uvc_query_v4l2_ctrl(struct uvc_video_device *video, if (ctrl->info->flags & UVC_CONTROL_GET_MIN) { if ((ret = uvc_query_ctrl(video->dev, GET_MIN, ctrl->entity->id, video->dev->intfnum, ctrl->info->selector, - &data, ctrl->info->size)) < 0) - return ret; + data, ctrl->info->size)) < 0) + goto out; v4l2_ctrl->minimum = uvc_get_le_value(data, mapping); } if (ctrl->info->flags & UVC_CONTROL_GET_MAX) { if ((ret = uvc_query_ctrl(video->dev, GET_MAX, ctrl->entity->id, video->dev->intfnum, ctrl->info->selector, - &data, ctrl->info->size)) < 0) - return ret; + data, ctrl->info->size)) < 0) + goto out; v4l2_ctrl->maximum = uvc_get_le_value(data, mapping); } if (ctrl->info->flags & UVC_CONTROL_GET_RES) { if ((ret = uvc_query_ctrl(video->dev, GET_RES, ctrl->entity->id, video->dev->intfnum, ctrl->info->selector, - &data, ctrl->info->size)) < 0) - return ret; + data, ctrl->info->size)) < 0) + goto out; v4l2_ctrl->step = uvc_get_le_value(data, mapping); } - return 0; + ret = 0; +out: + kfree(data); + return ret; } diff --git a/drivers/media/video/uvc/uvc_video.c b/drivers/media/video/uvc/uvc_video.c index ad63794fda77..6854ac78a161 100644 --- a/drivers/media/video/uvc/uvc_video.c +++ b/drivers/media/video/uvc/uvc_video.c @@ -90,17 +90,20 @@ static void uvc_fixup_buffer_size(struct uvc_video_device *video, static int uvc_get_video_ctrl(struct uvc_video_device *video, struct uvc_streaming_control *ctrl, int probe, __u8 query) { - __u8 data[34]; - __u8 size; + __u8 *data; + __u16 size; int ret; size = video->dev->uvc_version >= 0x0110 ? 34 : 26; + data = kmalloc(size, GFP_KERNEL); + if (data == NULL) + return -ENOMEM; + ret = __uvc_query_ctrl(video->dev, query, 0, video->streaming->intfnum, - probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, + probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size, UVC_CTRL_STREAMING_TIMEOUT); - if (ret < 0) - return ret; + goto out; ctrl->bmHint = le16_to_cpup((__le16 *)&data[0]); ctrl->bFormatIndex = data[2]; @@ -136,17 +139,22 @@ static int uvc_get_video_ctrl(struct uvc_video_device *video, */ uvc_fixup_buffer_size(video, ctrl); - return 0; +out: + kfree(data); + return ret; } int uvc_set_video_ctrl(struct uvc_video_device *video, struct uvc_streaming_control *ctrl, int probe) { - __u8 data[34]; - __u8 size; + __u8 *data; + __u16 size; + int ret; size = video->dev->uvc_version >= 0x0110 ? 34 : 26; - memset(data, 0, sizeof data); + data = kzalloc(size, GFP_KERNEL); + if (data == NULL) + return -ENOMEM; *(__le16 *)&data[0] = cpu_to_le16(ctrl->bmHint); data[2] = ctrl->bFormatIndex; @@ -174,10 +182,13 @@ int uvc_set_video_ctrl(struct uvc_video_device *video, data[33] = ctrl->bMaxVersion; } - return __uvc_query_ctrl(video->dev, SET_CUR, 0, + ret = __uvc_query_ctrl(video->dev, SET_CUR, 0, video->streaming->intfnum, - probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, &data, size, + probe ? VS_PROBE_CONTROL : VS_COMMIT_CONTROL, data, size, UVC_CTRL_STREAMING_TIMEOUT); + + kfree(data); + return ret; } int uvc_probe_video(struct uvc_video_device *video, -- cgit v1.2.3 From f7108f91cdcaca07c6a99777b2724093294f36ee Mon Sep 17 00:00:00 2001 From: Nikanth Karthikesan Date: Mon, 4 Aug 2008 10:56:07 +0200 Subject: cciss: return -EFAULT if copy_from_user() fails Return -EFAULT instead of -ENOMEM if copy_from_user() fails. Signed-off-by: Nikanth Karthikesan Acked-by: Mike Miller Signed-off-by: Jens Axboe --- drivers/block/cciss.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 0ce0c279aabf..aeaf465922e5 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -1134,7 +1134,7 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, if (ioc->Request.Type.Direction == XFER_WRITE) { if (copy_from_user (buff[sg_used], data_ptr, sz)) { - status = -ENOMEM; + status = -EFAULT; goto cleanup1; } } else { -- cgit v1.2.3 From a72da29b6cbc5cf918567f2a0d76df6871e94b01 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:51 +0200 Subject: cciss: make rebuild_lun_table behave better This patch makes the rebuild_lun_table smart enough to not rip a logical volume out from under the OS. Without this fix if a customer is running hpacucli to monitor their storage the driver will blindly remove and re-add the disks whenever the utility calls the CCISS_REGNEWD ioctl. Unfortunately, both hpacucli and ACUXE call the ioctl repeatedly. Customers have reported IO coming to a standstill. Calling the ioctl is the problem, this patch is the fix. Signed-off-by: Stephen M. Cameron Signed-off-by: Mike Miller Signed-off-by: Jens Axboe --- drivers/block/cciss.c | 336 ++++++++++++++++++++++++++++++++------------------ drivers/block/cciss.h | 2 + 2 files changed, 216 insertions(+), 122 deletions(-) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index aeaf465922e5..f9f10a15d253 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -1330,13 +1330,46 @@ static void cciss_softirq_done(struct request *rq) spin_unlock_irqrestore(&h->lock, flags); } +/* This function gets the serial number of a logical drive via + * inquiry page 0x83. Serial no. is 16 bytes. If the serial + * number cannot be had, for whatever reason, 16 bytes of 0xff + * are returned instead. + */ +static void cciss_get_serial_no(int ctlr, int logvol, int withirq, + unsigned char *serial_no, int buflen) +{ +#define PAGE_83_INQ_BYTES 64 + int rc; + unsigned char *buf; + + if (buflen > 16) + buflen = 16; + memset(serial_no, 0xff, buflen); + buf = kzalloc(PAGE_83_INQ_BYTES, GFP_KERNEL); + if (!buf) + return; + memset(serial_no, 0, buflen); + if (withirq) + rc = sendcmd_withirq(CISS_INQUIRY, ctlr, buf, + PAGE_83_INQ_BYTES, 1, logvol, 0x83, TYPE_CMD); + else + rc = sendcmd(CISS_INQUIRY, ctlr, buf, + PAGE_83_INQ_BYTES, 1, logvol, 0x83, NULL, TYPE_CMD); + if (rc == IO_OK) + memcpy(serial_no, &buf[8], buflen); + kfree(buf); + return; +} + /* This function will check the usage_count of the drive to be updated/added. - * If the usage_count is zero then the drive information will be updated and - * the disk will be re-registered with the kernel. If not then it will be - * left alone for the next reboot. The exception to this is disk 0 which - * will always be left registered with the kernel since it is also the - * controller node. Any changes to disk 0 will show up on the next - * reboot. + * If the usage_count is zero and it is a heretofore unknown drive, or, + * the drive's capacity, geometry, or serial number has changed, + * then the drive information will be updated and the disk will be + * re-registered with the kernel. If these conditions don't hold, + * then it will be left alone for the next reboot. The exception to this + * is disk 0 which will always be left registered with the kernel since it + * is also the controller node. Any changes to disk 0 will show up on + * the next reboot. */ static void cciss_update_drive_info(int ctlr, int drv_index) { @@ -1347,9 +1380,65 @@ static void cciss_update_drive_info(int ctlr, int drv_index) sector_t total_size; unsigned long flags = 0; int ret = 0; + drive_info_struct *drvinfo; + + /* Get information about the disk and modify the driver structure */ + inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); + drvinfo = kmalloc(sizeof(*drvinfo), GFP_KERNEL); + if (inq_buff == NULL || drvinfo == NULL) + goto mem_msg; + + /* testing to see if 16-byte CDBs are already being used */ + if (h->cciss_read == CCISS_READ_16) { + cciss_read_capacity_16(h->ctlr, drv_index, 1, + &total_size, &block_size); + + } else { + cciss_read_capacity(ctlr, drv_index, 1, + &total_size, &block_size); + + /* if read_capacity returns all F's this volume is >2TB */ + /* in size so we switch to 16-byte CDB's for all */ + /* read/write ops */ + if (total_size == 0xFFFFFFFFULL) { + cciss_read_capacity_16(ctlr, drv_index, 1, + &total_size, &block_size); + h->cciss_read = CCISS_READ_16; + h->cciss_write = CCISS_WRITE_16; + } else { + h->cciss_read = CCISS_READ_10; + h->cciss_write = CCISS_WRITE_10; + } + } + + cciss_geometry_inquiry(ctlr, drv_index, 1, total_size, block_size, + inq_buff, drvinfo); + drvinfo->block_size = block_size; + drvinfo->nr_blocks = total_size + 1; + + cciss_get_serial_no(ctlr, drv_index, 1, drvinfo->serial_no, + sizeof(drvinfo->serial_no)); + + /* Is it the same disk we already know, and nothing's changed? */ + if (h->drv[drv_index].raid_level != -1 && + ((memcmp(drvinfo->serial_no, + h->drv[drv_index].serial_no, 16) == 0) && + drvinfo->block_size == h->drv[drv_index].block_size && + drvinfo->nr_blocks == h->drv[drv_index].nr_blocks && + drvinfo->heads == h->drv[drv_index].heads && + drvinfo->sectors == h->drv[drv_index].sectors && + drvinfo->cylinders == h->drv[drv_index].cylinders)) { + /* The disk is unchanged, nothing to update */ + goto freeret; + } + + /* Not the same disk, or something's changed, so we need to */ + /* deregister it, and re-register it, if it's not in use. */ /* if the disk already exists then deregister it before proceeding */ - if (h->drv[drv_index].raid_level != -1) { + /* (unless it's the first disk (for the controller node). */ + if (h->drv[drv_index].raid_level != -1 && drv_index != 0) { + printk(KERN_WARNING "disk %d has changed.\n", drv_index); spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); h->drv[drv_index].busy_configuring = 1; spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); @@ -1364,43 +1453,23 @@ static void cciss_update_drive_info(int ctlr, int drv_index) /* If the disk is in use return */ if (ret) - return; - - /* Get information about the disk and modify the driver structure */ - inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); - if (inq_buff == NULL) - goto mem_msg; - - /* testing to see if 16-byte CDBs are already being used */ - if (h->cciss_read == CCISS_READ_16) { - cciss_read_capacity_16(h->ctlr, drv_index, 1, - &total_size, &block_size); - goto geo_inq; - } - - cciss_read_capacity(ctlr, drv_index, 1, - &total_size, &block_size); - - /* if read_capacity returns all F's this volume is >2TB in size */ - /* so we switch to 16-byte CDB's for all read/write ops */ - if (total_size == 0xFFFFFFFFULL) { - cciss_read_capacity_16(ctlr, drv_index, 1, - &total_size, &block_size); - h->cciss_read = CCISS_READ_16; - h->cciss_write = CCISS_WRITE_16; - } else { - h->cciss_read = CCISS_READ_10; - h->cciss_write = CCISS_WRITE_10; - } -geo_inq: - cciss_geometry_inquiry(ctlr, drv_index, 1, total_size, block_size, - inq_buff, &h->drv[drv_index]); + goto freeret; + + /* Save the new information from cciss_geometry_inquiry */ + /* and serial number inquiry. */ + h->drv[drv_index].block_size = drvinfo->block_size; + h->drv[drv_index].nr_blocks = drvinfo->nr_blocks; + h->drv[drv_index].heads = drvinfo->heads; + h->drv[drv_index].sectors = drvinfo->sectors; + h->drv[drv_index].cylinders = drvinfo->cylinders; + h->drv[drv_index].raid_level = drvinfo->raid_level; + memcpy(h->drv[drv_index].serial_no, drvinfo->serial_no, 16); ++h->num_luns; disk = h->gendisk[drv_index]; set_capacity(disk, h->drv[drv_index].nr_blocks); - /* if it's the controller it's already added */ + /* if it's the controller (if drv_index == 0) it's already added */ if (drv_index) { disk->queue = blk_init_queue(do_cciss_request, &h->lock); sprintf(disk->disk_name, "cciss/c%dd%d", ctlr, drv_index); @@ -1437,6 +1506,7 @@ geo_inq: freeret: kfree(inq_buff); + kfree(drvinfo); return; mem_msg: printk(KERN_ERR "cciss: out of memory\n"); @@ -1478,7 +1548,6 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) int ctlr = h->ctlr; int num_luns; ReportLunData_struct *ld_buff = NULL; - drive_info_struct *drv = NULL; int return_code; int listlength = 0; int i; @@ -1494,98 +1563,117 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) return -EBUSY; } h->busy_configuring = 1; + spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); - /* if del_disk is NULL then we are being called to add a new disk - * and update the logical drive table. If it is not NULL then - * we will check if the disk is in use or not. - */ - if (del_disk != NULL) { - drv = get_drv(del_disk); - drv->busy_configuring = 1; - spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); - return_code = deregister_disk(del_disk, drv, 1); - drv->busy_configuring = 0; - h->busy_configuring = 0; - return return_code; - } else { - spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); - if (!capable(CAP_SYS_RAWIO)) - return -EPERM; + if (!capable(CAP_SYS_RAWIO)) + return -EPERM; - ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); - if (ld_buff == NULL) - goto mem_msg; - - return_code = sendcmd_withirq(CISS_REPORT_LOG, ctlr, ld_buff, - sizeof(ReportLunData_struct), 0, - 0, 0, TYPE_CMD); - - if (return_code == IO_OK) { - listlength = - be32_to_cpu(*(__be32 *) ld_buff->LUNListLength); - } else { /* reading number of logical volumes failed */ - printk(KERN_WARNING "cciss: report logical volume" - " command failed\n"); - listlength = 0; - goto freeret; - } + ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); + if (ld_buff == NULL) + goto mem_msg; + + return_code = sendcmd_withirq(CISS_REPORT_LOG, ctlr, ld_buff, + sizeof(ReportLunData_struct), 0, + 0, 0, TYPE_CMD); - num_luns = listlength / 8; /* 8 bytes per entry */ - if (num_luns > CISS_MAX_LUN) { - num_luns = CISS_MAX_LUN; - printk(KERN_WARNING "cciss: more luns configured" - " on controller than can be handled by" - " this driver.\n"); + if (return_code == IO_OK) + listlength = be32_to_cpu(*(__be32 *) ld_buff->LUNListLength); + else { /* reading number of logical volumes failed */ + printk(KERN_WARNING "cciss: report logical volume" + " command failed\n"); + listlength = 0; + goto freeret; + } + + num_luns = listlength / 8; /* 8 bytes per entry */ + if (num_luns > CISS_MAX_LUN) { + num_luns = CISS_MAX_LUN; + printk(KERN_WARNING "cciss: more luns configured" + " on controller than can be handled by" + " this driver.\n"); + } + + /* Compare controller drive array to driver's drive array */ + /* to see if any drives are missing on the controller due */ + /* to action of Array Config Utility (user deletes drive) */ + /* and deregister logical drives which have disappeared. */ + for (i = 0; i <= h->highest_lun; i++) { + int j; + drv_found = 0; + for (j = 0; j < num_luns; j++) { + memcpy(&lunid, &ld_buff->LUN[j][0], 4); + lunid = le32_to_cpu(lunid); + if (h->drv[i].LunID == lunid) { + drv_found = 1; + break; + } + } + if (!drv_found) { + /* Deregister it from the OS, it's gone. */ + spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); + h->drv[i].busy_configuring = 1; + spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); + return_code = deregister_disk(h->gendisk[i], + &h->drv[i], 1); + h->drv[i].busy_configuring = 0; } + } - /* Compare controller drive array to drivers drive array. - * Check for updates in the drive information and any new drives - * on the controller. - */ - for (i = 0; i < num_luns; i++) { - int j; + /* Compare controller drive array to driver's drive array. + * Check for updates in the drive information and any new drives + * on the controller due to ACU adding logical drives, or changing + * a logical drive's size, etc. Reregister any new/changed drives + */ + for (i = 0; i < num_luns; i++) { + int j; - drv_found = 0; + drv_found = 0; - lunid = (0xff & - (unsigned int)(ld_buff->LUN[i][3])) << 24; - lunid |= (0xff & - (unsigned int)(ld_buff->LUN[i][2])) << 16; - lunid |= (0xff & - (unsigned int)(ld_buff->LUN[i][1])) << 8; - lunid |= 0xff & (unsigned int)(ld_buff->LUN[i][0]); + memcpy(&lunid, &ld_buff->LUN[i][0], 4); + lunid = le32_to_cpu(lunid); - /* Find if the LUN is already in the drive array - * of the controller. If so then update its info - * if not is use. If it does not exist then find - * the first free index and add it. - */ - for (j = 0; j <= h->highest_lun; j++) { - if (h->drv[j].LunID == lunid) { - drv_index = j; - drv_found = 1; - } + /* Find if the LUN is already in the drive array + * of the driver. If so then update its info + * if not in use. If it does not exist then find + * the first free index and add it. + */ + for (j = 0; j <= h->highest_lun; j++) { + if (h->drv[j].raid_level != -1 && + h->drv[j].LunID == lunid) { + drv_index = j; + drv_found = 1; + break; } + } - /* check if the drive was found already in the array */ - if (!drv_found) { - drv_index = cciss_find_free_drive_index(ctlr); - if (drv_index == -1) - goto freeret; - - /*Check if the gendisk needs to be allocated */ + /* check if the drive was found already in the array */ + if (!drv_found) { + drv_index = cciss_find_free_drive_index(ctlr); + if (drv_index == -1) + goto freeret; + /*Check if the gendisk needs to be allocated */ + if (!h->gendisk[drv_index]) { + h->gendisk[drv_index] = + alloc_disk(1 << NWD_SHIFT); if (!h->gendisk[drv_index]){ - h->gendisk[drv_index] = alloc_disk(1 << NWD_SHIFT); - if (!h->gendisk[drv_index]){ - printk(KERN_ERR "cciss: could not allocate new disk %d\n", drv_index); - goto mem_msg; - } + printk(KERN_ERR "cciss: could not " + "allocate new disk %d\n", + drv_index); + goto mem_msg; } } h->drv[drv_index].LunID = lunid; - cciss_update_drive_info(ctlr, drv_index); - } /* end for */ - } /* end else */ + + /* Don't need to mark this busy because nobody + * else knows about this disk yet to contend + * for access to it. + */ + h->drv[drv_index].busy_configuring = 0; + wmb(); + + } + cciss_update_drive_info(ctlr, drv_index); + } /* end for */ freeret: kfree(ld_buff); @@ -1597,6 +1685,7 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) return -1; mem_msg: printk(KERN_ERR "cciss: out of memory\n"); + h->busy_configuring = 0; goto freeret; } @@ -1652,15 +1741,15 @@ static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, * other than disk 0 we will call put_disk. We do not * do this for disk 0 as we need it to be able to * configure the controller. - */ + */ if (clear_all){ /* This isn't pretty, but we need to find the * disk in our array and NULL our the pointer. * This is so that we will call alloc_disk if * this index is used again later. - */ + */ for (i=0; i < CISS_MAX_LUN; i++){ - if(h->gendisk[i] == disk){ + if (h->gendisk[i] == disk) { h->gendisk[i] = NULL; break; } @@ -1688,7 +1777,7 @@ static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, if (drv == h->drv + h->highest_lun) { /* if so, find the new hightest lun */ int i, newhighest = -1; - for (i = 0; i < h->highest_lun; i++) { + for (i = 0; i <= h->highest_lun; i++) { /* if the disk has size > 0, it is available */ if (h->drv[i].heads) newhighest = i; @@ -3318,6 +3407,9 @@ geo_inq: cciss_geometry_inquiry(cntl_num, i, 0, total_size, block_size, inq_buff, &hba[cntl_num]->drv[i]); + cciss_get_serial_no(cntl_num, i, 0, + hba[cntl_num]->drv[i].serial_no, + sizeof(hba[cntl_num]->drv[i].serial_no)); } else { /* initialize raid_level to indicate a free space */ hba[cntl_num]->drv[i].raid_level = -1; diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h index b70988dd33ec..24a7efa993ab 100644 --- a/drivers/block/cciss.h +++ b/drivers/block/cciss.h @@ -39,6 +39,8 @@ typedef struct _drive_info_struct *to prevent it from being opened or it's queue *from being started. */ + __u8 serial_no[16]; /* from inquiry page 0x83, */ + /* not necc. null terminated. */ } drive_info_struct; #ifdef CONFIG_CISS_SCSI_TAPE -- cgit v1.2.3 From 6ae5ce8e8d4de666f31286808d2285aa6a50fa40 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:52 +0200 Subject: cciss: remove redundant code This patch removes redundant code where ever logical volumes are added or removed. It adds 3 new functions that are called instead of having the same code spread throughout the driver. It also removes the cciss_getgeometry function. The patch is fairly complex but we haven't figured out how to make it any simpler and still do everything that needs to be done. Some of the complexity comes from having to special case booting from cciss. Otherwise the gendisk doesn't get added in time and the switchroot will fail. Signed-off-by: Stephen M. Cameron Signed-off-by: Mike Miller Signed-off-by: Jens Axboe --- drivers/block/cciss.c | 473 ++++++++++++++++++-------------------------------- 1 file changed, 169 insertions(+), 304 deletions(-) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index f9f10a15d253..08255644e80a 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -159,7 +159,7 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo); static int cciss_revalidate(struct gendisk *disk); -static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk); +static int rebuild_lun_table(ctlr_info_t *h, int first_time); static int deregister_disk(struct gendisk *disk, drive_info_struct *drv, int clear_all); @@ -171,7 +171,6 @@ static void cciss_geometry_inquiry(int ctlr, int logvol, int withirq, sector_t total_size, unsigned int block_size, InquiryData_struct *inq_buff, drive_info_struct *drv); -static void cciss_getgeometry(int cntl_num); static void __devinit cciss_interrupt_mode(ctlr_info_t *, struct pci_dev *, __u32); static void start_io(ctlr_info_t *h); @@ -929,8 +928,10 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, return 0; } + case CCISS_DEREGDISK: + case CCISS_REGNEWD: case CCISS_REVALIDVOLS: - return rebuild_lun_table(host, NULL); + return rebuild_lun_table(host, 0); case CCISS_GETLUNINFO:{ LogvolInfo_struct luninfo; @@ -943,12 +944,6 @@ static int cciss_ioctl(struct inode *inode, struct file *filep, return -EFAULT; return 0; } - case CCISS_DEREGDISK: - return rebuild_lun_table(host, disk); - - case CCISS_REGNEWD: - return rebuild_lun_table(host, NULL); - case CCISS_PASSTHRU: { IOCTL_Command_struct iocommand; @@ -1361,6 +1356,42 @@ static void cciss_get_serial_no(int ctlr, int logvol, int withirq, return; } +static void cciss_add_disk(ctlr_info_t *h, struct gendisk *disk, + int drv_index) +{ + disk->queue = blk_init_queue(do_cciss_request, &h->lock); + sprintf(disk->disk_name, "cciss/c%dd%d", h->ctlr, drv_index); + disk->major = h->major; + disk->first_minor = drv_index << NWD_SHIFT; + disk->fops = &cciss_fops; + disk->private_data = &h->drv[drv_index]; + + /* Set up queue information */ + blk_queue_bounce_limit(disk->queue, h->pdev->dma_mask); + + /* This is a hardware imposed limit. */ + blk_queue_max_hw_segments(disk->queue, MAXSGENTRIES); + + /* This is a limit in the driver and could be eliminated. */ + blk_queue_max_phys_segments(disk->queue, MAXSGENTRIES); + + blk_queue_max_sectors(disk->queue, h->cciss_max_sectors); + + blk_queue_softirq_done(disk->queue, cciss_softirq_done); + + disk->queue->queuedata = h; + + blk_queue_hardsect_size(disk->queue, + h->drv[drv_index].block_size); + + /* Make sure all queue data is written out before */ + /* setting h->drv[drv_index].queue, as setting this */ + /* allows the interrupt handler to start the queue */ + wmb(); + h->drv[drv_index].queue = disk->queue; + add_disk(disk); +} + /* This function will check the usage_count of the drive to be updated/added. * If the usage_count is zero and it is a heretofore unknown drive, or, * the drive's capacity, geometry, or serial number has changed, @@ -1371,7 +1402,7 @@ static void cciss_get_serial_no(int ctlr, int logvol, int withirq, * is also the controller node. Any changes to disk 0 will show up on * the next reboot. */ -static void cciss_update_drive_info(int ctlr, int drv_index) +static void cciss_update_drive_info(int ctlr, int drv_index, int first_time) { ctlr_info_t *h = hba[ctlr]; struct gendisk *disk; @@ -1381,6 +1412,7 @@ static void cciss_update_drive_info(int ctlr, int drv_index) unsigned long flags = 0; int ret = 0; drive_info_struct *drvinfo; + int was_only_controller_node; /* Get information about the disk and modify the driver structure */ inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); @@ -1388,6 +1420,13 @@ static void cciss_update_drive_info(int ctlr, int drv_index) if (inq_buff == NULL || drvinfo == NULL) goto mem_msg; + /* See if we're trying to update the "controller node" + * this will happen the when the first logical drive gets + * created by ACU. + */ + was_only_controller_node = (drv_index == 0 && + h->drv[0].raid_level == -1); + /* testing to see if 16-byte CDBs are already being used */ if (h->cciss_read == CCISS_READ_16) { cciss_read_capacity_16(h->ctlr, drv_index, 1, @@ -1427,25 +1466,26 @@ static void cciss_update_drive_info(int ctlr, int drv_index) drvinfo->nr_blocks == h->drv[drv_index].nr_blocks && drvinfo->heads == h->drv[drv_index].heads && drvinfo->sectors == h->drv[drv_index].sectors && - drvinfo->cylinders == h->drv[drv_index].cylinders)) { + drvinfo->cylinders == h->drv[drv_index].cylinders)) /* The disk is unchanged, nothing to update */ goto freeret; - } - /* Not the same disk, or something's changed, so we need to */ - /* deregister it, and re-register it, if it's not in use. */ - - /* if the disk already exists then deregister it before proceeding */ - /* (unless it's the first disk (for the controller node). */ + /* If we get here it's not the same disk, or something's changed, + * so we need to * deregister it, and re-register it, if it's not + * in use. + * If the disk already exists then deregister it before proceeding + * (unless it's the first disk (for the controller node). + */ if (h->drv[drv_index].raid_level != -1 && drv_index != 0) { printk(KERN_WARNING "disk %d has changed.\n", drv_index); spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); h->drv[drv_index].busy_configuring = 1; spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); - /* deregister_disk sets h->drv[drv_index].queue = NULL */ - /* which keeps the interrupt handler from starting */ - /* the queue. */ + /* deregister_disk sets h->drv[drv_index].queue = NULL + * which keeps the interrupt handler from starting + * the queue. + */ ret = deregister_disk(h->gendisk[drv_index], &h->drv[drv_index], 0); h->drv[drv_index].busy_configuring = 0; @@ -1455,8 +1495,9 @@ static void cciss_update_drive_info(int ctlr, int drv_index) if (ret) goto freeret; - /* Save the new information from cciss_geometry_inquiry */ - /* and serial number inquiry. */ + /* Save the new information from cciss_geometry_inquiry + * and serial number inquiry. + */ h->drv[drv_index].block_size = drvinfo->block_size; h->drv[drv_index].nr_blocks = drvinfo->nr_blocks; h->drv[drv_index].heads = drvinfo->heads; @@ -1469,46 +1510,20 @@ static void cciss_update_drive_info(int ctlr, int drv_index) disk = h->gendisk[drv_index]; set_capacity(disk, h->drv[drv_index].nr_blocks); - /* if it's the controller (if drv_index == 0) it's already added */ - if (drv_index) { - disk->queue = blk_init_queue(do_cciss_request, &h->lock); - sprintf(disk->disk_name, "cciss/c%dd%d", ctlr, drv_index); - disk->major = h->major; - disk->first_minor = drv_index << NWD_SHIFT; - disk->fops = &cciss_fops; - disk->private_data = &h->drv[drv_index]; - - /* Set up queue information */ - blk_queue_bounce_limit(disk->queue, hba[ctlr]->pdev->dma_mask); - - /* This is a hardware imposed limit. */ - blk_queue_max_hw_segments(disk->queue, MAXSGENTRIES); - - /* This is a limit in the driver and could be eliminated. */ - blk_queue_max_phys_segments(disk->queue, MAXSGENTRIES); - - blk_queue_max_sectors(disk->queue, h->cciss_max_sectors); - - blk_queue_softirq_done(disk->queue, cciss_softirq_done); - - disk->queue->queuedata = hba[ctlr]; - - blk_queue_hardsect_size(disk->queue, - hba[ctlr]->drv[drv_index].block_size); - - /* Make sure all queue data is written out before */ - /* setting h->drv[drv_index].queue, as setting this */ - /* allows the interrupt handler to start the queue */ - wmb(); - h->drv[drv_index].queue = disk->queue; - add_disk(disk); - } + /* If it's not disk 0 (drv_index != 0) + * or if it was disk 0, but there was previously + * no actual corresponding configured logical drive + * (raid_leve == -1) then we want to update the + * logical drive's information. + */ + if (drv_index || first_time) + cciss_add_disk(h, disk, drv_index); - freeret: +freeret: kfree(inq_buff); kfree(drvinfo); return; - mem_msg: +mem_msg: printk(KERN_ERR "cciss: out of memory\n"); goto freeret; } @@ -1533,6 +1548,73 @@ static int cciss_find_free_drive_index(int ctlr) return -1; } +/* cciss_add_gendisk finds a free hba[]->drv structure + * and allocates a gendisk if needed, and sets the lunid + * in the drvinfo structure. It returns the index into + * the ->drv[] array, or -1 if none are free. + * is_controller_node indicates whether highest_lun should + * count this disk, or if it's only being added to provide + * a means to talk to the controller in case no logical + * drives have yet been configured. + */ +static int cciss_add_gendisk(ctlr_info_t *h, __u32 lunid) +{ + int drv_index; + + drv_index = cciss_find_free_drive_index(h->ctlr); + if (drv_index == -1) + return -1; + /*Check if the gendisk needs to be allocated */ + if (!h->gendisk[drv_index]) { + h->gendisk[drv_index] = + alloc_disk(1 << NWD_SHIFT); + if (!h->gendisk[drv_index]) { + printk(KERN_ERR "cciss%d: could not " + "allocate a new disk %d\n", + h->ctlr, drv_index); + return -1; + } + } + h->drv[drv_index].LunID = lunid; + + /* Don't need to mark this busy because nobody */ + /* else knows about this disk yet to contend */ + /* for access to it. */ + h->drv[drv_index].busy_configuring = 0; + wmb(); + return drv_index; +} + +/* This is for the special case of a controller which + * has no logical drives. In this case, we still need + * to register a disk so the controller can be accessed + * by the Array Config Utility. + */ +static void cciss_add_controller_node(ctlr_info_t *h) +{ + struct gendisk *disk; + int drv_index; + + if (h->gendisk[0] != NULL) /* already did this? Then bail. */ + return; + + drv_index = cciss_add_gendisk(h, 0); + if (drv_index == -1) { + printk(KERN_WARNING "cciss%d: could not " + "add disk 0.\n", h->ctlr); + return; + } + h->drv[drv_index].block_size = 512; + h->drv[drv_index].nr_blocks = 0; + h->drv[drv_index].heads = 0; + h->drv[drv_index].sectors = 0; + h->drv[drv_index].cylinders = 0; + h->drv[drv_index].raid_level = -1; + memset(h->drv[drv_index].serial_no, 0, 16); + disk = h->gendisk[drv_index]; + cciss_add_disk(h, disk, drv_index); +} + /* This function will add and remove logical drives from the Logical * drive array of the controller and maintain persistency of ordering * so that mount points are preserved until the next reboot. This allows @@ -1540,10 +1622,8 @@ static int cciss_find_free_drive_index(int ctlr) * without a re-ordering of those drives. * INPUT * h = The controller to perform the operations on - * del_disk = The disk to remove if specified. If the value given - * is NULL then no disk is removed. */ -static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) +static int rebuild_lun_table(ctlr_info_t *h, int first_time) { int ctlr = h->ctlr; int num_luns; @@ -1556,6 +1636,9 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) __u32 lunid = 0; unsigned long flags; + if (!capable(CAP_SYS_RAWIO)) + return -EPERM; + /* Set busy_configuring flag for this operation */ spin_lock_irqsave(CCISS_LOCK(h->ctlr), flags); if (h->busy_configuring) { @@ -1565,9 +1648,6 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) h->busy_configuring = 1; spin_unlock_irqrestore(CCISS_LOCK(h->ctlr), flags); - if (!capable(CAP_SYS_RAWIO)) - return -EPERM; - ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); if (ld_buff == NULL) goto mem_msg; @@ -1593,10 +1673,14 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) " this driver.\n"); } - /* Compare controller drive array to driver's drive array */ - /* to see if any drives are missing on the controller due */ - /* to action of Array Config Utility (user deletes drive) */ - /* and deregister logical drives which have disappeared. */ + if (num_luns == 0) + cciss_add_controller_node(h); + + /* Compare controller drive array to driver's drive array + * to see if any drives are missing on the controller due + * to action of Array Config Utility (user deletes drive) + * and deregister logical drives which have disappeared. + */ for (i = 0; i <= h->highest_lun; i++) { int j; drv_found = 0; @@ -1648,34 +1732,14 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) /* check if the drive was found already in the array */ if (!drv_found) { - drv_index = cciss_find_free_drive_index(ctlr); + drv_index = cciss_add_gendisk(h, lunid); if (drv_index == -1) goto freeret; - /*Check if the gendisk needs to be allocated */ - if (!h->gendisk[drv_index]) { - h->gendisk[drv_index] = - alloc_disk(1 << NWD_SHIFT); - if (!h->gendisk[drv_index]){ - printk(KERN_ERR "cciss: could not " - "allocate new disk %d\n", - drv_index); - goto mem_msg; - } - } - h->drv[drv_index].LunID = lunid; - - /* Don't need to mark this busy because nobody - * else knows about this disk yet to contend - * for access to it. - */ - h->drv[drv_index].busy_configuring = 0; - wmb(); - } - cciss_update_drive_info(ctlr, drv_index); + cciss_update_drive_info(ctlr, drv_index, first_time); } /* end for */ - freeret: +freeret: kfree(ld_buff); h->busy_configuring = 0; /* We return -1 here to tell the ACU that we have registered/updated @@ -1683,7 +1747,7 @@ static int rebuild_lun_table(ctlr_info_t *h, struct gendisk *del_disk) * additional times. */ return -1; - mem_msg: +mem_msg: printk(KERN_ERR "cciss: out of memory\n"); h->busy_configuring = 0; goto freeret; @@ -3288,139 +3352,9 @@ err_out_free_res: return err; } -/* - * Gets information about the local volumes attached to the controller. +/* Function to find the first free pointer into our hba[] array + * Returns -1 if no free entries are left. */ -static void cciss_getgeometry(int cntl_num) -{ - ReportLunData_struct *ld_buff; - InquiryData_struct *inq_buff; - int return_code; - int i; - int listlength = 0; - __u32 lunid = 0; - unsigned block_size; - sector_t total_size; - - ld_buff = kzalloc(sizeof(ReportLunData_struct), GFP_KERNEL); - if (ld_buff == NULL) { - printk(KERN_ERR "cciss: out of memory\n"); - return; - } - inq_buff = kmalloc(sizeof(InquiryData_struct), GFP_KERNEL); - if (inq_buff == NULL) { - printk(KERN_ERR "cciss: out of memory\n"); - kfree(ld_buff); - return; - } - /* Get the firmware version */ - return_code = sendcmd(CISS_INQUIRY, cntl_num, inq_buff, - sizeof(InquiryData_struct), 0, 0, 0, NULL, - TYPE_CMD); - if (return_code == IO_OK) { - hba[cntl_num]->firm_ver[0] = inq_buff->data_byte[32]; - hba[cntl_num]->firm_ver[1] = inq_buff->data_byte[33]; - hba[cntl_num]->firm_ver[2] = inq_buff->data_byte[34]; - hba[cntl_num]->firm_ver[3] = inq_buff->data_byte[35]; - } else { /* send command failed */ - - printk(KERN_WARNING "cciss: unable to determine firmware" - " version of controller\n"); - } - /* Get the number of logical volumes */ - return_code = sendcmd(CISS_REPORT_LOG, cntl_num, ld_buff, - sizeof(ReportLunData_struct), 0, 0, 0, NULL, - TYPE_CMD); - - if (return_code == IO_OK) { -#ifdef CCISS_DEBUG - printk("LUN Data\n--------------------------\n"); -#endif /* CCISS_DEBUG */ - - listlength |= - (0xff & (unsigned int)(ld_buff->LUNListLength[0])) << 24; - listlength |= - (0xff & (unsigned int)(ld_buff->LUNListLength[1])) << 16; - listlength |= - (0xff & (unsigned int)(ld_buff->LUNListLength[2])) << 8; - listlength |= 0xff & (unsigned int)(ld_buff->LUNListLength[3]); - } else { /* reading number of logical volumes failed */ - - printk(KERN_WARNING "cciss: report logical volume" - " command failed\n"); - listlength = 0; - } - hba[cntl_num]->num_luns = listlength / 8; // 8 bytes pre entry - if (hba[cntl_num]->num_luns > CISS_MAX_LUN) { - printk(KERN_ERR - "ciss: only %d number of logical volumes supported\n", - CISS_MAX_LUN); - hba[cntl_num]->num_luns = CISS_MAX_LUN; - } -#ifdef CCISS_DEBUG - printk(KERN_DEBUG "Length = %x %x %x %x = %d\n", - ld_buff->LUNListLength[0], ld_buff->LUNListLength[1], - ld_buff->LUNListLength[2], ld_buff->LUNListLength[3], - hba[cntl_num]->num_luns); -#endif /* CCISS_DEBUG */ - - hba[cntl_num]->highest_lun = hba[cntl_num]->num_luns - 1; - for (i = 0; i < CISS_MAX_LUN; i++) { - if (i < hba[cntl_num]->num_luns) { - lunid = (0xff & (unsigned int)(ld_buff->LUN[i][3])) - << 24; - lunid |= (0xff & (unsigned int)(ld_buff->LUN[i][2])) - << 16; - lunid |= (0xff & (unsigned int)(ld_buff->LUN[i][1])) - << 8; - lunid |= 0xff & (unsigned int)(ld_buff->LUN[i][0]); - - hba[cntl_num]->drv[i].LunID = lunid; - -#ifdef CCISS_DEBUG - printk(KERN_DEBUG "LUN[%d]: %x %x %x %x = %x\n", i, - ld_buff->LUN[i][0], ld_buff->LUN[i][1], - ld_buff->LUN[i][2], ld_buff->LUN[i][3], - hba[cntl_num]->drv[i].LunID); -#endif /* CCISS_DEBUG */ - - /* testing to see if 16-byte CDBs are already being used */ - if(hba[cntl_num]->cciss_read == CCISS_READ_16) { - cciss_read_capacity_16(cntl_num, i, 0, - &total_size, &block_size); - goto geo_inq; - } - cciss_read_capacity(cntl_num, i, 0, &total_size, &block_size); - - /* If read_capacity returns all F's the logical is >2TB */ - /* so we switch to 16-byte CDBs for all read/write ops */ - if(total_size == 0xFFFFFFFFULL) { - cciss_read_capacity_16(cntl_num, i, 0, - &total_size, &block_size); - hba[cntl_num]->cciss_read = CCISS_READ_16; - hba[cntl_num]->cciss_write = CCISS_WRITE_16; - } else { - hba[cntl_num]->cciss_read = CCISS_READ_10; - hba[cntl_num]->cciss_write = CCISS_WRITE_10; - } -geo_inq: - cciss_geometry_inquiry(cntl_num, i, 0, total_size, - block_size, inq_buff, - &hba[cntl_num]->drv[i]); - cciss_get_serial_no(cntl_num, i, 0, - hba[cntl_num]->drv[i].serial_no, - sizeof(hba[cntl_num]->drv[i].serial_no)); - } else { - /* initialize raid_level to indicate a free space */ - hba[cntl_num]->drv[i].raid_level = -1; - } - } - kfree(ld_buff); - kfree(inq_buff); -} - -/* Function to find the first free pointer into our hba[] array */ -/* Returns -1 if no free entries are left. */ static int alloc_cciss_hba(void) { int i; @@ -3432,11 +3366,6 @@ static int alloc_cciss_hba(void) p = kzalloc(sizeof(ctlr_info_t), GFP_KERNEL); if (!p) goto Enomem; - p->gendisk[0] = alloc_disk(1 << NWD_SHIFT); - if (!p->gendisk[0]) { - kfree(p); - goto Enomem; - } hba[i] = p; return i; } @@ -3564,11 +3493,13 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, ((hba[i]->nr_cmds + BITS_PER_LONG - 1) / BITS_PER_LONG) * sizeof(unsigned long)); -#ifdef CCISS_DEBUG - printk(KERN_DEBUG "Scanning for drives on controller cciss%d\n", i); -#endif /* CCISS_DEBUG */ - - cciss_getgeometry(i); + hba[i]->num_luns = 0; + hba[i]->highest_lun = -1; + for (j = 0; j < CISS_MAX_LUN; j++) { + hba[i]->drv[j].raid_level = -1; + hba[i]->drv[j].queue = NULL; + hba[i]->gendisk[j] = NULL; + } cciss_scsi_setup(i); @@ -3581,76 +3512,10 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, hba[i]->busy_initializing = 0; - do { - drive_info_struct *drv = &(hba[i]->drv[j]); - struct gendisk *disk = hba[i]->gendisk[j]; - struct request_queue *q; - - /* Check if the disk was allocated already */ - if (!disk){ - hba[i]->gendisk[j] = alloc_disk(1 << NWD_SHIFT); - disk = hba[i]->gendisk[j]; - } - - /* Check that the disk was able to be allocated */ - if (!disk) { - printk(KERN_ERR "cciss: unable to allocate memory for disk %d\n", j); - goto clean4; - } - - q = blk_init_queue(do_cciss_request, &hba[i]->lock); - if (!q) { - printk(KERN_ERR - "cciss: unable to allocate queue for disk %d\n", - j); - goto clean4; - } - drv->queue = q; - - blk_queue_bounce_limit(q, hba[i]->pdev->dma_mask); - - /* This is a hardware imposed limit. */ - blk_queue_max_hw_segments(q, MAXSGENTRIES); - - /* This is a limit in the driver and could be eliminated. */ - blk_queue_max_phys_segments(q, MAXSGENTRIES); - - blk_queue_max_sectors(q, hba[i]->cciss_max_sectors); - - blk_queue_softirq_done(q, cciss_softirq_done); - - q->queuedata = hba[i]; - sprintf(disk->disk_name, "cciss/c%dd%d", i, j); - disk->major = hba[i]->major; - disk->first_minor = j << NWD_SHIFT; - disk->fops = &cciss_fops; - disk->queue = q; - disk->private_data = drv; - disk->driverfs_dev = &pdev->dev; - /* we must register the controller even if no disks exist */ - /* this is for the online array utilities */ - if (!drv->heads && j) - continue; - blk_queue_hardsect_size(q, drv->block_size); - set_capacity(disk, drv->nr_blocks); - j++; - } while (j <= hba[i]->highest_lun); - - /* Make sure all queue data is written out before */ - /* interrupt handler, triggered by add_disk, */ - /* is allowed to start them. */ - wmb(); - - for (j = 0; j <= hba[i]->highest_lun; j++) - add_disk(hba[i]->gendisk[j]); - - /* we must register the controller even if no disks exist */ - if (hba[i]->highest_lun == -1) - add_disk(hba[i]->gendisk[0]); - + rebuild_lun_table(hba[i], 1); return 1; - clean4: +clean4: #ifdef CONFIG_CISS_SCSI_TAPE kfree(hba[i]->scsi_rejects.complete); #endif @@ -3665,9 +3530,9 @@ static int __devinit cciss_init_one(struct pci_dev *pdev, hba[i]->errinfo_pool, hba[i]->errinfo_pool_dhandle); free_irq(hba[i]->intr[SIMPLE_MODE_INT], hba[i]); - clean2: +clean2: unregister_blkdev(hba[i]->major, hba[i]->devname); - clean1: +clean1: hba[i]->busy_initializing = 0; /* cleanup any queues that may have been initialized */ for (j=0; j <= hba[i]->highest_lun; j++){ -- cgit v1.2.3 From eece695f8bf9d1aacf3a119ab8e21db31948e40b Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:53 +0200 Subject: cciss: fix negative logical drive count in procfs This patch fixes a problem where the logical volume count may go negative. In some instances if several logical are configured on a controller and all of them are deleted using the online utilities the volume count in /proc may go negative with no way get it correct again. Signed-off-by: Stephen M. Cameron Signed-off-by: Mike Miller Signed-off-by: Jens Axboe --- drivers/block/cciss.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 08255644e80a..9ffa821fbfd7 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -1533,15 +1533,18 @@ mem_msg: * where new drives will be added. If the index to be returned is greater * than the highest_lun index for the controller then highest_lun is set * to this new index. If there are no available indexes then -1 is returned. + * "controller_node" is used to know if this is a real logical drive, or just + * the controller node, which determines if this counts towards highest_lun. */ -static int cciss_find_free_drive_index(int ctlr) +static int cciss_find_free_drive_index(int ctlr, int controller_node) { int i; for (i = 0; i < CISS_MAX_LUN; i++) { if (hba[ctlr]->drv[i].raid_level == -1) { if (i > hba[ctlr]->highest_lun) - hba[ctlr]->highest_lun = i; + if (!controller_node) + hba[ctlr]->highest_lun = i; return i; } } @@ -1557,11 +1560,11 @@ static int cciss_find_free_drive_index(int ctlr) * a means to talk to the controller in case no logical * drives have yet been configured. */ -static int cciss_add_gendisk(ctlr_info_t *h, __u32 lunid) +static int cciss_add_gendisk(ctlr_info_t *h, __u32 lunid, int controller_node) { int drv_index; - drv_index = cciss_find_free_drive_index(h->ctlr); + drv_index = cciss_find_free_drive_index(h->ctlr, controller_node); if (drv_index == -1) return -1; /*Check if the gendisk needs to be allocated */ @@ -1598,7 +1601,7 @@ static void cciss_add_controller_node(ctlr_info_t *h) if (h->gendisk[0] != NULL) /* already did this? Then bail. */ return; - drv_index = cciss_add_gendisk(h, 0); + drv_index = cciss_add_gendisk(h, 0, 1); if (drv_index == -1) { printk(KERN_WARNING "cciss%d: could not " "add disk 0.\n", h->ctlr); @@ -1732,7 +1735,7 @@ static int rebuild_lun_table(ctlr_info_t *h, int first_time) /* check if the drive was found already in the array */ if (!drv_found) { - drv_index = cciss_add_gendisk(h, lunid); + drv_index = cciss_add_gendisk(h, lunid, 0); if (drv_index == -1) goto freeret; } -- cgit v1.2.3 From f4a93bcda74edfe6977dcf296ed8c86119638871 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:53 +0200 Subject: cciss: change the way we notify scsi midlayer of tape drives This patch changes way we notify the scsi layer that something has changed on the SCSI tape side of the driver. The user can now just tell the driver to rescan a particular controller rather than having to know the SCSI nexus to echo into the SCSI mid-layer. Signed-off-by: Stephen M. Cameron Signed-off-by: Mike Miller Signed-off-by: Jens Axboe --- Documentation/cciss.txt | 21 ++---- drivers/block/cciss_scsi.c | 157 ++++++++++++++++++++++++++++++++++----------- 2 files changed, 124 insertions(+), 54 deletions(-) diff --git a/Documentation/cciss.txt b/Documentation/cciss.txt index 63e59b8847c5..8244c6442faa 100644 --- a/Documentation/cciss.txt +++ b/Documentation/cciss.txt @@ -112,27 +112,18 @@ Hot plug support for SCSI tape drives Hot plugging of SCSI tape drives is supported, with some caveats. The cciss driver must be informed that changes to the SCSI bus -have been made, in addition to and prior to informing the SCSI -mid layer. This may be done via the /proc filesystem. For example: +have been made. This may be done via the /proc filesystem. +For example: echo "rescan" > /proc/scsi/cciss0/1 -This causes the adapter to query the adapter about changes to the -physical SCSI buses and/or fibre channel arbitrated loop and the +This causes the driver to query the adapter about changes to the +physical SCSI buses and/or fibre channel arbitrated loop and the driver to make note of any new or removed sequential access devices or medium changers. The driver will output messages indicating what devices have been added or removed and the controller, bus, target and -lun used to address the device. Once this is done, the SCSI mid layer -can be informed of changes to the virtual SCSI bus which the driver -presents to it in the usual way. For example: - - echo scsi add-single-device 3 2 1 0 > /proc/scsi/scsi - -to add a device on controller 3, bus 2, target 1, lun 0. Note that -the driver makes an effort to preserve the devices positions -in the virtual SCSI bus, so if you are only moving tape drives -around on the same adapter and not adding or removing tape drives -from the adapter, informing the SCSI mid layer may not be necessary. +lun used to address the device. It then notifies the SCSI mid layer +of these changes. Note that the naming convention of the /proc filesystem entries contains a number in addition to the driver name. (E.g. "cciss0" diff --git a/drivers/block/cciss_scsi.c b/drivers/block/cciss_scsi.c index e4bf9a11ca0d..c673ff14126a 100644 --- a/drivers/block/cciss_scsi.c +++ b/drivers/block/cciss_scsi.c @@ -358,10 +358,15 @@ find_bus_target_lun(int ctlr, int *bus, int *target, int *lun) } return (!found); } +struct scsi2map { + char scsi3addr[8]; + int bus, target, lun; +}; static int cciss_scsi_add_entry(int ctlr, int hostno, - unsigned char *scsi3addr, int devtype) + unsigned char *scsi3addr, int devtype, + struct scsi2map *added, int *nadded) { /* assumes hba[ctlr]->scsi_ctlr->lock is held */ int n = ccissscsi[ctlr].ndevices; @@ -375,6 +380,12 @@ cciss_scsi_add_entry(int ctlr, int hostno, sd = &ccissscsi[ctlr].dev[n]; if (find_bus_target_lun(ctlr, &sd->bus, &sd->target, &sd->lun) != 0) return -1; + + added[*nadded].bus = sd->bus; + added[*nadded].target = sd->target; + added[*nadded].lun = sd->lun; + (*nadded)++; + memcpy(&sd->scsi3addr[0], scsi3addr, 8); sd->devtype = devtype; ccissscsi[ctlr].ndevices++; @@ -390,7 +401,8 @@ cciss_scsi_add_entry(int ctlr, int hostno, } static void -cciss_scsi_remove_entry(int ctlr, int hostno, int entry) +cciss_scsi_remove_entry(int ctlr, int hostno, int entry, + struct scsi2map *removed, int *nremoved) { /* assumes hba[ctlr]->scsi_ctlr->lock is held */ int i; @@ -398,6 +410,10 @@ cciss_scsi_remove_entry(int ctlr, int hostno, int entry) if (entry < 0 || entry >= CCISS_MAX_SCSI_DEVS_PER_HBA) return; sd = ccissscsi[ctlr].dev[entry]; + removed[*nremoved].bus = sd.bus; + removed[*nremoved].target = sd.target; + removed[*nremoved].lun = sd.lun; + (*nremoved)++; for (i=entry;iscsi_ctlr)->scsi_host; + /* find any devices in ccissscsi[] that are not in sd[] and remove them from ccissscsi[] */ i = 0; + nremoved = 0; + nadded = 0; while(idevtype), hostno, csd->bus, csd->target, csd->lun); */ - cciss_scsi_remove_entry(ctlr, hostno, i); - /* note, i not incremented */ + cciss_scsi_remove_entry(ctlr, hostno, i, + removed, &nremoved); + /* remove ^^^, hence i not incremented */ } else if (found == 1) { /* device is different kind */ changes++; @@ -464,8 +521,15 @@ adjust_cciss_scsi_table(int ctlr, int hostno, "(device type now %s).\n", ctlr, hostno, csd->bus, csd->target, csd->lun, scsi_device_type(csd->devtype)); + cciss_scsi_remove_entry(ctlr, hostno, i, + removed, &nremoved); + /* remove ^^^, hence i not incremented */ + if (cciss_scsi_add_entry(ctlr, hostno, + &sd[j].scsi3addr[0], sd[j].devtype, + added, &nadded) != 0) + /* we just removed one, so add can't fail. */ + BUG(); csd->devtype = sd[j].devtype; - i++; /* so just move along. */ } else /* device is same as it ever was, */ i++; /* so just move along. */ } @@ -489,7 +553,9 @@ adjust_cciss_scsi_table(int ctlr, int hostno, if (!found) { changes++; if (cciss_scsi_add_entry(ctlr, hostno, - &sd[i].scsi3addr[0], sd[i].devtype) != 0) + + &sd[i].scsi3addr[0], sd[i].devtype, + added, &nadded) != 0) break; } else if (found == 1) { /* should never happen... */ @@ -501,9 +567,50 @@ adjust_cciss_scsi_table(int ctlr, int hostno, } CPQ_TAPE_UNLOCK(ctlr, flags); - if (!changes) - printk("cciss%d: No device changes detected.\n", ctlr); + /* Don't notify scsi mid layer of any changes the first time through */ + /* (or if there are no changes) scsi_scan_host will do it later the */ + /* first time through. */ + if (hostno == -1 || !changes) + goto free_and_out; + + /* Notify scsi mid layer of any removed devices */ + for (i = 0; i < nremoved; i++) { + struct scsi_device *sdev = + scsi_device_lookup(sh, removed[i].bus, + removed[i].target, removed[i].lun); + if (sdev != NULL) { + scsi_remove_device(sdev); + scsi_device_put(sdev); + } else { + /* We don't expect to get here. */ + /* future cmds to this device will get selection */ + /* timeout as if the device was gone. */ + printk(KERN_WARNING "cciss%d: didn't find " + "c%db%dt%dl%d\n for removal.", + ctlr, hostno, removed[i].bus, + removed[i].target, removed[i].lun); + } + } + + /* Notify scsi mid layer of any added devices */ + for (i = 0; i < nadded; i++) { + int rc; + rc = scsi_add_device(sh, added[i].bus, + added[i].target, added[i].lun); + if (rc == 0) + continue; + printk(KERN_WARNING "cciss%d: scsi_add_device " + "c%db%dt%dl%d failed, device not added.\n", + ctlr, hostno, + added[i].bus, added[i].target, added[i].lun); + /* now we have to remove it from ccissscsi, */ + /* since it didn't get added to scsi mid layer */ + fixup_botched_add(ctlr, added[i].scsi3addr); + } +free_and_out: + kfree(added); + kfree(removed); return 0; } @@ -1354,32 +1461,6 @@ cciss_unregister_scsi(int ctlr) kfree(sa); } -static int -cciss_register_scsi(int ctlr) -{ - unsigned long flags; - - CPQ_TAPE_LOCK(ctlr, flags); - - /* Since this is really a block driver, the SCSI core may not be - initialized at init time, in which case, calling scsi_register_host - would hang. Instead, we do it later, via /proc filesystem - and rc scripts, when we know SCSI core is good to go. */ - - /* Only register if SCSI devices are detected. */ - if (ccissscsi[ctlr].ndevices != 0) { - ((struct cciss_scsi_adapter_data_t *) - hba[ctlr]->scsi_ctlr)->registered = 1; - CPQ_TAPE_UNLOCK(ctlr, flags); - return cciss_scsi_detect(ctlr); - } - CPQ_TAPE_UNLOCK(ctlr, flags); - printk(KERN_INFO - "cciss%d: No appropriate SCSI device detected, " - "SCSI subsystem not engaged.\n", ctlr); - return 0; -} - static int cciss_engage_scsi(int ctlr) { @@ -1391,15 +1472,15 @@ cciss_engage_scsi(int ctlr) sa = (struct cciss_scsi_adapter_data_t *) hba[ctlr]->scsi_ctlr; stk = &sa->cmd_stack; - if (((struct cciss_scsi_adapter_data_t *) - hba[ctlr]->scsi_ctlr)->registered) { + if (sa->registered) { printk("cciss%d: SCSI subsystem already engaged.\n", ctlr); spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); return ENXIO; } + sa->registered = 1; spin_unlock_irqrestore(CCISS_LOCK(ctlr), flags); cciss_update_non_disk_devices(ctlr, -1); - cciss_register_scsi(ctlr); + cciss_scsi_detect(ctlr); return 0; } @@ -1493,7 +1574,5 @@ static int cciss_eh_abort_handler(struct scsi_cmnd *scsicmd) /* If no tape support, then these become defined out of existence */ #define cciss_scsi_setup(cntl_num) -#define cciss_unregister_scsi(ctlr) -#define cciss_register_scsi(ctlr) #endif /* CONFIG_CISS_SCSI_TAPE */ -- cgit v1.2.3 From 935dc8d7575e6c1292b057e39045a40f1fbe26e7 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:54 +0200 Subject: cciss: add support for multi lun tape devices This patch adds support for multi-lun devices in a SAS environment. It's required for the support of media changers. Signed-off-by: Stephen M. Cameron Signed-off-by: Mike Miller Signed-off-by: Jens Axboe --- drivers/block/cciss_scsi.c | 40 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/block/cciss_scsi.c b/drivers/block/cciss_scsi.c index c673ff14126a..e1233aabda77 100644 --- a/drivers/block/cciss_scsi.c +++ b/drivers/block/cciss_scsi.c @@ -371,16 +371,50 @@ cciss_scsi_add_entry(int ctlr, int hostno, /* assumes hba[ctlr]->scsi_ctlr->lock is held */ int n = ccissscsi[ctlr].ndevices; struct cciss_scsi_dev_t *sd; + int i, bus, target, lun; + unsigned char addr1[8], addr2[8]; if (n >= CCISS_MAX_SCSI_DEVS_PER_HBA) { printk("cciss%d: Too many devices, " "some will be inaccessible.\n", ctlr); return -1; } - sd = &ccissscsi[ctlr].dev[n]; - if (find_bus_target_lun(ctlr, &sd->bus, &sd->target, &sd->lun) != 0) - return -1; + bus = target = -1; + lun = 0; + /* Is this device a non-zero lun of a multi-lun device */ + /* byte 4 of the 8-byte LUN addr will contain the logical unit no. */ + if (scsi3addr[4] != 0) { + /* Search through our list and find the device which */ + /* has the same 8 byte LUN address, excepting byte 4. */ + /* Assign the same bus and target for this new LUN. */ + /* Use the logical unit number from the firmware. */ + memcpy(addr1, scsi3addr, 8); + addr1[4] = 0; + for (i = 0; i < n; i++) { + sd = &ccissscsi[ctlr].dev[i]; + memcpy(addr2, sd->scsi3addr, 8); + addr2[4] = 0; + /* differ only in byte 4? */ + if (memcmp(addr1, addr2, 8) == 0) { + bus = sd->bus; + target = sd->target; + lun = scsi3addr[4]; + break; + } + } + } + + sd = &ccissscsi[ctlr].dev[n]; + if (lun == 0) { + if (find_bus_target_lun(ctlr, + &sd->bus, &sd->target, &sd->lun) != 0) + return -1; + } else { + sd->bus = bus; + sd->target = target; + sd->lun = lun; + } added[*nadded].bus = sd->bus; added[*nadded].target = sd->target; added[*nadded].lun = sd->lun; -- cgit v1.2.3 From ba198efb5ef4e5f4927a18ff95a58f40c58cbaa9 Mon Sep 17 00:00:00 2001 From: Mike Miller Date: Mon, 4 Aug 2008 11:54:55 +0200 Subject: cciss: fix bug if scsi tape support is disabled Bug fix. If SCSI tape support is turned off we get an implicit declaration of cciss_unregister_scsi error in cciss_remove_one. Signed-off-by: Mike Miller Signed-off-by: Stephen M. Cameron Signed-off-by: Jens Axboe --- drivers/block/cciss.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c index 9ffa821fbfd7..b73116ef9236 100644 --- a/drivers/block/cciss.c +++ b/drivers/block/cciss.c @@ -3614,7 +3614,9 @@ static void __devexit cciss_remove_one(struct pci_dev *pdev) } } +#ifdef CONFIG_CISS_SCSI_TAPE cciss_unregister_scsi(i); /* unhook from SCSI subsystem */ +#endif cciss_shutdown(pdev); -- cgit v1.2.3 From 1ac0ae062cecd37587f5b951089f90e1d9d91769 Mon Sep 17 00:00:00 2001 From: Denis ChengRq Date: Mon, 4 Aug 2008 11:56:30 +0200 Subject: bio: make use of bvec_nr_vecs Since introduced in 7ba1ba12eee, it should be made use of. Signed-off-by: Denis ChengRq Signed-off-by: Jens Axboe --- fs/bio.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/fs/bio.c b/fs/bio.c index 25f1af0d81e5..8000e2fa16cb 100644 --- a/fs/bio.c +++ b/fs/bio.c @@ -77,11 +77,8 @@ struct bio_vec *bvec_alloc_bs(gfp_t gfp_mask, int nr, unsigned long *idx, struct */ bvl = mempool_alloc(bs->bvec_pools[*idx], gfp_mask); - if (bvl) { - struct biovec_slab *bp = bvec_slabs + *idx; - - memset(bvl, 0, bp->nr_vecs * sizeof(struct bio_vec)); - } + if (bvl) + memset(bvl, 0, bvec_nr_vecs(*idx) * sizeof(struct bio_vec)); return bvl; } @@ -149,7 +146,7 @@ struct bio *bio_alloc_bioset(gfp_t gfp_mask, int nr_iovecs, struct bio_set *bs) goto out; } bio->bi_flags |= idx << BIO_POOL_OFFSET; - bio->bi_max_vecs = bvec_slabs[idx].nr_vecs; + bio->bi_max_vecs = bvec_nr_vecs(idx); } bio->bi_io_vec = bvl; } -- cgit v1.2.3 From 62aa0054da220b8bbe6f23c0eb1d97a99005d0b3 Mon Sep 17 00:00:00 2001 From: Adrian Bunk Date: Mon, 4 Aug 2008 11:59:05 +0200 Subject: xen-blkfront.c: make blkif_ioctl() static This patch makes the needlessly global blkif_ioctl() static. Signed-off-by: Adrian Bunk Acked-by: Jeremy Fitzhardinge Signed-off-by: Jens Axboe --- drivers/block/xen-blkfront.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c index 9ae05c584234..3ca643cafccd 100644 --- a/drivers/block/xen-blkfront.c +++ b/drivers/block/xen-blkfront.c @@ -154,8 +154,8 @@ static int blkif_getgeo(struct block_device *bd, struct hd_geometry *hg) return 0; } -int blkif_ioctl(struct inode *inode, struct file *filep, - unsigned command, unsigned long argument) +static int blkif_ioctl(struct inode *inode, struct file *filep, + unsigned command, unsigned long argument) { struct blkfront_info *info = inode->i_bdev->bd_disk->private_data; -- cgit v1.2.3 From 9e74114d96bb5dbaa17b9292139b0c6205e0b971 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Tue, 15 Jul 2008 11:18:04 +0000 Subject: [WATCHDOG] hpwdt.c - fix double includes The last clean-up created 2 times the same include. delete the doubles. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/hpwdt.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index d20f591e3fd7..7ea8f3e844f3 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -39,9 +39,7 @@ #include #include #include -#include #include -#include #define PCI_BIOS32_SD_VALUE 0x5F32335F /* "_32_" */ #define CRU_BIOS_SIGNATURE_VALUE 0x55524324 -- cgit v1.2.3 From 089ab0791d127e8ada526c4b4d18b7584be8acf0 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Tue, 15 Jul 2008 11:46:11 +0000 Subject: [WATCHDOG] Clean-up includes Use #include instead of Use #include instead of Clean-up includes. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/acquirewdt.c | 1 - drivers/watchdog/advantechwdt.c | 4 ++-- drivers/watchdog/alim1535_wdt.c | 1 - drivers/watchdog/alim7101_wdt.c | 2 +- drivers/watchdog/bfin_wdt.c | 2 +- drivers/watchdog/geodewdt.c | 2 +- drivers/watchdog/iTCO_vendor_support.c | 1 - drivers/watchdog/ib700wdt.c | 2 +- drivers/watchdog/ixp4xx_wdt.c | 2 +- drivers/watchdog/mv64x60_wdt.c | 1 - drivers/watchdog/omap_wdt.c | 3 +-- drivers/watchdog/pcwd_pci.c | 5 ++--- drivers/watchdog/pcwd_usb.c | 3 +-- drivers/watchdog/pnx4008_wdt.c | 4 ++-- 14 files changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 269ada2f1fc3..28d9057c9be6 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -65,7 +65,6 @@ #include /* For io-port access */ #include /* For platform_driver framework */ #include /* For __init/__exit/... */ - #include /* For copy_to_user/put_user/... */ #include /* For inb/outb/... */ diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index 220d238ee427..e6bf8d2d3d30 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -37,9 +37,9 @@ #include #include #include +#include +#include -#include -#include #include #define DRV_NAME "advantechwdt" diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index 88760cb5ec13..80e323ddc4ba 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c @@ -18,7 +18,6 @@ #include #include #include - #include #include diff --git a/drivers/watchdog/alim7101_wdt.c b/drivers/watchdog/alim7101_wdt.c index c495f36c6aa9..726e75d9db7a 100644 --- a/drivers/watchdog/alim7101_wdt.c +++ b/drivers/watchdog/alim7101_wdt.c @@ -31,9 +31,9 @@ #include #include #include - #include #include + #include #define OUR_NAME "alim7101_wdt" diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 2b92818cc664..8f6e871b3fe3 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -24,8 +24,8 @@ #include #include #include -#include #include +#include #define stamp(fmt, args...) pr_debug("%s:%i: " fmt "\n", __func__, __LINE__, ## args) #define stampit() stamp("here i am") diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index 30d09cbbad94..a41f57ce581a 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c @@ -17,8 +17,8 @@ #include #include #include +#include -#include #include #define GEODEWDT_HZ 500 diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c index 09e9534ac2e4..e9e1f7b3fb75 100644 --- a/drivers/watchdog/iTCO_vendor_support.c +++ b/drivers/watchdog/iTCO_vendor_support.c @@ -31,7 +31,6 @@ #include /* For printk/panic/... */ #include /* For __init/__exit/... */ #include /* For io-port access */ - #include /* For inb/outb/... */ #include "iTCO_vendor.h" diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 805a54b02aa1..9eb9537c370e 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -41,9 +41,9 @@ #include #include #include - #include #include + #include static struct platform_device *ibwdt_platform_device; diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index 24e624c847ae..1bafd7b58ca5 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c @@ -22,9 +22,9 @@ #include #include #include +#include #include -#include static int nowayout = WATCHDOG_NOWAYOUT; static int heartbeat = 60; /* (secs) Default is 1 minute */ diff --git a/drivers/watchdog/mv64x60_wdt.c b/drivers/watchdog/mv64x60_wdt.c index ac09fe4d9573..acf589dc057c 100644 --- a/drivers/watchdog/mv64x60_wdt.c +++ b/drivers/watchdog/mv64x60_wdt.c @@ -22,7 +22,6 @@ #include #include #include - #include #include #include diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index ccdf069792d9..5aae071cc045 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -40,8 +40,7 @@ #include #include #include - -#include +#include #include #include diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 61a89e959642..a1d31d1f750f 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -46,9 +46,8 @@ #include /* For pci functions */ #include /* For io-port access */ #include /* For spin_lock/spin_unlock/... */ - -#include /* For copy_to_user/put_user/... */ -#include /* For inb/outb/... */ +#include /* For copy_to_user/put_user/... */ +#include /* For inb/outb/... */ /* Module and version information */ #define WATCHDOG_VERSION "1.03" diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index bf443d077a1e..825102a33910 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -40,8 +40,7 @@ #include /* For kmalloc, ... */ #include /* For mutex locking */ #include /* For HID_REQ_SET_REPORT & HID_DT_REPORT */ - -#include /* For copy_to_user/put_user/... */ +#include /* For copy_to_user/put_user/... */ #ifdef CONFIG_USB_DEBUG diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 8cd0d53941e7..56dee3bfd4aa 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c @@ -28,11 +28,11 @@ #include #include #include - -#include #include #include +#include + #define MODULE_NAME "PNX4008-WDT: " /* WatchDog Timer - Chapter 23 Page 207 */ -- cgit v1.2.3 From c9488520512df659ad21df5d100b52fed96bdf07 Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Thu, 3 Jul 2008 23:51:32 -0700 Subject: [WATCHDOG] pcwd: a couple of watchdogs escaped conversion Fix them up. Once we know the long term plan the watchdogs can all get shrunk massively anyway Signed-off-by: Alan Cox Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/pcwd_pci.c | 8 +++----- drivers/watchdog/pcwd_usb.c | 6 +++--- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index a1d31d1f750f..67d90810c6e9 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -454,8 +454,8 @@ static ssize_t pcipcwd_write(struct file *file, const char __user *data, return len; } -static int pcipcwd_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long pcipcwd_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -477,9 +477,7 @@ static int pcipcwd_ioctl(struct inode *inode, struct file *file, case WDIOC_GETSTATUS: { int status; - pcipcwd_get_status(&status); - return put_user(status, p); } @@ -643,7 +641,7 @@ static const struct file_operations pcipcwd_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = pcipcwd_write, - .ioctl = pcipcwd_ioctl, + .unlocked_ioctl = pcipcwd_ioctl, .open = pcipcwd_open, .release = pcipcwd_release, }; diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 825102a33910..bc399cf65cf7 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -368,8 +368,8 @@ static ssize_t usb_pcwd_write(struct file *file, const char __user *data, return len; } -static int usb_pcwd_ioctl(struct inode *inode, struct file *file, - unsigned int cmd, unsigned long arg) +static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -534,7 +534,7 @@ static const struct file_operations usb_pcwd_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = usb_pcwd_write, - .ioctl = usb_pcwd_ioctl, + .unlocked_ioctl = usb_pcwd_ioctl, .open = usb_pcwd_open, .release = usb_pcwd_release, }; -- cgit v1.2.3 From ef8ab12ec2d663f9b146c920a4dd589a7e767f2d Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:32 -0700 Subject: [WATCHDOG] mpc83xx_wdt: convert to the OF platform driver This patch simply converts mpc83xx_wdt to the OF platform driver so we can directly work with the device tree without passing various stuff through platform data. Signed-off-by: Anton Vorontsov Acked-by: Stephen Rothwell Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/mpc83xx_wdt.c | 61 +++++++++++++++++++++--------------------- 1 file changed, 30 insertions(+), 31 deletions(-) diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c index 109eea0df2d0..5f1b7bff8f12 100644 --- a/drivers/watchdog/mpc83xx_wdt.c +++ b/drivers/watchdog/mpc83xx_wdt.c @@ -19,11 +19,12 @@ #include #include #include -#include +#include #include #include #include #include +#include struct mpc83xx_wdt { __be32 res0; @@ -149,52 +150,42 @@ static struct miscdevice mpc83xx_wdt_miscdev = { .fops = &mpc83xx_wdt_fops, }; -static int __devinit mpc83xx_wdt_probe(struct platform_device *dev) +static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, + const struct of_device_id *match) { - struct resource *r; int ret; - unsigned int *freq = dev->dev.platform_data; + u32 freq = fsl_get_sys_freq(); - /* get a pointer to the register memory */ - r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!freq || freq == -1) + return -EINVAL; - if (!r) { - ret = -ENODEV; - goto err_out; - } - - wd_base = ioremap(r->start, sizeof(struct mpc83xx_wdt)); - if (wd_base == NULL) { - ret = -ENOMEM; - goto err_out; - } + wd_base = of_iomap(ofdev->node, 0); + if (!wd_base) + return -ENOMEM; ret = misc_register(&mpc83xx_wdt_miscdev); if (ret) { - printk(KERN_ERR "cannot register miscdev on minor=%d " - "(err=%d)\n", - WATCHDOG_MINOR, ret); + pr_err("cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); goto err_unmap; } /* Calculate the timeout in seconds */ if (prescale) - timeout_sec = (timeout * 0x10000) / (*freq); + timeout_sec = (timeout * 0x10000) / freq; else - timeout_sec = timeout / (*freq); + timeout_sec = timeout / freq; - printk(KERN_INFO "WDT driver for MPC83xx initialized. " - "mode:%s timeout=%d (%d seconds)\n", - reset ? "reset":"interrupt", timeout, timeout_sec); + pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d " + "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, + timeout_sec); return 0; - err_unmap: iounmap(wd_base); -err_out: return ret; } -static int __devexit mpc83xx_wdt_remove(struct platform_device *dev) +static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) { misc_deregister(&mpc83xx_wdt_miscdev); iounmap(wd_base); @@ -202,7 +193,16 @@ static int __devexit mpc83xx_wdt_remove(struct platform_device *dev) return 0; } -static struct platform_driver mpc83xx_wdt_driver = { +static const struct of_device_id mpc83xx_wdt_match[] = { + { + .compatible = "mpc83xx_wdt", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpc83xx_wdt_match); + +static struct of_platform_driver mpc83xx_wdt_driver = { + .match_table = mpc83xx_wdt_match, .probe = mpc83xx_wdt_probe, .remove = __devexit_p(mpc83xx_wdt_remove), .driver = { @@ -213,12 +213,12 @@ static struct platform_driver mpc83xx_wdt_driver = { static int __init mpc83xx_wdt_init(void) { - return platform_driver_register(&mpc83xx_wdt_driver); + return of_register_platform_driver(&mpc83xx_wdt_driver); } static void __exit mpc83xx_wdt_exit(void) { - platform_driver_unregister(&mpc83xx_wdt_driver); + of_unregister_platform_driver(&mpc83xx_wdt_driver); } module_init(mpc83xx_wdt_init); @@ -228,4 +228,3 @@ MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx uProcessor"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -MODULE_ALIAS("platform:mpc83xx_wdt"); -- cgit v1.2.3 From 500c919e3d699644cc9d6c1e93022481baafd8e1 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:34 -0700 Subject: [WATCHDOG] mpc83xx_wdt: add support for MPC86xx CPUs On MPC86xx the watchdog could be enabled only at power-on-reset, and could not be disabled afterwards. We must ping the watchdog from the kernel until the userspace handles it. MPC83xx CPUs are only differ in a way that watchdog could be disabled once, but after it was enabled via software it becomes just the same as MPC86xx. Thus, to support MPC86xx I added the kernel timer which pings the watchdog until the userspace opens it. Since we implemented the timer, now we're able to implement proper handling for the CONFIG_WATCHDOG_NOWAYOUT case, for MPC83xx and MPC86xx. Also move the probe code into subsys_initcall, because we want start pinging the watchdog ASAP, and misc devices are available in subsys_initcall. Signed-off-by: Anton Vorontsov Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/Kconfig | 4 +-- drivers/watchdog/mpc83xx_wdt.c | 80 +++++++++++++++++++++++++++++++++++++----- 2 files changed, 74 insertions(+), 10 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 48399e134c0d..93329620f447 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -696,8 +696,8 @@ config 8xx_WDT depends on 8xx config 83xx_WDT - tristate "MPC83xx Watchdog Timer" - depends on PPC_83xx + tristate "MPC83xx/MPC86xx Watchdog Timer" + depends on PPC_83xx || PPC_86xx config MV64X60_WDT tristate "MV64X60 (Marvell Discovery) Watchdog Timer" diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c index 5f1b7bff8f12..fa82ec99ba81 100644 --- a/drivers/watchdog/mpc83xx_wdt.c +++ b/drivers/watchdog/mpc83xx_wdt.c @@ -1,10 +1,12 @@ /* - * mpc83xx_wdt.c - MPC83xx watchdog userspace interface + * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface * * Authors: Dave Updegraff * Kumar Gala * Attribution: from 83xx_wst: Florian Schirmer * ..and from sc520_wdt + * Copyright (c) 2008 MontaVista Software, Inc. + * Anton Vorontsov * * Note: it appears that you can only actually ENABLE or DISABLE the thing * once after POR. Once enabled, you cannot disable, and vice versa. @@ -18,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +42,11 @@ struct mpc83xx_wdt { u8 res2[0xF0]; }; +struct mpc83xx_wdt_type { + int prescaler; + bool hw_enabled; +}; + static struct mpc83xx_wdt __iomem *wd_base; static u16 timeout = 0xffff; @@ -51,6 +59,11 @@ module_param(reset, bool, 0); MODULE_PARM_DESC(reset, "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset"); +static int nowayout = WATCHDOG_NOWAYOUT; +module_param(nowayout, int, 0); +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " + "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); + /* * We always prescale, but if someone really doesn't want to they can set this * to 0 @@ -70,6 +83,22 @@ static void mpc83xx_wdt_keepalive(void) spin_unlock(&wdt_spinlock); } +static void mpc83xx_wdt_timer_ping(unsigned long arg); +static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0); + +static void mpc83xx_wdt_timer_ping(unsigned long arg) +{ + mpc83xx_wdt_keepalive(); + /* We're pinging it twice faster than needed, just to be sure. */ + mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2); +} + +static void mpc83xx_wdt_pr_warn(const char *msg) +{ + pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg, + reset ? "reset" : "machine check exception"); +} + static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { @@ -85,7 +114,8 @@ static int mpc83xx_wdt_open(struct inode *inode, struct file *file) return -EBUSY; /* Once we start the watchdog we can't stop it */ - __module_get(THIS_MODULE); + if (nowayout) + __module_get(THIS_MODULE); /* Good, fire up the show */ if (prescale) @@ -97,13 +127,17 @@ static int mpc83xx_wdt_open(struct inode *inode, struct file *file) out_be32(&wd_base->swcrr, tmp); + del_timer_sync(&wdt_timer); + return nonseekable_open(inode, file); } static int mpc83xx_wdt_release(struct inode *inode, struct file *file) { - printk(KERN_CRIT "Unexpected close, not stopping watchdog!\n"); - mpc83xx_wdt_keepalive(); + if (!nowayout) + mpc83xx_wdt_timer_ping(0); + else + mpc83xx_wdt_pr_warn("watchdog closed"); clear_bit(0, &wdt_is_open); return 0; } @@ -154,15 +188,25 @@ static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, const struct of_device_id *match) { int ret; + struct device_node *np = ofdev->node; + struct mpc83xx_wdt_type *wdt_type = match->data; u32 freq = fsl_get_sys_freq(); + bool enabled; if (!freq || freq == -1) return -EINVAL; - wd_base = of_iomap(ofdev->node, 0); + wd_base = of_iomap(np, 0); if (!wd_base) return -ENOMEM; + enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; + if (!enabled && wdt_type->hw_enabled) { + pr_info("mpc83xx_wdt: could not be enabled in software\n"); + ret = -ENOSYS; + goto err_unmap; + } + ret = misc_register(&mpc83xx_wdt_miscdev); if (ret) { pr_err("cannot register miscdev on minor=%d (err=%d)\n", @@ -172,13 +216,21 @@ static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, /* Calculate the timeout in seconds */ if (prescale) - timeout_sec = (timeout * 0x10000) / freq; + timeout_sec = (timeout * wdt_type->prescaler) / freq; else timeout_sec = timeout / freq; pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d " "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, timeout_sec); + + /* + * If the watchdog was previously enabled or we're running on + * MPC86xx, we should ping the wdt from the kernel until the + * userspace handles it. + */ + if (enabled) + mpc83xx_wdt_timer_ping(0); return 0; err_unmap: iounmap(wd_base); @@ -187,6 +239,8 @@ err_unmap: static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) { + mpc83xx_wdt_pr_warn("watchdog removed"); + del_timer_sync(&wdt_timer); misc_deregister(&mpc83xx_wdt_miscdev); iounmap(wd_base); @@ -196,6 +250,16 @@ static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) static const struct of_device_id mpc83xx_wdt_match[] = { { .compatible = "mpc83xx_wdt", + .data = &(struct mpc83xx_wdt_type) { + .prescaler = 0x10000, + }, + }, + { + .compatible = "fsl,mpc8610-wdt", + .data = &(struct mpc83xx_wdt_type) { + .prescaler = 0x10000, + .hw_enabled = true, + }, }, {}, }; @@ -221,10 +285,10 @@ static void __exit mpc83xx_wdt_exit(void) of_unregister_platform_driver(&mpc83xx_wdt_driver); } -module_init(mpc83xx_wdt_init); +subsys_initcall(mpc83xx_wdt_init); module_exit(mpc83xx_wdt_exit); MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); -MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx uProcessor"); +MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- cgit v1.2.3 From 28acd02f9f9efe44718de3bbe8be22d6dfb7e47f Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:34 -0700 Subject: [WATCHDOG] mpc83xx_wdt: rename to mpc8xxx_wdt Rename the driver because now we support some MPC86xx processors. There are no changes to the mpc83xx_wdt.c file, yet. When possible, we do file renames and changes separately (because Linus once asked so, because it helps git to track the renamed files). Signed-off-by: Anton Vorontsov Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/Kconfig | 11 +- drivers/watchdog/Makefile | 2 +- drivers/watchdog/mpc83xx_wdt.c | 294 ----------------------------------------- drivers/watchdog/mpc8xxx_wdt.c | 294 +++++++++++++++++++++++++++++++++++++++++ 4 files changed, 304 insertions(+), 297 deletions(-) delete mode 100644 drivers/watchdog/mpc83xx_wdt.c create mode 100644 drivers/watchdog/mpc8xxx_wdt.c diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 93329620f447..01e33e80eac0 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -695,9 +695,16 @@ config 8xx_WDT tristate "MPC8xx Watchdog Timer" depends on 8xx -config 83xx_WDT - tristate "MPC83xx/MPC86xx Watchdog Timer" +config 8xxx_WDT + tristate "MPC8xxx Platform Watchdog Timer" depends on PPC_83xx || PPC_86xx + help + This driver is for a SoC level watchdog that exists on some + Freescale PowerPC processors. So far this driver supports: + - MPC83xx watchdogs + - MPC86xx watchdogs + + For BookE processors (MPC85xx) use the BOOKE_WDT driver instead. config MV64X60_WDT tristate "MV64X60 (Marvell Discovery) Watchdog Timer" diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index edd305a64e63..cdd674ffaa21 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -103,7 +103,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o # POWERPC Architecture obj-$(CONFIG_8xx_WDT) += mpc8xx_wdt.o obj-$(CONFIG_MPC5200_WDT) += mpc5200_wdt.o -obj-$(CONFIG_83xx_WDT) += mpc83xx_wdt.o +obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o diff --git a/drivers/watchdog/mpc83xx_wdt.c b/drivers/watchdog/mpc83xx_wdt.c deleted file mode 100644 index fa82ec99ba81..000000000000 --- a/drivers/watchdog/mpc83xx_wdt.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface - * - * Authors: Dave Updegraff - * Kumar Gala - * Attribution: from 83xx_wst: Florian Schirmer - * ..and from sc520_wdt - * Copyright (c) 2008 MontaVista Software, Inc. - * Anton Vorontsov - * - * Note: it appears that you can only actually ENABLE or DISABLE the thing - * once after POR. Once enabled, you cannot disable, and vice versa. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -struct mpc83xx_wdt { - __be32 res0; - __be32 swcrr; /* System watchdog control register */ -#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ -#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ -#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ -#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ - __be32 swcnr; /* System watchdog count register */ - u8 res1[2]; - __be16 swsrr; /* System watchdog service register */ - u8 res2[0xF0]; -}; - -struct mpc83xx_wdt_type { - int prescaler; - bool hw_enabled; -}; - -static struct mpc83xx_wdt __iomem *wd_base; - -static u16 timeout = 0xffff; -module_param(timeout, ushort, 0); -MODULE_PARM_DESC(timeout, - "Watchdog timeout in ticks. (0swsrr, 0x556c); - out_be16(&wd_base->swsrr, 0xaa39); - spin_unlock(&wdt_spinlock); -} - -static void mpc83xx_wdt_timer_ping(unsigned long arg); -static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0); - -static void mpc83xx_wdt_timer_ping(unsigned long arg) -{ - mpc83xx_wdt_keepalive(); - /* We're pinging it twice faster than needed, just to be sure. */ - mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2); -} - -static void mpc83xx_wdt_pr_warn(const char *msg) -{ - pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg, - reset ? "reset" : "machine check exception"); -} - -static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) -{ - if (count) - mpc83xx_wdt_keepalive(); - return count; -} - -static int mpc83xx_wdt_open(struct inode *inode, struct file *file) -{ - u32 tmp = SWCRR_SWEN; - if (test_and_set_bit(0, &wdt_is_open)) - return -EBUSY; - - /* Once we start the watchdog we can't stop it */ - if (nowayout) - __module_get(THIS_MODULE); - - /* Good, fire up the show */ - if (prescale) - tmp |= SWCRR_SWPR; - if (reset) - tmp |= SWCRR_SWRI; - - tmp |= timeout << 16; - - out_be32(&wd_base->swcrr, tmp); - - del_timer_sync(&wdt_timer); - - return nonseekable_open(inode, file); -} - -static int mpc83xx_wdt_release(struct inode *inode, struct file *file) -{ - if (!nowayout) - mpc83xx_wdt_timer_ping(0); - else - mpc83xx_wdt_pr_warn("watchdog closed"); - clear_bit(0, &wdt_is_open); - return 0; -} - -static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, - unsigned long arg) -{ - void __user *argp = (void __user *)arg; - int __user *p = argp; - static struct watchdog_info ident = { - .options = WDIOF_KEEPALIVEPING, - .firmware_version = 1, - .identity = "MPC83xx", - }; - - switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); - case WDIOC_KEEPALIVE: - mpc83xx_wdt_keepalive(); - return 0; - case WDIOC_GETTIMEOUT: - return put_user(timeout_sec, p); - default: - return -ENOTTY; - } -} - -static const struct file_operations mpc83xx_wdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = mpc83xx_wdt_write, - .unlocked_ioctl = mpc83xx_wdt_ioctl, - .open = mpc83xx_wdt_open, - .release = mpc83xx_wdt_release, -}; - -static struct miscdevice mpc83xx_wdt_miscdev = { - .minor = WATCHDOG_MINOR, - .name = "watchdog", - .fops = &mpc83xx_wdt_fops, -}; - -static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, - const struct of_device_id *match) -{ - int ret; - struct device_node *np = ofdev->node; - struct mpc83xx_wdt_type *wdt_type = match->data; - u32 freq = fsl_get_sys_freq(); - bool enabled; - - if (!freq || freq == -1) - return -EINVAL; - - wd_base = of_iomap(np, 0); - if (!wd_base) - return -ENOMEM; - - enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; - if (!enabled && wdt_type->hw_enabled) { - pr_info("mpc83xx_wdt: could not be enabled in software\n"); - ret = -ENOSYS; - goto err_unmap; - } - - ret = misc_register(&mpc83xx_wdt_miscdev); - if (ret) { - pr_err("cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); - goto err_unmap; - } - - /* Calculate the timeout in seconds */ - if (prescale) - timeout_sec = (timeout * wdt_type->prescaler) / freq; - else - timeout_sec = timeout / freq; - - pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d " - "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, - timeout_sec); - - /* - * If the watchdog was previously enabled or we're running on - * MPC86xx, we should ping the wdt from the kernel until the - * userspace handles it. - */ - if (enabled) - mpc83xx_wdt_timer_ping(0); - return 0; -err_unmap: - iounmap(wd_base); - return ret; -} - -static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) -{ - mpc83xx_wdt_pr_warn("watchdog removed"); - del_timer_sync(&wdt_timer); - misc_deregister(&mpc83xx_wdt_miscdev); - iounmap(wd_base); - - return 0; -} - -static const struct of_device_id mpc83xx_wdt_match[] = { - { - .compatible = "mpc83xx_wdt", - .data = &(struct mpc83xx_wdt_type) { - .prescaler = 0x10000, - }, - }, - { - .compatible = "fsl,mpc8610-wdt", - .data = &(struct mpc83xx_wdt_type) { - .prescaler = 0x10000, - .hw_enabled = true, - }, - }, - {}, -}; -MODULE_DEVICE_TABLE(of, mpc83xx_wdt_match); - -static struct of_platform_driver mpc83xx_wdt_driver = { - .match_table = mpc83xx_wdt_match, - .probe = mpc83xx_wdt_probe, - .remove = __devexit_p(mpc83xx_wdt_remove), - .driver = { - .name = "mpc83xx_wdt", - .owner = THIS_MODULE, - }, -}; - -static int __init mpc83xx_wdt_init(void) -{ - return of_register_platform_driver(&mpc83xx_wdt_driver); -} - -static void __exit mpc83xx_wdt_exit(void) -{ - of_unregister_platform_driver(&mpc83xx_wdt_driver); -} - -subsys_initcall(mpc83xx_wdt_init); -module_exit(mpc83xx_wdt_exit); - -MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); -MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors"); -MODULE_LICENSE("GPL"); -MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c new file mode 100644 index 000000000000..fa82ec99ba81 --- /dev/null +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -0,0 +1,294 @@ +/* + * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface + * + * Authors: Dave Updegraff + * Kumar Gala + * Attribution: from 83xx_wst: Florian Schirmer + * ..and from sc520_wdt + * Copyright (c) 2008 MontaVista Software, Inc. + * Anton Vorontsov + * + * Note: it appears that you can only actually ENABLE or DISABLE the thing + * once after POR. Once enabled, you cannot disable, and vice versa. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mpc83xx_wdt { + __be32 res0; + __be32 swcrr; /* System watchdog control register */ +#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ +#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ +#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/ +#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ + __be32 swcnr; /* System watchdog count register */ + u8 res1[2]; + __be16 swsrr; /* System watchdog service register */ + u8 res2[0xF0]; +}; + +struct mpc83xx_wdt_type { + int prescaler; + bool hw_enabled; +}; + +static struct mpc83xx_wdt __iomem *wd_base; + +static u16 timeout = 0xffff; +module_param(timeout, ushort, 0); +MODULE_PARM_DESC(timeout, + "Watchdog timeout in ticks. (0swsrr, 0x556c); + out_be16(&wd_base->swsrr, 0xaa39); + spin_unlock(&wdt_spinlock); +} + +static void mpc83xx_wdt_timer_ping(unsigned long arg); +static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0); + +static void mpc83xx_wdt_timer_ping(unsigned long arg) +{ + mpc83xx_wdt_keepalive(); + /* We're pinging it twice faster than needed, just to be sure. */ + mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2); +} + +static void mpc83xx_wdt_pr_warn(const char *msg) +{ + pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg, + reset ? "reset" : "machine check exception"); +} + +static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) +{ + if (count) + mpc83xx_wdt_keepalive(); + return count; +} + +static int mpc83xx_wdt_open(struct inode *inode, struct file *file) +{ + u32 tmp = SWCRR_SWEN; + if (test_and_set_bit(0, &wdt_is_open)) + return -EBUSY; + + /* Once we start the watchdog we can't stop it */ + if (nowayout) + __module_get(THIS_MODULE); + + /* Good, fire up the show */ + if (prescale) + tmp |= SWCRR_SWPR; + if (reset) + tmp |= SWCRR_SWRI; + + tmp |= timeout << 16; + + out_be32(&wd_base->swcrr, tmp); + + del_timer_sync(&wdt_timer); + + return nonseekable_open(inode, file); +} + +static int mpc83xx_wdt_release(struct inode *inode, struct file *file) +{ + if (!nowayout) + mpc83xx_wdt_timer_ping(0); + else + mpc83xx_wdt_pr_warn("watchdog closed"); + clear_bit(0, &wdt_is_open); + return 0; +} + +static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + void __user *argp = (void __user *)arg; + int __user *p = argp; + static struct watchdog_info ident = { + .options = WDIOF_KEEPALIVEPING, + .firmware_version = 1, + .identity = "MPC83xx", + }; + + switch (cmd) { + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); + case WDIOC_KEEPALIVE: + mpc83xx_wdt_keepalive(); + return 0; + case WDIOC_GETTIMEOUT: + return put_user(timeout_sec, p); + default: + return -ENOTTY; + } +} + +static const struct file_operations mpc83xx_wdt_fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = mpc83xx_wdt_write, + .unlocked_ioctl = mpc83xx_wdt_ioctl, + .open = mpc83xx_wdt_open, + .release = mpc83xx_wdt_release, +}; + +static struct miscdevice mpc83xx_wdt_miscdev = { + .minor = WATCHDOG_MINOR, + .name = "watchdog", + .fops = &mpc83xx_wdt_fops, +}; + +static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, + const struct of_device_id *match) +{ + int ret; + struct device_node *np = ofdev->node; + struct mpc83xx_wdt_type *wdt_type = match->data; + u32 freq = fsl_get_sys_freq(); + bool enabled; + + if (!freq || freq == -1) + return -EINVAL; + + wd_base = of_iomap(np, 0); + if (!wd_base) + return -ENOMEM; + + enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; + if (!enabled && wdt_type->hw_enabled) { + pr_info("mpc83xx_wdt: could not be enabled in software\n"); + ret = -ENOSYS; + goto err_unmap; + } + + ret = misc_register(&mpc83xx_wdt_miscdev); + if (ret) { + pr_err("cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); + goto err_unmap; + } + + /* Calculate the timeout in seconds */ + if (prescale) + timeout_sec = (timeout * wdt_type->prescaler) / freq; + else + timeout_sec = timeout / freq; + + pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d " + "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, + timeout_sec); + + /* + * If the watchdog was previously enabled or we're running on + * MPC86xx, we should ping the wdt from the kernel until the + * userspace handles it. + */ + if (enabled) + mpc83xx_wdt_timer_ping(0); + return 0; +err_unmap: + iounmap(wd_base); + return ret; +} + +static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) +{ + mpc83xx_wdt_pr_warn("watchdog removed"); + del_timer_sync(&wdt_timer); + misc_deregister(&mpc83xx_wdt_miscdev); + iounmap(wd_base); + + return 0; +} + +static const struct of_device_id mpc83xx_wdt_match[] = { + { + .compatible = "mpc83xx_wdt", + .data = &(struct mpc83xx_wdt_type) { + .prescaler = 0x10000, + }, + }, + { + .compatible = "fsl,mpc8610-wdt", + .data = &(struct mpc83xx_wdt_type) { + .prescaler = 0x10000, + .hw_enabled = true, + }, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mpc83xx_wdt_match); + +static struct of_platform_driver mpc83xx_wdt_driver = { + .match_table = mpc83xx_wdt_match, + .probe = mpc83xx_wdt_probe, + .remove = __devexit_p(mpc83xx_wdt_remove), + .driver = { + .name = "mpc83xx_wdt", + .owner = THIS_MODULE, + }, +}; + +static int __init mpc83xx_wdt_init(void) +{ + return of_register_platform_driver(&mpc83xx_wdt_driver); +} + +static void __exit mpc83xx_wdt_exit(void) +{ + of_unregister_platform_driver(&mpc83xx_wdt_driver); +} + +subsys_initcall(mpc83xx_wdt_init); +module_exit(mpc83xx_wdt_exit); + +MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); +MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- cgit v1.2.3 From 59ca1b0d14ca71bdefef372ccd5035341e0ca091 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:35 -0700 Subject: [WATCHDOG] mpc8xxx_wdt: various renames, mostly s/mpc83xx/mpc8xxx/g mpc83xx_wdt.c renamed to mpc8xxx_wdt.c, now we can do various renames in the file itself. Signed-off-by: Anton Vorontsov Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/mpc8xxx_wdt.c | 104 ++++++++++++++++++++--------------------- 1 file changed, 52 insertions(+), 52 deletions(-) diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index fa82ec99ba81..8b82b91caee7 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -1,5 +1,5 @@ /* - * mpc83xx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface + * mpc8xxx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface * * Authors: Dave Updegraff * Kumar Gala @@ -29,7 +29,7 @@ #include #include -struct mpc83xx_wdt { +struct mpc8xxx_wdt { __be32 res0; __be32 swcrr; /* System watchdog control register */ #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ @@ -42,12 +42,12 @@ struct mpc83xx_wdt { u8 res2[0xF0]; }; -struct mpc83xx_wdt_type { +struct mpc8xxx_wdt_type { int prescaler; bool hw_enabled; }; -static struct mpc83xx_wdt __iomem *wd_base; +static struct mpc8xxx_wdt __iomem *wd_base; static u16 timeout = 0xffff; module_param(timeout, ushort, 0); @@ -74,7 +74,7 @@ static unsigned int timeout_sec; static unsigned long wdt_is_open; static DEFINE_SPINLOCK(wdt_spinlock); -static void mpc83xx_wdt_keepalive(void) +static void mpc8xxx_wdt_keepalive(void) { /* Ping the WDT */ spin_lock(&wdt_spinlock); @@ -83,31 +83,31 @@ static void mpc83xx_wdt_keepalive(void) spin_unlock(&wdt_spinlock); } -static void mpc83xx_wdt_timer_ping(unsigned long arg); -static DEFINE_TIMER(wdt_timer, mpc83xx_wdt_timer_ping, 0, 0); +static void mpc8xxx_wdt_timer_ping(unsigned long arg); +static DEFINE_TIMER(wdt_timer, mpc8xxx_wdt_timer_ping, 0, 0); -static void mpc83xx_wdt_timer_ping(unsigned long arg) +static void mpc8xxx_wdt_timer_ping(unsigned long arg) { - mpc83xx_wdt_keepalive(); + mpc8xxx_wdt_keepalive(); /* We're pinging it twice faster than needed, just to be sure. */ mod_timer(&wdt_timer, jiffies + HZ * timeout_sec / 2); } -static void mpc83xx_wdt_pr_warn(const char *msg) +static void mpc8xxx_wdt_pr_warn(const char *msg) { - pr_crit("mpc83xx_wdt: %s, expect the %s soon!\n", msg, + pr_crit("mpc8xxx_wdt: %s, expect the %s soon!\n", msg, reset ? "reset" : "machine check exception"); } -static ssize_t mpc83xx_wdt_write(struct file *file, const char __user *buf, +static ssize_t mpc8xxx_wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) { if (count) - mpc83xx_wdt_keepalive(); + mpc8xxx_wdt_keepalive(); return count; } -static int mpc83xx_wdt_open(struct inode *inode, struct file *file) +static int mpc8xxx_wdt_open(struct inode *inode, struct file *file) { u32 tmp = SWCRR_SWEN; if (test_and_set_bit(0, &wdt_is_open)) @@ -132,17 +132,17 @@ static int mpc83xx_wdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int mpc83xx_wdt_release(struct inode *inode, struct file *file) +static int mpc8xxx_wdt_release(struct inode *inode, struct file *file) { if (!nowayout) - mpc83xx_wdt_timer_ping(0); + mpc8xxx_wdt_timer_ping(0); else - mpc83xx_wdt_pr_warn("watchdog closed"); + mpc8xxx_wdt_pr_warn("watchdog closed"); clear_bit(0, &wdt_is_open); return 0; } -static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, +static long mpc8xxx_wdt_ioctl(struct inode *inode, struct file *file, unsigned long arg) { void __user *argp = (void __user *)arg; @@ -150,7 +150,7 @@ static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, static struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING, .firmware_version = 1, - .identity = "MPC83xx", + .identity = "MPC8xxx", }; switch (cmd) { @@ -160,7 +160,7 @@ static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, p); case WDIOC_KEEPALIVE: - mpc83xx_wdt_keepalive(); + mpc8xxx_wdt_keepalive(); return 0; case WDIOC_GETTIMEOUT: return put_user(timeout_sec, p); @@ -169,27 +169,27 @@ static long mpc83xx_wdt_ioctl(struct file *file, unsigned int cmd, } } -static const struct file_operations mpc83xx_wdt_fops = { +static const struct file_operations mpc8xxx_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, - .write = mpc83xx_wdt_write, - .unlocked_ioctl = mpc83xx_wdt_ioctl, - .open = mpc83xx_wdt_open, - .release = mpc83xx_wdt_release, + .write = mpc8xxx_wdt_write, + .unlocked_ioctl = mpc8xxx_wdt_ioctl, + .open = mpc8xxx_wdt_open, + .release = mpc8xxx_wdt_release, }; -static struct miscdevice mpc83xx_wdt_miscdev = { +static struct miscdevice mpc8xxx_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", - .fops = &mpc83xx_wdt_fops, + .fops = &mpc8xxx_wdt_fops, }; -static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, +static int __devinit mpc8xxx_wdt_probe(struct of_device *ofdev, const struct of_device_id *match) { int ret; struct device_node *np = ofdev->node; - struct mpc83xx_wdt_type *wdt_type = match->data; + struct mpc8xxx_wdt_type *wdt_type = match->data; u32 freq = fsl_get_sys_freq(); bool enabled; @@ -202,12 +202,12 @@ static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, enabled = in_be32(&wd_base->swcrr) & SWCRR_SWEN; if (!enabled && wdt_type->hw_enabled) { - pr_info("mpc83xx_wdt: could not be enabled in software\n"); + pr_info("mpc8xxx_wdt: could not be enabled in software\n"); ret = -ENOSYS; goto err_unmap; } - ret = misc_register(&mpc83xx_wdt_miscdev); + ret = misc_register(&mpc8xxx_wdt_miscdev); if (ret) { pr_err("cannot register miscdev on minor=%d (err=%d)\n", WATCHDOG_MINOR, ret); @@ -220,73 +220,73 @@ static int __devinit mpc83xx_wdt_probe(struct of_device *ofdev, else timeout_sec = timeout / freq; - pr_info("WDT driver for MPC83xx initialized. mode:%s timeout=%d " + pr_info("WDT driver for MPC8xxx initialized. mode:%s timeout=%d " "(%d seconds)\n", reset ? "reset" : "interrupt", timeout, timeout_sec); /* * If the watchdog was previously enabled or we're running on - * MPC86xx, we should ping the wdt from the kernel until the + * MPC8xxx, we should ping the wdt from the kernel until the * userspace handles it. */ if (enabled) - mpc83xx_wdt_timer_ping(0); + mpc8xxx_wdt_timer_ping(0); return 0; err_unmap: iounmap(wd_base); return ret; } -static int __devexit mpc83xx_wdt_remove(struct of_device *ofdev) +static int __devexit mpc8xxx_wdt_remove(struct of_device *ofdev) { - mpc83xx_wdt_pr_warn("watchdog removed"); + mpc8xxx_wdt_pr_warn("watchdog removed"); del_timer_sync(&wdt_timer); - misc_deregister(&mpc83xx_wdt_miscdev); + misc_deregister(&mpc8xxx_wdt_miscdev); iounmap(wd_base); return 0; } -static const struct of_device_id mpc83xx_wdt_match[] = { +static const struct of_device_id mpc8xxx_wdt_match[] = { { .compatible = "mpc83xx_wdt", - .data = &(struct mpc83xx_wdt_type) { + .data = &(struct mpc8xxx_wdt_type) { .prescaler = 0x10000, }, }, { .compatible = "fsl,mpc8610-wdt", - .data = &(struct mpc83xx_wdt_type) { + .data = &(struct mpc8xxx_wdt_type) { .prescaler = 0x10000, .hw_enabled = true, }, }, {}, }; -MODULE_DEVICE_TABLE(of, mpc83xx_wdt_match); +MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match); -static struct of_platform_driver mpc83xx_wdt_driver = { - .match_table = mpc83xx_wdt_match, - .probe = mpc83xx_wdt_probe, - .remove = __devexit_p(mpc83xx_wdt_remove), +static struct of_platform_driver mpc8xxx_wdt_driver = { + .match_table = mpc8xxx_wdt_match, + .probe = mpc8xxx_wdt_probe, + .remove = __devexit_p(mpc8xxx_wdt_remove), .driver = { - .name = "mpc83xx_wdt", + .name = "mpc8xxx_wdt", .owner = THIS_MODULE, }, }; -static int __init mpc83xx_wdt_init(void) +static int __init mpc8xxx_wdt_init(void) { - return of_register_platform_driver(&mpc83xx_wdt_driver); + return of_register_platform_driver(&mpc8xxx_wdt_driver); } -static void __exit mpc83xx_wdt_exit(void) +static void __exit mpc8xxx_wdt_exit(void) { - of_unregister_platform_driver(&mpc83xx_wdt_driver); + of_unregister_platform_driver(&mpc8xxx_wdt_driver); } -subsys_initcall(mpc83xx_wdt_init); -module_exit(mpc83xx_wdt_exit); +subsys_initcall(mpc8xxx_wdt_init); +module_exit(mpc8xxx_wdt_exit); MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors"); -- cgit v1.2.3 From cb55d282a0d2156e7d40ee81726ab16b569e96d7 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:36 -0700 Subject: [WATCHDOG] mpc8xxx_wdt: fix build CC drivers/watchdog/mpc8xxx_wdt.o drivers/watchdog/mpc8xxx_wdt.c: In function 'mpc8xxx_wdt_ioctl': drivers/watchdog/mpc8xxx_wdt.c:156: error: 'cmd' undeclared (first use in this function) drivers/watchdog/mpc8xxx_wdt.c:156: error: (Each undeclared identifier is reported only once drivers/watchdog/mpc8xxx_wdt.c:156: error: for each function it appears in.) drivers/watchdog/mpc8xxx_wdt.c: At top level: drivers/watchdog/mpc8xxx_wdt.c:176: warning: initialization from incompatible pointer type This patch ought to be folded into mpc8xxx_wdt-various-renames-mostly-s-mpc83xx-mpc8xxx-g.patch Signed-off-by: Anton Vorontsov Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/mpc8xxx_wdt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 8b82b91caee7..3c5ed9e26226 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -142,7 +142,7 @@ static int mpc8xxx_wdt_release(struct inode *inode, struct file *file) return 0; } -static long mpc8xxx_wdt_ioctl(struct inode *inode, struct file *file, +static long mpc8xxx_wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; -- cgit v1.2.3 From 0d7b101404f7bedcf3f448c1667c3744551cd9ee Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 3 Jul 2008 23:51:36 -0700 Subject: [WATCHDOG] mpc8xxx_wdt: add support for MPC8xx watchdogs The mpc8xxx_wdt driver is using two registers: SWSRR to push magic numbers, and SWCRR to control the watchdog. Both registers are available on the MPC8xx, and seem to have the same offsets and semantics as in MPC83xx/MPC86xx watchdogs. The only difference is prescale value. So this driver simply works on the MPC8xx CPUs. One quirk is needed for the MPC8xx, though. It has small prescale value and slow CPU, so the watchdog resets board prior to the driver has time to load. To solve this we should split initialization in two steps: start ping the watchdog early, and register the watchdog userspace interface later. MPC823 seem to be the first CPU in MPC8xx line, so we use fsl,mpc823-wdt compatible matching. Signed-off-by: Anton Vorontsov Tested-by: Jochen Friedrich Cc: Kumar Gala Signed-off-by: Wim Van Sebroeck Signed-off-by: Andrew Morton --- drivers/watchdog/Kconfig | 3 ++- drivers/watchdog/mpc8xxx_wdt.c | 44 +++++++++++++++++++++++++++++++----------- 2 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 01e33e80eac0..50d44b4b466b 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -697,10 +697,11 @@ config 8xx_WDT config 8xxx_WDT tristate "MPC8xxx Platform Watchdog Timer" - depends on PPC_83xx || PPC_86xx + depends on PPC_8xx || PPC_83xx || PPC_86xx help This driver is for a SoC level watchdog that exists on some Freescale PowerPC processors. So far this driver supports: + - MPC8xx watchdogs - MPC83xx watchdogs - MPC86xx watchdogs diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 3c5ed9e26226..f2094960e662 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -1,5 +1,5 @@ /* - * mpc8xxx_wdt.c - MPC83xx/MPC86xx watchdog userspace interface + * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface * * Authors: Dave Updegraff * Kumar Gala @@ -207,13 +207,6 @@ static int __devinit mpc8xxx_wdt_probe(struct of_device *ofdev, goto err_unmap; } - ret = misc_register(&mpc8xxx_wdt_miscdev); - if (ret) { - pr_err("cannot register miscdev on minor=%d (err=%d)\n", - WATCHDOG_MINOR, ret); - goto err_unmap; - } - /* Calculate the timeout in seconds */ if (prescale) timeout_sec = (timeout * wdt_type->prescaler) / freq; @@ -234,6 +227,7 @@ static int __devinit mpc8xxx_wdt_probe(struct of_device *ofdev, return 0; err_unmap: iounmap(wd_base); + wd_base = NULL; return ret; } @@ -261,6 +255,12 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { .hw_enabled = true, }, }, + { + .compatible = "fsl,mpc823-wdt", + .data = &(struct mpc8xxx_wdt_type) { + .prescaler = 0x800, + }, + }, {}, }; MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match); @@ -275,20 +275,42 @@ static struct of_platform_driver mpc8xxx_wdt_driver = { }, }; +/* + * We do wdt initialization in two steps: arch_initcall probes the wdt + * very early to start pinging the watchdog (misc devices are not yet + * available), and later module_init() just registers the misc device. + */ +static int __init mpc8xxx_wdt_init_late(void) +{ + int ret; + + if (!wd_base) + return -ENODEV; + + ret = misc_register(&mpc8xxx_wdt_miscdev); + if (ret) { + pr_err("cannot register miscdev on minor=%d (err=%d)\n", + WATCHDOG_MINOR, ret); + return ret; + } + return 0; +} +module_init(mpc8xxx_wdt_init_late); + static int __init mpc8xxx_wdt_init(void) { return of_register_platform_driver(&mpc8xxx_wdt_driver); } +arch_initcall(mpc8xxx_wdt_init); static void __exit mpc8xxx_wdt_exit(void) { of_unregister_platform_driver(&mpc8xxx_wdt_driver); } - -subsys_initcall(mpc8xxx_wdt_init); module_exit(mpc8xxx_wdt_exit); MODULE_AUTHOR("Dave Updegraff, Kumar Gala"); -MODULE_DESCRIPTION("Driver for watchdog timer in MPC83xx/MPC86xx uProcessors"); +MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx " + "uProcessors"); MODULE_LICENSE("GPL"); MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); -- cgit v1.2.3 From 5eb82498e3a6da8a979c48945e3c1a85c10ccc25 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Thu, 17 Jul 2008 18:08:47 +0000 Subject: [WATCHDOG] Coding style - Indentation - part 1 This brings the watchdog drivers into line with coding style. This patch takes cares of the indentation as described in chapter 1: The preferred way to ease multiple indentation levels in a switch statement is to align the "switch" and its subordinate "case" labels in the same column instead of "double-indenting" the "case" labels. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/acquirewdt.c | 2 +- drivers/watchdog/geodewdt.c | 2 +- drivers/watchdog/pcwd_pci.c | 128 +++++++++++++++++++++--------------------- drivers/watchdog/pcwd_usb.c | 104 +++++++++++++++++----------------- drivers/watchdog/sc1200wdt.c | 1 - drivers/watchdog/sc520_wdt.c | 3 +- 6 files changed, 119 insertions(+), 121 deletions(-) diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 28d9057c9be6..340d1eeec16b 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -169,7 +169,7 @@ static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return 0; case WDIOC_GETTIMEOUT: - return put_user(WATCHDOG_HEARTBEAT, p); + return put_user(WATCHDOG_HEARTBEAT, p); case WDIOC_SETOPTIONS: { diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index a41f57ce581a..74c00698801d 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c @@ -149,7 +149,7 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, .identity = WATCHDOG_NAME, }; - switch(cmd) { + switch (cmd) { case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 67d90810c6e9..7f500ee4ee8a 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -470,90 +470,90 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, - sizeof (ident)) ? -EFAULT : 0; - - case WDIOC_GETSTATUS: - { - int status; - pcipcwd_get_status(&status); - return put_user(status, p); - } + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, + sizeof (ident)) ? -EFAULT : 0; + + case WDIOC_GETSTATUS: + { + int status; + pcipcwd_get_status(&status); + return put_user(status, p); + } - case WDIOC_GETBOOTSTATUS: - return put_user(pcipcwd_private.boot_status, p); + case WDIOC_GETBOOTSTATUS: + return put_user(pcipcwd_private.boot_status, p); - case WDIOC_GETTEMP: - { - int temperature; + case WDIOC_GETTEMP: + { + int temperature; - if (pcipcwd_get_temperature(&temperature)) - return -EFAULT; + if (pcipcwd_get_temperature(&temperature)) + return -EFAULT; - return put_user(temperature, p); - } - - case WDIOC_KEEPALIVE: - pcipcwd_keepalive(); - return 0; + return put_user(temperature, p); + } - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; + case WDIOC_KEEPALIVE: + pcipcwd_keepalive(); + return 0; - if (get_user (new_options, p)) - return -EFAULT; + case WDIOC_SETOPTIONS: + { + int new_options, retval = -EINVAL; - if (new_options & WDIOS_DISABLECARD) { - if (pcipcwd_stop()) - return -EIO; - retval = 0; - } + if (get_user (new_options, p)) + return -EFAULT; - if (new_options & WDIOS_ENABLECARD) { - if (pcipcwd_start()) - return -EIO; - retval = 0; - } + if (new_options & WDIOS_DISABLECARD) { + if (pcipcwd_stop()) + return -EIO; + retval = 0; + } - if (new_options & WDIOS_TEMPPANIC) { - temp_panic = 1; - retval = 0; - } + if (new_options & WDIOS_ENABLECARD) { + if (pcipcwd_start()) + return -EIO; + retval = 0; + } - return retval; + if (new_options & WDIOS_TEMPPANIC) { + temp_panic = 1; + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_heartbeat; + return retval; + } - if (get_user(new_heartbeat, p)) - return -EFAULT; + case WDIOC_SETTIMEOUT: + { + int new_heartbeat; - if (pcipcwd_set_heartbeat(new_heartbeat)) - return -EINVAL; + if (get_user(new_heartbeat, p)) + return -EFAULT; - pcipcwd_keepalive(); - /* Fall */ - } + if (pcipcwd_set_heartbeat(new_heartbeat)) + return -EINVAL; - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, p); + pcipcwd_keepalive(); + /* Fall */ + } - case WDIOC_GETTIMELEFT: - { - int time_left; + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, p); - if (pcipcwd_get_timeleft(&time_left)) - return -EFAULT; + case WDIOC_GETTIMELEFT: + { + int time_left; - return put_user(time_left, p); - } + if (pcipcwd_get_timeleft(&time_left)) + return -EFAULT; + + return put_user(time_left, p); + } - default: - return -ENOTTY; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index bc399cf65cf7..8194435052c8 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -382,77 +382,77 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, - sizeof (ident)) ? -EFAULT : 0; + case WDIOC_GETSUPPORT: + return copy_to_user(argp, &ident, + sizeof (ident)) ? -EFAULT : 0; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - return put_user(0, p); + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + return put_user(0, p); - case WDIOC_GETTEMP: - { - int temperature; + case WDIOC_GETTEMP: + { + int temperature; - if (usb_pcwd_get_temperature(usb_pcwd_device, &temperature)) - return -EFAULT; + if (usb_pcwd_get_temperature(usb_pcwd_device, &temperature)) + return -EFAULT; - return put_user(temperature, p); - } + return put_user(temperature, p); + } - case WDIOC_KEEPALIVE: - usb_pcwd_keepalive(usb_pcwd_device); - return 0; + case WDIOC_KEEPALIVE: + usb_pcwd_keepalive(usb_pcwd_device); + return 0; - case WDIOC_SETOPTIONS: - { - int new_options, retval = -EINVAL; + case WDIOC_SETOPTIONS: + { + int new_options, retval = -EINVAL; - if (get_user (new_options, p)) - return -EFAULT; + if (get_user (new_options, p)) + return -EFAULT; - if (new_options & WDIOS_DISABLECARD) { - usb_pcwd_stop(usb_pcwd_device); - retval = 0; - } - - if (new_options & WDIOS_ENABLECARD) { - usb_pcwd_start(usb_pcwd_device); - retval = 0; - } + if (new_options & WDIOS_DISABLECARD) { + usb_pcwd_stop(usb_pcwd_device); + retval = 0; + } - return retval; + if (new_options & WDIOS_ENABLECARD) { + usb_pcwd_start(usb_pcwd_device); + retval = 0; } - case WDIOC_SETTIMEOUT: - { - int new_heartbeat; + return retval; + } - if (get_user(new_heartbeat, p)) - return -EFAULT; + case WDIOC_SETTIMEOUT: + { + int new_heartbeat; - if (usb_pcwd_set_heartbeat(usb_pcwd_device, new_heartbeat)) - return -EINVAL; + if (get_user(new_heartbeat, p)) + return -EFAULT; - usb_pcwd_keepalive(usb_pcwd_device); - /* Fall */ - } + if (usb_pcwd_set_heartbeat(usb_pcwd_device, new_heartbeat)) + return -EINVAL; - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, p); + usb_pcwd_keepalive(usb_pcwd_device); + /* Fall */ + } - case WDIOC_GETTIMELEFT: - { - int time_left; + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, p); - if (usb_pcwd_get_timeleft(usb_pcwd_device, &time_left)) - return -EFAULT; + case WDIOC_GETTIMELEFT: + { + int time_left; - return put_user(time_left, p); - } + if (usb_pcwd_get_timeleft(usb_pcwd_device, &time_left)) + return -EFAULT; + + return put_user(time_left, p); + } - default: - return -ENOTTY; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index 621ebad56d86..03e67fa4d689 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c @@ -196,7 +196,6 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - case WDIOC_GETSUPPORT: if (copy_to_user(argp, &ident, sizeof ident)) return -EFAULT; diff --git a/drivers/watchdog/sc520_wdt.c b/drivers/watchdog/sc520_wdt.c index 01de239f49e8..1d5ba15dec63 100644 --- a/drivers/watchdog/sc520_wdt.c +++ b/drivers/watchdog/sc520_wdt.c @@ -290,8 +290,7 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) .identity = "SC520", }; - switch (cmd) - { + switch (cmd) { default: return -ENOTTY; case WDIOC_GETSUPPORT: -- cgit v1.2.3 From 0c06090c9472db0525cb6fe229c3bea33bbbbb3c Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Fri, 18 Jul 2008 11:41:17 +0000 Subject: [WATCHDOG] Coding style - Indentation - part 2 This brings the watchdog drivers into line with coding style. This patch takes cares of the indentation as described in chapter 1. Main changes: * Re-structure the ioctl switch call for all drivers as follows: switch (cmd) { case WDIOC_GETSUPPORT: case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: case WDIOC_GETTEMP: case WDIOC_SETOPTIONS: case WDIOC_KEEPALIVE: case WDIOC_SETTIMEOUT: case WDIOC_GETTIMEOUT: case WDIOC_GETTIMELEFT: default: } This to make the migration from the drivers to the uniform watchdog device driver easier in the future. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/acquirewdt.c | 14 +++++----- drivers/watchdog/advantechwdt.c | 26 +++++++++---------- drivers/watchdog/alim1535_wdt.c | 6 ++--- drivers/watchdog/alim7101_wdt.c | 6 ++--- drivers/watchdog/ar7_wdt.c | 4 +-- drivers/watchdog/at32ap700x_wdt.c | 34 ++++++++++++------------ drivers/watchdog/at91rm9200_wdt.c | 28 ++++++++++---------- drivers/watchdog/bfin_wdt.c | 28 ++++++++++---------- drivers/watchdog/booke_wdt.c | 18 ++++++------- drivers/watchdog/cpu5wdt.c | 12 ++++----- drivers/watchdog/davinci_wdt.c | 8 +++--- drivers/watchdog/ep93xx_wdt.c | 10 ++++---- drivers/watchdog/eurotechwdt.c | 36 +++++++++++++------------- drivers/watchdog/geodewdt.c | 30 ++++++++++------------ drivers/watchdog/i6300esb.c | 8 +++--- drivers/watchdog/iTCO_wdt.c | 8 +++--- drivers/watchdog/ib700wdt.c | 30 +++++++++++----------- drivers/watchdog/ibmasr.c | 20 +++++++-------- drivers/watchdog/indydog.c | 10 ++++---- drivers/watchdog/iop_wdt.c | 18 ++++++------- drivers/watchdog/it8712f_wdt.c | 4 +-- drivers/watchdog/ixp2000_wdt.c | 10 ++++---- drivers/watchdog/ixp4xx_wdt.c | 10 ++++---- drivers/watchdog/ks8695_wdt.c | 28 ++++++++++---------- drivers/watchdog/mixcomwd.c | 8 +++--- drivers/watchdog/mpcore_wdt.c | 12 ++++----- drivers/watchdog/mtx-1_wdt.c | 12 ++++----- drivers/watchdog/omap_wdt.c | 4 +-- drivers/watchdog/pc87413_wdt.c | 30 +++++++++++----------- drivers/watchdog/pcwd.c | 6 ++--- drivers/watchdog/pcwd_pci.c | 8 +++--- drivers/watchdog/pcwd_usb.c | 8 +++--- drivers/watchdog/pnx4008_wdt.c | 10 ++++---- drivers/watchdog/s3c2410_wdt.c | 4 +-- drivers/watchdog/sa1100_wdt.c | 10 ++++---- drivers/watchdog/sb_wdog.c | 10 ++++---- drivers/watchdog/sbc60xxwdt.c | 10 ++++---- drivers/watchdog/sbc7240_wdt.c | 54 ++++++++++++++++++++------------------- drivers/watchdog/sbc_epx_c3.c | 10 ++++---- drivers/watchdog/sc1200wdt.c | 36 +++++++++++++------------- drivers/watchdog/sc520_wdt.c | 10 ++++---- drivers/watchdog/scx200_wdt.c | 4 +-- drivers/watchdog/shwdt.c | 28 ++++++++++---------- drivers/watchdog/smsc37b787_wdt.c | 34 ++++++++++++------------ drivers/watchdog/softdog.c | 4 +-- drivers/watchdog/txx9wdt.c | 4 +-- drivers/watchdog/w83627hf_wdt.c | 24 ++++++++--------- drivers/watchdog/w83697hf_wdt.c | 30 +++++++++++----------- drivers/watchdog/w83877f_wdt.c | 10 ++++---- drivers/watchdog/w83977f_wdt.c | 14 +++++----- drivers/watchdog/wafer5823wdt.c | 32 +++++++++++------------ drivers/watchdog/wdt.c | 4 +-- drivers/watchdog/wdt977.c | 14 +++++----- drivers/watchdog/wdt_pci.c | 6 ++--- 54 files changed, 428 insertions(+), 428 deletions(-) diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 340d1eeec16b..7a5c69421f12 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -164,13 +164,6 @@ static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - acq_keepalive(); - return 0; - - case WDIOC_GETTIMEOUT: - return put_user(WATCHDOG_HEARTBEAT, p); - case WDIOC_SETOPTIONS: { if (get_user(options, p)) @@ -185,6 +178,13 @@ static long acq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + acq_keepalive(); + return 0; + + case WDIOC_GETTIMEOUT: + return put_user(WATCHDOG_HEARTBEAT, p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index e6bf8d2d3d30..bfec16600475 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -152,19 +152,6 @@ static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - advwdt_ping(); - break; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if (advwdt_set_heartbeat(new_timeout)) - return -EINVAL; - advwdt_ping(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -181,6 +168,19 @@ static long advwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + advwdt_ping(); + break; + + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + if (advwdt_set_heartbeat(new_timeout)) + return -EINVAL; + advwdt_ping(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index 80e323ddc4ba..dfa11d19043a 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c @@ -195,9 +195,6 @@ static long ali_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - ali_keepalive(); - return 0; case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -214,6 +211,9 @@ static long ali_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + ali_keepalive(); + return 0; case WDIOC_SETTIMEOUT: { int new_timeout; diff --git a/drivers/watchdog/alim7101_wdt.c b/drivers/watchdog/alim7101_wdt.c index 726e75d9db7a..049c9122e40d 100644 --- a/drivers/watchdog/alim7101_wdt.c +++ b/drivers/watchdog/alim7101_wdt.c @@ -251,9 +251,6 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -270,6 +267,9 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; case WDIOC_SETTIMEOUT: { int new_timeout; diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index ef7b0d67095e..9a81a205ef74 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -251,8 +251,6 @@ static long ar7_wdt_ioctl(struct file *file, int new_margin; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: if (copy_to_user((struct watchdog_info *)arg, &ident, sizeof(ident))) @@ -281,6 +279,8 @@ static long ar7_wdt_ioctl(struct file *file, if (put_user(margin, (int *)arg)) return -EFAULT; return 0; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c index c5dc5e912fb2..4538b57f451a 100644 --- a/drivers/watchdog/at32ap700x_wdt.c +++ b/drivers/watchdog/at32ap700x_wdt.c @@ -221,27 +221,10 @@ static long at32_wdt_ioctl(struct file *file, int __user *p = argp; switch (cmd) { - case WDIOC_KEEPALIVE: - at32_wdt_pat(); - ret = 0; - break; case WDIOC_GETSUPPORT: ret = copy_to_user(argp, &at32_wdt_info, sizeof(at32_wdt_info)) ? -EFAULT : 0; break; - case WDIOC_SETTIMEOUT: - ret = get_user(time, p); - if (ret) - break; - ret = at32_wdt_settimeout(time); - if (ret) - break; - /* Enable new time value */ - at32_wdt_start(); - /* fall through */ - case WDIOC_GETTIMEOUT: - ret = put_user(wdt->timeout, p); - break; case WDIOC_GETSTATUS: ret = put_user(0, p); break; @@ -258,6 +241,23 @@ static long at32_wdt_ioctl(struct file *file, at32_wdt_start(); ret = 0; break; + case WDIOC_KEEPALIVE: + at32_wdt_pat(); + ret = 0; + break; + case WDIOC_SETTIMEOUT: + ret = get_user(time, p); + if (ret) + break; + ret = at32_wdt_settimeout(time); + if (ret) + break; + /* Enable new time value */ + at32_wdt_start(); + /* fall through */ + case WDIOC_GETTIMEOUT: + ret = put_user(wdt->timeout, p); + break; } return ret; diff --git a/drivers/watchdog/at91rm9200_wdt.c b/drivers/watchdog/at91rm9200_wdt.c index bb79f649dc7e..2313f44144f8 100644 --- a/drivers/watchdog/at91rm9200_wdt.c +++ b/drivers/watchdog/at91rm9200_wdt.c @@ -137,23 +137,9 @@ static long at91_wdt_ioct(struct file *file, int new_value; switch (cmd) { - case WDIOC_KEEPALIVE: - at91_wdt_reload(); /* pat the watchdog */ - return 0; case WDIOC_GETSUPPORT: return copy_to_user(argp, &at91_wdt_info, sizeof(at91_wdt_info)) ? -EFAULT : 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - if (at91_wdt_settimeout(new_value)) - return -EINVAL; - /* Enable new time value */ - at91_wdt_start(); - /* Return current value */ - return put_user(wdt_time, p); - case WDIOC_GETTIMEOUT: - return put_user(wdt_time, p); case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); @@ -165,6 +151,20 @@ static long at91_wdt_ioct(struct file *file, if (new_value & WDIOS_ENABLECARD) at91_wdt_start(); return 0; + case WDIOC_KEEPALIVE: + at91_wdt_reload(); /* pat the watchdog */ + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_value, p)) + return -EFAULT; + if (at91_wdt_settimeout(new_value)) + return -EINVAL; + /* Enable new time value */ + at91_wdt_start(); + /* Return current value */ + return put_user(wdt_time, p); + case WDIOC_GETTIMEOUT: + return put_user(wdt_time, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/bfin_wdt.c b/drivers/watchdog/bfin_wdt.c index 8f6e871b3fe3..31b42253054e 100644 --- a/drivers/watchdog/bfin_wdt.c +++ b/drivers/watchdog/bfin_wdt.c @@ -265,20 +265,6 @@ static long bfin_wdt_ioctl(struct file *file, case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(!!(_bfin_swrst & SWRST_RESET_WDOG), p); - case WDIOC_KEEPALIVE: - bfin_wdt_keepalive(); - return 0; - case WDIOC_SETTIMEOUT: { - int new_timeout; - - if (get_user(new_timeout, p)) - return -EFAULT; - if (bfin_wdt_set_timeout(new_timeout)) - return -EINVAL; - } - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); case WDIOC_SETOPTIONS: { unsigned long flags; int options, ret = -EINVAL; @@ -298,6 +284,20 @@ static long bfin_wdt_ioctl(struct file *file, spin_unlock_irqrestore(&bfin_wdt_spinlock, flags); return ret; } + case WDIOC_KEEPALIVE: + bfin_wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: { + int new_timeout; + + if (get_user(new_timeout, p)) + return -EFAULT; + if (bfin_wdt_set_timeout(new_timeout)) + return -EINVAL; + } + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/booke_wdt.c b/drivers/watchdog/booke_wdt.c index 06b7a17a60e7..c3b78a76f173 100644 --- a/drivers/watchdog/booke_wdt.c +++ b/drivers/watchdog/booke_wdt.c @@ -99,6 +99,15 @@ static long booke_wdt_ioctl(struct file *file, tmp = mfspr(SPRN_TSR) & TSR_WRS(3); /* returns 1 if last reset was caused by the WDT */ return (tmp ? 1 : 0); + case WDIOC_SETOPTIONS: + if (get_user(tmp, p)) + return -EINVAL; + if (tmp == WDIOS_ENABLECARD) { + booke_wdt_ping(); + break; + } else + return -EINVAL; + return 0; case WDIOC_KEEPALIVE: booke_wdt_ping(); return 0; @@ -110,15 +119,6 @@ static long booke_wdt_ioctl(struct file *file, return 0; case WDIOC_GETTIMEOUT: return put_user(booke_wdt_period, p); - case WDIOC_SETOPTIONS: - if (get_user(tmp, p)) - return -EINVAL; - if (tmp == WDIOS_ENABLECARD) { - booke_wdt_ping(); - break; - } else - return -EINVAL; - return 0; default: return -ENOTTY; } diff --git a/drivers/watchdog/cpu5wdt.c b/drivers/watchdog/cpu5wdt.c index ec324e5e1c99..71f6d7eec9a8 100644 --- a/drivers/watchdog/cpu5wdt.c +++ b/drivers/watchdog/cpu5wdt.c @@ -160,8 +160,9 @@ static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - case WDIOC_KEEPALIVE: - cpu5wdt_reset(); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; break; case WDIOC_GETSTATUS: value = inb(port + CPU5WDT_STATUS_REG); @@ -169,10 +170,6 @@ static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, return put_user(value, p); case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; case WDIOC_SETOPTIONS: if (get_user(value, p)) return -EFAULT; @@ -181,6 +178,9 @@ static long cpu5wdt_ioctl(struct file *file, unsigned int cmd, if (value & WDIOS_DISABLECARD) cpu5wdt_stop(); break; + case WDIOC_KEEPALIVE: + cpu5wdt_reset(); + break; default: return -ENOTTY; } diff --git a/drivers/watchdog/davinci_wdt.c b/drivers/watchdog/davinci_wdt.c index 926b59c41186..802aeba347a0 100644 --- a/drivers/watchdog/davinci_wdt.c +++ b/drivers/watchdog/davinci_wdt.c @@ -159,14 +159,14 @@ static long davinci_wdt_ioctl(struct file *file, ret = put_user(0, (int *)arg); break; - case WDIOC_GETTIMEOUT: - ret = put_user(heartbeat, (int *)arg); - break; - case WDIOC_KEEPALIVE: wdt_service(); ret = 0; break; + + case WDIOC_GETTIMEOUT: + ret = put_user(heartbeat, (int *)arg); + break; } return ret; } diff --git a/drivers/watchdog/ep93xx_wdt.c b/drivers/watchdog/ep93xx_wdt.c index cdcdd11173a7..07b74a768922 100644 --- a/drivers/watchdog/ep93xx_wdt.c +++ b/drivers/watchdog/ep93xx_wdt.c @@ -155,15 +155,15 @@ static long ep93xx_wdt_ioctl(struct file *file, ret = put_user(boot_status, (int __user *)arg); break; - case WDIOC_GETTIMEOUT: - /* actually, it is 0.250 seconds.... */ - ret = put_user(1, (int __user *)arg); - break; - case WDIOC_KEEPALIVE: wdt_keepalive(); ret = 0; break; + + case WDIOC_GETTIMEOUT: + /* actually, it is 0.250 seconds.... */ + ret = put_user(1, (int __user *)arg); + break; } return ret; } diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index b94e6ef4c7a7..96250118fd7c 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c @@ -249,9 +249,6 @@ static long eurwdt_ioctl(struct file *file, int options, retval = -EINVAL; switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; @@ -259,6 +256,22 @@ static long eurwdt_ioctl(struct file *file, case WDIOC_GETBOOTSTATUS: return put_user(0, p); + case WDIOC_SETOPTIONS: + if (get_user(options, p)) + return -EFAULT; + spin_lock(&eurwdt_lock); + if (options & WDIOS_DISABLECARD) { + eurwdt_disable_timer(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + eurwdt_activate_timer(); + eurwdt_ping(); + retval = 0; + } + spin_unlock(&eurwdt_lock); + return retval; + case WDIOC_KEEPALIVE: spin_lock(&eurwdt_lock); eurwdt_ping(); @@ -282,21 +295,8 @@ static long eurwdt_ioctl(struct file *file, case WDIOC_GETTIMEOUT: return put_user(eurwdt_timeout, p); - case WDIOC_SETOPTIONS: - if (get_user(options, p)) - return -EFAULT; - spin_lock(&eurwdt_lock); - if (options & WDIOS_DISABLECARD) { - eurwdt_disable_timer(); - retval = 0; - } - if (options & WDIOS_ENABLECARD) { - eurwdt_activate_timer(); - eurwdt_ping(); - retval = 0; - } - spin_unlock(&eurwdt_lock); - return retval; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index 74c00698801d..04b861cfdf0c 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c @@ -159,22 +159,6 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - geodewdt_ping(); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(interval, p)) - return -EFAULT; - - if (geodewdt_set_heartbeat(interval)) - return -EINVAL; - -/* Fall through */ - - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - case WDIOC_SETOPTIONS: { int options, ret = -EINVAL; @@ -194,6 +178,20 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, return ret; } + case WDIOC_KEEPALIVE: + geodewdt_ping(); + return 0; + + case WDIOC_SETTIMEOUT: + if (get_user(interval, p)) + return -EFAULT; + + if (geodewdt_set_heartbeat(interval)) + return -EINVAL; + /* Fall through */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index 01a283f7a271..c768cb718904 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -280,10 +280,6 @@ static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(triggered, p); - case WDIOC_KEEPALIVE: - esb_timer_keepalive(); - return 0; - case WDIOC_SETOPTIONS: { if (get_user(new_options, p)) @@ -301,6 +297,10 @@ static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + esb_timer_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: { if (get_user(new_heartbeat, p)) diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index c9ca8f691d81..b18766436638 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -532,10 +532,6 @@ static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - iTCO_wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: { if (get_user(new_options, p)) @@ -552,6 +548,10 @@ static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd, } return retval; } + case WDIOC_KEEPALIVE: + iTCO_wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: { if (get_user(new_heartbeat, p)) diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 9eb9537c370e..6aa914e5caf5 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -213,21 +213,6 @@ static long ibwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - ibwdt_ping(); - break; - - case WDIOC_SETTIMEOUT: - if (get_user(new_margin, p)) - return -EFAULT; - if (ibwdt_set_heartbeat(new_margin)) - return -EINVAL; - ibwdt_ping(); - /* Fall */ - - case WDIOC_GETTIMEOUT: - return put_user(wd_times[wd_margin], p); - case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -245,6 +230,21 @@ static long ibwdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + ibwdt_ping(); + break; + + case WDIOC_SETTIMEOUT: + if (get_user(new_margin, p)) + return -EFAULT; + if (ibwdt_set_heartbeat(new_margin)) + return -EINVAL; + ibwdt_ping(); + /* Fall */ + + case WDIOC_GETTIMEOUT: + return put_user(wd_times[wd_margin], p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/ibmasr.c b/drivers/watchdog/ibmasr.c index 6824bf80b37e..0b549f3ff915 100644 --- a/drivers/watchdog/ibmasr.c +++ b/drivers/watchdog/ibmasr.c @@ -287,16 +287,6 @@ static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - asr_toggle(); - return 0; - /* - * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT - * and WDIOC_GETTIMEOUT always returns 256. - */ - case WDIOC_GETTIMEOUT: - heartbeat = 256; - return put_user(heartbeat, p); case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -313,6 +303,16 @@ static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + asr_toggle(); + return 0; + /* + * The hardware has a fixed timeout value, so no WDIOC_SETTIMEOUT + * and WDIOC_GETTIMEOUT always returns 256. + */ + case WDIOC_GETTIMEOUT: + heartbeat = 256; + return put_user(heartbeat, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/indydog.c b/drivers/watchdog/indydog.c index 0bffea37404e..73c9e7992feb 100644 --- a/drivers/watchdog/indydog.c +++ b/drivers/watchdog/indydog.c @@ -128,11 +128,6 @@ static long indydog_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, (int *)arg); - case WDIOC_KEEPALIVE: - indydog_ping(); - return 0; - case WDIOC_GETTIMEOUT: - return put_user(WATCHDOG_TIMEOUT, (int *)arg); case WDIOC_SETOPTIONS: { if (get_user(options, (int *)arg)) @@ -147,6 +142,11 @@ static long indydog_ioctl(struct file *file, unsigned int cmd, } return retval; } + case WDIOC_KEEPALIVE: + indydog_ping(); + return 0; + case WDIOC_GETTIMEOUT: + return put_user(WATCHDOG_TIMEOUT, (int *)arg); default: return -ENOTTY; } diff --git a/drivers/watchdog/iop_wdt.c b/drivers/watchdog/iop_wdt.c index e54c888d2afe..e0d0a90ea10c 100644 --- a/drivers/watchdog/iop_wdt.c +++ b/drivers/watchdog/iop_wdt.c @@ -153,15 +153,6 @@ static long iop_wdt_ioctl(struct file *file, ret = put_user(boot_status, argp); break; - case WDIOC_GETTIMEOUT: - ret = put_user(iop_watchdog_timeout(), argp); - break; - - case WDIOC_KEEPALIVE: - wdt_enable(); - ret = 0; - break; - case WDIOC_SETOPTIONS: if (get_user(options, (int *)arg)) return -EFAULT; @@ -181,6 +172,15 @@ static long iop_wdt_ioctl(struct file *file, ret = 0; } break; + + case WDIOC_KEEPALIVE: + wdt_enable(); + ret = 0; + break; + + case WDIOC_GETTIMEOUT: + ret = put_user(iop_watchdog_timeout(), argp); + break; } return ret; } diff --git a/drivers/watchdog/it8712f_wdt.c b/drivers/watchdog/it8712f_wdt.c index 51bfd5721833..c1db74f6e310 100644 --- a/drivers/watchdog/it8712f_wdt.c +++ b/drivers/watchdog/it8712f_wdt.c @@ -244,8 +244,6 @@ static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, int value; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; @@ -284,6 +282,8 @@ static long it8712f_wdt_ioctl(struct file *file, unsigned int cmd, if (put_user(margin, p)) return -EFAULT; return 0; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/ixp2000_wdt.c b/drivers/watchdog/ixp2000_wdt.c index 943ceffbd683..a77f69d52877 100644 --- a/drivers/watchdog/ixp2000_wdt.c +++ b/drivers/watchdog/ixp2000_wdt.c @@ -126,6 +126,11 @@ static long ixp2000_wdt_ioctl(struct file *file, unsigned int cmd, ret = put_user(0, (int *)arg); break; + case WDIOC_KEEPALIVE: + wdt_enable(); + ret = 0; + break; + case WDIOC_SETTIMEOUT: ret = get_user(time, (int *)arg); if (ret) @@ -143,11 +148,6 @@ static long ixp2000_wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETTIMEOUT: ret = put_user(heartbeat, (int *)arg); break; - - case WDIOC_KEEPALIVE: - wdt_enable(); - ret = 0; - break; } return ret; diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index 1bafd7b58ca5..b94713e4773d 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c @@ -117,6 +117,11 @@ static long ixp4xx_wdt_ioctl(struct file *file, unsigned int cmd, ret = put_user(boot_status, (int *)arg); break; + case WDIOC_KEEPALIVE: + wdt_enable(); + ret = 0; + break; + case WDIOC_SETTIMEOUT: ret = get_user(time, (int *)arg); if (ret) @@ -134,11 +139,6 @@ static long ixp4xx_wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETTIMEOUT: ret = put_user(heartbeat, (int *)arg); break; - - case WDIOC_KEEPALIVE: - wdt_enable(); - ret = 0; - break; } return ret; } diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c index 6d052b80aa20..f8566d5c62fe 100644 --- a/drivers/watchdog/ks8695_wdt.c +++ b/drivers/watchdog/ks8695_wdt.c @@ -161,23 +161,9 @@ static long ks8695_wdt_ioctl(struct file *file, unsigned int cmd, int new_value; switch (cmd) { - case WDIOC_KEEPALIVE: - ks8695_wdt_reload(); /* pat the watchdog */ - return 0; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ks8695_wdt_info, sizeof(ks8695_wdt_info)) ? -EFAULT : 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_value, p)) - return -EFAULT; - if (ks8695_wdt_settimeout(new_value)) - return -EINVAL; - /* Enable new time value */ - ks8695_wdt_start(); - /* Return current value */ - return put_user(wdt_time, p); - case WDIOC_GETTIMEOUT: - return put_user(wdt_time, p); case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); @@ -189,6 +175,20 @@ static long ks8695_wdt_ioctl(struct file *file, unsigned int cmd, if (new_value & WDIOS_ENABLECARD) ks8695_wdt_start(); return 0; + case WDIOC_KEEPALIVE: + ks8695_wdt_reload(); /* pat the watchdog */ + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_value, p)) + return -EFAULT; + if (ks8695_wdt_settimeout(new_value)) + return -EINVAL; + /* Enable new time value */ + ks8695_wdt_start(); + /* Return current value */ + return put_user(wdt_time, p); + case WDIOC_GETTIMEOUT: + return put_user(wdt_time, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/mixcomwd.c b/drivers/watchdog/mixcomwd.c index 2248a8187590..407b025cb104 100644 --- a/drivers/watchdog/mixcomwd.c +++ b/drivers/watchdog/mixcomwd.c @@ -208,6 +208,10 @@ static long mixcomwd_ioctl(struct file *file, }; switch (cmd) { + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; + break; case WDIOC_GETSTATUS: status = mixcomwd_opened; if (!nowayout) @@ -215,10 +219,6 @@ static long mixcomwd_ioctl(struct file *file, return put_user(status, p); case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; case WDIOC_KEEPALIVE: mixcomwd_ping(); break; diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 5e58f8b73d00..3c4f95599c65 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -243,6 +243,12 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, ret = 0; break; + case WDIOC_GETSTATUS: + case WDIOC_GETBOOTSTATUS: + uarg.i = 0; + ret = 0; + break; + case WDIOC_SETOPTIONS: ret = -EINVAL; if (uarg.i & WDIOS_DISABLECARD) { @@ -255,12 +261,6 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd, } break; - case WDIOC_GETSTATUS: - case WDIOC_GETBOOTSTATUS: - uarg.i = 0; - ret = 0; - break; - case WDIOC_KEEPALIVE: mpcore_wdt_keepalive(wdt); ret = 0; diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index e0b8cdfa5e70..f820b82da7c3 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c @@ -148,17 +148,14 @@ static long mtx1_wdt_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - case WDIOC_KEEPALIVE: - mtx1_wdt_reset(); + case WDIOC_GETSUPPORT: + if (copy_to_user(argp, &ident, sizeof(ident))) + return -EFAULT; break; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: put_user(0, p); break; - case WDIOC_GETSUPPORT: - if (copy_to_user(argp, &ident, sizeof(ident))) - return -EFAULT; - break; case WDIOC_SETOPTIONS: if (get_user(value, p)) return -EFAULT; @@ -169,6 +166,9 @@ static long mtx1_wdt_ioctl(struct file *file, unsigned int cmd, else return -EINVAL; return 0; + case WDIOC_KEEPALIVE: + mtx1_wdt_reset(); + break; default: return -ENOTTY; } diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 5aae071cc045..7beb21ce1de9 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -197,8 +197,6 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user((struct watchdog_info __user *)arg, &ident, sizeof(ident)); @@ -231,6 +229,8 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd, /* Fall */ case WDIOC_GETTIMEOUT: return put_user(timer_margin, (int __user *)arg); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/pc87413_wdt.c b/drivers/watchdog/pc87413_wdt.c index 326f2d2ded3b..5fc7f1349950 100644 --- a/drivers/watchdog/pc87413_wdt.c +++ b/drivers/watchdog/pc87413_wdt.c @@ -426,6 +426,21 @@ static long pc87413_ioctl(struct file *file, unsigned int cmd, return put_user(pc87413_status(), uarg.i); case WDIOC_GETBOOTSTATUS: return put_user(0, uarg.i); + case WDIOC_SETOPTIONS: + { + int options, retval = -EINVAL; + if (get_user(options, uarg.i)) + return -EFAULT; + if (options & WDIOS_DISABLECARD) { + pc87413_disable(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + pc87413_enable(); + retval = 0; + } + return retval; + } case WDIOC_KEEPALIVE: pc87413_refresh(); #ifdef DEBUG @@ -445,21 +460,6 @@ static long pc87413_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETTIMEOUT: new_timeout = timeout * 60; return put_user(new_timeout, uarg.i); - case WDIOC_SETOPTIONS: - { - int options, retval = -EINVAL; - if (get_user(options, uarg.i)) - return -EFAULT; - if (options & WDIOS_DISABLECARD) { - pc87413_disable(); - retval = 0; - } - if (options & WDIOS_ENABLECARD) { - pc87413_enable(); - retval = 0; - } - return retval; - } default: return -ENOTTY; } diff --git a/drivers/watchdog/pcwd.c b/drivers/watchdog/pcwd.c index e1259adf09f9..134386a88852 100644 --- a/drivers/watchdog/pcwd.c +++ b/drivers/watchdog/pcwd.c @@ -612,9 +612,6 @@ static long pcwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) }; switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; @@ -669,6 +666,9 @@ static long pcwd_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETTIMEOUT: return put_user(heartbeat, argp); + + default: + return -ENOTTY; } return 0; diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 7f500ee4ee8a..2617129a7ccc 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -494,10 +494,6 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, return put_user(temperature, p); } - case WDIOC_KEEPALIVE: - pcipcwd_keepalive(); - return 0; - case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -525,6 +521,10 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, return retval; } + case WDIOC_KEEPALIVE: + pcipcwd_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: { int new_heartbeat; diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 8194435052c8..8c582bc0588e 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -400,10 +400,6 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, return put_user(temperature, p); } - case WDIOC_KEEPALIVE: - usb_pcwd_keepalive(usb_pcwd_device); - return 0; - case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -424,6 +420,10 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, return retval; } + case WDIOC_KEEPALIVE: + usb_pcwd_keepalive(usb_pcwd_device); + return 0; + case WDIOC_SETTIMEOUT: { int new_heartbeat; diff --git a/drivers/watchdog/pnx4008_wdt.c b/drivers/watchdog/pnx4008_wdt.c index 56dee3bfd4aa..6eadf5ebb9b3 100644 --- a/drivers/watchdog/pnx4008_wdt.c +++ b/drivers/watchdog/pnx4008_wdt.c @@ -194,6 +194,11 @@ static long pnx4008_wdt_ioctl(struct inode *inode, struct file *file, ret = put_user(boot_status, (int *)arg); break; + case WDIOC_KEEPALIVE: + wdt_enable(); + ret = 0; + break; + case WDIOC_SETTIMEOUT: ret = get_user(time, (int *)arg); if (ret) @@ -211,11 +216,6 @@ static long pnx4008_wdt_ioctl(struct inode *inode, struct file *file, case WDIOC_GETTIMEOUT: ret = put_user(heartbeat, (int *)arg); break; - - case WDIOC_KEEPALIVE: - wdt_enable(); - ret = 0; - break; } return ret; } diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 97b4a2e8eb09..44bf5e4282e1 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -305,8 +305,6 @@ static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, int new_margin; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &s3c2410_wdt_ident, sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; @@ -325,6 +323,8 @@ static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, return put_user(tmr_margin, p); case WDIOC_GETTIMEOUT: return put_user(tmr_margin, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/sa1100_wdt.c b/drivers/watchdog/sa1100_wdt.c index 869d538c02f9..27d6898a7c98 100644 --- a/drivers/watchdog/sa1100_wdt.c +++ b/drivers/watchdog/sa1100_wdt.c @@ -107,6 +107,11 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd, ret = put_user(boot_status, p); break; + case WDIOC_KEEPALIVE: + OSMR3 = OSCR + pre_margin; + ret = 0; + break; + case WDIOC_SETTIMEOUT: ret = get_user(time, p); if (ret) @@ -124,11 +129,6 @@ static long sa1100dog_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETTIMEOUT: ret = put_user(pre_margin / OSCR_FREQ, p); break; - - case WDIOC_KEEPALIVE: - OSMR3 = OSCR + pre_margin; - ret = 0; - break; } return ret; } diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index c8b544ce77fb..528097651f7f 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -182,6 +182,11 @@ static long sbwdog_ioctl(struct file *file, unsigned int cmd, ret = put_user(0, p); break; + case WDIOC_KEEPALIVE: + sbwdog_pet(user_dog); + ret = 0; + break; + case WDIOC_SETTIMEOUT: ret = get_user(time, p); if (ret) @@ -203,11 +208,6 @@ static long sbwdog_ioctl(struct file *file, unsigned int cmd, */ ret = put_user(__raw_readq(user_dog - 8) / 1000000, p); break; - - case WDIOC_KEEPALIVE: - sbwdog_pet(user_dog); - ret = 0; - break; } return ret; } diff --git a/drivers/watchdog/sbc60xxwdt.c b/drivers/watchdog/sbc60xxwdt.c index e284a5d4fb1b..e801cd46c647 100644 --- a/drivers/watchdog/sbc60xxwdt.c +++ b/drivers/watchdog/sbc60xxwdt.c @@ -237,16 +237,11 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident))? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -262,6 +257,9 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; case WDIOC_SETTIMEOUT: { int new_timeout; @@ -277,6 +275,8 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } case WDIOC_GETTIMEOUT: return put_user(timeout, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/sbc7240_wdt.c b/drivers/watchdog/sbc7240_wdt.c index abccbe265249..67ddeb1c830a 100644 --- a/drivers/watchdog/sbc7240_wdt.c +++ b/drivers/watchdog/sbc7240_wdt.c @@ -177,39 +177,41 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, (int __user *)arg); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS:{ - int options; - int retval = -EINVAL; + case WDIOC_SETOPTIONS: + { + int options; + int retval = -EINVAL; - if (get_user(options, (int __user *)arg)) - return -EFAULT; + if (get_user(options, (int __user *)arg)) + return -EFAULT; - if (options & WDIOS_DISABLECARD) { - wdt_disable(); - retval = 0; - } - - if (options & WDIOS_ENABLECARD) { - wdt_enable(); - retval = 0; - } + if (options & WDIOS_DISABLECARD) { + wdt_disable(); + retval = 0; + } - return retval; + if (options & WDIOS_ENABLECARD) { + wdt_enable(); + retval = 0; } - case WDIOC_SETTIMEOUT:{ - int new_timeout; - if (get_user(new_timeout, (int __user *)arg)) - return -EFAULT; + return retval; + } + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: + { + int new_timeout; - if (wdt_set_timeout(new_timeout)) - return -EINVAL; + if (get_user(new_timeout, (int __user *)arg)) + return -EFAULT; - /* Fall through */ - } + if (wdt_set_timeout(new_timeout)) + return -EINVAL; + + /* Fall through */ + } case WDIOC_GETTIMEOUT: return put_user(timeout, (int __user *)arg); default: diff --git a/drivers/watchdog/sbc_epx_c3.c b/drivers/watchdog/sbc_epx_c3.c index 70ff9cbc8e9b..e5e470ca7759 100644 --- a/drivers/watchdog/sbc_epx_c3.c +++ b/drivers/watchdog/sbc_epx_c3.c @@ -120,11 +120,6 @@ static long epx_c3_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, argp); - case WDIOC_KEEPALIVE: - epx_c3_pet(); - return 0; - case WDIOC_GETTIMEOUT: - return put_user(WATCHDOG_TIMEOUT, argp); case WDIOC_SETOPTIONS: if (get_user(options, argp)) return -EFAULT; @@ -140,6 +135,11 @@ static long epx_c3_ioctl(struct file *file, unsigned int cmd, } return retval; + case WDIOC_KEEPALIVE: + epx_c3_pet(); + return 0; + case WDIOC_GETTIMEOUT: + return put_user(WATCHDOG_TIMEOUT, argp); default: return -ENOTTY; } diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index 03e67fa4d689..f3bdc8227cc4 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c @@ -207,24 +207,6 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - sc1200wdt_write_data(WDTO, timeout); - return 0; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - /* the API states this is given in secs */ - new_timeout /= 60; - if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) - return -EINVAL; - timeout = new_timeout; - sc1200wdt_write_data(WDTO, timeout); - /* fall through and return the new timeout */ - - case WDIOC_GETTIMEOUT: - return put_user(timeout * 60, p); - case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -244,6 +226,24 @@ static long sc1200wdt_ioctl(struct file *file, unsigned int cmd, return retval; } + case WDIOC_KEEPALIVE: + sc1200wdt_write_data(WDTO, timeout); + return 0; + + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + /* the API states this is given in secs */ + new_timeout /= 60; + if (new_timeout < 0 || new_timeout > MAX_TIMEOUT) + return -EINVAL; + timeout = new_timeout; + sc1200wdt_write_data(WDTO, timeout); + /* fall through and return the new timeout */ + + case WDIOC_GETTIMEOUT: + return put_user(timeout * 60, p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/sc520_wdt.c b/drivers/watchdog/sc520_wdt.c index 1d5ba15dec63..a2b6c1067ec5 100644 --- a/drivers/watchdog/sc520_wdt.c +++ b/drivers/watchdog/sc520_wdt.c @@ -291,16 +291,11 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -320,6 +315,9 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return retval; } + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; case WDIOC_SETTIMEOUT: { int new_timeout; @@ -335,6 +333,8 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } case WDIOC_GETTIMEOUT: return put_user(timeout, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/scx200_wdt.c b/drivers/watchdog/scx200_wdt.c index 7c1de94704f3..fd5c09446bce 100644 --- a/drivers/watchdog/scx200_wdt.c +++ b/drivers/watchdog/scx200_wdt.c @@ -168,8 +168,6 @@ static long scx200_wdt_ioctl(struct file *file, unsigned int cmd, int new_margin; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: if (copy_to_user(argp, &ident, sizeof(ident))) return -EFAULT; @@ -194,6 +192,8 @@ static long scx200_wdt_ioctl(struct file *file, unsigned int cmd, if (put_user(margin, p)) return -EFAULT; return 0; + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/shwdt.c b/drivers/watchdog/shwdt.c index 60f0036aaca6..824125adf90a 100644 --- a/drivers/watchdog/shwdt.c +++ b/drivers/watchdog/shwdt.c @@ -351,20 +351,6 @@ static long sh_wdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, (int *)arg); - case WDIOC_KEEPALIVE: - sh_wdt_keepalive(); - return 0; - case WDIOC_SETTIMEOUT: - if (get_user(new_heartbeat, (int *)arg)) - return -EFAULT; - - if (sh_wdt_set_heartbeat(new_heartbeat)) - return -EINVAL; - - sh_wdt_keepalive(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(heartbeat, (int *)arg); case WDIOC_SETOPTIONS: if (get_user(options, (int *)arg)) return -EFAULT; @@ -380,6 +366,20 @@ static long sh_wdt_ioctl(struct file *file, unsigned int cmd, } return retval; + case WDIOC_KEEPALIVE: + sh_wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: + if (get_user(new_heartbeat, (int *)arg)) + return -EFAULT; + + if (sh_wdt_set_heartbeat(new_heartbeat)) + return -EINVAL; + + sh_wdt_keepalive(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(heartbeat, (int *)arg); default: return -ENOTTY; } diff --git a/drivers/watchdog/smsc37b787_wdt.c b/drivers/watchdog/smsc37b787_wdt.c index b7c6394b7d70..239383da6d87 100644 --- a/drivers/watchdog/smsc37b787_wdt.c +++ b/drivers/watchdog/smsc37b787_wdt.c @@ -451,6 +451,23 @@ static long wb_smsc_wdt_ioctl(struct file *file, return put_user(wb_smsc_wdt_status(), uarg.i); case WDIOC_GETBOOTSTATUS: return put_user(0, uarg.i); + case WDIOC_SETOPTIONS: + { + int options, retval = -EINVAL; + + if (get_user(options, uarg.i)) + return -EFAULT; + + if (options & WDIOS_DISABLECARD) { + wb_smsc_wdt_disable(); + retval = 0; + } + if (options & WDIOS_ENABLECARD) { + wb_smsc_wdt_enable(); + retval = 0; + } + return retval; + } case WDIOC_KEEPALIVE: wb_smsc_wdt_reset_timer(); return 0; @@ -470,23 +487,6 @@ static long wb_smsc_wdt_ioctl(struct file *file, if (unit == UNIT_MINUTE) new_timeout *= 60; return put_user(new_timeout, uarg.i); - case WDIOC_SETOPTIONS: - { - int options, retval = -EINVAL; - - if (get_user(options, uarg.i)) - return -EFAULT; - - if (options & WDIOS_DISABLECARD) { - wb_smsc_wdt_disable(); - retval = 0; - } - if (options & WDIOS_ENABLECARD) { - wb_smsc_wdt_enable(); - retval = 0; - } - return retval; - } default: return -ENOTTY; } diff --git a/drivers/watchdog/softdog.c b/drivers/watchdog/softdog.c index bb3c75eed9df..c650464c5c63 100644 --- a/drivers/watchdog/softdog.c +++ b/drivers/watchdog/softdog.c @@ -206,8 +206,6 @@ static long softdog_ioctl(struct file *file, unsigned int cmd, .identity = "Software Watchdog", }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: @@ -225,6 +223,8 @@ static long softdog_ioctl(struct file *file, unsigned int cmd, /* Fall */ case WDIOC_GETTIMEOUT: return put_user(soft_margin, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index b729cc447df3..8382f9a9534b 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c @@ -142,8 +142,6 @@ static long txx9wdt_ioctl(struct file *file, unsigned int cmd, }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: @@ -163,6 +161,8 @@ static long txx9wdt_ioctl(struct file *file, unsigned int cmd, /* Fall */ case WDIOC_GETTIMEOUT: return put_user(timeout, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index 70c843f4201a..59507f609996 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -211,18 +211,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_ping(); - break; - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if (wdt_set_heartbeat(new_timeout)) - return -EINVAL; - wdt_ping(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -239,6 +227,18 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } return retval; } + case WDIOC_KEEPALIVE: + wdt_ping(); + break; + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + if (wdt_set_heartbeat(new_timeout)) + return -EINVAL; + wdt_ping(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); default: return -ENOTTY; } diff --git a/drivers/watchdog/w83697hf_wdt.c b/drivers/watchdog/w83697hf_wdt.c index 06ddd38675bd..12bd6618ed5e 100644 --- a/drivers/watchdog/w83697hf_wdt.c +++ b/drivers/watchdog/w83697hf_wdt.c @@ -251,21 +251,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_ping(); - break; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if (wdt_set_heartbeat(new_timeout)) - return -EINVAL; - wdt_ping(); - /* Fall */ - - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -286,6 +271,21 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return retval; } + case WDIOC_KEEPALIVE: + wdt_ping(); + break; + + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + if (wdt_set_heartbeat(new_timeout)) + return -EINVAL; + wdt_ping(); + /* Fall */ + + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/w83877f_wdt.c b/drivers/watchdog/w83877f_wdt.c index 75b546d7d8c2..24587d2060c4 100644 --- a/drivers/watchdog/w83877f_wdt.c +++ b/drivers/watchdog/w83877f_wdt.c @@ -254,16 +254,11 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) }; switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; case WDIOC_SETOPTIONS: { int new_options, retval = -EINVAL; @@ -283,6 +278,9 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return retval; } + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; case WDIOC_SETTIMEOUT: { int new_timeout; @@ -300,6 +298,8 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) } case WDIOC_GETTIMEOUT: return put_user(timeout, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/w83977f_wdt.c b/drivers/watchdog/w83977f_wdt.c index 6860a13f5bb9..2525da5080ca 100644 --- a/drivers/watchdog/w83977f_wdt.c +++ b/drivers/watchdog/w83977f_wdt.c @@ -390,9 +390,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) uarg.i = (int __user *)arg; switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: return copy_to_user(uarg.ident, &ident, sizeof(ident)) ? -EFAULT : 0; @@ -404,10 +401,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETBOOTSTATUS: return put_user(0, uarg.i); - case WDIOC_KEEPALIVE: - wdt_keepalive(); - return 0; - case WDIOC_SETOPTIONS: if (get_user(new_options, uarg.i)) return -EFAULT; @@ -424,6 +417,10 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) return retval; + case WDIOC_KEEPALIVE: + wdt_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: if (get_user(new_timeout, uarg.i)) return -EFAULT; @@ -437,6 +434,9 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) case WDIOC_GETTIMEOUT: return put_user(timeout, uarg.i); + default: + return -ENOTTY; + } } diff --git a/drivers/watchdog/wafer5823wdt.c b/drivers/watchdog/wafer5823wdt.c index 886cbbcf3eed..44e81f7d4322 100644 --- a/drivers/watchdog/wafer5823wdt.c +++ b/drivers/watchdog/wafer5823wdt.c @@ -145,22 +145,6 @@ static long wafwdt_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, p); - case WDIOC_KEEPALIVE: - wafwdt_ping(); - break; - - case WDIOC_SETTIMEOUT: - if (get_user(new_timeout, p)) - return -EFAULT; - if ((new_timeout < 1) || (new_timeout > 255)) - return -EINVAL; - timeout = new_timeout; - wafwdt_stop(); - wafwdt_start(); - /* Fall */ - case WDIOC_GETTIMEOUT: - return put_user(timeout, p); - case WDIOC_SETOPTIONS: { int options, retval = -EINVAL; @@ -181,6 +165,22 @@ static long wafwdt_ioctl(struct file *file, unsigned int cmd, return retval; } + case WDIOC_KEEPALIVE: + wafwdt_ping(); + break; + + case WDIOC_SETTIMEOUT: + if (get_user(new_timeout, p)) + return -EFAULT; + if ((new_timeout < 1) || (new_timeout > 255)) + return -EINVAL; + timeout = new_timeout; + wafwdt_stop(); + wafwdt_start(); + /* Fall */ + case WDIOC_GETTIMEOUT: + return put_user(timeout, p); + default: return -ENOTTY; } diff --git a/drivers/watchdog/wdt.c b/drivers/watchdog/wdt.c index 53a6b18bcb9a..deeebb2b13ea 100644 --- a/drivers/watchdog/wdt.c +++ b/drivers/watchdog/wdt.c @@ -373,8 +373,6 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) #endif /* CONFIG_WDT_501 */ switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: @@ -394,6 +392,8 @@ static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) /* Fall */ case WDIOC_GETTIMEOUT: return put_user(heartbeat, p); + default: + return -ENOTTY; } } diff --git a/drivers/watchdog/wdt977.c b/drivers/watchdog/wdt977.c index bdc28e522f03..60e28d49ff52 100644 --- a/drivers/watchdog/wdt977.c +++ b/drivers/watchdog/wdt977.c @@ -365,9 +365,6 @@ static long wdt977_ioctl(struct file *file, unsigned int cmd, uarg.i = (int __user *)arg; switch (cmd) { - default: - return -ENOTTY; - case WDIOC_GETSUPPORT: return copy_to_user(uarg.ident, &ident, sizeof(ident)) ? -EFAULT : 0; @@ -379,10 +376,6 @@ static long wdt977_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETBOOTSTATUS: return put_user(0, uarg.i); - case WDIOC_KEEPALIVE: - wdt977_keepalive(); - return 0; - case WDIOC_SETOPTIONS: if (get_user(new_options, uarg.i)) return -EFAULT; @@ -399,6 +392,10 @@ static long wdt977_ioctl(struct file *file, unsigned int cmd, return retval; + case WDIOC_KEEPALIVE: + wdt977_keepalive(); + return 0; + case WDIOC_SETTIMEOUT: if (get_user(new_timeout, uarg.i)) return -EFAULT; @@ -412,6 +409,9 @@ static long wdt977_ioctl(struct file *file, unsigned int cmd, case WDIOC_GETTIMEOUT: return put_user(timeout, uarg.i); + default: + return -ENOTTY; + } } diff --git a/drivers/watchdog/wdt_pci.c b/drivers/watchdog/wdt_pci.c index 5d922fd6eafc..fb8fc0144852 100644 --- a/drivers/watchdog/wdt_pci.c +++ b/drivers/watchdog/wdt_pci.c @@ -428,8 +428,6 @@ static long wdtpci_ioctl(struct file *file, unsigned int cmd, #endif /* CONFIG_WDT_501_PCI */ switch (cmd) { - default: - return -ENOTTY; case WDIOC_GETSUPPORT: return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: @@ -449,7 +447,9 @@ static long wdtpci_ioctl(struct file *file, unsigned int cmd, /* Fall */ case WDIOC_GETTIMEOUT: return put_user(heartbeat, p); - } + default: + return -ENOTTY; + } } /** -- cgit v1.2.3 From 12b7a1523eda9cd72362fdda928ddb995ecdc06d Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Fri, 18 Jul 2008 19:59:48 +0000 Subject: [WATCHDOG] sbc8360.c - move stop code into a function Move the sbc8360.c watchdog stop code into a seperate function. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/sbc8360.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/sbc8360.c b/drivers/watchdog/sbc8360.c index c66fa6694fc3..fd83dd052d8c 100644 --- a/drivers/watchdog/sbc8360.c +++ b/drivers/watchdog/sbc8360.c @@ -231,6 +231,13 @@ static void sbc8360_ping(void) outb(wd_margin, SBC8360_BASETIME); } +/* stop watchdog */ +static void sbc8360_stop(void) +{ + /* De-activate the watchdog */ + outb(0, SBC8360_ENABLE); +} + /* Userspace pings kernel driver, or requests clean close */ static ssize_t sbc8360_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos) @@ -271,7 +278,7 @@ static int sbc8360_open(struct inode *inode, struct file *file) static int sbc8360_close(struct inode *inode, struct file *file) { if (expect_close == 42) - outb(0, SBC8360_ENABLE); + sbc8360_stop(); else printk(KERN_CRIT PFX "SBC8360 device closed unexpectedly. SBC8360 will not stop!\n"); @@ -288,10 +295,9 @@ static int sbc8360_close(struct inode *inode, struct file *file) static int sbc8360_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Disable the SBC8360 Watchdog */ - outb(0, SBC8360_ENABLE); - } + if (code == SYS_DOWN || code == SYS_HALT) + sbc8360_stop(); /* Disable the SBC8360 Watchdog */ + return NOTIFY_DONE; } -- cgit v1.2.3 From 3a35c27ac68cea19c252e127ec61099648eb4870 Mon Sep 17 00:00:00 2001 From: Randy Dunlap Date: Wed, 6 Aug 2008 10:08:56 -0700 Subject: docbook: fix v4l fatal filename error docproc: /var/linsrc/lin2627-rc2/drivers/media/video/videodev.c: No such file or directory make[1]: *** [Documentation/DocBook/videobook.xml] Error 1 Signed-off-by: Randy Dunlap cc: mchehab@infradead.org Signed-off-by: Linus Torvalds --- Documentation/DocBook/videobook.tmpl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/DocBook/videobook.tmpl b/Documentation/DocBook/videobook.tmpl index 89817795e668..0bc25949b668 100644 --- a/Documentation/DocBook/videobook.tmpl +++ b/Documentation/DocBook/videobook.tmpl @@ -1648,7 +1648,7 @@ static struct video_buffer capture_fb; Public Functions Provided -!Edrivers/media/video/videodev.c +!Edrivers/media/video/v4l2-dev.c -- cgit v1.2.3 From 8bc5fb6abb670fa9079cd1994f016a39f99698fe Mon Sep 17 00:00:00 2001 From: Alan Cox Date: Wed, 6 Aug 2008 14:06:29 +0100 Subject: Remove bogons from the iSeries console The iSeries driver calls into the n_tty ldisc code directly for some bizarre reason. I previously tagged this with a query but this actually does need fixing as n_tty methods when you have a different ldisc set are not a good thing to call. In n_tty mode this change should have no effect, the core tty layer has always called the ldisc ioctl method *anyway* and will call the one for the right ldisc. Signed-off-by: Alan Cox Acked-by: Stephen Rothwell Signed-off-by: Linus Torvalds --- drivers/char/viocons.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/char/viocons.c b/drivers/char/viocons.c index 65fb848e1cce..f48892ba12f5 100644 --- a/drivers/char/viocons.c +++ b/drivers/char/viocons.c @@ -705,10 +705,6 @@ static int viotty_ioctl(struct tty_struct *tty, struct file *file, case KDSKBLED: return 0; } - /* FIXME: WTF is this being called for ??? */ - lock_kernel(); - ret = n_tty_ioctl(tty, file, cmd, arg); - unlock_kernel(); return ret; } -- cgit v1.2.3 From d6606683a5e3dac35cb979c7195f54ed827567bd Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 6 Aug 2008 12:04:54 -0700 Subject: Revert duplicate "mm/hugetlb.c must #include " This reverts commit 7cb93181629c613ee2b8f4ffe3446f8003074842, since we did that patch twice, and the problem was already fixed earlier by 78a34ae29bf1c9df62a5bd0f0798b6c62a54d520. Reported-by: Andi Kleen Signed-off-by: Linus Torvalds --- mm/hugetlb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/mm/hugetlb.c b/mm/hugetlb.c index 28a2980ee435..757ca983fd99 100644 --- a/mm/hugetlb.c +++ b/mm/hugetlb.c @@ -17,7 +17,7 @@ #include #include #include -#include + #include #include #include -- cgit v1.2.3 From 7944d3a5a70ee5c1904ed1e8b1d71ff0af2854d9 Mon Sep 17 00:00:00 2001 From: Wim Van Sebroeck Date: Wed, 6 Aug 2008 20:19:41 +0000 Subject: [WATCHDOG] more coding style clean-up's More coding style clean-up's. Signed-off-by: Wim Van Sebroeck --- drivers/watchdog/Kconfig | 2 +- drivers/watchdog/Makefile | 2 +- drivers/watchdog/acquirewdt.c | 2 +- drivers/watchdog/advantechwdt.c | 17 +++++----- drivers/watchdog/alim1535_wdt.c | 2 +- drivers/watchdog/alim7101_wdt.c | 4 +-- drivers/watchdog/ar7_wdt.c | 4 +-- drivers/watchdog/at32ap700x_wdt.c | 2 +- drivers/watchdog/eurotechwdt.c | 8 ++--- drivers/watchdog/geodewdt.c | 62 ++++++++++++++-------------------- drivers/watchdog/hpwdt.c | 4 +-- drivers/watchdog/i6300esb.c | 34 +++++++++---------- drivers/watchdog/iTCO_vendor_support.c | 10 +++--- drivers/watchdog/iTCO_wdt.c | 10 +++--- drivers/watchdog/ib700wdt.c | 12 +++---- drivers/watchdog/ibmasr.c | 4 +-- drivers/watchdog/iop_wdt.c | 2 +- drivers/watchdog/it8712f_wdt.c | 2 +- drivers/watchdog/ixp4xx_wdt.c | 13 ++++--- drivers/watchdog/mpc5200_wdt.c | 6 ++-- drivers/watchdog/mpcore_wdt.c | 8 ++--- drivers/watchdog/mtx-1_wdt.c | 4 +-- drivers/watchdog/omap_wdt.c | 2 +- drivers/watchdog/pc87413_wdt.c | 38 ++++++++++----------- drivers/watchdog/pcwd.c | 6 ++-- drivers/watchdog/pcwd_pci.c | 28 +++++++-------- drivers/watchdog/pcwd_usb.c | 61 ++++++++++++++++----------------- drivers/watchdog/rm9k_wdt.c | 13 ++++--- drivers/watchdog/sb_wdog.c | 4 +-- drivers/watchdog/sbc60xxwdt.c | 4 +-- drivers/watchdog/sc1200wdt.c | 2 +- drivers/watchdog/scx200_wdt.c | 2 +- drivers/watchdog/smsc37b787_wdt.c | 4 +-- drivers/watchdog/txx9wdt.c | 2 +- drivers/watchdog/w83627hf_wdt.c | 9 +++-- drivers/watchdog/w83697hf_wdt.c | 11 +++--- drivers/watchdog/wafer5823wdt.c | 20 +++++------ drivers/watchdog/wd501p.h | 2 +- drivers/watchdog/wdrtas.c | 2 +- drivers/watchdog/wdt_pci.c | 2 +- 40 files changed, 199 insertions(+), 227 deletions(-) diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 50d44b4b466b..32b9fe153641 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -463,7 +463,7 @@ config PC87413_WDT module will be called pc87413_wdt. Most people will say N. - + config 60XX_WDT tristate "SBC-60XX Watchdog Timer" depends on X86 diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index cdd674ffaa21..049c91895699 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -92,7 +92,7 @@ obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o # MIPS Architecture obj-$(CONFIG_INDYDOG) += indydog.o -obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o +obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o obj-$(CONFIG_WDT_RM9K_GPI) += rm9k_wdt.o obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o obj-$(CONFIG_AR7_WDT) += ar7_wdt.o diff --git a/drivers/watchdog/acquirewdt.c b/drivers/watchdog/acquirewdt.c index 7a5c69421f12..6e46a551395c 100644 --- a/drivers/watchdog/acquirewdt.c +++ b/drivers/watchdog/acquirewdt.c @@ -126,7 +126,7 @@ static ssize_t acq_write(struct file *file, const char __user *buf, if (!nowayout) { size_t i; /* note: just in case someone wrote the magic character - * five months ago... */ + five months ago... */ expect_close = 0; /* scan to see whether or not we got the magic character */ diff --git a/drivers/watchdog/advantechwdt.c b/drivers/watchdog/advantechwdt.c index bfec16600475..a5110f93a755 100644 --- a/drivers/watchdog/advantechwdt.c +++ b/drivers/watchdog/advantechwdt.c @@ -47,7 +47,8 @@ #define WATCHDOG_NAME "Advantech WDT" #define WATCHDOG_TIMEOUT 60 /* 60 sec default timeout */ -static struct platform_device *advwdt_platform_device; /* the watchdog platform device */ +/* the watchdog platform device */ +static struct platform_device *advwdt_platform_device; static unsigned long advwdt_is_open; static char adv_expect_close; @@ -120,7 +121,7 @@ static ssize_t advwdt_write(struct file *file, const char __user *buf, for (i = 0; i != count; i++) { char c; - if (get_user(c, buf+i)) + if (get_user(c, buf + i)) return -EFAULT; if (c == 'V') adv_expect_close = 42; @@ -199,8 +200,7 @@ static int advwdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int -advwdt_close(struct inode *inode, struct file *file) +static int advwdt_close(struct inode *inode, struct file *file) { if (adv_expect_close == 42) { advwdt_disable(); @@ -288,9 +288,9 @@ unreg_stop: static int __devexit advwdt_remove(struct platform_device *dev) { misc_deregister(&advwdt_miscdev); - release_region(wdt_start,1); - if(wdt_stop != wdt_start) - release_region(wdt_stop,1); + release_region(wdt_start, 1); + if (wdt_stop != wdt_start) + release_region(wdt_stop, 1); return 0; } @@ -315,7 +315,8 @@ static int __init advwdt_init(void) { int err; - printk(KERN_INFO "WDT driver for Advantech single board computer initialising.\n"); + printk(KERN_INFO + "WDT driver for Advantech single board computer initialising.\n"); err = platform_driver_register(&advwdt_driver); if (err) diff --git a/drivers/watchdog/alim1535_wdt.c b/drivers/watchdog/alim1535_wdt.c index dfa11d19043a..2a7690ecf97d 100644 --- a/drivers/watchdog/alim1535_wdt.c +++ b/drivers/watchdog/alim1535_wdt.c @@ -153,7 +153,7 @@ static ssize_t ali_write(struct file *file, const char __user *data, the magic character */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') ali_expect_release = 42; diff --git a/drivers/watchdog/alim7101_wdt.c b/drivers/watchdog/alim7101_wdt.c index 049c9122e40d..a045ef869439 100644 --- a/drivers/watchdog/alim7101_wdt.c +++ b/drivers/watchdog/alim7101_wdt.c @@ -125,7 +125,7 @@ static void wdt_timer_ping(unsigned long data) static void wdt_change(int writeval) { - char tmp; + char tmp; pci_read_config_byte(alim7101_pmu, ALI_7101_WDT, &tmp); if (writeval == WDT_ENABLE) { @@ -198,7 +198,7 @@ static ssize_t fop_write(struct file *file, const char __user *buf, /* now scan */ for (ofs = 0; ofs != count; ofs++) { char c; - if (get_user(c, buf+ofs)) + if (get_user(c, buf + ofs)) return -EFAULT; if (c == 'V') wdt_expect_close = 42; diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index 9a81a205ef74..55dcbfe2bb72 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -213,7 +213,7 @@ static int ar7_wdt_notify_sys(struct notifier_block *this, } static struct notifier_block ar7_wdt_notifier = { - .notifier_call = ar7_wdt_notify_sys + .notifier_call = ar7_wdt_notify_sys, }; static ssize_t ar7_wdt_write(struct file *file, const char *data, @@ -230,7 +230,7 @@ static ssize_t ar7_wdt_write(struct file *file, const char *data, expect_close = 0; for (i = 0; i < len; ++i) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 1; diff --git a/drivers/watchdog/at32ap700x_wdt.c b/drivers/watchdog/at32ap700x_wdt.c index 4538b57f451a..e8ae638e5804 100644 --- a/drivers/watchdog/at32ap700x_wdt.c +++ b/drivers/watchdog/at32ap700x_wdt.c @@ -283,7 +283,7 @@ static ssize_t at32_wdt_write(struct file *file, const char __user *data, */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_release = 42; diff --git a/drivers/watchdog/eurotechwdt.c b/drivers/watchdog/eurotechwdt.c index 96250118fd7c..bbd14e34319f 100644 --- a/drivers/watchdog/eurotechwdt.c +++ b/drivers/watchdog/eurotechwdt.c @@ -210,7 +210,7 @@ size_t count, loff_t *ppos) for (i = 0; i != count; i++) { char c; - if (get_user(c, buf+i)) + if (get_user(c, buf + i)) return -EFAULT; if (c == 'V') eur_expect_close = 42; @@ -360,10 +360,8 @@ static int eurwdt_release(struct inode *inode, struct file *file) static int eurwdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Turn the card off */ - eurwdt_disable_timer(); - } + if (code == SYS_DOWN || code == SYS_HALT) + eurwdt_disable_timer(); /* Turn the card off */ return NOTIFY_DONE; } diff --git a/drivers/watchdog/geodewdt.c b/drivers/watchdog/geodewdt.c index 04b861cfdf0c..614a5c7017b6 100644 --- a/drivers/watchdog/geodewdt.c +++ b/drivers/watchdog/geodewdt.c @@ -77,27 +77,24 @@ static int geodewdt_set_heartbeat(int val) return 0; } -static int -geodewdt_open(struct inode *inode, struct file *file) +static int geodewdt_open(struct inode *inode, struct file *file) { - if (test_and_set_bit(WDT_FLAGS_OPEN, &wdt_flags)) - return -EBUSY; + if (test_and_set_bit(WDT_FLAGS_OPEN, &wdt_flags)) + return -EBUSY; - if (!test_and_clear_bit(WDT_FLAGS_ORPHAN, &wdt_flags)) - __module_get(THIS_MODULE); + if (!test_and_clear_bit(WDT_FLAGS_ORPHAN, &wdt_flags)) + __module_get(THIS_MODULE); geodewdt_ping(); - return nonseekable_open(inode, file); + return nonseekable_open(inode, file); } -static int -geodewdt_release(struct inode *inode, struct file *file) +static int geodewdt_release(struct inode *inode, struct file *file) { if (safe_close) { geodewdt_disable(); module_put(THIS_MODULE); - } - else { + } else { printk(KERN_CRIT "Unexpected close - watchdog is not stopping.\n"); geodewdt_ping(); @@ -109,11 +106,10 @@ geodewdt_release(struct inode *inode, struct file *file) return 0; } -static ssize_t -geodewdt_write(struct file *file, const char __user *data, size_t len, - loff_t *ppos) +static ssize_t geodewdt_write(struct file *file, const char __user *data, + size_t len, loff_t *ppos) { - if(len) { + if (len) { if (!nowayout) { size_t i; safe_close = 0; @@ -134,9 +130,8 @@ geodewdt_write(struct file *file, const char __user *data, size_t len, return len; } -static int -geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, - unsigned long arg) +static int geodewdt_ioctl(struct inode *inode, struct file *file, + unsigned int cmd, unsigned long arg) { void __user *argp = (void __user *)arg; int __user *p = argp; @@ -147,7 +142,7 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, | WDIOF_MAGICCLOSE, .firmware_version = 1, .identity = WATCHDOG_NAME, - }; + }; switch (cmd) { case WDIOC_GETSUPPORT: @@ -200,22 +195,21 @@ geodewdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, } static const struct file_operations geodewdt_fops = { - .owner = THIS_MODULE, - .llseek = no_llseek, - .write = geodewdt_write, - .ioctl = geodewdt_ioctl, - .open = geodewdt_open, - .release = geodewdt_release, + .owner = THIS_MODULE, + .llseek = no_llseek, + .write = geodewdt_write, + .ioctl = geodewdt_ioctl, + .open = geodewdt_open, + .release = geodewdt_release, }; static struct miscdevice geodewdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", - .fops = &geodewdt_fops + .fops = &geodewdt_fops, }; -static int __devinit -geodewdt_probe(struct platform_device *dev) +static int __devinit geodewdt_probe(struct platform_device *dev) { int ret, timer; @@ -246,15 +240,13 @@ geodewdt_probe(struct platform_device *dev) return ret; } -static int __devexit -geodewdt_remove(struct platform_device *dev) +static int __devexit geodewdt_remove(struct platform_device *dev) { misc_deregister(&geodewdt_miscdev); return 0; } -static void -geodewdt_shutdown(struct platform_device *dev) +static void geodewdt_shutdown(struct platform_device *dev) { geodewdt_disable(); } @@ -269,8 +261,7 @@ static struct platform_driver geodewdt_driver = { }, }; -static int __init -geodewdt_init(void) +static int __init geodewdt_init(void) { int ret; @@ -290,8 +281,7 @@ err: return ret; } -static void __exit -geodewdt_exit(void) +static void __exit geodewdt_exit(void) { platform_device_unregister(geodewdt_platform_device); platform_driver_unregister(&geodewdt_driver); diff --git a/drivers/watchdog/hpwdt.c b/drivers/watchdog/hpwdt.c index 7ea8f3e844f3..d039d5f2fd1c 100644 --- a/drivers/watchdog/hpwdt.c +++ b/drivers/watchdog/hpwdt.c @@ -405,7 +405,7 @@ static int __devinit detect_cru_service(void) dmi_walk(dmi_find_cru); /* if cru_rom_addr has been set then we found a CRU service */ - return ((cru_rom_addr != NULL)? 0: -ENODEV); + return ((cru_rom_addr != NULL) ? 0: -ENODEV); } /* ------------------------------------------------------------------------- */ @@ -533,7 +533,7 @@ static ssize_t hpwdt_write(struct file *file, const char __user *data, /* scan to see whether or not we got the magic char. */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_release = 42; diff --git a/drivers/watchdog/i6300esb.c b/drivers/watchdog/i6300esb.c index c768cb718904..c13383f7fcb9 100644 --- a/drivers/watchdog/i6300esb.c +++ b/drivers/watchdog/i6300esb.c @@ -9,18 +9,18 @@ * as published by the Free Software Foundation; either version * 2 of the License, or (at your option) any later version. * - * based on i810-tco.c which is in turn based on softdog.c + * based on i810-tco.c which is in turn based on softdog.c * - * The timer is implemented in the following I/O controller hubs: - * (See the intel documentation on http://developer.intel.com.) - * 6300ESB chip : document number 300641-003 + * The timer is implemented in the following I/O controller hubs: + * (See the intel documentation on http://developer.intel.com.) + * 6300ESB chip : document number 300641-003 * * 2004YYZZ Ross Biro * Initial version 0.01 * 2004YYZZ Ross Biro - * Version 0.02 + * Version 0.02 * 20050210 David Härdeman - * Ported driver to kernel 2.6 + * Ported driver to kernel 2.6 */ /* @@ -108,7 +108,8 @@ MODULE_PARM_DESC(nowayout, * reload register. After this the appropriate registers can be written * to once before they need to be unlocked again. */ -static inline void esb_unlock_registers(void) { +static inline void esb_unlock_registers(void) +{ writeb(ESB_UNLOCK1, ESB_RELOAD_REG); writeb(ESB_UNLOCK2, ESB_RELOAD_REG); } @@ -169,7 +170,7 @@ static int esb_timer_set_heartbeat(int time) /* Write timer 2 */ esb_unlock_registers(); - writel(val, ESB_TIMER2_REG); + writel(val, ESB_TIMER2_REG); /* Reload */ esb_unlock_registers(); @@ -196,7 +197,7 @@ static int esb_timer_read(void) } /* - * /dev/watchdog handling + * /dev/watchdog handling */ static int esb_open(struct inode *inode, struct file *file) @@ -242,7 +243,7 @@ static ssize_t esb_write(struct file *file, const char __user *data, /* scan to see whether or not we got the magic character */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') esb_expect_close = 42; @@ -262,11 +263,11 @@ static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) void __user *argp = (void __user *)arg; int __user *p = argp; static struct watchdog_info ident = { - .options = WDIOF_SETTIMEOUT | + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, - .firmware_version = 0, - .identity = ESB_MODULE_NAME, + .firmware_version = 0, + .identity = ESB_MODULE_NAME, }; switch (cmd) { @@ -324,10 +325,9 @@ static long esb_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static int esb_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Turn the WDT off */ - esb_timer_stop(); - } + if (code == SYS_DOWN || code == SYS_HALT) + esb_timer_stop(); /* Turn the WDT off */ + return NOTIFY_DONE; } diff --git a/drivers/watchdog/iTCO_vendor_support.c b/drivers/watchdog/iTCO_vendor_support.c index e9e1f7b3fb75..ca344a85eb95 100644 --- a/drivers/watchdog/iTCO_vendor_support.c +++ b/drivers/watchdog/iTCO_vendor_support.c @@ -18,9 +18,9 @@ */ /* Module and version information */ -#define DRV_NAME "iTCO_vendor_support" -#define DRV_VERSION "1.01" -#define DRV_RELDATE "11-Nov-2006" +#define DRV_NAME "iTCO_vendor_support" +#define DRV_VERSION "1.01" +#define DRV_RELDATE "11-Nov-2006" #define PFX DRV_NAME ": " /* Includes */ @@ -37,8 +37,8 @@ /* iTCO defines */ #define SMI_EN acpibase + 0x30 /* SMI Control and Enable Register */ -#define TCOBASE acpibase + 0x60 /* TCO base address */ -#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ +#define TCOBASE acpibase + 0x60 /* TCO base address */ +#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */ /* List of vendor support modes */ /* SuperMicro Pentium 3 Era 370SSE+-OEM1/P3TSSE */ diff --git a/drivers/watchdog/iTCO_wdt.c b/drivers/watchdog/iTCO_wdt.c index b18766436638..bfb93bc2ca9f 100644 --- a/drivers/watchdog/iTCO_wdt.c +++ b/drivers/watchdog/iTCO_wdt.c @@ -55,9 +55,9 @@ */ /* Module and version information */ -#define DRV_NAME "iTCO_wdt" -#define DRV_VERSION "1.03" -#define DRV_RELDATE "30-Apr-2008" +#define DRV_NAME "iTCO_wdt" +#define DRV_VERSION "1.03" +#define DRV_RELDATE "30-Apr-2008" #define PFX DRV_NAME ": " /* Includes */ @@ -107,7 +107,7 @@ enum iTCO_chipsets { TCO_ICH9, /* ICH9 */ TCO_ICH9R, /* ICH9R */ TCO_ICH9DH, /* ICH9DH */ - TCO_ICH9DO, /* ICH9DO */ + TCO_ICH9DO, /* ICH9DO */ TCO_631XESB, /* 631xESB/632xESB */ }; @@ -497,7 +497,7 @@ static ssize_t iTCO_wdt_write(struct file *file, const char __user *data, magic character */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_release = 42; diff --git a/drivers/watchdog/ib700wdt.c b/drivers/watchdog/ib700wdt.c index 6aa914e5caf5..05a28106e8eb 100644 --- a/drivers/watchdog/ib700wdt.c +++ b/drivers/watchdog/ib700wdt.c @@ -129,8 +129,7 @@ MODULE_PARM_DESC(nowayout, * Watchdog Operations */ -static void -ibwdt_ping(void) +static void ibwdt_ping(void) { spin_lock(&ibwdt_lock); @@ -140,16 +139,14 @@ ibwdt_ping(void) spin_unlock(&ibwdt_lock); } -static void -ibwdt_disable(void) +static void ibwdt_disable(void) { spin_lock(&ibwdt_lock); outb_p(0, WDT_STOP); spin_unlock(&ibwdt_lock); } -static int -ibwdt_set_heartbeat(int t) +static int ibwdt_set_heartbeat(int t) { int i; @@ -263,8 +260,7 @@ static int ibwdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int -ibwdt_close(struct inode *inode, struct file *file) +static int ibwdt_close(struct inode *inode, struct file *file) { if (expect_close == 42) { ibwdt_disable(); diff --git a/drivers/watchdog/ibmasr.c b/drivers/watchdog/ibmasr.c index 0b549f3ff915..b82405cfb4cd 100644 --- a/drivers/watchdog/ibmasr.c +++ b/drivers/watchdog/ibmasr.c @@ -275,7 +275,7 @@ static long asr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) static const struct watchdog_info ident = { .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE, - .identity = "IBM ASR" + .identity = "IBM ASR", }; void __user *argp = (void __user *)arg; int __user *p = argp; @@ -345,7 +345,7 @@ static int asr_release(struct inode *inode, struct file *file) static const struct file_operations asr_fops = { .owner = THIS_MODULE, - .llseek = no_llseek, + .llseek = no_llseek, .write = asr_write, .unlocked_ioctl = asr_ioctl, .open = asr_open, diff --git a/drivers/watchdog/iop_wdt.c b/drivers/watchdog/iop_wdt.c index e0d0a90ea10c..8278b13f77c7 100644 --- a/drivers/watchdog/iop_wdt.c +++ b/drivers/watchdog/iop_wdt.c @@ -241,7 +241,7 @@ static int __init iop_wdt_init(void) with an open */ ret = misc_register(&iop_wdt_miscdev); if (ret == 0) - printk("iop watchdog timer: timeout %lu sec\n", + printk(KERN_INFO "iop watchdog timer: timeout %lu sec\n", iop_watchdog_timeout()); return ret; diff --git a/drivers/watchdog/it8712f_wdt.c b/drivers/watchdog/it8712f_wdt.c index c1db74f6e310..2270ee07c01b 100644 --- a/drivers/watchdog/it8712f_wdt.c +++ b/drivers/watchdog/it8712f_wdt.c @@ -221,7 +221,7 @@ static ssize_t it8712f_wdt_write(struct file *file, const char __user *data, expect_close = 0; for (i = 0; i < len; ++i) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; diff --git a/drivers/watchdog/ixp4xx_wdt.c b/drivers/watchdog/ixp4xx_wdt.c index b94713e4773d..ef3157dc9ac1 100644 --- a/drivers/watchdog/ixp4xx_wdt.c +++ b/drivers/watchdog/ixp4xx_wdt.c @@ -157,8 +157,7 @@ static int ixp4xx_wdt_release(struct inode *inode, struct file *file) } -static const struct file_operations ixp4xx_wdt_fops = -{ +static const struct file_operations ixp4xx_wdt_fops = { .owner = THIS_MODULE, .llseek = no_llseek, .write = ixp4xx_wdt_write, @@ -167,8 +166,7 @@ static const struct file_operations ixp4xx_wdt_fops = .release = ixp4xx_wdt_release, }; -static struct miscdevice ixp4xx_wdt_miscdev = -{ +static struct miscdevice ixp4xx_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", .fops = &ixp4xx_wdt_fops, @@ -181,8 +179,8 @@ static int __init ixp4xx_wdt_init(void) asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :); if (!(processor_id & 0xf) && !cpu_is_ixp46x()) { - printk("IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected - " - "watchdog disabled\n"); + printk(KERN_ERR "IXP4XXX Watchdog: Rev. A0 IXP42x CPU detected" + " - watchdog disabled\n"); return -ENODEV; } @@ -191,7 +189,8 @@ static int __init ixp4xx_wdt_init(void) WDIOF_CARDRESET : 0; ret = misc_register(&ixp4xx_wdt_miscdev); if (ret == 0) - printk("IXP4xx Watchdog Timer: heartbeat %d sec\n", heartbeat); + printk(KERN_INFO "IXP4xx Watchdog Timer: heartbeat %d sec\n", + heartbeat); return ret; } diff --git a/drivers/watchdog/mpc5200_wdt.c b/drivers/watchdog/mpc5200_wdt.c index ce1811d5d6b1..db91892558f2 100644 --- a/drivers/watchdog/mpc5200_wdt.c +++ b/drivers/watchdog/mpc5200_wdt.c @@ -164,7 +164,7 @@ static int mpc5200_wdt_release(struct inode *inode, struct file *file) static const struct file_operations mpc5200_wdt_fops = { .owner = THIS_MODULE, .write = mpc5200_wdt_write, - .ioctl = mpc5200_wdt_ioctl, + .unlocked_ioctl = mpc5200_wdt_ioctl, .open = mpc5200_wdt_open, .release = mpc5200_wdt_release, }; @@ -219,9 +219,9 @@ static int mpc5200_wdt_probe(struct of_device *op, return 0; iounmap(wdt->regs); - out_release: +out_release: release_mem_region(wdt->mem.start, size); - out_free: +out_free: kfree(wdt); return err; } diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c index 3c4f95599c65..2a9bfa81f9d6 100644 --- a/drivers/watchdog/mpcore_wdt.c +++ b/drivers/watchdog/mpcore_wdt.c @@ -377,13 +377,13 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev) return 0; - err_irq: +err_irq: misc_deregister(&mpcore_wdt_miscdev); - err_misc: +err_misc: iounmap(wdt->base); - err_free: +err_free: kfree(wdt); - err_out: +err_out: return ret; } diff --git a/drivers/watchdog/mtx-1_wdt.c b/drivers/watchdog/mtx-1_wdt.c index f820b82da7c3..b4b7b0a4c119 100644 --- a/drivers/watchdog/mtx-1_wdt.c +++ b/drivers/watchdog/mtx-1_wdt.c @@ -191,14 +191,14 @@ static const struct file_operations mtx1_wdt_fops = { .unlocked_ioctl = mtx1_wdt_ioctl, .open = mtx1_wdt_open, .write = mtx1_wdt_write, - .release = mtx1_wdt_release + .release = mtx1_wdt_release, }; static struct miscdevice mtx1_wdt_misc = { .minor = WATCHDOG_MINOR, .name = "watchdog", - .fops = &mtx1_wdt_fops + .fops = &mtx1_wdt_fops, }; diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c index 7beb21ce1de9..6f5420f478a9 100644 --- a/drivers/watchdog/omap_wdt.c +++ b/drivers/watchdog/omap_wdt.c @@ -245,7 +245,7 @@ static const struct file_operations omap_wdt_fops = { static struct miscdevice omap_wdt_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", - .fops = &omap_wdt_fops + .fops = &omap_wdt_fops, }; static int __init omap_wdt_probe(struct platform_device *pdev) diff --git a/drivers/watchdog/pc87413_wdt.c b/drivers/watchdog/pc87413_wdt.c index 5fc7f1349950..e91ada72da1d 100644 --- a/drivers/watchdog/pc87413_wdt.c +++ b/drivers/watchdog/pc87413_wdt.c @@ -38,7 +38,7 @@ /* #define DEBUG 1 */ -#define DEFAULT_TIMEOUT 1 /* 1 minute */ +#define DEFAULT_TIMEOUT 1 /* 1 minute */ #define MAX_TIMEOUT 255 #define VERSION "1.1" @@ -46,17 +46,17 @@ #define PFX MODNAME ": " #define DPFX MODNAME " - DEBUG: " -#define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */ +#define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */ #define WDT_DATA_IO_PORT (WDT_INDEX_IO_PORT+1) #define SWC_LDN 0x04 -#define SIOCFG2 0x22 /* Serial IO register */ -#define WDCTL 0x10 /* Watchdog-Timer-Controll-Register */ -#define WDTO 0x11 /* Watchdog timeout register */ -#define WDCFG 0x12 /* Watchdog config register */ +#define SIOCFG2 0x22 /* Serial IO register */ +#define WDCTL 0x10 /* Watchdog-Timer-Controll-Register */ +#define WDTO 0x11 /* Watchdog timeout register */ +#define WDCFG 0x12 /* Watchdog config register */ -static int io = 0x2E; /* Address used on Portwell Boards */ +static int io = 0x2E; /* Address used on Portwell Boards */ -static int timeout = DEFAULT_TIMEOUT; /* timeout value */ +static int timeout = DEFAULT_TIMEOUT; /* timeout value */ static unsigned long timer_enabled; /* is the timer enabled? */ static char expect_close; /* is the close expected? */ @@ -99,14 +99,14 @@ static inline void pc87413_enable_swc(void) /* Step 2: Enable SWC functions */ - outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */ + outb_p(0x07, WDT_INDEX_IO_PORT); /* Point SWC_LDN (LDN=4) */ outb_p(SWC_LDN, WDT_DATA_IO_PORT); - outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */ + outb_p(0x30, WDT_INDEX_IO_PORT); /* Read Index 0x30 First */ cr_data = inb(WDT_DATA_IO_PORT); - cr_data |= 0x01; /* Set Bit0 to 1 */ + cr_data |= 0x01; /* Set Bit0 to 1 */ outb_p(0x30, WDT_INDEX_IO_PORT); - outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */ + outb_p(cr_data, WDT_DATA_IO_PORT); /* Index0x30_bit0P1 */ #ifdef DEBUG printk(KERN_INFO DPFX "pc87413 - Enable SWC functions\n"); @@ -122,10 +122,10 @@ static inline unsigned int pc87413_get_swc_base(void) /* Step 3: Read SWC I/O Base Address */ - outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */ + outb_p(0x60, WDT_INDEX_IO_PORT); /* Read Index 0x60 */ addr_h = inb(WDT_DATA_IO_PORT); - outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */ + outb_p(0x61, WDT_INDEX_IO_PORT); /* Read Index 0x61 */ addr_l = inb(WDT_DATA_IO_PORT); @@ -374,7 +374,7 @@ static ssize_t pc87413_write(struct file *file, const char __user *data, magic character */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -413,7 +413,7 @@ static long pc87413_ioctl(struct file *file, unsigned int cmd, WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 1, - .identity = "PC87413(HF/F) watchdog" + .identity = "PC87413(HF/F) watchdog", }; uarg.i = (int __user *)arg; @@ -507,7 +507,7 @@ static struct notifier_block pc87413_notifier = { static struct miscdevice pc87413_miscdev = { .minor = WATCHDOG_MINOR, .name = "watchdog", - .fops = &pc87413_fops + .fops = &pc87413_fops, }; /* -- Module init functions -------------------------------------*/ @@ -567,9 +567,9 @@ static void __exit pc87413_exit(void) misc_deregister(&pc87413_miscdev); unregister_reboot_notifier(&pc87413_notifier); - /* release_region(io,2); */ + /* release_region(io, 2); */ - printk(MODNAME " watchdog component driver removed.\n"); + printk(KERN_INFO MODNAME " watchdog component driver removed.\n"); } module_init(pc87413_init); diff --git a/drivers/watchdog/pcwd.c b/drivers/watchdog/pcwd.c index 134386a88852..3b0ddc7fcf3f 100644 --- a/drivers/watchdog/pcwd.c +++ b/drivers/watchdog/pcwd.c @@ -145,7 +145,7 @@ static int pcwd_ioports[] = { 0x270, 0x350, 0x370, 0x000 }; #define CMD_ISA_RESET_RELAYS 0x0D /* Watchdog's Dip Switch heartbeat values */ -static const int heartbeat_tbl [] = { +static const int heartbeat_tbl[] = { 20, /* OFF-OFF-OFF = 20 Sec */ 40, /* OFF-OFF-ON = 40 Sec */ 60, /* OFF-ON-OFF = 1 Min */ @@ -272,7 +272,7 @@ static int set_command_mode(void) printk(KERN_DEBUG PFX "command_mode=%d\n", pcwd_private.command_mode); - return(found); + return found; } static void unset_command_mode(void) @@ -325,7 +325,7 @@ static inline int pcwd_get_option_switches(void) } unset_command_mode(); - return(option_switches); + return option_switches; } static void pcwd_show_card_info(void) diff --git a/drivers/watchdog/pcwd_pci.c b/drivers/watchdog/pcwd_pci.c index 2617129a7ccc..90eb1d4271d7 100644 --- a/drivers/watchdog/pcwd_pci.c +++ b/drivers/watchdog/pcwd_pci.c @@ -96,7 +96,7 @@ #define CMD_GET_CLEAR_RESET_COUNT 0x84 /* Watchdog's Dip Switch heartbeat values */ -static const int heartbeat_tbl [] = { +static const int heartbeat_tbl[] = { 5, /* OFF-OFF-OFF = 5 Sec */ 10, /* OFF-OFF-ON = 10 Sec */ 30, /* OFF-ON-OFF = 30 Sec */ @@ -219,11 +219,10 @@ static void pcipcwd_show_card_info(void) int option_switches; got_fw_rev = send_command(CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); - if (got_fw_rev) { + if (got_fw_rev) sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); - } else { + else sprintf(fw_ver_str, ""); - } /* Get switch settings */ option_switches = pcipcwd_get_option_switches(); @@ -330,7 +329,7 @@ static int pcipcwd_get_status(int *status) { int control_status; - *status=0; + *status = 0; control_status = inb_p(pcipcwd_private.io_addr + 1); if (control_status & WD_PCI_WTRP) *status |= WDIOF_CARDRESET; @@ -368,8 +367,8 @@ static int pcipcwd_clear_status(void) outb_p((control_status & WD_PCI_R2DS) | WD_PCI_WTRP, pcipcwd_private.io_addr + 1); /* clear reset counter */ - msb=0; - reset_counter=0xff; + msb = 0; + reset_counter = 0xff; send_command(CMD_GET_CLEAR_RESET_COUNT, &msb, &reset_counter); if (debug >= DEBUG) { @@ -441,7 +440,7 @@ static ssize_t pcipcwd_write(struct file *file, const char __user *data, /* scan to see whether or not we got the magic character */ for (i = 0; i != len; i++) { char c; - if(get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_release = 42; @@ -471,8 +470,7 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, - sizeof (ident)) ? -EFAULT : 0; + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: { @@ -498,7 +496,7 @@ static long pcipcwd_ioctl(struct file *file, unsigned int cmd, { int new_options, retval = -EINVAL; - if (get_user (new_options, p)) + if (get_user(new_options, p)) return -EFAULT; if (new_options & WDIOS_DISABLECARD) { @@ -600,7 +598,7 @@ static ssize_t pcipcwd_temp_read(struct file *file, char __user *data, if (pcipcwd_get_temperature(&temperature)) return -EFAULT; - if (copy_to_user (data, &temperature, 1)) + if (copy_to_user(data, &temperature, 1)) return -EFAULT; return 1; @@ -625,10 +623,8 @@ static int pcipcwd_temp_release(struct inode *inode, struct file *file) static int pcipcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code==SYS_DOWN || code==SYS_HALT) { - /* Turn the WDT off */ - pcipcwd_stop(); - } + if (code == SYS_DOWN || code == SYS_HALT) + pcipcwd_stop(); /* Turn the WDT off */ return NOTIFY_DONE; } diff --git a/drivers/watchdog/pcwd_usb.c b/drivers/watchdog/pcwd_usb.c index 8c582bc0588e..c1685c942de6 100644 --- a/drivers/watchdog/pcwd_usb.c +++ b/drivers/watchdog/pcwd_usb.c @@ -87,7 +87,7 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" _ #define USB_PCWD_PRODUCT_ID 0x1140 /* table of devices that work with this driver */ -static struct usb_device_id usb_pcwd_table [] = { +static struct usb_device_id usb_pcwd_table[] = { { USB_DEVICE(USB_PCWD_VENDOR_ID, USB_PCWD_PRODUCT_ID) }, { } /* Terminating entry */ }; @@ -109,7 +109,7 @@ MODULE_DEVICE_TABLE (usb, usb_pcwd_table); #define CMD_DISABLE_WATCHDOG CMD_ENABLE_WATCHDOG /* Watchdog's Dip Switch heartbeat values */ -static const int heartbeat_tbl [] = { +static const int heartbeat_tbl[] = { 5, /* OFF-OFF-OFF = 5 Sec */ 10, /* OFF-OFF-ON = 10 Sec */ 30, /* OFF-ON-OFF = 30 Sec */ @@ -129,15 +129,15 @@ static char expect_release; /* Structure to hold all of our device specific stuff */ struct usb_pcwd_private { - struct usb_device * udev; /* save off the usb device pointer */ - struct usb_interface * interface; /* the interface for this device */ + struct usb_device *udev; /* save off the usb device pointer */ + struct usb_interface *interface; /* the interface for this device */ unsigned int interface_number; /* the interface number used for cmd's */ - unsigned char * intr_buffer; /* the buffer to intr data */ + unsigned char *intr_buffer; /* the buffer to intr data */ dma_addr_t intr_dma; /* the dma address for the intr buffer */ size_t intr_size; /* the size of the intr buffer */ - struct urb * intr_urb; /* the urb used for the intr pipe */ + struct urb *intr_urb; /* the urb used for the intr pipe */ unsigned char cmd_command; /* The command that is reported back */ unsigned char cmd_data_msb; /* The data MSB that is reported back */ @@ -153,8 +153,8 @@ static struct usb_pcwd_private *usb_pcwd_device; static DEFINE_MUTEX(disconnect_mutex); /* local function prototypes */ -static int usb_pcwd_probe (struct usb_interface *interface, const struct usb_device_id *id); -static void usb_pcwd_disconnect (struct usb_interface *interface); +static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_device_id *id); +static void usb_pcwd_disconnect(struct usb_interface *interface); /* usb specific object needed to register this driver with the usb subsystem */ static struct usb_driver usb_pcwd_driver = { @@ -194,10 +194,10 @@ static void usb_pcwd_intr_done(struct urb *urb) usb_pcwd->cmd_data_lsb = data[2]; /* notify anyone waiting that the cmd has finished */ - atomic_set (&usb_pcwd->cmd_received, 1); + atomic_set(&usb_pcwd->cmd_received, 1); resubmit: - retval = usb_submit_urb (urb, GFP_ATOMIC); + retval = usb_submit_urb(urb, GFP_ATOMIC); if (retval) printk(KERN_ERR PFX "can't resubmit intr, usb_submit_urb failed with result %d\n", retval); @@ -223,7 +223,7 @@ static int usb_pcwd_send_command(struct usb_pcwd_private *usb_pcwd, unsigned cha dbg("sending following data cmd=0x%02x msb=0x%02x lsb=0x%02x", buf[0], buf[1], buf[2]); - atomic_set (&usb_pcwd->cmd_received, 0); + atomic_set(&usb_pcwd->cmd_received, 0); if (usb_control_msg(usb_pcwd->udev, usb_sndctrlpipe(usb_pcwd->udev, 0), HID_REQ_SET_REPORT, HID_DT_REPORT, @@ -236,7 +236,7 @@ static int usb_pcwd_send_command(struct usb_pcwd_private *usb_pcwd, unsigned cha got_response = 0; for (count = 0; (count < USB_COMMAND_TIMEOUT) && (!got_response); count++) { mdelay(1); - if (atomic_read (&usb_pcwd->cmd_received)) + if (atomic_read(&usb_pcwd->cmd_received)) got_response = 1; } @@ -355,7 +355,7 @@ static ssize_t usb_pcwd_write(struct file *file, const char __user *data, /* scan to see whether or not we got the magic character */ for (i = 0; i != len; i++) { char c; - if(get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_release = 42; @@ -383,8 +383,7 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, - sizeof (ident)) ? -EFAULT : 0; + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: @@ -404,7 +403,7 @@ static long usb_pcwd_ioctl(struct file *file, unsigned int cmd, { int new_options, retval = -EINVAL; - if (get_user (new_options, p)) + if (get_user(new_options, p)) return -EFAULT; if (new_options & WDIOS_DISABLECARD) { @@ -518,10 +517,8 @@ static int usb_pcwd_temperature_release(struct inode *inode, struct file *file) static int usb_pcwd_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code==SYS_DOWN || code==SYS_HALT) { - /* Turn the WDT off */ - usb_pcwd_stop(usb_pcwd_device); - } + if (code == SYS_DOWN || code == SYS_HALT) + usb_pcwd_stop(usb_pcwd_device); /* Turn the WDT off */ return NOTIFY_DONE; } @@ -566,13 +563,13 @@ static struct notifier_block usb_pcwd_notifier = { /** * usb_pcwd_delete */ -static inline void usb_pcwd_delete (struct usb_pcwd_private *usb_pcwd) +static inline void usb_pcwd_delete(struct usb_pcwd_private *usb_pcwd) { usb_free_urb(usb_pcwd->intr_urb); if (usb_pcwd->intr_buffer != NULL) usb_buffer_free(usb_pcwd->udev, usb_pcwd->intr_size, usb_pcwd->intr_buffer, usb_pcwd->intr_dma); - kfree (usb_pcwd); + kfree(usb_pcwd); } /** @@ -625,7 +622,7 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi maxp = usb_maxpacket(udev, pipe, usb_pipeout(pipe)); /* allocate memory for our device and initialize it */ - usb_pcwd = kzalloc (sizeof(struct usb_pcwd_private), GFP_KERNEL); + usb_pcwd = kzalloc(sizeof(struct usb_pcwd_private), GFP_KERNEL); if (usb_pcwd == NULL) { printk(KERN_ERR PFX "Out of memory\n"); goto error; @@ -640,7 +637,8 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi usb_pcwd->intr_size = (le16_to_cpu(endpoint->wMaxPacketSize) > 8 ? le16_to_cpu(endpoint->wMaxPacketSize) : 8); /* set up the memory buffer's */ - if (!(usb_pcwd->intr_buffer = usb_buffer_alloc(udev, usb_pcwd->intr_size, GFP_ATOMIC, &usb_pcwd->intr_dma))) { + usb_pcwd->intr_buffer = usb_buffer_alloc(udev, usb_pcwd->intr_size, GFP_ATOMIC, &usb_pcwd->intr_dma); + if (!usb_pcwd->intr_buffer) { printk(KERN_ERR PFX "Out of memory\n"); goto error; } @@ -674,11 +672,10 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi /* Get the Firmware Version */ got_fw_rev = usb_pcwd_send_command(usb_pcwd, CMD_GET_FIRMWARE_VERSION, &fw_rev_major, &fw_rev_minor); - if (got_fw_rev) { + if (got_fw_rev) sprintf(fw_ver_str, "%u.%02u", fw_rev_major, fw_rev_minor); - } else { + else sprintf(fw_ver_str, ""); - } printk(KERN_INFO PFX "Found card (Firmware: %s) with temp option\n", fw_ver_str); @@ -724,7 +721,7 @@ static int usb_pcwd_probe(struct usb_interface *interface, const struct usb_devi } /* we can register the device now, as it is ready */ - usb_set_intfdata (interface, usb_pcwd); + usb_set_intfdata(interface, usb_pcwd); printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n", heartbeat, nowayout); @@ -758,8 +755,8 @@ static void usb_pcwd_disconnect(struct usb_interface *interface) /* prevent races with open() */ mutex_lock(&disconnect_mutex); - usb_pcwd = usb_get_intfdata (interface); - usb_set_intfdata (interface, NULL); + usb_pcwd = usb_get_intfdata(interface); + usb_set_intfdata(interface, NULL); mutex_lock(&usb_pcwd->mtx); @@ -819,5 +816,5 @@ static void __exit usb_pcwd_exit(void) } -module_init (usb_pcwd_init); -module_exit (usb_pcwd_exit); +module_init(usb_pcwd_init); +module_exit(usb_pcwd_exit); diff --git a/drivers/watchdog/rm9k_wdt.c b/drivers/watchdog/rm9k_wdt.c index c172906b553c..f1ae3729a19e 100644 --- a/drivers/watchdog/rm9k_wdt.c +++ b/drivers/watchdog/rm9k_wdt.c @@ -234,8 +234,8 @@ static int wdt_gpi_release(struct inode *inode, struct file *file) return 0; } -static ssize_t -wdt_gpi_write(struct file *f, const char __user *d, size_t s, loff_t *o) +static ssize_t wdt_gpi_write(struct file *f, const char __user *d, size_t s, + loff_t *o) { char val; @@ -325,8 +325,8 @@ static long wdt_gpi_ioctl(struct file *f, unsigned int cmd, unsigned long arg) /* Shutdown notifier */ -static int -wdt_gpi_notify(struct notifier_block *this, unsigned long code, void *unused) +static int wdt_gpi_notify(struct notifier_block *this, unsigned long code, + void *unused) { if (code == SYS_DOWN || code == SYS_HALT) wdt_gpi_stop(); @@ -336,9 +336,8 @@ wdt_gpi_notify(struct notifier_block *this, unsigned long code, void *unused) /* Init & exit procedures */ -static const struct resource * -wdt_gpi_get_resource(struct platform_device *pdv, const char *name, - unsigned int type) +static const struct resource *wdt_gpi_get_resource(struct platform_device *pdv, + const char *name, unsigned int type) { char buf[80]; if (snprintf(buf, sizeof buf, "%s_0", name) >= sizeof buf) diff --git a/drivers/watchdog/sb_wdog.c b/drivers/watchdog/sb_wdog.c index 528097651f7f..27e526a07c9a 100644 --- a/drivers/watchdog/sb_wdog.c +++ b/drivers/watchdog/sb_wdog.c @@ -215,8 +215,8 @@ static long sbwdog_ioctl(struct file *file, unsigned int cmd, /* * Notifier for system down */ -static int -sbwdog_notify_sys(struct notifier_block *this, unsigned long code, void *erf) +static int sbwdog_notify_sys(struct notifier_block *this, unsigned long code, + void *erf) { if (code == SYS_DOWN || code == SYS_HALT) { /* diff --git a/drivers/watchdog/sbc60xxwdt.c b/drivers/watchdog/sbc60xxwdt.c index e801cd46c647..3266daaaecf8 100644 --- a/drivers/watchdog/sbc60xxwdt.c +++ b/drivers/watchdog/sbc60xxwdt.c @@ -183,7 +183,7 @@ static ssize_t fop_write(struct file *file, const char __user *buf, magic character */ for (ofs = 0; ofs != count; ofs++) { char c; - if (get_user(c, buf+ofs)) + if (get_user(c, buf + ofs)) return -EFAULT; if (c == 'V') wdt_expect_close = 42; @@ -238,7 +238,7 @@ static long fop_ioctl(struct file *file, unsigned int cmd, unsigned long arg) switch (cmd) { case WDIOC_GETSUPPORT: - return copy_to_user(argp, &ident, sizeof(ident))? -EFAULT : 0; + return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; case WDIOC_GETSTATUS: case WDIOC_GETBOOTSTATUS: return put_user(0, p); diff --git a/drivers/watchdog/sc1200wdt.c b/drivers/watchdog/sc1200wdt.c index f3bdc8227cc4..23da3ccd832a 100644 --- a/drivers/watchdog/sc1200wdt.c +++ b/drivers/watchdog/sc1200wdt.c @@ -279,7 +279,7 @@ static ssize_t sc1200wdt_write(struct file *file, const char __user *data, for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; diff --git a/drivers/watchdog/scx200_wdt.c b/drivers/watchdog/scx200_wdt.c index fd5c09446bce..9e19a10a5bb9 100644 --- a/drivers/watchdog/scx200_wdt.c +++ b/drivers/watchdog/scx200_wdt.c @@ -143,7 +143,7 @@ static ssize_t scx200_wdt_write(struct file *file, const char __user *data, expect_close = 0; for (i = 0; i < len; ++i) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; diff --git a/drivers/watchdog/smsc37b787_wdt.c b/drivers/watchdog/smsc37b787_wdt.c index 239383da6d87..988ff1d5b4be 100644 --- a/drivers/watchdog/smsc37b787_wdt.c +++ b/drivers/watchdog/smsc37b787_wdt.c @@ -408,7 +408,7 @@ static ssize_t wb_smsc_wdt_write(struct file *file, const char __user *data, magic character */ for (i = 0; i != len; i++) { char c; - if (get_user(c, data+i)) + if (get_user(c, data + i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -438,7 +438,7 @@ static long wb_smsc_wdt_ioctl(struct file *file, WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE, .firmware_version = 0, - .identity = "SMsC 37B787 Watchdog" + .identity = "SMsC 37B787 Watchdog", }; uarg.i = (int __user *)arg; diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index 8382f9a9534b..dbbc018a5f46 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c @@ -190,7 +190,7 @@ static struct miscdevice txx9wdt_miscdev = { }; static struct notifier_block txx9wdt_notifier = { - .notifier_call = txx9wdt_notify_sys + .notifier_call = txx9wdt_notify_sys, }; static int __init txx9wdt_probe(struct platform_device *dev) diff --git a/drivers/watchdog/w83627hf_wdt.c b/drivers/watchdog/w83627hf_wdt.c index 59507f609996..69396adaa5c3 100644 --- a/drivers/watchdog/w83627hf_wdt.c +++ b/drivers/watchdog/w83627hf_wdt.c @@ -180,7 +180,7 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, for (i = 0; i != count; i++) { char c; - if (get_user(c, buf+i)) + if (get_user(c, buf + i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -278,10 +278,9 @@ static int wdt_close(struct inode *inode, struct file *file) static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Turn the WDT off */ - wdt_disable(); - } + if (code == SYS_DOWN || code == SYS_HALT) + wdt_disable(); /* Turn the WDT off */ + return NOTIFY_DONE; } diff --git a/drivers/watchdog/w83697hf_wdt.c b/drivers/watchdog/w83697hf_wdt.c index 12bd6618ed5e..445d30a01ed3 100644 --- a/drivers/watchdog/w83697hf_wdt.c +++ b/drivers/watchdog/w83697hf_wdt.c @@ -218,7 +218,7 @@ static ssize_t wdt_write(struct file *file, const char __user *buf, for (i = 0; i != count; i++) { char c; - if (get_user(c, buf+i)) + if (get_user(c, buf + i)) return -EFAULT; if (c == 'V') expect_close = 42; @@ -325,10 +325,9 @@ static int wdt_close(struct inode *inode, struct file *file) static int wdt_notify_sys(struct notifier_block *this, unsigned long code, void *unused) { - if (code == SYS_DOWN || code == SYS_HALT) { - /* Turn the WDT off */ - wdt_disable(); - } + if (code == SYS_DOWN || code == SYS_HALT) + wdt_disable(); /* Turn the WDT off */ + return NOTIFY_DONE; } @@ -414,7 +413,7 @@ static int __init wdt_init(void) w83697hf_init(); if (early_disable) { if (wdt_running()) - printk (KERN_WARNING PFX "Stopping previously enabled watchdog until userland kicks in\n"); + printk(KERN_WARNING PFX "Stopping previously enabled watchdog until userland kicks in\n"); wdt_disable(); } diff --git a/drivers/watchdog/wafer5823wdt.c b/drivers/watchdog/wafer5823wdt.c index 44e81f7d4322..68377ae171ff 100644 --- a/drivers/watchdog/wafer5823wdt.c +++ b/drivers/watchdog/wafer5823wdt.c @@ -1,11 +1,11 @@ /* * ICP Wafer 5823 Single Board Computer WDT driver - * http://www.icpamerica.com/wafer_5823.php - * May also work on other similar models + * http://www.icpamerica.com/wafer_5823.php + * May also work on other similar models * * (c) Copyright 2002 Justin Cormack * - * Release 0.02 + * Release 0.02 * * Based on advantechwdt.c which is based on wdt.c. * Original copyright messages: @@ -50,10 +50,10 @@ static DEFINE_SPINLOCK(wafwdt_lock); /* * You must set these - there is no sane way to probe for this board. * - * To enable, write the timeout value in seconds (1 to 255) to I/O - * port WDT_START, then read the port to start the watchdog. To pat - * the dog, read port WDT_STOP to stop the timer, then read WDT_START - * to restart it again. + * To enable, write the timeout value in seconds (1 to 255) to I/O + * port WDT_START, then read the port to start the watchdog. To pat + * the dog, read port WDT_STOP to stop the timer, then read WDT_START + * to restart it again. */ static int wdt_stop = 0x843; @@ -87,8 +87,7 @@ static void wafwdt_start(void) inb_p(wdt_start); } -static void -wafwdt_stop(void) +static void wafwdt_stop(void) { /* stop watchdog */ inb_p(wdt_stop); @@ -199,8 +198,7 @@ static int wafwdt_open(struct inode *inode, struct file *file) return nonseekable_open(inode, file); } -static int -wafwdt_close(struct inode *inode, struct file *file) +static int wafwdt_close(struct inode *inode, struct file *file) { if (expect_close == 42) wafwdt_stop(); diff --git a/drivers/watchdog/wd501p.h b/drivers/watchdog/wd501p.h index a4504f40394d..db34853c28ae 100644 --- a/drivers/watchdog/wd501p.h +++ b/drivers/watchdog/wd501p.h @@ -12,7 +12,7 @@ * http://www.cymru.net * * This driver is provided under the GNU General Public License, incorporated - * herein by reference. The driver is provided without warranty or + * herein by reference. The driver is provided without warranty or * support. * * Release 0.04. diff --git a/drivers/watchdog/wdrtas.c b/drivers/watchdog/wdrtas.c index 20fd6715f25f..5d3b1a8e28b0 100644 --- a/drivers/watchdog/wdrtas.c +++ b/drivers/watchdog/wdrtas.c @@ -313,7 +313,7 @@ static long wdrtas_ioctl(struct file *file, unsigned int cmd, static struct watchdog_info wdinfo = { .options = WDRTAS_SUPPORTED_MASK, .firmware_version = 0, - .identity = "wdrtas" + .identity = "wdrtas", }; switch (cmd) { diff --git a/drivers/watchdog/wdt_pci.c b/drivers/watchdog/wdt_pci.c index fb8fc0144852..ed02bdb38c09 100644 --- a/drivers/watchdog/wdt_pci.c +++ b/drivers/watchdog/wdt_pci.c @@ -381,7 +381,7 @@ static ssize_t wdtpci_write(struct file *file, const char __user *buf, for (i = 0; i != count; i++) { char c; - if (get_user(c, buf+i)) + if (get_user(c, buf + i)) return -EFAULT; if (c == 'V') expect_close = 42; -- cgit v1.2.3 From 970a8a513c30a1c3e8995609a153658a34bc02bf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 6 Aug 2008 22:19:39 +0200 Subject: m68k/amiserial: fix fallout of tty break handling rework commit 9e98966c7bb94355689478bc84cc3e0c190f977e (tty: rework break handling) forgot to update one exit point of rs_break() in the Amiga serial driver. Signed-off-by: Geert Uytterhoeven Signed-off-by: Linus Torvalds --- drivers/char/amiserial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/char/amiserial.c b/drivers/char/amiserial.c index 3530ff417a51..6e763e3f5a81 100644 --- a/drivers/char/amiserial.c +++ b/drivers/char/amiserial.c @@ -1254,7 +1254,7 @@ static int rs_break(struct tty_struct *tty, int break_state) unsigned long flags; if (serial_paranoia_check(info, tty->name, "rs_break")) - return; + return -EINVAL; local_irq_save(flags); if (break_state == -1) -- cgit v1.2.3 From 73ce48f6c6b9d9dcf6a2bba0bcde39ede76809f0 Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Wed, 6 Aug 2008 22:41:03 +0200 Subject: hwmon: (dme1737) Cleanups Fix names of attribute structs to make them more consistent with the rest of the code. Minor comment changes. Signed-off-by: Juerg Haefliger Signed-off-by: Jean Delvare --- drivers/hwmon/dme1737.c | 94 ++++++++++++++++++++++++------------------------- 1 file changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c index 5e2cf0aef480..9635fa6014fc 100644 --- a/drivers/hwmon/dme1737.c +++ b/drivers/hwmon/dme1737.c @@ -1166,7 +1166,7 @@ static ssize_t show_pwm(struct device *dev, struct device_attribute *attr, return sprintf(buf, "%d\n", res); } -static struct attribute *dme1737_attr_pwm[]; +static struct attribute *dme1737_pwm_chmod_attr[]; static void dme1737_chmod_file(struct device*, struct attribute*, mode_t); static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, @@ -1230,7 +1230,7 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, switch (val) { case 0: /* Change permissions of pwm[ix] to read-only */ - dme1737_chmod_file(dev, dme1737_attr_pwm[ix], + dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], S_IRUGO); /* Turn fan fully on */ data->pwm_config[ix] = PWM_EN_TO_REG(0, @@ -1245,12 +1245,12 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, dme1737_write(client, DME1737_REG_PWM_CONFIG(ix), data->pwm_config[ix]); /* Change permissions of pwm[ix] to read-writeable */ - dme1737_chmod_file(dev, dme1737_attr_pwm[ix], + dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], S_IRUGO | S_IWUSR); break; case 2: /* Change permissions of pwm[ix] to read-only */ - dme1737_chmod_file(dev, dme1737_attr_pwm[ix], + dme1737_chmod_file(dev, dme1737_pwm_chmod_attr[ix], S_IRUGO); /* Turn on auto mode using the saved zone channel * assignment */ @@ -1612,7 +1612,7 @@ static const struct attribute_group dme1737_group = { /* The following structs hold the PWM attributes, some of which are optional. * Their creation depends on the chip configuration which is determined during * module load. */ -static struct attribute *dme1737_attr_pwm1[] = { +static struct attribute *dme1737_pwm1_attr[] = { &sensor_dev_attr_pwm1.dev_attr.attr, &sensor_dev_attr_pwm1_freq.dev_attr.attr, &sensor_dev_attr_pwm1_enable.dev_attr.attr, @@ -1623,7 +1623,7 @@ static struct attribute *dme1737_attr_pwm1[] = { &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm2[] = { +static struct attribute *dme1737_pwm2_attr[] = { &sensor_dev_attr_pwm2.dev_attr.attr, &sensor_dev_attr_pwm2_freq.dev_attr.attr, &sensor_dev_attr_pwm2_enable.dev_attr.attr, @@ -1634,7 +1634,7 @@ static struct attribute *dme1737_attr_pwm2[] = { &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm3[] = { +static struct attribute *dme1737_pwm3_attr[] = { &sensor_dev_attr_pwm3.dev_attr.attr, &sensor_dev_attr_pwm3_freq.dev_attr.attr, &sensor_dev_attr_pwm3_enable.dev_attr.attr, @@ -1645,13 +1645,13 @@ static struct attribute *dme1737_attr_pwm3[] = { &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm5[] = { +static struct attribute *dme1737_pwm5_attr[] = { &sensor_dev_attr_pwm5.dev_attr.attr, &sensor_dev_attr_pwm5_freq.dev_attr.attr, &sensor_dev_attr_pwm5_enable.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm6[] = { +static struct attribute *dme1737_pwm6_attr[] = { &sensor_dev_attr_pwm6.dev_attr.attr, &sensor_dev_attr_pwm6_freq.dev_attr.attr, &sensor_dev_attr_pwm6_enable.dev_attr.attr, @@ -1659,53 +1659,53 @@ static struct attribute *dme1737_attr_pwm6[] = { }; static const struct attribute_group dme1737_pwm_group[] = { - { .attrs = dme1737_attr_pwm1 }, - { .attrs = dme1737_attr_pwm2 }, - { .attrs = dme1737_attr_pwm3 }, + { .attrs = dme1737_pwm1_attr }, + { .attrs = dme1737_pwm2_attr }, + { .attrs = dme1737_pwm3_attr }, { .attrs = NULL }, - { .attrs = dme1737_attr_pwm5 }, - { .attrs = dme1737_attr_pwm6 }, + { .attrs = dme1737_pwm5_attr }, + { .attrs = dme1737_pwm6_attr }, }; /* The following structs hold the fan attributes, some of which are optional. * Their creation depends on the chip configuration which is determined during * module load. */ -static struct attribute *dme1737_attr_fan1[] = { +static struct attribute *dme1737_fan1_attr[] = { &sensor_dev_attr_fan1_input.dev_attr.attr, &sensor_dev_attr_fan1_min.dev_attr.attr, &sensor_dev_attr_fan1_alarm.dev_attr.attr, &sensor_dev_attr_fan1_type.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_fan2[] = { +static struct attribute *dme1737_fan2_attr[] = { &sensor_dev_attr_fan2_input.dev_attr.attr, &sensor_dev_attr_fan2_min.dev_attr.attr, &sensor_dev_attr_fan2_alarm.dev_attr.attr, &sensor_dev_attr_fan2_type.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_fan3[] = { +static struct attribute *dme1737_fan3_attr[] = { &sensor_dev_attr_fan3_input.dev_attr.attr, &sensor_dev_attr_fan3_min.dev_attr.attr, &sensor_dev_attr_fan3_alarm.dev_attr.attr, &sensor_dev_attr_fan3_type.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_fan4[] = { +static struct attribute *dme1737_fan4_attr[] = { &sensor_dev_attr_fan4_input.dev_attr.attr, &sensor_dev_attr_fan4_min.dev_attr.attr, &sensor_dev_attr_fan4_alarm.dev_attr.attr, &sensor_dev_attr_fan4_type.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_fan5[] = { +static struct attribute *dme1737_fan5_attr[] = { &sensor_dev_attr_fan5_input.dev_attr.attr, &sensor_dev_attr_fan5_min.dev_attr.attr, &sensor_dev_attr_fan5_alarm.dev_attr.attr, &sensor_dev_attr_fan5_max.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_fan6[] = { +static struct attribute *dme1737_fan6_attr[] = { &sensor_dev_attr_fan6_input.dev_attr.attr, &sensor_dev_attr_fan6_min.dev_attr.attr, &sensor_dev_attr_fan6_alarm.dev_attr.attr, @@ -1714,17 +1714,17 @@ static struct attribute *dme1737_attr_fan6[] = { }; static const struct attribute_group dme1737_fan_group[] = { - { .attrs = dme1737_attr_fan1 }, - { .attrs = dme1737_attr_fan2 }, - { .attrs = dme1737_attr_fan3 }, - { .attrs = dme1737_attr_fan4 }, - { .attrs = dme1737_attr_fan5 }, - { .attrs = dme1737_attr_fan6 }, + { .attrs = dme1737_fan1_attr }, + { .attrs = dme1737_fan2_attr }, + { .attrs = dme1737_fan3_attr }, + { .attrs = dme1737_fan4_attr }, + { .attrs = dme1737_fan5_attr }, + { .attrs = dme1737_fan6_attr }, }; /* The permissions of all of the following attributes are changed to read- * writeable if the chip is *not* locked. Otherwise they stay read-only. */ -static struct attribute *dme1737_attr_lock[] = { +static struct attribute *dme1737_misc_chmod_attr[] = { /* Temperatures */ &sensor_dev_attr_temp1_offset.dev_attr.attr, &sensor_dev_attr_temp2_offset.dev_attr.attr, @@ -1745,14 +1745,14 @@ static struct attribute *dme1737_attr_lock[] = { NULL }; -static const struct attribute_group dme1737_lock_group = { - .attrs = dme1737_attr_lock, +static const struct attribute_group dme1737_misc_chmod_group = { + .attrs = dme1737_misc_chmod_attr, }; /* The permissions of the following PWM attributes are changed to read- * writeable if the chip is *not* locked and the respective PWM is available. * Otherwise they stay read-only. */ -static struct attribute *dme1737_attr_pwm1_lock[] = { +static struct attribute *dme1737_pwm1_chmod_attr[] = { &sensor_dev_attr_pwm1_freq.dev_attr.attr, &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, @@ -1761,7 +1761,7 @@ static struct attribute *dme1737_attr_pwm1_lock[] = { &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm2_lock[] = { +static struct attribute *dme1737_pwm2_chmod_attr[] = { &sensor_dev_attr_pwm2_freq.dev_attr.attr, &sensor_dev_attr_pwm2_enable.dev_attr.attr, &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, @@ -1770,7 +1770,7 @@ static struct attribute *dme1737_attr_pwm2_lock[] = { &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm3_lock[] = { +static struct attribute *dme1737_pwm3_chmod_attr[] = { &sensor_dev_attr_pwm3_freq.dev_attr.attr, &sensor_dev_attr_pwm3_enable.dev_attr.attr, &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, @@ -1779,29 +1779,29 @@ static struct attribute *dme1737_attr_pwm3_lock[] = { &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm5_lock[] = { +static struct attribute *dme1737_pwm5_chmod_attr[] = { &sensor_dev_attr_pwm5.dev_attr.attr, &sensor_dev_attr_pwm5_freq.dev_attr.attr, NULL }; -static struct attribute *dme1737_attr_pwm6_lock[] = { +static struct attribute *dme1737_pwm6_chmod_attr[] = { &sensor_dev_attr_pwm6.dev_attr.attr, &sensor_dev_attr_pwm6_freq.dev_attr.attr, NULL }; -static const struct attribute_group dme1737_pwm_lock_group[] = { - { .attrs = dme1737_attr_pwm1_lock }, - { .attrs = dme1737_attr_pwm2_lock }, - { .attrs = dme1737_attr_pwm3_lock }, +static const struct attribute_group dme1737_pwm_chmod_group[] = { + { .attrs = dme1737_pwm1_chmod_attr }, + { .attrs = dme1737_pwm2_chmod_attr }, + { .attrs = dme1737_pwm3_chmod_attr }, { .attrs = NULL }, - { .attrs = dme1737_attr_pwm5_lock }, - { .attrs = dme1737_attr_pwm6_lock }, + { .attrs = dme1737_pwm5_chmod_attr }, + { .attrs = dme1737_pwm6_chmod_attr }, }; /* Pwm[1-3] are read-writeable if the associated pwm is in manual mode and the * chip is not locked. Otherwise they are read-only. */ -static struct attribute *dme1737_attr_pwm[] = { +static struct attribute *dme1737_pwm_chmod_attr[] = { &sensor_dev_attr_pwm1.dev_attr.attr, &sensor_dev_attr_pwm2.dev_attr.attr, &sensor_dev_attr_pwm3.dev_attr.attr, @@ -1927,15 +1927,15 @@ static int dme1737_create_files(struct device *dev) dev_info(dev, "Device is locked. Some attributes " "will be read-only.\n"); } else { - /* Change permissions of standard attributes */ - dme1737_chmod_group(dev, &dme1737_lock_group, + /* Change permissions of standard sysfs attributes */ + dme1737_chmod_group(dev, &dme1737_misc_chmod_group, S_IRUGO | S_IWUSR); - /* Change permissions of PWM attributes */ - for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_lock_group); ix++) { + /* Change permissions of PWM sysfs attributes */ + for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { if (data->has_pwm & (1 << ix)) { dme1737_chmod_group(dev, - &dme1737_pwm_lock_group[ix], + &dme1737_pwm_chmod_group[ix], S_IRUGO | S_IWUSR); } } @@ -1945,7 +1945,7 @@ static int dme1737_create_files(struct device *dev) if ((data->has_pwm & (1 << ix)) && (PWM_EN_FROM_REG(data->pwm_config[ix]) == 1)) { dme1737_chmod_file(dev, - dme1737_attr_pwm[ix], + dme1737_pwm_chmod_attr[ix], S_IRUGO | S_IWUSR); } } -- cgit v1.2.3 From 55d68d75ab00e60953f8784af5927b60967a297f Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Wed, 6 Aug 2008 22:41:03 +0200 Subject: hwmon: (dme1737) Skip detection if forced Skip the checking of the device ID register in the hwmon register block if the force_id option is used. Signed-off-by: Juerg Haefliger Signed-off-by: Jean Delvare --- drivers/hwmon/dme1737.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c index 9635fa6014fc..b36290048b98 100644 --- a/drivers/hwmon/dme1737.c +++ b/drivers/hwmon/dme1737.c @@ -2360,13 +2360,16 @@ static int __devinit dme1737_isa_probe(struct platform_device *pdev) client->addr = res->start; platform_set_drvdata(pdev, data); - company = dme1737_read(client, DME1737_REG_COMPANY); - device = dme1737_read(client, DME1737_REG_DEVICE); + /* Skip chip detection if module is loaded with force_id parameter */ + if (!force_id) { + company = dme1737_read(client, DME1737_REG_COMPANY); + device = dme1737_read(client, DME1737_REG_DEVICE); - if (!((company == DME1737_COMPANY_SMSC) && - (device == SCH311X_DEVICE))) { - err = -ENODEV; - goto exit_kfree; + if (!((company == DME1737_COMPANY_SMSC) && + (device == SCH311X_DEVICE))) { + err = -ENODEV; + goto exit_kfree; + } } data->type = -1; -- cgit v1.2.3 From 549edb83327f2a5027a22d65b10603b01dc40175 Mon Sep 17 00:00:00 2001 From: Juerg Haefliger Date: Wed, 6 Aug 2008 22:41:03 +0200 Subject: hwmon: (dme1737) Add support for the SMSC SCH5027 Add support for the SCH5027. The differences to the DME1737 are: - No support for programmable temp offsets - In auto mode, PWM outputs stay on min value if temp goes below low threshold and can't be programmed to fully turn off - Different voltage scaling - No VID input Signed-off-by: Juerg Haefliger Signed-off-by: Jean Delvare --- Documentation/hwmon/dme1737 | 53 ++++++++---- drivers/hwmon/Kconfig | 4 +- drivers/hwmon/dme1737.c | 193 +++++++++++++++++++++++++++++--------------- 3 files changed, 169 insertions(+), 81 deletions(-) diff --git a/Documentation/hwmon/dme1737 b/Documentation/hwmon/dme1737 index b1fe00999439..001d2e70bc11 100644 --- a/Documentation/hwmon/dme1737 +++ b/Documentation/hwmon/dme1737 @@ -10,6 +10,10 @@ Supported chips: Prefix: 'sch311x' Addresses scanned: none, address read from Super-I/O config space Datasheet: http://www.nuhorizons.com/FeaturedProducts/Volume1/SMSC/311x.pdf + * SMSC SCH5027 + Prefix: 'sch5027' + Addresses scanned: I2C 0x2c, 0x2d, 0x2e + Datasheet: Provided by SMSC upon request and under NDA Authors: Juerg Haefliger @@ -27,33 +31,31 @@ Module Parameters following boards: - VIA EPIA SN18000 -Note that there is no need to use this parameter if the driver loads without -complaining. The driver will say so if it is necessary. - Description ----------- This driver implements support for the hardware monitoring capabilities of the -SMSC DME1737 and Asus A8000 (which are the same) and SMSC SCH311x Super-I/O -chips. These chips feature monitoring of 3 temp sensors temp[1-3] (2 remote -diodes and 1 internal), 7 voltages in[0-6] (6 external and 1 internal) and up -to 6 fan speeds fan[1-6]. Additionally, the chips implement up to 5 PWM -outputs pwm[1-3,5-6] for controlling fan speeds both manually and +SMSC DME1737 and Asus A8000 (which are the same), SMSC SCH5027, and SMSC +SCH311x Super-I/O chips. These chips feature monitoring of 3 temp sensors +temp[1-3] (2 remote diodes and 1 internal), 7 voltages in[0-6] (6 external and +1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement +up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and automatically. -For the DME1737 and A8000, fan[1-2] and pwm[1-2] are always present. Fan[3-6] -and pwm[3,5-6] are optional features and their availability depends on the -configuration of the chip. The driver will detect which features are present -during initialization and create the sysfs attributes accordingly. +For the DME1737, A8000 and SCH5027, fan[1-2] and pwm[1-2] are always present. +Fan[3-6] and pwm[3,5-6] are optional features and their availability depends on +the configuration of the chip. The driver will detect which features are +present during initialization and create the sysfs attributes accordingly. For the SCH311x, fan[1-3] and pwm[1-3] are always present and fan[4-6] and pwm[5-6] don't exist. -The hardware monitoring features of the DME1737 and A8000 are only accessible -via SMBus, while the SCH311x only provides access via the ISA bus. The driver -will therefore register itself as an I2C client driver if it detects a DME1737 -or A8000 and as a platform driver if it detects a SCH311x chip. +The hardware monitoring features of the DME1737, A8000, and SCH5027 are only +accessible via SMBus, while the SCH311x only provides access via the ISA bus. +The driver will therefore register itself as an I2C client driver if it detects +a DME1737, A8000, or SCH5027 and as a platform driver if it detects a SCH311x +chip. Voltage Monitoring @@ -64,6 +66,7 @@ scaling resistors. The values returned by the driver therefore reflect true millivolts and don't need scaling. The voltage inputs are mapped as follows (the last column indicates the input ranges): +DME1737, A8000: in0: +5VTR (+5V standby) 0V - 6.64V in1: Vccp (processor core) 0V - 3V in2: VCC (internal +3.3V) 0V - 4.38V @@ -72,6 +75,24 @@ millivolts and don't need scaling. The voltage inputs are mapped as follows in5: VTR (+3.3V standby) 0V - 4.38V in6: Vbat (+3.0V) 0V - 4.38V +SCH311x: + in0: +2.5V 0V - 6.64V + in1: Vccp (processor core) 0V - 2V + in2: VCC (internal +3.3V) 0V - 4.38V + in3: +5V 0V - 6.64V + in4: +12V 0V - 16V + in5: VTR (+3.3V standby) 0V - 4.38V + in6: Vbat (+3.0V) 0V - 4.38V + +SCH5027: + in0: +5VTR (+5V standby) 0V - 6.64V + in1: Vccp (processor core) 0V - 3V + in2: VCC (internal +3.3V) 0V - 4.38V + in3: V2_IN 0V - 1.5V + in4: V1_IN 0V - 1.5V + in5: VTR (+3.3V standby) 0V - 4.38V + in6: Vbat (+3.0V) 0V - 4.38V + Each voltage input has associated min and max limits which trigger an alarm when crossed. diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index c882fd05cf29..1de240a26fc5 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -575,8 +575,8 @@ config SENSORS_DME1737 select HWMON_VID help If you say yes here you get support for the hardware monitoring - and fan control features of the SMSC DME1737 (and compatibles - like the Asus A8000) and SCH311x Super-I/O chips. + and fan control features of the SMSC DME1737, SCH311x, SCH5027, and + Asus A8000 Super-I/O chips. This driver can also be built as a module. If so, the module will be called dme1737. diff --git a/drivers/hwmon/dme1737.c b/drivers/hwmon/dme1737.c index b36290048b98..cdb8311e4ef7 100644 --- a/drivers/hwmon/dme1737.c +++ b/drivers/hwmon/dme1737.c @@ -1,11 +1,11 @@ /* - * dme1737.c - Driver for the SMSC DME1737, Asus A8000, and SMSC SCH311x - * Super-I/O chips integrated hardware monitoring features. - * Copyright (c) 2007 Juerg Haefliger + * dme1737.c - Driver for the SMSC DME1737, Asus A8000, SMSC SCH311x and + * SCH5027 Super-I/O chips integrated hardware monitoring features. + * Copyright (c) 2007, 2008 Juerg Haefliger * * This driver is an I2C/ISA hybrid, meaning that it uses the I2C bus to access - * the chip registers if a DME1737 (or A8000) is found and the ISA bus if a - * SCH311x chip is found. Both types of chips have very similar hardware + * the chip registers if a DME1737, A8000, or SCH5027 is found and the ISA bus + * if a SCH311x chip is found. Both types of chips have very similar hardware * monitoring capabilities but differ in the way they can be accessed. * * This program is free software; you can redistribute it and/or modify @@ -57,7 +57,10 @@ MODULE_PARM_DESC(probe_all_addr, "Include probing of non-standard LPC " static const unsigned short normal_i2c[] = {0x2c, 0x2d, 0x2e, I2C_CLIENT_END}; /* Insmod parameters */ -I2C_CLIENT_INSMOD_1(dme1737); +I2C_CLIENT_INSMOD_2(dme1737, sch5027); + +/* ISA chip types */ +enum isa_chips { sch311x = sch5027 + 1 }; /* --------------------------------------------------------------------- * Registers @@ -163,6 +166,7 @@ static const u8 DME1737_BIT_ALARM_FAN[] = {10, 11, 12, 13, 22, 23}; #define DME1737_VERSTEP 0x88 #define DME1737_VERSTEP_MASK 0xf8 #define SCH311X_DEVICE 0x8c +#define SCH5027_VERSTEP 0x69 /* Length of ISA address segment */ #define DME1737_EXTENT 2 @@ -182,6 +186,7 @@ struct dme1737_data { unsigned long last_update; /* in jiffies */ unsigned long last_vbat; /* in jiffies */ enum chips type; + const int *in_nominal; /* pointer to IN_NOMINAL array */ u8 vid; u8 pwm_rr_en; @@ -220,23 +225,23 @@ static const int IN_NOMINAL_DME1737[] = {5000, 2250, 3300, 5000, 12000, 3300, 3300}; static const int IN_NOMINAL_SCH311x[] = {2500, 1500, 3300, 5000, 12000, 3300, 3300}; -#define IN_NOMINAL(ix, type) (((type) == dme1737) ? \ - IN_NOMINAL_DME1737[(ix)] : \ - IN_NOMINAL_SCH311x[(ix)]) +static const int IN_NOMINAL_SCH5027[] = {5000, 2250, 3300, 1125, 1125, 3300, + 3300}; +#define IN_NOMINAL(type) ((type) == sch311x ? IN_NOMINAL_SCH311x : \ + (type) == sch5027 ? IN_NOMINAL_SCH5027 : \ + IN_NOMINAL_DME1737) /* Voltage input * Voltage inputs have 16 bits resolution, limit values have 8 bits * resolution. */ -static inline int IN_FROM_REG(int reg, int ix, int res, int type) +static inline int IN_FROM_REG(int reg, int nominal, int res) { - return (reg * IN_NOMINAL(ix, type) + (3 << (res - 3))) / - (3 << (res - 2)); + return (reg * nominal + (3 << (res - 3))) / (3 << (res - 2)); } -static inline int IN_TO_REG(int val, int ix, int type) +static inline int IN_TO_REG(int val, int nominal) { - return SENSORS_LIMIT((val * 192 + IN_NOMINAL(ix, type) / 2) / - IN_NOMINAL(ix, type), 0, 255); + return SENSORS_LIMIT((val * 192 + nominal / 2) / nominal, 0, 255); } /* Temperature input @@ -565,7 +570,10 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) /* Sample register contents every 1 sec */ if (time_after(jiffies, data->last_update + HZ) || !data->valid) { - data->vid = dme1737_read(client, DME1737_REG_VID) & 0x3f; + if (data->type != sch5027) { + data->vid = dme1737_read(client, DME1737_REG_VID) & + 0x3f; + } /* In (voltage) registers */ for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { @@ -593,8 +601,10 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) DME1737_REG_TEMP_MIN(ix)); data->temp_max[ix] = dme1737_read(client, DME1737_REG_TEMP_MAX(ix)); - data->temp_offset[ix] = dme1737_read(client, - DME1737_REG_TEMP_OFFSET(ix)); + if (data->type != sch5027) { + data->temp_offset[ix] = dme1737_read(client, + DME1737_REG_TEMP_OFFSET(ix)); + } } /* In and temp LSB registers @@ -669,9 +679,11 @@ static struct dme1737_data *dme1737_update_device(struct device *dev) data->zone_abs[ix] = dme1737_read(client, DME1737_REG_ZONE_ABS(ix)); } - for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { - data->zone_hyst[ix] = dme1737_read(client, + if (data->type != sch5027) { + for (ix = 0; ix < ARRAY_SIZE(data->zone_hyst); ix++) { + data->zone_hyst[ix] = dme1737_read(client, DME1737_REG_ZONE_HYST(ix)); + } } /* Alarm registers */ @@ -735,13 +747,13 @@ static ssize_t show_in(struct device *dev, struct device_attribute *attr, switch (fn) { case SYS_IN_INPUT: - res = IN_FROM_REG(data->in[ix], ix, 16, data->type); + res = IN_FROM_REG(data->in[ix], data->in_nominal[ix], 16); break; case SYS_IN_MIN: - res = IN_FROM_REG(data->in_min[ix], ix, 8, data->type); + res = IN_FROM_REG(data->in_min[ix], data->in_nominal[ix], 8); break; case SYS_IN_MAX: - res = IN_FROM_REG(data->in_max[ix], ix, 8, data->type); + res = IN_FROM_REG(data->in_max[ix], data->in_nominal[ix], 8); break; case SYS_IN_ALARM: res = (data->alarms >> DME1737_BIT_ALARM_IN[ix]) & 0x01; @@ -768,12 +780,12 @@ static ssize_t set_in(struct device *dev, struct device_attribute *attr, mutex_lock(&data->update_lock); switch (fn) { case SYS_IN_MIN: - data->in_min[ix] = IN_TO_REG(val, ix, data->type); + data->in_min[ix] = IN_TO_REG(val, data->in_nominal[ix]); dme1737_write(client, DME1737_REG_IN_MIN(ix), data->in_min[ix]); break; case SYS_IN_MAX: - data->in_max[ix] = IN_TO_REG(val, ix, data->type); + data->in_max[ix] = IN_TO_REG(val, data->in_nominal[ix]); dme1737_write(client, DME1737_REG_IN_MAX(ix), data->in_max[ix]); break; @@ -1570,43 +1582,56 @@ static struct attribute *dme1737_attr[] ={ &sensor_dev_attr_temp1_max.dev_attr.attr, &sensor_dev_attr_temp1_alarm.dev_attr.attr, &sensor_dev_attr_temp1_fault.dev_attr.attr, - &sensor_dev_attr_temp1_offset.dev_attr.attr, &sensor_dev_attr_temp2_input.dev_attr.attr, &sensor_dev_attr_temp2_min.dev_attr.attr, &sensor_dev_attr_temp2_max.dev_attr.attr, &sensor_dev_attr_temp2_alarm.dev_attr.attr, &sensor_dev_attr_temp2_fault.dev_attr.attr, - &sensor_dev_attr_temp2_offset.dev_attr.attr, &sensor_dev_attr_temp3_input.dev_attr.attr, &sensor_dev_attr_temp3_min.dev_attr.attr, &sensor_dev_attr_temp3_max.dev_attr.attr, &sensor_dev_attr_temp3_alarm.dev_attr.attr, &sensor_dev_attr_temp3_fault.dev_attr.attr, - &sensor_dev_attr_temp3_offset.dev_attr.attr, /* Zones */ - &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, &sensor_dev_attr_zone1_auto_channels_temp.dev_attr.attr, - &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, &sensor_dev_attr_zone2_auto_channels_temp.dev_attr.attr, - &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, &sensor_dev_attr_zone3_auto_channels_temp.dev_attr.attr, + NULL +}; + +static const struct attribute_group dme1737_group = { + .attrs = dme1737_attr, +}; + +/* The following struct holds misc attributes, which are not available in all + * chips. Their creation depends on the chip type which is determined during + * module load. */ +static struct attribute *dme1737_misc_attr[] = { + /* Temperatures */ + &sensor_dev_attr_temp1_offset.dev_attr.attr, + &sensor_dev_attr_temp2_offset.dev_attr.attr, + &sensor_dev_attr_temp3_offset.dev_attr.attr, + /* Zones */ + &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, + &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, + &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, /* Misc */ &dev_attr_vrm.attr, &dev_attr_cpu0_vid.attr, NULL }; -static const struct attribute_group dme1737_group = { - .attrs = dme1737_attr, +static const struct attribute_group dme1737_misc_group = { + .attrs = dme1737_misc_attr, }; /* The following structs hold the PWM attributes, some of which are optional. @@ -1618,7 +1643,6 @@ static struct attribute *dme1737_pwm1_attr[] = { &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr, NULL @@ -1629,7 +1653,6 @@ static struct attribute *dme1737_pwm2_attr[] = { &sensor_dev_attr_pwm2_enable.dev_attr.attr, &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr, NULL @@ -1640,7 +1663,6 @@ static struct attribute *dme1737_pwm3_attr[] = { &sensor_dev_attr_pwm3_enable.dev_attr.attr, &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr, NULL @@ -1667,6 +1689,15 @@ static const struct attribute_group dme1737_pwm_group[] = { { .attrs = dme1737_pwm6_attr }, }; +/* The following struct holds misc PWM attributes, which are not available in + * all chips. Their creation depends on the chip type which is determined + * during module load. */ +static struct attribute *dme1737_pwm_misc_attr[] = { + &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, + &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, + &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, +}; + /* The following structs hold the fan attributes, some of which are optional. * Their creation depends on the chip configuration which is determined during * module load. */ @@ -1722,31 +1753,23 @@ static const struct attribute_group dme1737_fan_group[] = { { .attrs = dme1737_fan6_attr }, }; -/* The permissions of all of the following attributes are changed to read- +/* The permissions of the following zone attributes are changed to read- * writeable if the chip is *not* locked. Otherwise they stay read-only. */ -static struct attribute *dme1737_misc_chmod_attr[] = { - /* Temperatures */ - &sensor_dev_attr_temp1_offset.dev_attr.attr, - &sensor_dev_attr_temp2_offset.dev_attr.attr, - &sensor_dev_attr_temp3_offset.dev_attr.attr, - /* Zones */ - &sensor_dev_attr_zone1_auto_point1_temp_hyst.dev_attr.attr, +static struct attribute *dme1737_zone_chmod_attr[] = { &sensor_dev_attr_zone1_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone1_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone1_auto_point3_temp.dev_attr.attr, - &sensor_dev_attr_zone2_auto_point1_temp_hyst.dev_attr.attr, &sensor_dev_attr_zone2_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone2_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone2_auto_point3_temp.dev_attr.attr, - &sensor_dev_attr_zone3_auto_point1_temp_hyst.dev_attr.attr, &sensor_dev_attr_zone3_auto_point1_temp.dev_attr.attr, &sensor_dev_attr_zone3_auto_point2_temp.dev_attr.attr, &sensor_dev_attr_zone3_auto_point3_temp.dev_attr.attr, NULL }; -static const struct attribute_group dme1737_misc_chmod_group = { - .attrs = dme1737_misc_chmod_attr, +static const struct attribute_group dme1737_zone_chmod_group = { + .attrs = dme1737_zone_chmod_attr, }; /* The permissions of the following PWM attributes are changed to read- @@ -1757,7 +1780,6 @@ static struct attribute *dme1737_pwm1_chmod_attr[] = { &sensor_dev_attr_pwm1_enable.dev_attr.attr, &sensor_dev_attr_pwm1_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm1_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm1_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr, NULL }; @@ -1766,7 +1788,6 @@ static struct attribute *dme1737_pwm2_chmod_attr[] = { &sensor_dev_attr_pwm2_enable.dev_attr.attr, &sensor_dev_attr_pwm2_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm2_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm2_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, NULL }; @@ -1775,7 +1796,6 @@ static struct attribute *dme1737_pwm3_chmod_attr[] = { &sensor_dev_attr_pwm3_enable.dev_attr.attr, &sensor_dev_attr_pwm3_ramp_rate.dev_attr.attr, &sensor_dev_attr_pwm3_auto_channels_zone.dev_attr.attr, - &sensor_dev_attr_pwm3_auto_pwm_min.dev_attr.attr, &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, NULL }; @@ -1875,9 +1895,17 @@ static void dme1737_remove_files(struct device *dev) if (data->has_pwm & (1 << ix)) { sysfs_remove_group(&dev->kobj, &dme1737_pwm_group[ix]); + if (data->type != sch5027 && ix < 3) { + sysfs_remove_file(&dev->kobj, + dme1737_pwm_misc_attr[ix]); + } } } + if (data->type != sch5027) { + sysfs_remove_group(&dev->kobj, &dme1737_misc_group); + } + sysfs_remove_group(&dev->kobj, &dme1737_group); if (!data->client.driver) { @@ -1901,6 +1929,13 @@ static int dme1737_create_files(struct device *dev) goto exit_remove; } + /* Create misc sysfs attributes */ + if ((data->type != sch5027) && + (err = sysfs_create_group(&dev->kobj, + &dme1737_misc_group))) { + goto exit_remove; + } + /* Create fan sysfs attributes */ for (ix = 0; ix < ARRAY_SIZE(dme1737_fan_group); ix++) { if (data->has_fan & (1 << ix)) { @@ -1918,6 +1953,11 @@ static int dme1737_create_files(struct device *dev) &dme1737_pwm_group[ix]))) { goto exit_remove; } + if (data->type != sch5027 && ix < 3 && + (err = sysfs_create_file(&dev->kobj, + dme1737_pwm_misc_attr[ix]))) { + goto exit_remove; + } } } @@ -1927,16 +1967,27 @@ static int dme1737_create_files(struct device *dev) dev_info(dev, "Device is locked. Some attributes " "will be read-only.\n"); } else { - /* Change permissions of standard sysfs attributes */ - dme1737_chmod_group(dev, &dme1737_misc_chmod_group, + /* Change permissions of zone sysfs attributes */ + dme1737_chmod_group(dev, &dme1737_zone_chmod_group, S_IRUGO | S_IWUSR); + /* Change permissions of misc sysfs attributes */ + if (data->type != sch5027) { + dme1737_chmod_group(dev, &dme1737_misc_group, + S_IRUGO | S_IWUSR); + } + /* Change permissions of PWM sysfs attributes */ for (ix = 0; ix < ARRAY_SIZE(dme1737_pwm_chmod_group); ix++) { if (data->has_pwm & (1 << ix)) { dme1737_chmod_group(dev, &dme1737_pwm_chmod_group[ix], S_IRUGO | S_IWUSR); + if (data->type != sch5027 && ix < 3) { + dme1737_chmod_file(dev, + dme1737_pwm_misc_attr[ix], + S_IRUGO | S_IWUSR); + } } } @@ -1966,6 +2017,9 @@ static int dme1737_init_device(struct device *dev) int ix; u8 reg; + /* Point to the right nominal voltages array */ + data->in_nominal = IN_NOMINAL(data->type); + data->config = dme1737_read(client, DME1737_REG_CONFIG); /* Inform if part is not monitoring/started */ if (!(data->config & 0x01)) { @@ -2076,7 +2130,9 @@ static int dme1737_init_device(struct device *dev) data->pwm_acz[2] = 4; /* pwm3 -> zone3 */ /* Set VRM */ - data->vrm = vid_which_vrm(); + if (data->type != sch5027) { + data->vrm = vid_which_vrm(); + } return 0; } @@ -2095,9 +2151,10 @@ static int dme1737_i2c_get_features(int sio_cip, struct dme1737_data *data) dme1737_sio_enter(sio_cip); /* Check device ID - * The DME1737 can return either 0x78 or 0x77 as its device ID. */ + * The DME1737 can return either 0x78 or 0x77 as its device ID. + * The SCH5027 returns 0x89 as its device ID. */ reg = force_id ? force_id : dme1737_sio_inb(sio_cip, 0x20); - if (!(reg == 0x77 || reg == 0x78)) { + if (!(reg == 0x77 || reg == 0x78 || reg == 0x89)) { err = -ENODEV; goto exit; } @@ -2166,15 +2223,24 @@ static int dme1737_i2c_detect(struct i2c_adapter *adapter, int address, company = dme1737_read(client, DME1737_REG_COMPANY); verstep = dme1737_read(client, DME1737_REG_VERSTEP); - if (!((company == DME1737_COMPANY_SMSC) && - ((verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP))) { + if (company == DME1737_COMPANY_SMSC && + (verstep & DME1737_VERSTEP_MASK) == DME1737_VERSTEP) { + kind = dme1737; + } else if (company == DME1737_COMPANY_SMSC && + verstep == SCH5027_VERSTEP) { + kind = sch5027; + } else { err = -ENODEV; goto exit_kfree; } } - kind = dme1737; - name = "dme1737"; + if (kind == sch5027) { + name = "sch5027"; + } else { + kind = dme1737; + name = "dme1737"; + } data->type = kind; /* Fill in the remaining client fields and put it into the global @@ -2187,8 +2253,9 @@ static int dme1737_i2c_detect(struct i2c_adapter *adapter, int address, goto exit_kfree; } - dev_info(dev, "Found a DME1737 chip at 0x%02x (rev 0x%02x).\n", - client->addr, verstep); + dev_info(dev, "Found a %s chip at 0x%02x (rev 0x%02x).\n", + kind == sch5027 ? "SCH5027" : "DME1737", client->addr, + verstep); /* Initialize the DME1737 chip */ if ((err = dme1737_init_device(dev))) { @@ -2371,7 +2438,7 @@ static int __devinit dme1737_isa_probe(struct platform_device *pdev) goto exit_kfree; } } - data->type = -1; + data->type = sch311x; /* Fill in the remaining client fields and initialize the mutex */ strlcpy(client->name, "sch311x", I2C_NAME_SIZE); -- cgit v1.2.3 From 05a5e477687ac7a22c0791b3e899ed7d539f7b95 Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Wed, 6 Aug 2008 22:41:04 +0200 Subject: hwmon: (f71882fg) Delete needless forward declarations These functions aren't used before being defined, so there's no point in forward-declaring them. Signed-off-by: Jean Delvare Acked-by: Hans de Goede --- drivers/hwmon/f71882fg.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/hwmon/f71882fg.c b/drivers/hwmon/f71882fg.c index cbeb4984b5c7..67067e9a323e 100644 --- a/drivers/hwmon/f71882fg.c +++ b/drivers/hwmon/f71882fg.c @@ -87,8 +87,6 @@ static inline void superio_enter(int base); static inline void superio_select(int base, int ld); static inline void superio_exit(int base); -static inline u16 fan_from_reg ( u16 reg ); - struct f71882fg_data { unsigned short addr; struct device *hwmon_dev; @@ -116,10 +114,6 @@ struct f71882fg_data { u8 temp_diode_open; }; -static u8 f71882fg_read8(struct f71882fg_data *data, u8 reg); -static u16 f71882fg_read16(struct f71882fg_data *data, u8 reg); -static void f71882fg_write8(struct f71882fg_data *data, u8 reg, u8 val); - /* Sysfs in*/ static ssize_t show_in(struct device *dev, struct device_attribute *devattr, char *buf); -- cgit v1.2.3 From ad02ad85cf221c9a0574b48516762e37cceca0da Mon Sep 17 00:00:00 2001 From: Marc Hulsman Date: Wed, 6 Aug 2008 22:41:04 +0200 Subject: hwmon: (w83791d) Use fan divisor bits from vbat register Update w83791d with fan bits in vbat mon register (7.48 of the datasheet). This change allows all fans to have a divisor of 128, and fixes a problem with incorrectly reported fan speeds. Signed-off-by: Marc Hulsman Signed-off-by: Jean Delvare --- Documentation/hwmon/w83791d | 6 +++--- drivers/hwmon/w83791d.c | 24 ++++++++++++++++++++---- 2 files changed, 23 insertions(+), 7 deletions(-) diff --git a/Documentation/hwmon/w83791d b/Documentation/hwmon/w83791d index f153b2f6d62c..a67d3b7a7098 100644 --- a/Documentation/hwmon/w83791d +++ b/Documentation/hwmon/w83791d @@ -22,6 +22,7 @@ Credits: Additional contributors: Sven Anders + Marc Hulsman Module Parameters ----------------- @@ -67,9 +68,8 @@ on until the temperature falls below the Hysteresis value. Fan rotation speeds are reported in RPM (rotations per minute). An alarm is triggered if the rotation speed has dropped below a programmable limit. Fan -readings can be divided by a programmable divider (1, 2, 4, 8 for fan 1/2/3 -and 1, 2, 4, 8, 16, 32, 64 or 128 for fan 4/5) to give the readings more -range or accuracy. +readings can be divided by a programmable divider (1, 2, 4, 8, 16, +32, 64 or 128 for all fans) to give the readings more range or accuracy. Voltage sensors (also known as IN sensors) report their values in millivolts. An alarm is triggered if the voltage has crossed a programmable minimum diff --git a/drivers/hwmon/w83791d.c b/drivers/hwmon/w83791d.c index e4e91c9d480a..daa7d121483b 100644 --- a/drivers/hwmon/w83791d.c +++ b/drivers/hwmon/w83791d.c @@ -233,11 +233,9 @@ static u8 fan_to_reg(long rpm, int div) static u8 div_to_reg(int nr, long val) { int i; - int max; - /* first three fan's divisor max out at 8, rest max out at 128 */ - max = (nr < 3) ? 8 : 128; - val = SENSORS_LIMIT(val, 1, max) >> 1; + /* fan divisors max out at 128 */ + val = SENSORS_LIMIT(val, 1, 128) >> 1; for (i = 0; i < 7; i++) { if (val == 0) break; @@ -530,6 +528,7 @@ static ssize_t store_fan_div(struct device *dev, struct device_attribute *attr, unsigned long min; u8 tmp_fan_div; u8 fan_div_reg; + u8 vbat_reg; int indx = 0; u8 keep_mask = 0; u8 new_shift = 0; @@ -581,6 +580,16 @@ static ssize_t store_fan_div(struct device *dev, struct device_attribute *attr, w83791d_write(client, W83791D_REG_FAN_DIV[indx], fan_div_reg | tmp_fan_div); + /* Bit 2 of fans 0-2 is stored in the vbat register (bits 5-7) */ + if (nr < 3) { + keep_mask = ~(1 << (nr + 5)); + vbat_reg = w83791d_read(client, W83791D_REG_VBAT) + & keep_mask; + tmp_fan_div = (data->fan_div[nr] << (3 + nr)) & ~keep_mask; + w83791d_write(client, W83791D_REG_VBAT, + vbat_reg | tmp_fan_div); + } + /* Restore fan_min */ data->fan_min[nr] = fan_to_reg(min, DIV_FROM_REG(data->fan_div[nr])); w83791d_write(client, W83791D_REG_FAN_MIN[nr], data->fan_min[nr]); @@ -1182,6 +1191,7 @@ static struct w83791d_data *w83791d_update_device(struct device *dev) struct w83791d_data *data = i2c_get_clientdata(client); int i, j; u8 reg_array_tmp[3]; + u8 vbat_reg; mutex_lock(&data->update_lock); @@ -1219,6 +1229,12 @@ static struct w83791d_data *w83791d_update_device(struct device *dev) data->fan_div[3] = reg_array_tmp[2] & 0x07; data->fan_div[4] = (reg_array_tmp[2] >> 4) & 0x07; + /* The fan divisor for fans 0-2 get bit 2 from + bits 5-7 respectively of vbat register */ + vbat_reg = w83791d_read(client, W83791D_REG_VBAT); + for (i = 0; i < 3; i++) + data->fan_div[i] |= (vbat_reg >> (3 + i)) & 0x04; + /* Update the first temperature sensor */ for (i = 0; i < 3; i++) { data->temp1[i] = w83791d_read(client, -- cgit v1.2.3 From a95a5ed856e902e513119d4cc5b745faa202f761 Mon Sep 17 00:00:00 2001 From: Dominik Geyer Date: Wed, 6 Aug 2008 22:41:04 +0200 Subject: hwmon: (w83627hf) Add pwm_enable sysfs interface Adds support for pwm_enable sysfs interface for the w83627hf driver. Signed-off-by: Dominik Geyer Signed-off-by: Jean Delvare --- drivers/hwmon/w83627hf.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/hwmon/w83627hf.c b/drivers/hwmon/w83627hf.c index 9564fb069957..ba8b069b1082 100644 --- a/drivers/hwmon/w83627hf.c +++ b/drivers/hwmon/w83627hf.c @@ -209,6 +209,13 @@ static const u16 w83627hf_reg_temp_over[] = { 0x39, 0x155, 0x255 }; #define W83627HF_REG_PWM1 0x5A #define W83627HF_REG_PWM2 0x5B +static const u8 W83627THF_REG_PWM_ENABLE[] = { + 0x04, /* FAN 1 mode */ + 0x04, /* FAN 2 mode */ + 0x12, /* FAN AUX mode */ +}; +static const u8 W83627THF_PWM_ENABLE_SHIFT[] = { 2, 4, 1 }; + #define W83627THF_REG_PWM1 0x01 /* 697HF/637HF/687THF too */ #define W83627THF_REG_PWM2 0x03 /* 697HF/637HF/687THF too */ #define W83627THF_REG_PWM3 0x11 /* 637HF/687THF too */ @@ -366,6 +373,9 @@ struct w83627hf_data { u32 alarms; /* Register encoding, combined */ u32 beep_mask; /* Register encoding, combined */ u8 pwm[3]; /* Register value */ + u8 pwm_enable[3]; /* 1 = manual + 2 = thermal cruise (also called SmartFan I) + 3 = fan speed cruise */ u8 pwm_freq[3]; /* Register value */ u16 sens[3]; /* 1 = pentium diode; 2 = 3904 diode; 4 = thermistor */ @@ -956,6 +966,42 @@ static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 0); static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 1); static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO|S_IWUSR, show_pwm, store_pwm, 2); +static ssize_t +show_pwm_enable(struct device *dev, struct device_attribute *devattr, char *buf) +{ + int nr = to_sensor_dev_attr(devattr)->index; + struct w83627hf_data *data = w83627hf_update_device(dev); + return sprintf(buf, "%d\n", data->pwm_enable[nr]); +} + +static ssize_t +store_pwm_enable(struct device *dev, struct device_attribute *devattr, + const char *buf, size_t count) +{ + int nr = to_sensor_dev_attr(devattr)->index; + struct w83627hf_data *data = dev_get_drvdata(dev); + unsigned long val = simple_strtoul(buf, NULL, 10); + u8 reg; + + if (!val || (val > 3)) /* modes 1, 2 and 3 are supported */ + return -EINVAL; + mutex_lock(&data->update_lock); + data->pwm_enable[nr] = val; + reg = w83627hf_read_value(data, W83627THF_REG_PWM_ENABLE[nr]); + reg &= ~(0x03 << W83627THF_PWM_ENABLE_SHIFT[nr]); + reg |= (val - 1) << W83627THF_PWM_ENABLE_SHIFT[nr]; + w83627hf_write_value(data, W83627THF_REG_PWM_ENABLE[nr], reg); + mutex_unlock(&data->update_lock); + return count; +} + +static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO|S_IWUSR, show_pwm_enable, + store_pwm_enable, 0); +static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO|S_IWUSR, show_pwm_enable, + store_pwm_enable, 1); +static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO|S_IWUSR, show_pwm_enable, + store_pwm_enable, 2); + static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *devattr, char *buf) { @@ -1223,6 +1269,11 @@ static struct attribute *w83627hf_attributes_opt[] = { &sensor_dev_attr_pwm1_freq.dev_attr.attr, &sensor_dev_attr_pwm2_freq.dev_attr.attr, &sensor_dev_attr_pwm3_freq.dev_attr.attr, + + &sensor_dev_attr_pwm1_enable.dev_attr.attr, + &sensor_dev_attr_pwm2_enable.dev_attr.attr, + &sensor_dev_attr_pwm3_enable.dev_attr.attr, + NULL }; @@ -1366,6 +1417,19 @@ static int __devinit w83627hf_probe(struct platform_device *pdev) &sensor_dev_attr_pwm3_freq.dev_attr))) goto ERROR4; + if (data->type != w83627hf) + if ((err = device_create_file(dev, + &sensor_dev_attr_pwm1_enable.dev_attr)) + || (err = device_create_file(dev, + &sensor_dev_attr_pwm2_enable.dev_attr))) + goto ERROR4; + + if (data->type == w83627thf || data->type == w83637hf + || data->type == w83687thf) + if ((err = device_create_file(dev, + &sensor_dev_attr_pwm3_enable.dev_attr))) + goto ERROR4; + data->hwmon_dev = hwmon_device_register(dev); if (IS_ERR(data->hwmon_dev)) { err = PTR_ERR(data->hwmon_dev); @@ -1655,6 +1719,7 @@ static struct w83627hf_data *w83627hf_update_device(struct device *dev) { struct w83627hf_data *data = dev_get_drvdata(dev); int i, num_temps = (data->type == w83697hf) ? 2 : 3; + int num_pwms = (data->type == w83697hf) ? 2 : 3; mutex_lock(&data->update_lock); @@ -1707,6 +1772,15 @@ static struct w83627hf_data *w83627hf_update_device(struct device *dev) break; } } + if (data->type != w83627hf) { + for (i = 0; i < num_pwms; i++) { + u8 tmp = w83627hf_read_value(data, + W83627THF_REG_PWM_ENABLE[i]); + data->pwm_enable[i] = + ((tmp >> W83627THF_PWM_ENABLE_SHIFT[i]) + & 0x03) + 1; + } + } for (i = 0; i < num_temps; i++) { data->temp[i] = w83627hf_read_value( data, w83627hf_reg_temp[i]); -- cgit v1.2.3 From 2f8ea97a45e9db382787dd7afa7f500ee661aa7b Mon Sep 17 00:00:00 2001 From: Jean Delvare Date: Wed, 6 Aug 2008 22:41:04 +0200 Subject: hwmon: (w83627hf) Drop reset module parameter Drop the reset parameter of the w83627hf driver. It seems it wasn't that useful. It was dropped from the Linux 2.4 version of this driver back in July 2004. The only users who have reported that they were still using this parameter, needed it to switch the chip from automatic fan speed control back to manual mode. Now that the driver creates pwmN_enable sysfs files, users will be able to use these files instead, which is way less agressive. Signed-off-by: Jean Delvare Acked-by: Dominik Geyer --- Documentation/hwmon/w83627hf | 4 ---- drivers/hwmon/w83627hf.c | 27 --------------------------- 2 files changed, 31 deletions(-) diff --git a/Documentation/hwmon/w83627hf b/Documentation/hwmon/w83627hf index 880a59f53da9..6ee36dbafd64 100644 --- a/Documentation/hwmon/w83627hf +++ b/Documentation/hwmon/w83627hf @@ -40,10 +40,6 @@ Module Parameters (default is 1) Use 'init=0' to bypass initializing the chip. Try this if your computer crashes when you load the module. -* reset: int - (default is 0) - The driver used to reset the chip on load, but does no more. Use - 'reset=1' to restore the old behavior. Report if you need to do this. Description ----------- diff --git a/drivers/hwmon/w83627hf.c b/drivers/hwmon/w83627hf.c index ba8b069b1082..b30e5796cb26 100644 --- a/drivers/hwmon/w83627hf.c +++ b/drivers/hwmon/w83627hf.c @@ -67,10 +67,6 @@ module_param(force_i2c, byte, 0); MODULE_PARM_DESC(force_i2c, "Initialize the i2c address of the sensors"); -static int reset; -module_param(reset, bool, 0); -MODULE_PARM_DESC(reset, "Set to one to reset chip on load"); - static int init = 1; module_param(init, bool, 0); MODULE_PARM_DESC(init, "Set to zero to bypass chip initialization"); @@ -1600,29 +1596,6 @@ static void __devinit w83627hf_init_device(struct platform_device *pdev) enum chips type = data->type; u8 tmp; - if (reset) { - /* Resetting the chip has been the default for a long time, - but repeatedly caused problems (fans going to full - speed...) so it is now optional. It might even go away if - nobody reports it as being useful, as I see very little - reason why this would be needed at all. */ - dev_info(&pdev->dev, "If reset=1 solved a problem you were " - "having, please report!\n"); - - /* save this register */ - i = w83627hf_read_value(data, W83781D_REG_BEEP_CONFIG); - /* Reset all except Watchdog values and last conversion values - This sets fan-divs to 2, among others */ - w83627hf_write_value(data, W83781D_REG_CONFIG, 0x80); - /* Restore the register and disable power-on abnormal beep. - This saves FAN 1/2/3 input/output values set by BIOS. */ - w83627hf_write_value(data, W83781D_REG_BEEP_CONFIG, i | 0x80); - /* Disable master beep-enable (reset turns it on). - Individual beeps should be reset to off but for some reason - disabling this bit helps some people not get beeped */ - w83627hf_write_value(data, W83781D_REG_BEEP_INTS2, 0); - } - /* Minimize conflicts with other winbond i2c-only clients... */ /* disable i2c subclients... how to disable main i2c client?? */ /* force i2c address to relatively uncommon address */ -- cgit v1.2.3 From 68f823de3f1916cc0694376330c08377706b877d Mon Sep 17 00:00:00 2001 From: Grant Coady Date: Wed, 6 Aug 2008 22:41:05 +0200 Subject: hwmon: (adm9240) Remove EXPERIMENTAL dependency The adm9240 driver is in the kernel for three years now, time to remove the EXPERIMENTAL dependency. Signed-off-by: Grant Coady Signed-off-by: Jean Delvare --- drivers/hwmon/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 1de240a26fc5..7fe392899908 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -124,7 +124,7 @@ config SENSORS_ADM1031 config SENSORS_ADM9240 tristate "Analog Devices ADM9240 and compatibles" - depends on I2C && EXPERIMENTAL + depends on I2C select HWMON_VID help If you say yes here you get support for Analog Devices ADM9240, -- cgit v1.2.3 From 84f768c1633cfc547d82b9dc671ffea2f3785542 Mon Sep 17 00:00:00 2001 From: Krzysztof Helt Date: Wed, 6 Aug 2008 22:41:05 +0200 Subject: hwmon: (thmc50) Add support for critical temperature limits Add critical temperature limits to the driver. These limits are read only. Signed-off-by: Krzysztof Helt Signed-off-by: Jean Delvare --- drivers/hwmon/thmc50.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/hwmon/thmc50.c b/drivers/hwmon/thmc50.c index 3b01001108c1..7d97431e132f 100644 --- a/drivers/hwmon/thmc50.c +++ b/drivers/hwmon/thmc50.c @@ -55,8 +55,11 @@ I2C_CLIENT_MODULE_PARM(adm1022_temp3, "List of adapter,address pairs " static const u8 THMC50_REG_TEMP[] = { 0x27, 0x26, 0x20 }; static const u8 THMC50_REG_TEMP_MIN[] = { 0x3A, 0x38, 0x2C }; static const u8 THMC50_REG_TEMP_MAX[] = { 0x39, 0x37, 0x2B }; +static const u8 THMC50_REG_TEMP_CRITICAL[] = { 0x13, 0x14, 0x14 }; +static const u8 THMC50_REG_TEMP_DEFAULT[] = { 0x17, 0x18, 0x18 }; #define THMC50_REG_CONF_nFANOFF 0x20 +#define THMC50_REG_CONF_PROGRAMMED 0x08 /* Each client has this additional data */ struct thmc50_data { @@ -72,6 +75,7 @@ struct thmc50_data { s8 temp_input[3]; s8 temp_max[3]; s8 temp_min[3]; + s8 temp_critical[3]; u8 analog_out; u8 alarms; }; @@ -199,6 +203,15 @@ static ssize_t set_temp_max(struct device *dev, struct device_attribute *attr, return count; } +static ssize_t show_temp_critical(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + int nr = to_sensor_dev_attr(attr)->index; + struct thmc50_data *data = thmc50_update_device(dev); + return sprintf(buf, "%d\n", data->temp_critical[nr] * 1000); +} + static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, char *buf) { @@ -214,7 +227,9 @@ static SENSOR_DEVICE_ATTR(temp##offset##_input, S_IRUGO, show_temp, \ static SENSOR_DEVICE_ATTR(temp##offset##_min, S_IRUGO | S_IWUSR, \ show_temp_min, set_temp_min, offset - 1); \ static SENSOR_DEVICE_ATTR(temp##offset##_max, S_IRUGO | S_IWUSR, \ - show_temp_max, set_temp_max, offset - 1); + show_temp_max, set_temp_max, offset - 1); \ +static SENSOR_DEVICE_ATTR(temp##offset##_crit, S_IRUGO, \ + show_temp_critical, NULL, offset - 1); temp_reg(1); temp_reg(2); @@ -234,10 +249,12 @@ static struct attribute *thmc50_attributes[] = { &sensor_dev_attr_temp1_max.dev_attr.attr, &sensor_dev_attr_temp1_min.dev_attr.attr, &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_crit.dev_attr.attr, &sensor_dev_attr_temp1_alarm.dev_attr.attr, &sensor_dev_attr_temp2_max.dev_attr.attr, &sensor_dev_attr_temp2_min.dev_attr.attr, &sensor_dev_attr_temp2_input.dev_attr.attr, + &sensor_dev_attr_temp2_crit.dev_attr.attr, &sensor_dev_attr_temp2_alarm.dev_attr.attr, &sensor_dev_attr_temp2_fault.dev_attr.attr, &sensor_dev_attr_pwm1.dev_attr.attr, @@ -254,6 +271,7 @@ static struct attribute *temp3_attributes[] = { &sensor_dev_attr_temp3_max.dev_attr.attr, &sensor_dev_attr_temp3_min.dev_attr.attr, &sensor_dev_attr_temp3_input.dev_attr.attr, + &sensor_dev_attr_temp3_crit.dev_attr.attr, &sensor_dev_attr_temp3_alarm.dev_attr.attr, &sensor_dev_attr_temp3_fault.dev_attr.attr, NULL @@ -429,6 +447,10 @@ static struct thmc50_data *thmc50_update_device(struct device *dev) int temps = data->has_temp3 ? 3 : 2; int i; + int prog = i2c_smbus_read_byte_data(client, THMC50_REG_CONF); + + prog &= THMC50_REG_CONF_PROGRAMMED; + for (i = 0; i < temps; i++) { data->temp_input[i] = i2c_smbus_read_byte_data(client, THMC50_REG_TEMP[i]); @@ -436,6 +458,10 @@ static struct thmc50_data *thmc50_update_device(struct device *dev) THMC50_REG_TEMP_MAX[i]); data->temp_min[i] = i2c_smbus_read_byte_data(client, THMC50_REG_TEMP_MIN[i]); + data->temp_critical[i] = + i2c_smbus_read_byte_data(client, + prog ? THMC50_REG_TEMP_CRITICAL[i] + : THMC50_REG_TEMP_DEFAULT[i]); } data->analog_out = i2c_smbus_read_byte_data(client, THMC50_REG_ANALOG_OUT); -- cgit v1.2.3 From 6c633c3025c75f5fcf3a76d375faff34e3be021b Mon Sep 17 00:00:00 2001 From: Sean MacLennan Date: Wed, 6 Aug 2008 22:41:05 +0200 Subject: hwmon: ad7414 driver Driver for the Analog Devices AD7414 temperature monitoring chip. Signed-off-by: Sean MacLennan Signed-off-by: Jean Delvare --- drivers/hwmon/Kconfig | 10 ++ drivers/hwmon/Makefile | 1 + drivers/hwmon/ad7414.c | 268 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 279 insertions(+) create mode 100644 drivers/hwmon/ad7414.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig index 7fe392899908..bf4ebfb86fa5 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig @@ -57,6 +57,16 @@ config SENSORS_ABITUGURU3 This driver can also be built as a module. If so, the module will be called abituguru3. +config SENSORS_AD7414 + tristate "Analog Devices AD7414" + depends on I2C && EXPERIMENTAL + help + If you say yes here you get support for the Analog Devices + AD7414 temperature monitoring chip. + + This driver can also be built as a module. If so, the module + will be called ad7414. + config SENSORS_AD7418 tristate "Analog Devices AD7416, AD7417 and AD7418" depends on I2C && EXPERIMENTAL diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index d098677e08de..7943e5cefb06 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SENSORS_W83791D) += w83791d.o obj-$(CONFIG_SENSORS_ABITUGURU) += abituguru.o obj-$(CONFIG_SENSORS_ABITUGURU3)+= abituguru3.o +obj-$(CONFIG_SENSORS_AD7414) += ad7414.o obj-$(CONFIG_SENSORS_AD7418) += ad7418.o obj-$(CONFIG_SENSORS_ADM1021) += adm1021.o obj-$(CONFIG_SENSORS_ADM1025) += adm1025.o diff --git a/drivers/hwmon/ad7414.c b/drivers/hwmon/ad7414.c new file mode 100644 index 000000000000..ce8d94fbfd7e --- /dev/null +++ b/drivers/hwmon/ad7414.c @@ -0,0 +1,268 @@ +/* + * An hwmon driver for the Analog Devices AD7414 + * + * Copyright 2006 Stefan Roese , DENX Software Engineering + * + * Copyright (c) 2008 PIKA Technologies + * Sean MacLennan + * + * Copyright (c) 2008 Spansion Inc. + * Frank Edelhaeuser + * (converted to "new style" I2C driver model, removed checkpatch.pl warnings) + * + * Based on ad7418.c + * Copyright 2006 Tower Technologies, Alessandro Zummo + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/* AD7414 registers */ +#define AD7414_REG_TEMP 0x00 +#define AD7414_REG_CONF 0x01 +#define AD7414_REG_T_HIGH 0x02 +#define AD7414_REG_T_LOW 0x03 + +static u8 AD7414_REG_LIMIT[] = { AD7414_REG_T_HIGH, AD7414_REG_T_LOW }; + +struct ad7414_data { + struct device *hwmon_dev; + struct mutex lock; /* atomic read data updates */ + char valid; /* !=0 if following fields are valid */ + unsigned long next_update; /* In jiffies */ + s16 temp_input; /* Register values */ + s8 temps[ARRAY_SIZE(AD7414_REG_LIMIT)]; +}; + +/* REG: (0.25C/bit, two's complement) << 6 */ +static inline int ad7414_temp_from_reg(s16 reg) +{ + /* use integer division instead of equivalent right shift to + * guarantee arithmetic shift and preserve the sign + */ + return ((int)reg / 64) * 250; +} + +static inline int ad7414_read(struct i2c_client *client, u8 reg) +{ + if (reg == AD7414_REG_TEMP) { + int value = i2c_smbus_read_word_data(client, reg); + return (value < 0) ? value : swab16(value); + } else + return i2c_smbus_read_byte_data(client, reg); +} + +static inline int ad7414_write(struct i2c_client *client, u8 reg, u8 value) +{ + return i2c_smbus_write_byte_data(client, reg, value); +} + +struct ad7414_data *ad7414_update_device(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ad7414_data *data = i2c_get_clientdata(client); + + mutex_lock(&data->lock); + + if (time_after(jiffies, data->next_update) || !data->valid) { + int value, i; + + dev_dbg(&client->dev, "starting ad7414 update\n"); + + value = ad7414_read(client, AD7414_REG_TEMP); + if (value < 0) + dev_dbg(&client->dev, "AD7414_REG_TEMP err %d\n", + value); + else + data->temp_input = value; + + for (i = 0; i < ARRAY_SIZE(AD7414_REG_LIMIT); ++i) { + value = ad7414_read(client, AD7414_REG_LIMIT[i]); + if (value < 0) + dev_dbg(&client->dev, "AD7414 reg %d err %d\n", + AD7414_REG_LIMIT[i], value); + else + data->temps[i] = value; + } + + data->next_update = jiffies + HZ + HZ / 2; + data->valid = 1; + } + + mutex_unlock(&data->lock); + + return data; +} + +static ssize_t show_temp_input(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct ad7414_data *data = ad7414_update_device(dev); + return sprintf(buf, "%d\n", ad7414_temp_from_reg(data->temp_input)); +} +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp_input, NULL, 0); + +static ssize_t show_max_min(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int index = to_sensor_dev_attr(attr)->index; + struct ad7414_data *data = ad7414_update_device(dev); + return sprintf(buf, "%d\n", data->temps[index] * 1000); +} + +static ssize_t set_max_min(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct i2c_client *client = to_i2c_client(dev); + struct ad7414_data *data = i2c_get_clientdata(client); + int index = to_sensor_dev_attr(attr)->index; + u8 reg = AD7414_REG_LIMIT[index]; + long temp = simple_strtol(buf, NULL, 10); + + temp = SENSORS_LIMIT(temp, -40000, 85000); + temp = (temp + (temp < 0 ? -500 : 500)) / 1000; + + mutex_lock(&data->lock); + data->temps[index] = temp; + ad7414_write(client, reg, temp); + mutex_unlock(&data->lock); + return count; +} + +static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO, + show_max_min, set_max_min, 0); +static SENSOR_DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO, + show_max_min, set_max_min, 1); + +static ssize_t show_alarm(struct device *dev, struct device_attribute *attr, + char *buf) +{ + int bitnr = to_sensor_dev_attr(attr)->index; + struct ad7414_data *data = ad7414_update_device(dev); + int value = (data->temp_input >> bitnr) & 1; + return sprintf(buf, "%d\n", value); +} + +static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL, 3); +static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL, 4); + +static struct attribute *ad7414_attributes[] = { + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_max.dev_attr.attr, + &sensor_dev_attr_temp1_min.dev_attr.attr, + &sensor_dev_attr_temp1_max_alarm.dev_attr.attr, + &sensor_dev_attr_temp1_min_alarm.dev_attr.attr, + NULL +}; + +static const struct attribute_group ad7414_group = { + .attrs = ad7414_attributes, +}; + +static int ad7414_probe(struct i2c_client *client, + const struct i2c_device_id *dev_id) +{ + struct ad7414_data *data; + int conf; + int err = 0; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA | + I2C_FUNC_SMBUS_READ_WORD_DATA)) + goto exit; + + data = kzalloc(sizeof(struct ad7414_data), GFP_KERNEL); + if (!data) { + err = -ENOMEM; + goto exit; + } + + i2c_set_clientdata(client, data); + mutex_init(&data->lock); + + dev_info(&client->dev, "chip found\n"); + + /* Make sure the chip is powered up. */ + conf = i2c_smbus_read_byte_data(client, AD7414_REG_CONF); + if (conf < 0) + dev_warn(&client->dev, + "ad7414_probe unable to read config register.\n"); + else { + conf &= ~(1 << 7); + i2c_smbus_write_byte_data(client, AD7414_REG_CONF, conf); + } + + /* Register sysfs hooks */ + err = sysfs_create_group(&client->dev.kobj, &ad7414_group); + if (err) + goto exit_free; + + data->hwmon_dev = hwmon_device_register(&client->dev); + if (IS_ERR(data->hwmon_dev)) { + err = PTR_ERR(data->hwmon_dev); + goto exit_remove; + } + + return 0; + +exit_remove: + sysfs_remove_group(&client->dev.kobj, &ad7414_group); +exit_free: + kfree(data); +exit: + return err; +} + +static int __devexit ad7414_remove(struct i2c_client *client) +{ + struct ad7414_data *data = i2c_get_clientdata(client); + + hwmon_device_unregister(data->hwmon_dev); + sysfs_remove_group(&client->dev.kobj, &ad7414_group); + kfree(data); + return 0; +} + +static const struct i2c_device_id ad7414_id[] = { + { "ad7414", 0 }, + {} +}; + +static struct i2c_driver ad7414_driver = { + .driver = { + .name = "ad7414", + }, + .probe = ad7414_probe, + .remove = __devexit_p(ad7414_remove), + .id_table = ad7414_id, +}; + +static int __init ad7414_init(void) +{ + return i2c_add_driver(&ad7414_driver); +} +module_init(ad7414_init); + +static void __exit ad7414_exit(void) +{ + i2c_del_driver(&ad7414_driver); +} +module_exit(ad7414_exit); + +MODULE_AUTHOR("Stefan Roese , " + "Frank Edelhaeuser "); + +MODULE_DESCRIPTION("AD7414 driver"); +MODULE_LICENSE("GPL"); -- cgit v1.2.3 From 15872212e876de9ae404108e4ad231a645b55b54 Mon Sep 17 00:00:00 2001 From: Frank Myhr Date: Wed, 6 Aug 2008 22:41:06 +0200 Subject: hwmon: (hwmon-vid) Trivial format multi-line comments per CodingStyle Signed-off-by: Frank Myhr Signed-off-by: Jean Delvare --- drivers/hwmon/hwmon-vid.c | 140 +++++++++++++++++++++++----------------------- 1 file changed, 71 insertions(+), 69 deletions(-) diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c index 3330667280b9..ed78a72e7261 100644 --- a/drivers/hwmon/hwmon-vid.c +++ b/drivers/hwmon/hwmon-vid.c @@ -1,76 +1,78 @@ /* - hwmon-vid.c - VID/VRM/VRD voltage conversions - - Copyright (c) 2004 Rudolf Marek - - Partly imported from i2c-vid.h of the lm_sensors project - Copyright (c) 2002 Mark D. Studebaker - With assistance from Trent Piepho - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -*/ + * hwmon-vid.c - VID/VRM/VRD voltage conversions + * + * Copyright (c) 2004 Rudolf Marek + * + * Partly imported from i2c-vid.h of the lm_sensors project + * Copyright (c) 2002 Mark D. Studebaker + * With assistance from Trent Piepho + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ #include #include #include /* - Common code for decoding VID pins. - - References: - - For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines", - available at http://developer.intel.com/. - - For VRD 10.0 and up, "VRD x.y Design Guide", - available at http://developer.intel.com/. - - AMD Opteron processors don't follow the Intel specifications. - I'm going to "make up" 2.4 as the spec number for the Opterons. - No good reason just a mnemonic for the 24x Opteron processor - series. - - Opteron VID encoding is: - 00000 = 1.550 V - 00001 = 1.525 V - . . . . - 11110 = 0.800 V - 11111 = 0.000 V (off) - - The 17 specification is in fact Intel Mobile Voltage Positioning - - (IMVP-II). You can find more information in the datasheet of Max1718 - http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 - - The 13 specification corresponds to the Intel Pentium M series. There - doesn't seem to be any named specification for these. The conversion - tables are detailed directly in the various Pentium M datasheets: - http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm - - The 14 specification corresponds to Intel Core series. There - doesn't seem to be any named specification for these. The conversion - tables are detailed directly in the various Pentium Core datasheets: - http://www.intel.com/design/mobile/datashts/309221.htm - - The 110 (VRM 11) specification corresponds to Intel Conroe based series. - http://www.intel.com/design/processor/applnots/313214.htm -*/ - -/* vrm is the VRM/VRD document version multiplied by 10. - val is the 4-bit or more VID code. - Returned value is in mV to avoid floating point in the kernel. - Some VID have some bits in uV scale, this is rounded to mV */ + * Common code for decoding VID pins. + * + * References: + * + * For VRM 8.4 to 9.1, "VRM x.y DC-DC Converter Design Guidelines", + * available at http://developer.intel.com/. + * + * For VRD 10.0 and up, "VRD x.y Design Guide", + * available at http://developer.intel.com/. + * + * AMD Opteron processors don't follow the Intel specifications. + * I'm going to "make up" 2.4 as the spec number for the Opterons. + * No good reason just a mnemonic for the 24x Opteron processor + * series. + * + * Opteron VID encoding is: + * 00000 = 1.550 V + * 00001 = 1.525 V + * . . . . + * 11110 = 0.800 V + * 11111 = 0.000 V (off) + * + * The 17 specification is in fact Intel Mobile Voltage Positioning - + * (IMVP-II). You can find more information in the datasheet of Max1718 + * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 + * + * The 13 specification corresponds to the Intel Pentium M series. There + * doesn't seem to be any named specification for these. The conversion + * tables are detailed directly in the various Pentium M datasheets: + * http://www.intel.com/design/intarch/pentiumm/docs_pentiumm.htm + * + * The 14 specification corresponds to Intel Core series. There + * doesn't seem to be any named specification for these. The conversion + * tables are detailed directly in the various Pentium Core datasheets: + * http://www.intel.com/design/mobile/datashts/309221.htm + * + * The 110 (VRM 11) specification corresponds to Intel Conroe based series. + * http://www.intel.com/design/processor/applnots/313214.htm + */ + +/* + * vrm is the VRM/VRD document version multiplied by 10. + * val is the 4-bit or more VID code. + * Returned value is in mV to avoid floating point in the kernel. + * Some VID have some bits in uV scale, this is rounded to mV. + */ int vid_from_reg(int val, u8 vrm) { int vid; @@ -141,9 +143,9 @@ int vid_from_reg(int val, u8 vrm) /* - After this point is the code to automatically determine which - VRM/VRD specification should be used depending on the CPU. -*/ + * After this point is the code to automatically determine which + * VRM/VRD specification should be used depending on the CPU. + */ struct vrm_model { u8 vendor; -- cgit v1.2.3 From 116d0486bdefc11f71e567cadf0c47f788b4dd06 Mon Sep 17 00:00:00 2001 From: Frank Myhr Date: Wed, 6 Aug 2008 22:41:06 +0200 Subject: hwmon: (hwmon-vid) Add 6-bit vid codes for AMD NPT 0Fh cpus AMD NPT 0Fh cpus use 6 bit VID codes. Successive codes with msb 0 describe 25mV decrements, while those with msb 1 describe 12.5mV decrements. Existing hwmon-vid.c is correct only for codes with msb 0; add support for the codes with msb 1. Ref: p 309, Table 71 AMD Publication 32559, BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf Signed-off-by: Frank Myhr Signed-off-by: Jean Delvare --- drivers/hwmon/hwmon-vid.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/drivers/hwmon/hwmon-vid.c b/drivers/hwmon/hwmon-vid.c index ed78a72e7261..7b0a32c4dcfb 100644 --- a/drivers/hwmon/hwmon-vid.c +++ b/drivers/hwmon/hwmon-vid.c @@ -37,18 +37,14 @@ * For VRD 10.0 and up, "VRD x.y Design Guide", * available at http://developer.intel.com/. * + * AMD NPT 0Fh (Athlon64 & Opteron), AMD Publication 32559, + * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf + * Table 71. VID Code Voltages * AMD Opteron processors don't follow the Intel specifications. * I'm going to "make up" 2.4 as the spec number for the Opterons. * No good reason just a mnemonic for the 24x Opteron processor * series. * - * Opteron VID encoding is: - * 00000 = 1.550 V - * 00001 = 1.525 V - * . . . . - * 11110 = 0.800 V - * 11111 = 0.000 V (off) - * * The 17 specification is in fact Intel Mobile Voltage Positioning - * (IMVP-II). You can find more information in the datasheet of Max1718 * http://www.maxim-ic.com/quick_view2.cfm/qv_pk/2452 @@ -98,9 +94,11 @@ int vid_from_reg(int val, u8 vrm) if (val < 0x02 || val > 0xb2) return 0; return((1600000 - (val - 2) * 6250 + 500) / 1000); - case 24: /* Opteron processor */ - val &= 0x1f; - return(val == 0x1f ? 0 : 1550 - val * 25); + + case 24: /* AMD NPT 0Fh (Athlon64 & Opteron) */ + val &= 0x3f; + return (val < 32) ? 1550 - 25 * val + : 775 - (25 * (val - 31)) / 2; case 91: /* VRM 9.1 */ case 90: /* VRM 9.0 */ -- cgit v1.2.3 From 0475169c13e177e1af5a02f5e9f30fda13dc0b86 Mon Sep 17 00:00:00 2001 From: Andrew Paprocki Date: Wed, 6 Aug 2008 22:41:06 +0200 Subject: hwmon: (it87) Support for 16-bit fan reading in it8712 >= rev 0x07 The it8712 chip supports 16-bit fan tachometers in revisions >= 0x07. Revisions >= 0x08 dropped support for 8-bit fan divisor registers. The patch enables 16-bit fan readings on all revisions >= 0x07 just like the it8716 and it8718 chips. Signed-off-by: Andrew Paprocki Signed-off-by: Jean Delvare --- Documentation/hwmon/it87 | 9 +++++---- drivers/hwmon/it87.c | 32 ++++++++++++++++++++++---------- 2 files changed, 27 insertions(+), 14 deletions(-) diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index f4ce1fdbeff6..d931525f3f37 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 @@ -11,7 +11,9 @@ Supported chips: Prefix: 'it8712' Addresses scanned: from Super I/O config space (8 I/O ports) Datasheet: Publicly available at the ITE website - http://www.ite.com.tw/ + http://www.ite.com.tw/product_info/file/pc/IT8712F_V0.9.1.pdf + http://www.ite.com.tw/product_info/file/pc/Errata%20V0.1%20for%20IT8712F%20V0.9.1.pdf + http://www.ite.com.tw/product_info/file/pc/IT8712F_V0.9.3.pdf * IT8716F/IT8726F Prefix: 'it8716' Addresses scanned: from Super I/O config space (8 I/O ports) @@ -90,14 +92,13 @@ upper VID bits share their pins with voltage inputs (in5 and in6) so you can't have both on a given board. The IT8716F, IT8718F and later IT8712F revisions have support for -2 additional fans. They are supported by the driver for the IT8716F and -IT8718F but not for the IT8712F +2 additional fans. The additional fans are supported by the driver. The IT8716F and IT8718F, and late IT8712F and IT8705F also have optional 16-bit tachometer counters for fans 1 to 3. This is better (no more fan clock divider mess) but not compatible with the older chips and revisions. For now, the driver only uses the 16-bit mode on the -IT8716F and IT8718F. +late IT8712F, IT8716F and IT8718F. The IT8726F is just bit enhanced IT8716F with additional hardware for AMD power sequencing. Therefore the chip will appear as IT8716F diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index e12c132ff83a..2a365681f969 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -151,9 +151,9 @@ static int fix_pwm_polarity; /* The IT8718F has the VID value in a different register, in Super-I/O configuration space. */ #define IT87_REG_VID 0x0a -/* Warning: register 0x0b is used for something completely different in - new chips/revisions. I suspect only 16-bit tachometer mode will work - for these. */ +/* The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b + for fan divisors. Later IT8712F revisions must use 16-bit tachometer + mode. */ #define IT87_REG_FAN_DIV 0x0b #define IT87_REG_FAN_16BIT 0x0c @@ -234,6 +234,7 @@ static const unsigned int pwm_freq[8] = { struct it87_sio_data { enum chips type; /* Values read from Super-I/O config space */ + u8 revision; u8 vid_value; }; @@ -242,6 +243,7 @@ struct it87_sio_data { struct it87_data { struct device *hwmon_dev; enum chips type; + u8 revision; unsigned short addr; const char *name; @@ -268,6 +270,14 @@ struct it87_data { u8 manual_pwm_ctl[3]; /* manual PWM value set by user */ }; +static inline int has_16bit_fans(const struct it87_data *data) +{ + /* IT8712F Datasheet 0.9.1, section 8.3.5 indicates 7h == Version I. + This is the first revision with 16bit tachometer support. */ + return (data->type == it8712 && data->revision >= 0x07) + || data->type == it8716 + || data->type == it8718; +} static int it87_probe(struct platform_device *pdev); static int __devexit it87_remove(struct platform_device *pdev); @@ -991,8 +1001,9 @@ static int __init it87_find(unsigned short *address, } err = 0; + sio_data->revision = superio_inb(DEVREV) & 0x0f; pr_info("it87: Found IT%04xF chip at 0x%x, revision %d\n", - chip_type, *address, superio_inb(DEVREV) & 0x0f); + chip_type, *address, sio_data->revision); /* Read GPIO config and VID value from LDN 7 (GPIO) */ if (chip_type != IT8705F_DEVID) { @@ -1045,6 +1056,7 @@ static int __devinit it87_probe(struct platform_device *pdev) data->addr = res->start; data->type = sio_data->type; + data->revision = sio_data->revision; data->name = names[sio_data->type]; /* Now, we do the remaining detection. */ @@ -1069,7 +1081,7 @@ static int __devinit it87_probe(struct platform_device *pdev) goto ERROR2; /* Do not create fan files for disabled fans */ - if (data->type == it8716 || data->type == it8718) { + if (has_16bit_fans(data)) { /* 16-bit tachometers */ if (data->has_fan & (1 << 0)) { if ((err = device_create_file(dev, @@ -1350,7 +1362,7 @@ static void __devinit it87_init_device(struct platform_device *pdev) data->has_fan = (data->fan_main_ctrl >> 4) & 0x07; /* Set tachometers to 16-bit mode if needed */ - if (data->type == it8716 || data->type == it8718) { + if (has_16bit_fans(data)) { tmp = it87_read_value(data, IT87_REG_FAN_16BIT); if (~tmp & 0x07 & data->has_fan) { dev_dbg(&pdev->dev, @@ -1426,7 +1438,7 @@ static struct it87_data *it87_update_device(struct device *dev) data->fan[i] = it87_read_value(data, IT87_REG_FAN[i]); /* Add high byte if in 16-bit mode */ - if (data->type == it8716 || data->type == it8718) { + if (has_16bit_fans(data)) { data->fan[i] |= it87_read_value(data, IT87_REG_FANX[i]) << 8; data->fan_min[i] |= it87_read_value(data, @@ -1443,8 +1455,7 @@ static struct it87_data *it87_update_device(struct device *dev) } /* Newer chips don't have clock dividers */ - if ((data->has_fan & 0x07) && data->type != it8716 - && data->type != it8718) { + if ((data->has_fan & 0x07) && !has_16bit_fans(data)) { i = it87_read_value(data, IT87_REG_FAN_DIV); data->fan_div[0] = i & 0x07; data->fan_div[1] = (i >> 3) & 0x07; @@ -1460,7 +1471,8 @@ static struct it87_data *it87_update_device(struct device *dev) data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL); data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE); - /* The 8705 does not have VID capability */ + /* The 8705 does not have VID capability. + The 8718 does not use IT87_REG_VID for the same purpose. */ if (data->type == it8712 || data->type == it8716) { data->vid = it87_read_value(data, IT87_REG_VID); /* The older IT8712F revisions had only 5 VID pins, -- cgit v1.2.3 From 816d8c6a2580562698cf0fa0b9e5b4dd570e636e Mon Sep 17 00:00:00 2001 From: Andrew Paprocki Date: Wed, 6 Aug 2008 22:41:06 +0200 Subject: hwmon: (it87) Support for 16-bit fan reading in it8705 >= rev 0x03 The it8705 chip supports 16-bit fan tachometers in revisions at least >= 0x03 (Version G). This patch enables 16-bit fan readings on all revisions >= 0x03 just like the it8712, it8716, and it8718 chips. Signed-off-by: Andrew Paprocki Signed-off-by: Jean Delvare --- Documentation/hwmon/it87 | 6 +++--- drivers/hwmon/it87.c | 19 ++++++++++++------- 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 index d931525f3f37..3496b7020e7c 100644 --- a/Documentation/hwmon/it87 +++ b/Documentation/hwmon/it87 @@ -6,7 +6,7 @@ Supported chips: Prefix: 'it87' Addresses scanned: from Super I/O config space (8 I/O ports) Datasheet: Publicly available at the ITE website - http://www.ite.com.tw/ + http://www.ite.com.tw/product_info/file/pc/IT8705F_V.0.4.1.pdf * IT8712F Prefix: 'it8712' Addresses scanned: from Super I/O config space (8 I/O ports) @@ -97,8 +97,8 @@ The IT8716F, IT8718F and later IT8712F revisions have support for The IT8716F and IT8718F, and late IT8712F and IT8705F also have optional 16-bit tachometer counters for fans 1 to 3. This is better (no more fan clock divider mess) but not compatible with the older chips and -revisions. For now, the driver only uses the 16-bit mode on the -late IT8712F, IT8716F and IT8718F. +revisions. The 16-bit tachometer mode is enabled by the driver when one +of the above chips is detected. The IT8726F is just bit enhanced IT8716F with additional hardware for AMD power sequencing. Therefore the chip will appear as IT8716F diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c index 2a365681f969..30cdb0956779 100644 --- a/drivers/hwmon/it87.c +++ b/drivers/hwmon/it87.c @@ -272,9 +272,11 @@ struct it87_data { static inline int has_16bit_fans(const struct it87_data *data) { - /* IT8712F Datasheet 0.9.1, section 8.3.5 indicates 7h == Version I. - This is the first revision with 16bit tachometer support. */ - return (data->type == it8712 && data->revision >= 0x07) + /* IT8705F Datasheet 0.4.1, 3h == Version G. + IT8712F Datasheet 0.9.1, section 8.3.5 indicates 7h == Version I. + These are the first revisions with 16bit tachometer support. */ + return (data->type == it87 && data->revision >= 0x03) + || (data->type == it8712 && data->revision >= 0x07) || data->type == it8716 || data->type == it8718; } @@ -1370,10 +1372,13 @@ static void __devinit it87_init_device(struct platform_device *pdev) it87_write_value(data, IT87_REG_FAN_16BIT, tmp | 0x07); } - if (tmp & (1 << 4)) - data->has_fan |= (1 << 3); /* fan4 enabled */ - if (tmp & (1 << 5)) - data->has_fan |= (1 << 4); /* fan5 enabled */ + /* IT8705F only supports three fans. */ + if (data->type != it87) { + if (tmp & (1 << 4)) + data->has_fan |= (1 << 3); /* fan4 enabled */ + if (tmp & (1 << 5)) + data->has_fan |= (1 << 4); /* fan5 enabled */ + } } /* Set current fan mode registers and the default settings for the -- cgit v1.2.3 From 680db0136e0778a0d7e025af7572c6a8d82279e2 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 6 Aug 2008 15:14:13 -0700 Subject: pcm_native.c: remove unused label This fixes the warning sound/core/pcm_native.c: In function 'snd_pcm_fasync': sound/core/pcm_native.c:3262: warning: label 'out' defined but not used Signed-off-by: Linus Torvalds --- sound/core/pcm_native.c | 1 - 1 file changed, 1 deletion(-) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index c49b9d9e303c..333cff68c150 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -3259,7 +3259,6 @@ static int snd_pcm_fasync(int fd, struct file * file, int on) runtime = substream->runtime; err = fasync_helper(fd, file, on, &runtime->fasync); -out: unlock_kernel(); if (err < 0) return err; -- cgit v1.2.3 From f99e8f277f1172c49ac7b0585aed5b094fe235d4 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 6 Aug 2008 17:36:23 -0700 Subject: iSeries: Fix up viotty_ioctl BKL locking fallout The bogus code to call into the n_tty layer got removed in commit 8bc5fb6abb670fa9079cd1994f016a39f99698fe ("Remove bogons from the iSeries console"), but it left a now uninitialized "return ret;" around. Not that this code has ever even compiled since the BKL pushdown, since not only is "ret" no longer initialized, it was never actually declared even originally. Replace it with a "return -ENOIOCTLCMD" Pointed-out-by: Paul Mackerras Acked-by: Alan Cox Signed-off-by: Linus Torvalds --- drivers/char/viocons.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/char/viocons.c b/drivers/char/viocons.c index f48892ba12f5..7feeb774a101 100644 --- a/drivers/char/viocons.c +++ b/drivers/char/viocons.c @@ -705,7 +705,7 @@ static int viotty_ioctl(struct tty_struct *tty, struct file *file, case KDSKBLED: return 0; } - return ret; + return -ENOIOCTLCMD; } /* -- cgit v1.2.3 From 685d87f7ccc649ab92b55e18e507a65d0e694eb9 Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Wed, 6 Aug 2008 19:24:47 -0700 Subject: Revert "pcm_native.c: remove unused label" This reverts commit 680db0136e0778a0d7e025af7572c6a8d82279e2. The label is actually used, but hidden behind CONFIG_SND_DEBUG and the horrible snd_assert() macro. That macro could probably be improved to be along the lines of #define snd_assert(expr, args...) do { if ((void)(expr),0) { args; } } while (0) or similar to make sure that we always both evaluate 'expr' and parse 'args', but while gcc should optimize it all away, I'm too lazy to really verify that. So I'll just admit defeat and will continue to live with the annoying warning. Noted-by: Robert P. J. Day Signed-off-by: Linus "Grr.." Torvalds --- sound/core/pcm_native.c | 1 + 1 file changed, 1 insertion(+) diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c index 333cff68c150..c49b9d9e303c 100644 --- a/sound/core/pcm_native.c +++ b/sound/core/pcm_native.c @@ -3259,6 +3259,7 @@ static int snd_pcm_fasync(int fd, struct file * file, int on) runtime = substream->runtime; err = fasync_helper(fd, file, on, &runtime->fasync); +out: unlock_kernel(); if (err < 0) return err; -- cgit v1.2.3 From f780a9f119caa48088b230836a7fa73d1096de7c Mon Sep 17 00:00:00 2001 From: Yevgeny Petrilin Date: Wed, 6 Aug 2008 20:14:06 -0700 Subject: mlx4_core: Add ethernet fields to CQE struct Add ethernet-related fields to struct mlx4_cqe so that the mlx4_en ethernet NIC driver can share the same definition. Signed-off-by: Yevgeny Petrilin Signed-off-by: Roland Dreier --- drivers/infiniband/hw/mlx4/cq.c | 33 ++++++++++++++++----------------- include/linux/mlx4/cq.h | 36 ++++++++++++++++++++++++------------ 2 files changed, 40 insertions(+), 29 deletions(-) diff --git a/drivers/infiniband/hw/mlx4/cq.c b/drivers/infiniband/hw/mlx4/cq.c index a1464574bfdd..d0866a3636e2 100644 --- a/drivers/infiniband/hw/mlx4/cq.c +++ b/drivers/infiniband/hw/mlx4/cq.c @@ -515,17 +515,17 @@ static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe, wc->vendor_err = cqe->vendor_err_syndrome; } -static int mlx4_ib_ipoib_csum_ok(__be32 status, __be16 checksum) +static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum) { - return ((status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | - MLX4_CQE_IPOIB_STATUS_IPV4F | - MLX4_CQE_IPOIB_STATUS_IPV4OPT | - MLX4_CQE_IPOIB_STATUS_IPV6 | - MLX4_CQE_IPOIB_STATUS_IPOK)) == - cpu_to_be32(MLX4_CQE_IPOIB_STATUS_IPV4 | - MLX4_CQE_IPOIB_STATUS_IPOK)) && - (status & cpu_to_be32(MLX4_CQE_IPOIB_STATUS_UDP | - MLX4_CQE_IPOIB_STATUS_TCP)) && + return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 | + MLX4_CQE_STATUS_IPV4F | + MLX4_CQE_STATUS_IPV4OPT | + MLX4_CQE_STATUS_IPV6 | + MLX4_CQE_STATUS_IPOK)) == + cpu_to_be16(MLX4_CQE_STATUS_IPV4 | + MLX4_CQE_STATUS_IPOK)) && + (status & cpu_to_be16(MLX4_CQE_STATUS_UDP | + MLX4_CQE_STATUS_TCP)) && checksum == cpu_to_be16(0xffff); } @@ -582,17 +582,17 @@ repoll: } if (!*cur_qp || - (be32_to_cpu(cqe->my_qpn) & 0xffffff) != (*cur_qp)->mqp.qpn) { + (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) { /* * We do not have to take the QP table lock here, * because CQs will be locked while QPs are removed * from the table. */ mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev, - be32_to_cpu(cqe->my_qpn)); + be32_to_cpu(cqe->vlan_my_qpn)); if (unlikely(!mqp)) { printk(KERN_WARNING "CQ %06x with entry for unknown QPN %06x\n", - cq->mcq.cqn, be32_to_cpu(cqe->my_qpn) & 0xffffff); + cq->mcq.cqn, be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK); return -EINVAL; } @@ -692,14 +692,13 @@ repoll: } wc->slid = be16_to_cpu(cqe->rlid); - wc->sl = cqe->sl >> 4; + wc->sl = be16_to_cpu(cqe->sl_vid >> 12); g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn); wc->src_qp = g_mlpath_rqpn & 0xffffff; wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f; wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0; wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f; - wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->ipoib_status, - cqe->checksum); + wc->csum_ok = mlx4_ib_ipoib_csum_ok(cqe->status, cqe->checksum); } return 0; @@ -767,7 +766,7 @@ void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq) */ while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) { cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); - if ((be32_to_cpu(cqe->my_qpn) & 0xffffff) == qpn) { + if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) { if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK)) mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index)); ++nfreed; diff --git a/include/linux/mlx4/cq.h b/include/linux/mlx4/cq.h index 071cf96cf01f..6f65b2c8bb89 100644 --- a/include/linux/mlx4/cq.h +++ b/include/linux/mlx4/cq.h @@ -39,17 +39,18 @@ #include struct mlx4_cqe { - __be32 my_qpn; + __be32 vlan_my_qpn; __be32 immed_rss_invalid; __be32 g_mlpath_rqpn; - u8 sl; - u8 reserved1; + __be16 sl_vid; __be16 rlid; - __be32 ipoib_status; + __be16 status; + u8 ipv6_ext_mask; + u8 badfcs_enc; __be32 byte_cnt; __be16 wqe_index; __be16 checksum; - u8 reserved2[3]; + u8 reserved[3]; u8 owner_sr_opcode; }; @@ -63,6 +64,11 @@ struct mlx4_err_cqe { u8 owner_sr_opcode; }; +enum { + MLX4_CQE_VLAN_PRESENT_MASK = 1 << 29, + MLX4_CQE_QPN_MASK = 0xffffff, +}; + enum { MLX4_CQE_OWNER_MASK = 0x80, MLX4_CQE_IS_SEND_MASK = 0x40, @@ -86,13 +92,19 @@ enum { }; enum { - MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22, - MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23, - MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24, - MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25, - MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26, - MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27, - MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28, + MLX4_CQE_STATUS_IPV4 = 1 << 6, + MLX4_CQE_STATUS_IPV4F = 1 << 7, + MLX4_CQE_STATUS_IPV6 = 1 << 8, + MLX4_CQE_STATUS_IPV4OPT = 1 << 9, + MLX4_CQE_STATUS_TCP = 1 << 10, + MLX4_CQE_STATUS_UDP = 1 << 11, + MLX4_CQE_STATUS_IPOK = 1 << 12, +}; + +enum { + MLX4_CQE_LLC = 1, + MLX4_CQE_SNAP = 1 << 1, + MLX4_CQE_BAD_FCS = 1 << 4, }; static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd, -- cgit v1.2.3 From 58750139001bae11a1f9b074f3a9c774fecf5ba8 Mon Sep 17 00:00:00 2001 From: Greg Ungerer Date: Thu, 31 Jul 2008 14:38:07 +1000 Subject: Move all of include/asm-m68knommu to arch/m68knommu/include/asm. With the current kbuild infrastructure in place no other changes are required for this to work. Signed-off-by: Greg Ungerer --- arch/m68knommu/include/asm/Kbuild | 1 + arch/m68knommu/include/asm/MC68328.h | 1266 ++++++++++++++ arch/m68knommu/include/asm/MC68332.h | 152 ++ arch/m68knommu/include/asm/MC68EZ328.h | 1253 +++++++++++++ arch/m68knommu/include/asm/MC68VZ328.h | 1349 ++++++++++++++ arch/m68knommu/include/asm/a.out.h | 1 + arch/m68knommu/include/asm/anchor.h | 112 ++ arch/m68knommu/include/asm/atomic.h | 155 ++ arch/m68knommu/include/asm/auxvec.h | 4 + arch/m68knommu/include/asm/bitops.h | 336 ++++ arch/m68knommu/include/asm/bootinfo.h | 2 + arch/m68knommu/include/asm/bootstd.h | 132 ++ arch/m68knommu/include/asm/bug.h | 4 + arch/m68knommu/include/asm/bugs.h | 16 + arch/m68knommu/include/asm/byteorder.h | 27 + arch/m68knommu/include/asm/cache.h | 12 + arch/m68knommu/include/asm/cachectl.h | 1 + arch/m68knommu/include/asm/cacheflush.h | 84 + arch/m68knommu/include/asm/checksum.h | 132 ++ arch/m68knommu/include/asm/coldfire.h | 51 + arch/m68knommu/include/asm/commproc.h | 703 ++++++++ arch/m68knommu/include/asm/cputime.h | 6 + arch/m68knommu/include/asm/current.h | 24 + arch/m68knommu/include/asm/dbg.h | 6 + arch/m68knommu/include/asm/delay.h | 76 + arch/m68knommu/include/asm/device.h | 7 + arch/m68knommu/include/asm/div64.h | 1 + arch/m68knommu/include/asm/dma-mapping.h | 10 + arch/m68knommu/include/asm/dma.h | 494 ++++++ arch/m68knommu/include/asm/elf.h | 110 ++ arch/m68knommu/include/asm/elia.h | 41 + arch/m68knommu/include/asm/emergency-restart.h | 6 + arch/m68knommu/include/asm/entry.h | 182 ++ arch/m68knommu/include/asm/errno.h | 1 + arch/m68knommu/include/asm/fb.h | 12 + arch/m68knommu/include/asm/fcntl.h | 1 + arch/m68knommu/include/asm/flat.h | 17 + arch/m68knommu/include/asm/fpu.h | 21 + arch/m68knommu/include/asm/futex.h | 6 + arch/m68knommu/include/asm/hardirq.h | 27 + arch/m68knommu/include/asm/hw_irq.h | 4 + arch/m68knommu/include/asm/hwtest.h | 1 + arch/m68knommu/include/asm/io.h | 194 ++ arch/m68knommu/include/asm/ioctl.h | 1 + arch/m68knommu/include/asm/ioctls.h | 1 + arch/m68knommu/include/asm/ipcbuf.h | 1 + arch/m68knommu/include/asm/irq.h | 26 + arch/m68knommu/include/asm/irq_regs.h | 1 + arch/m68knommu/include/asm/kdebug.h | 1 + arch/m68knommu/include/asm/kmap_types.h | 21 + arch/m68knommu/include/asm/linkage.h | 1 + arch/m68knommu/include/asm/local.h | 6 + arch/m68knommu/include/asm/m5206sim.h | 131 ++ arch/m68knommu/include/asm/m520xsim.h | 63 + arch/m68knommu/include/asm/m523xsim.h | 45 + arch/m68knommu/include/asm/m5249sim.h | 209 +++ arch/m68knommu/include/asm/m5272sim.h | 78 + arch/m68knommu/include/asm/m527xsim.h | 74 + arch/m68knommu/include/asm/m528xsim.h | 159 ++ arch/m68knommu/include/asm/m5307sim.h | 181 ++ arch/m68knommu/include/asm/m532xsim.h | 2238 ++++++++++++++++++++++++ arch/m68knommu/include/asm/m5407sim.h | 157 ++ arch/m68knommu/include/asm/m68360.h | 13 + arch/m68knommu/include/asm/m68360_enet.h | 177 ++ arch/m68knommu/include/asm/m68360_pram.h | 431 +++++ arch/m68knommu/include/asm/m68360_quicc.h | 362 ++++ arch/m68knommu/include/asm/m68360_regs.h | 408 +++++ arch/m68knommu/include/asm/machdep.h | 26 + arch/m68knommu/include/asm/math-emu.h | 1 + arch/m68knommu/include/asm/mc146818rtc.h | 9 + arch/m68knommu/include/asm/mcfcache.h | 150 ++ arch/m68knommu/include/asm/mcfdma.h | 144 ++ arch/m68knommu/include/asm/mcfmbus.h | 77 + arch/m68knommu/include/asm/mcfne.h | 325 ++++ arch/m68knommu/include/asm/mcfpci.h | 119 ++ arch/m68knommu/include/asm/mcfpit.h | 64 + arch/m68knommu/include/asm/mcfsim.h | 126 ++ arch/m68knommu/include/asm/mcfsmc.h | 187 ++ arch/m68knommu/include/asm/mcftimer.h | 80 + arch/m68knommu/include/asm/mcfuart.h | 216 +++ arch/m68knommu/include/asm/mcfwdebug.h | 118 ++ arch/m68knommu/include/asm/md.h | 1 + arch/m68knommu/include/asm/mman.h | 1 + arch/m68knommu/include/asm/mmu.h | 11 + arch/m68knommu/include/asm/mmu_context.h | 33 + arch/m68knommu/include/asm/module.h | 11 + arch/m68knommu/include/asm/movs.h | 1 + arch/m68knommu/include/asm/msgbuf.h | 1 + arch/m68knommu/include/asm/mutex.h | 9 + arch/m68knommu/include/asm/nettel.h | 108 ++ arch/m68knommu/include/asm/openprom.h | 1 + arch/m68knommu/include/asm/oplib.h | 1 + arch/m68knommu/include/asm/page.h | 77 + arch/m68knommu/include/asm/page_offset.h | 5 + arch/m68knommu/include/asm/param.h | 22 + arch/m68knommu/include/asm/pci.h | 29 + arch/m68knommu/include/asm/percpu.h | 6 + arch/m68knommu/include/asm/pgalloc.h | 8 + arch/m68knommu/include/asm/pgtable.h | 70 + arch/m68knommu/include/asm/poll.h | 1 + arch/m68knommu/include/asm/posix_types.h | 1 + arch/m68knommu/include/asm/processor.h | 143 ++ arch/m68knommu/include/asm/ptrace.h | 87 + arch/m68knommu/include/asm/quicc_simple.h | 52 + arch/m68knommu/include/asm/resource.h | 1 + arch/m68knommu/include/asm/rtc.h | 1 + arch/m68knommu/include/asm/scatterlist.h | 22 + arch/m68knommu/include/asm/sections.h | 7 + arch/m68knommu/include/asm/segment.h | 51 + arch/m68knommu/include/asm/sembuf.h | 1 + arch/m68knommu/include/asm/setup.h | 10 + arch/m68knommu/include/asm/shm.h | 1 + arch/m68knommu/include/asm/shmbuf.h | 1 + arch/m68knommu/include/asm/shmparam.h | 1 + arch/m68knommu/include/asm/sigcontext.h | 17 + arch/m68knommu/include/asm/siginfo.h | 6 + arch/m68knommu/include/asm/signal.h | 159 ++ arch/m68knommu/include/asm/smp.h | 1 + arch/m68knommu/include/asm/socket.h | 1 + arch/m68knommu/include/asm/sockios.h | 1 + arch/m68knommu/include/asm/spinlock.h | 1 + arch/m68knommu/include/asm/stat.h | 1 + arch/m68knommu/include/asm/statfs.h | 1 + arch/m68knommu/include/asm/string.h | 126 ++ arch/m68knommu/include/asm/system.h | 324 ++++ arch/m68knommu/include/asm/termbits.h | 1 + arch/m68knommu/include/asm/termios.h | 1 + arch/m68knommu/include/asm/thread_info.h | 98 ++ arch/m68knommu/include/asm/timex.h | 23 + arch/m68knommu/include/asm/tlb.h | 1 + arch/m68knommu/include/asm/tlbflush.h | 55 + arch/m68knommu/include/asm/topology.h | 6 + arch/m68knommu/include/asm/traps.h | 154 ++ arch/m68knommu/include/asm/types.h | 1 + arch/m68knommu/include/asm/uaccess.h | 181 ++ arch/m68knommu/include/asm/ucontext.h | 32 + arch/m68knommu/include/asm/unaligned.h | 25 + arch/m68knommu/include/asm/unistd.h | 366 ++++ arch/m68knommu/include/asm/user.h | 1 + include/asm-m68knommu/Kbuild | 1 - include/asm-m68knommu/MC68328.h | 1266 -------------- include/asm-m68knommu/MC68332.h | 152 -- include/asm-m68knommu/MC68EZ328.h | 1253 ------------- include/asm-m68knommu/MC68VZ328.h | 1349 -------------- include/asm-m68knommu/a.out.h | 1 - include/asm-m68knommu/anchor.h | 112 -- include/asm-m68knommu/atomic.h | 155 -- include/asm-m68knommu/auxvec.h | 4 - include/asm-m68knommu/bitops.h | 336 ---- include/asm-m68knommu/bootinfo.h | 2 - include/asm-m68knommu/bootstd.h | 132 -- include/asm-m68knommu/bug.h | 4 - include/asm-m68knommu/bugs.h | 16 - include/asm-m68knommu/byteorder.h | 27 - include/asm-m68knommu/cache.h | 12 - include/asm-m68knommu/cachectl.h | 1 - include/asm-m68knommu/cacheflush.h | 84 - include/asm-m68knommu/checksum.h | 132 -- include/asm-m68knommu/coldfire.h | 51 - include/asm-m68knommu/commproc.h | 703 -------- include/asm-m68knommu/cputime.h | 6 - include/asm-m68knommu/current.h | 24 - include/asm-m68knommu/dbg.h | 6 - include/asm-m68knommu/delay.h | 76 - include/asm-m68knommu/device.h | 7 - include/asm-m68knommu/div64.h | 1 - include/asm-m68knommu/dma-mapping.h | 10 - include/asm-m68knommu/dma.h | 494 ------ include/asm-m68knommu/elf.h | 110 -- include/asm-m68knommu/elia.h | 41 - include/asm-m68knommu/emergency-restart.h | 6 - include/asm-m68knommu/entry.h | 182 -- include/asm-m68knommu/errno.h | 1 - include/asm-m68knommu/fb.h | 12 - include/asm-m68knommu/fcntl.h | 1 - include/asm-m68knommu/flat.h | 17 - include/asm-m68knommu/fpu.h | 21 - include/asm-m68knommu/futex.h | 6 - include/asm-m68knommu/hardirq.h | 27 - include/asm-m68knommu/hw_irq.h | 4 - include/asm-m68knommu/hwtest.h | 1 - include/asm-m68knommu/io.h | 194 -- include/asm-m68knommu/ioctl.h | 1 - include/asm-m68knommu/ioctls.h | 1 - include/asm-m68knommu/ipcbuf.h | 1 - include/asm-m68knommu/irq.h | 26 - include/asm-m68knommu/irq_regs.h | 1 - include/asm-m68knommu/kdebug.h | 1 - include/asm-m68knommu/kmap_types.h | 21 - include/asm-m68knommu/linkage.h | 1 - include/asm-m68knommu/local.h | 6 - include/asm-m68knommu/m5206sim.h | 131 -- include/asm-m68knommu/m520xsim.h | 63 - include/asm-m68knommu/m523xsim.h | 45 - include/asm-m68knommu/m5249sim.h | 209 --- include/asm-m68knommu/m5272sim.h | 78 - include/asm-m68knommu/m527xsim.h | 74 - include/asm-m68knommu/m528xsim.h | 159 -- include/asm-m68knommu/m5307sim.h | 181 -- include/asm-m68knommu/m532xsim.h | 2238 ------------------------ include/asm-m68knommu/m5407sim.h | 157 -- include/asm-m68knommu/m68360.h | 13 - include/asm-m68knommu/m68360_enet.h | 177 -- include/asm-m68knommu/m68360_pram.h | 431 ----- include/asm-m68knommu/m68360_quicc.h | 362 ---- include/asm-m68knommu/m68360_regs.h | 408 ----- include/asm-m68knommu/machdep.h | 26 - include/asm-m68knommu/math-emu.h | 1 - include/asm-m68knommu/mc146818rtc.h | 9 - include/asm-m68knommu/mcfcache.h | 150 -- include/asm-m68knommu/mcfdma.h | 144 -- include/asm-m68knommu/mcfmbus.h | 77 - include/asm-m68knommu/mcfne.h | 325 ---- include/asm-m68knommu/mcfpci.h | 119 -- include/asm-m68knommu/mcfpit.h | 64 - include/asm-m68knommu/mcfsim.h | 126 -- include/asm-m68knommu/mcfsmc.h | 187 -- include/asm-m68knommu/mcftimer.h | 80 - include/asm-m68knommu/mcfuart.h | 216 --- include/asm-m68knommu/mcfwdebug.h | 118 -- include/asm-m68knommu/md.h | 1 - include/asm-m68knommu/mman.h | 1 - include/asm-m68knommu/mmu.h | 11 - include/asm-m68knommu/mmu_context.h | 33 - include/asm-m68knommu/module.h | 11 - include/asm-m68knommu/movs.h | 1 - include/asm-m68knommu/msgbuf.h | 1 - include/asm-m68knommu/mutex.h | 9 - include/asm-m68knommu/nettel.h | 108 -- include/asm-m68knommu/openprom.h | 1 - include/asm-m68knommu/oplib.h | 1 - include/asm-m68knommu/page.h | 77 - include/asm-m68knommu/page_offset.h | 5 - include/asm-m68knommu/param.h | 22 - include/asm-m68knommu/pci.h | 29 - include/asm-m68knommu/percpu.h | 6 - include/asm-m68knommu/pgalloc.h | 8 - include/asm-m68knommu/pgtable.h | 70 - include/asm-m68knommu/poll.h | 1 - include/asm-m68knommu/posix_types.h | 1 - include/asm-m68knommu/processor.h | 143 -- include/asm-m68knommu/ptrace.h | 87 - include/asm-m68knommu/quicc_simple.h | 52 - include/asm-m68knommu/resource.h | 1 - include/asm-m68knommu/rtc.h | 1 - include/asm-m68knommu/scatterlist.h | 22 - include/asm-m68knommu/sections.h | 7 - include/asm-m68knommu/segment.h | 51 - include/asm-m68knommu/sembuf.h | 1 - include/asm-m68knommu/setup.h | 10 - include/asm-m68knommu/shm.h | 1 - include/asm-m68knommu/shmbuf.h | 1 - include/asm-m68knommu/shmparam.h | 1 - include/asm-m68knommu/sigcontext.h | 17 - include/asm-m68knommu/siginfo.h | 6 - include/asm-m68knommu/signal.h | 159 -- include/asm-m68knommu/smp.h | 1 - include/asm-m68knommu/socket.h | 1 - include/asm-m68knommu/sockios.h | 1 - include/asm-m68knommu/spinlock.h | 1 - include/asm-m68knommu/stat.h | 1 - include/asm-m68knommu/statfs.h | 1 - include/asm-m68knommu/string.h | 126 -- include/asm-m68knommu/system.h | 324 ---- include/asm-m68knommu/termbits.h | 1 - include/asm-m68knommu/termios.h | 1 - include/asm-m68knommu/thread_info.h | 98 -- include/asm-m68knommu/timex.h | 23 - include/asm-m68knommu/tlb.h | 1 - include/asm-m68knommu/tlbflush.h | 55 - include/asm-m68knommu/topology.h | 6 - include/asm-m68knommu/traps.h | 154 -- include/asm-m68knommu/types.h | 1 - include/asm-m68knommu/uaccess.h | 181 -- include/asm-m68knommu/ucontext.h | 32 - include/asm-m68knommu/unaligned.h | 25 - include/asm-m68knommu/unistd.h | 366 ---- include/asm-m68knommu/user.h | 1 - 278 files changed, 15825 insertions(+), 15825 deletions(-) create mode 100644 arch/m68knommu/include/asm/Kbuild create mode 100644 arch/m68knommu/include/asm/MC68328.h create mode 100644 arch/m68knommu/include/asm/MC68332.h create mode 100644 arch/m68knommu/include/asm/MC68EZ328.h create mode 100644 arch/m68knommu/include/asm/MC68VZ328.h create mode 100644 arch/m68knommu/include/asm/a.out.h create mode 100644 arch/m68knommu/include/asm/anchor.h create mode 100644 arch/m68knommu/include/asm/atomic.h create mode 100644 arch/m68knommu/include/asm/auxvec.h create mode 100644 arch/m68knommu/include/asm/bitops.h create mode 100644 arch/m68knommu/include/asm/bootinfo.h create mode 100644 arch/m68knommu/include/asm/bootstd.h create mode 100644 arch/m68knommu/include/asm/bug.h create mode 100644 arch/m68knommu/include/asm/bugs.h create mode 100644 arch/m68knommu/include/asm/byteorder.h create mode 100644 arch/m68knommu/include/asm/cache.h create mode 100644 arch/m68knommu/include/asm/cachectl.h create mode 100644 arch/m68knommu/include/asm/cacheflush.h create mode 100644 arch/m68knommu/include/asm/checksum.h create mode 100644 arch/m68knommu/include/asm/coldfire.h create mode 100644 arch/m68knommu/include/asm/commproc.h create mode 100644 arch/m68knommu/include/asm/cputime.h create mode 100644 arch/m68knommu/include/asm/current.h create mode 100644 arch/m68knommu/include/asm/dbg.h create mode 100644 arch/m68knommu/include/asm/delay.h create mode 100644 arch/m68knommu/include/asm/device.h create mode 100644 arch/m68knommu/include/asm/div64.h create mode 100644 arch/m68knommu/include/asm/dma-mapping.h create mode 100644 arch/m68knommu/include/asm/dma.h create mode 100644 arch/m68knommu/include/asm/elf.h create mode 100644 arch/m68knommu/include/asm/elia.h create mode 100644 arch/m68knommu/include/asm/emergency-restart.h create mode 100644 arch/m68knommu/include/asm/entry.h create mode 100644 arch/m68knommu/include/asm/errno.h create mode 100644 arch/m68knommu/include/asm/fb.h create mode 100644 arch/m68knommu/include/asm/fcntl.h create mode 100644 arch/m68knommu/include/asm/flat.h create mode 100644 arch/m68knommu/include/asm/fpu.h create mode 100644 arch/m68knommu/include/asm/futex.h create mode 100644 arch/m68knommu/include/asm/hardirq.h create mode 100644 arch/m68knommu/include/asm/hw_irq.h create mode 100644 arch/m68knommu/include/asm/hwtest.h create mode 100644 arch/m68knommu/include/asm/io.h create mode 100644 arch/m68knommu/include/asm/ioctl.h create mode 100644 arch/m68knommu/include/asm/ioctls.h create mode 100644 arch/m68knommu/include/asm/ipcbuf.h create mode 100644 arch/m68knommu/include/asm/irq.h create mode 100644 arch/m68knommu/include/asm/irq_regs.h create mode 100644 arch/m68knommu/include/asm/kdebug.h create mode 100644 arch/m68knommu/include/asm/kmap_types.h create mode 100644 arch/m68knommu/include/asm/linkage.h create mode 100644 arch/m68knommu/include/asm/local.h create mode 100644 arch/m68knommu/include/asm/m5206sim.h create mode 100644 arch/m68knommu/include/asm/m520xsim.h create mode 100644 arch/m68knommu/include/asm/m523xsim.h create mode 100644 arch/m68knommu/include/asm/m5249sim.h create mode 100644 arch/m68knommu/include/asm/m5272sim.h create mode 100644 arch/m68knommu/include/asm/m527xsim.h create mode 100644 arch/m68knommu/include/asm/m528xsim.h create mode 100644 arch/m68knommu/include/asm/m5307sim.h create mode 100644 arch/m68knommu/include/asm/m532xsim.h create mode 100644 arch/m68knommu/include/asm/m5407sim.h create mode 100644 arch/m68knommu/include/asm/m68360.h create mode 100644 arch/m68knommu/include/asm/m68360_enet.h create mode 100644 arch/m68knommu/include/asm/m68360_pram.h create mode 100644 arch/m68knommu/include/asm/m68360_quicc.h create mode 100644 arch/m68knommu/include/asm/m68360_regs.h create mode 100644 arch/m68knommu/include/asm/machdep.h create mode 100644 arch/m68knommu/include/asm/math-emu.h create mode 100644 arch/m68knommu/include/asm/mc146818rtc.h create mode 100644 arch/m68knommu/include/asm/mcfcache.h create mode 100644 arch/m68knommu/include/asm/mcfdma.h create mode 100644 arch/m68knommu/include/asm/mcfmbus.h create mode 100644 arch/m68knommu/include/asm/mcfne.h create mode 100644 arch/m68knommu/include/asm/mcfpci.h create mode 100644 arch/m68knommu/include/asm/mcfpit.h create mode 100644 arch/m68knommu/include/asm/mcfsim.h create mode 100644 arch/m68knommu/include/asm/mcfsmc.h create mode 100644 arch/m68knommu/include/asm/mcftimer.h create mode 100644 arch/m68knommu/include/asm/mcfuart.h create mode 100644 arch/m68knommu/include/asm/mcfwdebug.h create mode 100644 arch/m68knommu/include/asm/md.h create mode 100644 arch/m68knommu/include/asm/mman.h create mode 100644 arch/m68knommu/include/asm/mmu.h create mode 100644 arch/m68knommu/include/asm/mmu_context.h create mode 100644 arch/m68knommu/include/asm/module.h create mode 100644 arch/m68knommu/include/asm/movs.h create mode 100644 arch/m68knommu/include/asm/msgbuf.h create mode 100644 arch/m68knommu/include/asm/mutex.h create mode 100644 arch/m68knommu/include/asm/nettel.h create mode 100644 arch/m68knommu/include/asm/openprom.h create mode 100644 arch/m68knommu/include/asm/oplib.h create mode 100644 arch/m68knommu/include/asm/page.h create mode 100644 arch/m68knommu/include/asm/page_offset.h create mode 100644 arch/m68knommu/include/asm/param.h create mode 100644 arch/m68knommu/include/asm/pci.h create mode 100644 arch/m68knommu/include/asm/percpu.h create mode 100644 arch/m68knommu/include/asm/pgalloc.h create mode 100644 arch/m68knommu/include/asm/pgtable.h create mode 100644 arch/m68knommu/include/asm/poll.h create mode 100644 arch/m68knommu/include/asm/posix_types.h create mode 100644 arch/m68knommu/include/asm/processor.h create mode 100644 arch/m68knommu/include/asm/ptrace.h create mode 100644 arch/m68knommu/include/asm/quicc_simple.h create mode 100644 arch/m68knommu/include/asm/resource.h create mode 100644 arch/m68knommu/include/asm/rtc.h create mode 100644 arch/m68knommu/include/asm/scatterlist.h create mode 100644 arch/m68knommu/include/asm/sections.h create mode 100644 arch/m68knommu/include/asm/segment.h create mode 100644 arch/m68knommu/include/asm/sembuf.h create mode 100644 arch/m68knommu/include/asm/setup.h create mode 100644 arch/m68knommu/include/asm/shm.h create mode 100644 arch/m68knommu/include/asm/shmbuf.h create mode 100644 arch/m68knommu/include/asm/shmparam.h create mode 100644 arch/m68knommu/include/asm/sigcontext.h create mode 100644 arch/m68knommu/include/asm/siginfo.h create mode 100644 arch/m68knommu/include/asm/signal.h create mode 100644 arch/m68knommu/include/asm/smp.h create mode 100644 arch/m68knommu/include/asm/socket.h create mode 100644 arch/m68knommu/include/asm/sockios.h create mode 100644 arch/m68knommu/include/asm/spinlock.h create mode 100644 arch/m68knommu/include/asm/stat.h create mode 100644 arch/m68knommu/include/asm/statfs.h create mode 100644 arch/m68knommu/include/asm/string.h create mode 100644 arch/m68knommu/include/asm/system.h create mode 100644 arch/m68knommu/include/asm/termbits.h create mode 100644 arch/m68knommu/include/asm/termios.h create mode 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+include include/asm-generic/Kbuild.asm diff --git a/arch/m68knommu/include/asm/MC68328.h b/arch/m68knommu/include/asm/MC68328.h new file mode 100644 index 000000000000..a337e56d09bf --- /dev/null +++ b/arch/m68knommu/include/asm/MC68328.h @@ -0,0 +1,1266 @@ + +/* include/asm-m68knommu/MC68328.h: '328 control registers + * + * Copyright (C) 1999 Vladimir Gurevich + * Bear & Hare Software, Inc. + * + * Based on include/asm-m68knommu/MC68332.h + * Copyright (C) 1998 Kenneth Albanowski , + * + */ + +#ifndef _MC68328_H_ +#define _MC68328_H_ + +#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) +#define WORD_REF(addr) (*((volatile unsigned short*)addr)) +#define LONG_REF(addr) (*((volatile unsigned long*)addr)) + +#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) +#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) + +/********** + * + * 0xFFFFF0xx -- System Control + * + **********/ + +/* + * System Control Register (SCR) + */ +#define SCR_ADDR 0xfffff000 +#define SCR BYTE_REF(SCR_ADDR) + +#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ +#define SCR_DMAP 0x04 /* Double Map */ +#define SCR_SO 0x08 /* Supervisor Only */ +#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ +#define SCR_PRV 0x20 /* Privilege Violation */ +#define SCR_WPV 0x40 /* Write Protect Violation */ +#define SCR_BETO 0x80 /* Bus-Error TimeOut */ + +/* + * Mask Revision Register + */ +#define MRR_ADDR 0xfffff004 +#define MRR LONG_REF(MRR_ADDR) + +/********** + * + * 0xFFFFF1xx -- Chip-Select logic + * + **********/ + +/********** + * + * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control + * + **********/ + +/* + * Group Base Address Registers + */ +#define GRPBASEA_ADDR 0xfffff100 +#define GRPBASEB_ADDR 0xfffff102 +#define GRPBASEC_ADDR 0xfffff104 +#define GRPBASED_ADDR 0xfffff106 + +#define GRPBASEA WORD_REF(GRPBASEA_ADDR) +#define GRPBASEB WORD_REF(GRPBASEB_ADDR) +#define GRPBASEC WORD_REF(GRPBASEC_ADDR) +#define GRPBASED WORD_REF(GRPBASED_ADDR) + +#define GRPBASE_V 0x0001 /* Valid */ +#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */ + +/* + * Group Base Address Mask Registers + */ +#define GRPMASKA_ADDR 0xfffff108 +#define GRPMASKB_ADDR 0xfffff10a +#define GRPMASKC_ADDR 0xfffff10c +#define GRPMASKD_ADDR 0xfffff10e + +#define GRPMASKA WORD_REF(GRPMASKA_ADDR) +#define GRPMASKB WORD_REF(GRPMASKB_ADDR) +#define GRPMASKC WORD_REF(GRPMASKC_ADDR) +#define GRPMASKD WORD_REF(GRPMASKD_ADDR) + +#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */ + +/* + * Chip-Select Option Registers (group A) + */ +#define CSA0_ADDR 0xfffff110 +#define CSA1_ADDR 0xfffff114 +#define CSA2_ADDR 0xfffff118 +#define CSA3_ADDR 0xfffff11c + +#define CSA0 LONG_REF(CSA0_ADDR) +#define CSA1 LONG_REF(CSA1_ADDR) +#define CSA2 LONG_REF(CSA2_ADDR) +#define CSA3 LONG_REF(CSA3_ADDR) + +#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */ +#define CSA_WAIT_SHIFT 0 +#define CSA_RO 0x00000008 /* Read-Only */ +#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ +#define CSA_AM_SHIFT 8 +#define CSA_BUSW 0x00010000 /* Bus Width Select */ +#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ +#define CSA_AC_SHIFT 24 + +/* + * Chip-Select Option Registers (group B) + */ +#define CSB0_ADDR 0xfffff120 +#define CSB1_ADDR 0xfffff124 +#define CSB2_ADDR 0xfffff128 +#define CSB3_ADDR 0xfffff12c + +#define CSB0 LONG_REF(CSB0_ADDR) +#define CSB1 LONG_REF(CSB1_ADDR) +#define CSB2 LONG_REF(CSB2_ADDR) +#define CSB3 LONG_REF(CSB3_ADDR) + +#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */ +#define CSB_WAIT_SHIFT 0 +#define CSB_RO 0x00000008 /* Read-Only */ +#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ +#define CSB_AM_SHIFT 8 +#define CSB_BUSW 0x00010000 /* Bus Width Select */ +#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ +#define CSB_AC_SHIFT 24 + +/* + * Chip-Select Option Registers (group C) + */ +#define CSC0_ADDR 0xfffff130 +#define CSC1_ADDR 0xfffff134 +#define CSC2_ADDR 0xfffff138 +#define CSC3_ADDR 0xfffff13c + +#define CSC0 LONG_REF(CSC0_ADDR) +#define CSC1 LONG_REF(CSC1_ADDR) +#define CSC2 LONG_REF(CSC2_ADDR) +#define CSC3 LONG_REF(CSC3_ADDR) + +#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */ +#define CSC_WAIT_SHIFT 0 +#define CSC_RO 0x00000008 /* Read-Only */ +#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ +#define CSC_AM_SHIFT 4 +#define CSC_BUSW 0x00010000 /* Bus Width Select */ +#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ +#define CSC_AC_SHIFT 20 + +/* + * Chip-Select Option Registers (group D) + */ +#define CSD0_ADDR 0xfffff140 +#define CSD1_ADDR 0xfffff144 +#define CSD2_ADDR 0xfffff148 +#define CSD3_ADDR 0xfffff14c + +#define CSD0 LONG_REF(CSD0_ADDR) +#define CSD1 LONG_REF(CSD1_ADDR) +#define CSD2 LONG_REF(CSD2_ADDR) +#define CSD3 LONG_REF(CSD3_ADDR) + +#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */ +#define CSD_WAIT_SHIFT 0 +#define CSD_RO 0x00000008 /* Read-Only */ +#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ +#define CSD_AM_SHIFT 4 +#define CSD_BUSW 0x00010000 /* Bus Width Select */ +#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ +#define CSD_AC_SHIFT 20 + +/********** + * + * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control + * + **********/ + +/* + * PLL Control Register + */ +#define PLLCR_ADDR 0xfffff200 +#define PLLCR WORD_REF(PLLCR_ADDR) + +#define PLLCR_DISPLL 0x0008 /* Disable PLL */ +#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ +#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ +#define PLLCR_SYSCLK_SEL_SHIFT 8 +#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ +#define PLLCR_PIXCLK_SEL_SHIFT 11 + +/* 'EZ328-compatible definitions */ +#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK +#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT + +/* + * PLL Frequency Select Register + */ +#define PLLFSR_ADDR 0xfffff202 +#define PLLFSR WORD_REF(PLLFSR_ADDR) + +#define PLLFSR_PC_MASK 0x00ff /* P Count */ +#define PLLFSR_PC_SHIFT 0 +#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ +#define PLLFSR_QC_SHIFT 8 +#define PLLFSR_PROT 0x4000 /* Protect P & Q */ +#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ + +/* + * Power Control Register + */ +#define PCTRL_ADDR 0xfffff207 +#define PCTRL BYTE_REF(PCTRL_ADDR) + +#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ +#define PCTRL_WIDTH_SHIFT 0 +#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */ +#define PCTRL_PCEN 0x80 /* Power Control Enable */ + +/********** + * + * 0xFFFFF3xx -- Interrupt Controller + * + **********/ + +/* + * Interrupt Vector Register + */ +#define IVR_ADDR 0xfffff300 +#define IVR BYTE_REF(IVR_ADDR) + +#define IVR_VECTOR_MASK 0xF8 + +/* + * Interrupt control Register + */ +#define ICR_ADRR 0xfffff302 +#define ICR WORD_REF(ICR_ADDR) + +#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ +#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ +#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ +#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ +#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ +#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ +#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ +#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ + +/* + * Interrupt Mask Register + */ +#define IMR_ADDR 0xfffff304 +#define IMR LONG_REF(IMR_ADDR) + +/* + * Define the names for bit positions first. This is useful for + * request_irq + */ +#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */ +#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */ +#define UART_IRQ_NUM 2 /* UART interrupt */ +#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ +#define RTC_IRQ_NUM 4 /* RTC interrupt */ +#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ +#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ +#define INT0_IRQ_NUM 8 /* External INT0 */ +#define INT1_IRQ_NUM 9 /* External INT1 */ +#define INT2_IRQ_NUM 10 /* External INT2 */ +#define INT3_IRQ_NUM 11 /* External INT3 */ +#define INT4_IRQ_NUM 12 /* External INT4 */ +#define INT5_IRQ_NUM 13 /* External INT5 */ +#define INT6_IRQ_NUM 14 /* External INT6 */ +#define INT7_IRQ_NUM 15 /* External INT7 */ +#define IRQ1_IRQ_NUM 16 /* IRQ1 */ +#define IRQ2_IRQ_NUM 17 /* IRQ2 */ +#define IRQ3_IRQ_NUM 18 /* IRQ3 */ +#define IRQ6_IRQ_NUM 19 /* IRQ6 */ +#define PEN_IRQ_NUM 20 /* Pen Interrupt */ +#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */ +#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */ +#define IRQ7_IRQ_NUM 23 /* IRQ7 */ + +/* '328-compatible definitions */ +#define SPI_IRQ_NUM SPIM_IRQ_NUM +#define TMR_IRQ_NUM TMR1_IRQ_NUM + +/* + * Here go the bitmasks themselves + */ +#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ +#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ +#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ +#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ +#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ +#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ +#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ +#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ +#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ +#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ +#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ +#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */ +#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */ +#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */ +#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */ +#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ +#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ +#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ +#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ +#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */ +#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */ +#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */ +#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */ + +/* 'EZ328-compatible definitions */ +#define IMR_MSPI IMR_MSPIM +#define IMR_MTMR IMR_MTMR1 + +/* + * Interrupt Wake-Up Enable Register + */ +#define IWR_ADDR 0xfffff308 +#define IWR LONG_REF(IWR_ADDR) + +#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ +#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ +#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ +#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ +#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ +#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ +#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ +#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ +#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ +#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ + +/* + * Interrupt Status Register + */ +#define ISR_ADDR 0xfffff30c +#define ISR LONG_REF(ISR_ADDR) + +#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ +#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ +#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ +#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ +#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ +#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ +#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ +#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ +#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ +#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ + +/* 'EZ328-compatible definitions */ +#define ISR_SPI ISR_SPIM +#define ISR_TMR ISR_TMR1 + +/* + * Interrupt Pending Register + */ +#define IPR_ADDR 0xfffff310 +#define IPR LONG_REF(IPR_ADDR) + +#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ +#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ +#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ +#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ +#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ +#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ +#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ +#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ +#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ +#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ +#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ + +/* 'EZ328-compatible definitions */ +#define IPR_SPI IPR_SPIM +#define IPR_TMR IPR_TMR1 + +/********** + * + * 0xFFFFF4xx -- Parallel Ports + * + **********/ + +/* + * Port A + */ +#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ +#define PADATA_ADDR 0xfffff401 /* Port A data register */ +#define PASEL_ADDR 0xfffff403 /* Port A Select register */ + +#define PADIR BYTE_REF(PADIR_ADDR) +#define PADATA BYTE_REF(PADATA_ADDR) +#define PASEL BYTE_REF(PASEL_ADDR) + +#define PA(x) (1 << (x)) +#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */ + +#define PA_A16 PA(0) /* Use A16 as PA(0) */ +#define PA_A17 PA(1) /* Use A17 as PA(1) */ +#define PA_A18 PA(2) /* Use A18 as PA(2) */ +#define PA_A19 PA(3) /* Use A19 as PA(3) */ +#define PA_A20 PA(4) /* Use A20 as PA(4) */ +#define PA_A21 PA(5) /* Use A21 as PA(5) */ +#define PA_A22 PA(6) /* Use A22 as PA(6) */ +#define PA_A23 PA(7) /* Use A23 as PA(7) */ + +/* + * Port B + */ +#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ +#define PBDATA_ADDR 0xfffff409 /* Port B data register */ +#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ + +#define PBDIR BYTE_REF(PBDIR_ADDR) +#define PBDATA BYTE_REF(PBDATA_ADDR) +#define PBSEL BYTE_REF(PBSEL_ADDR) + +#define PB(x) (1 << (x)) +#define PB_D(x) PB(x) /* This is specific to port B only */ + +#define PB_D0 PB(0) /* Use D0 as PB(0) */ +#define PB_D1 PB(1) /* Use D1 as PB(1) */ +#define PB_D2 PB(2) /* Use D2 as PB(2) */ +#define PB_D3 PB(3) /* Use D3 as PB(3) */ +#define PB_D4 PB(4) /* Use D4 as PB(4) */ +#define PB_D5 PB(5) /* Use D5 as PB(5) */ +#define PB_D6 PB(6) /* Use D6 as PB(6) */ +#define PB_D7 PB(7) /* Use D7 as PB(7) */ + +/* + * Port C + */ +#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ +#define PCDATA_ADDR 0xfffff411 /* Port C data register */ +#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ + +#define PCDIR BYTE_REF(PCDIR_ADDR) +#define PCDATA BYTE_REF(PCDATA_ADDR) +#define PCSEL BYTE_REF(PCSEL_ADDR) + +#define PC(x) (1 << (x)) + +#define PC_WE PC(6) /* Use WE as PC(6) */ +#define PC_DTACK PC(5) /* Use DTACK as PC(5) */ +#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */ +#define PC_LDS PC(2) /* Use LDS as PC(2) */ +#define PC_UDS PC(1) /* Use UDS as PC(1) */ +#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */ + +/* + * Port D + */ +#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ +#define PDDATA_ADDR 0xfffff419 /* Port D data register */ +#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ +#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ +#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ +#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ + +#define PDDIR BYTE_REF(PDDIR_ADDR) +#define PDDATA BYTE_REF(PDDATA_ADDR) +#define PDPUEN BYTE_REF(PDPUEN_ADDR) +#define PDPOL BYTE_REF(PDPOL_ADDR) +#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) +#define PDIQEG BYTE_REF(PDIQEG_ADDR) + +#define PD(x) (1 << (x)) +#define PD_KB(x) PD(x) /* This is specific for Port D only */ + +#define PD_KB0 PD(0) /* Use KB0 as PD(0) */ +#define PD_KB1 PD(1) /* Use KB1 as PD(1) */ +#define PD_KB2 PD(2) /* Use KB2 as PD(2) */ +#define PD_KB3 PD(3) /* Use KB3 as PD(3) */ +#define PD_KB4 PD(4) /* Use KB4 as PD(4) */ +#define PD_KB5 PD(5) /* Use KB5 as PD(5) */ +#define PD_KB6 PD(6) /* Use KB6 as PD(6) */ +#define PD_KB7 PD(7) /* Use KB7 as PD(7) */ + +/* + * Port E + */ +#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ +#define PEDATA_ADDR 0xfffff421 /* Port E data register */ +#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ +#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ + +#define PEDIR BYTE_REF(PEDIR_ADDR) +#define PEDATA BYTE_REF(PEDATA_ADDR) +#define PEPUEN BYTE_REF(PEPUEN_ADDR) +#define PESEL BYTE_REF(PESEL_ADDR) + +#define PE(x) (1 << (x)) + +#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */ +#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */ +#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */ +#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */ +#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */ +#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */ +#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */ + +/* + * Port F + */ +#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ +#define PFDATA_ADDR 0xfffff429 /* Port F data register */ +#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ +#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ + +#define PFDIR BYTE_REF(PFDIR_ADDR) +#define PFDATA BYTE_REF(PFDATA_ADDR) +#define PFPUEN BYTE_REF(PFPUEN_ADDR) +#define PFSEL BYTE_REF(PFSEL_ADDR) + +#define PF(x) (1 << (x)) +#define PF_A(x) PF((x) - 24) /* This is Port F specific only */ + +#define PF_A24 PF(0) /* Use A24 as PF(0) */ +#define PF_A25 PF(1) /* Use A25 as PF(1) */ +#define PF_A26 PF(2) /* Use A26 as PF(2) */ +#define PF_A27 PF(3) /* Use A27 as PF(3) */ +#define PF_A28 PF(4) /* Use A28 as PF(4) */ +#define PF_A29 PF(5) /* Use A29 as PF(5) */ +#define PF_A30 PF(6) /* Use A30 as PF(6) */ +#define PF_A31 PF(7) /* Use A31 as PF(7) */ + +/* + * Port G + */ +#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ +#define PGDATA_ADDR 0xfffff431 /* Port G data register */ +#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ +#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ + +#define PGDIR BYTE_REF(PGDIR_ADDR) +#define PGDATA BYTE_REF(PGDATA_ADDR) +#define PGPUEN BYTE_REF(PGPUEN_ADDR) +#define PGSEL BYTE_REF(PGSEL_ADDR) + +#define PG(x) (1 << (x)) + +#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */ +#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */ +#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */ +#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */ +#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */ +#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */ +#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */ +#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */ + +/* + * Port J + */ +#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ +#define PJDATA_ADDR 0xfffff439 /* Port J data register */ +#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */ + +#define PJDIR BYTE_REF(PJDIR_ADDR) +#define PJDATA BYTE_REF(PJDATA_ADDR) +#define PJSEL BYTE_REF(PJSEL_ADDR) + +#define PJ(x) (1 << (x)) + +#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */ + +/* + * Port K + */ +#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ +#define PKDATA_ADDR 0xfffff441 /* Port K data register */ +#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */ +#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ + +#define PKDIR BYTE_REF(PKDIR_ADDR) +#define PKDATA BYTE_REF(PKDATA_ADDR) +#define PKPUEN BYTE_REF(PKPUEN_ADDR) +#define PKSEL BYTE_REF(PKSEL_ADDR) + +#define PK(x) (1 << (x)) + +/* + * Port M + */ +#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */ +#define PMDATA_ADDR 0xfffff439 /* Port M data register */ +#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */ +#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */ + +#define PMDIR BYTE_REF(PMDIR_ADDR) +#define PMDATA BYTE_REF(PMDATA_ADDR) +#define PMPUEN BYTE_REF(PMPUEN_ADDR) +#define PMSEL BYTE_REF(PMSEL_ADDR) + +#define PM(x) (1 << (x)) + +/********** + * + * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) + * + **********/ + +/* + * PWM Control Register + */ +#define PWMC_ADDR 0xfffff500 +#define PWMC WORD_REF(PWMC_ADDR) + +#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */ +#define PWMC_CLKSEL_SHIFT 0 +#define PWMC_PWMEN 0x0010 /* Enable PWM */ +#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */ +#define PWMC_PIN 0x0080 /* Current PWM output pin status */ +#define PWMC_LOAD 0x0100 /* Force a new period */ +#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */ +#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ + +/* 'EZ328-compatible definitions */ +#define PWMC_EN PWMC_PWMEN + +/* + * PWM Period Register + */ +#define PWMP_ADDR 0xfffff502 +#define PWMP WORD_REF(PWMP_ADDR) + +/* + * PWM Width Register + */ +#define PWMW_ADDR 0xfffff504 +#define PWMW WORD_REF(PWMW_ADDR) + +/* + * PWM Counter Register + */ +#define PWMCNT_ADDR 0xfffff506 +#define PWMCNT WORD_REF(PWMCNT_ADDR) + +/********** + * + * 0xFFFFF6xx -- General-Purpose Timers + * + **********/ + +/* + * Timer Unit 1 and 2 Control Registers + */ +#define TCTL1_ADDR 0xfffff600 +#define TCTL1 WORD_REF(TCTL1_ADDR) +#define TCTL2_ADDR 0xfffff60c +#define TCTL2 WORD_REF(TCTL2_ADDR) + +#define TCTL_TEN 0x0001 /* Timer Enable */ +#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ +#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ +#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ +#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ +#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ +#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ +#define TCTL_IRQEN 0x0010 /* IRQ Enable */ +#define TCTL_OM 0x0020 /* Output Mode */ +#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ +#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ +#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ +#define TCTL_FRR 0x0010 /* Free-Run Mode */ + +/* 'EZ328-compatible definitions */ +#define TCTL_ADDR TCTL1_ADDR +#define TCTL TCTL1 + +/* + * Timer Unit 1 and 2 Prescaler Registers + */ +#define TPRER1_ADDR 0xfffff602 +#define TPRER1 WORD_REF(TPRER1_ADDR) +#define TPRER2_ADDR 0xfffff60e +#define TPRER2 WORD_REF(TPRER2_ADDR) + +/* 'EZ328-compatible definitions */ +#define TPRER_ADDR TPRER1_ADDR +#define TPRER TPRER1 + +/* + * Timer Unit 1 and 2 Compare Registers + */ +#define TCMP1_ADDR 0xfffff604 +#define TCMP1 WORD_REF(TCMP1_ADDR) +#define TCMP2_ADDR 0xfffff610 +#define TCMP2 WORD_REF(TCMP2_ADDR) + +/* 'EZ328-compatible definitions */ +#define TCMP_ADDR TCMP1_ADDR +#define TCMP TCMP1 + +/* + * Timer Unit 1 and 2 Capture Registers + */ +#define TCR1_ADDR 0xfffff606 +#define TCR1 WORD_REF(TCR1_ADDR) +#define TCR2_ADDR 0xfffff612 +#define TCR2 WORD_REF(TCR2_ADDR) + +/* 'EZ328-compatible definitions */ +#define TCR_ADDR TCR1_ADDR +#define TCR TCR1 + +/* + * Timer Unit 1 and 2 Counter Registers + */ +#define TCN1_ADDR 0xfffff608 +#define TCN1 WORD_REF(TCN1_ADDR) +#define TCN2_ADDR 0xfffff614 +#define TCN2 WORD_REF(TCN2_ADDR) + +/* 'EZ328-compatible definitions */ +#define TCN_ADDR TCN1_ADDR +#define TCN TCN + +/* + * Timer Unit 1 and 2 Status Registers + */ +#define TSTAT1_ADDR 0xfffff60a +#define TSTAT1 WORD_REF(TSTAT1_ADDR) +#define TSTAT2_ADDR 0xfffff616 +#define TSTAT2 WORD_REF(TSTAT2_ADDR) + +#define TSTAT_COMP 0x0001 /* Compare Event occurred */ +#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ + +/* 'EZ328-compatible definitions */ +#define TSTAT_ADDR TSTAT1_ADDR +#define TSTAT TSTAT1 + +/* + * Watchdog Compare Register + */ +#define WRR_ADDR 0xfffff61a +#define WRR WORD_REF(WRR_ADDR) + +/* + * Watchdog Counter Register + */ +#define WCN_ADDR 0xfffff61c +#define WCN WORD_REF(WCN_ADDR) + +/* + * Watchdog Control and Status Register + */ +#define WCSR_ADDR 0xfffff618 +#define WCSR WORD_REF(WCSR_ADDR) + +#define WCSR_WDEN 0x0001 /* Watchdog Enable */ +#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/ +#define WCSR_WRST 0x0004 /* Watchdog Reset */ + +/********** + * + * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS) + * + **********/ + +/* + * SPI Slave Register + */ +#define SPISR_ADDR 0xfffff700 +#define SPISR WORD_REF(SPISR_ADDR) + +#define SPISR_DATA_ADDR 0xfffff701 +#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR) + +#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */ +#define SPISR_DATA_SHIFT 0 +#define SPISR_SPISEN 0x0100 /* SPIS module enable */ +#define SPISR_POL 0x0200 /* SPSCLK polarity control */ +#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */ +#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */ +#define SPISR_DATARDY 0x1000 /* Data ready */ +#define SPISR_ENPOL 0x2000 /* Enable Polarity */ +#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */ +#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */ + +/********** + * + * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) + * + **********/ + +/* + * SPIM Data Register + */ +#define SPIMDATA_ADDR 0xfffff800 +#define SPIMDATA WORD_REF(SPIMDATA_ADDR) + +/* + * SPIM Control/Status Register + */ +#define SPIMCONT_ADDR 0xfffff802 +#define SPIMCONT WORD_REF(SPIMCONT_ADDR) + +#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ +#define SPIMCONT_BIT_COUNT_SHIFT 0 +#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ +#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ +#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ +#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */ +#define SPIMCONT_XCH 0x0100 /* Exchange */ +#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */ +#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ +#define SPIMCONT_DATA_RATE_SHIFT 13 + +/* 'EZ328-compatible definitions */ +#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ +#define SPIMCONT_ENABLE SPIMCONT_SPIMEN +/********** + * + * 0xFFFFF9xx -- UART + * + **********/ + +/* + * UART Status/Control Register + */ +#define USTCNT_ADDR 0xfffff900 +#define USTCNT WORD_REF(USTCNT_ADDR) + +#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */ +#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */ +#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */ +#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */ +#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */ +#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */ +#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */ +#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */ +#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ +#define USTCNT_STOP 0x0200 /* Stop bit transmission */ +#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */ +#define USTCNT_PARITYEN 0x0800 /* Parity Enable */ +#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */ +#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ +#define USTCNT_RXEN 0x4000 /* Receiver Enable */ +#define USTCNT_UARTEN 0x8000 /* UART Enable */ + +/* 'EZ328-compatible definitions */ +#define USTCNT_TXAE USTCNT_TXAVAILEN +#define USTCNT_TXHE USTCNT_TXHALFEN +#define USTCNT_TXEE USTCNT_TXEMPTYEN +#define USTCNT_RXRE USTCNT_RXREADYEN +#define USTCNT_RXHE USTCNT_RXHALFEN +#define USTCNT_RXFE USTCNT_RXFULLEN +#define USTCNT_CTSD USTCNT_CTSDELTAEN +#define USTCNT_ODD USTCNT_ODD_EVEN +#define USTCNT_PEN USTCNT_PARITYEN +#define USTCNT_CLKM USTCNT_CLKMODE +#define USTCNT_UEN USTCNT_UARTEN + +/* + * UART Baud Control Register + */ +#define UBAUD_ADDR 0xfffff902 +#define UBAUD WORD_REF(UBAUD_ADDR) + +#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ +#define UBAUD_PRESCALER_SHIFT 0 +#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ +#define UBAUD_DIVIDE_SHIFT 8 +#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ +#define UBAUD_GPIOSRC 0x1000 /* GPIO source */ +#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */ +#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */ +#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */ + +/* + * UART Receiver Register + */ +#define URX_ADDR 0xfffff904 +#define URX WORD_REF(URX_ADDR) + +#define URX_RXDATA_ADDR 0xfffff905 +#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) + +#define URX_RXDATA_MASK 0x00ff /* Received data */ +#define URX_RXDATA_SHIFT 0 +#define URX_PARITY_ERROR 0x0100 /* Parity Error */ +#define URX_BREAK 0x0200 /* Break Detected */ +#define URX_FRAME_ERROR 0x0400 /* Framing Error */ +#define URX_OVRUN 0x0800 /* Serial Overrun */ +#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ +#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ +#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ + +/* + * UART Transmitter Register + */ +#define UTX_ADDR 0xfffff906 +#define UTX WORD_REF(UTX_ADDR) + +#define UTX_TXDATA_ADDR 0xfffff907 +#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) + +#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ +#define UTX_TXDATA_SHIFT 0 +#define UTX_CTS_DELTA 0x0100 /* CTS changed */ +#define UTX_CTS_STATUS 0x0200 /* CTS State */ +#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */ +#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ +#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ +#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ +#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ + +/* 'EZ328-compatible definitions */ +#define UTX_CTS_STAT UTX_CTS_STATUS +#define UTX_NOCTS UTX_IGNORE_CTS + +/* + * UART Miscellaneous Register + */ +#define UMISC_ADDR 0xfffff908 +#define UMISC WORD_REF(UMISC_ADDR) + +#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ +#define UMISC_RX_POL 0x0008 /* Receive Polarity */ +#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ +#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ +#define UMISC_RTS 0x0040 /* Set RTS status */ +#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ +#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ +#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ +#define UMISC_CLKSRC 0x4000 /* Clock Source */ + + +/* generalization of uart control registers to support multiple ports: */ +typedef volatile struct { + volatile unsigned short int ustcnt; + volatile unsigned short int ubaud; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char rxdata; + } b; + } urx; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char txdata; + } b; + } utx; + volatile unsigned short int umisc; + volatile unsigned short int pad1; + volatile unsigned short int pad2; + volatile unsigned short int pad3; +} __attribute__((packed)) m68328_uart; + + +/********** + * + * 0xFFFFFAxx -- LCD Controller + * + **********/ + +/* + * LCD Screen Starting Address Register + */ +#define LSSA_ADDR 0xfffffa00 +#define LSSA LONG_REF(LSSA_ADDR) + +#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */ + +/* + * LCD Virtual Page Width Register + */ +#define LVPW_ADDR 0xfffffa05 +#define LVPW BYTE_REF(LVPW_ADDR) + +/* + * LCD Screen Width Register (not compatible with 'EZ328 !!!) + */ +#define LXMAX_ADDR 0xfffffa08 +#define LXMAX WORD_REF(LXMAX_ADDR) + +#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */ + +/* + * LCD Screen Height Register + */ +#define LYMAX_ADDR 0xfffffa0a +#define LYMAX WORD_REF(LYMAX_ADDR) + +#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */ + +/* + * LCD Cursor X Position Register + */ +#define LCXP_ADDR 0xfffffa18 +#define LCXP WORD_REF(LCXP_ADDR) + +#define LCXP_CC_MASK 0xc000 /* Cursor Control */ +#define LCXP_CC_TRAMSPARENT 0x0000 +#define LCXP_CC_BLACK 0x4000 +#define LCXP_CC_REVERSED 0x8000 +#define LCXP_CC_WHITE 0xc000 +#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ + +/* + * LCD Cursor Y Position Register + */ +#define LCYP_ADDR 0xfffffa1a +#define LCYP WORD_REF(LCYP_ADDR) + +#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ + +/* + * LCD Cursor Width and Heigth Register + */ +#define LCWCH_ADDR 0xfffffa1c +#define LCWCH WORD_REF(LCWCH_ADDR) + +#define LCWCH_CH_MASK 0x001f /* Cursor Height */ +#define LCWCH_CH_SHIFT 0 +#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ +#define LCWCH_CW_SHIFT 8 + +/* + * LCD Blink Control Register + */ +#define LBLKC_ADDR 0xfffffa1f +#define LBLKC BYTE_REF(LBLKC_ADDR) + +#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ +#define LBLKC_BD_SHIFT 0 +#define LBLKC_BKEN 0x80 /* Blink Enabled */ + +/* + * LCD Panel Interface Configuration Register + */ +#define LPICF_ADDR 0xfffffa20 +#define LPICF BYTE_REF(LPICF_ADDR) + +#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */ +#define LPICF_GS_BW 0x00 +#define LPICF_GS_GRAY_4 0x01 +#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */ +#define LPICF_PBSIZ_1 0x00 +#define LPICF_PBSIZ_2 0x02 +#define LPICF_PBSIZ_4 0x04 + +/* + * LCD Polarity Configuration Register + */ +#define LPOLCF_ADDR 0xfffffa21 +#define LPOLCF BYTE_REF(LPOLCF_ADDR) + +#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ +#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ +#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ +#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ + +/* + * LACD (LCD Alternate Crystal Direction) Rate Control Register + */ +#define LACDRC_ADDR 0xfffffa23 +#define LACDRC BYTE_REF(LACDRC_ADDR) + +#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ +#define LACDRC_ACD_SHIFT 0 + +/* + * LCD Pixel Clock Divider Register + */ +#define LPXCD_ADDR 0xfffffa25 +#define LPXCD BYTE_REF(LPXCD_ADDR) + +#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ +#define LPXCD_PCD_SHIFT 0 + +/* + * LCD Clocking Control Register + */ +#define LCKCON_ADDR 0xfffffa27 +#define LCKCON BYTE_REF(LCKCON_ADDR) + +#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */ +#define LCKCON_DWIDTH 0x02 /* Display Memory Width */ +#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */ +#define LCKCON_DWS_SHIFT 2 +#define LCKCON_DMA16 0x40 /* DMA burst length */ +#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ + +/* 'EZ328-compatible definitions */ +#define LCKCON_DW_MASK LCKCON_DWS_MASK +#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT + +/* + * LCD Last Buffer Address Register + */ +#define LLBAR_ADDR 0xfffffa29 +#define LLBAR BYTE_REF(LLBAR_ADDR) + +#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */ +#define LLBAR_LBAR_SHIFT 0 + +/* + * LCD Octet Terminal Count Register + */ +#define LOTCR_ADDR 0xfffffa2b +#define LOTCR BYTE_REF(LOTCR_ADDR) + +/* + * LCD Panning Offset Register + */ +#define LPOSR_ADDR 0xfffffa2d +#define LPOSR BYTE_REF(LPOSR_ADDR) + +#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */ +#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */ +#define LPOSR_POS_SHIFT 0 + +/* + * LCD Frame Rate Control Modulation Register + */ +#define LFRCM_ADDR 0xfffffa31 +#define LFRCM BYTE_REF(LFRCM_ADDR) + +#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ +#define LFRCM_YMOD_SHIFT 0 +#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ +#define LFRCM_XMOD_SHIFT 4 + +/* + * LCD Gray Palette Mapping Register + */ +#define LGPMR_ADDR 0xfffffa32 +#define LGPMR WORD_REF(LGPMR_ADDR) + +#define LGPMR_GLEVEL3_MASK 0x000f +#define LGPMR_GLEVEL3_SHIFT 0 +#define LGPMR_GLEVEL2_MASK 0x00f0 +#define LGPMR_GLEVEL2_SHIFT 4 +#define LGPMR_GLEVEL0_MASK 0x0f00 +#define LGPMR_GLEVEL0_SHIFT 8 +#define LGPMR_GLEVEL1_MASK 0xf000 +#define LGPMR_GLEVEL1_SHIFT 12 + +/********** + * + * 0xFFFFFBxx -- Real-Time Clock (RTC) + * + **********/ + +/* + * RTC Hours Minutes and Seconds Register + */ +#define RTCTIME_ADDR 0xfffffb00 +#define RTCTIME LONG_REF(RTCTIME_ADDR) + +#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCTIME_SECONDS_SHIFT 0 +#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCTIME_MINUTES_SHIFT 16 +#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCTIME_HOURS_SHIFT 24 + +/* + * RTC Alarm Register + */ +#define RTCALRM_ADDR 0xfffffb04 +#define RTCALRM LONG_REF(RTCALRM_ADDR) + +#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCALRM_SECONDS_SHIFT 0 +#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCALRM_MINUTES_SHIFT 16 +#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCALRM_HOURS_SHIFT 24 + +/* + * RTC Control Register + */ +#define RTCCTL_ADDR 0xfffffb0c +#define RTCCTL WORD_REF(RTCCTL_ADDR) + +#define RTCCTL_384 0x0020 /* Crystal Selection */ +#define RTCCTL_ENABLE 0x0080 /* RTC Enable */ + +/* 'EZ328-compatible definitions */ +#define RTCCTL_XTL RTCCTL_384 +#define RTCCTL_EN RTCCTL_ENABLE + +/* + * RTC Interrupt Status Register + */ +#define RTCISR_ADDR 0xfffffb0e +#define RTCISR WORD_REF(RTCISR_ADDR) + +#define RTCISR_SW 0x0001 /* Stopwatch timed out */ +#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ +#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ +#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ +#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ + +/* + * RTC Interrupt Enable Register + */ +#define RTCIENR_ADDR 0xfffffb10 +#define RTCIENR WORD_REF(RTCIENR_ADDR) + +#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ +#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ +#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ +#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ +#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ + +/* + * Stopwatch Minutes Register + */ +#define STPWCH_ADDR 0xfffffb12 +#define STPWCH WORD_REF(STPWCH) + +#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */ +#define SPTWCH_CNT_SHIFT 0 + +#endif /* _MC68328_H_ */ diff --git a/arch/m68knommu/include/asm/MC68332.h b/arch/m68knommu/include/asm/MC68332.h new file mode 100644 index 000000000000..6bb8f02685a2 --- /dev/null +++ b/arch/m68knommu/include/asm/MC68332.h @@ -0,0 +1,152 @@ + +/* include/asm-m68knommu/MC68332.h: '332 control registers + * + * Copyright (C) 1998 Kenneth Albanowski , + * + */ + +#ifndef _MC68332_H_ +#define _MC68332_H_ + +#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) +#define WORD_REF(addr) (*((volatile unsigned short*)addr)) + +#define PORTE_ADDR 0xfffa11 +#define PORTE BYTE_REF(PORTE_ADDR) +#define DDRE_ADDR 0xfffa15 +#define DDRE BYTE_REF(DDRE_ADDR) +#define PEPAR_ADDR 0xfffa17 +#define PEPAR BYTE_REF(PEPAR_ADDR) + +#define PORTF_ADDR 0xfffa19 +#define PORTF BYTE_REF(PORTF_ADDR) +#define DDRF_ADDR 0xfffa1d +#define DDRF BYTE_REF(DDRF_ADDR) +#define PFPAR_ADDR 0xfffa1f +#define PFPAR BYTE_REF(PFPAR_ADDR) + +#define PORTQS_ADDR 0xfffc15 +#define PORTQS BYTE_REF(PORTQS_ADDR) +#define DDRQS_ADDR 0xfffc17 +#define DDRQS BYTE_REF(DDRQS_ADDR) +#define PQSPAR_ADDR 0xfffc16 +#define PQSPAR BYTE_REF(PQSPAR_ADDR) + +#define CSPAR0_ADDR 0xFFFA44 +#define CSPAR0 WORD_REF(CSPAR0_ADDR) +#define CSPAR1_ADDR 0xFFFA46 +#define CSPAR1 WORD_REF(CSPAR1_ADDR) +#define CSARBT_ADDR 0xFFFA48 +#define CSARBT WORD_REF(CSARBT_ADDR) +#define CSOPBT_ADDR 0xFFFA4A +#define CSOPBT WORD_REF(CSOPBT_ADDR) +#define CSBAR0_ADDR 0xFFFA4C +#define CSBAR0 WORD_REF(CSBAR0_ADDR) +#define CSOR0_ADDR 0xFFFA4E +#define CSOR0 WORD_REF(CSOR0_ADDR) +#define CSBAR1_ADDR 0xFFFA50 +#define CSBAR1 WORD_REF(CSBAR1_ADDR) +#define CSOR1_ADDR 0xFFFA52 +#define CSOR1 WORD_REF(CSOR1_ADDR) +#define CSBAR2_ADDR 0xFFFA54 +#define CSBAR2 WORD_REF(CSBAR2_ADDR) +#define CSOR2_ADDR 0xFFFA56 +#define CSOR2 WORD_REF(CSOR2_ADDR) +#define CSBAR3_ADDR 0xFFFA58 +#define CSBAR3 WORD_REF(CSBAR3_ADDR) +#define CSOR3_ADDR 0xFFFA5A +#define CSOR3 WORD_REF(CSOR3_ADDR) +#define CSBAR4_ADDR 0xFFFA5C +#define CSBAR4 WORD_REF(CSBAR4_ADDR) +#define CSOR4_ADDR 0xFFFA5E +#define CSOR4 WORD_REF(CSOR4_ADDR) +#define CSBAR5_ADDR 0xFFFA60 +#define CSBAR5 WORD_REF(CSBAR5_ADDR) +#define CSOR5_ADDR 0xFFFA62 +#define CSOR5 WORD_REF(CSOR5_ADDR) +#define CSBAR6_ADDR 0xFFFA64 +#define CSBAR6 WORD_REF(CSBAR6_ADDR) +#define CSOR6_ADDR 0xFFFA66 +#define CSOR6 WORD_REF(CSOR6_ADDR) +#define CSBAR7_ADDR 0xFFFA68 +#define CSBAR7 WORD_REF(CSBAR7_ADDR) +#define CSOR7_ADDR 0xFFFA6A +#define CSOR7 WORD_REF(CSOR7_ADDR) +#define CSBAR8_ADDR 0xFFFA6C +#define CSBAR8 WORD_REF(CSBAR8_ADDR) +#define CSOR8_ADDR 0xFFFA6E +#define CSOR8 WORD_REF(CSOR8_ADDR) +#define CSBAR9_ADDR 0xFFFA70 +#define CSBAR9 WORD_REF(CSBAR9_ADDR) +#define CSOR9_ADDR 0xFFFA72 +#define CSOR9 WORD_REF(CSOR9_ADDR) +#define CSBAR10_ADDR 0xFFFA74 +#define CSBAR10 WORD_REF(CSBAR10_ADDR) +#define CSOR10_ADDR 0xFFFA76 +#define CSOR10 WORD_REF(CSOR10_ADDR) + +#define CSOR_MODE_ASYNC 0x0000 +#define CSOR_MODE_SYNC 0x8000 +#define CSOR_MODE_MASK 0x8000 +#define CSOR_BYTE_DISABLE 0x0000 +#define CSOR_BYTE_UPPER 0x4000 +#define CSOR_BYTE_LOWER 0x2000 +#define CSOR_BYTE_BOTH 0x6000 +#define CSOR_BYTE_MASK 0x6000 +#define CSOR_RW_RSVD 0x0000 +#define CSOR_RW_READ 0x0800 +#define CSOR_RW_WRITE 0x1000 +#define CSOR_RW_BOTH 0x1800 +#define CSOR_RW_MASK 0x1800 +#define CSOR_STROBE_DS 0x0400 +#define CSOR_STROBE_AS 0x0000 +#define CSOR_STROBE_MASK 0x0400 +#define CSOR_DSACK_WAIT(x) (wait << 6) +#define CSOR_DSACK_FTERM (14 << 6) +#define CSOR_DSACK_EXTERNAL (15 << 6) +#define CSOR_DSACK_MASK 0x03c0 +#define CSOR_SPACE_CPU 0x0000 +#define CSOR_SPACE_USER 0x0010 +#define CSOR_SPACE_SU 0x0020 +#define CSOR_SPACE_BOTH 0x0030 +#define CSOR_SPACE_MASK 0x0030 +#define CSOR_IPL_ALL 0x0000 +#define CSOR_IPL_PRIORITY(x) (x << 1) +#define CSOR_IPL_MASK 0x000e +#define CSOR_AVEC_ON 0x0001 +#define CSOR_AVEC_OFF 0x0000 +#define CSOR_AVEC_MASK 0x0001 + +#define CSBAR_ADDR(x) ((addr >> 11) << 3) +#define CSBAR_ADDR_MASK 0xfff8 +#define CSBAR_BLKSIZE_2K 0x0000 +#define CSBAR_BLKSIZE_8K 0x0001 +#define CSBAR_BLKSIZE_16K 0x0002 +#define CSBAR_BLKSIZE_64K 0x0003 +#define CSBAR_BLKSIZE_128K 0x0004 +#define CSBAR_BLKSIZE_256K 0x0005 +#define CSBAR_BLKSIZE_512K 0x0006 +#define CSBAR_BLKSIZE_1M 0x0007 +#define CSBAR_BLKSIZE_MASK 0x0007 + +#define CSPAR_DISC 0 +#define CSPAR_ALT 1 +#define CSPAR_CS8 2 +#define CSPAR_CS16 3 +#define CSPAR_MASK 3 + +#define CSPAR0_CSBOOT(x) (x << 0) +#define CSPAR0_CS0(x) (x << 2) +#define CSPAR0_CS1(x) (x << 4) +#define CSPAR0_CS2(x) (x << 6) +#define CSPAR0_CS3(x) (x << 8) +#define CSPAR0_CS4(x) (x << 10) +#define CSPAR0_CS5(x) (x << 12) + +#define CSPAR1_CS6(x) (x << 0) +#define CSPAR1_CS7(x) (x << 2) +#define CSPAR1_CS8(x) (x << 4) +#define CSPAR1_CS9(x) (x << 6) +#define CSPAR1_CS10(x) (x << 8) + +#endif diff --git a/arch/m68knommu/include/asm/MC68EZ328.h b/arch/m68knommu/include/asm/MC68EZ328.h new file mode 100644 index 000000000000..69b7f9139e5e --- /dev/null +++ b/arch/m68knommu/include/asm/MC68EZ328.h @@ -0,0 +1,1253 @@ + +/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers + * + * Copyright (C) 1999 Vladimir Gurevich + * Bear & Hare Software, Inc. + * + * Based on include/asm-m68knommu/MC68332.h + * Copyright (C) 1998 Kenneth Albanowski , + * The Silver Hammer Group, Ltd. + * + */ + +#ifndef _MC68EZ328_H_ +#define _MC68EZ328_H_ + +#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) +#define WORD_REF(addr) (*((volatile unsigned short*)addr)) +#define LONG_REF(addr) (*((volatile unsigned long*)addr)) + +#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) +#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) + +/********** + * + * 0xFFFFF0xx -- System Control + * + **********/ + +/* + * System Control Register (SCR) + */ +#define SCR_ADDR 0xfffff000 +#define SCR BYTE_REF(SCR_ADDR) + +#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ +#define SCR_DMAP 0x04 /* Double Map */ +#define SCR_SO 0x08 /* Supervisor Only */ +#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ +#define SCR_PRV 0x20 /* Privilege Violation */ +#define SCR_WPV 0x40 /* Write Protect Violation */ +#define SCR_BETO 0x80 /* Bus-Error TimeOut */ + +/* + * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) + */ +#define MRR_ADDR 0xfffff004 +#define MRR LONG_REF(MRR_ADDR) + +/********** + * + * 0xFFFFF1xx -- Chip-Select logic + * + **********/ + +/* + * Chip Select Group Base Registers + */ +#define CSGBA_ADDR 0xfffff100 +#define CSGBB_ADDR 0xfffff102 + +#define CSGBC_ADDR 0xfffff104 +#define CSGBD_ADDR 0xfffff106 + +#define CSGBA WORD_REF(CSGBA_ADDR) +#define CSGBB WORD_REF(CSGBB_ADDR) +#define CSGBC WORD_REF(CSGBC_ADDR) +#define CSGBD WORD_REF(CSGBD_ADDR) + +/* + * Chip Select Registers + */ +#define CSA_ADDR 0xfffff110 +#define CSB_ADDR 0xfffff112 +#define CSC_ADDR 0xfffff114 +#define CSD_ADDR 0xfffff116 + +#define CSA WORD_REF(CSA_ADDR) +#define CSB WORD_REF(CSB_ADDR) +#define CSC WORD_REF(CSC_ADDR) +#define CSD WORD_REF(CSD_ADDR) + +#define CSA_EN 0x0001 /* Chip-Select Enable */ +#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSA_SIZ_SHIFT 1 +#define CSA_WS_MASK 0x0070 /* Wait State */ +#define CSA_WS_SHIFT 4 +#define CSA_BSW 0x0080 /* Data Bus Width */ +#define CSA_FLASH 0x0100 /* FLASH Memory Support */ +#define CSA_RO 0x8000 /* Read-Only */ + +#define CSB_EN 0x0001 /* Chip-Select Enable */ +#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSB_SIZ_SHIFT 1 +#define CSB_WS_MASK 0x0070 /* Wait State */ +#define CSB_WS_SHIFT 4 +#define CSB_BSW 0x0080 /* Data Bus Width */ +#define CSB_FLASH 0x0100 /* FLASH Memory Support */ +#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSB_UPSIZ_SHIFT 11 +#define CSB_ROP 0x2000 /* Readonly if protected */ +#define CSB_SOP 0x4000 /* Supervisor only if protected */ +#define CSB_RO 0x8000 /* Read-Only */ + +#define CSC_EN 0x0001 /* Chip-Select Enable */ +#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSC_SIZ_SHIFT 1 +#define CSC_WS_MASK 0x0070 /* Wait State */ +#define CSC_WS_SHIFT 4 +#define CSC_BSW 0x0080 /* Data Bus Width */ +#define CSC_FLASH 0x0100 /* FLASH Memory Support */ +#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSC_UPSIZ_SHIFT 11 +#define CSC_ROP 0x2000 /* Readonly if protected */ +#define CSC_SOP 0x4000 /* Supervisor only if protected */ +#define CSC_RO 0x8000 /* Read-Only */ + +#define CSD_EN 0x0001 /* Chip-Select Enable */ +#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSD_SIZ_SHIFT 1 +#define CSD_WS_MASK 0x0070 /* Wait State */ +#define CSD_WS_SHIFT 4 +#define CSD_BSW 0x0080 /* Data Bus Width */ +#define CSD_FLASH 0x0100 /* FLASH Memory Support */ +#define CSD_DRAM 0x0200 /* Dram Selection */ +#define CSD_COMB 0x0400 /* Combining */ +#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSD_UPSIZ_SHIFT 11 +#define CSD_ROP 0x2000 /* Readonly if protected */ +#define CSD_SOP 0x4000 /* Supervisor only if protected */ +#define CSD_RO 0x8000 /* Read-Only */ + +/* + * Emulation Chip-Select Register + */ +#define EMUCS_ADDR 0xfffff118 +#define EMUCS WORD_REF(EMUCS_ADDR) + +#define EMUCS_WS_MASK 0x0070 +#define EMUCS_WS_SHIFT 4 + +/********** + * + * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control + * + **********/ + +/* + * PLL Control Register + */ +#define PLLCR_ADDR 0xfffff200 +#define PLLCR WORD_REF(PLLCR_ADDR) + +#define PLLCR_DISPLL 0x0008 /* Disable PLL */ +#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ +#define PLLCR_PRESC 0x0020 /* VCO prescaler */ +#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ +#define PLLCR_SYSCLK_SEL_SHIFT 8 +#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ +#define PLLCR_LCDCLK_SEL_SHIFT 11 + +/* '328-compatible definitions */ +#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK +#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT + +/* + * PLL Frequency Select Register + */ +#define PLLFSR_ADDR 0xfffff202 +#define PLLFSR WORD_REF(PLLFSR_ADDR) + +#define PLLFSR_PC_MASK 0x00ff /* P Count */ +#define PLLFSR_PC_SHIFT 0 +#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ +#define PLLFSR_QC_SHIFT 8 +#define PLLFSR_PROT 0x4000 /* Protect P & Q */ +#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ + +/* + * Power Control Register + */ +#define PCTRL_ADDR 0xfffff207 +#define PCTRL BYTE_REF(PCTRL_ADDR) + +#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ +#define PCTRL_WIDTH_SHIFT 0 +#define PCTRL_PCEN 0x80 /* Power Control Enable */ + +/********** + * + * 0xFFFFF3xx -- Interrupt Controller + * + **********/ + +/* + * Interrupt Vector Register + */ +#define IVR_ADDR 0xfffff300 +#define IVR BYTE_REF(IVR_ADDR) + +#define IVR_VECTOR_MASK 0xF8 + +/* + * Interrupt control Register + */ +#define ICR_ADDR 0xfffff302 +#define ICR WORD_REF(ICR_ADDR) + +#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ +#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ +#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ +#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ +#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ +#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ +#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ +#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ +#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ + +/* + * Interrupt Mask Register + */ +#define IMR_ADDR 0xfffff304 +#define IMR LONG_REF(IMR_ADDR) + +/* + * Define the names for bit positions first. This is useful for + * request_irq + */ +#define SPI_IRQ_NUM 0 /* SPI interrupt */ +#define TMR_IRQ_NUM 1 /* Timer interrupt */ +#define UART_IRQ_NUM 2 /* UART interrupt */ +#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ +#define RTC_IRQ_NUM 4 /* RTC interrupt */ +#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ +#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ +#define INT0_IRQ_NUM 8 /* External INT0 */ +#define INT1_IRQ_NUM 9 /* External INT1 */ +#define INT2_IRQ_NUM 10 /* External INT2 */ +#define INT3_IRQ_NUM 11 /* External INT3 */ +#define IRQ1_IRQ_NUM 16 /* IRQ1 */ +#define IRQ2_IRQ_NUM 17 /* IRQ2 */ +#define IRQ3_IRQ_NUM 18 /* IRQ3 */ +#define IRQ6_IRQ_NUM 19 /* IRQ6 */ +#define IRQ5_IRQ_NUM 20 /* IRQ5 */ +#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ +#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ + +/* '328-compatible definitions */ +#define SPIM_IRQ_NUM SPI_IRQ_NUM +#define TMR1_IRQ_NUM TMR_IRQ_NUM + +/* + * Here go the bitmasks themselves + */ +#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ +#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ +#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ +#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ +#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ +#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ +#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ +#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ +#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ +#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ +#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ +#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ +#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ +#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ +#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ +#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ +#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ +#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ + +/* '328-compatible definitions */ +#define IMR_MSPIM IMR_MSPI +#define IMR_MTMR1 IMR_MTMR + +/* + * Interrupt Status Register + */ +#define ISR_ADDR 0xfffff30c +#define ISR LONG_REF(ISR_ADDR) + +#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ +#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ +#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ +#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ +#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ +#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ + +/* '328-compatible definitions */ +#define ISR_SPIM ISR_SPI +#define ISR_TMR1 ISR_TMR + +/* + * Interrupt Pending Register + */ +#define IPR_ADDR 0xfffff30c +#define IPR LONG_REF(IPR_ADDR) + +#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ +#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ +#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ +#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ +#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ +#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ + +/* '328-compatible definitions */ +#define IPR_SPIM IPR_SPI +#define IPR_TMR1 IPR_TMR + +/********** + * + * 0xFFFFF4xx -- Parallel Ports + * + **********/ + +/* + * Port A + */ +#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ +#define PADATA_ADDR 0xfffff401 /* Port A data register */ +#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ + +#define PADIR BYTE_REF(PADIR_ADDR) +#define PADATA BYTE_REF(PADATA_ADDR) +#define PAPUEN BYTE_REF(PAPUEN_ADDR) + +#define PA(x) (1 << (x)) + +/* + * Port B + */ +#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ +#define PBDATA_ADDR 0xfffff409 /* Port B data register */ +#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ +#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ + +#define PBDIR BYTE_REF(PBDIR_ADDR) +#define PBDATA BYTE_REF(PBDATA_ADDR) +#define PBPUEN BYTE_REF(PBPUEN_ADDR) +#define PBSEL BYTE_REF(PBSEL_ADDR) + +#define PB(x) (1 << (x)) + +#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ +#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ +#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ +#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ +#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ +#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ +#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ +#define PB_PWMO 0x80 /* Use PWMO as PB[7] */ + +/* + * Port C + */ +#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ +#define PCDATA_ADDR 0xfffff411 /* Port C data register */ +#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ +#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ + +#define PCDIR BYTE_REF(PCDIR_ADDR) +#define PCDATA BYTE_REF(PCDATA_ADDR) +#define PCPDEN BYTE_REF(PCPDEN_ADDR) +#define PCSEL BYTE_REF(PCSEL_ADDR) + +#define PC(x) (1 << (x)) + +#define PC_LD0 0x01 /* Use LD0 as PC[0] */ +#define PC_LD1 0x02 /* Use LD1 as PC[1] */ +#define PC_LD2 0x04 /* Use LD2 as PC[2] */ +#define PC_LD3 0x08 /* Use LD3 as PC[3] */ +#define PC_LFLM 0x10 /* Use LFLM as PC[4] */ +#define PC_LLP 0x20 /* Use LLP as PC[5] */ +#define PC_LCLK 0x40 /* Use LCLK as PC[6] */ +#define PC_LACD 0x80 /* Use LACD as PC[7] */ + +/* + * Port D + */ +#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ +#define PDDATA_ADDR 0xfffff419 /* Port D data register */ +#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ +#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ +#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ +#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ +#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ +#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ + +#define PDDIR BYTE_REF(PDDIR_ADDR) +#define PDDATA BYTE_REF(PDDATA_ADDR) +#define PDPUEN BYTE_REF(PDPUEN_ADDR) +#define PDSEL BYTE_REF(PDSEL_ADDR) +#define PDPOL BYTE_REF(PDPOL_ADDR) +#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) +#define PDKBEN BYTE_REF(PDKBEN_ADDR) +#define PDIQEG BYTE_REF(PDIQEG_ADDR) + +#define PD(x) (1 << (x)) + +#define PD_INT0 0x01 /* Use INT0 as PD[0] */ +#define PD_INT1 0x02 /* Use INT1 as PD[1] */ +#define PD_INT2 0x04 /* Use INT2 as PD[2] */ +#define PD_INT3 0x08 /* Use INT3 as PD[3] */ +#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ +#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ +#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ +#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ + +/* + * Port E + */ +#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ +#define PEDATA_ADDR 0xfffff421 /* Port E data register */ +#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ +#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ + +#define PEDIR BYTE_REF(PEDIR_ADDR) +#define PEDATA BYTE_REF(PEDATA_ADDR) +#define PEPUEN BYTE_REF(PEPUEN_ADDR) +#define PESEL BYTE_REF(PESEL_ADDR) + +#define PE(x) (1 << (x)) + +#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ +#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ +#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ +#define PE_DWE 0x08 /* Use DWE as PE[3] */ +#define PE_RXD 0x10 /* Use RXD as PE[4] */ +#define PE_TXD 0x20 /* Use TXD as PE[5] */ +#define PE_RTS 0x40 /* Use RTS as PE[6] */ +#define PE_CTS 0x80 /* Use CTS as PE[7] */ + +/* + * Port F + */ +#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ +#define PFDATA_ADDR 0xfffff429 /* Port F data register */ +#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ +#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ + +#define PFDIR BYTE_REF(PFDIR_ADDR) +#define PFDATA BYTE_REF(PFDATA_ADDR) +#define PFPUEN BYTE_REF(PFPUEN_ADDR) +#define PFSEL BYTE_REF(PFSEL_ADDR) + +#define PF(x) (1 << (x)) + +#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ +#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ +#define PF_CLKO 0x04 /* Use CLKO as PF[2] */ +#define PF_A20 0x08 /* Use A20 as PF[3] */ +#define PF_A21 0x10 /* Use A21 as PF[4] */ +#define PF_A22 0x20 /* Use A22 as PF[5] */ +#define PF_A23 0x40 /* Use A23 as PF[6] */ +#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ + +/* + * Port G + */ +#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ +#define PGDATA_ADDR 0xfffff431 /* Port G data register */ +#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ +#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ + +#define PGDIR BYTE_REF(PGDIR_ADDR) +#define PGDATA BYTE_REF(PGDATA_ADDR) +#define PGPUEN BYTE_REF(PGPUEN_ADDR) +#define PGSEL BYTE_REF(PGSEL_ADDR) + +#define PG(x) (1 << (x)) + +#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ +#define PG_A0 0x02 /* Use A0 as PG[1] */ +#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ +#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ +#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ +#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ + +/********** + * + * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) + * + **********/ + +/* + * PWM Control Register + */ +#define PWMC_ADDR 0xfffff500 +#define PWMC WORD_REF(PWMC_ADDR) + +#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ +#define PWMC_CLKSEL_SHIFT 0 +#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ +#define PWMC_REPEAT_SHIFT 2 +#define PWMC_EN 0x0010 /* Enable PWM */ +#define PMNC_FIFOAV 0x0020 /* FIFO Available */ +#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ +#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ +#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ +#define PWMC_PRESCALER_SHIFT 8 +#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ + +/* '328-compatible definitions */ +#define PWMC_PWMEN PWMC_EN + +/* + * PWM Sample Register + */ +#define PWMS_ADDR 0xfffff502 +#define PWMS WORD_REF(PWMS_ADDR) + +/* + * PWM Period Register + */ +#define PWMP_ADDR 0xfffff504 +#define PWMP BYTE_REF(PWMP_ADDR) + +/* + * PWM Counter Register + */ +#define PWMCNT_ADDR 0xfffff505 +#define PWMCNT BYTE_REF(PWMCNT_ADDR) + +/********** + * + * 0xFFFFF6xx -- General-Purpose Timer + * + **********/ + +/* + * Timer Control register + */ +#define TCTL_ADDR 0xfffff600 +#define TCTL WORD_REF(TCTL_ADDR) + +#define TCTL_TEN 0x0001 /* Timer Enable */ +#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ +#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ +#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ +#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ +#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ +#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ +#define TCTL_IRQEN 0x0010 /* IRQ Enable */ +#define TCTL_OM 0x0020 /* Output Mode */ +#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ +#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ +#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ +#define TCTL_FRR 0x0010 /* Free-Run Mode */ + +/* '328-compatible definitions */ +#define TCTL1_ADDR TCTL_ADDR +#define TCTL1 TCTL + +/* + * Timer Prescaler Register + */ +#define TPRER_ADDR 0xfffff602 +#define TPRER WORD_REF(TPRER_ADDR) + +/* '328-compatible definitions */ +#define TPRER1_ADDR TPRER_ADDR +#define TPRER1 TPRER + +/* + * Timer Compare Register + */ +#define TCMP_ADDR 0xfffff604 +#define TCMP WORD_REF(TCMP_ADDR) + +/* '328-compatible definitions */ +#define TCMP1_ADDR TCMP_ADDR +#define TCMP1 TCMP + +/* + * Timer Capture register + */ +#define TCR_ADDR 0xfffff606 +#define TCR WORD_REF(TCR_ADDR) + +/* '328-compatible definitions */ +#define TCR1_ADDR TCR_ADDR +#define TCR1 TCR + +/* + * Timer Counter Register + */ +#define TCN_ADDR 0xfffff608 +#define TCN WORD_REF(TCN_ADDR) + +/* '328-compatible definitions */ +#define TCN1_ADDR TCN_ADDR +#define TCN1 TCN + +/* + * Timer Status Register + */ +#define TSTAT_ADDR 0xfffff60a +#define TSTAT WORD_REF(TSTAT_ADDR) + +#define TSTAT_COMP 0x0001 /* Compare Event occurred */ +#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ + +/* '328-compatible definitions */ +#define TSTAT1_ADDR TSTAT_ADDR +#define TSTAT1 TSTAT + +/********** + * + * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) + * + **********/ + +/* + * SPIM Data Register + */ +#define SPIMDATA_ADDR 0xfffff800 +#define SPIMDATA WORD_REF(SPIMDATA_ADDR) + +/* + * SPIM Control/Status Register + */ +#define SPIMCONT_ADDR 0xfffff802 +#define SPIMCONT WORD_REF(SPIMCONT_ADDR) + +#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ +#define SPIMCONT_BIT_COUNT_SHIFT 0 +#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ +#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ +#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ +#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ +#define SPIMCONT_XCH 0x0100 /* Exchange */ +#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ +#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ +#define SPIMCONT_DATA_RATE_SHIFT 13 + +/* '328-compatible definitions */ +#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ +#define SPIMCONT_SPIMEN SPIMCONT_ENABLE + +/********** + * + * 0xFFFFF9xx -- UART + * + **********/ + +/* + * UART Status/Control Register + */ +#define USTCNT_ADDR 0xfffff900 +#define USTCNT WORD_REF(USTCNT_ADDR) + +#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ +#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ +#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ +#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ +#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ +#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ +#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ +#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ +#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ +#define USTCNT_STOP 0x0200 /* Stop bit transmission */ +#define USTCNT_ODD 0x0400 /* Odd Parity */ +#define USTCNT_PEN 0x0800 /* Parity Enable */ +#define USTCNT_CLKM 0x1000 /* Clock Mode Select */ +#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ +#define USTCNT_RXEN 0x4000 /* Receiver Enable */ +#define USTCNT_UEN 0x8000 /* UART Enable */ + +/* '328-compatible definitions */ +#define USTCNT_TXAVAILEN USTCNT_TXAE +#define USTCNT_TXHALFEN USTCNT_TXHE +#define USTCNT_TXEMPTYEN USTCNT_TXEE +#define USTCNT_RXREADYEN USTCNT_RXRE +#define USTCNT_RXHALFEN USTCNT_RXHE +#define USTCNT_RXFULLEN USTCNT_RXFE +#define USTCNT_CTSDELTAEN USTCNT_CTSD +#define USTCNT_ODD_EVEN USTCNT_ODD +#define USTCNT_PARITYEN USTCNT_PEN +#define USTCNT_CLKMODE USTCNT_CLKM +#define USTCNT_UARTEN USTCNT_UEN + +/* + * UART Baud Control Register + */ +#define UBAUD_ADDR 0xfffff902 +#define UBAUD WORD_REF(UBAUD_ADDR) + +#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ +#define UBAUD_PRESCALER_SHIFT 0 +#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ +#define UBAUD_DIVIDE_SHIFT 8 +#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ +#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ + +/* + * UART Receiver Register + */ +#define URX_ADDR 0xfffff904 +#define URX WORD_REF(URX_ADDR) + +#define URX_RXDATA_ADDR 0xfffff905 +#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) + +#define URX_RXDATA_MASK 0x00ff /* Received data */ +#define URX_RXDATA_SHIFT 0 +#define URX_PARITY_ERROR 0x0100 /* Parity Error */ +#define URX_BREAK 0x0200 /* Break Detected */ +#define URX_FRAME_ERROR 0x0400 /* Framing Error */ +#define URX_OVRUN 0x0800 /* Serial Overrun */ +#define URX_OLD_DATA 0x1000 /* Old data in FIFO */ +#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ +#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ +#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ + +/* + * UART Transmitter Register + */ +#define UTX_ADDR 0xfffff906 +#define UTX WORD_REF(UTX_ADDR) + +#define UTX_TXDATA_ADDR 0xfffff907 +#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) + +#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ +#define UTX_TXDATA_SHIFT 0 +#define UTX_CTS_DELTA 0x0100 /* CTS changed */ +#define UTX_CTS_STAT 0x0200 /* CTS State */ +#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ +#define UTX_NOCTS 0x0800 /* Ignore CTS */ +#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ +#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ +#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ +#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ + +/* '328-compatible definitions */ +#define UTX_CTS_STATUS UTX_CTS_STAT +#define UTX_IGNORE_CTS UTX_NOCTS + +/* + * UART Miscellaneous Register + */ +#define UMISC_ADDR 0xfffff908 +#define UMISC WORD_REF(UMISC_ADDR) + +#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ +#define UMISC_RX_POL 0x0008 /* Receive Polarity */ +#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ +#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ +#define UMISC_RTS 0x0040 /* Set RTS status */ +#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ +#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ +#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ +#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ +#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ +#define UMISC_CLKSRC 0x4000 /* Clock Source */ +#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ + +/* + * UART Non-integer Prescaler Register + */ +#define NIPR_ADDR 0xfffff90a +#define NIPR WORD_REF(NIPR_ADDR) + +#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ +#define NIPR_STEP_VALUE_SHIFT 0 +#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ +#define NIPR_SELECT_SHIFT 8 +#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ + + +/* generalization of uart control registers to support multiple ports: */ +typedef volatile struct { + volatile unsigned short int ustcnt; + volatile unsigned short int ubaud; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char rxdata; + } b; + } urx; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char txdata; + } b; + } utx; + volatile unsigned short int umisc; + volatile unsigned short int nipr; + volatile unsigned short int pad1; + volatile unsigned short int pad2; +} __attribute__((packed)) m68328_uart; + + +/********** + * + * 0xFFFFFAxx -- LCD Controller + * + **********/ + +/* + * LCD Screen Starting Address Register + */ +#define LSSA_ADDR 0xfffffa00 +#define LSSA LONG_REF(LSSA_ADDR) + +#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ + +/* + * LCD Virtual Page Width Register + */ +#define LVPW_ADDR 0xfffffa05 +#define LVPW BYTE_REF(LVPW_ADDR) + +/* + * LCD Screen Width Register (not compatible with '328 !!!) + */ +#define LXMAX_ADDR 0xfffffa08 +#define LXMAX WORD_REF(LXMAX_ADDR) + +#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ + +/* + * LCD Screen Height Register + */ +#define LYMAX_ADDR 0xfffffa0a +#define LYMAX WORD_REF(LYMAX_ADDR) + +#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ + +/* + * LCD Cursor X Position Register + */ +#define LCXP_ADDR 0xfffffa18 +#define LCXP WORD_REF(LCXP_ADDR) + +#define LCXP_CC_MASK 0xc000 /* Cursor Control */ +#define LCXP_CC_TRAMSPARENT 0x0000 +#define LCXP_CC_BLACK 0x4000 +#define LCXP_CC_REVERSED 0x8000 +#define LCXP_CC_WHITE 0xc000 +#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ + +/* + * LCD Cursor Y Position Register + */ +#define LCYP_ADDR 0xfffffa1a +#define LCYP WORD_REF(LCYP_ADDR) + +#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ + +/* + * LCD Cursor Width and Heigth Register + */ +#define LCWCH_ADDR 0xfffffa1c +#define LCWCH WORD_REF(LCWCH_ADDR) + +#define LCWCH_CH_MASK 0x001f /* Cursor Height */ +#define LCWCH_CH_SHIFT 0 +#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ +#define LCWCH_CW_SHIFT 8 + +/* + * LCD Blink Control Register + */ +#define LBLKC_ADDR 0xfffffa1f +#define LBLKC BYTE_REF(LBLKC_ADDR) + +#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ +#define LBLKC_BD_SHIFT 0 +#define LBLKC_BKEN 0x80 /* Blink Enabled */ + +/* + * LCD Panel Interface Configuration Register + */ +#define LPICF_ADDR 0xfffffa20 +#define LPICF BYTE_REF(LPICF_ADDR) + +#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ +#define LPICF_GS_BW 0x00 +#define LPICF_GS_GRAY_4 0x01 +#define LPICF_GS_GRAY_16 0x02 +#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ +#define LPICF_PBSIZ_1 0x00 +#define LPICF_PBSIZ_2 0x04 +#define LPICF_PBSIZ_4 0x08 + +/* + * LCD Polarity Configuration Register + */ +#define LPOLCF_ADDR 0xfffffa21 +#define LPOLCF BYTE_REF(LPOLCF_ADDR) + +#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ +#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ +#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ +#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ + +/* + * LACD (LCD Alternate Crystal Direction) Rate Control Register + */ +#define LACDRC_ADDR 0xfffffa23 +#define LACDRC BYTE_REF(LACDRC_ADDR) + +#define LACDRC_ACDSLT 0x80 /* Signal Source Select */ +#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ +#define LACDRC_ACD_SHIFT 0 + +/* + * LCD Pixel Clock Divider Register + */ +#define LPXCD_ADDR 0xfffffa25 +#define LPXCD BYTE_REF(LPXCD_ADDR) + +#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ +#define LPXCD_PCD_SHIFT 0 + +/* + * LCD Clocking Control Register + */ +#define LCKCON_ADDR 0xfffffa27 +#define LCKCON BYTE_REF(LCKCON_ADDR) + +#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ +#define LCKCON_DWS_SHIFT 0 +#define LCKCON_DWIDTH 0x40 /* Display Memory Width */ +#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ + +/* '328-compatible definitions */ +#define LCKCON_DW_MASK LCKCON_DWS_MASK +#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT + +/* + * LCD Refresh Rate Adjustment Register + */ +#define LRRA_ADDR 0xfffffa29 +#define LRRA BYTE_REF(LRRA_ADDR) + +/* + * LCD Panning Offset Register + */ +#define LPOSR_ADDR 0xfffffa2d +#define LPOSR BYTE_REF(LPOSR_ADDR) + +#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ +#define LPOSR_POS_SHIFT 0 + +/* + * LCD Frame Rate Control Modulation Register + */ +#define LFRCM_ADDR 0xfffffa31 +#define LFRCM BYTE_REF(LFRCM_ADDR) + +#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ +#define LFRCM_YMOD_SHIFT 0 +#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ +#define LFRCM_XMOD_SHIFT 4 + +/* + * LCD Gray Palette Mapping Register + */ +#define LGPMR_ADDR 0xfffffa33 +#define LGPMR BYTE_REF(LGPMR_ADDR) + +#define LGPMR_G1_MASK 0x0f +#define LGPMR_G1_SHIFT 0 +#define LGPMR_G2_MASK 0xf0 +#define LGPMR_G2_SHIFT 4 + +/* + * PWM Contrast Control Register + */ +#define PWMR_ADDR 0xfffffa36 +#define PWMR WORD_REF(PWMR_ADDR) + +#define PWMR_PW_MASK 0x00ff /* Pulse Width */ +#define PWMR_PW_SHIFT 0 +#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ +#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ +#define PWMR_SRC_LINE 0x0000 /* Line Pulse */ +#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ +#define PWMR_SRC_LCD 0x4000 /* LCD clock */ + +/********** + * + * 0xFFFFFBxx -- Real-Time Clock (RTC) + * + **********/ + +/* + * RTC Hours Minutes and Seconds Register + */ +#define RTCTIME_ADDR 0xfffffb00 +#define RTCTIME LONG_REF(RTCTIME_ADDR) + +#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCTIME_SECONDS_SHIFT 0 +#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCTIME_MINUTES_SHIFT 16 +#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCTIME_HOURS_SHIFT 24 + +/* + * RTC Alarm Register + */ +#define RTCALRM_ADDR 0xfffffb04 +#define RTCALRM LONG_REF(RTCALRM_ADDR) + +#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCALRM_SECONDS_SHIFT 0 +#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCALRM_MINUTES_SHIFT 16 +#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCALRM_HOURS_SHIFT 24 + +/* + * Watchdog Timer Register + */ +#define WATCHDOG_ADDR 0xfffffb0a +#define WATCHDOG WORD_REF(WATCHDOG_ADDR) + +#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ +#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ +#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ +#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ +#define WATCHDOG_CNT_SHIFT 8 + +/* + * RTC Control Register + */ +#define RTCCTL_ADDR 0xfffffb0c +#define RTCCTL WORD_REF(RTCCTL_ADDR) + +#define RTCCTL_XTL 0x0020 /* Crystal Selection */ +#define RTCCTL_EN 0x0080 /* RTC Enable */ + +/* '328-compatible definitions */ +#define RTCCTL_384 RTCCTL_XTL +#define RTCCTL_ENABLE RTCCTL_EN + +/* + * RTC Interrupt Status Register + */ +#define RTCISR_ADDR 0xfffffb0e +#define RTCISR WORD_REF(RTCISR_ADDR) + +#define RTCISR_SW 0x0001 /* Stopwatch timed out */ +#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ +#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ +#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ +#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ +#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ +#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ +#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ +#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ +#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ +#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ +#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ +#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ +#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ + +/* + * RTC Interrupt Enable Register + */ +#define RTCIENR_ADDR 0xfffffb10 +#define RTCIENR WORD_REF(RTCIENR_ADDR) + +#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ +#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ +#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ +#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ +#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ +#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ +#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ +#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ +#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ +#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ +#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ +#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ +#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ +#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ + +/* + * Stopwatch Minutes Register + */ +#define STPWCH_ADDR 0xfffffb12 +#define STPWCH WORD_REF(STPWCH) + +#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ +#define SPTWCH_CNT_SHIFT 0 + +/* + * RTC Day Count Register + */ +#define DAYR_ADDR 0xfffffb1a +#define DAYR WORD_REF(DAYR_ADDR) + +#define DAYR_DAYS_MASK 0x1ff /* Day Setting */ +#define DAYR_DAYS_SHIFT 0 + +/* + * RTC Day Alarm Register + */ +#define DAYALARM_ADDR 0xfffffb1c +#define DAYALARM WORD_REF(DAYALARM_ADDR) + +#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ +#define DAYALARM_DAYSAL_SHIFT 0 + +/********** + * + * 0xFFFFFCxx -- DRAM Controller + * + **********/ + +/* + * DRAM Memory Configuration Register + */ +#define DRAMMC_ADDR 0xfffffc00 +#define DRAMMC WORD_REF(DRAMMC_ADDR) + +#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ +#define DRAMMC_ROW12_PA10 0x0000 +#define DRAMMC_ROW12_PA21 0x4000 +#define DRAMMC_ROW12_PA23 0x8000 +#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ +#define DRAMMC_ROW0_PA11 0x0000 +#define DRAMMC_ROW0_PA22 0x1000 +#define DRAMMC_ROW0_PA23 0x2000 +#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ +#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ +#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ +#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ +#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ +#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ +#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ +#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ +#define DRAMMC_REF_SHIFT 0 + +/* + * DRAM Control Register + */ +#define DRAMC_ADDR 0xfffffc02 +#define DRAMC WORD_REF(DRAMC_ADDR) + +#define DRAMC_DWE 0x0001 /* DRAM Write Enable */ +#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ +#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ +#define DRAMC_SLW 0x0008 /* Slow RAM */ +#define DRAMC_LSP 0x0010 /* Light Sleep */ +#define DRAMC_MSW 0x0020 /* Slow Multiplexing */ +#define DRAMC_WS_MASK 0x00c0 /* Wait-states */ +#define DRAMC_WS_SHIFT 6 +#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ +#define DRAMC_PGSZ_SHIFT 8 +#define DRAMC_PGSZ_256K 0x0000 +#define DRAMC_PGSZ_512K 0x0100 +#define DRAMC_PGSZ_1024K 0x0200 +#define DRAMC_PGSZ_2048K 0x0300 +#define DRAMC_EDO 0x0400 /* EDO DRAM */ +#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ +#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ +#define DRAMC_BC_SHIFT 12 +#define DRAMC_RM 0x4000 /* Refresh Mode */ +#define DRAMC_EN 0x8000 /* DRAM Controller enable */ + + +/********** + * + * 0xFFFFFDxx -- In-Circuit Emulation (ICE) + * + **********/ + +/* + * ICE Module Address Compare Register + */ +#define ICEMACR_ADDR 0xfffffd00 +#define ICEMACR LONG_REF(ICEMACR_ADDR) + +/* + * ICE Module Address Mask Register + */ +#define ICEMAMR_ADDR 0xfffffd04 +#define ICEMAMR LONG_REF(ICEMAMR_ADDR) + +/* + * ICE Module Control Compare Register + */ +#define ICEMCCR_ADDR 0xfffffd08 +#define ICEMCCR WORD_REF(ICEMCCR_ADDR) + +#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ +#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ + +/* + * ICE Module Control Mask Register + */ +#define ICEMCMR_ADDR 0xfffffd0a +#define ICEMCMR WORD_REF(ICEMCMR_ADDR) + +#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ +#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ + +/* + * ICE Module Control Register + */ +#define ICEMCR_ADDR 0xfffffd0c +#define ICEMCR WORD_REF(ICEMCR_ADDR) + +#define ICEMCR_CEN 0x0001 /* Compare Enable */ +#define ICEMCR_PBEN 0x0002 /* Program Break Enable */ +#define ICEMCR_SB 0x0004 /* Single Breakpoint */ +#define ICEMCR_HMDIS 0x0008 /* HardMap disable */ +#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ + +/* + * ICE Module Status Register + */ +#define ICEMSR_ADDR 0xfffffd0e +#define ICEMSR WORD_REF(ICEMSR_ADDR) + +#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ +#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ +#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ +#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ + +#endif /* _MC68EZ328_H_ */ diff --git a/arch/m68knommu/include/asm/MC68VZ328.h b/arch/m68knommu/include/asm/MC68VZ328.h new file mode 100644 index 000000000000..2b9bf626a0a5 --- /dev/null +++ b/arch/m68knommu/include/asm/MC68VZ328.h @@ -0,0 +1,1349 @@ + +/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers + * + * Copyright (c) 2000-2001 Lineo Inc. + * Copyright (c) 2000-2001 Lineo Canada Corp. + * Copyright (C) 1999 Vladimir Gurevich + * Bare & Hare Software, Inc. + * Based on include/asm-m68knommu/MC68332.h + * Copyright (C) 1998 Kenneth Albanowski , + * The Silver Hammer Group, Ltd. + * + * M68VZ328 fixes by Evan Stawnyczy + * vz multiport fixes by Michael Leslie + */ + +#ifndef _MC68VZ328_H_ +#define _MC68VZ328_H_ + +#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) +#define WORD_REF(addr) (*((volatile unsigned short*)addr)) +#define LONG_REF(addr) (*((volatile unsigned long*)addr)) + +#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) +#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) + +/********** + * + * 0xFFFFF0xx -- System Control + * + **********/ + +/* + * System Control Register (SCR) + */ +#define SCR_ADDR 0xfffff000 +#define SCR BYTE_REF(SCR_ADDR) + +#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ +#define SCR_DMAP 0x04 /* Double Map */ +#define SCR_SO 0x08 /* Supervisor Only */ +#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ +#define SCR_PRV 0x20 /* Privilege Violation */ +#define SCR_WPV 0x40 /* Write Protect Violation */ +#define SCR_BETO 0x80 /* Bus-Error TimeOut */ + +/* + * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) + */ +#define MRR_ADDR 0xfffff004 +#define MRR LONG_REF(MRR_ADDR) + +/********** + * + * 0xFFFFF1xx -- Chip-Select logic + * + **********/ + +/* + * Chip Select Group Base Registers + */ +#define CSGBA_ADDR 0xfffff100 +#define CSGBB_ADDR 0xfffff102 + +#define CSGBC_ADDR 0xfffff104 +#define CSGBD_ADDR 0xfffff106 + +#define CSGBA WORD_REF(CSGBA_ADDR) +#define CSGBB WORD_REF(CSGBB_ADDR) +#define CSGBC WORD_REF(CSGBC_ADDR) +#define CSGBD WORD_REF(CSGBD_ADDR) + +/* + * Chip Select Registers + */ +#define CSA_ADDR 0xfffff110 +#define CSB_ADDR 0xfffff112 +#define CSC_ADDR 0xfffff114 +#define CSD_ADDR 0xfffff116 + +#define CSA WORD_REF(CSA_ADDR) +#define CSB WORD_REF(CSB_ADDR) +#define CSC WORD_REF(CSC_ADDR) +#define CSD WORD_REF(CSD_ADDR) + +#define CSA_EN 0x0001 /* Chip-Select Enable */ +#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSA_SIZ_SHIFT 1 +#define CSA_WS_MASK 0x0070 /* Wait State */ +#define CSA_WS_SHIFT 4 +#define CSA_BSW 0x0080 /* Data Bus Width */ +#define CSA_FLASH 0x0100 /* FLASH Memory Support */ +#define CSA_RO 0x8000 /* Read-Only */ + +#define CSB_EN 0x0001 /* Chip-Select Enable */ +#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSB_SIZ_SHIFT 1 +#define CSB_WS_MASK 0x0070 /* Wait State */ +#define CSB_WS_SHIFT 4 +#define CSB_BSW 0x0080 /* Data Bus Width */ +#define CSB_FLASH 0x0100 /* FLASH Memory Support */ +#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSB_UPSIZ_SHIFT 11 +#define CSB_ROP 0x2000 /* Readonly if protected */ +#define CSB_SOP 0x4000 /* Supervisor only if protected */ +#define CSB_RO 0x8000 /* Read-Only */ + +#define CSC_EN 0x0001 /* Chip-Select Enable */ +#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSC_SIZ_SHIFT 1 +#define CSC_WS_MASK 0x0070 /* Wait State */ +#define CSC_WS_SHIFT 4 +#define CSC_BSW 0x0080 /* Data Bus Width */ +#define CSC_FLASH 0x0100 /* FLASH Memory Support */ +#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSC_UPSIZ_SHIFT 11 +#define CSC_ROP 0x2000 /* Readonly if protected */ +#define CSC_SOP 0x4000 /* Supervisor only if protected */ +#define CSC_RO 0x8000 /* Read-Only */ + +#define CSD_EN 0x0001 /* Chip-Select Enable */ +#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ +#define CSD_SIZ_SHIFT 1 +#define CSD_WS_MASK 0x0070 /* Wait State */ +#define CSD_WS_SHIFT 4 +#define CSD_BSW 0x0080 /* Data Bus Width */ +#define CSD_FLASH 0x0100 /* FLASH Memory Support */ +#define CSD_DRAM 0x0200 /* Dram Selection */ +#define CSD_COMB 0x0400 /* Combining */ +#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ +#define CSD_UPSIZ_SHIFT 11 +#define CSD_ROP 0x2000 /* Readonly if protected */ +#define CSD_SOP 0x4000 /* Supervisor only if protected */ +#define CSD_RO 0x8000 /* Read-Only */ + +/* + * Emulation Chip-Select Register + */ +#define EMUCS_ADDR 0xfffff118 +#define EMUCS WORD_REF(EMUCS_ADDR) + +#define EMUCS_WS_MASK 0x0070 +#define EMUCS_WS_SHIFT 4 + +/********** + * + * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control + * + **********/ + +/* + * PLL Control Register + */ +#define PLLCR_ADDR 0xfffff200 +#define PLLCR WORD_REF(PLLCR_ADDR) + +#define PLLCR_DISPLL 0x0008 /* Disable PLL */ +#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ +#define PLLCR_PRESC 0x0020 /* VCO prescaler */ +#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ +#define PLLCR_SYSCLK_SEL_SHIFT 8 +#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ +#define PLLCR_LCDCLK_SEL_SHIFT 11 + +/* '328-compatible definitions */ +#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK +#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT + +/* + * PLL Frequency Select Register + */ +#define PLLFSR_ADDR 0xfffff202 +#define PLLFSR WORD_REF(PLLFSR_ADDR) + +#define PLLFSR_PC_MASK 0x00ff /* P Count */ +#define PLLFSR_PC_SHIFT 0 +#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ +#define PLLFSR_QC_SHIFT 8 +#define PLLFSR_PROT 0x4000 /* Protect P & Q */ +#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ + +/* + * Power Control Register + */ +#define PCTRL_ADDR 0xfffff207 +#define PCTRL BYTE_REF(PCTRL_ADDR) + +#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ +#define PCTRL_WIDTH_SHIFT 0 +#define PCTRL_PCEN 0x80 /* Power Control Enable */ + +/********** + * + * 0xFFFFF3xx -- Interrupt Controller + * + **********/ + +/* + * Interrupt Vector Register + */ +#define IVR_ADDR 0xfffff300 +#define IVR BYTE_REF(IVR_ADDR) + +#define IVR_VECTOR_MASK 0xF8 + +/* + * Interrupt control Register + */ +#define ICR_ADDR 0xfffff302 +#define ICR WORD_REF(ICR_ADDR) + +#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ +#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ +#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ +#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ +#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ +#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ +#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ +#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ +#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ + +/* + * Interrupt Mask Register + */ +#define IMR_ADDR 0xfffff304 +#define IMR LONG_REF(IMR_ADDR) + +/* + * Define the names for bit positions first. This is useful for + * request_irq + */ +#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */ +#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */ +#define UART1_IRQ_NUM 2 /* UART 1 interrupt */ +#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ +#define RTC_IRQ_NUM 4 /* RTC interrupt */ +#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */ +#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ +#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */ +#define INT0_IRQ_NUM 8 /* External INT0 */ +#define INT1_IRQ_NUM 9 /* External INT1 */ +#define INT2_IRQ_NUM 10 /* External INT2 */ +#define INT3_IRQ_NUM 11 /* External INT3 */ +#define UART2_IRQ_NUM 12 /* UART 2 interrupt */ +#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */ +#define IRQ1_IRQ_NUM 16 /* IRQ1 */ +#define IRQ2_IRQ_NUM 17 /* IRQ2 */ +#define IRQ3_IRQ_NUM 18 /* IRQ3 */ +#define IRQ6_IRQ_NUM 19 /* IRQ6 */ +#define IRQ5_IRQ_NUM 20 /* IRQ5 */ +#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */ +#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ +#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ + +#define SPI_IRQ_NUM SPI2_IRQ_NUM + +/* '328-compatible definitions */ +#define SPIM_IRQ_NUM SPI_IRQ_NUM +#define TMR1_IRQ_NUM TMR_IRQ_NUM +#define UART_IRQ_NUM UART1_IRQ_NUM + +/* + * Here go the bitmasks themselves + */ +#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ +#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ +#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ +#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ +#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ +#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ +#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ +#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ +#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ +#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ +#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ +#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ +#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ +#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ +#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ +#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ +#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ +#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ + +/* '328-compatible definitions */ +#define IMR_MSPIM IMR_MSPI +#define IMR_MTMR1 IMR_MTMR + +/* + * Interrupt Status Register + */ +#define ISR_ADDR 0xfffff30c +#define ISR LONG_REF(ISR_ADDR) + +#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ +#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ +#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ +#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ +#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ +#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ + +/* '328-compatible definitions */ +#define ISR_SPIM ISR_SPI +#define ISR_TMR1 ISR_TMR + +/* + * Interrupt Pending Register + */ +#define IPR_ADDR 0xfffff30c +#define IPR LONG_REF(IPR_ADDR) + +#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ +#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ +#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ +#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ +#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ +#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ +#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ +#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ +#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ +#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ +#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ +#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ +#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ +#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ +#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ +#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ +#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ +#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ + +/* '328-compatible definitions */ +#define IPR_SPIM IPR_SPI +#define IPR_TMR1 IPR_TMR + +/********** + * + * 0xFFFFF4xx -- Parallel Ports + * + **********/ + +/* + * Port A + */ +#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ +#define PADATA_ADDR 0xfffff401 /* Port A data register */ +#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ + +#define PADIR BYTE_REF(PADIR_ADDR) +#define PADATA BYTE_REF(PADATA_ADDR) +#define PAPUEN BYTE_REF(PAPUEN_ADDR) + +#define PA(x) (1 << (x)) + +/* + * Port B + */ +#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ +#define PBDATA_ADDR 0xfffff409 /* Port B data register */ +#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ +#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ + +#define PBDIR BYTE_REF(PBDIR_ADDR) +#define PBDATA BYTE_REF(PBDATA_ADDR) +#define PBPUEN BYTE_REF(PBPUEN_ADDR) +#define PBSEL BYTE_REF(PBSEL_ADDR) + +#define PB(x) (1 << (x)) + +#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ +#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ +#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ +#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ +#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ +#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ +#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ +#define PB_PWMO 0x80 /* Use PWMO as PB[7] */ + +/* + * Port C + */ +#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ +#define PCDATA_ADDR 0xfffff411 /* Port C data register */ +#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ +#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ + +#define PCDIR BYTE_REF(PCDIR_ADDR) +#define PCDATA BYTE_REF(PCDATA_ADDR) +#define PCPDEN BYTE_REF(PCPDEN_ADDR) +#define PCSEL BYTE_REF(PCSEL_ADDR) + +#define PC(x) (1 << (x)) + +#define PC_LD0 0x01 /* Use LD0 as PC[0] */ +#define PC_LD1 0x02 /* Use LD1 as PC[1] */ +#define PC_LD2 0x04 /* Use LD2 as PC[2] */ +#define PC_LD3 0x08 /* Use LD3 as PC[3] */ +#define PC_LFLM 0x10 /* Use LFLM as PC[4] */ +#define PC_LLP 0x20 /* Use LLP as PC[5] */ +#define PC_LCLK 0x40 /* Use LCLK as PC[6] */ +#define PC_LACD 0x80 /* Use LACD as PC[7] */ + +/* + * Port D + */ +#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ +#define PDDATA_ADDR 0xfffff419 /* Port D data register */ +#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ +#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ +#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ +#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ +#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ +#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ + +#define PDDIR BYTE_REF(PDDIR_ADDR) +#define PDDATA BYTE_REF(PDDATA_ADDR) +#define PDPUEN BYTE_REF(PDPUEN_ADDR) +#define PDSEL BYTE_REF(PDSEL_ADDR) +#define PDPOL BYTE_REF(PDPOL_ADDR) +#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) +#define PDKBEN BYTE_REF(PDKBEN_ADDR) +#define PDIQEG BYTE_REF(PDIQEG_ADDR) + +#define PD(x) (1 << (x)) + +#define PD_INT0 0x01 /* Use INT0 as PD[0] */ +#define PD_INT1 0x02 /* Use INT1 as PD[1] */ +#define PD_INT2 0x04 /* Use INT2 as PD[2] */ +#define PD_INT3 0x08 /* Use INT3 as PD[3] */ +#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ +#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ +#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ +#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ + +/* + * Port E + */ +#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ +#define PEDATA_ADDR 0xfffff421 /* Port E data register */ +#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ +#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ + +#define PEDIR BYTE_REF(PEDIR_ADDR) +#define PEDATA BYTE_REF(PEDATA_ADDR) +#define PEPUEN BYTE_REF(PEPUEN_ADDR) +#define PESEL BYTE_REF(PESEL_ADDR) + +#define PE(x) (1 << (x)) + +#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ +#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ +#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ +#define PE_DWE 0x08 /* Use DWE as PE[3] */ +#define PE_RXD 0x10 /* Use RXD as PE[4] */ +#define PE_TXD 0x20 /* Use TXD as PE[5] */ +#define PE_RTS 0x40 /* Use RTS as PE[6] */ +#define PE_CTS 0x80 /* Use CTS as PE[7] */ + +/* + * Port F + */ +#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ +#define PFDATA_ADDR 0xfffff429 /* Port F data register */ +#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ +#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ + +#define PFDIR BYTE_REF(PFDIR_ADDR) +#define PFDATA BYTE_REF(PFDATA_ADDR) +#define PFPUEN BYTE_REF(PFPUEN_ADDR) +#define PFSEL BYTE_REF(PFSEL_ADDR) + +#define PF(x) (1 << (x)) + +#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ +#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ +#define PF_CLKO 0x04 /* Use CLKO as PF[2] */ +#define PF_A20 0x08 /* Use A20 as PF[3] */ +#define PF_A21 0x10 /* Use A21 as PF[4] */ +#define PF_A22 0x20 /* Use A22 as PF[5] */ +#define PF_A23 0x40 /* Use A23 as PF[6] */ +#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ + +/* + * Port G + */ +#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ +#define PGDATA_ADDR 0xfffff431 /* Port G data register */ +#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ +#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ + +#define PGDIR BYTE_REF(PGDIR_ADDR) +#define PGDATA BYTE_REF(PGDATA_ADDR) +#define PGPUEN BYTE_REF(PGPUEN_ADDR) +#define PGSEL BYTE_REF(PGSEL_ADDR) + +#define PG(x) (1 << (x)) + +#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ +#define PG_A0 0x02 /* Use A0 as PG[1] */ +#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ +#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ +#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ +#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ + +/* + * Port J + */ +#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ +#define PJDATA_ADDR 0xfffff439 /* Port J data register */ +#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */ +#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ + +#define PJDIR BYTE_REF(PJDIR_ADDR) +#define PJDATA BYTE_REF(PJDATA_ADDR) +#define PJPUEN BYTE_REF(PJPUEN_ADDR) +#define PJSEL BYTE_REF(PJSEL_ADDR) + +#define PJ(x) (1 << (x)) + +/* + * Port K + */ +#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ +#define PKDATA_ADDR 0xfffff441 /* Port K data register */ +#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */ +#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ + +#define PKDIR BYTE_REF(PKDIR_ADDR) +#define PKDATA BYTE_REF(PKDATA_ADDR) +#define PKPUEN BYTE_REF(PKPUEN_ADDR) +#define PKSEL BYTE_REF(PKSEL_ADDR) + +#define PK(x) (1 << (x)) + +#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */ +#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */ +#define PK_R_W 0x02 /* Use R/W as PK[1] */ +#define PK_LDS 0x04 /* Use /LDS as PK[2] */ +#define PK_UDS 0x08 /* Use /UDS as PK[3] */ +#define PK_LD4 0x10 /* Use LD4 as PK[4] */ +#define PK_LD5 0x20 /* Use LD5 as PK[5] */ +#define PK_LD6 0x40 /* Use LD6 as PK[6] */ +#define PK_LD7 0x80 /* Use LD7 as PK[7] */ + +#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ +#define PJDATA_ADDR 0xfffff439 /* Port J data register */ +#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */ +#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ + +#define PJDIR BYTE_REF(PJDIR_ADDR) +#define PJDATA BYTE_REF(PJDATA_ADDR) +#define PJPUEN BYTE_REF(PJPUEN_ADDR) +#define PJSEL BYTE_REF(PJSEL_ADDR) + +#define PJ(x) (1 << (x)) + +#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */ +#define PJ_MISO 0x02 /* Use MISO as PJ[1] */ +#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */ +#define PJ_SS 0x08 /* Use SS as PJ[3] */ +#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */ +#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */ +#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */ +#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */ + +/* + * Port M + */ +#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */ +#define PMDATA_ADDR 0xfffff449 /* Port M data register */ +#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */ +#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */ + +#define PMDIR BYTE_REF(PMDIR_ADDR) +#define PMDATA BYTE_REF(PMDATA_ADDR) +#define PMPUEN BYTE_REF(PMPUEN_ADDR) +#define PMSEL BYTE_REF(PMSEL_ADDR) + +#define PM(x) (1 << (x)) + +#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */ +#define PM_SDCE 0x02 /* Use SDCE as PM[1] */ +#define PM_DQMH 0x04 /* Use DQMH as PM[2] */ +#define PM_DQML 0x08 /* Use DQML as PM[3] */ +#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */ +#define PM_DMOE 0x20 /* Use DMOE as PM[5] */ + +/********** + * + * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) + * + **********/ + +/* + * PWM Control Register + */ +#define PWMC_ADDR 0xfffff500 +#define PWMC WORD_REF(PWMC_ADDR) + +#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ +#define PWMC_CLKSEL_SHIFT 0 +#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ +#define PWMC_REPEAT_SHIFT 2 +#define PWMC_EN 0x0010 /* Enable PWM */ +#define PMNC_FIFOAV 0x0020 /* FIFO Available */ +#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ +#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ +#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ +#define PWMC_PRESCALER_SHIFT 8 +#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ + +/* '328-compatible definitions */ +#define PWMC_PWMEN PWMC_EN + +/* + * PWM Sample Register + */ +#define PWMS_ADDR 0xfffff502 +#define PWMS WORD_REF(PWMS_ADDR) + +/* + * PWM Period Register + */ +#define PWMP_ADDR 0xfffff504 +#define PWMP BYTE_REF(PWMP_ADDR) + +/* + * PWM Counter Register + */ +#define PWMCNT_ADDR 0xfffff505 +#define PWMCNT BYTE_REF(PWMCNT_ADDR) + +/********** + * + * 0xFFFFF6xx -- General-Purpose Timer + * + **********/ + +/* + * Timer Control register + */ +#define TCTL_ADDR 0xfffff600 +#define TCTL WORD_REF(TCTL_ADDR) + +#define TCTL_TEN 0x0001 /* Timer Enable */ +#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ +#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ +#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ +#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ +#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ +#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ +#define TCTL_IRQEN 0x0010 /* IRQ Enable */ +#define TCTL_OM 0x0020 /* Output Mode */ +#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ +#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ +#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ +#define TCTL_FRR 0x0010 /* Free-Run Mode */ + +/* '328-compatible definitions */ +#define TCTL1_ADDR TCTL_ADDR +#define TCTL1 TCTL + +/* + * Timer Prescaler Register + */ +#define TPRER_ADDR 0xfffff602 +#define TPRER WORD_REF(TPRER_ADDR) + +/* '328-compatible definitions */ +#define TPRER1_ADDR TPRER_ADDR +#define TPRER1 TPRER + +/* + * Timer Compare Register + */ +#define TCMP_ADDR 0xfffff604 +#define TCMP WORD_REF(TCMP_ADDR) + +/* '328-compatible definitions */ +#define TCMP1_ADDR TCMP_ADDR +#define TCMP1 TCMP + +/* + * Timer Capture register + */ +#define TCR_ADDR 0xfffff606 +#define TCR WORD_REF(TCR_ADDR) + +/* '328-compatible definitions */ +#define TCR1_ADDR TCR_ADDR +#define TCR1 TCR + +/* + * Timer Counter Register + */ +#define TCN_ADDR 0xfffff608 +#define TCN WORD_REF(TCN_ADDR) + +/* '328-compatible definitions */ +#define TCN1_ADDR TCN_ADDR +#define TCN1 TCN + +/* + * Timer Status Register + */ +#define TSTAT_ADDR 0xfffff60a +#define TSTAT WORD_REF(TSTAT_ADDR) + +#define TSTAT_COMP 0x0001 /* Compare Event occurred */ +#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ + +/* '328-compatible definitions */ +#define TSTAT1_ADDR TSTAT_ADDR +#define TSTAT1 TSTAT + +/********** + * + * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) + * + **********/ + +/* + * SPIM Data Register + */ +#define SPIMDATA_ADDR 0xfffff800 +#define SPIMDATA WORD_REF(SPIMDATA_ADDR) + +/* + * SPIM Control/Status Register + */ +#define SPIMCONT_ADDR 0xfffff802 +#define SPIMCONT WORD_REF(SPIMCONT_ADDR) + +#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ +#define SPIMCONT_BIT_COUNT_SHIFT 0 +#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ +#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ +#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ +#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ +#define SPIMCONT_XCH 0x0100 /* Exchange */ +#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ +#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ +#define SPIMCONT_DATA_RATE_SHIFT 13 + +/* '328-compatible definitions */ +#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ +#define SPIMCONT_SPIMEN SPIMCONT_ENABLE + +/********** + * + * 0xFFFFF9xx -- UART + * + **********/ + +/* + * UART Status/Control Register + */ + +#define USTCNT_ADDR 0xfffff900 +#define USTCNT WORD_REF(USTCNT_ADDR) + +#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ +#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ +#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ +#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ +#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ +#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ +#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ +#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ +#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ +#define USTCNT_STOP 0x0200 /* Stop bit transmission */ +#define USTCNT_ODD 0x0400 /* Odd Parity */ +#define USTCNT_PEN 0x0800 /* Parity Enable */ +#define USTCNT_CLKM 0x1000 /* Clock Mode Select */ +#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ +#define USTCNT_RXEN 0x4000 /* Receiver Enable */ +#define USTCNT_UEN 0x8000 /* UART Enable */ + +/* '328-compatible definitions */ +#define USTCNT_TXAVAILEN USTCNT_TXAE +#define USTCNT_TXHALFEN USTCNT_TXHE +#define USTCNT_TXEMPTYEN USTCNT_TXEE +#define USTCNT_RXREADYEN USTCNT_RXRE +#define USTCNT_RXHALFEN USTCNT_RXHE +#define USTCNT_RXFULLEN USTCNT_RXFE +#define USTCNT_CTSDELTAEN USTCNT_CTSD +#define USTCNT_ODD_EVEN USTCNT_ODD +#define USTCNT_PARITYEN USTCNT_PEN +#define USTCNT_CLKMODE USTCNT_CLKM +#define USTCNT_UARTEN USTCNT_UEN + +/* + * UART Baud Control Register + */ +#define UBAUD_ADDR 0xfffff902 +#define UBAUD WORD_REF(UBAUD_ADDR) + +#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ +#define UBAUD_PRESCALER_SHIFT 0 +#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ +#define UBAUD_DIVIDE_SHIFT 8 +#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ +#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ + +/* + * UART Receiver Register + */ +#define URX_ADDR 0xfffff904 +#define URX WORD_REF(URX_ADDR) + +#define URX_RXDATA_ADDR 0xfffff905 +#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) + +#define URX_RXDATA_MASK 0x00ff /* Received data */ +#define URX_RXDATA_SHIFT 0 +#define URX_PARITY_ERROR 0x0100 /* Parity Error */ +#define URX_BREAK 0x0200 /* Break Detected */ +#define URX_FRAME_ERROR 0x0400 /* Framing Error */ +#define URX_OVRUN 0x0800 /* Serial Overrun */ +#define URX_OLD_DATA 0x1000 /* Old data in FIFO */ +#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ +#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ +#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ + +/* + * UART Transmitter Register + */ +#define UTX_ADDR 0xfffff906 +#define UTX WORD_REF(UTX_ADDR) + +#define UTX_TXDATA_ADDR 0xfffff907 +#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) + +#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ +#define UTX_TXDATA_SHIFT 0 +#define UTX_CTS_DELTA 0x0100 /* CTS changed */ +#define UTX_CTS_STAT 0x0200 /* CTS State */ +#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ +#define UTX_NOCTS 0x0800 /* Ignore CTS */ +#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ +#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ +#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ +#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ + +/* '328-compatible definitions */ +#define UTX_CTS_STATUS UTX_CTS_STAT +#define UTX_IGNORE_CTS UTX_NOCTS + +/* + * UART Miscellaneous Register + */ +#define UMISC_ADDR 0xfffff908 +#define UMISC WORD_REF(UMISC_ADDR) + +#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ +#define UMISC_RX_POL 0x0008 /* Receive Polarity */ +#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ +#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ +#define UMISC_RTS 0x0040 /* Set RTS status */ +#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ +#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ +#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ +#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ +#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ +#define UMISC_CLKSRC 0x4000 /* Clock Source */ +#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ + +/* + * UART Non-integer Prescaler Register + */ +#define NIPR_ADDR 0xfffff90a +#define NIPR WORD_REF(NIPR_ADDR) + +#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ +#define NIPR_STEP_VALUE_SHIFT 0 +#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ +#define NIPR_SELECT_SHIFT 8 +#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ + + +/* generalization of uart control registers to support multiple ports: */ +typedef struct { + volatile unsigned short int ustcnt; + volatile unsigned short int ubaud; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char rxdata; + } b; + } urx; + union { + volatile unsigned short int w; + struct { + volatile unsigned char status; + volatile unsigned char txdata; + } b; + } utx; + volatile unsigned short int umisc; + volatile unsigned short int nipr; + volatile unsigned short int hmark; + volatile unsigned short int unused; +} __attribute__((packed)) m68328_uart; + + + + +/********** + * + * 0xFFFFFAxx -- LCD Controller + * + **********/ + +/* + * LCD Screen Starting Address Register + */ +#define LSSA_ADDR 0xfffffa00 +#define LSSA LONG_REF(LSSA_ADDR) + +#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ + +/* + * LCD Virtual Page Width Register + */ +#define LVPW_ADDR 0xfffffa05 +#define LVPW BYTE_REF(LVPW_ADDR) + +/* + * LCD Screen Width Register (not compatible with '328 !!!) + */ +#define LXMAX_ADDR 0xfffffa08 +#define LXMAX WORD_REF(LXMAX_ADDR) + +#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ + +/* + * LCD Screen Height Register + */ +#define LYMAX_ADDR 0xfffffa0a +#define LYMAX WORD_REF(LYMAX_ADDR) + +#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ + +/* + * LCD Cursor X Position Register + */ +#define LCXP_ADDR 0xfffffa18 +#define LCXP WORD_REF(LCXP_ADDR) + +#define LCXP_CC_MASK 0xc000 /* Cursor Control */ +#define LCXP_CC_TRAMSPARENT 0x0000 +#define LCXP_CC_BLACK 0x4000 +#define LCXP_CC_REVERSED 0x8000 +#define LCXP_CC_WHITE 0xc000 +#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ + +/* + * LCD Cursor Y Position Register + */ +#define LCYP_ADDR 0xfffffa1a +#define LCYP WORD_REF(LCYP_ADDR) + +#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ + +/* + * LCD Cursor Width and Heigth Register + */ +#define LCWCH_ADDR 0xfffffa1c +#define LCWCH WORD_REF(LCWCH_ADDR) + +#define LCWCH_CH_MASK 0x001f /* Cursor Height */ +#define LCWCH_CH_SHIFT 0 +#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ +#define LCWCH_CW_SHIFT 8 + +/* + * LCD Blink Control Register + */ +#define LBLKC_ADDR 0xfffffa1f +#define LBLKC BYTE_REF(LBLKC_ADDR) + +#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ +#define LBLKC_BD_SHIFT 0 +#define LBLKC_BKEN 0x80 /* Blink Enabled */ + +/* + * LCD Panel Interface Configuration Register + */ +#define LPICF_ADDR 0xfffffa20 +#define LPICF BYTE_REF(LPICF_ADDR) + +#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ +#define LPICF_GS_BW 0x00 +#define LPICF_GS_GRAY_4 0x01 +#define LPICF_GS_GRAY_16 0x02 +#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ +#define LPICF_PBSIZ_1 0x00 +#define LPICF_PBSIZ_2 0x04 +#define LPICF_PBSIZ_4 0x08 + +/* + * LCD Polarity Configuration Register + */ +#define LPOLCF_ADDR 0xfffffa21 +#define LPOLCF BYTE_REF(LPOLCF_ADDR) + +#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ +#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ +#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ +#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ + +/* + * LACD (LCD Alternate Crystal Direction) Rate Control Register + */ +#define LACDRC_ADDR 0xfffffa23 +#define LACDRC BYTE_REF(LACDRC_ADDR) + +#define LACDRC_ACDSLT 0x80 /* Signal Source Select */ +#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ +#define LACDRC_ACD_SHIFT 0 + +/* + * LCD Pixel Clock Divider Register + */ +#define LPXCD_ADDR 0xfffffa25 +#define LPXCD BYTE_REF(LPXCD_ADDR) + +#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ +#define LPXCD_PCD_SHIFT 0 + +/* + * LCD Clocking Control Register + */ +#define LCKCON_ADDR 0xfffffa27 +#define LCKCON BYTE_REF(LCKCON_ADDR) + +#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ +#define LCKCON_DWS_SHIFT 0 +#define LCKCON_DWIDTH 0x40 /* Display Memory Width */ +#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ + +/* '328-compatible definitions */ +#define LCKCON_DW_MASK LCKCON_DWS_MASK +#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT + +/* + * LCD Refresh Rate Adjustment Register + */ +#define LRRA_ADDR 0xfffffa29 +#define LRRA BYTE_REF(LRRA_ADDR) + +/* + * LCD Panning Offset Register + */ +#define LPOSR_ADDR 0xfffffa2d +#define LPOSR BYTE_REF(LPOSR_ADDR) + +#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ +#define LPOSR_POS_SHIFT 0 + +/* + * LCD Frame Rate Control Modulation Register + */ +#define LFRCM_ADDR 0xfffffa31 +#define LFRCM BYTE_REF(LFRCM_ADDR) + +#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ +#define LFRCM_YMOD_SHIFT 0 +#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ +#define LFRCM_XMOD_SHIFT 4 + +/* + * LCD Gray Palette Mapping Register + */ +#define LGPMR_ADDR 0xfffffa33 +#define LGPMR BYTE_REF(LGPMR_ADDR) + +#define LGPMR_G1_MASK 0x0f +#define LGPMR_G1_SHIFT 0 +#define LGPMR_G2_MASK 0xf0 +#define LGPMR_G2_SHIFT 4 + +/* + * PWM Contrast Control Register + */ +#define PWMR_ADDR 0xfffffa36 +#define PWMR WORD_REF(PWMR_ADDR) + +#define PWMR_PW_MASK 0x00ff /* Pulse Width */ +#define PWMR_PW_SHIFT 0 +#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ +#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ +#define PWMR_SRC_LINE 0x0000 /* Line Pulse */ +#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ +#define PWMR_SRC_LCD 0x4000 /* LCD clock */ + +/********** + * + * 0xFFFFFBxx -- Real-Time Clock (RTC) + * + **********/ + +/* + * RTC Hours Minutes and Seconds Register + */ +#define RTCTIME_ADDR 0xfffffb00 +#define RTCTIME LONG_REF(RTCTIME_ADDR) + +#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCTIME_SECONDS_SHIFT 0 +#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCTIME_MINUTES_SHIFT 16 +#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCTIME_HOURS_SHIFT 24 + +/* + * RTC Alarm Register + */ +#define RTCALRM_ADDR 0xfffffb04 +#define RTCALRM LONG_REF(RTCALRM_ADDR) + +#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ +#define RTCALRM_SECONDS_SHIFT 0 +#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ +#define RTCALRM_MINUTES_SHIFT 16 +#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ +#define RTCALRM_HOURS_SHIFT 24 + +/* + * Watchdog Timer Register + */ +#define WATCHDOG_ADDR 0xfffffb0a +#define WATCHDOG WORD_REF(WATCHDOG_ADDR) + +#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ +#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ +#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ +#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ +#define WATCHDOG_CNT_SHIFT 8 + +/* + * RTC Control Register + */ +#define RTCCTL_ADDR 0xfffffb0c +#define RTCCTL WORD_REF(RTCCTL_ADDR) + +#define RTCCTL_XTL 0x0020 /* Crystal Selection */ +#define RTCCTL_EN 0x0080 /* RTC Enable */ + +/* '328-compatible definitions */ +#define RTCCTL_384 RTCCTL_XTL +#define RTCCTL_ENABLE RTCCTL_EN + +/* + * RTC Interrupt Status Register + */ +#define RTCISR_ADDR 0xfffffb0e +#define RTCISR WORD_REF(RTCISR_ADDR) + +#define RTCISR_SW 0x0001 /* Stopwatch timed out */ +#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ +#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ +#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ +#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ +#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ +#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ +#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ +#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ +#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ +#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ +#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ +#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ +#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ + +/* + * RTC Interrupt Enable Register + */ +#define RTCIENR_ADDR 0xfffffb10 +#define RTCIENR WORD_REF(RTCIENR_ADDR) + +#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ +#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ +#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ +#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ +#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ +#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ +#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ +#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ +#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ +#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ +#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ +#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ +#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ +#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ + +/* + * Stopwatch Minutes Register + */ +#define STPWCH_ADDR 0xfffffb12 +#define STPWCH WORD_REF(STPWCH_ADDR) + +#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ +#define SPTWCH_CNT_SHIFT 0 + +/* + * RTC Day Count Register + */ +#define DAYR_ADDR 0xfffffb1a +#define DAYR WORD_REF(DAYR_ADDR) + +#define DAYR_DAYS_MASK 0x1ff /* Day Setting */ +#define DAYR_DAYS_SHIFT 0 + +/* + * RTC Day Alarm Register + */ +#define DAYALARM_ADDR 0xfffffb1c +#define DAYALARM WORD_REF(DAYALARM_ADDR) + +#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ +#define DAYALARM_DAYSAL_SHIFT 0 + +/********** + * + * 0xFFFFFCxx -- DRAM Controller + * + **********/ + +/* + * DRAM Memory Configuration Register + */ +#define DRAMMC_ADDR 0xfffffc00 +#define DRAMMC WORD_REF(DRAMMC_ADDR) + +#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ +#define DRAMMC_ROW12_PA10 0x0000 +#define DRAMMC_ROW12_PA21 0x4000 +#define DRAMMC_ROW12_PA23 0x8000 +#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ +#define DRAMMC_ROW0_PA11 0x0000 +#define DRAMMC_ROW0_PA22 0x1000 +#define DRAMMC_ROW0_PA23 0x2000 +#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ +#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ +#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ +#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ +#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ +#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ +#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ +#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ +#define DRAMMC_REF_SHIFT 0 + +/* + * DRAM Control Register + */ +#define DRAMC_ADDR 0xfffffc02 +#define DRAMC WORD_REF(DRAMC_ADDR) + +#define DRAMC_DWE 0x0001 /* DRAM Write Enable */ +#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ +#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ +#define DRAMC_SLW 0x0008 /* Slow RAM */ +#define DRAMC_LSP 0x0010 /* Light Sleep */ +#define DRAMC_MSW 0x0020 /* Slow Multiplexing */ +#define DRAMC_WS_MASK 0x00c0 /* Wait-states */ +#define DRAMC_WS_SHIFT 6 +#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ +#define DRAMC_PGSZ_SHIFT 8 +#define DRAMC_PGSZ_256K 0x0000 +#define DRAMC_PGSZ_512K 0x0100 +#define DRAMC_PGSZ_1024K 0x0200 +#define DRAMC_PGSZ_2048K 0x0300 +#define DRAMC_EDO 0x0400 /* EDO DRAM */ +#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ +#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ +#define DRAMC_BC_SHIFT 12 +#define DRAMC_RM 0x4000 /* Refresh Mode */ +#define DRAMC_EN 0x8000 /* DRAM Controller enable */ + + +/********** + * + * 0xFFFFFDxx -- In-Circuit Emulation (ICE) + * + **********/ + +/* + * ICE Module Address Compare Register + */ +#define ICEMACR_ADDR 0xfffffd00 +#define ICEMACR LONG_REF(ICEMACR_ADDR) + +/* + * ICE Module Address Mask Register + */ +#define ICEMAMR_ADDR 0xfffffd04 +#define ICEMAMR LONG_REF(ICEMAMR_ADDR) + +/* + * ICE Module Control Compare Register + */ +#define ICEMCCR_ADDR 0xfffffd08 +#define ICEMCCR WORD_REF(ICEMCCR_ADDR) + +#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ +#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ + +/* + * ICE Module Control Mask Register + */ +#define ICEMCMR_ADDR 0xfffffd0a +#define ICEMCMR WORD_REF(ICEMCMR_ADDR) + +#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ +#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ + +/* + * ICE Module Control Register + */ +#define ICEMCR_ADDR 0xfffffd0c +#define ICEMCR WORD_REF(ICEMCR_ADDR) + +#define ICEMCR_CEN 0x0001 /* Compare Enable */ +#define ICEMCR_PBEN 0x0002 /* Program Break Enable */ +#define ICEMCR_SB 0x0004 /* Single Breakpoint */ +#define ICEMCR_HMDIS 0x0008 /* HardMap disable */ +#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ + +/* + * ICE Module Status Register + */ +#define ICEMSR_ADDR 0xfffffd0e +#define ICEMSR WORD_REF(ICEMSR_ADDR) + +#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ +#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ +#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ +#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ + +#endif /* _MC68VZ328_H_ */ diff --git a/arch/m68knommu/include/asm/a.out.h b/arch/m68knommu/include/asm/a.out.h new file mode 100644 index 000000000000..ce18ef99de04 --- /dev/null +++ b/arch/m68knommu/include/asm/a.out.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/anchor.h b/arch/m68knommu/include/asm/anchor.h new file mode 100644 index 000000000000..871c0d5cfc3d --- /dev/null +++ b/arch/m68knommu/include/asm/anchor.h @@ -0,0 +1,112 @@ +/****************************************************************************/ + +/* + * anchor.h -- Anchor CO-MEM Lite PCI host bridge part. + * + * (C) Copyright 2000, Moreton Bay (www.moreton.com.au) + */ + +/****************************************************************************/ +#ifndef anchor_h +#define anchor_h +/****************************************************************************/ + +/* + * Define basic addressing info. + */ +#if defined(CONFIG_M5407C3) +#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */ +#define COMEM_IRQ 25 /* IRQ of anchor part */ +#else +#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */ +#define COMEM_IRQ 25 /* IRQ of anchor part */ +#endif + +/****************************************************************************/ + +/* + * 4-byte registers of CO-MEM, so adjust register addresses for + * easy access. Handy macro for word access too. + */ +#define LREG(a) ((a) >> 2) +#define WREG(a) ((a) >> 1) + + +/* + * Define base addresses within CO-MEM Lite register address space. + */ +#define COMEM_I2O 0x0000 /* I2O registers */ +#define COMEM_OPREGS 0x0400 /* Operation registers */ +#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */ +#define COMEM_SHMEM 0x4000 /* Shared memory region */ + +#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */ + + +/* + * Define CO-MEM Registers. + */ +#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */ +#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */ +#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */ +#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */ +#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */ +#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */ +#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */ +#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */ + +#define COMEM_DAHBASE 0x0460 /* Direct access base address */ + +#define COMEM_NVCMD 0x04a0 /* I2C serial command */ +#define COMEM_NVREAD 0x04a4 /* I2C serial read */ +#define COMEM_NVSTAT 0x04a8 /* I2C status */ + +#define COMEM_DMALBASE 0x04b0 /* DMA local base address */ +#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */ +#define COMEM_DMASIZE 0x04b8 /* DMA size */ +#define COMEM_DMACTL 0x04bc /* DMA control */ + +#define COMEM_HCTL 0x04e0 /* Host control */ +#define COMEM_HINT 0x04e4 /* Host interrupt control/status */ +#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */ +#define COMEM_LINT 0x04f4 /* Local interrupt contole status */ +#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */ + +#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */ + + +/* + * Commands and flags for use with Direct Access Register. + */ +#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */ +#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */ +#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */ +#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */ +#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */ +#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */ +#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */ +#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */ + +#define COMEM_DA_ADDR(a) ((a) & 0xffffe000) + +#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff) + + +/* + * The PCI bus will be limited in what slots will actually be used. + * Define valid device numbers for different boards. + */ +#if defined(CONFIG_M5407C3) +#define COMEM_MINDEV 14 /* Minimum valid DEVICE */ +#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */ +#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */ +#else +#define COMEM_MINDEV 0 /* Minimum valid DEVICE */ +#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */ +#endif + +#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */ + + +/****************************************************************************/ +#endif /* anchor_h */ diff --git a/arch/m68knommu/include/asm/atomic.h b/arch/m68knommu/include/asm/atomic.h new file mode 100644 index 000000000000..d5632a305dae --- /dev/null +++ b/arch/m68knommu/include/asm/atomic.h @@ -0,0 +1,155 @@ +#ifndef __ARCH_M68KNOMMU_ATOMIC__ +#define __ARCH_M68KNOMMU_ATOMIC__ + +#include + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + */ + +/* + * We do not have SMP m68k systems, so we don't have to deal with that. + */ + +typedef struct { int counter; } atomic_t; +#define ATOMIC_INIT(i) { (i) } + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v, i) (((v)->counter) = i) + +static __inline__ void atomic_add(int i, atomic_t *v) +{ +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i)); +#else + __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i)); +#endif +} + +static __inline__ void atomic_sub(int i, atomic_t *v) +{ +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i)); +#else + __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i)); +#endif +} + +static __inline__ int atomic_sub_and_test(int i, atomic_t * v) +{ + char c; +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__("subl %2,%1; seq %0" + : "=d" (c), "+m" (*v) + : "d" (i)); +#else + __asm__ __volatile__("subl %2,%1; seq %0" + : "=d" (c), "+m" (*v) + : "di" (i)); +#endif + return c != 0; +} + +static __inline__ void atomic_inc(volatile atomic_t *v) +{ + __asm__ __volatile__("addql #1,%0" : "+m" (*v)); +} + +/* + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ + +static __inline__ int atomic_inc_and_test(volatile atomic_t *v) +{ + char c; + __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); + return c != 0; +} + +static __inline__ void atomic_dec(volatile atomic_t *v) +{ + __asm__ __volatile__("subql #1,%0" : "+m" (*v)); +} + +static __inline__ int atomic_dec_and_test(volatile atomic_t *v) +{ + char c; + __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); + return c != 0; +} + +static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v) +{ + __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); +} + +static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v) +{ + __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); +} + +/* Atomic operations are already serializing */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +static inline int atomic_add_return(int i, atomic_t * v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp += i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) + +static inline int atomic_sub_return(int i, atomic_t * v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp -= i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) +#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) + +static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) +{ + int c, old; + c = atomic_read(v); + for (;;) { + if (unlikely(c == (u))) + break; + old = atomic_cmpxchg((v), c, c + (a)); + if (likely(old == c)) + break; + c = old; + } + return c != (u); +} + +#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) + +#define atomic_dec_return(v) atomic_sub_return(1,(v)) +#define atomic_inc_return(v) atomic_add_return(1,(v)) + +#include +#endif /* __ARCH_M68KNOMMU_ATOMIC __ */ diff --git a/arch/m68knommu/include/asm/auxvec.h b/arch/m68knommu/include/asm/auxvec.h new file mode 100644 index 000000000000..844d6d52204b --- /dev/null +++ b/arch/m68knommu/include/asm/auxvec.h @@ -0,0 +1,4 @@ +#ifndef __ASMm68k_AUXVEC_H +#define __ASMm68k_AUXVEC_H + +#endif diff --git a/arch/m68knommu/include/asm/bitops.h b/arch/m68knommu/include/asm/bitops.h new file mode 100644 index 000000000000..6f3685eab44c --- /dev/null +++ b/arch/m68knommu/include/asm/bitops.h @@ -0,0 +1,336 @@ +#ifndef _M68KNOMMU_BITOPS_H +#define _M68KNOMMU_BITOPS_H + +/* + * Copyright 1992, Linus Torvalds. + */ + +#include +#include /* swab32 */ + +#ifdef __KERNEL__ + +#ifndef _LINUX_BITOPS_H +#error only can be included directly +#endif + +#if defined (__mcfisaaplus__) || defined (__mcfisac__) +static inline int ffs(unsigned int val) +{ + if (!val) + return 0; + + asm volatile( + "bitrev %0\n\t" + "ff1 %0\n\t" + : "=d" (val) + : "0" (val) + ); + val++; + return val; +} + +static inline int __ffs(unsigned int val) +{ + asm volatile( + "bitrev %0\n\t" + "ff1 %0\n\t" + : "=d" (val) + : "0" (val) + ); + return val; +} + +#else +#include +#include +#endif + +#include +#include + +static __inline__ void set_bit(int nr, volatile unsigned long * addr) +{ +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0", "cc"); +#else + __asm__ __volatile__ ("bset %1,%0" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + : "cc"); +#endif +} + +#define __set_bit(nr, addr) set_bit(nr, addr) + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() + +static __inline__ void clear_bit(int nr, volatile unsigned long * addr) +{ +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0", "cc"); +#else + __asm__ __volatile__ ("bclr %1,%0" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + : "cc"); +#endif +} + +#define __clear_bit(nr, addr) clear_bit(nr, addr) + +static __inline__ void change_bit(int nr, volatile unsigned long * addr) +{ +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0", "cc"); +#else + __asm__ __volatile__ ("bchg %1,%0" + : "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + : "cc"); +#endif +} + +#define __change_bit(nr, addr) change_bit(nr, addr) + +static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("bset %2,%1; sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) + +static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("bclr %2,%1; sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) + +static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("bchg %2,%1; sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) + : "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr) + +/* + * This routine doesn't need to be atomic. + */ +static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr) +{ + return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; +} + +static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) +{ + int * a = (int *) addr; + int mask; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + return ((mask & *a) != 0); +} + +#define test_bit(nr,addr) \ +(__builtin_constant_p(nr) ? \ + __constant_test_bit((nr),(addr)) : \ + __test_bit((nr),(addr))) + +#include +#include +#include + +static __inline__ int ext2_set_bit(int nr, volatile void * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) + : "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("bset %2,%1; sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) + : "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +static __inline__ int ext2_clear_bit(int nr, volatile void * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) + : "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("bclr %2,%1; sne %0" + : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) + : "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +#define ext2_set_bit_atomic(lock, nr, addr) \ + ({ \ + int ret; \ + spin_lock(lock); \ + ret = ext2_set_bit((nr), (addr)); \ + spin_unlock(lock); \ + ret; \ + }) + +#define ext2_clear_bit_atomic(lock, nr, addr) \ + ({ \ + int ret; \ + spin_lock(lock); \ + ret = ext2_clear_bit((nr), (addr)); \ + spin_unlock(lock); \ + ret; \ + }) + +static __inline__ int ext2_test_bit(int nr, const volatile void * addr) +{ + char retval; + +#ifdef CONFIG_COLDFIRE + __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0" + : "=d" (retval) + : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr) + : "%a0"); +#else + __asm__ __volatile__ ("btst %2,%1; sne %0" + : "=d" (retval) + : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr) + /* No clobber */); +#endif + + return retval; +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease performance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} + +#define ext2_find_next_bit(addr, size, off) \ + generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) +#include + +#endif /* __KERNEL__ */ + +#include +#include + +#endif /* _M68KNOMMU_BITOPS_H */ diff --git a/arch/m68knommu/include/asm/bootinfo.h b/arch/m68knommu/include/asm/bootinfo.h new file mode 100644 index 000000000000..c12e526f5189 --- /dev/null +++ b/arch/m68knommu/include/asm/bootinfo.h @@ -0,0 +1,2 @@ + +/* Nothing for m68knommu */ diff --git a/arch/m68knommu/include/asm/bootstd.h b/arch/m68knommu/include/asm/bootstd.h new file mode 100644 index 000000000000..bdc1a4ac4fe9 --- /dev/null +++ b/arch/m68knommu/include/asm/bootstd.h @@ -0,0 +1,132 @@ +/* bootstd.h: Bootloader system call interface + * + * (c) 1999, Rt-Control, Inc. + */ + +#ifndef __BOOTSTD_H__ +#define __BOOTSTD_H__ + +#define NR_BSC 21 /* last used bootloader system call */ + +#define __BN_reset 0 /* reset and start the bootloader */ +#define __BN_test 1 /* tests the system call interface */ +#define __BN_exec 2 /* executes a bootloader image */ +#define __BN_exit 3 /* terminates a bootloader image */ +#define __BN_program 4 /* program FLASH from a chain */ +#define __BN_erase 5 /* erase sector(s) of FLASH */ +#define __BN_open 6 +#define __BN_write 7 +#define __BN_read 8 +#define __BN_close 9 +#define __BN_mmap 10 /* map a file descriptor into memory */ +#define __BN_munmap 11 /* remove a file to memory mapping */ +#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */ +#define __BN_getserialnum 13 /* get the serial number of this board */ +#define __BN_getbenv 14 /* get a bootloader envvar */ +#define __BN_setbenv 15 /* get a bootloader envvar */ +#define __BN_setpmask 16 /* set the protection mask */ +#define __BN_readenv 17 /* read environment variables */ +#define __BN_flash_chattr_range 18 +#define __BN_flash_erase_range 19 +#define __BN_flash_write_range 20 + +/* Calling conventions compatible to (uC)linux/68k + * We use simmilar macros to call into the bootloader as for uClinux + */ + +#define __bsc_return(type, res) \ +do { \ + if ((unsigned long)(res) >= (unsigned long)(-64)) { \ + /* let errno be a function, preserve res in %d0 */ \ + int __err = -(res); \ + errno = __err; \ + res = -1; \ + } \ + return (type)(res); \ +} while (0) + +#define _bsc0(type,name) \ +type name(void) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res) \ + ); \ + __bsc_return(type,__res); \ +} + +#define _bsc1(type,name,atype,a) \ +type name(atype a) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + register long __a __asm__ ("%d1") = (long)a; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res), "d" (__a) \ + ); \ + __bsc_return(type,__res); \ +} + +#define _bsc2(type,name,atype,a,btype,b) \ +type name(atype a, btype b) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + register long __a __asm__ ("%d1") = (long)a; \ + register long __b __asm__ ("%d2") = (long)b; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res), "d" (__a), "d" (__b) \ + ); \ + __bsc_return(type,__res); \ +} + +#define _bsc3(type,name,atype,a,btype,b,ctype,c) \ +type name(atype a, btype b, ctype c) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + register long __a __asm__ ("%d1") = (long)a; \ + register long __b __asm__ ("%d2") = (long)b; \ + register long __c __asm__ ("%d3") = (long)c; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res), "d" (__a), "d" (__b), \ + "d" (__c) \ + ); \ + __bsc_return(type,__res); \ +} + +#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ +type name(atype a, btype b, ctype c, dtype d) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + register long __a __asm__ ("%d1") = (long)a; \ + register long __b __asm__ ("%d2") = (long)b; \ + register long __c __asm__ ("%d3") = (long)c; \ + register long __d __asm__ ("%d4") = (long)d; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res), "d" (__a), "d" (__b), \ + "d" (__c), "d" (__d) \ + ); \ + __bsc_return(type,__res); \ +} + +#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ +type name(atype a, btype b, ctype c, dtype d, etype e) \ +{ \ + register long __res __asm__ ("%d0") = __BN_##name; \ + register long __a __asm__ ("%d1") = (long)a; \ + register long __b __asm__ ("%d2") = (long)b; \ + register long __c __asm__ ("%d3") = (long)c; \ + register long __d __asm__ ("%d4") = (long)d; \ + register long __e __asm__ ("%d5") = (long)e; \ + __asm__ __volatile__ ("trap #2" \ + : "=g" (__res) \ + : "0" (__res), "d" (__a), "d" (__b), \ + "d" (__c), "d" (__d), "d" (__e) \ + ); \ + __bsc_return(type,__res); \ +} + +#endif /* __BOOTSTD_H__ */ diff --git a/arch/m68knommu/include/asm/bug.h b/arch/m68knommu/include/asm/bug.h new file mode 100644 index 000000000000..70e7dc0af21a --- /dev/null +++ b/arch/m68knommu/include/asm/bug.h @@ -0,0 +1,4 @@ +#ifndef _M68KNOMMU_BUG_H +#define _M68KNOMMU_BUG_H +#include +#endif diff --git a/arch/m68knommu/include/asm/bugs.h b/arch/m68knommu/include/asm/bugs.h new file mode 100644 index 000000000000..5f382dac3a60 --- /dev/null +++ b/arch/m68knommu/include/asm/bugs.h @@ -0,0 +1,16 @@ +/* + * include/asm-m68k/bugs.h + * + * Copyright (C) 1994 Linus Torvalds + */ + +/* + * This is included by init/main.c to check for architecture-dependent bugs. + * + * Needs: + * void check_bugs(void); + */ + +static void check_bugs(void) +{ +} diff --git a/arch/m68knommu/include/asm/byteorder.h b/arch/m68knommu/include/asm/byteorder.h new file mode 100644 index 000000000000..20bb4426b610 --- /dev/null +++ b/arch/m68knommu/include/asm/byteorder.h @@ -0,0 +1,27 @@ +#ifndef _M68KNOMMU_BYTEORDER_H +#define _M68KNOMMU_BYTEORDER_H + +#include + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#if defined (__mcfisaaplus__) || defined (__mcfisac__) +static inline __attribute_const__ __u32 ___arch__swab32(__u32 val) +{ + asm( + "byterev %0" + : "=d" (val) + : "0" (val) + ); + return val; +} + +#define __arch__swab32(x) ___arch__swab32(x) +#endif + +#include + +#endif /* _M68KNOMMU_BYTEORDER_H */ diff --git a/arch/m68knommu/include/asm/cache.h b/arch/m68knommu/include/asm/cache.h new file mode 100644 index 000000000000..24e9eace5f8c --- /dev/null +++ b/arch/m68knommu/include/asm/cache.h @@ -0,0 +1,12 @@ +#ifndef __ARCH_M68KNOMMU_CACHE_H +#define __ARCH_M68KNOMMU_CACHE_H + +/* bytes per L1 cache line */ +#define L1_CACHE_BYTES 16 /* this need to be at least 1 */ + +/* m68k-elf-gcc 2.95.2 doesn't like these */ + +#define __cacheline_aligned +#define ____cacheline_aligned + +#endif diff --git a/arch/m68knommu/include/asm/cachectl.h b/arch/m68knommu/include/asm/cachectl.h new file mode 100644 index 000000000000..bcf5a6a9dd52 --- /dev/null +++ b/arch/m68knommu/include/asm/cachectl.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/cacheflush.h b/arch/m68knommu/include/asm/cacheflush.h new file mode 100644 index 000000000000..87e5dc0413b4 --- /dev/null +++ b/arch/m68knommu/include/asm/cacheflush.h @@ -0,0 +1,84 @@ +#ifndef _M68KNOMMU_CACHEFLUSH_H +#define _M68KNOMMU_CACHEFLUSH_H + +/* + * (C) Copyright 2000-2004, Greg Ungerer + */ +#include + +#define flush_cache_all() __flush_cache_all() +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) __flush_cache_all() +#define flush_cache_page(vma, vmaddr) do { } while (0) +#define flush_dcache_range(start,len) __flush_cache_all() +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_range(start,len) __flush_cache_all() +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_vmap(start, end) do { } while (0) +#define flush_cache_vunmap(start, end) do { } while (0) + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + memcpy(dst, src, len) + +static inline void __flush_cache_all(void) +{ +#ifdef CONFIG_M5407 + /* + * Use cpushl to push and invalidate all cache lines. + * Gas doesn't seem to know how to generate the ColdFire + * cpushl instruction... Oh well, bit stuff it for now. + */ + __asm__ __volatile__ ( + "nop\n\t" + "clrl %%d0\n\t" + "1:\n\t" + "movel %%d0,%%a0\n\t" + "2:\n\t" + ".word 0xf468\n\t" + "addl #0x10,%%a0\n\t" + "cmpl #0x00000800,%%a0\n\t" + "blt 2b\n\t" + "addql #1,%%d0\n\t" + "cmpil #4,%%d0\n\t" + "bne 1b\n\t" + "movel #0xb6088500,%%d0\n\t" + "movec %%d0,%%CACR\n\t" + : : : "d0", "a0" ); +#endif /* CONFIG_M5407 */ +#if defined(CONFIG_M527x) || defined(CONFIG_M528x) + __asm__ __volatile__ ( + "movel #0x81000200, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : : "d0" ); +#endif /* CONFIG_M527x || CONFIG_M528x */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) + __asm__ __volatile__ ( + "movel #0x81000100, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : : "d0" ); +#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ +#ifdef CONFIG_M5249 + __asm__ __volatile__ ( + "movel #0xa1000200, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : : "d0" ); +#endif /* CONFIG_M5249 */ +#ifdef CONFIG_M532x + __asm__ __volatile__ ( + "movel #0x81000200, %%d0\n\t" + "movec %%d0, %%CACR\n\t" + "nop\n\t" + : : : "d0" ); +#endif /* CONFIG_M532x */ +} + +#endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/arch/m68knommu/include/asm/checksum.h b/arch/m68knommu/include/asm/checksum.h new file mode 100644 index 000000000000..81883482ffb1 --- /dev/null +++ b/arch/m68knommu/include/asm/checksum.h @@ -0,0 +1,132 @@ +#ifndef _M68K_CHECKSUM_H +#define _M68K_CHECKSUM_H + +#include + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +__wsum csum_partial(const void *buff, int len, __wsum sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +__wsum csum_partial_copy_nocheck(const void *src, void *dst, + int len, __wsum sum); + + +/* + * the same as csum_partial_copy, but copies from user space. + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +extern __wsum csum_partial_copy_from_user(const void __user *src, + void *dst, int len, __wsum sum, int *csum_err); + +__sum16 ip_fast_csum(const void *iph, unsigned int ihl); + +/* + * Fold a partial checksum + */ + +static inline __sum16 csum_fold(__wsum sum) +{ + unsigned int tmp = (__force u32)sum; +#ifdef CONFIG_COLDFIRE + tmp = (tmp & 0xffff) + (tmp >> 16); + tmp = (tmp & 0xffff) + (tmp >> 16); + return (__force __sum16)~tmp; +#else + __asm__("swap %1\n\t" + "addw %1, %0\n\t" + "clrw %1\n\t" + "addxw %1, %0" + : "=&d" (sum), "=&d" (tmp) + : "0" (sum), "1" (sum)); + return (__force __sum16)~sum; +#endif +} + + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ + +static inline __wsum +csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + __asm__ ("addl %1,%0\n\t" + "addxl %4,%0\n\t" + "addxl %5,%0\n\t" + "clrl %1\n\t" + "addxl %1,%0" + : "=&d" (sum), "=&d" (saddr) + : "0" (daddr), "1" (saddr), "d" (len + proto), + "d"(sum)); + return sum; +} + +static inline __sum16 +csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, + unsigned short proto, __wsum sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +extern __sum16 ip_compute_csum(const void *buff, int len); + +#define _HAVE_ARCH_IPV6_CSUM +static __inline__ __sum16 +csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, + __u32 len, unsigned short proto, __wsum sum) +{ + register unsigned long tmp; + __asm__("addl %2@,%0\n\t" + "movel %2@(4),%1\n\t" + "addxl %1,%0\n\t" + "movel %2@(8),%1\n\t" + "addxl %1,%0\n\t" + "movel %2@(12),%1\n\t" + "addxl %1,%0\n\t" + "movel %3@,%1\n\t" + "addxl %1,%0\n\t" + "movel %3@(4),%1\n\t" + "addxl %1,%0\n\t" + "movel %3@(8),%1\n\t" + "addxl %1,%0\n\t" + "movel %3@(12),%1\n\t" + "addxl %1,%0\n\t" + "addxl %4,%0\n\t" + "clrl %1\n\t" + "addxl %1,%0" + : "=&d" (sum), "=&d" (tmp) + : "a" (saddr), "a" (daddr), "d" (len + proto), + "0" (sum)); + + return csum_fold(sum); +} + +#endif /* _M68K_CHECKSUM_H */ diff --git a/arch/m68knommu/include/asm/coldfire.h b/arch/m68knommu/include/asm/coldfire.h new file mode 100644 index 000000000000..83a9fa4e618a --- /dev/null +++ b/arch/m68knommu/include/asm/coldfire.h @@ -0,0 +1,51 @@ +/****************************************************************************/ + +/* + * coldfire.h -- Motorola ColdFire CPU sepecific defines + * + * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef coldfire_h +#define coldfire_h +/****************************************************************************/ + + +/* + * Define master clock frequency. This is essentially done at config + * time now. No point enumerating dozens of possible clock options + * here. Also the peripheral clock (bus clock) divide ratio is set + * at config time too. + */ +#ifdef CONFIG_CLOCK_SET +#define MCF_CLK CONFIG_CLOCK_FREQ +#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) +#else +#error "Don't know what your ColdFire CPU clock frequency is??" +#endif + +/* + * Define the processor support peripherals base address. + * This is generally setup by the boards start up code. + */ +#define MCF_MBAR 0x10000000 +#define MCF_MBAR2 0x80000000 +#if defined(CONFIG_M520x) +#define MCF_IPSBAR 0xFC000000 +#else +#define MCF_IPSBAR 0x40000000 +#endif + +#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ + defined(CONFIG_M520x) +#undef MCF_MBAR +#define MCF_MBAR MCF_IPSBAR +#elif defined(CONFIG_M532x) +#undef MCF_MBAR +#define MCF_MBAR 0x00000000 +#endif + +/****************************************************************************/ +#endif /* coldfire_h */ diff --git a/arch/m68knommu/include/asm/commproc.h b/arch/m68knommu/include/asm/commproc.h new file mode 100644 index 000000000000..edf5eb6c08d2 --- /dev/null +++ b/arch/m68knommu/include/asm/commproc.h @@ -0,0 +1,703 @@ + +/* + * 68360 Communication Processor Module. + * Copyright (c) 2000 Michael Leslie (mc68360) after: + * Copyright (c) 1997 Dan Malek (mpc8xx) + * + * This file contains structures and information for the communication + * processor channels. Some CPM control and status is available + * through the 68360 internal memory map. See include/asm/360_immap.h for details. + * This file is not a complete map of all of the 360 QUICC's capabilities + * + * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 + * bytes of the DP RAM and relocates the I2C parameter area to the + * IDMA1 space. The remaining DP RAM is available for buffer descriptors + * or other use. + */ +#ifndef __CPM_360__ +#define __CPM_360__ + + +/* CPM Command register masks: */ +#define CPM_CR_RST ((ushort)0x8000) +#define CPM_CR_OPCODE ((ushort)0x0f00) +#define CPM_CR_CHAN ((ushort)0x00f0) +#define CPM_CR_FLG ((ushort)0x0001) + +/* CPM Command set (opcodes): */ +#define CPM_CR_INIT_TRX ((ushort)0x0000) +#define CPM_CR_INIT_RX ((ushort)0x0001) +#define CPM_CR_INIT_TX ((ushort)0x0002) +#define CPM_CR_HUNT_MODE ((ushort)0x0003) +#define CPM_CR_STOP_TX ((ushort)0x0004) +#define CPM_CR_GRSTOP_TX ((ushort)0x0005) +#define CPM_CR_RESTART_TX ((ushort)0x0006) +#define CPM_CR_CLOSE_RXBD ((ushort)0x0007) +#define CPM_CR_SET_GADDR ((ushort)0x0008) +#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009) +#define CPM_CR_GCI_ABORT ((ushort)0x000a) +#define CPM_CR_RESET_BCS ((ushort)0x000a) + +/* CPM Channel numbers. */ +#define CPM_CR_CH_SCC1 ((ushort)0x0000) +#define CPM_CR_CH_SCC2 ((ushort)0x0004) +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */ +#define CPM_CR_CH_TMR ((ushort)0x0005) +#define CPM_CR_CH_SCC3 ((ushort)0x0008) +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */ +#define CPM_CR_CH_IDMA1 ((ushort)0x0009) +#define CPM_CR_CH_SCC4 ((ushort)0x000c) +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */ +#define CPM_CR_CH_IDMA2 ((ushort)0x000d) + + +#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) + +#if 1 /* mleslie: I dinna think we have any such restrictions on + * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */ + +/* The dual ported RAM is multi-functional. Some areas can be (and are + * being) used for microcode. There is an area that can only be used + * as data ram for buffer descriptors, which is all we use right now. + * Currently the first 512 and last 256 bytes are used for microcode. + */ +/* mleslie: The uCquicc board is using no extra microcode in DPRAM */ +#define CPM_DATAONLY_BASE ((uint)0x0000) +#define CPM_DATAONLY_SIZE ((uint)0x0800) +#define CPM_DP_NOSPACE ((uint)0x7fffffff) + +#endif + + +/* Export the base address of the communication processor registers + * and dual port ram. */ +/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */ +extern QUICC *pquicc; +uint m360_cpm_dpalloc(uint size); +/* void *m360_cpm_hostalloc(uint size); */ +void m360_cpm_setbrg(uint brg, uint rate); + +#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */ +/* Buffer descriptors used by many of the CPM protocols. */ +typedef struct cpm_buf_desc { + ushort cbd_sc; /* Status and Control */ + ushort cbd_datlen; /* Data length in buffer */ + uint cbd_bufaddr; /* Buffer address in host memory */ +} cbd_t; +#endif + + +/* rx bd status/control bits */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ +#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ +#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ + +#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ +#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ + +#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ +#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ + +#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ +#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */ + +#define BD_SC_BR ((ushort)0x0020) /* Break received */ +#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */ + +#define BD_SC_FR ((ushort)0x0010) /* Framing error */ +#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */ + +#define BD_SC_PR ((ushort)0x0008) /* Parity error */ +#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */ + +#define BD_SC_OV ((ushort)0x0002) /* Overrun */ +#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ + +/* tx bd status/control bits (as differ from rx bd) */ +#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ +#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ +#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ +#define BD_SC_UN ((ushort)0x0002) /* Underrun */ + + + + +/* Parameter RAM offsets. */ + + + +/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM. + * In 2.0, we use a more structured C struct map of DPRAM, and so + * instead, we need only a parameter ram `slot' */ + +#define PRSLOT_SCC1 0 +#define PRSLOT_SCC2 1 +#define PRSLOT_SCC3 2 +#define PRSLOT_SMC1 2 +#define PRSLOT_SCC4 3 +#define PRSLOT_SMC2 3 + + +/* #define PROFF_SCC1 ((uint)0x0000) */ +/* #define PROFF_SCC2 ((uint)0x0100) */ +/* #define PROFF_SCC3 ((uint)0x0200) */ +/* #define PROFF_SMC1 ((uint)0x0280) */ +/* #define PROFF_SCC4 ((uint)0x0300) */ +/* #define PROFF_SMC2 ((uint)0x0380) */ + + +/* Define enough so I can at least use the serial port as a UART. + * The MBX uses SMC1 as the host serial port. + */ +typedef struct smc_uart { + ushort smc_rbase; /* Rx Buffer descriptor base address */ + ushort smc_tbase; /* Tx Buffer descriptor base address */ + u_char smc_rfcr; /* Rx function code */ + u_char smc_tfcr; /* Tx function code */ + ushort smc_mrblr; /* Max receive buffer length */ + uint smc_rstate; /* Internal */ + uint smc_idp; /* Internal */ + ushort smc_rbptr; /* Internal */ + ushort smc_ibc; /* Internal */ + uint smc_rxtmp; /* Internal */ + uint smc_tstate; /* Internal */ + uint smc_tdp; /* Internal */ + ushort smc_tbptr; /* Internal */ + ushort smc_tbc; /* Internal */ + uint smc_txtmp; /* Internal */ + ushort smc_maxidl; /* Maximum idle characters */ + ushort smc_tmpidl; /* Temporary idle counter */ + ushort smc_brklen; /* Last received break length */ + ushort smc_brkec; /* rcv'd break condition counter */ + ushort smc_brkcr; /* xmt break count register */ + ushort smc_rmask; /* Temporary bit mask */ +} smc_uart_t; + +/* Function code bits. +*/ +#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ + +/* SMC uart mode register. +*/ +#define SMCMR_REN ((ushort)0x0001) +#define SMCMR_TEN ((ushort)0x0002) +#define SMCMR_DM ((ushort)0x000c) +#define SMCMR_SM_GCI ((ushort)0x0000) +#define SMCMR_SM_UART ((ushort)0x0020) +#define SMCMR_SM_TRANS ((ushort)0x0030) +#define SMCMR_SM_MASK ((ushort)0x0030) +#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ +#define SMCMR_REVD SMCMR_PM_EVEN +#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ +#define SMCMR_BS SMCMR_PEN +#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ +#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ +#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) + +/* SMC2 as Centronics parallel printer. It is half duplex, in that + * it can only receive or transmit. The parameter ram values for + * each direction are either unique or properly overlap, so we can + * include them in one structure. + */ +typedef struct smc_centronics { + ushort scent_rbase; + ushort scent_tbase; + u_char scent_cfcr; + u_char scent_smask; + ushort scent_mrblr; + uint scent_rstate; + uint scent_r_ptr; + ushort scent_rbptr; + ushort scent_r_cnt; + uint scent_rtemp; + uint scent_tstate; + uint scent_t_ptr; + ushort scent_tbptr; + ushort scent_t_cnt; + uint scent_ttemp; + ushort scent_max_sl; + ushort scent_sl_cnt; + ushort scent_character1; + ushort scent_character2; + ushort scent_character3; + ushort scent_character4; + ushort scent_character5; + ushort scent_character6; + ushort scent_character7; + ushort scent_character8; + ushort scent_rccm; + ushort scent_rccr; +} smc_cent_t; + +/* Centronics Status Mask Register. +*/ +#define SMC_CENT_F ((u_char)0x08) +#define SMC_CENT_PE ((u_char)0x04) +#define SMC_CENT_S ((u_char)0x02) + +/* SMC Event and Mask register. +*/ +#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ +#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ +#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ +#define SMCM_BSY ((unsigned char)0x04) +#define SMCM_TX ((unsigned char)0x02) +#define SMCM_RX ((unsigned char)0x01) + +/* Baud rate generators. +*/ +#define CPM_BRG_RST ((uint)0x00020000) +#define CPM_BRG_EN ((uint)0x00010000) +#define CPM_BRG_EXTC_INT ((uint)0x00000000) +#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) +#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) +#define CPM_BRG_ATB ((uint)0x00002000) +#define CPM_BRG_CD_MASK ((uint)0x00001ffe) +#define CPM_BRG_DIV16 ((uint)0x00000001) + +/* SCCs. +*/ +#define SCC_GSMRH_IRP ((uint)0x00040000) +#define SCC_GSMRH_GDE ((uint)0x00010000) +#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) +#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) +#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) +#define SCC_GSMRH_REVD ((uint)0x00002000) +#define SCC_GSMRH_TRX ((uint)0x00001000) +#define SCC_GSMRH_TTX ((uint)0x00000800) +#define SCC_GSMRH_CDP ((uint)0x00000400) +#define SCC_GSMRH_CTSP ((uint)0x00000200) +#define SCC_GSMRH_CDS ((uint)0x00000100) +#define SCC_GSMRH_CTSS ((uint)0x00000080) +#define SCC_GSMRH_TFL ((uint)0x00000040) +#define SCC_GSMRH_RFW ((uint)0x00000020) +#define SCC_GSMRH_TXSY ((uint)0x00000010) +#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) +#define SCC_GSMRH_SYNL8 ((uint)0x00000008) +#define SCC_GSMRH_SYNL4 ((uint)0x00000004) +#define SCC_GSMRH_RTSM ((uint)0x00000002) +#define SCC_GSMRH_RSYN ((uint)0x00000001) + +#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ +#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) +#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) +#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) +#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) +#define SCC_GSMRL_TCI ((uint)0x10000000) +#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) +#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) +#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) +#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) +#define SCC_GSMRL_RINV ((uint)0x02000000) +#define SCC_GSMRL_TINV ((uint)0x01000000) +#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) +#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) +#define SCC_GSMRL_TPL_48 ((uint)0x00800000) +#define SCC_GSMRL_TPL_32 ((uint)0x00600000) +#define SCC_GSMRL_TPL_16 ((uint)0x00400000) +#define SCC_GSMRL_TPL_8 ((uint)0x00200000) +#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) +#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) +#define SCC_GSMRL_TPP_01 ((uint)0x00100000) +#define SCC_GSMRL_TPP_10 ((uint)0x00080000) +#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) +#define SCC_GSMRL_TEND ((uint)0x00040000) +#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) +#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) +#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) +#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) +#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) +#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) +#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) +#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) +#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) +#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) +#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) +#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) +#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) +#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) +#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) +#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) +#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ +#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) +#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) +#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) +#define SCC_GSMRL_ENR ((uint)0x00000020) +#define SCC_GSMRL_ENT ((uint)0x00000010) +#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) +#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) +#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) +#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) +#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) +#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) +#define SCC_GSMRL_MODE_UART ((uint)0x00000004) +#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) +#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) +#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) + +#define SCC_TODR_TOD ((ushort)0x8000) + +/* SCC Event and Mask register. +*/ +#define SCCM_TXE ((unsigned char)0x10) +#define SCCM_BSY ((unsigned char)0x04) +#define SCCM_TX ((unsigned char)0x02) +#define SCCM_RX ((unsigned char)0x01) + +typedef struct scc_param { + ushort scc_rbase; /* Rx Buffer descriptor base address */ + ushort scc_tbase; /* Tx Buffer descriptor base address */ + u_char scc_rfcr; /* Rx function code */ + u_char scc_tfcr; /* Tx function code */ + ushort scc_mrblr; /* Max receive buffer length */ + uint scc_rstate; /* Internal */ + uint scc_idp; /* Internal */ + ushort scc_rbptr; /* Internal */ + ushort scc_ibc; /* Internal */ + uint scc_rxtmp; /* Internal */ + uint scc_tstate; /* Internal */ + uint scc_tdp; /* Internal */ + ushort scc_tbptr; /* Internal */ + ushort scc_tbc; /* Internal */ + uint scc_txtmp; /* Internal */ + uint scc_rcrc; /* Internal */ + uint scc_tcrc; /* Internal */ +} sccp_t; + + +/* Function code bits. + */ +#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ +#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */ + +/* CPM Ethernet through SCC1. + */ +typedef struct scc_enet { + sccp_t sen_genscc; + uint sen_cpres; /* Preset CRC */ + uint sen_cmask; /* Constant mask for CRC */ + uint sen_crcec; /* CRC Error counter */ + uint sen_alec; /* alignment error counter */ + uint sen_disfc; /* discard frame counter */ + ushort sen_pads; /* Tx short frame pad character */ + ushort sen_retlim; /* Retry limit threshold */ + ushort sen_retcnt; /* Retry limit counter */ + ushort sen_maxflr; /* maximum frame length register */ + ushort sen_minflr; /* minimum frame length register */ + ushort sen_maxd1; /* maximum DMA1 length */ + ushort sen_maxd2; /* maximum DMA2 length */ + ushort sen_maxd; /* Rx max DMA */ + ushort sen_dmacnt; /* Rx DMA counter */ + ushort sen_maxb; /* Max BD byte count */ + ushort sen_gaddr1; /* Group address filter */ + ushort sen_gaddr2; + ushort sen_gaddr3; + ushort sen_gaddr4; + uint sen_tbuf0data0; /* Save area 0 - current frame */ + uint sen_tbuf0data1; /* Save area 1 - current frame */ + uint sen_tbuf0rba; /* Internal */ + uint sen_tbuf0crc; /* Internal */ + ushort sen_tbuf0bcnt; /* Internal */ + ushort sen_paddrh; /* physical address (MSB) */ + ushort sen_paddrm; + ushort sen_paddrl; /* physical address (LSB) */ + ushort sen_pper; /* persistence */ + ushort sen_rfbdptr; /* Rx first BD pointer */ + ushort sen_tfbdptr; /* Tx first BD pointer */ + ushort sen_tlbdptr; /* Tx last BD pointer */ + uint sen_tbuf1data0; /* Save area 0 - current frame */ + uint sen_tbuf1data1; /* Save area 1 - current frame */ + uint sen_tbuf1rba; /* Internal */ + uint sen_tbuf1crc; /* Internal */ + ushort sen_tbuf1bcnt; /* Internal */ + ushort sen_txlen; /* Tx Frame length counter */ + ushort sen_iaddr1; /* Individual address filter */ + ushort sen_iaddr2; + ushort sen_iaddr3; + ushort sen_iaddr4; + ushort sen_boffcnt; /* Backoff counter */ + + /* NOTE: Some versions of the manual have the following items + * incorrectly documented. Below is the proper order. + */ + ushort sen_taddrh; /* temp address (MSB) */ + ushort sen_taddrm; + ushort sen_taddrl; /* temp address (LSB) */ +} scc_enet_t; + + + +#if defined (CONFIG_UCQUICC) +/* uCquicc has the following signals connected to Ethernet: + * 68360 - lxt905 + * PA0/RXD1 - rxd + * PA1/TXD1 - txd + * PA8/CLK1 - tclk + * PA9/CLK2 - rclk + * PC0/!RTS1 - t_en + * PC1/!CTS1 - col + * PC5/!CD1 - cd + */ +#define PA_ENET_RXD PA_RXD1 +#define PA_ENET_TXD PA_TXD1 +#define PA_ENET_TCLK PA_CLK1 +#define PA_ENET_RCLK PA_CLK2 +#define PC_ENET_TENA PC_RTS1 +#define PC_ENET_CLSN PC_CTS1 +#define PC_ENET_RENA PC_CD1 + +/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to + * SCC1. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000002c) + +#endif /* config_ucquicc */ + + +#ifdef MBX +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. The TCLK and RCLK seem unique + * to the MBX860 board. Any two of the four available clocks could be + * used, and the MPC860 cookbook manual has an example using different + * clock pins. + */ +#define PA_ENET_RXD ((ushort)0x0001) +#define PA_ENET_TXD ((ushort)0x0002) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PC_ENET_TENA ((ushort)0x0001) +#define PC_ENET_CLSN ((ushort)0x0010) +#define PC_ENET_RENA ((ushort)0x0020) + +/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x0000003d) +#endif + +#ifdef CONFIG_RPXLITE +/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of + * this may be unique to the RPX-Lite configuration. + * Note TENA is on Port B. + */ +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0200) +#define PA_ENET_RCLK ((ushort)0x0800) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00003d00) +#endif + +#ifdef CONFIG_BSEIP +/* This ENET stuff is for the MPC823 with ethernet on SCC2. + * This is unique to the BSE ip-Engine board. + */ +#define PA_ENET_RXD ((ushort)0x0004) +#define PA_ENET_TXD ((ushort)0x0008) +#define PA_ENET_TCLK ((ushort)0x0100) +#define PA_ENET_RCLK ((ushort)0x0200) +#define PB_ENET_TENA ((uint)0x00002000) +#define PC_ENET_CLSN ((ushort)0x0040) +#define PC_ENET_RENA ((ushort)0x0080) + +/* BSE uses port B and C bits for PHY control also. +*/ +#define PB_BSE_POWERUP ((uint)0x00000004) +#define PB_BSE_FDXDIS ((uint)0x00008000) +#define PC_BSE_LOOPBACK ((ushort)0x0800) + +#define SICR_ENET_MASK ((uint)0x0000ff00) +#define SICR_ENET_CLKRT ((uint)0x00002c00) +#endif + +/* SCC Event register as used by Ethernet. +*/ +#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ +#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ +#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ +#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ +#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ +#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ + +/* SCC Mode Register (PMSR) as used by Ethernet. +*/ +#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ +#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ +#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ +#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ +#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ +#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ +#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ +#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ +#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ +#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ +#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ +#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ +#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ + +/* Buffer descriptor control/status used by Ethernet receive. +*/ +#define BD_ENET_RX_EMPTY ((ushort)0x8000) +#define BD_ENET_RX_WRAP ((ushort)0x2000) +#define BD_ENET_RX_INTR ((ushort)0x1000) +#define BD_ENET_RX_LAST ((ushort)0x0800) +#define BD_ENET_RX_FIRST ((ushort)0x0400) +#define BD_ENET_RX_MISS ((ushort)0x0100) +#define BD_ENET_RX_LG ((ushort)0x0020) +#define BD_ENET_RX_NO ((ushort)0x0010) +#define BD_ENET_RX_SH ((ushort)0x0008) +#define BD_ENET_RX_CR ((ushort)0x0004) +#define BD_ENET_RX_OV ((ushort)0x0002) +#define BD_ENET_RX_CL ((ushort)0x0001) +#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ + +/* Buffer descriptor control/status used by Ethernet transmit. +*/ +#define BD_ENET_TX_READY ((ushort)0x8000) +#define BD_ENET_TX_PAD ((ushort)0x4000) +#define BD_ENET_TX_WRAP ((ushort)0x2000) +#define BD_ENET_TX_INTR ((ushort)0x1000) +#define BD_ENET_TX_LAST ((ushort)0x0800) +#define BD_ENET_TX_TC ((ushort)0x0400) +#define BD_ENET_TX_DEF ((ushort)0x0200) +#define BD_ENET_TX_HB ((ushort)0x0100) +#define BD_ENET_TX_LC ((ushort)0x0080) +#define BD_ENET_TX_RL ((ushort)0x0040) +#define BD_ENET_TX_RCMASK ((ushort)0x003c) +#define BD_ENET_TX_UN ((ushort)0x0002) +#define BD_ENET_TX_CSL ((ushort)0x0001) +#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ + +/* SCC as UART +*/ +typedef struct scc_uart { + sccp_t scc_genscc; + uint scc_res1; /* Reserved */ + uint scc_res2; /* Reserved */ + ushort scc_maxidl; /* Maximum idle chars */ + ushort scc_idlc; /* temp idle counter */ + ushort scc_brkcr; /* Break count register */ + ushort scc_parec; /* receive parity error counter */ + ushort scc_frmec; /* receive framing error counter */ + ushort scc_nosec; /* receive noise counter */ + ushort scc_brkec; /* receive break condition counter */ + ushort scc_brkln; /* last received break length */ + ushort scc_uaddr1; /* UART address character 1 */ + ushort scc_uaddr2; /* UART address character 2 */ + ushort scc_rtemp; /* Temp storage */ + ushort scc_toseq; /* Transmit out of sequence char */ + ushort scc_char1; /* control character 1 */ + ushort scc_char2; /* control character 2 */ + ushort scc_char3; /* control character 3 */ + ushort scc_char4; /* control character 4 */ + ushort scc_char5; /* control character 5 */ + ushort scc_char6; /* control character 6 */ + ushort scc_char7; /* control character 7 */ + ushort scc_char8; /* control character 8 */ + ushort scc_rccm; /* receive control character mask */ + ushort scc_rccr; /* receive control character register */ + ushort scc_rlbc; /* receive last break character */ +} scc_uart_t; + +/* SCC Event and Mask registers when it is used as a UART. +*/ +#define UART_SCCM_GLR ((ushort)0x1000) +#define UART_SCCM_GLT ((ushort)0x0800) +#define UART_SCCM_AB ((ushort)0x0200) +#define UART_SCCM_IDL ((ushort)0x0100) +#define UART_SCCM_GRA ((ushort)0x0080) +#define UART_SCCM_BRKE ((ushort)0x0040) +#define UART_SCCM_BRKS ((ushort)0x0020) +#define UART_SCCM_CCR ((ushort)0x0008) +#define UART_SCCM_BSY ((ushort)0x0004) +#define UART_SCCM_TX ((ushort)0x0002) +#define UART_SCCM_RX ((ushort)0x0001) + +/* The SCC PMSR when used as a UART. +*/ +#define SCU_PMSR_FLC ((ushort)0x8000) +#define SCU_PMSR_SL ((ushort)0x4000) +#define SCU_PMSR_CL ((ushort)0x3000) +#define SCU_PMSR_UM ((ushort)0x0c00) +#define SCU_PMSR_FRZ ((ushort)0x0200) +#define SCU_PMSR_RZS ((ushort)0x0100) +#define SCU_PMSR_SYN ((ushort)0x0080) +#define SCU_PMSR_DRT ((ushort)0x0040) +#define SCU_PMSR_PEN ((ushort)0x0010) +#define SCU_PMSR_RPM ((ushort)0x000c) +#define SCU_PMSR_REVP ((ushort)0x0008) +#define SCU_PMSR_TPM ((ushort)0x0003) +#define SCU_PMSR_TEVP ((ushort)0x0003) + +/* CPM Transparent mode SCC. + */ +typedef struct scc_trans { + sccp_t st_genscc; + uint st_cpres; /* Preset CRC */ + uint st_cmask; /* Constant mask for CRC */ +} scc_trans_t; + +#define BD_SCC_TX_LAST ((ushort)0x0800) + + + +/* CPM interrupts. There are nearly 32 interrupts generated by CPM + * channels or devices. All of these are presented to the PPC core + * as a single interrupt. The CPM interrupt handler dispatches its + * own handlers, in a similar fashion to the PPC core handler. We + * use the table as defined in the manuals (i.e. no special high + * priority and SCC1 == SCCa, etc...). + */ +/* #define CPMVEC_NR 32 */ +/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */ +/* #define CPMVEC_SCC1 ((ushort)0x1e) */ +/* #define CPMVEC_SCC2 ((ushort)0x1d) */ +/* #define CPMVEC_SCC3 ((ushort)0x1c) */ +/* #define CPMVEC_SCC4 ((ushort)0x1b) */ +/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */ +/* #define CPMVEC_TIMER1 ((ushort)0x19) */ +/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */ +/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */ +/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ +/* #define CPMVEC_IDMA1 ((ushort)0x15) */ +/* #define CPMVEC_IDMA2 ((ushort)0x14) */ +/* #define CPMVEC_TIMER2 ((ushort)0x12) */ +/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ +/* #define CPMVEC_I2C ((ushort)0x10) */ +/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */ +/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */ +/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ +/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */ +/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */ +/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */ +/* #define CPMVEC_TIMER4 ((ushort)0x07) */ +/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */ +/* #define CPMVEC_SPI ((ushort)0x05) */ +/* #define CPMVEC_SMC1 ((ushort)0x04) */ +/* #define CPMVEC_SMC2 ((ushort)0x03) */ +/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */ +/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */ +/* #define CPMVEC_ERROR ((ushort)0x00) */ + +extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); + +/* CPM interrupt configuration vector. +*/ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_IEN ((uint)0x00000080) /* Int. enable */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ +#endif /* __CPM_360__ */ diff --git a/arch/m68knommu/include/asm/cputime.h b/arch/m68knommu/include/asm/cputime.h new file mode 100644 index 000000000000..a0c4a660878d --- /dev/null +++ b/arch/m68knommu/include/asm/cputime.h @@ -0,0 +1,6 @@ +#ifndef __M68KNOMMU_CPUTIME_H +#define __M68KNOMMU_CPUTIME_H + +#include + +#endif /* __M68KNOMMU_CPUTIME_H */ diff --git a/arch/m68knommu/include/asm/current.h b/arch/m68knommu/include/asm/current.h new file mode 100644 index 000000000000..53ee0f9f7cef --- /dev/null +++ b/arch/m68knommu/include/asm/current.h @@ -0,0 +1,24 @@ +#ifndef _M68KNOMMU_CURRENT_H +#define _M68KNOMMU_CURRENT_H +/* + * current.h + * (C) Copyright 2000, Lineo, David McCullough + * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) + * + * rather than dedicate a register (as the m68k source does), we + * just keep a global, we should probably just change it all to be + * current and lose _current_task. + */ + +#include + +struct task_struct; + +static inline struct task_struct *get_current(void) +{ + return(current_thread_info()->task); +} + +#define current get_current() + +#endif /* _M68KNOMMU_CURRENT_H */ diff --git a/arch/m68knommu/include/asm/dbg.h b/arch/m68knommu/include/asm/dbg.h new file mode 100644 index 000000000000..27af3270f671 --- /dev/null +++ b/arch/m68knommu/include/asm/dbg.h @@ -0,0 +1,6 @@ +#define DEBUG 1 +#ifdef CONFIG_COLDFIRE +#define BREAK asm volatile ("halt") +#else +#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0 +#endif diff --git a/arch/m68knommu/include/asm/delay.h b/arch/m68knommu/include/asm/delay.h new file mode 100644 index 000000000000..55cbd6294ab6 --- /dev/null +++ b/arch/m68knommu/include/asm/delay.h @@ -0,0 +1,76 @@ +#ifndef _M68KNOMMU_DELAY_H +#define _M68KNOMMU_DELAY_H + +/* + * Copyright (C) 1994 Hamish Macdonald + * Copyright (C) 2004 Greg Ungerer + */ + +#include + +static inline void __delay(unsigned long loops) +{ +#if defined(CONFIG_COLDFIRE) + /* The coldfire runs this loop at significantly different speeds + * depending upon long word alignment or not. We'll pad it to + * long word alignment which is the faster version. + * The 0x4a8e is of course a 'tstl %fp' instruction. This is better + * than using a NOP (0x4e71) instruction because it executes in one + * cycle not three and doesn't allow for an arbitary delay waiting + * for bus cycles to finish. Also fp/a6 isn't likely to cause a + * stall waiting for the register to become valid if such is added + * to the coldfire at some stage. + */ + __asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t" + "1: subql #1, %0\n\t" + "jcc 1b" + : "=d" (loops) : "0" (loops)); +#else + __asm__ __volatile__ ( "1: subql #1, %0\n\t" + "jcc 1b" + : "=d" (loops) : "0" (loops)); +#endif +} + +/* + * Ideally we use a 32*32->64 multiply to calculate the number of + * loop iterations, but the older standard 68k and ColdFire do not + * have this instruction. So for them we have a clsoe approximation + * loop using 32*32->32 multiplies only. This calculation based on + * the ARM version of delay. + * + * We want to implement: + * + * loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32 + */ + +#define HZSCALE (268435456 / (1000000/HZ)) + +extern unsigned long loops_per_jiffy; + +static inline void _udelay(unsigned long usecs) +{ +#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \ + defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \ + defined(CONFIG_COLDFIRE) + __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6); +#else + unsigned long tmp; + + usecs *= 4295; /* 2**32 / 1000000 */ + __asm__ ("mulul %2,%0:%1" + : "=d" (usecs), "=d" (tmp) + : "d" (usecs), "1" (loops_per_jiffy*HZ)); + __delay(usecs); +#endif +} + +/* + * Moved the udelay() function into library code, no longer inlined. + * I had to change the algorithm because we are overflowing now on + * the faster ColdFire parts. The code is a little bigger, so it makes + * sense to library it. + */ +extern void udelay(unsigned long usecs); + +#endif /* defined(_M68KNOMMU_DELAY_H) */ diff --git a/arch/m68knommu/include/asm/device.h b/arch/m68knommu/include/asm/device.h new file mode 100644 index 000000000000..d8f9872b0e2d --- /dev/null +++ b/arch/m68knommu/include/asm/device.h @@ -0,0 +1,7 @@ +/* + * Arch specific extensions to struct device + * + * This file is released under the GPLv2 + */ +#include + diff --git a/arch/m68knommu/include/asm/div64.h b/arch/m68knommu/include/asm/div64.h new file mode 100644 index 000000000000..6cd978cefb28 --- /dev/null +++ b/arch/m68knommu/include/asm/div64.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/dma-mapping.h b/arch/m68knommu/include/asm/dma-mapping.h new file mode 100644 index 000000000000..6aeab18e58bd --- /dev/null +++ b/arch/m68knommu/include/asm/dma-mapping.h @@ -0,0 +1,10 @@ +#ifndef _M68KNOMMU_DMA_MAPPING_H +#define _M68KNOMMU_DMA_MAPPING_H + +#ifdef CONFIG_PCI +#include +#else +#include +#endif + +#endif /* _M68KNOMMU_DMA_MAPPING_H */ diff --git a/arch/m68knommu/include/asm/dma.h b/arch/m68knommu/include/asm/dma.h new file mode 100644 index 000000000000..939a02056217 --- /dev/null +++ b/arch/m68knommu/include/asm/dma.h @@ -0,0 +1,494 @@ +#ifndef _M68K_DMA_H +#define _M68K_DMA_H 1 + +//#define DMA_DEBUG 1 + + +#ifdef CONFIG_COLDFIRE +/* + * ColdFire DMA Model: + * ColdFire DMA supports two forms of DMA: Single and Dual address. Single + * address mode emits a source address, and expects that the device will either + * pick up the data (DMA READ) or source data (DMA WRITE). This implies that + * the device will place data on the correct byte(s) of the data bus, as the + * memory transactions are always 32 bits. This implies that only 32 bit + * devices will find single mode transfers useful. Dual address DMA mode + * performs two cycles: source read and destination write. ColdFire will + * align the data so that the device will always get the correct bytes, thus + * is useful for 8 and 16 bit devices. This is the mode that is supported + * below. + * + * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000 + * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) + * + * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000 + * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) + * + * APR/18/2002 : added proper support for MCF5272 DMA controller. + * Arthur Shipkowski (art@videon-central.com) + */ + +#include +#include +#include + +/* + * Set number of channels of DMA on ColdFire for different implementations. + */ +#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ + defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +#define MAX_M68K_DMA_CHANNELS 4 +#elif defined(CONFIG_M5272) +#define MAX_M68K_DMA_CHANNELS 1 +#elif defined(CONFIG_M532x) +#define MAX_M68K_DMA_CHANNELS 0 +#else +#define MAX_M68K_DMA_CHANNELS 2 +#endif + +extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS]; +extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; + +#if !defined(CONFIG_M5272) +#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */ +#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */ +#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */ +#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */ + +/* I/O to memory, 8 bits, mode */ +#define DMA_MODE_READ 0 +/* memory to I/O, 8 bits, mode */ +#define DMA_MODE_WRITE 1 +/* I/O to memory, 16 bits, mode */ +#define DMA_MODE_READ_WORD 2 +/* memory to I/O, 16 bits, mode */ +#define DMA_MODE_WRITE_WORD 3 +/* I/O to memory, 32 bits, mode */ +#define DMA_MODE_READ_LONG 4 +/* memory to I/O, 32 bits, mode */ +#define DMA_MODE_WRITE_LONG 5 +/* I/O to memory, 8 bits, single-address-mode */ +#define DMA_MODE_READ_SINGLE 8 +/* memory to I/O, 8 bits, single-address-mode */ +#define DMA_MODE_WRITE_SINGLE 9 +/* I/O to memory, 16 bits, single-address-mode */ +#define DMA_MODE_READ_WORD_SINGLE 10 +/* memory to I/O, 16 bits, single-address-mode */ +#define DMA_MODE_WRITE_WORD_SINGLE 11 +/* I/O to memory, 32 bits, single-address-mode */ +#define DMA_MODE_READ_LONG_SINGLE 12 +/* memory to I/O, 32 bits, single-address-mode */ +#define DMA_MODE_WRITE_LONG_SINGLE 13 + +#else /* CONFIG_M5272 is defined */ + +/* Source static-address mode */ +#define DMA_MODE_SRC_SA_BIT 0x01 +/* Two bits to select between all four modes */ +#define DMA_MODE_SSIZE_MASK 0x06 +/* Offset to shift bits in */ +#define DMA_MODE_SSIZE_OFF 0x01 +/* Destination static-address mode */ +#define DMA_MODE_DES_SA_BIT 0x10 +/* Two bits to select between all four modes */ +#define DMA_MODE_DSIZE_MASK 0x60 +/* Offset to shift bits in */ +#define DMA_MODE_DSIZE_OFF 0x05 +/* Size modifiers */ +#define DMA_MODE_SIZE_LONG 0x00 +#define DMA_MODE_SIZE_BYTE 0x01 +#define DMA_MODE_SIZE_WORD 0x02 +#define DMA_MODE_SIZE_LINE 0x03 + +/* + * Aliases to help speed quick ports; these may be suboptimal, however. They + * do not include the SINGLE mode modifiers since the MCF5272 does not have a + * mode where the device is in control of its addressing. + */ + +/* I/O to memory, 8 bits, mode */ +#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) +/* memory to I/O, 8 bits, mode */ +#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) +/* I/O to memory, 16 bits, mode */ +#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) +/* memory to I/O, 16 bits, mode */ +#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) +/* I/O to memory, 32 bits, mode */ +#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) +/* memory to I/O, 32 bits, mode */ +#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) + +#endif /* !defined(CONFIG_M5272) */ + +#if !defined(CONFIG_M5272) +/* enable/disable a specific DMA channel */ +static __inline__ void enable_dma(unsigned int dmanr) +{ + volatile unsigned short *dmawp; + +#ifdef DMA_DEBUG + printk("enable_dma(dmanr=%d)\n", dmanr); +#endif + + dmawp = (unsigned short *) dma_base_addr[dmanr]; + dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT; +} + +static __inline__ void disable_dma(unsigned int dmanr) +{ + volatile unsigned short *dmawp; + volatile unsigned char *dmapb; + +#ifdef DMA_DEBUG + printk("disable_dma(dmanr=%d)\n", dmanr); +#endif + + dmawp = (unsigned short *) dma_base_addr[dmanr]; + dmapb = (unsigned char *) dma_base_addr[dmanr]; + + /* Turn off external requests, and stop any DMA in progress */ + dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT; + dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE; +} + +/* + * Clear the 'DMA Pointer Flip Flop'. + * Write 0 for LSB/MSB, 1 for MSB/LSB access. + * Use this once to initialize the FF to a known state. + * After that, keep track of it. :-) + * --- In order to do that, the DMA routines below should --- + * --- only be used while interrupts are disabled! --- + * + * This is a NOP for ColdFire. Provide a stub for compatibility. + */ +static __inline__ void clear_dma_ff(unsigned int dmanr) +{ +} + +/* set mode (above) for a specific DMA channel */ +static __inline__ void set_dma_mode(unsigned int dmanr, char mode) +{ + + volatile unsigned char *dmabp; + volatile unsigned short *dmawp; + +#ifdef DMA_DEBUG + printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); +#endif + + dmabp = (unsigned char *) dma_base_addr[dmanr]; + dmawp = (unsigned short *) dma_base_addr[dmanr]; + + // Clear config errors + dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; + + // Set command register + dmawp[MCFDMA_DCR] = + MCFDMA_DCR_INT | // Enable completion irq + MCFDMA_DCR_CS | // Force one xfer per request + MCFDMA_DCR_AA | // Enable auto alignment + // single-address-mode + ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | + // sets s_rw (-> r/w) high if Memory to I/0 + ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | + // Memory to I/O or I/O to Memory + ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | + // 32 bit, 16 bit or 8 bit transfers + ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : + ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : + MCFDMA_DCR_SSIZE_BYTE)) | + ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD : + ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG : + MCFDMA_DCR_DSIZE_BYTE)); + +#ifdef DEBUG_DMA + printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__, + dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR], + (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]); +#endif +} + +/* Set transfer address for specific DMA channel */ +static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) +{ + volatile unsigned short *dmawp; + volatile unsigned int *dmalp; + +#ifdef DMA_DEBUG + printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); +#endif + + dmawp = (unsigned short *) dma_base_addr[dmanr]; + dmalp = (unsigned int *) dma_base_addr[dmanr]; + + // Determine which address registers are used for memory/device accesses + if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { + // Source incrementing, must be memory + dmalp[MCFDMA_SAR] = a; + // Set dest address, must be device + dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; + } else { + // Destination incrementing, must be memory + dmalp[MCFDMA_DAR] = a; + // Set source address, must be device + dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; + } + +#ifdef DEBUG_DMA + printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", + __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR], + (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR], + (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]); +#endif +} + +/* + * Specific for Coldfire - sets device address. + * Should be called after the mode set call, and before set DMA address. + */ +static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) +{ +#ifdef DMA_DEBUG + printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); +#endif + + dma_device_address[dmanr] = a; +} + +/* + * NOTE 2: "count" represents _bytes_. + */ +static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) +{ + volatile unsigned short *dmawp; + +#ifdef DMA_DEBUG + printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); +#endif + + dmawp = (unsigned short *) dma_base_addr[dmanr]; + dmawp[MCFDMA_BCR] = (unsigned short)count; +} + +/* + * Get DMA residue count. After a DMA transfer, this + * should return zero. Reading this while a DMA transfer is + * still in progress will return unpredictable results. + * Otherwise, it returns the number of _bytes_ left to transfer. + */ +static __inline__ int get_dma_residue(unsigned int dmanr) +{ + volatile unsigned short *dmawp; + unsigned short count; + +#ifdef DMA_DEBUG + printk("get_dma_residue(dmanr=%d)\n", dmanr); +#endif + + dmawp = (unsigned short *) dma_base_addr[dmanr]; + count = dmawp[MCFDMA_BCR]; + return((int) count); +} +#else /* CONFIG_M5272 is defined */ + +/* + * The MCF5272 DMA controller is very different than the controller defined above + * in terms of register mapping. For instance, with the exception of the 16-bit + * interrupt register (IRQ#85, for reference), all of the registers are 32-bit. + * + * The big difference, however, is the lack of device-requested DMA. All modes + * are dual address transfer, and there is no 'device' setup or direction bit. + * You can DMA between a device and memory, between memory and memory, or even between + * two devices directly, with any combination of incrementing and non-incrementing + * addresses you choose. This puts a crimp in distinguishing between the 'device + * address' set up by set_dma_device_addr. + * + * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr, + * which will act exactly as above in -- it will look to see if the source is set to + * autoincrement, and if so it will make the source use the set_dma_addr value and the + * destination the set_dma_device_addr value. Otherwise the source will be set to the + * set_dma_device_addr value and the destination will get the set_dma_addr value. + * + * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions + * and make it explicit. Depending on what you're doing, one of these two should work + * for you, but don't mix them in the same transfer setup. + */ + +/* enable/disable a specific DMA channel */ +static __inline__ void enable_dma(unsigned int dmanr) +{ + volatile unsigned int *dmalp; + +#ifdef DMA_DEBUG + printk("enable_dma(dmanr=%d)\n", dmanr); +#endif + + dmalp = (unsigned int *) dma_base_addr[dmanr]; + dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN; +} + +static __inline__ void disable_dma(unsigned int dmanr) +{ + volatile unsigned int *dmalp; + +#ifdef DMA_DEBUG + printk("disable_dma(dmanr=%d)\n", dmanr); +#endif + + dmalp = (unsigned int *) dma_base_addr[dmanr]; + + /* Turn off external requests, and stop any DMA in progress */ + dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN; + dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; +} + +/* + * Clear the 'DMA Pointer Flip Flop'. + * Write 0 for LSB/MSB, 1 for MSB/LSB access. + * Use this once to initialize the FF to a known state. + * After that, keep track of it. :-) + * --- In order to do that, the DMA routines below should --- + * --- only be used while interrupts are disabled! --- + * + * This is a NOP for ColdFire. Provide a stub for compatibility. + */ +static __inline__ void clear_dma_ff(unsigned int dmanr) +{ +} + +/* set mode (above) for a specific DMA channel */ +static __inline__ void set_dma_mode(unsigned int dmanr, char mode) +{ + + volatile unsigned int *dmalp; + volatile unsigned short *dmawp; + +#ifdef DMA_DEBUG + printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); +#endif + dmalp = (unsigned int *) dma_base_addr[dmanr]; + dmawp = (unsigned short *) dma_base_addr[dmanr]; + + // Clear config errors + dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; + + // Set command register + dmalp[MCFDMA_DMR] = + MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting + MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data. + MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data. + // source static-address-mode + ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | + // dest static-address-mode + ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | + // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 + (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | + (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); + + dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */ + +#ifdef DEBUG_DMA + printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__, + dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR], + (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]); +#endif +} + +/* Set transfer address for specific DMA channel */ +static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) +{ + volatile unsigned int *dmalp; + +#ifdef DMA_DEBUG + printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); +#endif + + dmalp = (unsigned int *) dma_base_addr[dmanr]; + + // Determine which address registers are used for memory/device accesses + if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { + // Source incrementing, must be memory + dmalp[MCFDMA_DSAR] = a; + // Set dest address, must be device + dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; + } else { + // Destination incrementing, must be memory + dmalp[MCFDMA_DDAR] = a; + // Set source address, must be device + dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; + } + +#ifdef DEBUG_DMA + printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", + __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR], + (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR], + (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]); +#endif +} + +/* + * Specific for Coldfire - sets device address. + * Should be called after the mode set call, and before set DMA address. + */ +static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) +{ +#ifdef DMA_DEBUG + printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); +#endif + + dma_device_address[dmanr] = a; +} + +/* + * NOTE 2: "count" represents _bytes_. + * + * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value. + */ +static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) +{ + volatile unsigned int *dmalp; + +#ifdef DMA_DEBUG + printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); +#endif + + dmalp = (unsigned int *) dma_base_addr[dmanr]; + dmalp[MCFDMA_DBCR] = count; +} + +/* + * Get DMA residue count. After a DMA transfer, this + * should return zero. Reading this while a DMA transfer is + * still in progress will return unpredictable results. + * Otherwise, it returns the number of _bytes_ left to transfer. + */ +static __inline__ int get_dma_residue(unsigned int dmanr) +{ + volatile unsigned int *dmalp; + unsigned int count; + +#ifdef DMA_DEBUG + printk("get_dma_residue(dmanr=%d)\n", dmanr); +#endif + + dmalp = (unsigned int *) dma_base_addr[dmanr]; + count = dmalp[MCFDMA_DBCR]; + return(count); +} + +#endif /* !defined(CONFIG_M5272) */ +#endif /* CONFIG_COLDFIRE */ + +#define MAX_DMA_CHANNELS 8 + +/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any + occurrence should be flagged as an error. */ +/* under 2.4 it is actually needed by the new bootmem allocator */ +#define MAX_DMA_ADDRESS PAGE_OFFSET + +/* These are in kernel/dma.c: */ +extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */ +extern void free_dma(unsigned int dmanr); /* release it again */ + +#endif /* _M68K_DMA_H */ diff --git a/arch/m68knommu/include/asm/elf.h b/arch/m68knommu/include/asm/elf.h new file mode 100644 index 000000000000..27f0ec70fba8 --- /dev/null +++ b/arch/m68knommu/include/asm/elf.h @@ -0,0 +1,110 @@ +#ifndef __ASMm68k_ELF_H +#define __ASMm68k_ELF_H + +/* + * ELF register definitions.. + */ + +#include +#include + +/* + * 68k ELF relocation types + */ +#define R_68K_NONE 0 +#define R_68K_32 1 +#define R_68K_16 2 +#define R_68K_8 3 +#define R_68K_PC32 4 +#define R_68K_PC16 5 +#define R_68K_PC8 6 +#define R_68K_GOT32 7 +#define R_68K_GOT16 8 +#define R_68K_GOT8 9 +#define R_68K_GOT32O 10 +#define R_68K_GOT16O 11 +#define R_68K_GOT8O 12 +#define R_68K_PLT32 13 +#define R_68K_PLT16 14 +#define R_68K_PLT8 15 +#define R_68K_PLT32O 16 +#define R_68K_PLT16O 17 +#define R_68K_PLT8O 18 +#define R_68K_COPY 19 +#define R_68K_GLOB_DAT 20 +#define R_68K_JMP_SLOT 21 +#define R_68K_RELATIVE 22 + +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct user_m68kfp_struct elf_fpregset_t; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ((x)->e_machine == EM_68K) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#define ELF_DATA ELFDATA2MSB +#define ELF_ARCH EM_68K + +/* For SVR4/m68k the function pointer to be registered with `atexit' is + passed in %a1. Although my copy of the ABI has no such statement, it + is actually used on ASV. */ +#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE 0xD0000000UL + +#define ELF_CORE_COPY_REGS(pr_reg, regs) \ + /* Bleech. */ \ + pr_reg[0] = regs->d1; \ + pr_reg[1] = regs->d2; \ + pr_reg[2] = regs->d3; \ + pr_reg[3] = regs->d4; \ + pr_reg[4] = regs->d5; \ + pr_reg[7] = regs->a0; \ + pr_reg[8] = regs->a1; \ + pr_reg[14] = regs->d0; \ + pr_reg[15] = rdusp(); \ + pr_reg[16] = 0 /* regs->orig_d0 */; \ + pr_reg[17] = regs->sr; \ + pr_reg[18] = regs->pc; \ + /* pr_reg[19] = (regs->format << 12) | regs->vector; */ \ + { \ + struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ + pr_reg[5] = sw->d6; \ + pr_reg[6] = sw->d7; \ + pr_reg[10] = sw->a3; \ + pr_reg[11] = sw->a4; \ + pr_reg[12] = sw->a5; \ + pr_reg[13] = sw->a6; \ + } + +/* This yields a mask that user programs can use to figure out what + instruction set this cpu supports. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. */ + +#define ELF_PLATFORM (NULL) + +#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) + +#endif diff --git a/arch/m68knommu/include/asm/elia.h b/arch/m68knommu/include/asm/elia.h new file mode 100644 index 000000000000..e037d4e2de33 --- /dev/null +++ b/arch/m68knommu/include/asm/elia.h @@ -0,0 +1,41 @@ +/****************************************************************************/ + +/* + * elia.h -- Lineo (formerly Moreton Bay) eLIA platform support. + * + * (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au) + * (C) Copyright 1999-2000, Lineo (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef elia_h +#define elia_h +/****************************************************************************/ + +#include + +#ifdef CONFIG_eLIA + +/* + * The serial port DTR and DCD lines are also on the Parallel I/O + * as well, so define those too. + */ + +#define eLIA_DCD1 0x0001 +#define eLIA_DCD0 0x0002 +#define eLIA_DTR1 0x0004 +#define eLIA_DTR0 0x0008 + +#define eLIA_PCIRESET 0x0020 + +/* + * Kernel macros to set and unset the LEDs. + */ +#ifndef __ASSEMBLY__ +extern unsigned short ppdata; +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_eLIA */ + +/****************************************************************************/ +#endif /* elia_h */ diff --git a/arch/m68knommu/include/asm/emergency-restart.h b/arch/m68knommu/include/asm/emergency-restart.h new file mode 100644 index 000000000000..108d8c48e42e --- /dev/null +++ b/arch/m68knommu/include/asm/emergency-restart.h @@ -0,0 +1,6 @@ +#ifndef _ASM_EMERGENCY_RESTART_H +#define _ASM_EMERGENCY_RESTART_H + +#include + +#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/arch/m68knommu/include/asm/entry.h b/arch/m68knommu/include/asm/entry.h new file mode 100644 index 000000000000..c2553d26273d --- /dev/null +++ b/arch/m68knommu/include/asm/entry.h @@ -0,0 +1,182 @@ +#ifndef __M68KNOMMU_ENTRY_H +#define __M68KNOMMU_ENTRY_H + +#include +#include + +/* + * Stack layout in 'ret_from_exception': + * + * This allows access to the syscall arguments in registers d1-d5 + * + * 0(sp) - d1 + * 4(sp) - d2 + * 8(sp) - d3 + * C(sp) - d4 + * 10(sp) - d5 + * 14(sp) - a0 + * 18(sp) - a1 + * 1C(sp) - a2 + * 20(sp) - d0 + * 24(sp) - orig_d0 + * 28(sp) - stack adjustment + * 2C(sp) - [ sr ] [ format & vector ] + * 2E(sp) - [ pc-hiword ] [ sr ] + * 30(sp) - [ pc-loword ] [ pc-hiword ] + * 32(sp) - [ format & vector ] [ pc-loword ] + * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^ + * M68K COLDFIRE + */ + +#define ALLOWINT 0xf8ff + +#ifdef __ASSEMBLY__ + +/* process bits for task_struct.flags */ +PF_TRACESYS_OFF = 3 +PF_TRACESYS_BIT = 5 +PF_PTRACED_OFF = 3 +PF_PTRACED_BIT = 4 +PF_DTRACE_OFF = 1 +PF_DTRACE_BIT = 5 + +LENOSYS = 38 + +#define SWITCH_STACK_SIZE (6*4+4) /* Includes return address */ + +/* + * This defines the normal kernel pt-regs layout. + * + * regs are a2-a6 and d6-d7 preserved by C code + * the kernel doesn't mess with usp unless it needs to + */ + +#ifdef CONFIG_COLDFIRE +/* + * This is made a little more tricky on the ColdFire. There is no + * separate kernel and user stack pointers. Need to artificially + * construct a usp in software... When doing this we need to disable + * interrupts, otherwise bad things could happen. + */ +.macro SAVE_ALL + move #0x2700,%sr /* disable intrs */ + btst #5,%sp@(2) /* from user? */ + bnes 6f /* no, skip */ + movel %sp,sw_usp /* save user sp */ + addql #8,sw_usp /* remove exception */ + movel sw_ksp,%sp /* kernel sp */ + subql #8,%sp /* room for exception */ + clrl %sp@- /* stkadj */ + movel %d0,%sp@- /* orig d0 */ + movel %d0,%sp@- /* d0 */ + lea %sp@(-32),%sp /* space for 8 regs */ + moveml %d1-%d5/%a0-%a2,%sp@ + movel sw_usp,%a0 /* get usp */ + movel %a0@-,%sp@(PT_PC) /* copy exception program counter */ + movel %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */ + bra 7f + 6: + clrl %sp@- /* stkadj */ + movel %d0,%sp@- /* orig d0 */ + movel %d0,%sp@- /* d0 */ + lea %sp@(-32),%sp /* space for 8 regs */ + moveml %d1-%d5/%a0-%a2,%sp@ + 7: +.endm + +.macro RESTORE_ALL + btst #5,%sp@(PT_SR) /* going user? */ + bnes 8f /* no, skip */ + move #0x2700,%sr /* disable intrs */ + movel sw_usp,%a0 /* get usp */ + movel %sp@(PT_PC),%a0@- /* copy exception program counter */ + movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */ + moveml %sp@,%d1-%d5/%a0-%a2 + lea %sp@(32),%sp /* space for 8 regs */ + movel %sp@+,%d0 + addql #4,%sp /* orig d0 */ + addl %sp@+,%sp /* stkadj */ + addql #8,%sp /* remove exception */ + movel %sp,sw_ksp /* save ksp */ + subql #8,sw_usp /* set exception */ + movel sw_usp,%sp /* restore usp */ + rte + 8: + moveml %sp@,%d1-%d5/%a0-%a2 + lea %sp@(32),%sp /* space for 8 regs */ + movel %sp@+,%d0 + addql #4,%sp /* orig d0 */ + addl %sp@+,%sp /* stkadj */ + rte +.endm + +/* + * Quick exception save, use current stack only. + */ +.macro SAVE_LOCAL + move #0x2700,%sr /* disable intrs */ + clrl %sp@- /* stkadj */ + movel %d0,%sp@- /* orig d0 */ + movel %d0,%sp@- /* d0 */ + lea %sp@(-32),%sp /* space for 8 regs */ + moveml %d1-%d5/%a0-%a2,%sp@ +.endm + +.macro RESTORE_LOCAL + moveml %sp@,%d1-%d5/%a0-%a2 + lea %sp@(32),%sp /* space for 8 regs */ + movel %sp@+,%d0 + addql #4,%sp /* orig d0 */ + addl %sp@+,%sp /* stkadj */ + rte +.endm + +.macro SAVE_SWITCH_STACK + lea %sp@(-24),%sp /* 6 regs */ + moveml %a3-%a6/%d6-%d7,%sp@ +.endm + +.macro RESTORE_SWITCH_STACK + moveml %sp@,%a3-%a6/%d6-%d7 + lea %sp@(24),%sp /* 6 regs */ +.endm + +/* + * Software copy of the user and kernel stack pointers... Ugh... + * Need these to get around ColdFire not having separate kernel + * and user stack pointers. + */ +.globl sw_usp +.globl sw_ksp + +#else /* !CONFIG_COLDFIRE */ + +/* + * Standard 68k interrupt entry and exit macros. + */ +.macro SAVE_ALL + clrl %sp@- /* stkadj */ + movel %d0,%sp@- /* orig d0 */ + movel %d0,%sp@- /* d0 */ + moveml %d1-%d5/%a0-%a2,%sp@- +.endm + +.macro RESTORE_ALL + moveml %sp@+,%a0-%a2/%d1-%d5 + movel %sp@+,%d0 + addql #4,%sp /* orig d0 */ + addl %sp@+,%sp /* stkadj */ + rte +.endm + +.macro SAVE_SWITCH_STACK + moveml %a3-%a6/%d6-%d7,%sp@- +.endm + +.macro RESTORE_SWITCH_STACK + moveml %sp@+,%a3-%a6/%d6-%d7 +.endm + +#endif /* !CONFIG_COLDFIRE */ +#endif /* __ASSEMBLY__ */ +#endif /* __M68KNOMMU_ENTRY_H */ diff --git a/arch/m68knommu/include/asm/errno.h b/arch/m68knommu/include/asm/errno.h new file mode 100644 index 000000000000..7e8c22b9a5e6 --- /dev/null +++ b/arch/m68knommu/include/asm/errno.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/fb.h b/arch/m68knommu/include/asm/fb.h new file mode 100644 index 000000000000..c7df38030992 --- /dev/null +++ b/arch/m68knommu/include/asm/fb.h @@ -0,0 +1,12 @@ +#ifndef _ASM_FB_H_ +#define _ASM_FB_H_ +#include + +#define fb_pgprotect(...) do {} while (0) + +static inline int fb_is_primary_device(struct fb_info *info) +{ + return 0; +} + +#endif /* _ASM_FB_H_ */ diff --git a/arch/m68knommu/include/asm/fcntl.h b/arch/m68knommu/include/asm/fcntl.h new file mode 100644 index 000000000000..f6a552cda4cd --- /dev/null +++ b/arch/m68knommu/include/asm/fcntl.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/flat.h b/arch/m68knommu/include/asm/flat.h new file mode 100644 index 000000000000..814b5174a8e0 --- /dev/null +++ b/arch/m68knommu/include/asm/flat.h @@ -0,0 +1,17 @@ +/* + * include/asm-m68knommu/flat.h -- uClinux flat-format executables + */ + +#ifndef __M68KNOMMU_FLAT_H__ +#define __M68KNOMMU_FLAT_H__ + +#define flat_stack_align(sp) /* nothing needed */ +#define flat_argvp_envp_on_stack() 1 +#define flat_old_ram_flag(flags) (flags) +#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) +#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) +#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) +#define flat_get_relocate_addr(rel) (rel) +#define flat_set_persistent(relval, p) 0 + +#endif /* __M68KNOMMU_FLAT_H__ */ diff --git a/arch/m68knommu/include/asm/fpu.h b/arch/m68knommu/include/asm/fpu.h new file mode 100644 index 000000000000..b16b2e4fca2a --- /dev/null +++ b/arch/m68knommu/include/asm/fpu.h @@ -0,0 +1,21 @@ +#ifndef __M68KNOMMU_FPU_H +#define __M68KNOMMU_FPU_H + + +/* + * MAX floating point unit state size (FSAVE/FRESTORE) + */ +#if defined(CONFIG_M68020) || defined(CONFIG_M68030) +#define FPSTATESIZE (216/sizeof(unsigned char)) +#elif defined(CONFIG_M68040) +#define FPSTATESIZE (96/sizeof(unsigned char)) +#elif defined(CONFIG_M68KFPU_EMU) +#define FPSTATESIZE (28/sizeof(unsigned char)) +#elif defined(CONFIG_M68060) +#define FPSTATESIZE (12/sizeof(unsigned char)) +#else +/* Assume no FP unit present then... */ +#define FPSTATESIZE (2) /* dummy size */ +#endif + +#endif /* __M68K_FPU_H */ diff --git a/arch/m68knommu/include/asm/futex.h b/arch/m68knommu/include/asm/futex.h new file mode 100644 index 000000000000..6a332a9f099c --- /dev/null +++ b/arch/m68knommu/include/asm/futex.h @@ -0,0 +1,6 @@ +#ifndef _ASM_FUTEX_H +#define _ASM_FUTEX_H + +#include + +#endif diff --git a/arch/m68knommu/include/asm/hardirq.h b/arch/m68knommu/include/asm/hardirq.h new file mode 100644 index 000000000000..bfad28149a49 --- /dev/null +++ b/arch/m68knommu/include/asm/hardirq.h @@ -0,0 +1,27 @@ +#ifndef __M68K_HARDIRQ_H +#define __M68K_HARDIRQ_H + +#include +#include +#include + +typedef struct { + unsigned int __softirq_pending; +} ____cacheline_aligned irq_cpustat_t; + +#include /* Standard mappings for irq_cpustat_t above */ + +#define HARDIRQ_BITS 8 + +/* + * The hardirq mask has to be large enough to have + * space for potentially all IRQ sources in the system + * nesting on a single CPU: + */ +#if (1 << HARDIRQ_BITS) < NR_IRQS +# error HARDIRQ_BITS is too low! +#endif + +void ack_bad_irq(unsigned int irq); + +#endif /* __M68K_HARDIRQ_H */ diff --git a/arch/m68knommu/include/asm/hw_irq.h b/arch/m68knommu/include/asm/hw_irq.h new file mode 100644 index 000000000000..f3ec9e5ae049 --- /dev/null +++ b/arch/m68knommu/include/asm/hw_irq.h @@ -0,0 +1,4 @@ +#ifndef __M68KNOMMU_HW_IRQ_H__ +#define __M68KNOMMU_HW_IRQ_H__ + +#endif /* __M68KNOMMU_HW_IRQ_H__ */ diff --git a/arch/m68knommu/include/asm/hwtest.h b/arch/m68knommu/include/asm/hwtest.h new file mode 100644 index 000000000000..700626a1b1bf --- /dev/null +++ b/arch/m68knommu/include/asm/hwtest.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/io.h b/arch/m68knommu/include/asm/io.h new file mode 100644 index 000000000000..6adef1ee2082 --- /dev/null +++ b/arch/m68knommu/include/asm/io.h @@ -0,0 +1,194 @@ +#ifndef _M68KNOMMU_IO_H +#define _M68KNOMMU_IO_H + +#ifdef __KERNEL__ + + +/* + * These are for ISA/PCI shared memory _only_ and should never be used + * on any other type of memory, including Zorro memory. They are meant to + * access the bus in the bus byte order which is little-endian!. + * + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the m68k architecture, we just read/write the + * memory location directly. + */ +/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates + * two accesses to memory, which may be undesireable for some devices. + */ + +/* + * swap functions are sometimes needed to interface little-endian hardware + */ +static inline unsigned short _swapw(volatile unsigned short v) +{ + return ((v << 8) | (v >> 8)); +} + +static inline unsigned int _swapl(volatile unsigned long v) +{ + return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24)); +} + +#define readb(addr) \ + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) +#define readw(addr) \ + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) +#define readl(addr) \ + ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) + +#define readb_relaxed(addr) readb(addr) +#define readw_relaxed(addr) readw(addr) +#define readl_relaxed(addr) readl(addr) + +#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) +#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) +#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) + +#define __raw_readb readb +#define __raw_readw readw +#define __raw_readl readl +#define __raw_writeb writeb +#define __raw_writew writew +#define __raw_writel writel + +static inline void io_outsb(unsigned int addr, void *buf, int len) +{ + volatile unsigned char *ap = (volatile unsigned char *) addr; + unsigned char *bp = (unsigned char *) buf; + while (len--) + *ap = *bp++; +} + +static inline void io_outsw(unsigned int addr, void *buf, int len) +{ + volatile unsigned short *ap = (volatile unsigned short *) addr; + unsigned short *bp = (unsigned short *) buf; + while (len--) + *ap = _swapw(*bp++); +} + +static inline void io_outsl(unsigned int addr, void *buf, int len) +{ + volatile unsigned int *ap = (volatile unsigned int *) addr; + unsigned int *bp = (unsigned int *) buf; + while (len--) + *ap = _swapl(*bp++); +} + +static inline void io_insb(unsigned int addr, void *buf, int len) +{ + volatile unsigned char *ap = (volatile unsigned char *) addr; + unsigned char *bp = (unsigned char *) buf; + while (len--) + *bp++ = *ap; +} + +static inline void io_insw(unsigned int addr, void *buf, int len) +{ + volatile unsigned short *ap = (volatile unsigned short *) addr; + unsigned short *bp = (unsigned short *) buf; + while (len--) + *bp++ = _swapw(*ap); +} + +static inline void io_insl(unsigned int addr, void *buf, int len) +{ + volatile unsigned int *ap = (volatile unsigned int *) addr; + unsigned int *bp = (unsigned int *) buf; + while (len--) + *bp++ = _swapl(*ap); +} + +#define mmiowb() + +/* + * make the short names macros so specific devices + * can override them as required + */ + +#define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) +#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) + +#define inb(addr) readb(addr) +#define inw(addr) readw(addr) +#define inl(addr) readl(addr) +#define outb(x,addr) ((void) writeb(x,addr)) +#define outw(x,addr) ((void) writew(x,addr)) +#define outl(x,addr) ((void) writel(x,addr)) + +#define inb_p(addr) inb(addr) +#define inw_p(addr) inw(addr) +#define inl_p(addr) inl(addr) +#define outb_p(x,addr) outb(x,addr) +#define outw_p(x,addr) outw(x,addr) +#define outl_p(x,addr) outl(x,addr) + +#define outsb(a,b,l) io_outsb(a,b,l) +#define outsw(a,b,l) io_outsw(a,b,l) +#define outsl(a,b,l) io_outsl(a,b,l) + +#define insb(a,b,l) io_insb(a,b,l) +#define insw(a,b,l) io_insw(a,b,l) +#define insl(a,b,l) io_insl(a,b,l) + +#define IO_SPACE_LIMIT 0xffff + + +/* Values for nocacheflag and cmode */ +#define IOMAP_FULL_CACHING 0 +#define IOMAP_NOCACHE_SER 1 +#define IOMAP_NOCACHE_NONSER 2 +#define IOMAP_WRITETHROUGH 3 + +extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); +extern void __iounmap(void *addr, unsigned long size); + +static inline void *ioremap(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); +} +static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); +} +static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) +{ + return __ioremap(physaddr, size, IOMAP_FULL_CACHING); +} + +extern void iounmap(void *addr); + +/* Pages to physical address... */ +#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) +#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) + +/* + * Macros used for converting between virtual and physical mappings. + */ +#define phys_to_virt(vaddr) ((void *) (vaddr)) +#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#endif /* __KERNEL__ */ + +#endif /* _M68KNOMMU_IO_H */ diff --git a/arch/m68knommu/include/asm/ioctl.h b/arch/m68knommu/include/asm/ioctl.h new file mode 100644 index 000000000000..b279fe06dfe5 --- /dev/null +++ b/arch/m68knommu/include/asm/ioctl.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/ioctls.h b/arch/m68knommu/include/asm/ioctls.h new file mode 100644 index 000000000000..0b1eb4d85059 --- /dev/null +++ b/arch/m68knommu/include/asm/ioctls.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/ipcbuf.h b/arch/m68knommu/include/asm/ipcbuf.h new file mode 100644 index 000000000000..e4a7be6dd706 --- /dev/null +++ b/arch/m68knommu/include/asm/ipcbuf.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/irq.h b/arch/m68knommu/include/asm/irq.h new file mode 100644 index 000000000000..9373c31ac87d --- /dev/null +++ b/arch/m68knommu/include/asm/irq.h @@ -0,0 +1,26 @@ +#ifndef _M68KNOMMU_IRQ_H_ +#define _M68KNOMMU_IRQ_H_ + +#ifdef CONFIG_COLDFIRE +/* + * On the ColdFire we keep track of all vectors. That way drivers + * can register whatever vector number they wish, and we can deal + * with it. + */ +#define SYS_IRQS 256 +#define NR_IRQS SYS_IRQS + +#else + +/* + * # of m68k interrupts + */ +#define SYS_IRQS 8 +#define NR_IRQS (24 + SYS_IRQS) + +#endif /* CONFIG_COLDFIRE */ + + +#define irq_canonicalize(irq) (irq) + +#endif /* _M68KNOMMU_IRQ_H_ */ diff --git a/arch/m68knommu/include/asm/irq_regs.h b/arch/m68knommu/include/asm/irq_regs.h new file mode 100644 index 000000000000..3dd9c0b70270 --- /dev/null +++ b/arch/m68knommu/include/asm/irq_regs.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/kdebug.h b/arch/m68knommu/include/asm/kdebug.h new file mode 100644 index 000000000000..6ece1b037665 --- /dev/null +++ b/arch/m68knommu/include/asm/kdebug.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/kmap_types.h b/arch/m68knommu/include/asm/kmap_types.h new file mode 100644 index 000000000000..bfb6707575d1 --- /dev/null +++ b/arch/m68knommu/include/asm/kmap_types.h @@ -0,0 +1,21 @@ +#ifndef __ASM_M68K_KMAP_TYPES_H +#define __ASM_M68K_KMAP_TYPES_H + +enum km_type { + KM_BOUNCE_READ, + KM_SKB_SUNRPC_DATA, + KM_SKB_DATA_SOFTIRQ, + KM_USER0, + KM_USER1, + KM_BIO_SRC_IRQ, + KM_BIO_DST_IRQ, + KM_PTE0, + KM_PTE1, + KM_IRQ0, + KM_IRQ1, + KM_SOFTIRQ0, + KM_SOFTIRQ1, + KM_TYPE_NR +}; + +#endif diff --git a/arch/m68knommu/include/asm/linkage.h b/arch/m68knommu/include/asm/linkage.h new file mode 100644 index 000000000000..c288a19ff489 --- /dev/null +++ b/arch/m68knommu/include/asm/linkage.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/local.h b/arch/m68knommu/include/asm/local.h new file mode 100644 index 000000000000..84a39c1b86f8 --- /dev/null +++ b/arch/m68knommu/include/asm/local.h @@ -0,0 +1,6 @@ +#ifndef __M68KNOMMU_LOCAL_H +#define __M68KNOMMU_LOCAL_H + +#include + +#endif /* __M68KNOMMU_LOCAL_H */ diff --git a/arch/m68knommu/include/asm/m5206sim.h b/arch/m68knommu/include/asm/m5206sim.h new file mode 100644 index 000000000000..7e3594dea88b --- /dev/null +++ b/arch/m68knommu/include/asm/m5206sim.h @@ -0,0 +1,131 @@ +/****************************************************************************/ + +/* + * m5206sim.h -- ColdFire 5206 System Integration Module support. + * + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef m5206sim_h +#define m5206sim_h +/****************************************************************************/ + + +/* + * Define the 5206 SIM register set addresses. + */ +#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ +#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ +#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ +#ifdef CONFIG_M5206e +#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ +#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ +#endif + +#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ + +#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ + +#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ + +#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ +#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ +#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ + +#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ +#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ +#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ +#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ +#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ +#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ +#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ +#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ +#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ +#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ +#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ +#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ +#define MCFSIM_DMCR 0xc6 /* Default control */ + +#ifdef CONFIG_M5206e +#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ +#else +#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ +#endif + +#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */ +#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */ + +/* + * Some symbol defines for the Parallel Port Pin Assignment Register + */ +#ifdef CONFIG_M5206e +#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */ + /* Clear to select T0 input */ +#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */ + /* Clear to select T0 output */ +#endif + +/* + * Some symbol defines for the Interrupt Control Register + */ +#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ +#ifdef CONFIG_M5206e +#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */ +#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ +#endif + +#if defined(CONFIG_M5206e) +#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */ +#endif + +/* + * Macro to get and set IMR register. It is 16 bits on the 5206. + */ +#define mcf_getimr() \ + *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr) + +#define mcf_getipr() \ + *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR)) + +/****************************************************************************/ +#endif /* m5206sim_h */ diff --git a/arch/m68knommu/include/asm/m520xsim.h b/arch/m68knommu/include/asm/m520xsim.h new file mode 100644 index 000000000000..49d016e6391a --- /dev/null +++ b/arch/m68knommu/include/asm/m520xsim.h @@ -0,0 +1,63 @@ +/****************************************************************************/ + +/* + * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. + * + * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) + */ + +/****************************************************************************/ +#ifndef m520xsim_h +#define m520xsim_h +/****************************************************************************/ + + +/* + * Define the 5282 SIM register set addresses. + */ +#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 +#define MCFINT_UART0 26 /* Interrupt number for UART0 */ +#define MCFINT_UART1 27 /* Interrupt number for UART1 */ +#define MCFINT_UART2 28 /* Interrupt number for UART2 */ +#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ +#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ + +/* + * SDRAM configuration registers. + */ +#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ +#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ +#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ +#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ +#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ +#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ + + +#define MCF_GPIO_PAR_UART (0xA4036) +#define MCF_GPIO_PAR_FECI2C (0xA4033) +#define MCF_GPIO_PAR_FEC (0xA4038) + +#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) +#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) + +#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) +#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) + +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) + +#define ICR_INTRCONF 0x05 +#define MCFPIT_IMR MCFINTC_IMRL +#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) + +/****************************************************************************/ +#endif /* m520xsim_h */ diff --git a/arch/m68knommu/include/asm/m523xsim.h b/arch/m68knommu/include/asm/m523xsim.h new file mode 100644 index 000000000000..bf397313e93f --- /dev/null +++ b/arch/m68knommu/include/asm/m523xsim.h @@ -0,0 +1,45 @@ +/****************************************************************************/ + +/* + * m523xsim.h -- ColdFire 523x System Integration Module support. + * + * (C) Copyright 2003-2005, Greg Ungerer + */ + +/****************************************************************************/ +#ifndef m523xsim_h +#define m523xsim_h +/****************************************************************************/ + + +/* + * Define the 523x SIM register set addresses. + */ +#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 /* Vector base number */ +#define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ +#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ + +/* + * SDRAM configuration registers. + */ +#define MCFSIM_DCR 0x44 /* SDRAM control */ +#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ +#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ +#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ +#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ + +/****************************************************************************/ +#endif /* m523xsim_h */ diff --git a/arch/m68knommu/include/asm/m5249sim.h b/arch/m68knommu/include/asm/m5249sim.h new file mode 100644 index 000000000000..366eb8602d2f --- /dev/null +++ b/arch/m68knommu/include/asm/m5249sim.h @@ -0,0 +1,209 @@ +/****************************************************************************/ + +/* + * m5249sim.h -- ColdFire 5249 System Integration Module support. + * + * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) + */ + +/****************************************************************************/ +#ifndef m5249sim_h +#define m5249sim_h +/****************************************************************************/ + +/* + * Define the 5249 SIM register set addresses. + */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ +#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ +#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ +#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ +#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ +#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + +/* + * General purpose IO registers (in MBAR2). + */ +#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ +#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ +#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ +#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ +#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ +#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ +#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ +#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ + +#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ +#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ +#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ + +#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ +#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ +#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ +#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ +#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ +#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ +#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ +#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ + +#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ + +#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ +#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ + + +/* + * Macro to set IMR register. It is 32 bits on the 5249. + */ +#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ + +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#define mcf_getipr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) + +/****************************************************************************/ + +#ifdef __ASSEMBLER__ + +/* + * The M5249C3 board needs a little help getting all its SIM devices + * initialized at kernel start time. dBUG doesn't set much up, so + * we need to do it manually. + */ +.macro m5249c3_setup + /* + * Set MBAR1 and MBAR2, just incase they are not set. + */ + movel #0x10000001,%a0 + movec %a0,%MBAR /* map MBAR region */ + subql #1,%a0 /* get MBAR address in a0 */ + + movel #0x80000001,%a1 + movec %a1,#3086 /* map MBAR2 region */ + subql #1,%a1 /* get MBAR2 address in a1 */ + + /* + * Move secondary interrupts to base at 128. + */ + moveb #0x80,%d0 + moveb %d0,0x16b(%a1) /* interrupt base register */ + + /* + * Work around broken CSMR0/DRAM vector problem. + */ + movel #0x001F0021,%d0 /* disable C/I bit */ + movel %d0,0x84(%a0) /* set CSMR0 */ + + /* + * Disable the PLL firstly. (Who knows what state it is + * in here!). + */ + movel 0x180(%a1),%d0 /* get current PLL value */ + andl #0xfffffffe,%d0 /* PLL bypass first */ + movel %d0,0x180(%a1) /* set PLL register */ + nop + +#if CONFIG_CLOCK_FREQ == 140000000 + /* + * Set initial clock frequency. This assumes M5249C3 board + * is fitted with 11.2896MHz crystal. It will program the + * PLL for 140MHz. Lets go fast :-) + */ + movel #0x125a40f0,%d0 /* set for 140MHz */ + movel %d0,0x180(%a1) /* set PLL register */ + orl #0x1,%d0 + movel %d0,0x180(%a1) /* set PLL register */ +#endif + + /* + * Setup CS1 for ethernet controller. + * (Setup as per M5249C3 doco). + */ + movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ + movel %d0,0x8c(%a0) + movel #0x001f0021,%d0 /* CS1 size of 1Mb */ + movel %d0,0x90(%a0) + movew #0x0080,%d0 /* CS1 = 16bit port, AA */ + movew %d0,0x96(%a0) + + /* + * Setup CS2 for IDE interface. + */ + movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ + movel %d0,0x98(%a0) + movel #0x001f0001,%d0 /* CS2 size of 1MB */ + movel %d0,0x9c(%a0) + movew #0x0080,%d0 /* CS2 = 16bit, TA */ + movew %d0,0xa2(%a0) + + movel #0x00107000,%d0 /* IDEconfig1 */ + movel %d0,0x18c(%a1) + movel #0x000c0400,%d0 /* IDEconfig2 */ + movel %d0,0x190(%a1) + + movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ + orl %d0,0xc(%a1) /* function GPIO19 */ + orl %d0,0x8(%a1) /* enable GPIO19 as output */ + orl %d0,0x4(%a1) /* de-assert IDE reset */ +.endm + +#define PLATFORM_SETUP m5249c3_setup + +#endif /* __ASSEMBLER__ */ + +/****************************************************************************/ +#endif /* m5249sim_h */ diff --git a/arch/m68knommu/include/asm/m5272sim.h b/arch/m68knommu/include/asm/m5272sim.h new file mode 100644 index 000000000000..6217edc21139 --- /dev/null +++ b/arch/m68knommu/include/asm/m5272sim.h @@ -0,0 +1,78 @@ +/****************************************************************************/ + +/* + * m5272sim.h -- ColdFire 5272 System Integration Module support. + * + * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef m5272sim_h +#define m5272sim_h +/****************************************************************************/ + + +/* + * Define the 5272 SIM register set addresses. + */ +#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ +#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ +#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ +#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ +#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ + +#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ + +#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ +#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ +#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ +#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ + +#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ +#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ +#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ +#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ + +#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ +#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ +#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ +#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ +#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ +#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ +#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ +#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ +#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ +#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ +#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ +#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ +#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ +#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ +#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ +#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ + +#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ +#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ +#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ +#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ +#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ +#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ +#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ + +#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ +#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ +#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ +#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ +#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ +#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ +#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ +#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ +#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ + + +/****************************************************************************/ +#endif /* m5272sim_h */ diff --git a/arch/m68knommu/include/asm/m527xsim.h b/arch/m68knommu/include/asm/m527xsim.h new file mode 100644 index 000000000000..1f63ab3fb3e6 --- /dev/null +++ b/arch/m68knommu/include/asm/m527xsim.h @@ -0,0 +1,74 @@ +/****************************************************************************/ + +/* + * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. + * + * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) + */ + +/****************************************************************************/ +#ifndef m527xsim_h +#define m527xsim_h +/****************************************************************************/ + + +/* + * Define the 5270/5271 SIM register set addresses. + */ +#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 /* Vector base number */ +#define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_UART1 14 /* Interrupt number for UART1 */ +#define MCFINT_UART2 15 /* Interrupt number for UART2 */ +#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ + +/* + * SDRAM configuration registers. + */ +#ifdef CONFIG_M5271 +#define MCFSIM_DCR 0x40 /* SDRAM control */ +#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ +#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ +#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ +#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ +#endif +#ifdef CONFIG_M5275 +#define MCFSIM_DMR 0x40 /* SDRAM mode */ +#define MCFSIM_DCR 0x44 /* SDRAM control */ +#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ +#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ +#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ +#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ +#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ +#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ +#endif + +/* + * GPIO pins setups to enable the UARTs. + */ +#ifdef CONFIG_M5271 +#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x0ff0 +#define UART2_ENABLE_MASK 0x3000 +#endif +#ifdef CONFIG_M5275 +#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ +#define UART0_ENABLE_MASK 0x000f +#define UART1_ENABLE_MASK 0x00f0 +#define UART2_ENABLE_MASK 0x3f00 +#endif + +/****************************************************************************/ +#endif /* m527xsim_h */ diff --git a/arch/m68knommu/include/asm/m528xsim.h b/arch/m68knommu/include/asm/m528xsim.h new file mode 100644 index 000000000000..28bf783a5d6d --- /dev/null +++ b/arch/m68knommu/include/asm/m528xsim.h @@ -0,0 +1,159 @@ +/****************************************************************************/ + +/* + * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. + * + * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) + */ + +/****************************************************************************/ +#ifndef m528xsim_h +#define m528xsim_h +/****************************************************************************/ + + +/* + * Define the 5280/5282 SIM register set addresses. + */ +#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ +#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ +#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ +#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ +#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ +#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ +#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ +#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ +#define MCFINTC_IRLR 0x18 /* */ +#define MCFINTC_IACKL 0x19 /* */ +#define MCFINTC_ICR0 0x40 /* Base ICR register */ + +#define MCFINT_VECBASE 64 /* Vector base number */ +#define MCFINT_UART0 13 /* Interrupt number for UART0 */ +#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ + +/* + * SDRAM configuration registers. + */ +#define MCFSIM_DCR 0x44 /* SDRAM control */ +#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ +#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ +#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ +#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ + +/* + * Derek Cheung - 6 Feb 2005 + * add I2C and QSPI register definition using Freescale's MCF5282 + */ +/* set Port AS pin for I2C or UART */ +#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) + +/* Port UA Pin Assignment Register (8 Bit) */ +#define MCF5282_GPIO_PUAPAR 0x10005C + +/* Interrupt Mask Register Register Low */ +#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) +/* Interrupt Control Register 7 */ +#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) + + + +/********************************************************************* +* +* Inter-IC (I2C) Module +* +*********************************************************************/ +/* Read/Write access macros for general use */ +#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address +#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider +#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control +#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status +#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O + +/* Bit level definitions and macros */ +#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable +#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable +#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode +#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode +#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable +#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start + +#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit +#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave +#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy +#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost +#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write +#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt +#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge + + + +/********************************************************************* +* +* Queued Serial Peripheral Interface (QSPI) Module +* +*********************************************************************/ +/* Derek - 21 Feb 2005 */ +/* change to the format used in I2C */ +/* Read/Write access macros for general use */ +#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 +#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 +#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 +#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C +#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 +#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 +#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 + +/* Bit level definitions and macros */ +#define MCF5282_QSPI_QMR_MSTR (0x8000) +#define MCF5282_QSPI_QMR_DOHIE (0x4000) +#define MCF5282_QSPI_QMR_BITS_16 (0x0000) +#define MCF5282_QSPI_QMR_BITS_8 (0x2000) +#define MCF5282_QSPI_QMR_BITS_9 (0x2400) +#define MCF5282_QSPI_QMR_BITS_10 (0x2800) +#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) +#define MCF5282_QSPI_QMR_BITS_12 (0x3000) +#define MCF5282_QSPI_QMR_BITS_13 (0x3400) +#define MCF5282_QSPI_QMR_BITS_14 (0x3800) +#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) +#define MCF5282_QSPI_QMR_CPOL (0x0200) +#define MCF5282_QSPI_QMR_CPHA (0x0100) +#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QDLYR_SPE (0x80) +#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) +#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) + +#define MCF5282_QSPI_QWR_HALT (0x8000) +#define MCF5282_QSPI_QWR_WREN (0x4000) +#define MCF5282_QSPI_QWR_WRTO (0x2000) +#define MCF5282_QSPI_QWR_CSIV (0x1000) +#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) +#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) +#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) + +#define MCF5282_QSPI_QIR_WCEFB (0x8000) +#define MCF5282_QSPI_QIR_ABRTB (0x4000) +#define MCF5282_QSPI_QIR_ABRTL (0x1000) +#define MCF5282_QSPI_QIR_WCEFE (0x0800) +#define MCF5282_QSPI_QIR_ABRTE (0x0400) +#define MCF5282_QSPI_QIR_SPIFE (0x0100) +#define MCF5282_QSPI_QIR_WCEF (0x0008) +#define MCF5282_QSPI_QIR_ABRT (0x0004) +#define MCF5282_QSPI_QIR_SPIF (0x0001) + +#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) + +#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) +#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) +#define MCF5282_QSPI_QCR_CONT (0x8000) +#define MCF5282_QSPI_QCR_BITSE (0x4000) +#define MCF5282_QSPI_QCR_DT (0x2000) +#define MCF5282_QSPI_QCR_DSCK (0x1000) +#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) + +/****************************************************************************/ +#endif /* m528xsim_h */ diff --git a/arch/m68knommu/include/asm/m5307sim.h b/arch/m68knommu/include/asm/m5307sim.h new file mode 100644 index 000000000000..5886728409c0 --- /dev/null +++ b/arch/m68knommu/include/asm/m5307sim.h @@ -0,0 +1,181 @@ +/****************************************************************************/ + +/* + * m5307sim.h -- ColdFire 5307 System Integration Module support. + * + * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. + * (C) Copyright 1999, Lineo (www.lineo.com) + * + * Modified by David W. Miller for the MCF5307 Eval Board. + */ + +/****************************************************************************/ +#ifndef m5307sim_h +#define m5307sim_h +/****************************************************************************/ + +/* + * Define the 5307 SIM register set addresses. + */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ +#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ +#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ + +#ifdef CONFIG_OLDMASK +#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ +#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ +#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ +#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ +#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ +#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ +#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ +#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ +#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ +#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ +#else +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ +#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ +#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ +#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ +#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ +#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ +#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ +#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ +#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ +#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ +#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ +#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ +#endif /* CONFIG_OLDMASK */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ +#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ + + +/* Definition offset address for CS2-7 -- old mask 5307 */ + +#define MCF5307_CS2 (0x400000) +#define MCF5307_CS3 (0x600000) +#define MCF5307_CS4 (0x800000) +#define MCF5307_CS5 (0xA00000) +#define MCF5307_CS6 (0xC00000) +#define MCF5307_CS7 (0xE00000) + + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ +#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ +#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ +#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + +#if defined(CONFIG_M5307) +#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ +#endif + +/* + * Macro to set IMR register. It is 32 bits on the 5307. + */ +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#define mcf_getipr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) + + +/* + * Some symbol defines for the Parallel Port Pin Assignment Register + */ +#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ + /* Clear to select par I/O */ +#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ + /* Clear to select par I/O */ + +/* + * Defines for the IRQPAR Register + */ +#define IRQ5_LEVEL4 0x80 +#define IRQ3_LEVEL6 0x40 +#define IRQ1_LEVEL2 0x20 + + +/* + * Define the Cache register flags. + */ +#define CACR_EC (1<<31) +#define CACR_ESB (1<<29) +#define CACR_DPI (1<<28) +#define CACR_HLCK (1<<27) +#define CACR_CINVA (1<<24) +#define CACR_DNFB (1<<10) +#define CACR_DCM_WTHRU (0<<8) +#define CACR_DCM_WBACK (1<<8) +#define CACR_DCM_OFF_PRE (2<<8) +#define CACR_DCM_OFF_IMP (3<<8) +#define CACR_DW (1<<5) + +#define ACR_BASE_POS 24 +#define ACR_MASK_POS 16 +#define ACR_ENABLE (1<<15) +#define ACR_USER (0<<13) +#define ACR_SUPER (1<<13) +#define ACR_ANY (2<<13) +#define ACR_CM_WTHRU (0<<5) +#define ACR_CM_WBACK (1<<5) +#define ACR_CM_OFF_PRE (2<<5) +#define ACR_CM_OFF_IMP (3<<5) +#define ACR_WPROTECT (1<<2) + +/****************************************************************************/ +#endif /* m5307sim_h */ diff --git a/arch/m68knommu/include/asm/m532xsim.h b/arch/m68knommu/include/asm/m532xsim.h new file mode 100644 index 000000000000..1835fd20a82c --- /dev/null +++ b/arch/m68knommu/include/asm/m532xsim.h @@ -0,0 +1,2238 @@ +/****************************************************************************/ + +/* + * m532xsim.h -- ColdFire 5329 registers + */ + +/****************************************************************************/ +#ifndef m532xsim_h +#define m532xsim_h +/****************************************************************************/ + +#define MCF_REG32(x) (*(volatile unsigned long *)(x)) +#define MCF_REG16(x) (*(volatile unsigned short *)(x)) +#define MCF_REG08(x) (*(volatile unsigned char *)(x)) + +#define MCFINT_VECBASE 64 +#define MCFINT_UART0 26 /* Interrupt number for UART0 */ +#define MCFINT_UART1 27 /* Interrupt number for UART1 */ + +#define MCF_WTM_WCR MCF_REG16(0xFC098000) + +/* + * Define the 532x SIM register set addresses. + */ +#define MCFSIM_IPRL 0xFC048004 +#define MCFSIM_IPRH 0xFC048000 +#define MCFSIM_IPR MCFSIM_IPRL +#define MCFSIM_IMRL 0xFC04800C +#define MCFSIM_IMRH 0xFC048008 +#define MCFSIM_IMR MCFSIM_IMRL +#define MCFSIM_ICR0 0xFC048040 +#define MCFSIM_ICR1 0xFC048041 +#define MCFSIM_ICR2 0xFC048042 +#define MCFSIM_ICR3 0xFC048043 +#define MCFSIM_ICR4 0xFC048044 +#define MCFSIM_ICR5 0xFC048045 +#define MCFSIM_ICR6 0xFC048046 +#define MCFSIM_ICR7 0xFC048047 +#define MCFSIM_ICR8 0xFC048048 +#define MCFSIM_ICR9 0xFC048049 +#define MCFSIM_ICR10 0xFC04804A +#define MCFSIM_ICR11 0xFC04804B + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ +#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ +#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ +#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + + +#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ + +#define MCFSIM_IMR_SIMR0 0xFC04801C +#define MCFSIM_IMR_SIMR1 0xFC04C01C +#define MCFSIM_IMR_CIMR0 0xFC04801D +#define MCFSIM_IMR_CIMR1 0xFC04C01D + +#define MCFSIM_ICR_TIMER1 (0xFC048040+32) +#define MCFSIM_ICR_TIMER2 (0xFC048040+33) + + +/* + * Macro to set IMR register. It is 32 bits on the 5307. + */ +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#define mcf_getipr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) + +#define mcf_getiprl() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL)) + +#define mcf_getiprh() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH)) + + +#define mcf_enable_irq0(irq) \ + *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq); + +#define mcf_enable_irq1(irq) \ + *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq); + +#define mcf_disable_irq0(irq) \ + *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq); + +#define mcf_disable_irq1(irq) \ + *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq); + +/* + * Define the Cache register flags. + */ +#define CACR_EC (1<<31) +#define CACR_ESB (1<<29) +#define CACR_DPI (1<<28) +#define CACR_HLCK (1<<27) +#define CACR_CINVA (1<<24) +#define CACR_DNFB (1<<10) +#define CACR_DCM_WTHRU (0<<8) +#define CACR_DCM_WBACK (1<<8) +#define CACR_DCM_OFF_PRE (2<<8) +#define CACR_DCM_OFF_IMP (3<<8) +#define CACR_DW (1<<5) + +#define ACR_BASE_POS 24 +#define ACR_MASK_POS 16 +#define ACR_ENABLE (1<<15) +#define ACR_USER (0<<13) +#define ACR_SUPER (1<<13) +#define ACR_ANY (2<<13) +#define ACR_CM_WTHRU (0<<5) +#define ACR_CM_WBACK (1<<5) +#define ACR_CM_OFF_PRE (2<<5) +#define ACR_CM_OFF_IMP (3<<5) +#define ACR_WPROTECT (1<<2) + +/********************************************************************* + * + * Inter-IC (I2C) Module + * + *********************************************************************/ + +/* Read/Write access macros for general use */ +#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address +#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider +#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control +#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status +#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O + +/* Bit level definitions and macros */ +#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) + +#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F)) + +#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable +#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable +#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode +#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode +#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable +#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start + +#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit +#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave +#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy +#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost +#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write +#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt +#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge + +#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053) + + +/* + * The M5329EVB board needs a help getting its devices initialized + * at kernel start time if dBUG doesn't set it up (for example + * it is not used), so we need to do it manually. + */ +#ifdef __ASSEMBLER__ +.macro m5329EVB_setup + movel #0xFC098000, %a7 + movel #0x0, (%a7) +#define CORE_SRAM 0x80000000 +#define CORE_SRAM_SIZE 0x8000 + movel #CORE_SRAM, %d0 + addl #0x221, %d0 + movec %d0,%RAMBAR1 + movel #CORE_SRAM, %sp + addl #CORE_SRAM_SIZE, %sp + jsr sysinit +.endm +#define PLATFORM_SETUP m5329EVB_setup + +#endif /* __ASSEMBLER__ */ + +/********************************************************************* + * + * Chip Configuration Module (CCM) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) +#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) +#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) +#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) +#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) +#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) +#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) + +/* Bit definitions and macros for MCF_CCM_CCR */ +#define MCF_CCM_CCR_RESERVED (0x0001) +#define MCF_CCM_CCR_PLL_MODE (0x0003) +#define MCF_CCM_CCR_OSC_MODE (0x0005) +#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define MCF_CCM_CCR_LOAD (0x0021) +#define MCF_CCM_CCR_LIMP (0x0041) +#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) + +/* Bit definitions and macros for MCF_CCM_RCON */ +#define MCF_CCM_RCON_RESERVED (0x0001) +#define MCF_CCM_RCON_PLL_MODE (0x0003) +#define MCF_CCM_RCON_OSC_MODE (0x0005) +#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) +#define MCF_CCM_RCON_LOAD (0x0021) +#define MCF_CCM_RCON_LIMP (0x0041) +#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) + +/* Bit definitions and macros for MCF_CCM_CIR */ +#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) +#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) + +/* Bit definitions and macros for MCF_CCM_MISCCR */ +#define MCF_CCM_MISCCR_USBSRC (0x0001) +#define MCF_CCM_MISCCR_USBDIV (0x0002) +#define MCF_CCM_MISCCR_SSI_SRC (0x0010) +#define MCF_CCM_MISCCR_TIM_DMA (0x0020) +#define MCF_CCM_MISCCR_SSI_PUS (0x0040) +#define MCF_CCM_MISCCR_SSI_PUE (0x0080) +#define MCF_CCM_MISCCR_LCD_CHEN (0x0100) +#define MCF_CCM_MISCCR_LIMP (0x1000) +#define MCF_CCM_MISCCR_PLL_LOCK (0x2000) + +/* Bit definitions and macros for MCF_CCM_CDR */ +#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) +#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) + +/* Bit definitions and macros for MCF_CCM_UHCSR */ +#define MCF_CCM_UHCSR_XPDE (0x0001) +#define MCF_CCM_UHCSR_UHMIE (0x0002) +#define MCF_CCM_UHCSR_WKUP (0x0004) +#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_CCM_UOCSR */ +#define MCF_CCM_UOCSR_XPDE (0x0001) +#define MCF_CCM_UOCSR_UOMIE (0x0002) +#define MCF_CCM_UOCSR_WKUP (0x0004) +#define MCF_CCM_UOCSR_PWRFLT (0x0008) +#define MCF_CCM_UOCSR_SEND (0x0010) +#define MCF_CCM_UOCSR_VVLD (0x0020) +#define MCF_CCM_UOCSR_BVLD (0x0040) +#define MCF_CCM_UOCSR_AVLD (0x0080) +#define MCF_CCM_UOCSR_DPPU (0x0100) +#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) +#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) +#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) +#define MCF_CCM_UOCSR_DMPD (0x1000) +#define MCF_CCM_UOCSR_DPPD (0x2000) +#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) + +/********************************************************************* + * + * DMA Timers (DTIM) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000) +#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002) +#define MCF_DTIM0_DTER MCF_REG08(0xFC070003) +#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004) +#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008) +#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C) +#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000) +#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002) +#define MCF_DTIM1_DTER MCF_REG08(0xFC074003) +#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004) +#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008) +#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C) +#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000) +#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002) +#define MCF_DTIM2_DTER MCF_REG08(0xFC078003) +#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004) +#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008) +#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C) +#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000) +#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002) +#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003) +#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004) +#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008) +#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C) +#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000)) +#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000)) +#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000)) +#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000)) +#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000)) +#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000)) + +/* Bit definitions and macros for MCF_DTIM_DTMR */ +#define MCF_DTIM_DTMR_RST (0x0001) +#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) +#define MCF_DTIM_DTMR_FRR (0x0008) +#define MCF_DTIM_DTMR_ORRI (0x0010) +#define MCF_DTIM_DTMR_OM (0x0020) +#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) +#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) +#define MCF_DTIM_DTMR_CE_ANY (0x00C0) +#define MCF_DTIM_DTMR_CE_FALL (0x0080) +#define MCF_DTIM_DTMR_CE_RISE (0x0040) +#define MCF_DTIM_DTMR_CE_NONE (0x0000) +#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) +#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) +#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) +#define MCF_DTIM_DTMR_CLK_STOP (0x0000) + +/* Bit definitions and macros for MCF_DTIM_DTXMR */ +#define MCF_DTIM_DTXMR_MODE16 (0x01) +#define MCF_DTIM_DTXMR_DMAEN (0x80) + +/* Bit definitions and macros for MCF_DTIM_DTER */ +#define MCF_DTIM_DTER_CAP (0x01) +#define MCF_DTIM_DTER_REF (0x02) + +/* Bit definitions and macros for MCF_DTIM_DTRR */ +#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCR */ +#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_DTIM_DTCN */ +#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* + * + * FlexBus Chip Selects (FBCS) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) +#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) +#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) +#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) +#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) +#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) +#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) +#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) +#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) +#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) +#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) +#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) +#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) +#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) +#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) +#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) +#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) +#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) +#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) +#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) +#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) + +/* Bit definitions and macros for MCF_FBCS_CSAR */ +#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) + +/* Bit definitions and macros for MCF_FBCS_CSMR */ +#define MCF_FBCS_CSMR_V (0x00000001) +#define MCF_FBCS_CSMR_WP (0x00000100) +#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) +#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) +#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) +#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) +#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) +#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) +#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) +#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) +#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) +#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) +#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) +#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) +#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) +#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) +#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) +#define MCF_FBCS_CSMR_BAM_512K (0x00070000) +#define MCF_FBCS_CSMR_BAM_256K (0x00030000) +#define MCF_FBCS_CSMR_BAM_128K (0x00010000) +#define MCF_FBCS_CSMR_BAM_64K (0x00000000) + +/* Bit definitions and macros for MCF_FBCS_CSCR */ +#define MCF_FBCS_CSCR_BSTW (0x00000008) +#define MCF_FBCS_CSCR_BSTR (0x00000010) +#define MCF_FBCS_CSCR_BEM (0x00000020) +#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) +#define MCF_FBCS_CSCR_AA (0x00000100) +#define MCF_FBCS_CSCR_SBM (0x00000200) +#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) +#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) +#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) +#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) +#define MCF_FBCS_CSCR_SWSEN (0x00800000) +#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) +#define MCF_FBCS_CSCR_PS_8 (0x0040) +#define MCF_FBCS_CSCR_PS_16 (0x0080) +#define MCF_FBCS_CSCR_PS_32 (0x0000) + +/********************************************************************* + * + * General Purpose I/O (GPIO) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_GPIO_PODR_FECH MCF_REG08(0xFC0A4000) +#define MCF_GPIO_PODR_FECL MCF_REG08(0xFC0A4001) +#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) +#define MCF_GPIO_PODR_BUSCTL MCF_REG08(0xFC0A4003) +#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) +#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) +#define MCF_GPIO_PODR_PWM MCF_REG08(0xFC0A4006) +#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) +#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) +#define MCF_GPIO_PODR_QSPI MCF_REG08(0xFC0A400A) +#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) +#define MCF_GPIO_PODR_LCDDATAH MCF_REG08(0xFC0A400D) +#define MCF_GPIO_PODR_LCDDATAM MCF_REG08(0xFC0A400E) +#define MCF_GPIO_PODR_LCDDATAL MCF_REG08(0xFC0A400F) +#define MCF_GPIO_PODR_LCDCTLH MCF_REG08(0xFC0A4010) +#define MCF_GPIO_PODR_LCDCTLL MCF_REG08(0xFC0A4011) +#define MCF_GPIO_PDDR_FECH MCF_REG08(0xFC0A4014) +#define MCF_GPIO_PDDR_FECL MCF_REG08(0xFC0A4015) +#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A4016) +#define MCF_GPIO_PDDR_BUSCTL MCF_REG08(0xFC0A4017) +#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A4018) +#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A4019) +#define MCF_GPIO_PDDR_PWM MCF_REG08(0xFC0A401A) +#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401B) +#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A401C) +#define MCF_GPIO_PDDR_QSPI MCF_REG08(0xFC0A401E) +#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A401F) +#define MCF_GPIO_PDDR_LCDDATAH MCF_REG08(0xFC0A4021) +#define MCF_GPIO_PDDR_LCDDATAM MCF_REG08(0xFC0A4022) +#define MCF_GPIO_PDDR_LCDDATAL MCF_REG08(0xFC0A4023) +#define MCF_GPIO_PDDR_LCDCTLH MCF_REG08(0xFC0A4024) +#define MCF_GPIO_PDDR_LCDCTLL MCF_REG08(0xFC0A4025) +#define MCF_GPIO_PPDSDR_FECH MCF_REG08(0xFC0A4028) +#define MCF_GPIO_PPDSDR_FECL MCF_REG08(0xFC0A4029) +#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A402A) +#define MCF_GPIO_PPDSDR_BUSCTL MCF_REG08(0xFC0A402B) +#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A402C) +#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A402D) +#define MCF_GPIO_PPDSDR_PWM MCF_REG08(0xFC0A402E) +#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A402F) +#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4031) +#define MCF_GPIO_PPDSDR_QSPI MCF_REG08(0xFC0A4032) +#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A4033) +#define MCF_GPIO_PPDSDR_LCDDATAH MCF_REG08(0xFC0A4035) +#define MCF_GPIO_PPDSDR_LCDDATAM MCF_REG08(0xFC0A4036) +#define MCF_GPIO_PPDSDR_LCDDATAL MCF_REG08(0xFC0A4037) +#define MCF_GPIO_PPDSDR_LCDCTLH MCF_REG08(0xFC0A4038) +#define MCF_GPIO_PPDSDR_LCDCTLL MCF_REG08(0xFC0A4039) +#define MCF_GPIO_PCLRR_FECH MCF_REG08(0xFC0A403C) +#define MCF_GPIO_PCLRR_FECL MCF_REG08(0xFC0A403D) +#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A403E) +#define MCF_GPIO_PCLRR_BUSCTL MCF_REG08(0xFC0A403F) +#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A4040) +#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A4041) +#define MCF_GPIO_PCLRR_PWM MCF_REG08(0xFC0A4042) +#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A4043) +#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4045) +#define MCF_GPIO_PCLRR_QSPI MCF_REG08(0xFC0A4046) +#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4047) +#define MCF_GPIO_PCLRR_LCDDATAH MCF_REG08(0xFC0A4049) +#define MCF_GPIO_PCLRR_LCDDATAM MCF_REG08(0xFC0A404A) +#define MCF_GPIO_PCLRR_LCDDATAL MCF_REG08(0xFC0A404B) +#define MCF_GPIO_PCLRR_LCDCTLH MCF_REG08(0xFC0A404C) +#define MCF_GPIO_PCLRR_LCDCTLL MCF_REG08(0xFC0A404D) +#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) +#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) +#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) +#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) +#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) +#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) +#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) +#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) +#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) +#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) +#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) +#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) +#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) +#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) +#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) +#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) +#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) +#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) +#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) +#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) +#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) +#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) +#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) +#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) +#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) +#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ +#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) +#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) +#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) +#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) +#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) +#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) +#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) +#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECL */ +#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) +#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) +#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) +#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) +#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) +#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) +#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) +#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_SSI */ +#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) +#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) +#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) +#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) +#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ +#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) +#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_BE */ +#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) +#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) +#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) +#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_CS */ +#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) +#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) +#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) +#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) +#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_PWM */ +#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) +#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) +#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) +#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) +#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_UART */ +#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) +#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) +#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) +#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) +#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) +#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) +#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) +#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ +#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) +#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ +#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) +#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) +#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) +#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) +#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ +#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) +#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ +#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) +#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ +#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) +#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ +#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) +#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ +#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) +#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_BE */ +#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) +#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) +#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) +#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ +#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) +#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) +#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) +#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) +#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ +#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) +#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) +#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_UART */ +#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) +#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) +#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) +#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) +#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) +#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) +#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) +#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) +#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) +#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) +#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) +#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ +#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) +#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) +#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) +#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) +#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ +#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) +#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) +#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) +#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) +#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) +#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) +#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) +#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) +#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) +#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) +#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ +#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) +#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) +#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) +#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) +#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ +#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) +#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ +#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) +#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ +#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) +#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) +#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) +#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ +#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) +#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) +#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) +#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) +#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) +#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ +#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) + +/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) +#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) + +/* Bit definitions and macros for MCF_GPIO_PAR_FEC */ +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) +#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) +#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_PWM */ +#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) +#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) + +/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ +#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) +#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) + +/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ +#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) +#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) +#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) +#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) +#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_BE */ +#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) +#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) +#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) +#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) + +/* Bit definitions and macros for MCF_GPIO_PAR_CS */ +#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) +#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) +#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) +#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) +#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) +#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_SSI */ +#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) +#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_GPIO_PAR_UART */ +#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) +#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) +#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) +#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) +#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) +#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) +#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) +#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) +#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) +#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) +#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) +#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) +#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) + +/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ +#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) +#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) + +/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ +#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) +#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) +#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) +#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) +#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) + +/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ +#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) +#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) + +/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ +#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) +#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) +#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) +#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) +#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) +#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) +#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) +#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) +#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) + +/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ +#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) +#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) + +/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) +#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) +#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) + +/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ +#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ +#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ +#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ +#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) +#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) + +/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ +#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ +#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ +#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ +#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ +#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ +#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) + +/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ +#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) + +/********************************************************************* + * + * Interrupt Controller (INTC) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) +#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) +#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) +#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) +#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) +#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) +#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) +#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) +#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) +#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) +#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) +#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040) +#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) +#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) +#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) +#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) +#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) +#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) +#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) +#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) +#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) +#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) +#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) +#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) +#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) +#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) +#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) +#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) +#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) +#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) +#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) +#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) +#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) +#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) +#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) +#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) +#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) +#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) +#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) +#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) +#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) +#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) +#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) +#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) +#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) +#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) +#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) +#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) +#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) +#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) +#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) +#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) +#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) +#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) +#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) +#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) +#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) +#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) +#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) +#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) +#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) +#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) +#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) +#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) +#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) +#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) +#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) +#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) +#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) +#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) +#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) +#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) +#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) +#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) +#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) +#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001)) +#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) +#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) +#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) +#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) +#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) +#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) +#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) +#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) +#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004)) +#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) +#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) +#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) +#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) +#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) +#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) +#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) +#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) +#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) +#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) +#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) +#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040) +#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) +#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) +#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) +#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) +#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) +#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) +#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) +#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) +#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) +#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) +#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) +#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) +#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) +#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) +#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) +#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) +#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) +#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) +#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) +#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) +#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) +#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) +#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) +#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) +#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) +#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) +#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) +#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) +#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) +#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) +#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) +#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) +#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) +#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) +#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) +#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) +#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) +#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) +#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) +#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) +#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) +#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) +#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) +#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) +#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) +#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) +#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) +#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) +#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) +#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) +#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) +#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) +#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) +#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) +#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) +#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) +#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) +#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) +#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) +#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) +#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) +#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) +#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) +#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001)) +#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) +#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) +#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) +#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) +#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) +#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) +#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8) +#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) +#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004)) +#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) +#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) +#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) +#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) +#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) +#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) +#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) +#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) +#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) +#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) +#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) +#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000)) +#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) +#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) +#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) +#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) +#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) +#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) +#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) +#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) +#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) +#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) +#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) +#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) +#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) +#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) +#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) +#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) +#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) +#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) +#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) +#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) +#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) +#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) +#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) +#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) +#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) +#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) +#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) +#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) +#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) +#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) +#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) +#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) +#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) +#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) +#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) +#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) +#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) +#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) +#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) +#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) +#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) +#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) +#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) +#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) +#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) +#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) +#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) +#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) +#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) +#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) +#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) +#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) +#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) +#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) +#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) +#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) +#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) +#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) +#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) +#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) +#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) +#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) +#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) +#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) +#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) +#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) +#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) +#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) +#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) +#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) +#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) + +/* Bit definitions and macros for MCF_INTC_IPRH */ +#define MCF_INTC_IPRH_INT32 (0x00000001) +#define MCF_INTC_IPRH_INT33 (0x00000002) +#define MCF_INTC_IPRH_INT34 (0x00000004) +#define MCF_INTC_IPRH_INT35 (0x00000008) +#define MCF_INTC_IPRH_INT36 (0x00000010) +#define MCF_INTC_IPRH_INT37 (0x00000020) +#define MCF_INTC_IPRH_INT38 (0x00000040) +#define MCF_INTC_IPRH_INT39 (0x00000080) +#define MCF_INTC_IPRH_INT40 (0x00000100) +#define MCF_INTC_IPRH_INT41 (0x00000200) +#define MCF_INTC_IPRH_INT42 (0x00000400) +#define MCF_INTC_IPRH_INT43 (0x00000800) +#define MCF_INTC_IPRH_INT44 (0x00001000) +#define MCF_INTC_IPRH_INT45 (0x00002000) +#define MCF_INTC_IPRH_INT46 (0x00004000) +#define MCF_INTC_IPRH_INT47 (0x00008000) +#define MCF_INTC_IPRH_INT48 (0x00010000) +#define MCF_INTC_IPRH_INT49 (0x00020000) +#define MCF_INTC_IPRH_INT50 (0x00040000) +#define MCF_INTC_IPRH_INT51 (0x00080000) +#define MCF_INTC_IPRH_INT52 (0x00100000) +#define MCF_INTC_IPRH_INT53 (0x00200000) +#define MCF_INTC_IPRH_INT54 (0x00400000) +#define MCF_INTC_IPRH_INT55 (0x00800000) +#define MCF_INTC_IPRH_INT56 (0x01000000) +#define MCF_INTC_IPRH_INT57 (0x02000000) +#define MCF_INTC_IPRH_INT58 (0x04000000) +#define MCF_INTC_IPRH_INT59 (0x08000000) +#define MCF_INTC_IPRH_INT60 (0x10000000) +#define MCF_INTC_IPRH_INT61 (0x20000000) +#define MCF_INTC_IPRH_INT62 (0x40000000) +#define MCF_INTC_IPRH_INT63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IPRL */ +#define MCF_INTC_IPRL_INT0 (0x00000001) +#define MCF_INTC_IPRL_INT1 (0x00000002) +#define MCF_INTC_IPRL_INT2 (0x00000004) +#define MCF_INTC_IPRL_INT3 (0x00000008) +#define MCF_INTC_IPRL_INT4 (0x00000010) +#define MCF_INTC_IPRL_INT5 (0x00000020) +#define MCF_INTC_IPRL_INT6 (0x00000040) +#define MCF_INTC_IPRL_INT7 (0x00000080) +#define MCF_INTC_IPRL_INT8 (0x00000100) +#define MCF_INTC_IPRL_INT9 (0x00000200) +#define MCF_INTC_IPRL_INT10 (0x00000400) +#define MCF_INTC_IPRL_INT11 (0x00000800) +#define MCF_INTC_IPRL_INT12 (0x00001000) +#define MCF_INTC_IPRL_INT13 (0x00002000) +#define MCF_INTC_IPRL_INT14 (0x00004000) +#define MCF_INTC_IPRL_INT15 (0x00008000) +#define MCF_INTC_IPRL_INT16 (0x00010000) +#define MCF_INTC_IPRL_INT17 (0x00020000) +#define MCF_INTC_IPRL_INT18 (0x00040000) +#define MCF_INTC_IPRL_INT19 (0x00080000) +#define MCF_INTC_IPRL_INT20 (0x00100000) +#define MCF_INTC_IPRL_INT21 (0x00200000) +#define MCF_INTC_IPRL_INT22 (0x00400000) +#define MCF_INTC_IPRL_INT23 (0x00800000) +#define MCF_INTC_IPRL_INT24 (0x01000000) +#define MCF_INTC_IPRL_INT25 (0x02000000) +#define MCF_INTC_IPRL_INT26 (0x04000000) +#define MCF_INTC_IPRL_INT27 (0x08000000) +#define MCF_INTC_IPRL_INT28 (0x10000000) +#define MCF_INTC_IPRL_INT29 (0x20000000) +#define MCF_INTC_IPRL_INT30 (0x40000000) +#define MCF_INTC_IPRL_INT31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRH */ +#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) +#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) +#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) +#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) +#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) +#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) +#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) +#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) +#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) +#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) +#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) +#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) +#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) +#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) +#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) +#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) +#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) +#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) +#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) +#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) +#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) +#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) +#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) +#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) +#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) +#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) +#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) +#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) +#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) +#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) +#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) +#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_IMRL */ +#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) +#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) +#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) +#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) +#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) +#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) +#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) +#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) +#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) +#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) +#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) +#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) +#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) +#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) +#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) +#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) +#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) +#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) +#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) +#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) +#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) +#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) +#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) +#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) +#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) +#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) +#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) +#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) +#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) +#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) +#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) +#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCH */ +#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) +#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) +#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) +#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) +#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) +#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) +#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) +#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) +#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) +#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) +#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) +#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) +#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) +#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) +#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) +#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) +#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) +#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) +#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) +#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) +#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) +#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) +#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) +#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) +#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) +#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) +#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) +#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) +#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) +#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) +#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) +#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_INTFRCL */ +#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) +#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) +#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) +#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) +#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) +#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) +#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) +#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) +#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) +#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) +#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) +#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) +#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) +#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) +#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) +#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) +#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) +#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) +#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) +#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) +#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) +#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) +#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) +#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) +#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) +#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) +#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) +#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) +#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) +#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) +#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) +#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) + +/* Bit definitions and macros for MCF_INTC_ICONFIG */ +#define MCF_INTC_ICONFIG_EMASK (0x0020) +#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) +#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) +#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) +#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) +#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) +#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) +#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) + +/* Bit definitions and macros for MCF_INTC_SIMR */ +#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_INTC_CIMR */ +#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) + +/* Bit definitions and macros for MCF_INTC_CLMASK */ +#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_INTC_SLMASK */ +#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) + +/* Bit definitions and macros for MCF_INTC_ICR */ +#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) + +/* Bit definitions and macros for MCF_INTC_SWIACK */ +#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_INTC_LIACK */ +#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) + +/********************************************************************/ +/********************************************************************* +* +* LCD Controller (LCDC) +* +*********************************************************************/ + +/* Register read/write macros */ +#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000) +#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004) +#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008) +#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C) +#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010) +#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014) +#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018) +#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C) +#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020) +#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024) +#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028) +#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C) +#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030) +#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034) +#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038) +#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C) +#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040) +#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050) +#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054) +#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058) +#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C) +#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060) +#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064) +#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068) +#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800) +#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00) + +/* Bit definitions and macros for MCF_LCDC_LSSAR */ +#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_LCDC_LSR */ +#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for MCF_LCDC_LVPWR */ +#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for MCF_LCDC_LCPR */ +#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) +#define MCF_LCDC_LCPR_OP (0x10000000) +#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) +#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) +#define MCF_LCDC_LCPR_CC_OR (0x40000000) +#define MCF_LCDC_LCPR_CC_XOR (0x80000000) +#define MCF_LCDC_LCPR_CC_AND (0xC0000000) +#define MCF_LCDC_LCPR_OP_ON (0x10000000) +#define MCF_LCDC_LCPR_OP_OFF (0x00000000) + +/* Bit definitions and macros for MCF_LCDC_LCWHBR */ +#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) +#define MCF_LCDC_LCWHBR_BK_EN (0x80000000) +#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) +#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) + +/* Bit definitions and macros for MCF_LCDC_LCCMR */ +#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) +#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) + +/* Bit definitions and macros for MCF_LCDC_LPCR */ +#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LPCR_SHARP (0x00000040) +#define MCF_LCDC_LPCR_SCLKSEL (0x00000080) +#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) +#define MCF_LCDC_LPCR_ACDSEL (0x00008000) +#define MCF_LCDC_LPCR_REV_VS (0x00010000) +#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) +#define MCF_LCDC_LPCR_ENDSEL (0x00040000) +#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) +#define MCF_LCDC_LPCR_OEPOL (0x00100000) +#define MCF_LCDC_LPCR_CLKPOL (0x00200000) +#define MCF_LCDC_LPCR_LPPOL (0x00400000) +#define MCF_LCDC_LPCR_FLM (0x00800000) +#define MCF_LCDC_LPCR_PIXPOL (0x01000000) +#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) +#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) +#define MCF_LCDC_LPCR_COLOR (0x40000000) +#define MCF_LCDC_LPCR_TFT (0x80000000) +#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000) +#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) +#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) +#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) +#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) +#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) +#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) +#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) +#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) +#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) +#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) +#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) +#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) +#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) + +#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) + +/* Bit definitions and macros for MCF_LCDC_LHCR */ +#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) +#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for MCF_LCDC_LVCR */ +#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) +#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) + +/* Bit definitions and macros for MCF_LCDC_LPOR */ +#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for MCF_LCDC_LPCCR */ +#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) +#define MCF_LCDC_LPCCR_CC_EN (0x00000100) +#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) +#define MCF_LCDC_LPCCR_LDMSK (0x00008000) +#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) +#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) +#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) +#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) + +/* Bit definitions and macros for MCF_LCDC_LDCR */ +#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) +#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LDCR_BURST (0x80000000) + +/* Bit definitions and macros for MCF_LCDC_LRMCR */ +#define MCF_LCDC_LRMCR_SEL_REF (0x00000001) + +/* Bit definitions and macros for MCF_LCDC_LICR */ +#define MCF_LCDC_LICR_INTCON (0x00000001) +#define MCF_LCDC_LICR_INTSYN (0x00000004) +#define MCF_LCDC_LICR_GW_INT_CON (0x00000010) + +/* Bit definitions and macros for MCF_LCDC_LIER */ +#define MCF_LCDC_LIER_BOF_EN (0x00000001) +#define MCF_LCDC_LIER_EOF_EN (0x00000002) +#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) +#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) +#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) +#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) +#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) +#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) + +/* Bit definitions and macros for MCF_LCDC_LISR */ +#define MCF_LCDC_LISR_BOF (0x00000001) +#define MCF_LCDC_LISR_EOF (0x00000002) +#define MCF_LCDC_LISR_ERR_RES (0x00000004) +#define MCF_LCDC_LISR_UDR_ERR (0x00000008) +#define MCF_LCDC_LISR_GW_BOF (0x00000010) +#define MCF_LCDC_LISR_GW_EOF (0x00000020) +#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) +#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) + +/* Bit definitions and macros for MCF_LCDC_LGWSAR */ +#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) + +/* Bit definitions and macros for MCF_LCDC_LGWSR */ +#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) + +/* Bit definitions and macros for MCF_LCDC_LGWVPWR */ +#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) + +/* Bit definitions and macros for MCF_LCDC_LGWPOR */ +#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) + +/* Bit definitions and macros for MCF_LCDC_LGWPR */ +#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) +#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) + +/* Bit definitions and macros for MCF_LCDC_LGWCR */ +#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) +#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) +#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) +#define MCF_LCDC_LGWCR_GW_RVS (0x00200000) +#define MCF_LCDC_LGWCR_GWE (0x00400000) +#define MCF_LCDC_LGWCR_GWCKE (0x00800000) +#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) + +/* Bit definitions and macros for MCF_LCDC_LGWDCR */ +#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) +#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) +#define MCF_LCDC_LGWDCR_GWBT (0x80000000) + +/* Bit definitions and macros for MCF_LCDC_LSCR */ +#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) +#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) +#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) +#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) +#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) + +/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ +#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ +#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) + +/********************************************************************* + * + * Phase Locked Loop (PLL) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_PLL_PODR MCF_REG08(0xFC0C0000) +#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) +#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) +#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) + +/* Bit definitions and macros for MCF_PLL_PODR */ +#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) +#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) + +/* Bit definitions and macros for MCF_PLL_PLLCR */ +#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) +#define MCF_PLL_PLLCR_DITHEN (0x80) + +/* Bit definitions and macros for MCF_PLL_PMDR */ +#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) + +/* Bit definitions and macros for MCF_PLL_PFDR */ +#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) + +/********************************************************************* + * + * System Control Module Registers (SCM) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_SCM_MPR MCF_REG32(0xFC000000) +#define MCF_SCM_PACRA MCF_REG32(0xFC000020) +#define MCF_SCM_PACRB MCF_REG32(0xFC000024) +#define MCF_SCM_PACRC MCF_REG32(0xFC000028) +#define MCF_SCM_PACRD MCF_REG32(0xFC00002C) +#define MCF_SCM_PACRE MCF_REG32(0xFC000040) +#define MCF_SCM_PACRF MCF_REG32(0xFC000044) + +#define MCF_SCM_BCR MCF_REG32(0xFC040024) + +/********************************************************************* + * + * SDRAM Controller (SDRAMC) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) +#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) +#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) +#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) +#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) +#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) +#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) +#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) +#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) +#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) +#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004)) + +/* Bit definitions and macros for MCF_SDRAMC_SDMR */ +#define MCF_SDRAMC_SDMR_CMD (0x00010000) +#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) +#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) +#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) +#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCR */ +#define MCF_SDRAMC_SDCR_IPALL (0x00000002) +#define MCF_SDRAMC_SDCR_IREF (0x00000004) +#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) +#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) +#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) +#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) +#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) +#define MCF_SDRAMC_SDCR_REF (0x10000000) +#define MCF_SDRAMC_SDCR_DDR (0x20000000) +#define MCF_SDRAMC_SDCR_CKE (0x40000000) +#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) +#define MCF_SDRAMC_SDCR_PS_16 (0x00002000) +#define MCF_SDRAMC_SDCR_PS_32 (0x00000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ +#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) +#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) +#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) +#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) +#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) +#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) +#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) + +/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ +#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) +#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) +#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) +#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) + +/* Device Errata - LIMP mode work around */ +#define MCF_SDRAMC_REFRESH (0x40000000) + +/* Bit definitions and macros for MCF_SDRAMC_SDDS */ +#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) +#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) +#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) +#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) +#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) + +/* Bit definitions and macros for MCF_SDRAMC_SDCS */ +#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) +#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) +#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) +#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) +#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) +#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) +#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) +#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) +#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) +#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) +#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) +#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) +#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) +#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) +#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) +#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) +#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) + +/********************************************************************* + * + * FlexCAN module registers + * + *********************************************************************/ +#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800) +#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00) +#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04) +#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08) +#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10) +#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14) +#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18) +#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C) +#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20) +#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28) +#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30) + +#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0) +#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4) +#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1) + +/* + * FlexCAN Module Configuration Register + */ +#define CANMCR_MDIS (0x80000000) +#define CANMCR_FRZ (0x40000000) +#define CANMCR_HALT (0x10000000) +#define CANMCR_SOFTRST (0x02000000) +#define CANMCR_FRZACK (0x01000000) +#define CANMCR_SUPV (0x00800000) +#define CANMCR_MAXMB(x) ((x)&0x0F) + +/* + * FlexCAN Control Register + */ +#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) +#define CANCTRL_RJW(x) (((x)&0x03)<<22) +#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) +#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) +#define CANCTRL_BOFFMSK (0x00008000) +#define CANCTRL_ERRMSK (0x00004000) +#define CANCTRL_CLKSRC (0x00002000) +#define CANCTRL_LPB (0x00001000) +#define CANCTRL_SAMP (0x00000080) +#define CANCTRL_BOFFREC (0x00000040) +#define CANCTRL_TSYNC (0x00000020) +#define CANCTRL_LBUF (0x00000010) +#define CANCTRL_LOM (0x00000008) +#define CANCTRL_PROPSEG(x) ((x)&0x07) + +/* + * FlexCAN Error Counter Register + */ +#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) +#define ERRCNT_TXECTR(x) ((x)&0xFF) + +/* + * FlexCAN Error and Status Register + */ +#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) +#define ERRSTAT_ACKERR (0x00002000) +#define ERRSTAT_CRCERR (0x00001000) +#define ERRSTAT_FRMERR (0x00000800) +#define ERRSTAT_STFERR (0x00000400) +#define ERRSTAT_TXWRN (0x00000200) +#define ERRSTAT_RXWRN (0x00000100) +#define ERRSTAT_IDLE (0x00000080) +#define ERRSTAT_TXRX (0x00000040) +#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) +#define ERRSTAT_BOFFINT (0x00000004) +#define ERRSTAT_ERRINT (0x00000002) + +/* + * Interrupt Mask Register + */ +#define IMASK_BUF15M (0x8000) +#define IMASK_BUF14M (0x4000) +#define IMASK_BUF13M (0x2000) +#define IMASK_BUF12M (0x1000) +#define IMASK_BUF11M (0x0800) +#define IMASK_BUF10M (0x0400) +#define IMASK_BUF9M (0x0200) +#define IMASK_BUF8M (0x0100) +#define IMASK_BUF7M (0x0080) +#define IMASK_BUF6M (0x0040) +#define IMASK_BUF5M (0x0020) +#define IMASK_BUF4M (0x0010) +#define IMASK_BUF3M (0x0008) +#define IMASK_BUF2M (0x0004) +#define IMASK_BUF1M (0x0002) +#define IMASK_BUF0M (0x0001) +#define IMASK_BUFnM(x) (0x1<<(x)) +#define IMASK_BUFF_ENABLE_ALL (0x1111) +#define IMASK_BUFF_DISABLE_ALL (0x0000) + +/* + * Interrupt Flag Register + */ +#define IFLAG_BUF15M (0x8000) +#define IFLAG_BUF14M (0x4000) +#define IFLAG_BUF13M (0x2000) +#define IFLAG_BUF12M (0x1000) +#define IFLAG_BUF11M (0x0800) +#define IFLAG_BUF10M (0x0400) +#define IFLAG_BUF9M (0x0200) +#define IFLAG_BUF8M (0x0100) +#define IFLAG_BUF7M (0x0080) +#define IFLAG_BUF6M (0x0040) +#define IFLAG_BUF5M (0x0020) +#define IFLAG_BUF4M (0x0010) +#define IFLAG_BUF3M (0x0008) +#define IFLAG_BUF2M (0x0004) +#define IFLAG_BUF1M (0x0002) +#define IFLAG_BUF0M (0x0001) +#define IFLAG_BUFF_SET_ALL (0xFFFF) +#define IFLAG_BUFF_CLEAR_ALL (0x0000) +#define IFLAG_BUFnM(x) (0x1<<(x)) + +/* + * Message Buffers + */ +#define MB_CNT_CODE(x) (((x)&0x0F)<<24) +#define MB_CNT_SRR (0x00400000) +#define MB_CNT_IDE (0x00200000) +#define MB_CNT_RTR (0x00100000) +#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16) +#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) +#define MB_ID_STD(x) (((x)&0x07FF)<<18) +#define MB_ID_EXT(x) ((x)&0x3FFFF) + +/********************************************************************* + * + * Edge Port Module (EPORT) + * + *********************************************************************/ + +/* Register read/write macros */ +#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) +#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) +#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) +#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) +#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) +#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) + +/* Bit definitions and macros for MCF_EPORT_EPPAR */ +#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) +#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) +#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) +#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) +#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) +#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) +#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) +#define MCF_EPORT_EPPAR_LEVEL (0) +#define MCF_EPORT_EPPAR_RISING (1) +#define MCF_EPORT_EPPAR_FALLING (2) +#define MCF_EPORT_EPPAR_BOTH (3) +#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) +#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) +#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) +#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) +#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) +#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) +#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) +#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) +#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) +#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) +#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) +#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) +#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) +#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) +#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) +#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) +#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) +#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) +#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) +#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) +#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) +#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) + +/* Bit definitions and macros for MCF_EPORT_EPDDR */ +#define MCF_EPORT_EPDDR_EPDD1 (0x02) +#define MCF_EPORT_EPDDR_EPDD2 (0x04) +#define MCF_EPORT_EPDDR_EPDD3 (0x08) +#define MCF_EPORT_EPDDR_EPDD4 (0x10) +#define MCF_EPORT_EPDDR_EPDD5 (0x20) +#define MCF_EPORT_EPDDR_EPDD6 (0x40) +#define MCF_EPORT_EPDDR_EPDD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPIER */ +#define MCF_EPORT_EPIER_EPIE1 (0x02) +#define MCF_EPORT_EPIER_EPIE2 (0x04) +#define MCF_EPORT_EPIER_EPIE3 (0x08) +#define MCF_EPORT_EPIER_EPIE4 (0x10) +#define MCF_EPORT_EPIER_EPIE5 (0x20) +#define MCF_EPORT_EPIER_EPIE6 (0x40) +#define MCF_EPORT_EPIER_EPIE7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPDR */ +#define MCF_EPORT_EPDR_EPD1 (0x02) +#define MCF_EPORT_EPDR_EPD2 (0x04) +#define MCF_EPORT_EPDR_EPD3 (0x08) +#define MCF_EPORT_EPDR_EPD4 (0x10) +#define MCF_EPORT_EPDR_EPD5 (0x20) +#define MCF_EPORT_EPDR_EPD6 (0x40) +#define MCF_EPORT_EPDR_EPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPPDR */ +#define MCF_EPORT_EPPDR_EPPD1 (0x02) +#define MCF_EPORT_EPPDR_EPPD2 (0x04) +#define MCF_EPORT_EPPDR_EPPD3 (0x08) +#define MCF_EPORT_EPPDR_EPPD4 (0x10) +#define MCF_EPORT_EPPDR_EPPD5 (0x20) +#define MCF_EPORT_EPPDR_EPPD6 (0x40) +#define MCF_EPORT_EPPDR_EPPD7 (0x80) + +/* Bit definitions and macros for MCF_EPORT_EPFR */ +#define MCF_EPORT_EPFR_EPF1 (0x02) +#define MCF_EPORT_EPFR_EPF2 (0x04) +#define MCF_EPORT_EPFR_EPF3 (0x08) +#define MCF_EPORT_EPFR_EPF4 (0x10) +#define MCF_EPORT_EPFR_EPF5 (0x20) +#define MCF_EPORT_EPFR_EPF6 (0x40) +#define MCF_EPORT_EPFR_EPF7 (0x80) + +/********************************************************************/ +#endif /* m532xsim_h */ diff --git a/arch/m68knommu/include/asm/m5407sim.h b/arch/m68knommu/include/asm/m5407sim.h new file mode 100644 index 000000000000..cc22c4a53005 --- /dev/null +++ b/arch/m68knommu/include/asm/m5407sim.h @@ -0,0 +1,157 @@ +/****************************************************************************/ + +/* + * m5407sim.h -- ColdFire 5407 System Integration Module support. + * + * (C) Copyright 2000, Lineo (www.lineo.com) + * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. + * + * Modified by David W. Miller for the MCF5307 Eval Board. + */ + +/****************************************************************************/ +#ifndef m5407sim_h +#define m5407sim_h +/****************************************************************************/ + +/* + * Define the 5407 SIM register set addresses. + */ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ +#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ +#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ +#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ +#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ +#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ +#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ +#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ +#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ +#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ + +#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ +#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ +#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ +#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ +#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ +#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ +#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ +#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ +#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ +#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ +#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ +#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ +#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ +#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ +#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ +#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ +#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ +#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ +#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ + + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ +#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ +#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ +#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ + +/* + * Macro to set IMR register. It is 32 bits on the 5407. + */ +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#define mcf_getipr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) + + +/* + * Some symbol defines for the Parallel Port Pin Assignment Register + */ +#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ + /* Clear to select par I/O */ +#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ + /* Clear to select par I/O */ + +/* + * Defines for the IRQPAR Register + */ +#define IRQ5_LEVEL4 0x80 +#define IRQ3_LEVEL6 0x40 +#define IRQ1_LEVEL2 0x20 + + +/* + * Define the Cache register flags. + */ +#define CACR_DEC 0x80000000 /* Enable data cache */ +#define CACR_DWP 0x40000000 /* Data write protection */ +#define CACR_DESB 0x20000000 /* Enable data store buffer */ +#define CACR_DDPI 0x10000000 /* Disable CPUSHL */ +#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ +#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ +#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ +#define CACR_DDCM_P 0x04000000 /* No cache, precise */ +#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ +#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ +#define CACR_BEC 0x00080000 /* Enable branch cache */ +#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ +#define CACR_IEC 0x00008000 /* Enable instruction cache */ +#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ +#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ +#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ +#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ +#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ + +#define ACR_BASE_POS 24 /* Address Base */ +#define ACR_MASK_POS 16 /* Address Mask */ +#define ACR_ENABLE 0x00008000 /* Enable address */ +#define ACR_USER 0x00000000 /* User mode access only */ +#define ACR_SUPER 0x00002000 /* Supervisor mode only */ +#define ACR_ANY 0x00004000 /* Match any access mode */ +#define ACR_CM_WT 0x00000000 /* Write through mode */ +#define ACR_CM_CP 0x00000020 /* Copyback mode */ +#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ +#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ +#define ACR_WPROTECT 0x00000004 /* Write protect */ + +/****************************************************************************/ +#endif /* m5407sim_h */ diff --git a/arch/m68knommu/include/asm/m68360.h b/arch/m68knommu/include/asm/m68360.h new file mode 100644 index 000000000000..eb7d39ef2855 --- /dev/null +++ b/arch/m68knommu/include/asm/m68360.h @@ -0,0 +1,13 @@ +#include "m68360_regs.h" +#include "m68360_pram.h" +#include "m68360_quicc.h" +#include "m68360_enet.h" + +#ifdef CONFIG_M68360 + +#define CPM_INTERRUPT 4 + +/* see MC68360 User's Manual, p. 7-377 */ +#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */ + +#endif /* CONFIG_M68360 */ diff --git a/arch/m68knommu/include/asm/m68360_enet.h b/arch/m68knommu/include/asm/m68360_enet.h new file mode 100644 index 000000000000..c36f4d059203 --- /dev/null +++ b/arch/m68knommu/include/asm/m68360_enet.h @@ -0,0 +1,177 @@ +/*********************************** + * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ + *********************************** + * + *************************************** + * Definitions for the ETHERNET controllers + *************************************** + */ + +#ifndef __ETHER_H +#define __ETHER_H + +#include "quicc_simple.h" + +/* + * transmit BD's + */ +#define T_R 0x8000 /* ready bit */ +#define E_T_PAD 0x4000 /* short frame padding */ +#define T_W 0x2000 /* wrap bit */ +#define T_I 0x1000 /* interrupt on completion */ +#define T_L 0x0800 /* last in frame */ +#define T_TC 0x0400 /* transmit CRC (when last) */ + +#define T_DEF 0x0200 /* defer indication */ +#define T_HB 0x0100 /* heartbeat */ +#define T_LC 0x0080 /* error: late collision */ +#define T_RL 0x0040 /* error: retransmission limit */ +#define T_RC 0x003c /* retry count */ +#define T_UN 0x0002 /* error: underrun */ +#define T_CSL 0x0001 /* carier sense lost */ +#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL) + +/* + * receive BD's + */ +#define R_E 0x8000 /* buffer empty */ +#define R_W 0x2000 /* wrap bit */ +#define R_I 0x1000 /* interrupt on reception */ +#define R_L 0x0800 /* last BD in frame */ +#define R_F 0x0400 /* first BD in frame */ +#define R_M 0x0100 /* received because of promisc. mode */ + +#define R_LG 0x0020 /* frame too long */ +#define R_NO 0x0010 /* non-octet aligned */ +#define R_SH 0x0008 /* short frame */ +#define R_CR 0x0004 /* receive CRC error */ +#define R_OV 0x0002 /* receive overrun */ +#define R_CL 0x0001 /* collision */ +#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL) + + +/* + * ethernet interrupts + */ +#define ETHERNET_GRA 0x0080 /* graceful stop complete */ +#define ETHERNET_TXE 0x0010 /* transmit error */ +#define ETHERNET_RXF 0x0008 /* receive frame */ +#define ETHERNET_BSY 0x0004 /* busy condition */ +#define ETHERNET_TXB 0x0002 /* transmit buffer */ +#define ETHERNET_RXB 0x0001 /* receive buffer */ + +/* + * ethernet protocol specific mode register (PSMR) + */ +#define ETHER_HBC 0x8000 /* heartbeat checking */ +#define ETHER_FC 0x4000 /* force collision */ +#define ETHER_RSH 0x2000 /* receive short frames */ +#define ETHER_IAM 0x1000 /* individual address mode */ +#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */ +#define ETHER_PRO 0x0200 /* promiscuous */ +#define ETHER_BRO 0x0100 /* broadcast address */ +#define ETHER_SBT 0x0080 /* stop backoff timer */ +#define ETHER_LPB 0x0040 /* Loop Back Mode */ +#define ETHER_SIP 0x0020 /* sample input pins */ +#define ETHER_LCW 0x0010 /* late collision window */ +#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */ +#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */ +#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */ +#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */ +#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */ +#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */ +#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */ +#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */ + +/* + * ethernet specific parameters + */ +#define CRC_WORD 4 /* Length in bytes of CRC */ +#define C_PRES 0xffffffff /* preform 32 bit CRC */ +#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */ +#define CRCEC 0x00000000 +#define ALEC 0x00000000 +#define DISFC 0x00000000 +#define PADS 0x00000000 +#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */ +#define ETH_MFLR 0x05ee /* 1518 max frame size */ +#define MINFLR 0x0040 /* Minimum frame size 64 */ +#define MAXD1 0x05ee /* Max dma count 1518 */ +#define MAXD2 0x05ee +#define GADDR1 0x00000000 /* Clear group address */ +#define GADDR2 0x00000000 +#define GADDR3 0x00000000 +#define GADDR4 0x00000000 +#define P_PER 0x00000000 /*not used */ +#define IADDR1 0x00000000 /* Individual hash table not used */ +#define IADDR2 0x00000000 +#define IADDR3 0x00000000 +#define IADDR4 0x00000000 +#define TADDR_H 0x00000000 /* clear this regs */ +#define TADDR_M 0x00000000 +#define TADDR_L 0x00000000 + +/* SCC Parameter Ram */ +#define RFCR 0x18 /* normal operation */ +#define TFCR 0x18 /* normal operation */ +#define E_MRBLR 1518 /* Max ethernet frame length */ + +/* + * ethernet specific structure + */ +typedef union { + unsigned char b[6]; + struct { + unsigned short high; + unsigned short middl; + unsigned short low; + } w; +} ETHER_ADDR; + +typedef struct { + int max_frame_length; + int promisc_mode; + int reject_broadcast; + ETHER_ADDR phys_adr; +} ETHER_SPECIFIC; + +typedef struct { + ETHER_ADDR dst_addr; + ETHER_ADDR src_addr; + unsigned short type_or_len; + unsigned char data[1]; +} ETHER_FRAME; + +#define MAX_DATALEN 1500 +typedef struct { + ETHER_ADDR dst_addr; + ETHER_ADDR src_addr; + unsigned short type_or_len; + unsigned char data[MAX_DATALEN]; + unsigned char fcs[CRC_WORD]; +} ETHER_MAX_FRAME; + + +/* + * Internal ethernet function prototypes + */ +void ether_interrupt(int scc_num); +/* mleslie: debug */ +/* static void ethernet_rx_internal(int scc_num); */ +/* static void ethernet_tx_internal(int scc_num); */ + +/* + * User callable routines prototypes (ethernet specific) + */ +void ethernet_init(int scc_number, + alloc_routine *alloc_buffer, + free_routine *free_buffer, + store_rx_buffer_routine *store_rx_buffer, + handle_tx_error_routine *handle_tx_error, + handle_rx_error_routine *handle_rx_error, + handle_lost_error_routine *handle_lost_error, + ETHER_SPECIFIC *ether_spec); +int ethernet_tx(int scc_number, void *buf, int length); + +#endif + diff --git a/arch/m68knommu/include/asm/m68360_pram.h b/arch/m68knommu/include/asm/m68360_pram.h new file mode 100644 index 000000000000..e6088bbce93d --- /dev/null +++ b/arch/m68knommu/include/asm/m68360_pram.h @@ -0,0 +1,431 @@ +/*********************************** + * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ + *********************************** + * + *************************************** + * Definitions of the parameter area RAM. + * Note that different structures are overlaid + * at the same offsets for the different modes + * of operation. + *************************************** + */ + +#ifndef __PRAM_H +#define __PRAM_H + +/* Time slot assignment table */ +#define VALID_SLOT 0x8000 +#define WRAP_SLOT 0x4000 + +/***************************************************************** + Global Multichannel parameter RAM +*****************************************************************/ +struct global_multi_pram { + /* + * Global Multichannel parameter RAM + */ + unsigned long mcbase; /* Multichannel Base pointer */ + unsigned short qmcstate; /* Multichannel Controller state */ + unsigned short mrblr; /* Maximum Receive Buffer Length */ + unsigned short tx_s_ptr; /* TSTATx Pointer */ + unsigned short rxptr; /* Current Time slot entry in TSATRx */ + unsigned short grfthr; /* Global Receive frame threshold */ + unsigned short grfcnt; /* Global Receive Frame Count */ + unsigned long intbase; /* Multichannel Base address */ + unsigned long iintptr; /* Pointer to interrupt queue */ + unsigned short rx_s_ptr; /* TSTARx Pointer */ + + unsigned short txptr; /* Current Time slot entry in TSATTx */ + unsigned long c_mask32; /* CRC Constant (debb20e3) */ + unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */ + unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */ + unsigned short c_mask16; /* CRC Constant (f0b8) */ +}; + +/***************************************************************** + Quicc32 HDLC parameter RAM +*****************************************************************/ +struct quicc32_pram { + + unsigned short tbase; /* Tx Buffer Descriptors Base Address */ + unsigned short chamr; /* Channel Mode Register */ + unsigned long tstate; /* Tx Internal State */ + unsigned long txintr; /* Tx Internal Data Pointer */ + unsigned short tbptr; /* Tx Buffer Descriptor Pointer */ + unsigned short txcntr; /* Tx Internal Byte Count */ + unsigned long tupack; /* (Tx Temp) */ + unsigned long zistate; /* Zero Insertion machine state */ + unsigned long tcrc; /* Temp Transmit CRC */ + unsigned short intmask; /* Channel's interrupt mask flags */ + unsigned short bdflags; + unsigned short rbase; /* Rx Buffer Descriptors Base Address */ + unsigned short mflr; /* Max Frame Length Register */ + unsigned long rstate; /* Rx Internal State */ + unsigned long rxintr; /* Rx Internal Data Pointer */ + unsigned short rbptr; /* Rx Buffer Descriptor Pointer */ + unsigned short rxbyc; /* Rx Internal Byte Count */ + unsigned long rpack; /* (Rx Temp) */ + unsigned long zdstate; /* Zero Deletion machine state */ + unsigned long rcrc; /* Temp Transmit CRC */ + unsigned short maxc; /* Max_length counter */ + unsigned short tmp_mb; /* Temp */ +}; + + +/***************************************************************** + HDLC parameter RAM +*****************************************************************/ + +struct hdlc_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * HDLC specific parameter RAM + */ + unsigned char RESERVED1[4]; /* Reserved area */ + unsigned long c_mask; /* CRC constant */ + unsigned long c_pres; /* CRC preset */ + unsigned short disfc; /* discarded frame counter */ + unsigned short crcec; /* CRC error counter */ + unsigned short abtsc; /* abort sequence counter */ + unsigned short nmarc; /* nonmatching address rx cnt */ + unsigned short retrc; /* frame retransmission cnt */ + unsigned short mflr; /* maximum frame length reg */ + unsigned short max_cnt; /* maximum length counter */ + unsigned short rfthr; /* received frames threshold */ + unsigned short rfcnt; /* received frames count */ + unsigned short hmask; /* user defined frm addr mask */ + unsigned short haddr1; /* user defined frm address 1 */ + unsigned short haddr2; /* user defined frm address 2 */ + unsigned short haddr3; /* user defined frm address 3 */ + unsigned short haddr4; /* user defined frm address 4 */ + unsigned short tmp; /* temp */ + unsigned short tmp_mb; /* temp */ +}; + + + +/***************************************************************** + UART parameter RAM +*****************************************************************/ + +/* + * bits in uart control characters table + */ +#define CC_INVALID 0x8000 /* control character is valid */ +#define CC_REJ 0x4000 /* don't store char in buffer */ +#define CC_CHAR 0x00ff /* control character */ + +/* UART */ +struct uart_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rx_temp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * UART specific parameter RAM + */ + unsigned char RESERVED1[8]; /* Reserved area */ + unsigned short max_idl; /* maximum idle characters */ + unsigned short idlc; /* rx idle counter (internal) */ + unsigned short brkcr; /* break count register */ + + unsigned short parec; /* Rx parity error counter */ + unsigned short frmer; /* Rx framing error counter */ + unsigned short nosec; /* Rx noise counter */ + unsigned short brkec; /* Rx break character counter */ + unsigned short brkln; /* Reaceive break length */ + + unsigned short uaddr1; /* address character 1 */ + unsigned short uaddr2; /* address character 2 */ + unsigned short rtemp; /* temp storage */ + unsigned short toseq; /* Tx out of sequence char */ + unsigned short cc[8]; /* Rx control characters */ + unsigned short rccm; /* Rx control char mask */ + unsigned short rccr; /* Rx control char register */ + unsigned short rlbc; /* Receive last break char */ +}; + + + +/***************************************************************** + BISYNC parameter RAM +*****************************************************************/ + +struct bisync_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * BISYNC specific parameter RAM + */ + unsigned char RESERVED1[4]; /* Reserved area */ + unsigned long crcc; /* CRC Constant Temp Value */ + unsigned short prcrc; /* Preset Receiver CRC-16/LRC */ + unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */ + unsigned short parec; /* Receive Parity Error Counter */ + unsigned short bsync; /* BISYNC SYNC Character */ + unsigned short bdle; /* BISYNC DLE Character */ + unsigned short cc[8]; /* Rx control characters */ + unsigned short rccm; /* Receive Control Character Mask */ +}; + +/***************************************************************** + IOM2 parameter RAM + (overlaid on tx bd[5] of SCC channel[2]) +*****************************************************************/ +struct iom2_pram { + unsigned short ci_data; /* ci data */ + unsigned short monitor_data; /* monitor data */ + unsigned short tstate; /* transmitter state */ + unsigned short rstate; /* receiver state */ +}; + +/***************************************************************** + SPI/SMC parameter RAM + (overlaid on tx bd[6,7] of SCC channel[2]) +*****************************************************************/ + +#define SPI_R 0x8000 /* Ready bit in BD */ + +struct spi_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ +}; + +struct smc_uart_pram { + unsigned short rbase; /* Rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned short max_idl; /* Maximum IDLE Characters */ + unsigned short idlc; /* Temporary IDLE Counter */ + unsigned short brkln; /* Last Rx Break Length */ + unsigned short brkec; /* Rx Break Condition Counter */ + unsigned short brkcr; /* Break Count Register (Tx) */ + unsigned short r_mask; /* Temporary bit mask */ +}; + +struct smc_trnsp_pram { + unsigned short rbase; /* rx BD Base Address */ + unsigned short tbase; /* Tx BD Base Address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned short reserved[5]; /* Reserved */ +}; + +struct idma_pram { + unsigned short ibase; /* IDMA BD Base Address */ + unsigned short ibptr; /* IDMA buffer descriptor pointer */ + unsigned long istate; /* IDMA internal state */ + unsigned long itemp; /* IDMA temp */ +}; + +struct ethernet_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * ETHERNET specific parameter RAM + */ + unsigned long c_pres; /* preset CRC */ + unsigned long c_mask; /* constant mask for CRC */ + unsigned long crcec; /* CRC error counter */ + unsigned long alec; /* alighnment error counter */ + unsigned long disfc; /* discard frame counter */ + unsigned short pads; /* short frame PAD characters */ + unsigned short ret_lim; /* retry limit threshold */ + unsigned short ret_cnt; /* retry limit counter */ + unsigned short mflr; /* maximum frame length reg */ + unsigned short minflr; /* minimum frame length reg */ + unsigned short maxd1; /* maximum DMA1 length reg */ + unsigned short maxd2; /* maximum DMA2 length reg */ + unsigned short maxd; /* rx max DMA */ + unsigned short dma_cnt; /* rx dma counter */ + unsigned short max_b; /* max bd byte count */ + unsigned short gaddr1; /* group address filter 1 */ + unsigned short gaddr2; /* group address filter 2 */ + unsigned short gaddr3; /* group address filter 3 */ + unsigned short gaddr4; /* group address filter 4 */ + unsigned long tbuf0_data0; /* save area 0 - current frm */ + unsigned long tbuf0_data1; /* save area 1 - current frm */ + unsigned long tbuf0_rba0; + unsigned long tbuf0_crc; + unsigned short tbuf0_bcnt; + union { + unsigned char b[6]; + struct { + unsigned short high; + unsigned short middl; + unsigned short low; + } w; + } paddr; + unsigned short p_per; /* persistence */ + unsigned short rfbd_ptr; /* rx first bd pointer */ + unsigned short tfbd_ptr; /* tx first bd pointer */ + unsigned short tlbd_ptr; /* tx last bd pointer */ + unsigned long tbuf1_data0; /* save area 0 - next frame */ + unsigned long tbuf1_data1; /* save area 1 - next frame */ + unsigned long tbuf1_rba0; + unsigned long tbuf1_crc; + unsigned short tbuf1_bcnt; + unsigned short tx_len; /* tx frame length counter */ + unsigned short iaddr1; /* individual address filter 1*/ + unsigned short iaddr2; /* individual address filter 2*/ + unsigned short iaddr3; /* individual address filter 3*/ + unsigned short iaddr4; /* individual address filter 4*/ + unsigned short boff_cnt; /* back-off counter */ + unsigned short taddr_h; /* temp address (MSB) */ + unsigned short taddr_m; /* temp address */ + unsigned short taddr_l; /* temp address (LSB) */ +}; + +struct transparent_pram { + /* + * SCC parameter RAM + */ + unsigned short rbase; /* RX BD base address */ + unsigned short tbase; /* TX BD base address */ + unsigned char rfcr; /* Rx function code */ + unsigned char tfcr; /* Tx function code */ + unsigned short mrblr; /* Rx buffer length */ + unsigned long rstate; /* Rx internal state */ + unsigned long rptr; /* Rx internal data pointer */ + unsigned short rbptr; /* rb BD Pointer */ + unsigned short rcount; /* Rx internal byte count */ + unsigned long rtemp; /* Rx temp */ + unsigned long tstate; /* Tx internal state */ + unsigned long tptr; /* Tx internal data pointer */ + unsigned short tbptr; /* Tx BD pointer */ + unsigned short tcount; /* Tx byte count */ + unsigned long ttemp; /* Tx temp */ + unsigned long rcrc; /* temp receive CRC */ + unsigned long tcrc; /* temp transmit CRC */ + + /* + * TRANSPARENT specific parameter RAM + */ + unsigned long crc_p; /* CRC Preset */ + unsigned long crc_c; /* CRC constant */ +}; + +struct timer_pram { + /* + * RISC timers parameter RAM + */ + unsigned short tm_base; /* RISC timer table base adr */ + unsigned short tm_ptr; /* RISC timer table pointer */ + unsigned short r_tmr; /* RISC timer mode register */ + unsigned short r_tmv; /* RISC timer valid register */ + unsigned long tm_cmd; /* RISC timer cmd register */ + unsigned long tm_cnt; /* RISC timer internal cnt */ +}; + +#endif diff --git a/arch/m68knommu/include/asm/m68360_quicc.h b/arch/m68knommu/include/asm/m68360_quicc.h new file mode 100644 index 000000000000..6d40f4d18e10 --- /dev/null +++ b/arch/m68knommu/include/asm/m68360_quicc.h @@ -0,0 +1,362 @@ +/*********************************** + * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ + *********************************** + * + *************************************** + * Definitions of QUICC memory structures + *************************************** + */ + +#ifndef __M68360_QUICC_H +#define __M68360_QUICC_H + +/* + * include registers and + * parameter ram definitions files + */ +#include +#include + + + +/* Buffer Descriptors */ +typedef struct quicc_bd { + volatile unsigned short status; + volatile unsigned short length; + volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */ +} QUICC_BD; + + +#ifdef MOTOROLA_ORIGINAL +struct user_data { + /* BASE + 0x000: user data memory */ + volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ + volatile unsigned char udata_bd[0x200]; /*user data Ucode */ + volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ + volatile unsigned char RESERVED1[0x500]; /* Reserved area */ +}; +#else +struct user_data { + /* BASE + 0x000: user data memory */ + volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/ + volatile unsigned char udata_bd1[0x200]; /* user, bds */ + volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */ + volatile unsigned char udata_bd2[0x100]; /* user, bds */ + volatile unsigned char RESERVED1[0x400]; /* Reserved area */ +}; +#endif + + +/* + * internal ram + */ +typedef struct quicc { + union { + struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */ + struct user_data u; + }ch_or_u; /* multipul or user space */ + + /* BASE + 0xc00: PARAMETER RAM */ + union { + struct scc_pram { + union { + struct hdlc_pram h; + struct uart_pram u; + struct bisync_pram b; + struct transparent_pram t; + unsigned char RESERVED66[0x70]; + } pscc; /* scc parameter area (protocol dependent) */ + union { + struct { + unsigned char RESERVED70[0x10]; + struct spi_pram spi; + unsigned char RESERVED72[0x8]; + struct timer_pram timer; + } timer_spi; + struct { + struct idma_pram idma; + unsigned char RESERVED67[0x4]; + union { + struct smc_uart_pram u; + struct smc_trnsp_pram t; + } psmc; + } idma_smc; + } pothers; + } scc; + struct ethernet_pram enet_scc; + struct global_multi_pram m; + unsigned char pr[0x100]; + } pram[4]; + + /* reserved */ + + /* BASE + 0x1000: INTERNAL REGISTERS */ + /* SIM */ + volatile unsigned long sim_mcr; /* module configuration reg */ + volatile unsigned short sim_simtr; /* module test register */ + volatile unsigned char RESERVED2[0x2]; /* Reserved area */ + volatile unsigned char sim_avr; /* auto vector reg */ + volatile unsigned char sim_rsr; /* reset status reg */ + volatile unsigned char RESERVED3[0x2]; /* Reserved area */ + volatile unsigned char sim_clkocr; /* CLCO control register */ + volatile unsigned char RESERVED62[0x3]; /* Reserved area */ + volatile unsigned short sim_pllcr; /* PLL control register */ + volatile unsigned char RESERVED63[0x2]; /* Reserved area */ + volatile unsigned short sim_cdvcr; /* Clock devider control register */ + volatile unsigned short sim_pepar; /* Port E pin assignment register */ + volatile unsigned char RESERVED64[0xa]; /* Reserved area */ + volatile unsigned char sim_sypcr; /* system protection control*/ + volatile unsigned char sim_swiv; /* software interrupt vector*/ + volatile unsigned char RESERVED6[0x2]; /* Reserved area */ + volatile unsigned short sim_picr; /* periodic interrupt control reg */ + volatile unsigned char RESERVED7[0x2]; /* Reserved area */ + volatile unsigned short sim_pitr; /* periodic interrupt timing reg */ + volatile unsigned char RESERVED8[0x3]; /* Reserved area */ + volatile unsigned char sim_swsr; /* software service */ + volatile unsigned long sim_bkar; /* breakpoint address register*/ + volatile unsigned long sim_bkcr; /* breakpoint control register*/ + volatile unsigned char RESERVED10[0x8]; /* Reserved area */ + /* MEMC */ + volatile unsigned long memc_gmr; /* Global memory register */ + volatile unsigned short memc_mstat; /* MEMC status register */ + volatile unsigned char RESERVED11[0xa]; /* Reserved area */ + volatile unsigned long memc_br0; /* base register 0 */ + volatile unsigned long memc_or0; /* option register 0 */ + volatile unsigned char RESERVED12[0x8]; /* Reserved area */ + volatile unsigned long memc_br1; /* base register 1 */ + volatile unsigned long memc_or1; /* option register 1 */ + volatile unsigned char RESERVED13[0x8]; /* Reserved area */ + volatile unsigned long memc_br2; /* base register 2 */ + volatile unsigned long memc_or2; /* option register 2 */ + volatile unsigned char RESERVED14[0x8]; /* Reserved area */ + volatile unsigned long memc_br3; /* base register 3 */ + volatile unsigned long memc_or3; /* option register 3 */ + volatile unsigned char RESERVED15[0x8]; /* Reserved area */ + volatile unsigned long memc_br4; /* base register 3 */ + volatile unsigned long memc_or4; /* option register 3 */ + volatile unsigned char RESERVED16[0x8]; /* Reserved area */ + volatile unsigned long memc_br5; /* base register 3 */ + volatile unsigned long memc_or5; /* option register 3 */ + volatile unsigned char RESERVED17[0x8]; /* Reserved area */ + volatile unsigned long memc_br6; /* base register 3 */ + volatile unsigned long memc_or6; /* option register 3 */ + volatile unsigned char RESERVED18[0x8]; /* Reserved area */ + volatile unsigned long memc_br7; /* base register 3 */ + volatile unsigned long memc_or7; /* option register 3 */ + volatile unsigned char RESERVED9[0x28]; /* Reserved area */ + /* TEST */ + volatile unsigned short test_tstmra; /* master shift a */ + volatile unsigned short test_tstmrb; /* master shift b */ + volatile unsigned short test_tstsc; /* shift count */ + volatile unsigned short test_tstrc; /* repetition counter */ + volatile unsigned short test_creg; /* control */ + volatile unsigned short test_dreg; /* destributed register */ + volatile unsigned char RESERVED58[0x404]; /* Reserved area */ + /* IDMA1 */ + volatile unsigned short idma_iccr; /* channel configuration reg*/ + volatile unsigned char RESERVED19[0x2]; /* Reserved area */ + volatile unsigned short idma1_cmr; /* dma mode reg */ + volatile unsigned char RESERVED68[0x2]; /* Reserved area */ + volatile unsigned long idma1_sapr; /* dma source addr ptr */ + volatile unsigned long idma1_dapr; /* dma destination addr ptr */ + volatile unsigned long idma1_bcr; /* dma byte count reg */ + volatile unsigned char idma1_fcr; /* function code reg */ + volatile unsigned char RESERVED20; /* Reserved area */ + volatile unsigned char idma1_cmar; /* channel mask reg */ + volatile unsigned char RESERVED21; /* Reserved area */ + volatile unsigned char idma1_csr; /* channel status reg */ + volatile unsigned char RESERVED22[0x3]; /* Reserved area */ + /* SDMA */ + volatile unsigned char sdma_sdsr; /* status reg */ + volatile unsigned char RESERVED23; /* Reserved area */ + volatile unsigned short sdma_sdcr; /* configuration reg */ + volatile unsigned long sdma_sdar; /* address reg */ + /* IDMA2 */ + volatile unsigned char RESERVED69[0x2]; /* Reserved area */ + volatile unsigned short idma2_cmr; /* dma mode reg */ + volatile unsigned long idma2_sapr; /* dma source addr ptr */ + volatile unsigned long idma2_dapr; /* dma destination addr ptr */ + volatile unsigned long idma2_bcr; /* dma byte count reg */ + volatile unsigned char idma2_fcr; /* function code reg */ + volatile unsigned char RESERVED24; /* Reserved area */ + volatile unsigned char idma2_cmar; /* channel mask reg */ + volatile unsigned char RESERVED25; /* Reserved area */ + volatile unsigned char idma2_csr; /* channel status reg */ + volatile unsigned char RESERVED26[0x7]; /* Reserved area */ + /* Interrupt Controller */ + volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/ + volatile unsigned long intr_cipr; /* CP interrupt pending reg */ + volatile unsigned long intr_cimr; /* CP interrupt mask reg */ + volatile unsigned long intr_cisr; /* CP interrupt in service reg*/ + /* Parallel I/O */ + volatile unsigned short pio_padir; /* port A data direction reg */ + volatile unsigned short pio_papar; /* port A pin assignment reg */ + volatile unsigned short pio_paodr; /* port A open drain reg */ + volatile unsigned short pio_padat; /* port A data register */ + volatile unsigned char RESERVED28[0x8]; /* Reserved area */ + volatile unsigned short pio_pcdir; /* port C data direction reg*/ + volatile unsigned short pio_pcpar; /* port C pin assignment reg*/ + volatile unsigned short pio_pcso; /* port C special options */ + volatile unsigned short pio_pcdat; /* port C data register */ + volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */ + volatile unsigned char RESERVED29[0x16]; /* Reserved area */ + /* Timer */ + volatile unsigned short timer_tgcr; /* timer global configuration reg */ + volatile unsigned char RESERVED30[0xe]; /* Reserved area */ + volatile unsigned short timer_tmr1; /* timer 1 mode reg */ + volatile unsigned short timer_tmr2; /* timer 2 mode reg */ + volatile unsigned short timer_trr1; /* timer 1 referance reg */ + volatile unsigned short timer_trr2; /* timer 2 referance reg */ + volatile unsigned short timer_tcr1; /* timer 1 capture reg */ + volatile unsigned short timer_tcr2; /* timer 2 capture reg */ + volatile unsigned short timer_tcn1; /* timer 1 counter reg */ + volatile unsigned short timer_tcn2; /* timer 2 counter reg */ + volatile unsigned short timer_tmr3; /* timer 3 mode reg */ + volatile unsigned short timer_tmr4; /* timer 4 mode reg */ + volatile unsigned short timer_trr3; /* timer 3 referance reg */ + volatile unsigned short timer_trr4; /* timer 4 referance reg */ + volatile unsigned short timer_tcr3; /* timer 3 capture reg */ + volatile unsigned short timer_tcr4; /* timer 4 capture reg */ + volatile unsigned short timer_tcn3; /* timer 3 counter reg */ + volatile unsigned short timer_tcn4; /* timer 4 counter reg */ + volatile unsigned short timer_ter1; /* timer 1 event reg */ + volatile unsigned short timer_ter2; /* timer 2 event reg */ + volatile unsigned short timer_ter3; /* timer 3 event reg */ + volatile unsigned short timer_ter4; /* timer 4 event reg */ + volatile unsigned char RESERVED34[0x8]; /* Reserved area */ + /* CP */ + volatile unsigned short cp_cr; /* command register */ + volatile unsigned char RESERVED35[0x2]; /* Reserved area */ + volatile unsigned short cp_rccr; /* main configuration reg */ + volatile unsigned char RESERVED37; /* Reserved area */ + volatile unsigned char cp_rmds; /* development support status reg */ + volatile unsigned long cp_rmdr; /* development support control reg */ + volatile unsigned short cp_rctr1; /* ram break register 1 */ + volatile unsigned short cp_rctr2; /* ram break register 2 */ + volatile unsigned short cp_rctr3; /* ram break register 3 */ + volatile unsigned short cp_rctr4; /* ram break register 4 */ + volatile unsigned char RESERVED59[0x2]; /* Reserved area */ + volatile unsigned short cp_rter; /* RISC timers event reg */ + volatile unsigned char RESERVED38[0x2]; /* Reserved area */ + volatile unsigned short cp_rtmr; /* RISC timers mask reg */ + volatile unsigned char RESERVED39[0x14]; /* Reserved area */ + /* BRG */ + union { + volatile unsigned long l; + struct { + volatile unsigned short BRGC_RESERV:14; + volatile unsigned short rst:1; + volatile unsigned short en:1; + volatile unsigned short extc:2; + volatile unsigned short atb:1; + volatile unsigned short cd:12; + volatile unsigned short div16:1; + } b; + } brgc[4]; /* BRG1-BRG4 configuration regs*/ + /* SCC registers */ + struct scc_regs { + union { + struct { + /* Low word. */ + volatile unsigned short GSMR_RESERV2:1; + volatile unsigned short edge:2; + volatile unsigned short tci:1; + volatile unsigned short tsnc:2; + volatile unsigned short rinv:1; + volatile unsigned short tinv:1; + volatile unsigned short tpl:3; + volatile unsigned short tpp:2; + volatile unsigned short tend:1; + volatile unsigned short tdcr:2; + volatile unsigned short rdcr:2; + volatile unsigned short renc:3; + volatile unsigned short tenc:3; + volatile unsigned short diag:2; + volatile unsigned short enr:1; + volatile unsigned short ent:1; + volatile unsigned short mode:4; + /* High word. */ + volatile unsigned short GSMR_RESERV1:14; + volatile unsigned short pri:1; + volatile unsigned short gde:1; + volatile unsigned short tcrc:2; + volatile unsigned short revd:1; + volatile unsigned short trx:1; + volatile unsigned short ttx:1; + volatile unsigned short cdp:1; + volatile unsigned short ctsp:1; + volatile unsigned short cds:1; + volatile unsigned short ctss:1; + volatile unsigned short tfl:1; + volatile unsigned short rfw:1; + volatile unsigned short txsy:1; + volatile unsigned short synl:2; + volatile unsigned short rtsm:1; + volatile unsigned short rsyn:1; + } b; + struct { + volatile unsigned long low; + volatile unsigned long high; + } w; + } scc_gsmr; /* SCC general mode reg */ + volatile unsigned short scc_psmr; /* protocol specific mode reg */ + volatile unsigned char RESERVED42[0x2]; /* Reserved area */ + volatile unsigned short scc_todr; /* SCC transmit on demand */ + volatile unsigned short scc_dsr; /* SCC data sync reg */ + volatile unsigned short scc_scce; /* SCC event reg */ + volatile unsigned char RESERVED43[0x2];/* Reserved area */ + volatile unsigned short scc_sccm; /* SCC mask reg */ + volatile unsigned char RESERVED44[0x1];/* Reserved area */ + volatile unsigned char scc_sccs; /* SCC status reg */ + volatile unsigned char RESERVED45[0x8]; /* Reserved area */ + } scc_regs[4]; + /* SMC */ + struct smc_regs { + volatile unsigned char RESERVED46[0x2]; /* Reserved area */ + volatile unsigned short smc_smcmr; /* SMC mode reg */ + volatile unsigned char RESERVED60[0x2]; /* Reserved area */ + volatile unsigned char smc_smce; /* SMC event reg */ + volatile unsigned char RESERVED47[0x3]; /* Reserved area */ + volatile unsigned char smc_smcm; /* SMC mask reg */ + volatile unsigned char RESERVED48[0x5]; /* Reserved area */ + } smc_regs[2]; + /* SPI */ + volatile unsigned short spi_spmode; /* SPI mode reg */ + volatile unsigned char RESERVED51[0x4]; /* Reserved area */ + volatile unsigned char spi_spie; /* SPI event reg */ + volatile unsigned char RESERVED52[0x3]; /* Reserved area */ + volatile unsigned char spi_spim; /* SPI mask reg */ + volatile unsigned char RESERVED53[0x2]; /* Reserved area */ + volatile unsigned char spi_spcom; /* SPI command reg */ + volatile unsigned char RESERVED54[0x4]; /* Reserved area */ + /* PIP */ + volatile unsigned short pip_pipc; /* pip configuration reg */ + volatile unsigned char RESERVED65[0x2]; /* Reserved area */ + volatile unsigned short pip_ptpr; /* pip timing parameters reg */ + volatile unsigned long pip_pbdir; /* port b data direction reg */ + volatile unsigned long pip_pbpar; /* port b pin assignment reg */ + volatile unsigned long pip_pbodr; /* port b open drain reg */ + volatile unsigned long pip_pbdat; /* port b data reg */ + volatile unsigned char RESERVED71[0x18]; /* Reserved area */ + /* Serial Interface */ + volatile unsigned long si_simode; /* SI mode register */ + volatile unsigned char si_sigmr; /* SI global mode register */ + volatile unsigned char RESERVED55; /* Reserved area */ + volatile unsigned char si_sistr; /* SI status register */ + volatile unsigned char si_sicmr; /* SI command register */ + volatile unsigned char RESERVED56[0x4]; /* Reserved area */ + volatile unsigned long si_sicr; /* SI clock routing */ + volatile unsigned long si_sirp; /* SI ram pointers */ + volatile unsigned char RESERVED57[0xc]; /* Reserved area */ + volatile unsigned short si_siram[0x80]; /* SI routing ram */ +} QUICC; + +#endif + +/* + * Local variables: + * c-indent-level: 4 + * c-basic-offset: 4 + * tab-width: 4 + * End: + */ diff --git a/arch/m68knommu/include/asm/m68360_regs.h b/arch/m68knommu/include/asm/m68360_regs.h new file mode 100644 index 000000000000..d57217ca4f27 --- /dev/null +++ b/arch/m68knommu/include/asm/m68360_regs.h @@ -0,0 +1,408 @@ +/*********************************** + * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $ + *********************************** + * + *************************************** + * Definitions of the QUICC registers + *************************************** + */ + +#ifndef __REGISTERS_H +#define __REGISTERS_H + +#define CLEAR_BIT(x, bit) x =bit + +/***************************************************************** + Command Register +*****************************************************************/ + +/* bit fields within command register */ +#define SOFTWARE_RESET 0x8000 +#define CMD_OPCODE 0x0f00 +#define CMD_CHANNEL 0x00f0 +#define CMD_FLAG 0x0001 + +/* general command opcodes */ +#define INIT_RXTX_PARAMS 0x0000 +#define INIT_RX_PARAMS 0x0100 +#define INIT_TX_PARAMS 0x0200 +#define ENTER_HUNT_MODE 0x0300 +#define STOP_TX 0x0400 +#define GR_STOP_TX 0x0500 +#define RESTART_TX 0x0600 +#define CLOSE_RX_BD 0x0700 +#define SET_ENET_GROUP 0x0800 +#define RESET_ENET_GROUP 0x0900 + +/* quicc32 CP commands */ +#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */ +#define ENTER_HUNT_MODE_32 0x1e00 + +/* quicc32 mask/event SCC register */ +#define GOV 0x01 +#define GUN 0x02 +#define GINT 0x04 +#define IQOV 0x08 + + +/* Timer commands */ +#define SET_TIMER 0x0800 + +/* Multi channel Interrupt structure */ +#define INTR_VALID 0x8000 /* Valid interrupt entry */ +#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */ +#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */ +#define INTR_MASK_BITS 0x383f + +/* + * General SCC mode register (GSMR) + */ + +#define MODE_HDLC 0x0 +#define MODE_APPLE_TALK 0x2 +#define MODE_SS7 0x3 +#define MODE_UART 0x4 +#define MODE_PROFIBUS 0x5 +#define MODE_ASYNC_HDLC 0x6 +#define MODE_V14 0x7 +#define MODE_BISYNC 0x8 +#define MODE_DDCMP 0x9 +#define MODE_MULTI_CHANNEL 0xa +#define MODE_ETHERNET 0xc + +#define DIAG_NORMAL 0x0 +#define DIAG_LOCAL_LPB 0x1 +#define DIAG_AUTO_ECHO 0x2 +#define DIAG_LBP_ECHO 0x3 + +/* For RENC and TENC fields in GSMR */ +#define ENC_NRZ 0x0 +#define ENC_NRZI 0x1 +#define ENC_FM0 0x2 +#define ENC_MANCH 0x4 +#define ENC_DIFF_MANC 0x6 + +/* For TDCR and RDCR fields in GSMR */ +#define CLOCK_RATE_1 0x0 +#define CLOCK_RATE_8 0x1 +#define CLOCK_RATE_16 0x2 +#define CLOCK_RATE_32 0x3 + +#define TPP_00 0x0 +#define TPP_10 0x1 +#define TPP_01 0x2 +#define TPP_11 0x3 + +#define TPL_NO 0x0 +#define TPL_8 0x1 +#define TPL_16 0x2 +#define TPL_32 0x3 +#define TPL_48 0x4 +#define TPL_64 0x5 +#define TPL_128 0x6 + +#define TSNC_INFINITE 0x0 +#define TSNC_14_65 0x1 +#define TSNC_4_15 0x2 +#define TSNC_3_1 0x3 + +#define EDGE_BOTH 0x0 +#define EDGE_POS 0x1 +#define EDGE_NEG 0x2 +#define EDGE_NO 0x3 + +#define SYNL_NO 0x0 +#define SYNL_4 0x1 +#define SYNL_8 0x2 +#define SYNL_16 0x3 + +#define TCRC_CCITT16 0x0 +#define TCRC_CRC16 0x1 +#define TCRC_CCITT32 0x2 + + +/***************************************************************** + TODR (Transmit on demand) Register +*****************************************************************/ +#define TODR_TOD 0x8000 /* Transmit on demand */ + + +/***************************************************************** + CICR register settings +*****************************************************************/ + +/* note that relative irq priorities of the SCCs can be reordered + * if desired - see p. 7-377 of the MC68360UM */ +#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ +#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ +#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ +#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ + +#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ +#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ +#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */ +#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ + + +/***************************************************************** + Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379) +*****************************************************************/ + +#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */ +#define INTR_SCC1 0x40000000 /* SCC port 1 */ +#define INTR_SCC2 0x20000000 /* SCC port 2 */ +#define INTR_SCC3 0x10000000 /* SCC port 3 */ +#define INTR_SCC4 0x08000000 /* SCC port 4 */ +#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */ +#define INTR_TIMER1 0x02000000 /* timer 1 */ +#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */ +#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */ +#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */ +#define INTR_DMA1 0x00200000 /* idma 1 */ +#define INTR_DMA2 0x00100000 /* idma 2 */ +#define INTR_TIMER2 0x00040000 /* timer 2 */ +#define INTR_CP_TIMER 0x00020000 /* CP timer */ +#define INTR_PIP_STATUS 0x00010000 /* PIP status */ +#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */ +#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */ +#define INTR_TIMER3 0x00001000 /* timer 3 */ +#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */ +#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */ +#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */ +#define INTR_TIMER4 0x00000080 /* timer 4 */ +#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */ +#define INTR_SCP 0x00000020 /* SCP */ +#define INTR_SMC1 0x00000010 /* SMC 1 */ +#define INTR_SMC2 0x00000008 /* SMC 2 */ +#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */ +#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */ +#define INTR_ERR 0x00000001 /* error */ + + +/***************************************************************** + CPM Interrupt vector encodings (MC68360UM p. 7-376) +*****************************************************************/ + +#define CPMVEC_NR 32 +#define CPMVEC_PIO_PC0 0x1f +#define CPMVEC_SCC1 0x1e +#define CPMVEC_SCC2 0x1d +#define CPMVEC_SCC3 0x1c +#define CPMVEC_SCC4 0x1b +#define CPMVEC_PIO_PC1 0x1a +#define CPMVEC_TIMER1 0x19 +#define CPMVEC_PIO_PC2 0x18 +#define CPMVEC_PIO_PC3 0x17 +#define CPMVEC_SDMA_CB_ERR 0x16 +#define CPMVEC_IDMA1 0x15 +#define CPMVEC_IDMA2 0x14 +#define CPMVEC_RESERVED3 0x13 +#define CPMVEC_TIMER2 0x12 +#define CPMVEC_RISCTIMER 0x11 +#define CPMVEC_RESERVED2 0x10 +#define CPMVEC_PIO_PC4 0x0f +#define CPMVEC_PIO_PC5 0x0e +#define CPMVEC_TIMER3 0x0c +#define CPMVEC_PIO_PC6 0x0b +#define CPMVEC_PIO_PC7 0x0a +#define CPMVEC_PIO_PC8 0x09 +#define CPMVEC_RESERVED1 0x08 +#define CPMVEC_TIMER4 0x07 +#define CPMVEC_PIO_PC9 0x06 +#define CPMVEC_SPI 0x05 +#define CPMVEC_SMC1 0x04 +#define CPMVEC_SMC2 0x03 +#define CPMVEC_PIO_PC10 0x02 +#define CPMVEC_PIO_PC11 0x01 +#define CPMVEC_ERROR 0x00 + +/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */ +/* #define CPMVEC_SCC1 ((ushort)0x1e) */ +/* #define CPMVEC_SCC2 ((ushort)0x1d) */ +/* #define CPMVEC_SCC3 ((ushort)0x1c) */ +/* #define CPMVEC_SCC4 ((ushort)0x1b) */ +/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */ +/* #define CPMVEC_TIMER1 ((ushort)0x19) */ +/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */ +/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */ +/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ +/* #define CPMVEC_IDMA1 ((ushort)0x15) */ +/* #define CPMVEC_IDMA2 ((ushort)0x14) */ +/* #define CPMVEC_RESERVED3 ((ushort)0x13) */ +/* #define CPMVEC_TIMER2 ((ushort)0x12) */ +/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ +/* #define CPMVEC_RESERVED2 ((ushort)0x10) */ +/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */ +/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */ +/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ +/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */ +/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */ +/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */ +/* #define CPMVEC_RESERVED1 ((ushort)0x08) */ +/* #define CPMVEC_TIMER4 ((ushort)0x07) */ +/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */ +/* #define CPMVEC_SPI ((ushort)0x05) */ +/* #define CPMVEC_SMC1 ((ushort)0x04) */ +/* #define CPMVEC_SMC2 ((ushort)0x03) */ +/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */ +/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */ +/* #define CPMVEC_ERROR ((ushort)0x00) */ + + +/***************************************************************** + * PIO control registers + *****************************************************************/ + +/* Port A - See 360UM p. 7-358 + * + * Note that most of these pins have alternate functions + */ + + +/* The macros are nice, but there are all sorts of references to 1-indexed + * facilities on the 68360... */ +/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */ +/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */ + +#define PA_RXD1 ((ushort)0x0001) +#define PA_TXD1 ((ushort)0x0002) +#define PA_RXD2 ((ushort)0x0004) +#define PA_TXD2 ((ushort)0x0008) +#define PA_RXD3 ((ushort)0x0010) +#define PA_TXD3 ((ushort)0x0020) +#define PA_RXD4 ((ushort)0x0040) +#define PA_TXD4 ((ushort)0x0080) + +#define PA_CLK1 ((ushort)0x0100) +#define PA_CLK2 ((ushort)0x0200) +#define PA_CLK3 ((ushort)0x0400) +#define PA_CLK4 ((ushort)0x0800) +#define PA_CLK5 ((ushort)0x1000) +#define PA_CLK6 ((ushort)0x2000) +#define PA_CLK7 ((ushort)0x4000) +#define PA_CLK8 ((ushort)0x8000) + + +/* Port B - See 360UM p. 7-362 + */ + + +/* Port C - See 360UM p. 7-365 + */ + +#define PC_RTS1 ((ushort)0x0001) +#define PC_RTS2 ((ushort)0x0002) +#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */ +#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */ + +#define PC_CTS1 ((ushort)0x0010) +#define PC_CD1 ((ushort)0x0020) +#define PC_CTS2 ((ushort)0x0040) +#define PC_CD2 ((ushort)0x0080) +#define PC_CTS3 ((ushort)0x0100) +#define PC_CD3 ((ushort)0x0200) +#define PC_CTS4 ((ushort)0x0400) +#define PC_CD4 ((ushort)0x0800) + + + +/***************************************************************** + chip select option register +*****************************************************************/ +#define DTACK 0xe000 +#define ADR_MASK 0x1ffc +#define RDWR_MASK 0x0002 +#define FC_MASK 0x0001 + +/***************************************************************** + tbase and rbase registers +*****************************************************************/ +#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \ + (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase)) +#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \ + (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase)) +#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ + (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr)) +#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ + (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr)) +#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \ + ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) +#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \ + ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) +#define INCREASE_TBD(bd,quicc,pram) { \ + if((bd)->status & T_W) \ + (bd) = TBD_ADDR(quicc,pram); \ + else \ + (bd)++; \ +} +#define DECREASE_TBD(bd,quicc,pram) { \ + if ((bd) == TBD_ADDR(quicc, pram)) \ + while (!((bd)->status & T_W)) \ + (bd)++; \ + else \ + (bd)--; \ +} +#define INCREASE_RBD(bd,quicc,pram) { \ + if((bd)->status & R_W) \ + (bd) = RBD_ADDR(quicc,pram); \ + else \ + (bd)++; \ +} +#define DECREASE_RBD(bd,quicc,pram) { \ + if ((bd) == RBD_ADDR(quicc, pram)) \ + while (!((bd)->status & T_W)) \ + (bd)++; \ + else \ + (bd)--; \ +} + +/***************************************************************** + Macros for Multi channel +*****************************************************************/ +#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page]) +#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase) +#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \ + (&(quicc->ch_or_u.ch_pram_tbl[channel]))) +#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ + (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase))) +#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ + (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase))) +#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ + (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr))) +#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ + (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr))) +#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ + CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \ + ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) +#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ + CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \ + ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) + +#define INCREASE_TBD_32(bd,quicc,page,channel) { \ + if((bd)->status & T_W) \ + (bd) = TBD_32_ADDR(quicc,page,channel); \ + else \ + (bd)++; \ +} +#define DECREASE_TBD_32(bd,quicc,page,channel) { \ + if ((bd) == TBD_32_ADDR(quicc, page,channel)) \ + while (!((bd)->status & T_W)) \ + (bd)++; \ + else \ + (bd)--; \ +} +#define INCREASE_RBD_32(bd,quicc,page,channel) { \ + if((bd)->status & R_W) \ + (bd) = RBD_32_ADDR(quicc,page,channel); \ + else \ + (bd)++; \ +} +#define DECREASE_RBD_32(bd,quicc,page,channel) { \ + if ((bd) == RBD_32_ADDR(quicc, page,channel)) \ + while (!((bd)->status & T_W)) \ + (bd)++; \ + else \ + (bd)--; \ +} + +#endif diff --git a/arch/m68knommu/include/asm/machdep.h b/arch/m68knommu/include/asm/machdep.h new file mode 100644 index 000000000000..de9f47a51cc2 --- /dev/null +++ b/arch/m68knommu/include/asm/machdep.h @@ -0,0 +1,26 @@ +#ifndef _M68KNOMMU_MACHDEP_H +#define _M68KNOMMU_MACHDEP_H + +#include + +/* Hardware clock functions */ +extern void hw_timer_init(void); +extern unsigned long hw_timer_offset(void); + +extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); + +/* Machine dependent time handling */ +extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, + int *min, int *sec); +extern int (*mach_set_clock_mmss)(unsigned long); + +/* machine dependent power off functions */ +extern void (*mach_reset)( void ); +extern void (*mach_halt)( void ); +extern void (*mach_power_off)( void ); + +extern void config_BSP(char *command, int len); + +extern void do_IRQ(int irq, struct pt_regs *fp); + +#endif /* _M68KNOMMU_MACHDEP_H */ diff --git a/arch/m68knommu/include/asm/math-emu.h b/arch/m68knommu/include/asm/math-emu.h new file mode 100644 index 000000000000..7e7090517b72 --- /dev/null +++ b/arch/m68knommu/include/asm/math-emu.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/mc146818rtc.h b/arch/m68knommu/include/asm/mc146818rtc.h new file mode 100644 index 000000000000..907a0481a140 --- /dev/null +++ b/arch/m68knommu/include/asm/mc146818rtc.h @@ -0,0 +1,9 @@ +/* + * Machine dependent access functions for RTC registers. + */ +#ifndef _M68KNOMMU_MC146818RTC_H +#define _M68KNOMMU_MC146818RTC_H + +/* empty include file to satisfy the include in genrtc.c/ide-geometry.c */ + +#endif /* _M68KNOMMU_MC146818RTC_H */ diff --git a/arch/m68knommu/include/asm/mcfcache.h b/arch/m68knommu/include/asm/mcfcache.h new file mode 100644 index 000000000000..c042634fadaa --- /dev/null +++ b/arch/m68knommu/include/asm/mcfcache.h @@ -0,0 +1,150 @@ +/****************************************************************************/ + +/* + * mcfcache.h -- ColdFire CPU cache support code + * + * (C) Copyright 2004, Greg Ungerer + */ + +/****************************************************************************/ +#ifndef __M68KNOMMU_MCFCACHE_H +#define __M68KNOMMU_MCFCACHE_H +/****************************************************************************/ + + +/* + * The different ColdFire families have different cache arrangments. + * Everything from a small instruction only cache, to configurable + * data and/or instruction cache, to unified instruction/data, to + * harvard style separate instruction and data caches. + */ + +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) +/* + * Simple version 2 core cache. These have instruction cache only, + * we just need to invalidate it and enable it. + */ +.macro CACHE_ENABLE + movel #0x01000000,%d0 /* invalidate cache cmd */ + movec %d0,%CACR /* do invalidate cache */ + movel #0x80000100,%d0 /* setup cache mask */ + movec %d0,%CACR /* enable cache */ +.endm +#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ + +#if defined(CONFIG_M523x) || defined(CONFIG_M527x) +/* + * New version 2 cores have a configurable split cache arrangement. + * For now I am just enabling instruction cache - but ultimately I + * think a split instruction/data cache would be better. + */ +.macro CACHE_ENABLE + movel #0x01400000,%d0 + movec %d0,%CACR /* invalidate cache */ + nop + movel #0x0000c000,%d0 /* set SDRAM cached only */ + movec %d0,%ACR0 + movel #0x00000000,%d0 /* no other regions cached */ + movec %d0,%ACR1 + movel #0x80400100,%d0 /* configure cache */ + movec %d0,%CACR /* enable cache */ + nop +.endm +#endif /* CONFIG_M523x || CONFIG_M527x */ + +#if defined(CONFIG_M528x) +.macro CACHE_ENABLE + nop + movel #0x01000000, %d0 + movec %d0, %CACR /* Invalidate cache */ + nop + movel #0x0000c020, %d0 /* Set SDRAM cached only */ + movec %d0, %ACR0 + movel #0x00000000, %d0 /* No other regions cached */ + movec %d0, %ACR1 + movel #0x80000200, %d0 /* Setup cache mask */ + movec %d0, %CACR /* Enable cache */ + nop +.endm +#endif /* CONFIG_M528x */ + +#if defined(CONFIG_M5249) || defined(CONFIG_M5307) +/* + * The version 3 core cache. Oddly enough the version 2 core 5249 + * has the same SDRAM and cache setup as the version 3 cores. + * This is a single unified instruction/data cache. + */ +.macro CACHE_ENABLE + movel #0x01000000,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop +#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) + movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ +#else + movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ +#endif + movec %d0,%ACR0 + movel #0x00000000,%d0 /* no other regions cached */ + movec %d0,%ACR1 + movel #0xa0000200,%d0 /* enable cache */ + movec %d0,%CACR + nop +.endm +#endif /* CONFIG_M5249 || CONFIG_M5307 */ + +#if defined(CONFIG_M532x) +.macro CACHE_ENABLE + movel #0x01000000,%d0 /* invalidate cache cmd */ + movec %d0,%CACR /* do invalidate cache */ + nop + movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ + movec %d0,%ACR0 + movel #0x00000000,%d0 /* no other regions cached */ + movec %d0,%ACR1 + movel #0x80000200,%d0 /* setup cache mask */ + movec %d0,%CACR /* enable cache */ + nop +.endm +#endif /* CONFIG_M532x */ + +#if defined(CONFIG_M5407) +/* + * Version 4 cores have a true harvard style separate instruction + * and data cache. Invalidate and enable cache, also enable write + * buffers and branch accelerator. + */ +.macro CACHE_ENABLE + movel #0x01040100,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + movel #0x000fc000,%d0 /* set SDRAM cached only */ + movec %d0, %ACR0 + movel #0x00000000,%d0 /* no other regions cached */ + movec %d0, %ACR1 + movel #0x000fc000,%d0 /* set SDRAM cached only */ + movec %d0, %ACR2 + movel #0x00000000,%d0 /* no other regions cached */ + movec %d0, %ACR3 + movel #0xb6088400,%d0 /* enable caches */ + movec %d0,%CACR + nop +.endm +#endif /* CONFIG_M5407 */ + +#if defined(CONFIG_M520x) +.macro CACHE_ENABLE + move.l #0x01000000,%d0 /* invalidate whole cache */ + movec %d0,%CACR + nop + move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ + movec %d0,%ACR0 + move.l #0x00000000,%d0 /* no other regions cached */ + movec %d0,%ACR1 + move.l #0x80400000,%d0 /* enable 8K instruction cache */ + movec %d0,%CACR + nop +.endm +#endif /* CONFIG_M520x */ + +/****************************************************************************/ +#endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/arch/m68knommu/include/asm/mcfdma.h b/arch/m68knommu/include/asm/mcfdma.h new file mode 100644 index 000000000000..705c52c79cd8 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfdma.h @@ -0,0 +1,144 @@ +/****************************************************************************/ + +/* + * mcfdma.h -- Coldfire internal DMA support defines. + * + * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) + */ + +/****************************************************************************/ +#ifndef mcfdma_h +#define mcfdma_h +/****************************************************************************/ + + +/* + * Get address specific defines for this Coldfire member. + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ +#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ +#elif defined(CONFIG_M5272) +#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ +#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +/* These are relative to the IPSBAR, not MBAR */ +#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ +#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ +#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ +#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ +#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ +#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ +#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ +#endif + + +#if !defined(CONFIG_M5272) + +/* + * Define the DMA register set addresses. + * Note: these are longword registers, use unsigned long as data type + */ +#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ +#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ +/* these are word registers, use unsigned short data type */ +#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ +#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ +/* these are byte registers, use unsiged char data type */ +#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ +#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ + +/* + * Bit definitions for the DMA Control Register (DCR). + */ +#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ +#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ +#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ +#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ +#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ +#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ +#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ +#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ +#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ +#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ +#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ +#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ +#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ +#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ +#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ +#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ +#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ +#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ +#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ +#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ +#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ +#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ +#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ +#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ +#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ +#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ +#define MCFDMA_DCR_START 0x0001 /* Start transfer */ + +/* + * Bit definitions for the DMA Status Register (DSR). + */ +#define MCFDMA_DSR_CE 0x40 /* Config error */ +#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ +#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ +#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ +#define MCFDMA_DSR_BSY 0x02 /* Busy */ +#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ + +#else /* This is an MCF5272 */ + +#define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ +#define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ +#define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ +#define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ +#define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ + +/* Bit definitions for the DMA Mode Register (DMR) */ +#define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ +#define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ +#define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ +#define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ +#define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ +#define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ +#define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ +#define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ +#define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ +#define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ +#define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ +#define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ +#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ +#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ +#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ +#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ +#define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ +#define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ +#define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ +#define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ +#define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ +#define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ +#define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ +#define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ +#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ +#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ +#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ +#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ + +/* Bit definitions for the DMA interrupt register (DIR) */ +#define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ +#define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ +#define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ +#define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ +#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ +#define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ +#define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ +#define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ + +#endif /* !defined(CONFIG_M5272) */ + +/****************************************************************************/ +#endif /* mcfdma_h */ diff --git a/arch/m68knommu/include/asm/mcfmbus.h b/arch/m68knommu/include/asm/mcfmbus.h new file mode 100644 index 000000000000..319899c47a2c --- /dev/null +++ b/arch/m68knommu/include/asm/mcfmbus.h @@ -0,0 +1,77 @@ +/****************************************************************************/ + +/* + * mcfmbus.h -- Coldfire MBUS support defines. + * + * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) + */ + +/****************************************************************************/ + + +#ifndef mcfmbus_h +#define mcfmbus_h + + +#define MCFMBUS_BASE 0x280 +#define MCFMBUS_IRQ_VECTOR 0x19 +#define MCFMBUS_IRQ 0x1 +#define MCFMBUS_CLK 0x3f +#define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/ +#define MCFMBUS_ADDRESS 0x01 + + +/* +* Define the 5307 MBUS register set addresses +*/ + +#define MCFMBUS_MADR 0x00 +#define MCFMBUS_MFDR 0x04 +#define MCFMBUS_MBCR 0x08 +#define MCFMBUS_MBSR 0x0C +#define MCFMBUS_MBDR 0x10 + + +#define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/ + +#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/ + +/* +* Define bit flags in Control Register +*/ + +#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */ +#define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ +#define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */ +#define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */ +#define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ +#define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */ + +/* +* Define bit flags in Status Register +*/ + +#define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */ +#define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */ +#define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */ +#define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */ +#define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */ +#define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */ +#define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */ + +/* +* Define bit flags in DATA I/O Register +*/ + +#define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */ + +#define MBUSIOCSCLOCK 1 +#define MBUSIOCGCLOCK 2 +#define MBUSIOCSADDR 3 +#define MBUSIOCGADDR 4 +#define MBUSIOCSSLADDR 5 +#define MBUSIOCGSLADDR 6 +#define MBUSIOCSSUBADDR 7 +#define MBUSIOCGSUBADDR 8 + +#endif diff --git a/arch/m68knommu/include/asm/mcfne.h b/arch/m68knommu/include/asm/mcfne.h new file mode 100644 index 000000000000..431f63aadd0e --- /dev/null +++ b/arch/m68knommu/include/asm/mcfne.h @@ -0,0 +1,325 @@ +/****************************************************************************/ + +/* + * mcfne.h -- NE2000 in ColdFire eval boards. + * + * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo (www.lineo.com) + * (C) Copyright 2001, SnapGear (www.snapgear.com) + * + * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board + * + * Hacked support for m5206e Cadre III evaluation board + * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999 + */ + +/****************************************************************************/ +#ifndef mcfne_h +#define mcfne_h +/****************************************************************************/ + + +/* + * Support for NE2000 clones devices in ColdFire based boards. + * Not all boards address these parts the same way, some use a + * direct addressing method, others use a side-band address space + * to access odd address registers, some require byte swapping + * others do not. + */ +#define BSWAP(w) (((w) << 8) | ((w) >> 8)) +#define RSWAP(w) (w) + + +/* + * Define the basic hardware resources of NE2000 boards. + */ + +#if defined(CONFIG_ARN5206) +#define NE2000_ADDR 0x40000300 +#define NE2000_ODDOFFSET 0x00010000 +#define NE2000_IRQ_VECTOR 0xf0 +#define NE2000_IRQ_PRIORITY 2 +#define NE2000_IRQ_LEVEL 4 +#define NE2000_BYTE volatile unsigned short +#endif + +#if defined(CONFIG_M5206eC3) +#define NE2000_ADDR 0x40000300 +#define NE2000_ODDOFFSET 0x00010000 +#define NE2000_IRQ_VECTOR 0x1c +#define NE2000_IRQ_PRIORITY 2 +#define NE2000_IRQ_LEVEL 4 +#define NE2000_BYTE volatile unsigned short +#endif + +#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) +#define NE2000_ADDR 0x30000300 +#define NE2000_IRQ_VECTOR 25 +#define NE2000_IRQ_PRIORITY 1 +#define NE2000_IRQ_LEVEL 3 +#define NE2000_BYTE volatile unsigned char +#endif + +#if defined(CONFIG_M5307C3) +#define NE2000_ADDR 0x40000300 +#define NE2000_ODDOFFSET 0x00010000 +#define NE2000_IRQ_VECTOR 0x1b +#define NE2000_BYTE volatile unsigned short +#endif + +#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) +#define NE2000_ADDR 0x30600300 +#define NE2000_ODDOFFSET 0x00008000 +#define NE2000_IRQ_VECTOR 67 +#undef BSWAP +#define BSWAP(w) (w) +#define NE2000_BYTE volatile unsigned short +#undef RSWAP +#define RSWAP(w) (((w) << 8) | ((w) >> 8)) +#endif + +#if defined(CONFIG_M5307) && defined(CONFIG_NETtel) +#define NE2000_ADDR0 0x30600300 +#define NE2000_ADDR1 0x30800300 +#define NE2000_ODDOFFSET 0x00008000 +#define NE2000_IRQ_VECTOR0 27 +#define NE2000_IRQ_VECTOR1 29 +#undef BSWAP +#define BSWAP(w) (w) +#define NE2000_BYTE volatile unsigned short +#undef RSWAP +#define RSWAP(w) (((w) << 8) | ((w) >> 8)) +#endif + +#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3) +#define NE2000_ADDR 0x30600300 +#define NE2000_ODDOFFSET 0x00008000 +#define NE2000_IRQ_VECTOR 27 +#undef BSWAP +#define BSWAP(w) (w) +#define NE2000_BYTE volatile unsigned short +#undef RSWAP +#define RSWAP(w) (((w) << 8) | ((w) >> 8)) +#endif + +#if defined(CONFIG_ARN5307) +#define NE2000_ADDR 0xfe600300 +#define NE2000_ODDOFFSET 0x00010000 +#define NE2000_IRQ_VECTOR 0x1b +#define NE2000_IRQ_PRIORITY 2 +#define NE2000_IRQ_LEVEL 3 +#define NE2000_BYTE volatile unsigned short +#endif + +#if defined(CONFIG_M5407C3) +#define NE2000_ADDR 0x40000300 +#define NE2000_ODDOFFSET 0x00010000 +#define NE2000_IRQ_VECTOR 0x1b +#define NE2000_BYTE volatile unsigned short +#endif + +/****************************************************************************/ + +/* + * Side-band address space for odd address requires re-mapping + * many of the standard ISA access functions. + */ +#ifdef NE2000_ODDOFFSET + +#undef outb +#undef outb_p +#undef inb +#undef inb_p +#undef outsb +#undef outsw +#undef insb +#undef insw + +#define outb ne2000_outb +#define inb ne2000_inb +#define outb_p ne2000_outb +#define inb_p ne2000_inb +#define outsb ne2000_outsb +#define outsw ne2000_outsw +#define insb ne2000_insb +#define insw ne2000_insw + + +#ifndef COLDFIRE_NE2000_FUNCS + +void ne2000_outb(unsigned int val, unsigned int addr); +int ne2000_inb(unsigned int addr); +void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len); +void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len); +void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len); +void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len); + +#else + +/* + * This macro converts a conventional register address into the + * real memory pointer of the mapped NE2000 device. + * On most NE2000 implementations on ColdFire boards the chip is + * mapped in kinda funny, due to its ISA heritage. + */ +#define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr)) +#define NE2000_DATA_PTR(addr) (addr) + + +void ne2000_outb(unsigned int val, unsigned int addr) +{ + NE2000_BYTE *rp; + + rp = (NE2000_BYTE *) NE2000_PTR(addr); + *rp = RSWAP(val); +} + +int ne2000_inb(unsigned int addr) +{ + NE2000_BYTE *rp, val; + + rp = (NE2000_BYTE *) NE2000_PTR(addr); + val = *rp; + return((int) ((NE2000_BYTE) RSWAP(val))); +} + +void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len) +{ + NE2000_BYTE *rp, val; + unsigned char *buf; + + buf = (unsigned char *) vbuf; + rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); + for (; (len > 0); len--) { + val = *rp; + *buf++ = RSWAP(val); + } +} + +void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len) +{ + volatile unsigned short *rp; + unsigned short w, *buf; + + buf = (unsigned short *) vbuf; + rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); + for (; (len > 0); len--) { + w = *rp; + *buf++ = BSWAP(w); + } +} + +void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len) +{ + NE2000_BYTE *rp, val; + unsigned char *buf; + + buf = (unsigned char *) vbuf; + rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); + for (; (len > 0); len--) { + val = *buf++; + *rp = RSWAP(val); + } +} + +void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len) +{ + volatile unsigned short *rp; + unsigned short w, *buf; + + buf = (unsigned short *) vbuf; + rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); + for (; (len > 0); len--) { + w = *buf++; + *rp = BSWAP(w); + } +} + +#endif /* COLDFIRE_NE2000_FUNCS */ +#endif /* NE2000_OFFOFFSET */ + +/****************************************************************************/ + +#ifdef COLDFIRE_NE2000_FUNCS + +/* + * Lastly the interrupt set up code... + * Minor differences between the different board types. + */ + +#if defined(CONFIG_ARN5206) +void ne2000_irqsetup(int irq) +{ + volatile unsigned char *icrp; + + icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); + *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2; + mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); +} +#endif + +#if defined(CONFIG_M5206eC3) +void ne2000_irqsetup(int irq) +{ + volatile unsigned char *icrp; + + icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); + *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC; + mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); +} +#endif + +#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) +void ne2000_irqsetup(int irq) +{ + mcf_autovector(irq); +} +#endif + +#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) +void ne2000_irqsetup(int irq) +{ + volatile unsigned long *icrp; + volatile unsigned long *pitr; + + /* The NE2000 device uses external IRQ3 */ + icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); + *icrp = (*icrp & 0x77077777) | 0x00d00000; + + pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR); + *pitr = *pitr | 0x20000000; +} + +void ne2000_irqack(int irq) +{ + volatile unsigned long *icrp; + + /* The NE2000 device uses external IRQ3 */ + icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); + *icrp = (*icrp & 0x77777777) | 0x00800000; +} +#endif + +#if defined(CONFIG_M5307) || defined(CONFIG_M5407) +#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) + +void ne2000_irqsetup(int irq) +{ + mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); + mcf_autovector(irq); +} + +#else + +void ne2000_irqsetup(int irq) +{ + mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); +} + +#endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */ +#endif /* CONFIG_M5307 || CONFIG_M5407 */ + +#endif /* COLDFIRE_NE2000_FUNCS */ + +/****************************************************************************/ +#endif /* mcfne_h */ diff --git a/arch/m68knommu/include/asm/mcfpci.h b/arch/m68knommu/include/asm/mcfpci.h new file mode 100644 index 000000000000..f1507dd06ec6 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfpci.h @@ -0,0 +1,119 @@ +/****************************************************************************/ + +/* + * mcfpci.h -- PCI bridge on ColdFire eval boards. + * + * (C) Copyright 2000, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcfpci_h +#define mcfpci_h +/****************************************************************************/ + + +#ifdef CONFIG_PCI + +/* + * Address regions in the PCI address space are not mapped into the + * normal memory space of the ColdFire. They must be accessed via + * handler routines. This is easy for I/O space (inb/outb/etc) but + * needs some code changes to support ordinary memory. Interrupts + * also need to be vectored through the PCI handler first, then it + * will call the actual driver sub-handlers. + */ + +/* + * Un-define all the standard I/O access routines. + */ +#undef inb +#undef inw +#undef inl +#undef inb_p +#undef inw_p +#undef insb +#undef insw +#undef insl +#undef outb +#undef outw +#undef outl +#undef outb_p +#undef outw_p +#undef outsb +#undef outsw +#undef outsl + +#undef request_irq +#undef free_irq + +#undef bus_to_virt +#undef virt_to_bus + + +/* + * Re-direct all I/O memory accesses functions to PCI specific ones. + */ +#define inb pci_inb +#define inw pci_inw +#define inl pci_inl +#define inb_p pci_inb +#define inw_p pci_inw +#define insb pci_insb +#define insw pci_insw +#define insl pci_insl + +#define outb pci_outb +#define outw pci_outw +#define outl pci_outl +#define outb_p pci_outb +#define outw_p pci_outw +#define outsb pci_outsb +#define outsw pci_outsw +#define outsl pci_outsl + +#define request_irq pci_request_irq +#define free_irq pci_free_irq + +#define virt_to_bus pci_virt_to_bus +#define bus_to_virt pci_bus_to_virt + +#define CONFIG_COMEMPCI 1 + + +/* + * Prototypes of the real PCI functions (defined in bios32.c). + */ +unsigned char pci_inb(unsigned int addr); +unsigned short pci_inw(unsigned int addr); +unsigned int pci_inl(unsigned int addr); +void pci_insb(void *addr, void *buf, int len); +void pci_insw(void *addr, void *buf, int len); +void pci_insl(void *addr, void *buf, int len); + +void pci_outb(unsigned char val, unsigned int addr); +void pci_outw(unsigned short val, unsigned int addr); +void pci_outl(unsigned int val, unsigned int addr); +void pci_outsb(void *addr, void *buf, int len); +void pci_outsw(void *addr, void *buf, int len); +void pci_outsl(void *addr, void *buf, int len); + +int pci_request_irq(unsigned int irq, + void (*handler)(int, void *, struct pt_regs *), + unsigned long flags, + const char *device, + void *dev_id); +void pci_free_irq(unsigned int irq, void *dev_id); + +void *pci_bmalloc(int size); +void pci_bmfree(void *bmp, int len); +void pci_copytoshmem(unsigned long bmp, void *src, int size); +void pci_copyfromshmem(void *dst, unsigned long bmp, int size); +unsigned long pci_virt_to_bus(volatile void *address); +void *pci_bus_to_virt(unsigned long address); +void pci_bmcpyto(void *dst, void *src, int len); +void pci_bmcpyfrom(void *dst, void *src, int len); + +#endif /* CONFIG_PCI */ +/****************************************************************************/ +#endif /* mcfpci_h */ diff --git a/arch/m68knommu/include/asm/mcfpit.h b/arch/m68knommu/include/asm/mcfpit.h new file mode 100644 index 000000000000..f570cf64fd29 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfpit.h @@ -0,0 +1,64 @@ +/****************************************************************************/ + +/* + * mcfpit.h -- ColdFire internal PIT timer support defines. + * + * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) + */ + +/****************************************************************************/ +#ifndef mcfpit_h +#define mcfpit_h +/****************************************************************************/ + + +/* + * Get address specific defines for the 5270/5271, 5280/5282, and 5208. + */ +#if defined(CONFIG_M520x) +#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ +#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ +#else +#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ +#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ +#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ +#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ +#endif + +/* + * Define the PIT timer register set addresses. + */ +#define MCFPIT_PCSR 0x0 /* PIT control register */ +#define MCFPIT_PMR 0x2 /* PIT modulus register */ +#define MCFPIT_PCNTR 0x4 /* PIT count register */ + +/* + * Bit definitions for the PIT Control and Status register. + */ +#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ +#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ +#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ +#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ +#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ +#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ +#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ +#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ +#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ +#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ +#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ +#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ +#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ +#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ +#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ +#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ +#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ +#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ +#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ +#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ +#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ +#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ +#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ +#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ + +/****************************************************************************/ +#endif /* mcfpit_h */ diff --git a/arch/m68knommu/include/asm/mcfsim.h b/arch/m68knommu/include/asm/mcfsim.h new file mode 100644 index 000000000000..da3f2ceff3a4 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfsim.h @@ -0,0 +1,126 @@ +/****************************************************************************/ + +/* + * mcfsim.h -- ColdFire System Integration Module support. + * + * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcfsim_h +#define mcfsim_h +/****************************************************************************/ + + +/* + * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, + * 5307 or 5407 specific addresses. + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#include +#elif defined(CONFIG_M520x) +#include +#elif defined(CONFIG_M523x) +#include +#elif defined(CONFIG_M5249) +#include +#elif defined(CONFIG_M527x) +#include +#elif defined(CONFIG_M5272) +#include +#elif defined(CONFIG_M528x) +#include +#elif defined(CONFIG_M5307) +#include +#elif defined(CONFIG_M532x) +#include +#elif defined(CONFIG_M5407) +#include +#endif + + +/* + * Define the base address of the SIM within the MBAR address space. + */ +#define MCFSIM_BASE 0x0 /* Base address of SIM */ + + +/* + * Bit definitions for the ICR family of registers. + */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + +/* + * Bit definitions for the Interrupt Mask register (IMR). + */ +#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ +#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ +#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ +#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ +#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ +#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ +#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ + +#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ +#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ +#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ +#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ +#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ +#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ + +#if defined(CONFIG_M5206e) +#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ +#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) +#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ +#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ +#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ +#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ +#endif + +/* + * Mask for all of the SIM devices. Some parts have more or less + * SIM devices. This is a catchall for the sandard set. + */ +#ifndef MCFSIM_IMR_MASKALL +#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ +#endif + + +/* + * PIT interrupt settings, if not found in mXXXXsim.h file. + */ +#ifndef ICR_INTRCONF +#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */ +#endif +#ifndef MCFPIT_IMR +#define MCFPIT_IMR MCFINTC_IMRH +#endif +#ifndef MCFPIT_IMR_IBIT +#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32)) +#endif + + +#ifndef __ASSEMBLY__ +/* + * Definition for the interrupt auto-vectoring support. + */ +extern void mcf_autovector(unsigned int vec); +#endif /* __ASSEMBLY__ */ + +/****************************************************************************/ +#endif /* mcfsim_h */ diff --git a/arch/m68knommu/include/asm/mcfsmc.h b/arch/m68knommu/include/asm/mcfsmc.h new file mode 100644 index 000000000000..2d7a4dbd9683 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfsmc.h @@ -0,0 +1,187 @@ +/****************************************************************************/ + +/* + * mcfsmc.h -- SMC ethernet support for ColdFire environments. + * + * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcfsmc_h +#define mcfsmc_h +/****************************************************************************/ + +/* + * None of the current ColdFire targets that use the SMC91x111 + * allow 8 bit accesses. So this code is 16bit access only. + */ + + +#undef outb +#undef inb +#undef outw +#undef outwd +#undef inw +#undef outl +#undef inl + +#undef outsb +#undef outsw +#undef outsl +#undef insb +#undef insw +#undef insl + +/* + * Re-defines for ColdFire environment... The SMC part is + * mapped into memory space, so remap the PC-style in/out + * routines to handle that. + */ +#define outb smc_outb +#define inb smc_inb +#define outw smc_outw +#define outwd smc_outwd +#define inw smc_inw +#define outl smc_outl +#define inl smc_inl + +#define outsb smc_outsb +#define outsw smc_outsw +#define outsl smc_outsl +#define insb smc_insb +#define insw smc_insw +#define insl smc_insl + + +static inline int smc_inb(unsigned int addr) +{ + register unsigned short w; + w = *((volatile unsigned short *) (addr & ~0x1)); + return(((addr & 0x1) ? w : (w >> 8)) & 0xff); +} + +static inline void smc_outw(unsigned int val, unsigned int addr) +{ + *((volatile unsigned short *) addr) = (val << 8) | (val >> 8); +} + +static inline int smc_inw(unsigned int addr) +{ + register unsigned short w; + w = *((volatile unsigned short *) addr); + return(((w << 8) | (w >> 8)) & 0xffff); +} + +static inline void smc_outl(unsigned long val, unsigned int addr) +{ + *((volatile unsigned long *) addr) = + ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) | + ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff); +} + +static inline void smc_outwd(unsigned int val, unsigned int addr) +{ + *((volatile unsigned short *) addr) = val; +} + + +/* + * The rep* functions are used to feed the data port with + * raw data. So we do not byte swap them when copying. + */ + +static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len) +{ + volatile unsigned short *rp; + unsigned short *buf, *ebuf; + + buf = (unsigned short *) vbuf; + rp = (volatile unsigned short *) addr; + + /* Copy as words for as long as possible */ + for (ebuf = buf + (len >> 1); (buf < ebuf); ) + *buf++ = *rp; + + /* Lastly, handle left over byte */ + if (len & 0x1) + *((unsigned char *) buf) = (*rp >> 8) & 0xff; +} + +static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len) +{ + volatile unsigned short *rp; + unsigned short *buf, *ebuf; + + buf = (unsigned short *) vbuf; + rp = (volatile unsigned short *) addr; + for (ebuf = buf + len; (buf < ebuf); ) + *buf++ = *rp; +} + +static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len) +{ + volatile unsigned long *rp; + unsigned long *buf, *ebuf; + + buf = (unsigned long *) vbuf; + rp = (volatile unsigned long *) addr; + for (ebuf = buf + len; (buf < ebuf); ) + *buf++ = *rp; +} + +static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len) +{ + volatile unsigned short *rp; + unsigned short *buf, *ebuf; + + buf = (unsigned short *) vbuf; + rp = (volatile unsigned short *) addr; + for (ebuf = buf + len; (buf < ebuf); ) + *rp = *buf++; +} + +static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len) +{ + volatile unsigned long *rp; + unsigned long *buf, *ebuf; + + buf = (unsigned long *) vbuf; + rp = (volatile unsigned long *) addr; + for (ebuf = buf + len; (buf < ebuf); ) + *rp = *buf++; +} + + +#ifdef CONFIG_NETtel +/* + * Re-map the address space of at least one of the SMC ethernet + * parts. Both parts power up decoding the same address, so we + * need to move one of them first, before doing enything else. + * + * We also increase the number of wait states for this part by one. + */ + +void smc_remap(unsigned int ioaddr) +{ + static int once = 0; + extern unsigned short ppdata; + if (once++ == 0) { + *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec; + ppdata |= 0x0080; + *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; + outw(0x0001, ioaddr + BANK_SELECT); + outw(0x0001, ioaddr + BANK_SELECT); + outw(0x0067, ioaddr + BASE); + + ppdata &= ~0x0080; + *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; + } + + *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180; +} + +#endif + +/****************************************************************************/ +#endif /* mcfsmc_h */ diff --git a/arch/m68knommu/include/asm/mcftimer.h b/arch/m68knommu/include/asm/mcftimer.h new file mode 100644 index 000000000000..0f90f6d2227a --- /dev/null +++ b/arch/m68knommu/include/asm/mcftimer.h @@ -0,0 +1,80 @@ +/****************************************************************************/ + +/* + * mcftimer.h -- ColdFire internal TIMER support defines. + * + * (C) Copyright 1999-2006, Greg Ungerer + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcftimer_h +#define mcftimer_h +/****************************************************************************/ + + +/* + * Get address specific defines for this ColdFire member. + */ +#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ +#elif defined(CONFIG_M5272) +#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ +#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ +#elif defined(CONFIG_M532x) +#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ +#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ +#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ +#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ +#endif + + +/* + * Define the TIMER register set addresses. + */ +#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ +#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ +#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ +#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ +#if defined(CONFIG_M532x) +#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ +#else +#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ +#endif + +/* + * Bit definitions for the Timer Mode Register (TMR). + * Register bit flags are common accross ColdFires. + */ +#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ +#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ +#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ +#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ +#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ +#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ +#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ +#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ +#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ +#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ +#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ +#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ +#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ +#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ +#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ +#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ +#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ + +/* + * Bit definitions for the Timer Event Registers (TER). + */ +#define MCFTIMER_TER_CAP 0x01 /* Capture event */ +#define MCFTIMER_TER_REF 0x02 /* Refernece event */ + +/****************************************************************************/ +#endif /* mcftimer_h */ diff --git a/arch/m68knommu/include/asm/mcfuart.h b/arch/m68knommu/include/asm/mcfuart.h new file mode 100644 index 000000000000..ef2293873612 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfuart.h @@ -0,0 +1,216 @@ +/****************************************************************************/ + +/* + * mcfuart.h -- ColdFire internal UART support defines. + * + * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) + * (C) Copyright 2000, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcfuart_h +#define mcfuart_h +/****************************************************************************/ + +/* + * Define the base address of the UARTS within the MBAR address + * space. + */ +#if defined(CONFIG_M5272) +#define MCFUART_BASE1 0x100 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) +#if defined(CONFIG_NETtel) +#define MCFUART_BASE1 0x180 /* Base address of UART1 */ +#define MCFUART_BASE2 0x140 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x140 /* Base address of UART1 */ +#define MCFUART_BASE2 0x180 /* Base address of UART2 */ +#endif +#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x240 /* Base address of UART2 */ +#define MCFUART_BASE3 0x280 /* Base address of UART3 */ +#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) +#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) +#define MCFUART_BASE1 0x200 /* Base address of UART1 */ +#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ +#else +#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ +#define MCFUART_BASE2 0x200 /* Base address of UART2 */ +#endif +#elif defined(CONFIG_M520x) +#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ +#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ +#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ +#elif defined(CONFIG_M532x) +#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ +#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ +#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ +#endif + + +#include +#include + +struct mcf_platform_uart { + unsigned long mapbase; /* Physical address base */ + void __iomem *membase; /* Virtual address if mapped */ + unsigned int irq; /* Interrupt vector */ + unsigned int uartclk; /* UART clock rate */ +}; + +/* + * Define the ColdFire UART register set addresses. + */ +#define MCFUART_UMR 0x00 /* Mode register (r/w) */ +#define MCFUART_USR 0x04 /* Status register (r) */ +#define MCFUART_UCSR 0x04 /* Clock Select (w) */ +#define MCFUART_UCR 0x08 /* Command register (w) */ +#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ +#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ +#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ +#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ +#define MCFUART_UISR 0x14 /* Interrupt Status (r) */ +#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ +#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ +#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ +#ifdef CONFIG_M5272 +#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ +#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ +#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ +#else +#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ +#endif +#define MCFUART_UIPR 0x34 /* Input Port (r) */ +#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ +#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ + + +/* + * Define bit flags in Mode Register 1 (MR1). + */ +#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ +#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ +#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ +#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ +#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ + +#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ +#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ +#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ +#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ +#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ + +#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ +#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ +#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ +#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ + +/* + * Define bit flags in Mode Register 2 (MR2). + */ +#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ +#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ +#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ +#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ +#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ + +#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ +#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ +#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ + +/* + * Define bit flags in Status Register (USR). + */ +#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ +#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ +#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ +#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ +#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ +#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ +#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ +#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ + +#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ + MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) + +/* + * Define bit flags in Clock Select Register (UCSR). + */ +#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ +#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ +#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ + +#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ +#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ +#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ + +/* + * Define bit flags in Command Register (UCR). + */ +#define MCFUART_UCR_CMDNULL 0x00 /* No command */ +#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ +#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ +#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ +#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ +#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ +#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ +#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ + +#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ +#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ +#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ +#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ +#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ +#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ + +/* + * Define bit flags in Input Port Change Register (UIPCR). + */ +#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ +#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Input Port Register (UIP). + */ +#define MCFUART_UIPR_CTS 0x01 /* CTS value */ + +/* + * Define bit flags in Output Port Registers (UOP). + * Clear bit by writing to UOP0, set by writing to UOP1. + */ +#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ + +/* + * Define bit flags in the Auxiliary Control Register (UACR). + */ +#define MCFUART_UACR_IEC 0x01 /* Input enable control */ + +/* + * Define bit flags in Interrupt Status Register (UISR). + * These same bits are used for the Interrupt Mask Register (UIMR). + */ +#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ +#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ +#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ +#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ + +#ifdef CONFIG_M5272 +/* + * Define bit flags in the Transmitter FIFO Register (UTF). + */ +#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ +#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ +#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ + +/* + * Define bit flags in the Receiver FIFO Register (URF). + */ +#define MCFUART_URF_RXB 0x1f /* Receiver data level */ +#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ +#define MCFUART_URF_RXS 0xc0 /* Receiver status */ +#endif + +/****************************************************************************/ +#endif /* mcfuart_h */ diff --git a/arch/m68knommu/include/asm/mcfwdebug.h b/arch/m68knommu/include/asm/mcfwdebug.h new file mode 100644 index 000000000000..27f70e45d700 --- /dev/null +++ b/arch/m68knommu/include/asm/mcfwdebug.h @@ -0,0 +1,118 @@ +/****************************************************************************/ + +/* + * mcfdebug.h -- ColdFire Debug Module support. + * + * (C) Copyright 2001, Lineo Inc. (www.lineo.com) + */ + +/****************************************************************************/ +#ifndef mcfdebug_h +#define mcfdebug_h +/****************************************************************************/ + +/* Define the debug module registers */ +#define MCFDEBUG_CSR 0x0 /* Configuration status */ +#define MCFDEBUG_BAAR 0x5 /* BDM address attribute */ +#define MCFDEBUG_AATR 0x6 /* Address attribute trigger */ +#define MCFDEBUG_TDR 0x7 /* Trigger definition */ +#define MCFDEBUG_PBR 0x8 /* PC breakpoint */ +#define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ +#define MCFDEBUG_ABHR 0xc /* High address breakpoint */ +#define MCFDEBUG_ABLR 0xd /* Low address breakpoint */ +#define MCFDEBUG_DBR 0xe /* Data breakpoint */ +#define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ + +/* Define some handy constants for the trigger definition register */ +#define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ +#define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ +#define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ +#define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ +#define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ +#define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ +#define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ +#define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ +#define MCFDEBUG_TDR_EDLW2 0x10000000 +#define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ +#define MCFDEBUG_TDR_EDWL2 0x08000000 +#define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ +#define MCFDEBUG_TDR_EDWU2 0x04000000 +#define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ +#define MCFDEBUG_TDR_EDLL2 0x02000000 +#define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ +#define MCFDEBUG_TDR_EDLM2 0x01000000 +#define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ +#define MCFDEBUG_TDR_EDUM2 0x00800000 +#define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ +#define MCFDEBUG_TDR_EDUU2 0x00400000 +#define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ +#define MCFDEBUG_TDR_DI2 0x00200000 +#define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ +#define MCFDEBUG_TDR_EAI2 0x00100000 +#define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ +#define MCFDEBUG_TDR_EAR2 0x00080000 +#define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ +#define MCFDEBUG_TDR_EAL2 0x00040000 +#define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ +#define MCFDEBUG_TDR_EPC2 0x00020000 +#define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ +#define MCFDEBUG_TDR_PCI2 0x00010000 + +/* Constants for the address attribute trigger register */ +#define MCFDEBUG_AAR_RESET 0x00000005 +/* Fields not yet implemented */ + +/* And some definitions for the writable sections of the CSR */ +#define MCFDEBUG_CSR_RESET 0x00100000 +#define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ +#define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ +#define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ +#define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ +#define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ +#define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ +#define MCFDEBUG_CSR_DDC_WRITE 0x00001000 +#define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ +#define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ +#define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ +#define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ +#define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ +#define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ +#define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ + +/* Constants for the BDM address attribute register */ +#define MCFDEBUG_BAAR_RESET 0x00000005 +/* Fields not yet implemented */ + + +/* This routine wrappers up the wdebug asm instruction so that the register + * and value can be relatively easily specified. The biggest hassle here is + * that the debug module instructions (2 longs) must be long word aligned and + * some pointer fiddling is performed to ensure this. + */ +static inline void wdebug(int reg, unsigned long data) { + unsigned short dbg_spc[6]; + unsigned short *dbg; + + // Force alignment to long word boundary + dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc); + + // Build up the debug instruction + dbg[0] = 0x2c80 | (reg & 0xf); + dbg[1] = (data >> 16) & 0xffff; + dbg[2] = data & 0xffff; + dbg[3] = 0; + + // Perform the wdebug instruction +#if 0 + // This strain is for gas which doesn't have the wdebug instructions defined + asm( "move.l %0, %%a0\n\t" + ".word 0xfbd0\n\t" + ".word 0x0003\n\t" + :: "g" (dbg) : "a0"); +#else + // And this is for when it does + asm( "wdebug (%0)" :: "a" (dbg)); +#endif +} + +#endif diff --git a/arch/m68knommu/include/asm/md.h b/arch/m68knommu/include/asm/md.h new file mode 100644 index 000000000000..d810c78de5ff --- /dev/null +++ b/arch/m68knommu/include/asm/md.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/mman.h b/arch/m68knommu/include/asm/mman.h new file mode 100644 index 000000000000..4846c682efed --- /dev/null +++ b/arch/m68knommu/include/asm/mman.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/mmu.h b/arch/m68knommu/include/asm/mmu.h new file mode 100644 index 000000000000..5fa6b68353ba --- /dev/null +++ b/arch/m68knommu/include/asm/mmu.h @@ -0,0 +1,11 @@ +#ifndef __M68KNOMMU_MMU_H +#define __M68KNOMMU_MMU_H + +/* Copyright (C) 2002, David McCullough */ + +typedef struct { + struct vm_list_struct *vmlist; + unsigned long end_brk; +} mm_context_t; + +#endif /* __M68KNOMMU_MMU_H */ diff --git a/arch/m68knommu/include/asm/mmu_context.h b/arch/m68knommu/include/asm/mmu_context.h new file mode 100644 index 000000000000..9ccee4278c97 --- /dev/null +++ b/arch/m68knommu/include/asm/mmu_context.h @@ -0,0 +1,33 @@ +#ifndef __M68KNOMMU_MMU_CONTEXT_H +#define __M68KNOMMU_MMU_CONTEXT_H + +#include +#include +#include +#include + +static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} + +static inline int +init_new_context(struct task_struct *tsk, struct mm_struct *mm) +{ + // mm->context = virt_to_phys(mm->pgd); + return(0); +} + +#define destroy_context(mm) do { } while(0) + +static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) +{ +} + +#define deactivate_mm(tsk,mm) do { } while (0) + +static inline void activate_mm(struct mm_struct *prev_mm, + struct mm_struct *next_mm) +{ +} + +#endif diff --git a/arch/m68knommu/include/asm/module.h b/arch/m68knommu/include/asm/module.h new file mode 100644 index 000000000000..2e45ab50b232 --- /dev/null +++ b/arch/m68knommu/include/asm/module.h @@ -0,0 +1,11 @@ +#ifndef ASM_M68KNOMMU_MODULE_H +#define ASM_M68KNOMMU_MODULE_H + +struct mod_arch_specific { +}; + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr + +#endif /* ASM_M68KNOMMU_MODULE_H */ diff --git a/arch/m68knommu/include/asm/movs.h b/arch/m68knommu/include/asm/movs.h new file mode 100644 index 000000000000..81a16779e833 --- /dev/null +++ b/arch/m68knommu/include/asm/movs.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/msgbuf.h b/arch/m68knommu/include/asm/msgbuf.h new file mode 100644 index 000000000000..bdfadec4d52d --- /dev/null +++ b/arch/m68knommu/include/asm/msgbuf.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/mutex.h b/arch/m68knommu/include/asm/mutex.h new file mode 100644 index 000000000000..458c1f7fbc18 --- /dev/null +++ b/arch/m68knommu/include/asm/mutex.h @@ -0,0 +1,9 @@ +/* + * Pull in the generic implementation for the mutex fastpath. + * + * TODO: implement optimized primitives instead, or leave the generic + * implementation in place, or pick the atomic_xchg() based generic + * implementation. (see asm-generic/mutex-xchg.h for details) + */ + +#include diff --git a/arch/m68knommu/include/asm/nettel.h b/arch/m68knommu/include/asm/nettel.h new file mode 100644 index 000000000000..0299f6a2deeb --- /dev/null +++ b/arch/m68knommu/include/asm/nettel.h @@ -0,0 +1,108 @@ +/****************************************************************************/ + +/* + * nettel.h -- Lineo (formerly Moreton Bay) NETtel support. + * + * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com) + * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com) + * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com) + */ + +/****************************************************************************/ +#ifndef nettel_h +#define nettel_h +/****************************************************************************/ + + +/****************************************************************************/ +#ifdef CONFIG_NETtel +/****************************************************************************/ + +#ifdef CONFIG_COLDFIRE +#include +#include +#endif + +/*---------------------------------------------------------------------------*/ +#if defined(CONFIG_M5307) +/* + * NETtel/5307 based hardware first. DTR/DCD lines are wired to + * GPIO lines. Most of the LED's are driver through a latch + * connected to CS2. + */ +#define MCFPP_DCD1 0x0001 +#define MCFPP_DCD0 0x0002 +#define MCFPP_DTR1 0x0004 +#define MCFPP_DTR0 0x0008 + +#define NETtel_LEDADDR 0x30400000 + +#ifndef __ASSEMBLY__ + +extern volatile unsigned short ppdata; + +/* + * These functions defined to give quasi generic access to the + * PPIO bits used for DTR/DCD. + */ +static __inline__ unsigned int mcf_getppdata(void) +{ + volatile unsigned short *pp; + pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); + return((unsigned int) *pp); +} + +static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) +{ + volatile unsigned short *pp; + pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); + ppdata = (ppdata & ~mask) | bits; + *pp = ppdata; +} +#endif + +/*---------------------------------------------------------------------------*/ +#elif defined(CONFIG_M5206e) +/* + * NETtel/5206e based hardware has leds on latch on CS3. + * No support modem for lines?? + */ +#define NETtel_LEDADDR 0x50000000 + +/*---------------------------------------------------------------------------*/ +#elif defined(CONFIG_M5272) +/* + * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines. + */ +#define MCFPP_DCD0 0x0080 +#define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */ +#define MCFPP_DTR0 0x0040 +#define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */ + +#ifndef __ASSEMBLY__ +/* + * These functions defined to give quasi generic access to the + * PPIO bits used for DTR/DCD. + */ +static __inline__ unsigned int mcf_getppdata(void) +{ + volatile unsigned short *pp; + pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); + return((unsigned int) *pp); +} + +static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) +{ + volatile unsigned short *pp; + pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); + *pp = (*pp & ~mask) | bits; +} +#endif + +#endif +/*---------------------------------------------------------------------------*/ + +/****************************************************************************/ +#endif /* CONFIG_NETtel */ +/****************************************************************************/ +#endif /* nettel_h */ diff --git a/arch/m68knommu/include/asm/openprom.h b/arch/m68knommu/include/asm/openprom.h new file mode 100644 index 000000000000..fdba7953ff9f --- /dev/null +++ b/arch/m68knommu/include/asm/openprom.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/oplib.h b/arch/m68knommu/include/asm/oplib.h new file mode 100644 index 000000000000..ce079dc332d9 --- /dev/null +++ b/arch/m68knommu/include/asm/oplib.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/page.h b/arch/m68knommu/include/asm/page.h new file mode 100644 index 000000000000..3a1ede4544cb --- /dev/null +++ b/arch/m68knommu/include/asm/page.h @@ -0,0 +1,77 @@ +#ifndef _M68KNOMMU_PAGE_H +#define _M68KNOMMU_PAGE_H + +/* PAGE_SHIFT determines the page size */ + +#define PAGE_SHIFT (12) +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) + +#include + +#ifndef __ASSEMBLY__ + +#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) +#define free_user_page(page, addr) free_page(addr) + +#define clear_page(page) memset((page), 0, PAGE_SIZE) +#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) + +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) + +#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ + alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) +#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pmd[16]; } pmd_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; +typedef struct page *pgtable_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((&x)->pmd[0]) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +extern unsigned long memory_start; +extern unsigned long memory_end; + +#endif /* !__ASSEMBLY__ */ + +#include + +#define PAGE_OFFSET (PAGE_OFFSET_RAW) + +#ifndef __ASSEMBLY__ + +#define __pa(vaddr) virt_to_phys((void *)(vaddr)) +#define __va(paddr) phys_to_virt((unsigned long)(paddr)) + +#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) +#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) + +#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) +#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) + +#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) +#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) +#define pfn_valid(pfn) ((pfn) < max_mapnr) + +#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ + ((void *)(kaddr) < (void *)memory_end)) + +#endif /* __ASSEMBLY__ */ + +#include + +#endif /* _M68KNOMMU_PAGE_H */ diff --git a/arch/m68knommu/include/asm/page_offset.h b/arch/m68knommu/include/asm/page_offset.h new file mode 100644 index 000000000000..d4e73e0ba646 --- /dev/null +++ b/arch/m68knommu/include/asm/page_offset.h @@ -0,0 +1,5 @@ + + +/* This handles the memory map.. */ +#define PAGE_OFFSET_RAW CONFIG_RAMBASE + diff --git a/arch/m68knommu/include/asm/param.h b/arch/m68knommu/include/asm/param.h new file mode 100644 index 000000000000..6044397adb64 --- /dev/null +++ b/arch/m68knommu/include/asm/param.h @@ -0,0 +1,22 @@ +#ifndef _M68KNOMMU_PARAM_H +#define _M68KNOMMU_PARAM_H + +#ifdef __KERNEL__ +#define HZ CONFIG_HZ +#define USER_HZ HZ +#define CLOCKS_PER_SEC (USER_HZ) +#endif + +#ifndef HZ +#define HZ 100 +#endif + +#define EXEC_PAGESIZE 4096 + +#ifndef NOGROUP +#define NOGROUP (-1) +#endif + +#define MAXHOSTNAMELEN 64 /* max length of hostname */ + +#endif /* _M68KNOMMU_PARAM_H */ diff --git a/arch/m68knommu/include/asm/pci.h b/arch/m68knommu/include/asm/pci.h new file mode 100644 index 000000000000..a13f3cc87451 --- /dev/null +++ b/arch/m68knommu/include/asm/pci.h @@ -0,0 +1,29 @@ +#ifndef M68KNOMMU_PCI_H +#define M68KNOMMU_PCI_H + +#include + +#ifdef CONFIG_COMEMPCI +/* + * These are pretty much arbitary with the CoMEM implementation. + * We have the whole address space to ourselves. + */ +#define PCIBIOS_MIN_IO 0x100 +#define PCIBIOS_MIN_MEM 0x00010000 + +#define pcibios_scan_all_fns(a, b) 0 + +/* + * Return whether the given PCI device DMA address mask can + * be supported properly. For example, if your device can + * only drive the low 24-bits during PCI bus mastering, then + * you would pass 0x00ffffff as the mask to this function. + */ +static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) +{ + return 1; +} + +#endif /* CONFIG_COMEMPCI */ + +#endif /* M68KNOMMU_PCI_H */ diff --git a/arch/m68knommu/include/asm/percpu.h b/arch/m68knommu/include/asm/percpu.h new file mode 100644 index 000000000000..5de72c327efd --- /dev/null +++ b/arch/m68knommu/include/asm/percpu.h @@ -0,0 +1,6 @@ +#ifndef __ARCH_M68KNOMMU_PERCPU__ +#define __ARCH_M68KNOMMU_PERCPU__ + +#include + +#endif /* __ARCH_M68KNOMMU_PERCPU__ */ diff --git a/arch/m68knommu/include/asm/pgalloc.h b/arch/m68knommu/include/asm/pgalloc.h new file mode 100644 index 000000000000..d6352f671ec0 --- /dev/null +++ b/arch/m68knommu/include/asm/pgalloc.h @@ -0,0 +1,8 @@ +#ifndef _M68KNOMMU_PGALLOC_H +#define _M68KNOMMU_PGALLOC_H + +#include + +#define check_pgt_cache() do { } while (0) + +#endif /* _M68KNOMMU_PGALLOC_H */ diff --git a/arch/m68knommu/include/asm/pgtable.h b/arch/m68knommu/include/asm/pgtable.h new file mode 100644 index 000000000000..46251016e821 --- /dev/null +++ b/arch/m68knommu/include/asm/pgtable.h @@ -0,0 +1,70 @@ +#ifndef _M68KNOMMU_PGTABLE_H +#define _M68KNOMMU_PGTABLE_H + +#include + +/* + * (C) Copyright 2000-2002, Greg Ungerer + */ + +#include +#include +#include +#include + +/* + * Trivial page table functions. + */ +#define pgd_present(pgd) (1) +#define pgd_none(pgd) (0) +#define pgd_bad(pgd) (0) +#define pgd_clear(pgdp) +#define kern_addr_valid(addr) (1) +#define pmd_offset(a, b) ((void *)0) + +#define PAGE_NONE __pgprot(0) +#define PAGE_SHARED __pgprot(0) +#define PAGE_COPY __pgprot(0) +#define PAGE_READONLY __pgprot(0) +#define PAGE_KERNEL __pgprot(0) + +extern void paging_init(void); +#define swapper_pg_dir ((pgd_t *) 0) + +#define __swp_type(x) (0) +#define __swp_offset(x) (0) +#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) + +static inline int pte_file(pte_t pte) { return 0; } + +/* + * ZERO_PAGE is a global shared page that is always zero: used + * for zero-mapped memory areas etc.. + */ +#define ZERO_PAGE(vaddr) (virt_to_page(0)) + +/* + * These would be in other places but having them here reduces the diffs. + */ +extern unsigned int kobjsize(const void *objp); + +/* + * No page table caches to initialise. + */ +#define pgtable_cache_init() do { } while (0) + +#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ + remap_pfn_range(vma, vaddr, pfn, size, prot) + +/* + * All 32bit addresses are effectively valid for vmalloc... + * Sort of meaningless for non-VM targets. + */ +#define VMALLOC_START 0 +#define VMALLOC_END 0xffffffff + +#include + +#endif /* _M68KNOMMU_PGTABLE_H */ diff --git a/arch/m68knommu/include/asm/poll.h b/arch/m68knommu/include/asm/poll.h new file mode 100644 index 000000000000..ee1b6cb549ca --- /dev/null +++ b/arch/m68knommu/include/asm/poll.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/posix_types.h b/arch/m68knommu/include/asm/posix_types.h new file mode 100644 index 000000000000..6205fb9392a3 --- /dev/null +++ b/arch/m68knommu/include/asm/posix_types.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/processor.h b/arch/m68knommu/include/asm/processor.h new file mode 100644 index 000000000000..91cba18acdd3 --- /dev/null +++ b/arch/m68knommu/include/asm/processor.h @@ -0,0 +1,143 @@ +/* + * include/asm-m68knommu/processor.h + * + * Copyright (C) 1995 Hamish Macdonald + */ + +#ifndef __ASM_M68K_PROCESSOR_H +#define __ASM_M68K_PROCESSOR_H + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ __label__ _l; _l: &&_l;}) + +#include +#include +#include +#include +#include +#include +#include + +static inline unsigned long rdusp(void) +{ +#ifdef CONFIG_COLDFIRE + extern unsigned int sw_usp; + return(sw_usp); +#else + unsigned long usp; + __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); + return usp; +#endif +} + +static inline void wrusp(unsigned long usp) +{ +#ifdef CONFIG_COLDFIRE + extern unsigned int sw_usp; + sw_usp = usp; +#else + __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); +#endif +} + +/* + * User space process size: 3.75GB. This is hardcoded into a few places, + * so don't change it unless you know what you are doing. + */ +#define TASK_SIZE (0xF0000000UL) + +/* + * This decides where the kernel will search for a free chunk of vm + * space during mmap's. We won't be using it + */ +#define TASK_UNMAPPED_BASE 0 + +/* + * if you change this structure, you must change the code and offsets + * in m68k/machasm.S + */ + +struct thread_struct { + unsigned long ksp; /* kernel stack pointer */ + unsigned long usp; /* user stack pointer */ + unsigned short sr; /* saved status register */ + unsigned short fs; /* saved fs (sfc, dfc) */ + unsigned long crp[2]; /* cpu root pointer */ + unsigned long esp0; /* points to SR of stack frame */ + unsigned long fp[8*3]; + unsigned long fpcntl[3]; /* fp control regs */ + unsigned char fpstate[FPSTATESIZE]; /* floating point state */ +}; + +#define INIT_THREAD { \ + sizeof(init_stack) + (unsigned long) init_stack, 0, \ + PS_S, __KERNEL_DS, \ + {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \ +} + +/* + * Coldfire stacks need to be re-aligned on trap exit, conventional + * 68k can handle this case cleanly. + */ +#if defined(CONFIG_COLDFIRE) +#define reformat(_regs) do { (_regs)->format = 0x4; } while(0) +#else +#define reformat(_regs) do { } while (0) +#endif + +/* + * Do necessary setup to start up a newly executed thread. + * + * pass the data segment into user programs if it exists, + * it can't hurt anything as far as I can tell + */ +#define start_thread(_regs, _pc, _usp) \ +do { \ + set_fs(USER_DS); /* reads from user space */ \ + (_regs)->pc = (_pc); \ + ((struct switch_stack *)(_regs))[-1].a6 = 0; \ + reformat(_regs); \ + if (current->mm) \ + (_regs)->d5 = current->mm->start_data; \ + (_regs)->sr &= ~0x2000; \ + wrusp(_usp); \ +} while(0) + +/* Forward declaration, a strange C thing */ +struct task_struct; + +/* Free all resources held by a thread. */ +static inline void release_thread(struct task_struct *dead_task) +{ +} + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while (0) + +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +/* + * Free current thread data structures etc.. + */ +static inline void exit_thread(void) +{ +} + +unsigned long thread_saved_pc(struct task_struct *tsk); +unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) \ + ({ \ + unsigned long eip = 0; \ + if ((tsk)->thread.esp0 > PAGE_SIZE && \ + (virt_addr_valid((tsk)->thread.esp0))) \ + eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ + eip; }) +#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) + +#define cpu_relax() barrier() + +#endif diff --git a/arch/m68knommu/include/asm/ptrace.h b/arch/m68knommu/include/asm/ptrace.h new file mode 100644 index 000000000000..8c9194b98548 --- /dev/null +++ b/arch/m68knommu/include/asm/ptrace.h @@ -0,0 +1,87 @@ +#ifndef _M68K_PTRACE_H +#define _M68K_PTRACE_H + +#define PT_D1 0 +#define PT_D2 1 +#define PT_D3 2 +#define PT_D4 3 +#define PT_D5 4 +#define PT_D6 5 +#define PT_D7 6 +#define PT_A0 7 +#define PT_A1 8 +#define PT_A2 9 +#define PT_A3 10 +#define PT_A4 11 +#define PT_A5 12 +#define PT_A6 13 +#define PT_D0 14 +#define PT_USP 15 +#define PT_ORIG_D0 16 +#define PT_SR 17 +#define PT_PC 18 + +#ifndef __ASSEMBLY__ + +/* this struct defines the way the registers are stored on the + stack during a system call. */ + +struct pt_regs { + long d1; + long d2; + long d3; + long d4; + long d5; + long a0; + long a1; + long a2; + long d0; + long orig_d0; + long stkadj; +#ifdef CONFIG_COLDFIRE + unsigned format : 4; /* frame format specifier */ + unsigned vector : 12; /* vector offset */ + unsigned short sr; + unsigned long pc; +#else + unsigned short sr; + unsigned long pc; + unsigned format : 4; /* frame format specifier */ + unsigned vector : 12; /* vector offset */ +#endif +}; + +/* + * This is the extended stack used by signal handlers and the context + * switcher: it's pushed after the normal "struct pt_regs". + */ +struct switch_stack { + unsigned long d6; + unsigned long d7; + unsigned long a3; + unsigned long a4; + unsigned long a5; + unsigned long a6; + unsigned long retpc; +}; + +/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ +#define PTRACE_GETREGS 12 +#define PTRACE_SETREGS 13 +#define PTRACE_GETFPREGS 14 +#define PTRACE_SETFPREGS 15 + +#ifdef __KERNEL__ + +#ifndef PS_S +#define PS_S (0x2000) +#define PS_M (0x1000) +#endif + +#define user_mode(regs) (!((regs)->sr & PS_S)) +#define instruction_pointer(regs) ((regs)->pc) +#define profile_pc(regs) instruction_pointer(regs) +extern void show_regs(struct pt_regs *); +#endif /* __KERNEL__ */ +#endif /* __ASSEMBLY__ */ +#endif /* _M68K_PTRACE_H */ diff --git a/arch/m68knommu/include/asm/quicc_simple.h b/arch/m68knommu/include/asm/quicc_simple.h new file mode 100644 index 000000000000..c3636932d4bc --- /dev/null +++ b/arch/m68knommu/include/asm/quicc_simple.h @@ -0,0 +1,52 @@ +/*********************************** + * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $ + *********************************** + * + *************************************** + * Simple drivers common header + *************************************** + */ + +#ifndef __SIMPLE_H +#define __SIMPLE_H + +/* #include "quicc.h" */ + +#define GLB_SCC_0 0 +#define GLB_SCC_1 1 +#define GLB_SCC_2 2 +#define GLB_SCC_3 3 + +typedef void (int_routine)(unsigned short interrupt_event); +typedef int_routine *int_routine_ptr; +typedef void *(alloc_routine)(int length); +typedef void (free_routine)(int scc_num, int channel_num, void *buf); +typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length); +typedef int (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd); +typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd); +typedef void (handle_lost_error_routine)(int scc_num, int channel_num); + +/* user defined functions for global errors */ +typedef void (handle_glob_overrun_routine)(int scc_number); +typedef void (handle_glob_underrun_routine)(int scc_number); +typedef void (glob_intr_q_overflow_routine)(int scc_number); + +/* + * General initialization and command routines + */ +void quicc_issue_cmd (unsigned short cmd, int scc_num); +void quicc_init(void); +void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf); +void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf); +void quicc_scc_start(int scc_num); +void quicc_scc_loopback(int scc_num); + +/* Interrupt enable/disable routines for critical pieces of code*/ +unsigned short IntrDis(void); +void IntrEna(unsigned short old_sr); + +/* For debugging */ +void print_rbd(int scc_num); +void print_tbd(int scc_num); + +#endif diff --git a/arch/m68knommu/include/asm/resource.h b/arch/m68knommu/include/asm/resource.h new file mode 100644 index 000000000000..7fa63d5ea576 --- /dev/null +++ b/arch/m68knommu/include/asm/resource.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/rtc.h b/arch/m68knommu/include/asm/rtc.h new file mode 100644 index 000000000000..eaf18ec83c8e --- /dev/null +++ b/arch/m68knommu/include/asm/rtc.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/scatterlist.h b/arch/m68knommu/include/asm/scatterlist.h new file mode 100644 index 000000000000..afc4788b0d2c --- /dev/null +++ b/arch/m68knommu/include/asm/scatterlist.h @@ -0,0 +1,22 @@ +#ifndef _M68KNOMMU_SCATTERLIST_H +#define _M68KNOMMU_SCATTERLIST_H + +#include +#include + +struct scatterlist { +#ifdef CONFIG_DEBUG_SG + unsigned long sg_magic; +#endif + unsigned long page_link; + unsigned int offset; + dma_addr_t dma_address; + unsigned int length; +}; + +#define sg_dma_address(sg) ((sg)->dma_address) +#define sg_dma_len(sg) ((sg)->length) + +#define ISA_DMA_THRESHOLD (0xffffffff) + +#endif /* !(_M68KNOMMU_SCATTERLIST_H) */ diff --git a/arch/m68knommu/include/asm/sections.h b/arch/m68knommu/include/asm/sections.h new file mode 100644 index 000000000000..dd0ecb98ec08 --- /dev/null +++ b/arch/m68knommu/include/asm/sections.h @@ -0,0 +1,7 @@ +#ifndef _M68KNOMMU_SECTIONS_H +#define _M68KNOMMU_SECTIONS_H + +/* nothing to see, move along */ +#include + +#endif diff --git a/arch/m68knommu/include/asm/segment.h b/arch/m68knommu/include/asm/segment.h new file mode 100644 index 000000000000..42318ebec7ec --- /dev/null +++ b/arch/m68knommu/include/asm/segment.h @@ -0,0 +1,51 @@ +#ifndef _M68K_SEGMENT_H +#define _M68K_SEGMENT_H + +/* define constants */ +/* Address spaces (FC0-FC2) */ +#define USER_DATA (1) +#ifndef __USER_DS +#define __USER_DS (USER_DATA) +#endif +#define USER_PROGRAM (2) +#define SUPER_DATA (5) +#ifndef __KERNEL_DS +#define __KERNEL_DS (SUPER_DATA) +#endif +#define SUPER_PROGRAM (6) +#define CPU_SPACE (7) + +#ifndef __ASSEMBLY__ + +typedef struct { + unsigned long seg; +} mm_segment_t; + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) +#define USER_DS MAKE_MM_SEG(__USER_DS) +#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) + +/* + * Get/set the SFC/DFC registers for MOVES instructions + */ + +static inline mm_segment_t get_fs(void) +{ + return USER_DS; +} + +static inline mm_segment_t get_ds(void) +{ + /* return the supervisor data space code */ + return KERNEL_DS; +} + +static inline void set_fs(mm_segment_t val) +{ +} + +#define segment_eq(a,b) ((a).seg == (b).seg) + +#endif /* __ASSEMBLY__ */ + +#endif /* _M68K_SEGMENT_H */ diff --git a/arch/m68knommu/include/asm/sembuf.h b/arch/m68knommu/include/asm/sembuf.h new file mode 100644 index 000000000000..3a634f9ecf50 --- /dev/null +++ b/arch/m68knommu/include/asm/sembuf.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/setup.h b/arch/m68knommu/include/asm/setup.h new file mode 100644 index 000000000000..fb86bb2a6078 --- /dev/null +++ b/arch/m68knommu/include/asm/setup.h @@ -0,0 +1,10 @@ +#ifdef __KERNEL__ + +#include + +/* We have a bigger command line buffer. */ +#undef COMMAND_LINE_SIZE + +#endif /* __KERNEL__ */ + +#define COMMAND_LINE_SIZE 512 diff --git a/arch/m68knommu/include/asm/shm.h b/arch/m68knommu/include/asm/shm.h new file mode 100644 index 000000000000..cc8e522d9050 --- /dev/null +++ b/arch/m68knommu/include/asm/shm.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/shmbuf.h b/arch/m68knommu/include/asm/shmbuf.h new file mode 100644 index 000000000000..bc34cf8eefce --- /dev/null +++ b/arch/m68knommu/include/asm/shmbuf.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/shmparam.h b/arch/m68knommu/include/asm/shmparam.h new file mode 100644 index 000000000000..d7ee69648ebf --- /dev/null +++ b/arch/m68knommu/include/asm/shmparam.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/sigcontext.h b/arch/m68knommu/include/asm/sigcontext.h new file mode 100644 index 000000000000..36c293fc133d --- /dev/null +++ b/arch/m68knommu/include/asm/sigcontext.h @@ -0,0 +1,17 @@ +#ifndef _ASM_M68KNOMMU_SIGCONTEXT_H +#define _ASM_M68KNOMMU_SIGCONTEXT_H + +struct sigcontext { + unsigned long sc_mask; /* old sigmask */ + unsigned long sc_usp; /* old user stack pointer */ + unsigned long sc_d0; + unsigned long sc_d1; + unsigned long sc_a0; + unsigned long sc_a1; + unsigned long sc_a5; + unsigned short sc_sr; + unsigned long sc_pc; + unsigned short sc_formatvec; +}; + +#endif diff --git a/arch/m68knommu/include/asm/siginfo.h b/arch/m68knommu/include/asm/siginfo.h new file mode 100644 index 000000000000..b18e5f4064ae --- /dev/null +++ b/arch/m68knommu/include/asm/siginfo.h @@ -0,0 +1,6 @@ +#ifndef _M68KNOMMU_SIGINFO_H +#define _M68KNOMMU_SIGINFO_H + +#include + +#endif diff --git a/arch/m68knommu/include/asm/signal.h b/arch/m68knommu/include/asm/signal.h new file mode 100644 index 000000000000..216c08be54a0 --- /dev/null +++ b/arch/m68knommu/include/asm/signal.h @@ -0,0 +1,159 @@ +#ifndef _M68KNOMMU_SIGNAL_H +#define _M68KNOMMU_SIGNAL_H + +#include + +/* Avoid too many header ordering problems. */ +struct siginfo; + +#ifdef __KERNEL__ +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001 +#define SA_NOCLDWAIT 0x00000002 +#define SA_SIGINFO 0x00000004 +#define SA_ONSTACK 0x08000000 +#define SA_RESTART 0x10000000 +#define SA_NODEFER 0x40000000 +#define SA_RESETHAND 0x80000000 + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#include + +#ifdef __KERNEL__ +struct old_sigaction { + __sighandler_t sa_handler; + old_sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +struct sigaction { + __sighandler_t sa_handler; + unsigned long sa_flags; + void (*sa_restorer)(void); + sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct k_sigaction { + struct sigaction sa; +}; +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + +#ifdef __KERNEL__ + +#include +#undef __HAVE_ARCH_SIG_BITOPS + +#define ptrace_signal_deliver(regs, cookie) do { } while (0) + +#endif /* __KERNEL__ */ + +#endif /* _M68KNOMMU_SIGNAL_H */ diff --git a/arch/m68knommu/include/asm/smp.h b/arch/m68knommu/include/asm/smp.h new file mode 100644 index 000000000000..9e9bd7e58922 --- /dev/null +++ b/arch/m68knommu/include/asm/smp.h @@ -0,0 +1 @@ +/* nothing required here yet */ diff --git a/arch/m68knommu/include/asm/socket.h b/arch/m68knommu/include/asm/socket.h new file mode 100644 index 000000000000..ac5478bf6371 --- /dev/null +++ b/arch/m68knommu/include/asm/socket.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/sockios.h b/arch/m68knommu/include/asm/sockios.h new file mode 100644 index 000000000000..dcc6a8900ce2 --- /dev/null +++ b/arch/m68knommu/include/asm/sockios.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/spinlock.h b/arch/m68knommu/include/asm/spinlock.h new file mode 100644 index 000000000000..6bb1f06c4781 --- /dev/null +++ b/arch/m68knommu/include/asm/spinlock.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/stat.h b/arch/m68knommu/include/asm/stat.h new file mode 100644 index 000000000000..3d4b260e7c03 --- /dev/null +++ b/arch/m68knommu/include/asm/stat.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/statfs.h b/arch/m68knommu/include/asm/statfs.h new file mode 100644 index 000000000000..2ce99eaf0970 --- /dev/null +++ b/arch/m68knommu/include/asm/statfs.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/string.h b/arch/m68knommu/include/asm/string.h new file mode 100644 index 000000000000..af09e17000fc --- /dev/null +++ b/arch/m68knommu/include/asm/string.h @@ -0,0 +1,126 @@ +#ifndef _M68KNOMMU_STRING_H_ +#define _M68KNOMMU_STRING_H_ + +#ifdef __KERNEL__ /* only set these up for kernel code */ + +#include +#include + +#define __HAVE_ARCH_STRCPY +static inline char * strcpy(char * dest,const char *src) +{ + char *xdest = dest; + + __asm__ __volatile__ + ("1:\tmoveb %1@+,%0@+\n\t" + "jne 1b" + : "=a" (dest), "=a" (src) + : "0" (dest), "1" (src) : "memory"); + return xdest; +} + +#define __HAVE_ARCH_STRNCPY +static inline char * strncpy(char *dest, const char *src, size_t n) +{ + char *xdest = dest; + + if (n == 0) + return xdest; + + __asm__ __volatile__ + ("1:\tmoveb %1@+,%0@+\n\t" + "jeq 2f\n\t" + "subql #1,%2\n\t" + "jne 1b\n\t" + "2:" + : "=a" (dest), "=a" (src), "=d" (n) + : "0" (dest), "1" (src), "2" (n) + : "memory"); + return xdest; +} + + +#ifndef CONFIG_COLDFIRE + +#define __HAVE_ARCH_STRCMP +static inline int strcmp(const char * cs,const char * ct) +{ + char __res; + + __asm__ + ("1:\tmoveb %0@+,%2\n\t" /* get *cs */ + "cmpb %1@+,%2\n\t" /* compare a byte */ + "jne 2f\n\t" /* not equal, break out */ + "tstb %2\n\t" /* at end of cs? */ + "jne 1b\n\t" /* no, keep going */ + "jra 3f\n\t" /* strings are equal */ + "2:\tsubb %1@-,%2\n\t" /* *cs - *ct */ + "3:" + : "=a" (cs), "=a" (ct), "=d" (__res) + : "0" (cs), "1" (ct)); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +static inline int strncmp(const char * cs,const char * ct,size_t count) +{ + char __res; + + if (!count) + return 0; + __asm__ + ("1:\tmovb %0@+,%3\n\t" /* get *cs */ + "cmpb %1@+,%3\n\t" /* compare a byte */ + "jne 3f\n\t" /* not equal, break out */ + "tstb %3\n\t" /* at end of cs? */ + "jeq 4f\n\t" /* yes, all done */ + "subql #1,%2\n\t" /* no, adjust count */ + "jne 1b\n\t" /* more to do, keep going */ + "2:\tmoveq #0,%3\n\t" /* strings are equal */ + "jra 4f\n\t" + "3:\tsubb %1@-,%3\n\t" /* *cs - *ct */ + "4:" + : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res) + : "0" (cs), "1" (ct), "2" (count)); + return __res; +} + +#endif /* CONFIG_COLDFIRE */ + +#define __HAVE_ARCH_MEMSET +extern void * memset(void * s, int c, size_t count); + +#define __HAVE_ARCH_MEMCPY +extern void * memcpy(void *d, const void *s, size_t count); + +#else /* KERNEL */ + +/* + * let user libraries deal with these, + * IMHO the kernel has no place defining these functions for user apps + */ + +#define __HAVE_ARCH_STRCPY 1 +#define __HAVE_ARCH_STRNCPY 1 +#define __HAVE_ARCH_STRCAT 1 +#define __HAVE_ARCH_STRNCAT 1 +#define __HAVE_ARCH_STRCMP 1 +#define __HAVE_ARCH_STRNCMP 1 +#define __HAVE_ARCH_STRNICMP 1 +#define __HAVE_ARCH_STRCHR 1 +#define __HAVE_ARCH_STRRCHR 1 +#define __HAVE_ARCH_STRSTR 1 +#define __HAVE_ARCH_STRLEN 1 +#define __HAVE_ARCH_STRNLEN 1 +#define __HAVE_ARCH_MEMSET 1 +#define __HAVE_ARCH_MEMCPY 1 +#define __HAVE_ARCH_MEMMOVE 1 +#define __HAVE_ARCH_MEMSCAN 1 +#define __HAVE_ARCH_MEMCMP 1 +#define __HAVE_ARCH_MEMCHR 1 +#define __HAVE_ARCH_STRTOK 1 + +#endif /* KERNEL */ + +#endif /* _M68K_STRING_H_ */ diff --git a/arch/m68knommu/include/asm/system.h b/arch/m68knommu/include/asm/system.h new file mode 100644 index 000000000000..40f49de69821 --- /dev/null +++ b/arch/m68knommu/include/asm/system.h @@ -0,0 +1,324 @@ +#ifndef _M68KNOMMU_SYSTEM_H +#define _M68KNOMMU_SYSTEM_H + +#include +#include +#include + +/* + * switch_to(n) should switch tasks to task ptr, first checking that + * ptr isn't the current task, in which case it does nothing. This + * also clears the TS-flag if the task we switched to has used the + * math co-processor latest. + */ +/* + * switch_to() saves the extra registers, that are not saved + * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and + * a0-a1. Some of these are used by schedule() and its predecessors + * and so we might get see unexpected behaviors when a task returns + * with unexpected register values. + * + * syscall stores these registers itself and none of them are used + * by syscall after the function in the syscall has been called. + * + * Beware that resume now expects *next to be in d1 and the offset of + * tss to be in a1. This saves a few instructions as we no longer have + * to push them onto the stack and read them back right after. + * + * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) + * + * Changed 96/09/19 by Andreas Schwab + * pass prev in a0, next in a1, offset of tss in d1, and whether + * the mm structures are shared in d2 (to avoid atc flushing). + */ +asmlinkage void resume(void); +#define switch_to(prev,next,last) \ +{ \ + void *_last; \ + __asm__ __volatile__( \ + "movel %1, %%a0\n\t" \ + "movel %2, %%a1\n\t" \ + "jbsr resume\n\t" \ + "movel %%d1, %0\n\t" \ + : "=d" (_last) \ + : "d" (prev), "d" (next) \ + : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \ + (last) = _last; \ +} + +#ifdef CONFIG_COLDFIRE +#define local_irq_enable() __asm__ __volatile__ ( \ + "move %/sr,%%d0\n\t" \ + "andi.l #0xf8ff,%%d0\n\t" \ + "move %%d0,%/sr\n" \ + : /* no outputs */ \ + : \ + : "cc", "%d0", "memory") +#define local_irq_disable() __asm__ __volatile__ ( \ + "move %/sr,%%d0\n\t" \ + "ori.l #0x0700,%%d0\n\t" \ + "move %%d0,%/sr\n" \ + : /* no outputs */ \ + : \ + : "cc", "%d0", "memory") +/* For spinlocks etc */ +#define local_irq_save(x) __asm__ __volatile__ ( \ + "movew %%sr,%0\n\t" \ + "movew #0x0700,%%d0\n\t" \ + "or.l %0,%%d0\n\t" \ + "movew %%d0,%/sr" \ + : "=d" (x) \ + : \ + : "cc", "%d0", "memory") +#else + +/* portable version */ /* FIXME - see entry.h*/ +#define ALLOWINT 0xf8ff + +#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") +#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") +#endif + +#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") +#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") + +/* For spinlocks etc */ +#ifndef local_irq_save +#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0) +#endif + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + ((flags & 0x0700) == 0x0700); \ +}) + +#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") + +/* + * Force strict CPU ordering. + * Not really required on m68k... + */ +#define nop() asm volatile ("nop"::) +#define mb() asm volatile ("" : : :"memory") +#define rmb() asm volatile ("" : : :"memory") +#define wmb() asm volatile ("" : : :"memory") +#define set_mb(var, value) ({ (var) = (value); wmb(); }) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif + +#define read_barrier_depends() ((void)0) + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + +struct __xchg_dummy { unsigned long a[100]; }; +#define __xg(x) ((volatile struct __xchg_dummy *)(x)) + +#ifndef CONFIG_RMW_INSNS +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + unsigned long tmp, flags; + + local_irq_save(flags); + + switch (size) { + case 1: + __asm__ __volatile__ + ("moveb %2,%0\n\t" + "moveb %1,%2" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 2: + __asm__ __volatile__ + ("movew %2,%0\n\t" + "movew %1,%2" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 4: + __asm__ __volatile__ + ("movel %2,%0\n\t" + "movel %1,%2" + : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + } + local_irq_restore(flags); + return tmp; +} +#else +static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 1: + __asm__ __volatile__ + ("moveb %2,%0\n\t" + "1:\n\t" + "casb %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 2: + __asm__ __volatile__ + ("movew %2,%0\n\t" + "1:\n\t" + "casw %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + case 4: + __asm__ __volatile__ + ("movel %2,%0\n\t" + "1:\n\t" + "casl %0,%1,%2\n\t" + "jne 1b" + : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); + break; + } + return x; +} +#endif + +#include + +/* + * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make + * them available. + */ +#define cmpxchg_local(ptr, o, n) \ + ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ + (unsigned long)(n), sizeof(*(ptr)))) +#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) + +#ifndef CONFIG_SMP +#include +#endif + +#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \ + defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 ) +#define HARD_RESET_NOW() ({ \ + local_irq_disable(); \ + asm(" \ + moveal #0x10c00000, %a0; \ + moveb #0, 0xFFFFF300; \ + moveal 0(%a0), %sp; \ + moveal 4(%a0), %a0; \ + jmp (%a0); \ + "); \ +}) +#endif + +#ifdef CONFIG_COLDFIRE +#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) +/* + * Need to account for broken early mask of 5272 silicon. So don't + * jump through the original start address. Jump strait into the + * known start of the FLASH code. + */ +#define HARD_RESET_NOW() ({ \ + asm(" \ + movew #0x2700, %sr; \ + jmp 0xf0000400; \ + "); \ +}) +#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \ + defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) +#define HARD_RESET_NOW() ({ \ + asm(" \ + movew #0x2700, %sr; \ + moveal #0x10000044, %a0; \ + movel #0xffffffff, (%a0); \ + moveal #0x10000001, %a0; \ + moveb #0x00, (%a0); \ + moveal #0xf0000004, %a0; \ + moveal (%a0), %a0; \ + jmp (%a0); \ + "); \ +}) +#elif defined(CONFIG_M5272) +/* + * Retrieve the boot address in flash using CSBR0 and CSOR0 + * find the reset vector at flash_address + 4 (e.g. 0x400) + * remap it in the flash's current location (e.g. 0xf0000400) + * and jump there. + */ +#define HARD_RESET_NOW() ({ \ + asm(" \ + movew #0x2700, %%sr; \ + move.l %0+0x40,%%d0; \ + and.l %0+0x44,%%d0; \ + andi.l #0xfffff000,%%d0; \ + mov.l %%d0,%%a0; \ + or.l 4(%%a0),%%d0; \ + mov.l %%d0,%%a0; \ + jmp (%%a0);" \ + : /* No output */ \ + : "o" (*(char *)MCF_MBAR) ); \ +}) +#elif defined(CONFIG_M528x) +/* + * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR), + * that when set, resets the MCF528x. + */ +#define HARD_RESET_NOW() \ +({ \ + unsigned char volatile *reset; \ + asm("move.w #0x2700, %sr"); \ + reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \ + while(1) \ + *reset |= (0x01 << 7);\ +}) +#elif defined(CONFIG_M523x) +#define HARD_RESET_NOW() ({ \ + asm(" \ + movew #0x2700, %sr; \ + movel #0x01000000, %sp; \ + moveal #0x40110000, %a0; \ + moveb #0x80, (%a0); \ + "); \ +}) +#elif defined(CONFIG_M520x) + /* + * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register + * RCR), that when set, resets the MCF5208. + */ +#define HARD_RESET_NOW() \ +({ \ + unsigned char volatile *reset; \ + asm("move.w #0x2700, %sr"); \ + reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \ + while(1) \ + *reset |= 0x80; \ +}) +#else +#define HARD_RESET_NOW() ({ \ + asm(" \ + movew #0x2700, %sr; \ + moveal #0x4, %a0; \ + moveal (%a0), %a0; \ + jmp (%a0); \ + "); \ +}) +#endif +#endif +#define arch_align_stack(x) (x) + + +static inline int irqs_disabled_flags(unsigned long flags) +{ + if (flags & 0x0700) + return 0; + else + return 1; +} + +#endif /* _M68KNOMMU_SYSTEM_H */ diff --git a/arch/m68knommu/include/asm/termbits.h b/arch/m68knommu/include/asm/termbits.h new file mode 100644 index 000000000000..05dd6bc27285 --- /dev/null +++ b/arch/m68knommu/include/asm/termbits.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/termios.h b/arch/m68knommu/include/asm/termios.h new file mode 100644 index 000000000000..e7337881a985 --- /dev/null +++ b/arch/m68knommu/include/asm/termios.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/thread_info.h b/arch/m68knommu/include/asm/thread_info.h new file mode 100644 index 000000000000..0c9bc095f3f0 --- /dev/null +++ b/arch/m68knommu/include/asm/thread_info.h @@ -0,0 +1,98 @@ +/* thread_info.h: m68knommu low-level thread information + * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com) + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#include + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ + +/* + * Size of kernel stack for each process. This must be a power of 2... + */ +#ifdef CONFIG_4KSTACKS +#define THREAD_SIZE_ORDER (0) +#else +#define THREAD_SIZE_ORDER (1) +#endif + +/* + * for asm files, THREAD_SIZE is now generated by asm-offsets.c + */ +#define THREAD_SIZE (PAGE_SIZE< preemptable, <0 => BUG */ + struct restart_block restart_block; +}; + +/* + * macros/functions for gaining access to the thread information structure + */ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__( + "move.l %%sp, %0 \n\t" + "and.l %1, %0" + : "=&d"(ti) + : "di" (~(THREAD_SIZE-1)) + ); + return ti; +} + +#endif /* __ASSEMBLY__ */ + +#define PREEMPT_ACTIVE 0x4000000 + +/* + * thread information flag bit numbers + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_SIGPENDING 1 /* signal pending */ +#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling + TIF_NEED_RESCHED */ +#define TIF_MEMDIE 4 + +/* as above, but as bit values */ +#define _TIF_SYSCALL_TRACE (1< +#define CLOCK_TICK_RATE MCF_CLK +#else +#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ +#endif + +typedef unsigned long cycles_t; + +static inline cycles_t get_cycles(void) +{ + return 0; +} + +#endif diff --git a/arch/m68knommu/include/asm/tlb.h b/arch/m68knommu/include/asm/tlb.h new file mode 100644 index 000000000000..77a7c51ca299 --- /dev/null +++ b/arch/m68knommu/include/asm/tlb.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/tlbflush.h b/arch/m68knommu/include/asm/tlbflush.h new file mode 100644 index 000000000000..a470cfb803eb --- /dev/null +++ b/arch/m68knommu/include/asm/tlbflush.h @@ -0,0 +1,55 @@ +#ifndef _M68KNOMMU_TLBFLUSH_H +#define _M68KNOMMU_TLBFLUSH_H + +/* + * Copyright (C) 2000 Lineo, David McCullough + * Copyright (C) 2000-2002, Greg Ungerer + */ + +#include + +/* + * flush all user-space atc entries. + */ +static inline void __flush_tlb(void) +{ + BUG(); +} + +static inline void __flush_tlb_one(unsigned long addr) +{ + BUG(); +} + +#define flush_tlb() __flush_tlb() + +/* + * flush all atc entries (both kernel and user-space entries). + */ +static inline void flush_tlb_all(void) +{ + BUG(); +} + +static inline void flush_tlb_mm(struct mm_struct *mm) +{ + BUG(); +} + +static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) +{ + BUG(); +} + +static inline void flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ + BUG(); +} + +static inline void flush_tlb_kernel_page(unsigned long addr) +{ + BUG(); +} + +#endif /* _M68KNOMMU_TLBFLUSH_H */ diff --git a/arch/m68knommu/include/asm/topology.h b/arch/m68knommu/include/asm/topology.h new file mode 100644 index 000000000000..ca173e9f26ff --- /dev/null +++ b/arch/m68knommu/include/asm/topology.h @@ -0,0 +1,6 @@ +#ifndef _ASM_M68K_TOPOLOGY_H +#define _ASM_M68K_TOPOLOGY_H + +#include + +#endif /* _ASM_M68K_TOPOLOGY_H */ diff --git a/arch/m68knommu/include/asm/traps.h b/arch/m68knommu/include/asm/traps.h new file mode 100644 index 000000000000..d0671e5f8e29 --- /dev/null +++ b/arch/m68knommu/include/asm/traps.h @@ -0,0 +1,154 @@ +/* + * linux/include/asm/traps.h + * + * Copyright (C) 1993 Hamish Macdonald + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#ifndef _M68KNOMMU_TRAPS_H +#define _M68KNOMMU_TRAPS_H + +#ifndef __ASSEMBLY__ + +typedef void (*e_vector)(void); + +extern e_vector vectors[]; +extern void init_vectors(void); +extern void enable_vector(unsigned int irq); +extern void disable_vector(unsigned int irq); +extern void ack_vector(unsigned int irq); + +#endif + +#define VEC_BUSERR (2) +#define VEC_ADDRERR (3) +#define VEC_ILLEGAL (4) +#define VEC_ZERODIV (5) +#define VEC_CHK (6) +#define VEC_TRAP (7) +#define VEC_PRIV (8) +#define VEC_TRACE (9) +#define VEC_LINE10 (10) +#define VEC_LINE11 (11) +#define VEC_RESV1 (12) +#define VEC_COPROC (13) +#define VEC_FORMAT (14) +#define VEC_UNINT (15) +#define VEC_SPUR (24) +#define VEC_INT1 (25) +#define VEC_INT2 (26) +#define VEC_INT3 (27) +#define VEC_INT4 (28) +#define VEC_INT5 (29) +#define VEC_INT6 (30) +#define VEC_INT7 (31) +#define VEC_SYS (32) +#define VEC_TRAP1 (33) +#define VEC_TRAP2 (34) +#define VEC_TRAP3 (35) +#define VEC_TRAP4 (36) +#define VEC_TRAP5 (37) +#define VEC_TRAP6 (38) +#define VEC_TRAP7 (39) +#define VEC_TRAP8 (40) +#define VEC_TRAP9 (41) +#define VEC_TRAP10 (42) +#define VEC_TRAP11 (43) +#define VEC_TRAP12 (44) +#define VEC_TRAP13 (45) +#define VEC_TRAP14 (46) +#define VEC_TRAP15 (47) +#define VEC_FPBRUC (48) +#define VEC_FPIR (49) +#define VEC_FPDIVZ (50) +#define VEC_FPUNDER (51) +#define VEC_FPOE (52) +#define VEC_FPOVER (53) +#define VEC_FPNAN (54) +#define VEC_FPUNSUP (55) +#define VEC_UNIMPEA (60) +#define VEC_UNIMPII (61) +#define VEC_USER (64) + +#define VECOFF(vec) ((vec)<<2) + +#ifndef __ASSEMBLY__ + +/* Status register bits */ +#define PS_T (0x8000) +#define PS_S (0x2000) +#define PS_M (0x1000) +#define PS_C (0x0001) + +/* structure for stack frames */ + +struct frame { + struct pt_regs ptregs; + union { + struct { + unsigned long iaddr; /* instruction address */ + } fmt2; + struct { + unsigned long effaddr; /* effective address */ + } fmt3; + struct { + unsigned long effaddr; /* effective address */ + unsigned long pc; /* pc of faulted instr */ + } fmt4; + struct { + unsigned long effaddr; /* effective address */ + unsigned short ssw; /* special status word */ + unsigned short wb3s; /* write back 3 status */ + unsigned short wb2s; /* write back 2 status */ + unsigned short wb1s; /* write back 1 status */ + unsigned long faddr; /* fault address */ + unsigned long wb3a; /* write back 3 address */ + unsigned long wb3d; /* write back 3 data */ + unsigned long wb2a; /* write back 2 address */ + unsigned long wb2d; /* write back 2 data */ + unsigned long wb1a; /* write back 1 address */ + unsigned long wb1dpd0; /* write back 1 data/push data 0*/ + unsigned long pd1; /* push data 1*/ + unsigned long pd2; /* push data 2*/ + unsigned long pd3; /* push data 3*/ + } fmt7; + struct { + unsigned long iaddr; /* instruction address */ + unsigned short int1[4]; /* internal registers */ + } fmt9; + struct { + unsigned short int1; + unsigned short ssw; /* special status word */ + unsigned short isc; /* instruction stage c */ + unsigned short isb; /* instruction stage b */ + unsigned long daddr; /* data cycle fault address */ + unsigned short int2[2]; + unsigned long dobuf; /* data cycle output buffer */ + unsigned short int3[2]; + } fmta; + struct { + unsigned short int1; + unsigned short ssw; /* special status word */ + unsigned short isc; /* instruction stage c */ + unsigned short isb; /* instruction stage b */ + unsigned long daddr; /* data cycle fault address */ + unsigned short int2[2]; + unsigned long dobuf; /* data cycle output buffer */ + unsigned short int3[4]; + unsigned long baddr; /* stage B address */ + unsigned short int4[2]; + unsigned long dibuf; /* data cycle input buffer */ + unsigned short int5[3]; + unsigned ver : 4; /* stack frame version # */ + unsigned int6:12; + unsigned short int7[18]; + } fmtb; + } un; +}; + +#endif /* __ASSEMBLY__ */ + +#endif /* _M68KNOMMU_TRAPS_H */ diff --git a/arch/m68knommu/include/asm/types.h b/arch/m68knommu/include/asm/types.h new file mode 100644 index 000000000000..031238c2d180 --- /dev/null +++ b/arch/m68knommu/include/asm/types.h @@ -0,0 +1 @@ +#include diff --git a/arch/m68knommu/include/asm/uaccess.h b/arch/m68knommu/include/asm/uaccess.h new file mode 100644 index 000000000000..68bbe9b312f1 --- /dev/null +++ b/arch/m68knommu/include/asm/uaccess.h @@ -0,0 +1,181 @@ +#ifndef __M68KNOMMU_UACCESS_H +#define __M68KNOMMU_UACCESS_H + +/* + * User space memory access functions + */ +#include +#include +#include + +#include + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) + +/* + * It is not enough to just have access_ok check for a real RAM address. + * This would disallow the case of code/ro-data running XIP in flash/rom. + * Ideally we would check the possible flash ranges too, but that is + * currently not so easy. + */ +static inline int _access_ok(unsigned long addr, unsigned long size) +{ + return 1; +} + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry +{ + unsigned long insn, fixup; +}; + +/* Returns 0 if exception not found and fixup otherwise. */ +extern unsigned long search_exception_table(unsigned long); + + +/* + * These are the main single-value transfer routines. They automatically + * use the right size if we just have the right pointer type. + */ + +#define put_user(x, ptr) \ +({ \ + int __pu_err = 0; \ + typeof(*(ptr)) __pu_val = (x); \ + switch (sizeof (*(ptr))) { \ + case 1: \ + __put_user_asm(__pu_err, __pu_val, ptr, b); \ + break; \ + case 2: \ + __put_user_asm(__pu_err, __pu_val, ptr, w); \ + break; \ + case 4: \ + __put_user_asm(__pu_err, __pu_val, ptr, l); \ + break; \ + case 8: \ + memcpy(ptr, &__pu_val, sizeof (*(ptr))); \ + break; \ + default: \ + __pu_err = __put_user_bad(); \ + break; \ + } \ + __pu_err; \ +}) +#define __put_user(x, ptr) put_user(x, ptr) + +extern int __put_user_bad(void); + +/* + * Tell gcc we read from memory instead of writing: this is because + * we do not write to any memory gcc knows about, so there are no + * aliasing issues. + */ + +#define __ptr(x) ((unsigned long *)(x)) + +#define __put_user_asm(err,x,ptr,bwl) \ + __asm__ ("move" #bwl " %0,%1" \ + : /* no outputs */ \ + :"d" (x),"m" (*__ptr(ptr)) : "memory") + +#define get_user(x, ptr) \ +({ \ + int __gu_err = 0; \ + typeof(x) __gu_val = 0; \ + switch (sizeof(*(ptr))) { \ + case 1: \ + __get_user_asm(__gu_err, __gu_val, ptr, b, "=d"); \ + break; \ + case 2: \ + __get_user_asm(__gu_err, __gu_val, ptr, w, "=r"); \ + break; \ + case 4: \ + __get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \ + break; \ + case 8: \ + memcpy((void *) &__gu_val, ptr, sizeof (*(ptr))); \ + break; \ + default: \ + __gu_val = 0; \ + __gu_err = __get_user_bad(); \ + break; \ + } \ + (x) = (typeof(*(ptr))) __gu_val; \ + __gu_err; \ +}) +#define __get_user(x, ptr) get_user(x, ptr) + +extern int __get_user_bad(void); + +#define __get_user_asm(err,x,ptr,bwl,reg) \ + __asm__ ("move" #bwl " %1,%0" \ + : "=d" (x) \ + : "m" (*__ptr(ptr))) + +#define copy_from_user(to, from, n) (memcpy(to, from, n), 0) +#define copy_to_user(to, from, n) (memcpy(to, from, n), 0) + +#define __copy_from_user(to, from, n) copy_from_user(to, from, n) +#define __copy_to_user(to, from, n) copy_to_user(to, from, n) +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user + +#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) + +#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) + +/* + * Copy a null terminated string from userspace. + */ + +static inline long +strncpy_from_user(char *dst, const char *src, long count) +{ + char *tmp; + strncpy(dst, src, count); + for (tmp = dst; *tmp && count > 0; tmp++, count--) + ; + return(tmp - dst); /* DAVIDM should we count a NUL ? check getname */ +} + +/* + * Return the size of a string (including the ending 0) + * + * Return 0 on exception, a value greater than N if too long + */ +static inline long strnlen_user(const char *src, long n) +{ + return(strlen(src) + 1); /* DAVIDM make safer */ +} + +#define strlen_user(str) strnlen_user(str, 32767) + +/* + * Zero Userspace + */ + +static inline unsigned long +__clear_user(void *to, unsigned long n) +{ + memset(to, 0, n); + return 0; +} + +#define clear_user(to,n) __clear_user(to,n) + +#endif /* _M68KNOMMU_UACCESS_H */ diff --git a/arch/m68knommu/include/asm/ucontext.h b/arch/m68knommu/include/asm/ucontext.h new file mode 100644 index 000000000000..713a27f901cd --- /dev/null +++ b/arch/m68knommu/include/asm/ucontext.h @@ -0,0 +1,32 @@ +#ifndef _M68KNOMMU_UCONTEXT_H +#define _M68KNOMMU_UCONTEXT_H + +typedef int greg_t; +#define NGREG 18 +typedef greg_t gregset_t[NGREG]; + +typedef struct fpregset { + int f_pcr; + int f_psr; + int f_fpiaddr; + int f_fpregs[8][3]; +} fpregset_t; + +struct mcontext { + int version; + gregset_t gregs; + fpregset_t fpregs; +}; + +#define MCONTEXT_VERSION 2 + +struct ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct mcontext uc_mcontext; + unsigned long uc_filler[80]; + sigset_t uc_sigmask; /* mask last for extensibility */ +}; + +#endif diff --git a/arch/m68knommu/include/asm/unaligned.h b/arch/m68knommu/include/asm/unaligned.h new file mode 100644 index 000000000000..eb1ea4cb9a59 --- /dev/null +++ b/arch/m68knommu/include/asm/unaligned.h @@ -0,0 +1,25 @@ +#ifndef _ASM_M68KNOMMU_UNALIGNED_H +#define _ASM_M68KNOMMU_UNALIGNED_H + + +#ifdef CONFIG_COLDFIRE +#include +#include +#include + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#else +/* + * The m68k can do unaligned accesses itself. + */ +#include +#include + +#define get_unaligned __get_unaligned_be +#define put_unaligned __put_unaligned_be + +#endif + +#endif /* _ASM_M68KNOMMU_UNALIGNED_H */ diff --git a/arch/m68knommu/include/asm/unistd.h b/arch/m68knommu/include/asm/unistd.h new file mode 100644 index 000000000000..4ba98b9c5d79 --- /dev/null +++ b/arch/m68knommu/include/asm/unistd.h @@ -0,0 +1,366 @@ +#ifndef _ASM_M68K_UNISTD_H_ +#define _ASM_M68K_UNISTD_H_ + +/* + * This file contains the system call numbers. + */ + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_chown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl /* 110 */ not supported +#define __NR_vhangup 111 +#define __NR_idle /* 112 */ Obsolete +#define __NR_vm86 /* 113 */ not supported +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_cacheflush 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 +#define __NR_getpagesize 166 +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_lchown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_getpmsg 188 /* some people actually want streams */ +#define __NR_putpmsg 189 /* some people actually want streams */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_chown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_lchown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_getdents64 220 +#define __NR_gettid 221 +#define __NR_tkill 222 +#define __NR_setxattr 223 +#define __NR_lsetxattr 224 +#define __NR_fsetxattr 225 +#define __NR_getxattr 226 +#define __NR_lgetxattr 227 +#define __NR_fgetxattr 228 +#define __NR_listxattr 229 +#define __NR_llistxattr 230 +#define __NR_flistxattr 231 +#define __NR_removexattr 232 +#define __NR_lremovexattr 233 +#define __NR_fremovexattr 234 +#define __NR_futex 235 +#define __NR_sendfile64 236 +#define __NR_mincore 237 +#define __NR_madvise 238 +#define __NR_fcntl64 239 +#define __NR_readahead 240 +#define __NR_io_setup 241 +#define __NR_io_destroy 242 +#define __NR_io_getevents 243 +#define __NR_io_submit 244 +#define __NR_io_cancel 245 +#define __NR_fadvise64 246 +#define __NR_exit_group 247 +#define __NR_lookup_dcookie 248 +#define __NR_epoll_create 249 +#define __NR_epoll_ctl 250 +#define __NR_epoll_wait 251 +#define __NR_remap_file_pages 252 +#define __NR_set_tid_address 253 +#define __NR_timer_create 254 +#define __NR_timer_settime 255 +#define __NR_timer_gettime 256 +#define __NR_timer_getoverrun 257 +#define __NR_timer_delete 258 +#define __NR_clock_settime 259 +#define __NR_clock_gettime 260 +#define __NR_clock_getres 261 +#define __NR_clock_nanosleep 262 +#define __NR_statfs64 263 +#define __NR_fstatfs64 264 +#define __NR_tgkill 265 +#define __NR_utimes 266 +#define __NR_fadvise64_64 267 +#define __NR_mbind 268 +#define __NR_get_mempolicy 269 +#define __NR_set_mempolicy 270 +#define __NR_mq_open 271 +#define __NR_mq_unlink 272 +#define __NR_mq_timedsend 273 +#define __NR_mq_timedreceive 274 +#define __NR_mq_notify 275 +#define __NR_mq_getsetattr 276 +#define __NR_waitid 277 +#define __NR_vserver 278 +#define __NR_add_key 279 +#define __NR_request_key 280 +#define __NR_keyctl 281 +#define __NR_ioprio_set 282 +#define __NR_ioprio_get 283 +#define __NR_inotify_init 284 +#define __NR_inotify_add_watch 285 +#define __NR_inotify_rm_watch 286 +#define __NR_migrate_pages 287 +#define __NR_openat 288 +#define __NR_mkdirat 289 +#define __NR_mknodat 290 +#define __NR_fchownat 291 +#define __NR_futimesat 292 +#define __NR_fstatat64 293 +#define __NR_unlinkat 294 +#define __NR_renameat 295 +#define __NR_linkat 296 +#define __NR_symlinkat 297 +#define __NR_readlinkat 298 +#define __NR_fchmodat 299 +#define __NR_faccessat 300 +#define __NR_pselect6 301 +#define __NR_ppoll 302 +#define __NR_unshare 303 +#define __NR_set_robust_list 304 +#define __NR_get_robust_list 305 +#define __NR_splice 306 +#define __NR_sync_file_range 307 +#define __NR_tee 308 +#define __NR_vmsplice 309 +#define __NR_move_pages 310 +#define __NR_sched_setaffinity 311 +#define __NR_sched_getaffinity 312 +#define __NR_kexec_load 313 +#define __NR_getcpu 314 +#define __NR_epoll_pwait 315 +#define __NR_utimensat 316 +#define __NR_signalfd 317 +#define __NR_timerfd_create 318 +#define __NR_eventfd 319 +#define __NR_fallocate 320 +#define __NR_timerfd_settime 321 +#define __NR_timerfd_gettime 322 + +#ifdef __KERNEL__ + +#define NR_syscalls 323 + +#define __ARCH_WANT_IPC_PARSE_VERSION +#define __ARCH_WANT_OLD_READDIR +#define __ARCH_WANT_OLD_STAT +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_SGETMASK +#define __ARCH_WANT_SYS_SIGNAL +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_UTIME +#define __ARCH_WANT_SYS_WAITPID +#define __ARCH_WANT_SYS_SOCKETCALL +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_OLD_GETRLIMIT +#define __ARCH_WANT_SYS_OLDUMOUNT +#define __ARCH_WANT_SYS_SIGPENDING +#define __ARCH_WANT_SYS_SIGPROCMASK +#define __ARCH_WANT_SYS_RT_SIGACTION + +/* + * "Conditional" syscalls + * + * What we want is __attribute__((weak,alias("sys_ni_syscall"))), + * but it doesn't work on all toolchains, so we just do it by hand + */ +#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") + +#endif /* __KERNEL__ */ +#endif /* _ASM_M68K_UNISTD_H_ */ diff --git a/arch/m68knommu/include/asm/user.h b/arch/m68knommu/include/asm/user.h new file mode 100644 index 000000000000..a5a555b761c4 --- /dev/null +++ b/arch/m68knommu/include/asm/user.h @@ -0,0 +1 @@ +#include diff --git a/include/asm-m68knommu/Kbuild b/include/asm-m68knommu/Kbuild deleted file mode 100644 index c68e1680da01..000000000000 --- a/include/asm-m68knommu/Kbuild +++ /dev/null @@ -1 +0,0 @@ -include include/asm-generic/Kbuild.asm diff --git a/include/asm-m68knommu/MC68328.h b/include/asm-m68knommu/MC68328.h deleted file mode 100644 index a337e56d09bf..000000000000 --- a/include/asm-m68knommu/MC68328.h +++ /dev/null @@ -1,1266 +0,0 @@ - -/* include/asm-m68knommu/MC68328.h: '328 control registers - * - * Copyright (C) 1999 Vladimir Gurevich - * Bear & Hare Software, Inc. - * - * Based on include/asm-m68knommu/MC68332.h - * Copyright (C) 1998 Kenneth Albanowski , - * - */ - -#ifndef _MC68328_H_ -#define _MC68328_H_ - -#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) -#define WORD_REF(addr) (*((volatile unsigned short*)addr)) -#define LONG_REF(addr) (*((volatile unsigned long*)addr)) - -#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) -#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) - -/********** - * - * 0xFFFFF0xx -- System Control - * - **********/ - -/* - * System Control Register (SCR) - */ -#define SCR_ADDR 0xfffff000 -#define SCR BYTE_REF(SCR_ADDR) - -#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ -#define SCR_DMAP 0x04 /* Double Map */ -#define SCR_SO 0x08 /* Supervisor Only */ -#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ -#define SCR_PRV 0x20 /* Privilege Violation */ -#define SCR_WPV 0x40 /* Write Protect Violation */ -#define SCR_BETO 0x80 /* Bus-Error TimeOut */ - -/* - * Mask Revision Register - */ -#define MRR_ADDR 0xfffff004 -#define MRR LONG_REF(MRR_ADDR) - -/********** - * - * 0xFFFFF1xx -- Chip-Select logic - * - **********/ - -/********** - * - * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control - * - **********/ - -/* - * Group Base Address Registers - */ -#define GRPBASEA_ADDR 0xfffff100 -#define GRPBASEB_ADDR 0xfffff102 -#define GRPBASEC_ADDR 0xfffff104 -#define GRPBASED_ADDR 0xfffff106 - -#define GRPBASEA WORD_REF(GRPBASEA_ADDR) -#define GRPBASEB WORD_REF(GRPBASEB_ADDR) -#define GRPBASEC WORD_REF(GRPBASEC_ADDR) -#define GRPBASED WORD_REF(GRPBASED_ADDR) - -#define GRPBASE_V 0x0001 /* Valid */ -#define GRPBASE_GBA_MASK 0xfff0 /* Group Base Address (bits 31-20) */ - -/* - * Group Base Address Mask Registers - */ -#define GRPMASKA_ADDR 0xfffff108 -#define GRPMASKB_ADDR 0xfffff10a -#define GRPMASKC_ADDR 0xfffff10c -#define GRPMASKD_ADDR 0xfffff10e - -#define GRPMASKA WORD_REF(GRPMASKA_ADDR) -#define GRPMASKB WORD_REF(GRPMASKB_ADDR) -#define GRPMASKC WORD_REF(GRPMASKC_ADDR) -#define GRPMASKD WORD_REF(GRPMASKD_ADDR) - -#define GRMMASK_GMA_MASK 0xfffff0 /* Group Base Mask (bits 31-20) */ - -/* - * Chip-Select Option Registers (group A) - */ -#define CSA0_ADDR 0xfffff110 -#define CSA1_ADDR 0xfffff114 -#define CSA2_ADDR 0xfffff118 -#define CSA3_ADDR 0xfffff11c - -#define CSA0 LONG_REF(CSA0_ADDR) -#define CSA1 LONG_REF(CSA1_ADDR) -#define CSA2 LONG_REF(CSA2_ADDR) -#define CSA3 LONG_REF(CSA3_ADDR) - -#define CSA_WAIT_MASK 0x00000007 /* Wait State Selection */ -#define CSA_WAIT_SHIFT 0 -#define CSA_RO 0x00000008 /* Read-Only */ -#define CSA_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ -#define CSA_AM_SHIFT 8 -#define CSA_BUSW 0x00010000 /* Bus Width Select */ -#define CSA_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ -#define CSA_AC_SHIFT 24 - -/* - * Chip-Select Option Registers (group B) - */ -#define CSB0_ADDR 0xfffff120 -#define CSB1_ADDR 0xfffff124 -#define CSB2_ADDR 0xfffff128 -#define CSB3_ADDR 0xfffff12c - -#define CSB0 LONG_REF(CSB0_ADDR) -#define CSB1 LONG_REF(CSB1_ADDR) -#define CSB2 LONG_REF(CSB2_ADDR) -#define CSB3 LONG_REF(CSB3_ADDR) - -#define CSB_WAIT_MASK 0x00000007 /* Wait State Selection */ -#define CSB_WAIT_SHIFT 0 -#define CSB_RO 0x00000008 /* Read-Only */ -#define CSB_AM_MASK 0x0000ff00 /* Address Mask (bits 23-16) */ -#define CSB_AM_SHIFT 8 -#define CSB_BUSW 0x00010000 /* Bus Width Select */ -#define CSB_AC_MASK 0xff000000 /* Address Compare (bits 23-16) */ -#define CSB_AC_SHIFT 24 - -/* - * Chip-Select Option Registers (group C) - */ -#define CSC0_ADDR 0xfffff130 -#define CSC1_ADDR 0xfffff134 -#define CSC2_ADDR 0xfffff138 -#define CSC3_ADDR 0xfffff13c - -#define CSC0 LONG_REF(CSC0_ADDR) -#define CSC1 LONG_REF(CSC1_ADDR) -#define CSC2 LONG_REF(CSC2_ADDR) -#define CSC3 LONG_REF(CSC3_ADDR) - -#define CSC_WAIT_MASK 0x00000007 /* Wait State Selection */ -#define CSC_WAIT_SHIFT 0 -#define CSC_RO 0x00000008 /* Read-Only */ -#define CSC_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ -#define CSC_AM_SHIFT 4 -#define CSC_BUSW 0x00010000 /* Bus Width Select */ -#define CSC_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ -#define CSC_AC_SHIFT 20 - -/* - * Chip-Select Option Registers (group D) - */ -#define CSD0_ADDR 0xfffff140 -#define CSD1_ADDR 0xfffff144 -#define CSD2_ADDR 0xfffff148 -#define CSD3_ADDR 0xfffff14c - -#define CSD0 LONG_REF(CSD0_ADDR) -#define CSD1 LONG_REF(CSD1_ADDR) -#define CSD2 LONG_REF(CSD2_ADDR) -#define CSD3 LONG_REF(CSD3_ADDR) - -#define CSD_WAIT_MASK 0x00000007 /* Wait State Selection */ -#define CSD_WAIT_SHIFT 0 -#define CSD_RO 0x00000008 /* Read-Only */ -#define CSD_AM_MASK 0x0000fff0 /* Address Mask (bits 23-12) */ -#define CSD_AM_SHIFT 4 -#define CSD_BUSW 0x00010000 /* Bus Width Select */ -#define CSD_AC_MASK 0xfff00000 /* Address Compare (bits 23-12) */ -#define CSD_AC_SHIFT 20 - -/********** - * - * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control - * - **********/ - -/* - * PLL Control Register - */ -#define PLLCR_ADDR 0xfffff200 -#define PLLCR WORD_REF(PLLCR_ADDR) - -#define PLLCR_DISPLL 0x0008 /* Disable PLL */ -#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ -#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ -#define PLLCR_SYSCLK_SEL_SHIFT 8 -#define PLLCR_PIXCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ -#define PLLCR_PIXCLK_SEL_SHIFT 11 - -/* 'EZ328-compatible definitions */ -#define PLLCR_LCDCLK_SEL_MASK PLLCR_PIXCLK_SEL_MASK -#define PLLCR_LCDCLK_SEL_SHIFT PLLCR_PIXCLK_SEL_SHIFT - -/* - * PLL Frequency Select Register - */ -#define PLLFSR_ADDR 0xfffff202 -#define PLLFSR WORD_REF(PLLFSR_ADDR) - -#define PLLFSR_PC_MASK 0x00ff /* P Count */ -#define PLLFSR_PC_SHIFT 0 -#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ -#define PLLFSR_QC_SHIFT 8 -#define PLLFSR_PROT 0x4000 /* Protect P & Q */ -#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ - -/* - * Power Control Register - */ -#define PCTRL_ADDR 0xfffff207 -#define PCTRL BYTE_REF(PCTRL_ADDR) - -#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ -#define PCTRL_WIDTH_SHIFT 0 -#define PCTRL_STOP 0x40 /* Enter power-save mode immediately */ -#define PCTRL_PCEN 0x80 /* Power Control Enable */ - -/********** - * - * 0xFFFFF3xx -- Interrupt Controller - * - **********/ - -/* - * Interrupt Vector Register - */ -#define IVR_ADDR 0xfffff300 -#define IVR BYTE_REF(IVR_ADDR) - -#define IVR_VECTOR_MASK 0xF8 - -/* - * Interrupt control Register - */ -#define ICR_ADRR 0xfffff302 -#define ICR WORD_REF(ICR_ADDR) - -#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ -#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ -#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ -#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ -#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ -#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ -#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ -#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ - -/* - * Interrupt Mask Register - */ -#define IMR_ADDR 0xfffff304 -#define IMR LONG_REF(IMR_ADDR) - -/* - * Define the names for bit positions first. This is useful for - * request_irq - */ -#define SPIM_IRQ_NUM 0 /* SPI Master interrupt */ -#define TMR2_IRQ_NUM 1 /* Timer 2 interrupt */ -#define UART_IRQ_NUM 2 /* UART interrupt */ -#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ -#define RTC_IRQ_NUM 4 /* RTC interrupt */ -#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ -#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ -#define INT0_IRQ_NUM 8 /* External INT0 */ -#define INT1_IRQ_NUM 9 /* External INT1 */ -#define INT2_IRQ_NUM 10 /* External INT2 */ -#define INT3_IRQ_NUM 11 /* External INT3 */ -#define INT4_IRQ_NUM 12 /* External INT4 */ -#define INT5_IRQ_NUM 13 /* External INT5 */ -#define INT6_IRQ_NUM 14 /* External INT6 */ -#define INT7_IRQ_NUM 15 /* External INT7 */ -#define IRQ1_IRQ_NUM 16 /* IRQ1 */ -#define IRQ2_IRQ_NUM 17 /* IRQ2 */ -#define IRQ3_IRQ_NUM 18 /* IRQ3 */ -#define IRQ6_IRQ_NUM 19 /* IRQ6 */ -#define PEN_IRQ_NUM 20 /* Pen Interrupt */ -#define SPIS_IRQ_NUM 21 /* SPI Slave Interrupt */ -#define TMR1_IRQ_NUM 22 /* Timer 1 interrupt */ -#define IRQ7_IRQ_NUM 23 /* IRQ7 */ - -/* '328-compatible definitions */ -#define SPI_IRQ_NUM SPIM_IRQ_NUM -#define TMR_IRQ_NUM TMR1_IRQ_NUM - -/* - * Here go the bitmasks themselves - */ -#define IMR_MSPIM (1 << SPIM _IRQ_NUM) /* Mask SPI Master interrupt */ -#define IMR_MTMR2 (1 << TMR2_IRQ_NUM) /* Mask Timer 2 interrupt */ -#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ -#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ -#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ -#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ -#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ -#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ -#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ -#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ -#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ -#define IMR_MINT4 (1 << INT4_IRQ_NUM) /* Mask External INT4 */ -#define IMR_MINT5 (1 << INT5_IRQ_NUM) /* Mask External INT5 */ -#define IMR_MINT6 (1 << INT6_IRQ_NUM) /* Mask External INT6 */ -#define IMR_MINT7 (1 << INT7_IRQ_NUM) /* Mask External INT7 */ -#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ -#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ -#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ -#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ -#define IMR_MPEN (1 << PEN_IRQ_NUM) /* Mask Pen Interrupt */ -#define IMR_MSPIS (1 << SPIS_IRQ_NUM) /* Mask SPI Slave Interrupt */ -#define IMR_MTMR1 (1 << TMR1_IRQ_NUM) /* Mask Timer 1 interrupt */ -#define IMR_MIRQ7 (1 << IRQ7_IRQ_NUM) /* Mask IRQ7 */ - -/* 'EZ328-compatible definitions */ -#define IMR_MSPI IMR_MSPIM -#define IMR_MTMR IMR_MTMR1 - -/* - * Interrupt Wake-Up Enable Register - */ -#define IWR_ADDR 0xfffff308 -#define IWR LONG_REF(IWR_ADDR) - -#define IWR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ -#define IWR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ -#define IWR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define IWR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define IWR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define IWR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define IWR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ -#define IWR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define IWR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define IWR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define IWR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define IWR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ -#define IWR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ -#define IWR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ -#define IWR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ -#define IWR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define IWR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define IWR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define IWR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define IWR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ -#define IWR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ -#define IWR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ -#define IWR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ - -/* - * Interrupt Status Register - */ -#define ISR_ADDR 0xfffff30c -#define ISR LONG_REF(ISR_ADDR) - -#define ISR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ -#define ISR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ -#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ -#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define ISR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ -#define ISR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ -#define ISR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ -#define ISR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ -#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define ISR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ -#define ISR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ -#define ISR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ -#define ISR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ - -/* 'EZ328-compatible definitions */ -#define ISR_SPI ISR_SPIM -#define ISR_TMR ISR_TMR1 - -/* - * Interrupt Pending Register - */ -#define IPR_ADDR 0xfffff310 -#define IPR LONG_REF(IPR_ADDR) - -#define IPR_SPIM (1 << SPIM _IRQ_NUM) /* SPI Master interrupt */ -#define IPR_TMR2 (1 << TMR2_IRQ_NUM) /* Timer 2 interrupt */ -#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator int. */ -#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define IPR_INT4 (1 << INT4_IRQ_NUM) /* External INT4 */ -#define IPR_INT5 (1 << INT5_IRQ_NUM) /* External INT5 */ -#define IPR_INT6 (1 << INT6_IRQ_NUM) /* External INT6 */ -#define IPR_INT7 (1 << INT7_IRQ_NUM) /* External INT7 */ -#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define IPR_PEN (1 << PEN_IRQ_NUM) /* Pen Interrupt */ -#define IPR_SPIS (1 << SPIS_IRQ_NUM) /* SPI Slave Interrupt */ -#define IPR_TMR1 (1 << TMR1_IRQ_NUM) /* Timer 1 interrupt */ -#define IPR_IRQ7 (1 << IRQ7_IRQ_NUM) /* IRQ7 */ - -/* 'EZ328-compatible definitions */ -#define IPR_SPI IPR_SPIM -#define IPR_TMR IPR_TMR1 - -/********** - * - * 0xFFFFF4xx -- Parallel Ports - * - **********/ - -/* - * Port A - */ -#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ -#define PADATA_ADDR 0xfffff401 /* Port A data register */ -#define PASEL_ADDR 0xfffff403 /* Port A Select register */ - -#define PADIR BYTE_REF(PADIR_ADDR) -#define PADATA BYTE_REF(PADATA_ADDR) -#define PASEL BYTE_REF(PASEL_ADDR) - -#define PA(x) (1 << (x)) -#define PA_A(x) PA((x) - 16) /* This is specific to PA only! */ - -#define PA_A16 PA(0) /* Use A16 as PA(0) */ -#define PA_A17 PA(1) /* Use A17 as PA(1) */ -#define PA_A18 PA(2) /* Use A18 as PA(2) */ -#define PA_A19 PA(3) /* Use A19 as PA(3) */ -#define PA_A20 PA(4) /* Use A20 as PA(4) */ -#define PA_A21 PA(5) /* Use A21 as PA(5) */ -#define PA_A22 PA(6) /* Use A22 as PA(6) */ -#define PA_A23 PA(7) /* Use A23 as PA(7) */ - -/* - * Port B - */ -#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ -#define PBDATA_ADDR 0xfffff409 /* Port B data register */ -#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ - -#define PBDIR BYTE_REF(PBDIR_ADDR) -#define PBDATA BYTE_REF(PBDATA_ADDR) -#define PBSEL BYTE_REF(PBSEL_ADDR) - -#define PB(x) (1 << (x)) -#define PB_D(x) PB(x) /* This is specific to port B only */ - -#define PB_D0 PB(0) /* Use D0 as PB(0) */ -#define PB_D1 PB(1) /* Use D1 as PB(1) */ -#define PB_D2 PB(2) /* Use D2 as PB(2) */ -#define PB_D3 PB(3) /* Use D3 as PB(3) */ -#define PB_D4 PB(4) /* Use D4 as PB(4) */ -#define PB_D5 PB(5) /* Use D5 as PB(5) */ -#define PB_D6 PB(6) /* Use D6 as PB(6) */ -#define PB_D7 PB(7) /* Use D7 as PB(7) */ - -/* - * Port C - */ -#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ -#define PCDATA_ADDR 0xfffff411 /* Port C data register */ -#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ - -#define PCDIR BYTE_REF(PCDIR_ADDR) -#define PCDATA BYTE_REF(PCDATA_ADDR) -#define PCSEL BYTE_REF(PCSEL_ADDR) - -#define PC(x) (1 << (x)) - -#define PC_WE PC(6) /* Use WE as PC(6) */ -#define PC_DTACK PC(5) /* Use DTACK as PC(5) */ -#define PC_IRQ7 PC(4) /* Use IRQ7 as PC(4) */ -#define PC_LDS PC(2) /* Use LDS as PC(2) */ -#define PC_UDS PC(1) /* Use UDS as PC(1) */ -#define PC_MOCLK PC(0) /* Use MOCLK as PC(0) */ - -/* - * Port D - */ -#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ -#define PDDATA_ADDR 0xfffff419 /* Port D data register */ -#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ -#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ -#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ -#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ - -#define PDDIR BYTE_REF(PDDIR_ADDR) -#define PDDATA BYTE_REF(PDDATA_ADDR) -#define PDPUEN BYTE_REF(PDPUEN_ADDR) -#define PDPOL BYTE_REF(PDPOL_ADDR) -#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) -#define PDIQEG BYTE_REF(PDIQEG_ADDR) - -#define PD(x) (1 << (x)) -#define PD_KB(x) PD(x) /* This is specific for Port D only */ - -#define PD_KB0 PD(0) /* Use KB0 as PD(0) */ -#define PD_KB1 PD(1) /* Use KB1 as PD(1) */ -#define PD_KB2 PD(2) /* Use KB2 as PD(2) */ -#define PD_KB3 PD(3) /* Use KB3 as PD(3) */ -#define PD_KB4 PD(4) /* Use KB4 as PD(4) */ -#define PD_KB5 PD(5) /* Use KB5 as PD(5) */ -#define PD_KB6 PD(6) /* Use KB6 as PD(6) */ -#define PD_KB7 PD(7) /* Use KB7 as PD(7) */ - -/* - * Port E - */ -#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ -#define PEDATA_ADDR 0xfffff421 /* Port E data register */ -#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ -#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ - -#define PEDIR BYTE_REF(PEDIR_ADDR) -#define PEDATA BYTE_REF(PEDATA_ADDR) -#define PEPUEN BYTE_REF(PEPUEN_ADDR) -#define PESEL BYTE_REF(PESEL_ADDR) - -#define PE(x) (1 << (x)) - -#define PE_CSA1 PE(1) /* Use CSA1 as PE(1) */ -#define PE_CSA2 PE(2) /* Use CSA2 as PE(2) */ -#define PE_CSA3 PE(3) /* Use CSA3 as PE(3) */ -#define PE_CSB0 PE(4) /* Use CSB0 as PE(4) */ -#define PE_CSB1 PE(5) /* Use CSB1 as PE(5) */ -#define PE_CSB2 PE(6) /* Use CSB2 as PE(6) */ -#define PE_CSB3 PE(7) /* Use CSB3 as PE(7) */ - -/* - * Port F - */ -#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ -#define PFDATA_ADDR 0xfffff429 /* Port F data register */ -#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ -#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ - -#define PFDIR BYTE_REF(PFDIR_ADDR) -#define PFDATA BYTE_REF(PFDATA_ADDR) -#define PFPUEN BYTE_REF(PFPUEN_ADDR) -#define PFSEL BYTE_REF(PFSEL_ADDR) - -#define PF(x) (1 << (x)) -#define PF_A(x) PF((x) - 24) /* This is Port F specific only */ - -#define PF_A24 PF(0) /* Use A24 as PF(0) */ -#define PF_A25 PF(1) /* Use A25 as PF(1) */ -#define PF_A26 PF(2) /* Use A26 as PF(2) */ -#define PF_A27 PF(3) /* Use A27 as PF(3) */ -#define PF_A28 PF(4) /* Use A28 as PF(4) */ -#define PF_A29 PF(5) /* Use A29 as PF(5) */ -#define PF_A30 PF(6) /* Use A30 as PF(6) */ -#define PF_A31 PF(7) /* Use A31 as PF(7) */ - -/* - * Port G - */ -#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ -#define PGDATA_ADDR 0xfffff431 /* Port G data register */ -#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ -#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ - -#define PGDIR BYTE_REF(PGDIR_ADDR) -#define PGDATA BYTE_REF(PGDATA_ADDR) -#define PGPUEN BYTE_REF(PGPUEN_ADDR) -#define PGSEL BYTE_REF(PGSEL_ADDR) - -#define PG(x) (1 << (x)) - -#define PG_UART_TXD PG(0) /* Use UART_TXD as PG(0) */ -#define PG_UART_RXD PG(1) /* Use UART_RXD as PG(1) */ -#define PG_PWMOUT PG(2) /* Use PWMOUT as PG(2) */ -#define PG_TOUT2 PG(3) /* Use TOUT2 as PG(3) */ -#define PG_TIN2 PG(4) /* Use TIN2 as PG(4) */ -#define PG_TOUT1 PG(5) /* Use TOUT1 as PG(5) */ -#define PG_TIN1 PG(6) /* Use TIN1 as PG(6) */ -#define PG_RTCOUT PG(7) /* Use RTCOUT as PG(7) */ - -/* - * Port J - */ -#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ -#define PJDATA_ADDR 0xfffff439 /* Port J data register */ -#define PJSEL_ADDR 0xfffff43b /* Port J Select Register */ - -#define PJDIR BYTE_REF(PJDIR_ADDR) -#define PJDATA BYTE_REF(PJDATA_ADDR) -#define PJSEL BYTE_REF(PJSEL_ADDR) - -#define PJ(x) (1 << (x)) - -#define PJ_CSD3 PJ(7) /* Use CSD3 as PJ(7) */ - -/* - * Port K - */ -#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ -#define PKDATA_ADDR 0xfffff441 /* Port K data register */ -#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enable reg */ -#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ - -#define PKDIR BYTE_REF(PKDIR_ADDR) -#define PKDATA BYTE_REF(PKDATA_ADDR) -#define PKPUEN BYTE_REF(PKPUEN_ADDR) -#define PKSEL BYTE_REF(PKSEL_ADDR) - -#define PK(x) (1 << (x)) - -/* - * Port M - */ -#define PMDIR_ADDR 0xfffff438 /* Port M direction reg */ -#define PMDATA_ADDR 0xfffff439 /* Port M data register */ -#define PMPUEN_ADDR 0xfffff43a /* Port M Pull-Up enable reg */ -#define PMSEL_ADDR 0xfffff43b /* Port M Select Register */ - -#define PMDIR BYTE_REF(PMDIR_ADDR) -#define PMDATA BYTE_REF(PMDATA_ADDR) -#define PMPUEN BYTE_REF(PMPUEN_ADDR) -#define PMSEL BYTE_REF(PMSEL_ADDR) - -#define PM(x) (1 << (x)) - -/********** - * - * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) - * - **********/ - -/* - * PWM Control Register - */ -#define PWMC_ADDR 0xfffff500 -#define PWMC WORD_REF(PWMC_ADDR) - -#define PWMC_CLKSEL_MASK 0x0007 /* Clock Selection */ -#define PWMC_CLKSEL_SHIFT 0 -#define PWMC_PWMEN 0x0010 /* Enable PWM */ -#define PMNC_POL 0x0020 /* PWM Output Bit Polarity */ -#define PWMC_PIN 0x0080 /* Current PWM output pin status */ -#define PWMC_LOAD 0x0100 /* Force a new period */ -#define PWMC_IRQEN 0x4000 /* Interrupt Request Enable */ -#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ - -/* 'EZ328-compatible definitions */ -#define PWMC_EN PWMC_PWMEN - -/* - * PWM Period Register - */ -#define PWMP_ADDR 0xfffff502 -#define PWMP WORD_REF(PWMP_ADDR) - -/* - * PWM Width Register - */ -#define PWMW_ADDR 0xfffff504 -#define PWMW WORD_REF(PWMW_ADDR) - -/* - * PWM Counter Register - */ -#define PWMCNT_ADDR 0xfffff506 -#define PWMCNT WORD_REF(PWMCNT_ADDR) - -/********** - * - * 0xFFFFF6xx -- General-Purpose Timers - * - **********/ - -/* - * Timer Unit 1 and 2 Control Registers - */ -#define TCTL1_ADDR 0xfffff600 -#define TCTL1 WORD_REF(TCTL1_ADDR) -#define TCTL2_ADDR 0xfffff60c -#define TCTL2 WORD_REF(TCTL2_ADDR) - -#define TCTL_TEN 0x0001 /* Timer Enable */ -#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ -#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ -#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ -#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ -#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ -#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ -#define TCTL_IRQEN 0x0010 /* IRQ Enable */ -#define TCTL_OM 0x0020 /* Output Mode */ -#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ -#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ -#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ -#define TCTL_FRR 0x0010 /* Free-Run Mode */ - -/* 'EZ328-compatible definitions */ -#define TCTL_ADDR TCTL1_ADDR -#define TCTL TCTL1 - -/* - * Timer Unit 1 and 2 Prescaler Registers - */ -#define TPRER1_ADDR 0xfffff602 -#define TPRER1 WORD_REF(TPRER1_ADDR) -#define TPRER2_ADDR 0xfffff60e -#define TPRER2 WORD_REF(TPRER2_ADDR) - -/* 'EZ328-compatible definitions */ -#define TPRER_ADDR TPRER1_ADDR -#define TPRER TPRER1 - -/* - * Timer Unit 1 and 2 Compare Registers - */ -#define TCMP1_ADDR 0xfffff604 -#define TCMP1 WORD_REF(TCMP1_ADDR) -#define TCMP2_ADDR 0xfffff610 -#define TCMP2 WORD_REF(TCMP2_ADDR) - -/* 'EZ328-compatible definitions */ -#define TCMP_ADDR TCMP1_ADDR -#define TCMP TCMP1 - -/* - * Timer Unit 1 and 2 Capture Registers - */ -#define TCR1_ADDR 0xfffff606 -#define TCR1 WORD_REF(TCR1_ADDR) -#define TCR2_ADDR 0xfffff612 -#define TCR2 WORD_REF(TCR2_ADDR) - -/* 'EZ328-compatible definitions */ -#define TCR_ADDR TCR1_ADDR -#define TCR TCR1 - -/* - * Timer Unit 1 and 2 Counter Registers - */ -#define TCN1_ADDR 0xfffff608 -#define TCN1 WORD_REF(TCN1_ADDR) -#define TCN2_ADDR 0xfffff614 -#define TCN2 WORD_REF(TCN2_ADDR) - -/* 'EZ328-compatible definitions */ -#define TCN_ADDR TCN1_ADDR -#define TCN TCN - -/* - * Timer Unit 1 and 2 Status Registers - */ -#define TSTAT1_ADDR 0xfffff60a -#define TSTAT1 WORD_REF(TSTAT1_ADDR) -#define TSTAT2_ADDR 0xfffff616 -#define TSTAT2 WORD_REF(TSTAT2_ADDR) - -#define TSTAT_COMP 0x0001 /* Compare Event occurred */ -#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ - -/* 'EZ328-compatible definitions */ -#define TSTAT_ADDR TSTAT1_ADDR -#define TSTAT TSTAT1 - -/* - * Watchdog Compare Register - */ -#define WRR_ADDR 0xfffff61a -#define WRR WORD_REF(WRR_ADDR) - -/* - * Watchdog Counter Register - */ -#define WCN_ADDR 0xfffff61c -#define WCN WORD_REF(WCN_ADDR) - -/* - * Watchdog Control and Status Register - */ -#define WCSR_ADDR 0xfffff618 -#define WCSR WORD_REF(WCSR_ADDR) - -#define WCSR_WDEN 0x0001 /* Watchdog Enable */ -#define WCSR_FI 0x0002 /* Forced Interrupt (instead of SW reset)*/ -#define WCSR_WRST 0x0004 /* Watchdog Reset */ - -/********** - * - * 0xFFFFF7xx -- Serial Periferial Interface Slave (SPIS) - * - **********/ - -/* - * SPI Slave Register - */ -#define SPISR_ADDR 0xfffff700 -#define SPISR WORD_REF(SPISR_ADDR) - -#define SPISR_DATA_ADDR 0xfffff701 -#define SPISR_DATA BYTE_REF(SPISR_DATA_ADDR) - -#define SPISR_DATA_MASK 0x00ff /* Shifted data from the external device */ -#define SPISR_DATA_SHIFT 0 -#define SPISR_SPISEN 0x0100 /* SPIS module enable */ -#define SPISR_POL 0x0200 /* SPSCLK polarity control */ -#define SPISR_PHA 0x0400 /* Phase relationship between SPSCLK & SPSRxD */ -#define SPISR_OVWR 0x0800 /* Data buffer has been overwritten */ -#define SPISR_DATARDY 0x1000 /* Data ready */ -#define SPISR_ENPOL 0x2000 /* Enable Polarity */ -#define SPISR_IRQEN 0x4000 /* SPIS IRQ Enable */ -#define SPISR_SPISIRQ 0x8000 /* SPIS IRQ posted */ - -/********** - * - * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) - * - **********/ - -/* - * SPIM Data Register - */ -#define SPIMDATA_ADDR 0xfffff800 -#define SPIMDATA WORD_REF(SPIMDATA_ADDR) - -/* - * SPIM Control/Status Register - */ -#define SPIMCONT_ADDR 0xfffff802 -#define SPIMCONT WORD_REF(SPIMCONT_ADDR) - -#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ -#define SPIMCONT_BIT_COUNT_SHIFT 0 -#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ -#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ -#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ -#define SPIMCONT_SPIMIRQ 0x0080 /* Interrupt Request */ -#define SPIMCONT_XCH 0x0100 /* Exchange */ -#define SPIMCONT_RSPIMEN 0x0200 /* Enable SPIM */ -#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ -#define SPIMCONT_DATA_RATE_SHIFT 13 - -/* 'EZ328-compatible definitions */ -#define SPIMCONT_IRQ SPIMCONT_SPIMIRQ -#define SPIMCONT_ENABLE SPIMCONT_SPIMEN -/********** - * - * 0xFFFFF9xx -- UART - * - **********/ - -/* - * UART Status/Control Register - */ -#define USTCNT_ADDR 0xfffff900 -#define USTCNT WORD_REF(USTCNT_ADDR) - -#define USTCNT_TXAVAILEN 0x0001 /* Transmitter Available Int Enable */ -#define USTCNT_TXHALFEN 0x0002 /* Transmitter Half Empty Int Enable */ -#define USTCNT_TXEMPTYEN 0x0004 /* Transmitter Empty Int Enable */ -#define USTCNT_RXREADYEN 0x0008 /* Receiver Ready Interrupt Enable */ -#define USTCNT_RXHALFEN 0x0010 /* Receiver Half-Full Int Enable */ -#define USTCNT_RXFULLEN 0x0020 /* Receiver Full Interrupt Enable */ -#define USTCNT_CTSDELTAEN 0x0040 /* CTS Delta Interrupt Enable */ -#define USTCNT_GPIODELTAEN 0x0080 /* Old Data Interrupt Enable */ -#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ -#define USTCNT_STOP 0x0200 /* Stop bit transmission */ -#define USTCNT_ODD_EVEN 0x0400 /* Odd Parity */ -#define USTCNT_PARITYEN 0x0800 /* Parity Enable */ -#define USTCNT_CLKMODE 0x1000 /* Clock Mode Select */ -#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ -#define USTCNT_RXEN 0x4000 /* Receiver Enable */ -#define USTCNT_UARTEN 0x8000 /* UART Enable */ - -/* 'EZ328-compatible definitions */ -#define USTCNT_TXAE USTCNT_TXAVAILEN -#define USTCNT_TXHE USTCNT_TXHALFEN -#define USTCNT_TXEE USTCNT_TXEMPTYEN -#define USTCNT_RXRE USTCNT_RXREADYEN -#define USTCNT_RXHE USTCNT_RXHALFEN -#define USTCNT_RXFE USTCNT_RXFULLEN -#define USTCNT_CTSD USTCNT_CTSDELTAEN -#define USTCNT_ODD USTCNT_ODD_EVEN -#define USTCNT_PEN USTCNT_PARITYEN -#define USTCNT_CLKM USTCNT_CLKMODE -#define USTCNT_UEN USTCNT_UARTEN - -/* - * UART Baud Control Register - */ -#define UBAUD_ADDR 0xfffff902 -#define UBAUD WORD_REF(UBAUD_ADDR) - -#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ -#define UBAUD_PRESCALER_SHIFT 0 -#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ -#define UBAUD_DIVIDE_SHIFT 8 -#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ -#define UBAUD_GPIOSRC 0x1000 /* GPIO source */ -#define UBAUD_GPIODIR 0x2000 /* GPIO Direction */ -#define UBAUD_GPIO 0x4000 /* Current GPIO pin status */ -#define UBAUD_GPIODELTA 0x8000 /* GPIO pin value changed */ - -/* - * UART Receiver Register - */ -#define URX_ADDR 0xfffff904 -#define URX WORD_REF(URX_ADDR) - -#define URX_RXDATA_ADDR 0xfffff905 -#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) - -#define URX_RXDATA_MASK 0x00ff /* Received data */ -#define URX_RXDATA_SHIFT 0 -#define URX_PARITY_ERROR 0x0100 /* Parity Error */ -#define URX_BREAK 0x0200 /* Break Detected */ -#define URX_FRAME_ERROR 0x0400 /* Framing Error */ -#define URX_OVRUN 0x0800 /* Serial Overrun */ -#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ -#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ -#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ - -/* - * UART Transmitter Register - */ -#define UTX_ADDR 0xfffff906 -#define UTX WORD_REF(UTX_ADDR) - -#define UTX_TXDATA_ADDR 0xfffff907 -#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) - -#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ -#define UTX_TXDATA_SHIFT 0 -#define UTX_CTS_DELTA 0x0100 /* CTS changed */ -#define UTX_CTS_STATUS 0x0200 /* CTS State */ -#define UTX_IGNORE_CTS 0x0800 /* Ignore CTS */ -#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ -#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ -#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ -#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ - -/* 'EZ328-compatible definitions */ -#define UTX_CTS_STAT UTX_CTS_STATUS -#define UTX_NOCTS UTX_IGNORE_CTS - -/* - * UART Miscellaneous Register - */ -#define UMISC_ADDR 0xfffff908 -#define UMISC WORD_REF(UMISC_ADDR) - -#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ -#define UMISC_RX_POL 0x0008 /* Receive Polarity */ -#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ -#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ -#define UMISC_RTS 0x0040 /* Set RTS status */ -#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ -#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ -#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ -#define UMISC_CLKSRC 0x4000 /* Clock Source */ - - -/* generalization of uart control registers to support multiple ports: */ -typedef volatile struct { - volatile unsigned short int ustcnt; - volatile unsigned short int ubaud; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char rxdata; - } b; - } urx; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char txdata; - } b; - } utx; - volatile unsigned short int umisc; - volatile unsigned short int pad1; - volatile unsigned short int pad2; - volatile unsigned short int pad3; -} __attribute__((packed)) m68328_uart; - - -/********** - * - * 0xFFFFFAxx -- LCD Controller - * - **********/ - -/* - * LCD Screen Starting Address Register - */ -#define LSSA_ADDR 0xfffffa00 -#define LSSA LONG_REF(LSSA_ADDR) - -#define LSSA_SSA_MASK 0xfffffffe /* Bit 0 is reserved */ - -/* - * LCD Virtual Page Width Register - */ -#define LVPW_ADDR 0xfffffa05 -#define LVPW BYTE_REF(LVPW_ADDR) - -/* - * LCD Screen Width Register (not compatible with 'EZ328 !!!) - */ -#define LXMAX_ADDR 0xfffffa08 -#define LXMAX WORD_REF(LXMAX_ADDR) - -#define LXMAX_XM_MASK 0x02ff /* Bits 0-3 are reserved */ - -/* - * LCD Screen Height Register - */ -#define LYMAX_ADDR 0xfffffa0a -#define LYMAX WORD_REF(LYMAX_ADDR) - -#define LYMAX_YM_MASK 0x02ff /* Bits 10-15 are reserved */ - -/* - * LCD Cursor X Position Register - */ -#define LCXP_ADDR 0xfffffa18 -#define LCXP WORD_REF(LCXP_ADDR) - -#define LCXP_CC_MASK 0xc000 /* Cursor Control */ -#define LCXP_CC_TRAMSPARENT 0x0000 -#define LCXP_CC_BLACK 0x4000 -#define LCXP_CC_REVERSED 0x8000 -#define LCXP_CC_WHITE 0xc000 -#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ - -/* - * LCD Cursor Y Position Register - */ -#define LCYP_ADDR 0xfffffa1a -#define LCYP WORD_REF(LCYP_ADDR) - -#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ - -/* - * LCD Cursor Width and Heigth Register - */ -#define LCWCH_ADDR 0xfffffa1c -#define LCWCH WORD_REF(LCWCH_ADDR) - -#define LCWCH_CH_MASK 0x001f /* Cursor Height */ -#define LCWCH_CH_SHIFT 0 -#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ -#define LCWCH_CW_SHIFT 8 - -/* - * LCD Blink Control Register - */ -#define LBLKC_ADDR 0xfffffa1f -#define LBLKC BYTE_REF(LBLKC_ADDR) - -#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ -#define LBLKC_BD_SHIFT 0 -#define LBLKC_BKEN 0x80 /* Blink Enabled */ - -/* - * LCD Panel Interface Configuration Register - */ -#define LPICF_ADDR 0xfffffa20 -#define LPICF BYTE_REF(LPICF_ADDR) - -#define LPICF_GS_MASK 0x01 /* Gray-Scale Mode */ -#define LPICF_GS_BW 0x00 -#define LPICF_GS_GRAY_4 0x01 -#define LPICF_PBSIZ_MASK 0x06 /* Panel Bus Width */ -#define LPICF_PBSIZ_1 0x00 -#define LPICF_PBSIZ_2 0x02 -#define LPICF_PBSIZ_4 0x04 - -/* - * LCD Polarity Configuration Register - */ -#define LPOLCF_ADDR 0xfffffa21 -#define LPOLCF BYTE_REF(LPOLCF_ADDR) - -#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ -#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ -#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ -#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ - -/* - * LACD (LCD Alternate Crystal Direction) Rate Control Register - */ -#define LACDRC_ADDR 0xfffffa23 -#define LACDRC BYTE_REF(LACDRC_ADDR) - -#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ -#define LACDRC_ACD_SHIFT 0 - -/* - * LCD Pixel Clock Divider Register - */ -#define LPXCD_ADDR 0xfffffa25 -#define LPXCD BYTE_REF(LPXCD_ADDR) - -#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ -#define LPXCD_PCD_SHIFT 0 - -/* - * LCD Clocking Control Register - */ -#define LCKCON_ADDR 0xfffffa27 -#define LCKCON BYTE_REF(LCKCON_ADDR) - -#define LCKCON_PCDS 0x01 /* Pixel Clock Divider Source Select */ -#define LCKCON_DWIDTH 0x02 /* Display Memory Width */ -#define LCKCON_DWS_MASK 0x3c /* Display Wait-State */ -#define LCKCON_DWS_SHIFT 2 -#define LCKCON_DMA16 0x40 /* DMA burst length */ -#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ - -/* 'EZ328-compatible definitions */ -#define LCKCON_DW_MASK LCKCON_DWS_MASK -#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT - -/* - * LCD Last Buffer Address Register - */ -#define LLBAR_ADDR 0xfffffa29 -#define LLBAR BYTE_REF(LLBAR_ADDR) - -#define LLBAR_LBAR_MASK 0x7f /* Number of memory words to fill 1 line */ -#define LLBAR_LBAR_SHIFT 0 - -/* - * LCD Octet Terminal Count Register - */ -#define LOTCR_ADDR 0xfffffa2b -#define LOTCR BYTE_REF(LOTCR_ADDR) - -/* - * LCD Panning Offset Register - */ -#define LPOSR_ADDR 0xfffffa2d -#define LPOSR BYTE_REF(LPOSR_ADDR) - -#define LPOSR_BOS 0x08 /* Byte offset (for B/W mode only */ -#define LPOSR_POS_MASK 0x07 /* Pixel Offset Code */ -#define LPOSR_POS_SHIFT 0 - -/* - * LCD Frame Rate Control Modulation Register - */ -#define LFRCM_ADDR 0xfffffa31 -#define LFRCM BYTE_REF(LFRCM_ADDR) - -#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ -#define LFRCM_YMOD_SHIFT 0 -#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ -#define LFRCM_XMOD_SHIFT 4 - -/* - * LCD Gray Palette Mapping Register - */ -#define LGPMR_ADDR 0xfffffa32 -#define LGPMR WORD_REF(LGPMR_ADDR) - -#define LGPMR_GLEVEL3_MASK 0x000f -#define LGPMR_GLEVEL3_SHIFT 0 -#define LGPMR_GLEVEL2_MASK 0x00f0 -#define LGPMR_GLEVEL2_SHIFT 4 -#define LGPMR_GLEVEL0_MASK 0x0f00 -#define LGPMR_GLEVEL0_SHIFT 8 -#define LGPMR_GLEVEL1_MASK 0xf000 -#define LGPMR_GLEVEL1_SHIFT 12 - -/********** - * - * 0xFFFFFBxx -- Real-Time Clock (RTC) - * - **********/ - -/* - * RTC Hours Minutes and Seconds Register - */ -#define RTCTIME_ADDR 0xfffffb00 -#define RTCTIME LONG_REF(RTCTIME_ADDR) - -#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCTIME_SECONDS_SHIFT 0 -#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCTIME_MINUTES_SHIFT 16 -#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCTIME_HOURS_SHIFT 24 - -/* - * RTC Alarm Register - */ -#define RTCALRM_ADDR 0xfffffb04 -#define RTCALRM LONG_REF(RTCALRM_ADDR) - -#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCALRM_SECONDS_SHIFT 0 -#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCALRM_MINUTES_SHIFT 16 -#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCALRM_HOURS_SHIFT 24 - -/* - * RTC Control Register - */ -#define RTCCTL_ADDR 0xfffffb0c -#define RTCCTL WORD_REF(RTCCTL_ADDR) - -#define RTCCTL_384 0x0020 /* Crystal Selection */ -#define RTCCTL_ENABLE 0x0080 /* RTC Enable */ - -/* 'EZ328-compatible definitions */ -#define RTCCTL_XTL RTCCTL_384 -#define RTCCTL_EN RTCCTL_ENABLE - -/* - * RTC Interrupt Status Register - */ -#define RTCISR_ADDR 0xfffffb0e -#define RTCISR WORD_REF(RTCISR_ADDR) - -#define RTCISR_SW 0x0001 /* Stopwatch timed out */ -#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ -#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ -#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ -#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ - -/* - * RTC Interrupt Enable Register - */ -#define RTCIENR_ADDR 0xfffffb10 -#define RTCIENR WORD_REF(RTCIENR_ADDR) - -#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ -#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ -#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ -#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ -#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ - -/* - * Stopwatch Minutes Register - */ -#define STPWCH_ADDR 0xfffffb12 -#define STPWCH WORD_REF(STPWCH) - -#define STPWCH_CNT_MASK 0x00ff /* Stopwatch countdown value */ -#define SPTWCH_CNT_SHIFT 0 - -#endif /* _MC68328_H_ */ diff --git a/include/asm-m68knommu/MC68332.h b/include/asm-m68knommu/MC68332.h deleted file mode 100644 index 6bb8f02685a2..000000000000 --- a/include/asm-m68knommu/MC68332.h +++ /dev/null @@ -1,152 +0,0 @@ - -/* include/asm-m68knommu/MC68332.h: '332 control registers - * - * Copyright (C) 1998 Kenneth Albanowski , - * - */ - -#ifndef _MC68332_H_ -#define _MC68332_H_ - -#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) -#define WORD_REF(addr) (*((volatile unsigned short*)addr)) - -#define PORTE_ADDR 0xfffa11 -#define PORTE BYTE_REF(PORTE_ADDR) -#define DDRE_ADDR 0xfffa15 -#define DDRE BYTE_REF(DDRE_ADDR) -#define PEPAR_ADDR 0xfffa17 -#define PEPAR BYTE_REF(PEPAR_ADDR) - -#define PORTF_ADDR 0xfffa19 -#define PORTF BYTE_REF(PORTF_ADDR) -#define DDRF_ADDR 0xfffa1d -#define DDRF BYTE_REF(DDRF_ADDR) -#define PFPAR_ADDR 0xfffa1f -#define PFPAR BYTE_REF(PFPAR_ADDR) - -#define PORTQS_ADDR 0xfffc15 -#define PORTQS BYTE_REF(PORTQS_ADDR) -#define DDRQS_ADDR 0xfffc17 -#define DDRQS BYTE_REF(DDRQS_ADDR) -#define PQSPAR_ADDR 0xfffc16 -#define PQSPAR BYTE_REF(PQSPAR_ADDR) - -#define CSPAR0_ADDR 0xFFFA44 -#define CSPAR0 WORD_REF(CSPAR0_ADDR) -#define CSPAR1_ADDR 0xFFFA46 -#define CSPAR1 WORD_REF(CSPAR1_ADDR) -#define CSARBT_ADDR 0xFFFA48 -#define CSARBT WORD_REF(CSARBT_ADDR) -#define CSOPBT_ADDR 0xFFFA4A -#define CSOPBT WORD_REF(CSOPBT_ADDR) -#define CSBAR0_ADDR 0xFFFA4C -#define CSBAR0 WORD_REF(CSBAR0_ADDR) -#define CSOR0_ADDR 0xFFFA4E -#define CSOR0 WORD_REF(CSOR0_ADDR) -#define CSBAR1_ADDR 0xFFFA50 -#define CSBAR1 WORD_REF(CSBAR1_ADDR) -#define CSOR1_ADDR 0xFFFA52 -#define CSOR1 WORD_REF(CSOR1_ADDR) -#define CSBAR2_ADDR 0xFFFA54 -#define CSBAR2 WORD_REF(CSBAR2_ADDR) -#define CSOR2_ADDR 0xFFFA56 -#define CSOR2 WORD_REF(CSOR2_ADDR) -#define CSBAR3_ADDR 0xFFFA58 -#define CSBAR3 WORD_REF(CSBAR3_ADDR) -#define CSOR3_ADDR 0xFFFA5A -#define CSOR3 WORD_REF(CSOR3_ADDR) -#define CSBAR4_ADDR 0xFFFA5C -#define CSBAR4 WORD_REF(CSBAR4_ADDR) -#define CSOR4_ADDR 0xFFFA5E -#define CSOR4 WORD_REF(CSOR4_ADDR) -#define CSBAR5_ADDR 0xFFFA60 -#define CSBAR5 WORD_REF(CSBAR5_ADDR) -#define CSOR5_ADDR 0xFFFA62 -#define CSOR5 WORD_REF(CSOR5_ADDR) -#define CSBAR6_ADDR 0xFFFA64 -#define CSBAR6 WORD_REF(CSBAR6_ADDR) -#define CSOR6_ADDR 0xFFFA66 -#define CSOR6 WORD_REF(CSOR6_ADDR) -#define CSBAR7_ADDR 0xFFFA68 -#define CSBAR7 WORD_REF(CSBAR7_ADDR) -#define CSOR7_ADDR 0xFFFA6A -#define CSOR7 WORD_REF(CSOR7_ADDR) -#define CSBAR8_ADDR 0xFFFA6C -#define CSBAR8 WORD_REF(CSBAR8_ADDR) -#define CSOR8_ADDR 0xFFFA6E -#define CSOR8 WORD_REF(CSOR8_ADDR) -#define CSBAR9_ADDR 0xFFFA70 -#define CSBAR9 WORD_REF(CSBAR9_ADDR) -#define CSOR9_ADDR 0xFFFA72 -#define CSOR9 WORD_REF(CSOR9_ADDR) -#define CSBAR10_ADDR 0xFFFA74 -#define CSBAR10 WORD_REF(CSBAR10_ADDR) -#define CSOR10_ADDR 0xFFFA76 -#define CSOR10 WORD_REF(CSOR10_ADDR) - -#define CSOR_MODE_ASYNC 0x0000 -#define CSOR_MODE_SYNC 0x8000 -#define CSOR_MODE_MASK 0x8000 -#define CSOR_BYTE_DISABLE 0x0000 -#define CSOR_BYTE_UPPER 0x4000 -#define CSOR_BYTE_LOWER 0x2000 -#define CSOR_BYTE_BOTH 0x6000 -#define CSOR_BYTE_MASK 0x6000 -#define CSOR_RW_RSVD 0x0000 -#define CSOR_RW_READ 0x0800 -#define CSOR_RW_WRITE 0x1000 -#define CSOR_RW_BOTH 0x1800 -#define CSOR_RW_MASK 0x1800 -#define CSOR_STROBE_DS 0x0400 -#define CSOR_STROBE_AS 0x0000 -#define CSOR_STROBE_MASK 0x0400 -#define CSOR_DSACK_WAIT(x) (wait << 6) -#define CSOR_DSACK_FTERM (14 << 6) -#define CSOR_DSACK_EXTERNAL (15 << 6) -#define CSOR_DSACK_MASK 0x03c0 -#define CSOR_SPACE_CPU 0x0000 -#define CSOR_SPACE_USER 0x0010 -#define CSOR_SPACE_SU 0x0020 -#define CSOR_SPACE_BOTH 0x0030 -#define CSOR_SPACE_MASK 0x0030 -#define CSOR_IPL_ALL 0x0000 -#define CSOR_IPL_PRIORITY(x) (x << 1) -#define CSOR_IPL_MASK 0x000e -#define CSOR_AVEC_ON 0x0001 -#define CSOR_AVEC_OFF 0x0000 -#define CSOR_AVEC_MASK 0x0001 - -#define CSBAR_ADDR(x) ((addr >> 11) << 3) -#define CSBAR_ADDR_MASK 0xfff8 -#define CSBAR_BLKSIZE_2K 0x0000 -#define CSBAR_BLKSIZE_8K 0x0001 -#define CSBAR_BLKSIZE_16K 0x0002 -#define CSBAR_BLKSIZE_64K 0x0003 -#define CSBAR_BLKSIZE_128K 0x0004 -#define CSBAR_BLKSIZE_256K 0x0005 -#define CSBAR_BLKSIZE_512K 0x0006 -#define CSBAR_BLKSIZE_1M 0x0007 -#define CSBAR_BLKSIZE_MASK 0x0007 - -#define CSPAR_DISC 0 -#define CSPAR_ALT 1 -#define CSPAR_CS8 2 -#define CSPAR_CS16 3 -#define CSPAR_MASK 3 - -#define CSPAR0_CSBOOT(x) (x << 0) -#define CSPAR0_CS0(x) (x << 2) -#define CSPAR0_CS1(x) (x << 4) -#define CSPAR0_CS2(x) (x << 6) -#define CSPAR0_CS3(x) (x << 8) -#define CSPAR0_CS4(x) (x << 10) -#define CSPAR0_CS5(x) (x << 12) - -#define CSPAR1_CS6(x) (x << 0) -#define CSPAR1_CS7(x) (x << 2) -#define CSPAR1_CS8(x) (x << 4) -#define CSPAR1_CS9(x) (x << 6) -#define CSPAR1_CS10(x) (x << 8) - -#endif diff --git a/include/asm-m68knommu/MC68EZ328.h b/include/asm-m68knommu/MC68EZ328.h deleted file mode 100644 index 69b7f9139e5e..000000000000 --- a/include/asm-m68knommu/MC68EZ328.h +++ /dev/null @@ -1,1253 +0,0 @@ - -/* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers - * - * Copyright (C) 1999 Vladimir Gurevich - * Bear & Hare Software, Inc. - * - * Based on include/asm-m68knommu/MC68332.h - * Copyright (C) 1998 Kenneth Albanowski , - * The Silver Hammer Group, Ltd. - * - */ - -#ifndef _MC68EZ328_H_ -#define _MC68EZ328_H_ - -#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) -#define WORD_REF(addr) (*((volatile unsigned short*)addr)) -#define LONG_REF(addr) (*((volatile unsigned long*)addr)) - -#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) -#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) - -/********** - * - * 0xFFFFF0xx -- System Control - * - **********/ - -/* - * System Control Register (SCR) - */ -#define SCR_ADDR 0xfffff000 -#define SCR BYTE_REF(SCR_ADDR) - -#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ -#define SCR_DMAP 0x04 /* Double Map */ -#define SCR_SO 0x08 /* Supervisor Only */ -#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ -#define SCR_PRV 0x20 /* Privilege Violation */ -#define SCR_WPV 0x40 /* Write Protect Violation */ -#define SCR_BETO 0x80 /* Bus-Error TimeOut */ - -/* - * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) - */ -#define MRR_ADDR 0xfffff004 -#define MRR LONG_REF(MRR_ADDR) - -/********** - * - * 0xFFFFF1xx -- Chip-Select logic - * - **********/ - -/* - * Chip Select Group Base Registers - */ -#define CSGBA_ADDR 0xfffff100 -#define CSGBB_ADDR 0xfffff102 - -#define CSGBC_ADDR 0xfffff104 -#define CSGBD_ADDR 0xfffff106 - -#define CSGBA WORD_REF(CSGBA_ADDR) -#define CSGBB WORD_REF(CSGBB_ADDR) -#define CSGBC WORD_REF(CSGBC_ADDR) -#define CSGBD WORD_REF(CSGBD_ADDR) - -/* - * Chip Select Registers - */ -#define CSA_ADDR 0xfffff110 -#define CSB_ADDR 0xfffff112 -#define CSC_ADDR 0xfffff114 -#define CSD_ADDR 0xfffff116 - -#define CSA WORD_REF(CSA_ADDR) -#define CSB WORD_REF(CSB_ADDR) -#define CSC WORD_REF(CSC_ADDR) -#define CSD WORD_REF(CSD_ADDR) - -#define CSA_EN 0x0001 /* Chip-Select Enable */ -#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSA_SIZ_SHIFT 1 -#define CSA_WS_MASK 0x0070 /* Wait State */ -#define CSA_WS_SHIFT 4 -#define CSA_BSW 0x0080 /* Data Bus Width */ -#define CSA_FLASH 0x0100 /* FLASH Memory Support */ -#define CSA_RO 0x8000 /* Read-Only */ - -#define CSB_EN 0x0001 /* Chip-Select Enable */ -#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSB_SIZ_SHIFT 1 -#define CSB_WS_MASK 0x0070 /* Wait State */ -#define CSB_WS_SHIFT 4 -#define CSB_BSW 0x0080 /* Data Bus Width */ -#define CSB_FLASH 0x0100 /* FLASH Memory Support */ -#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSB_UPSIZ_SHIFT 11 -#define CSB_ROP 0x2000 /* Readonly if protected */ -#define CSB_SOP 0x4000 /* Supervisor only if protected */ -#define CSB_RO 0x8000 /* Read-Only */ - -#define CSC_EN 0x0001 /* Chip-Select Enable */ -#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSC_SIZ_SHIFT 1 -#define CSC_WS_MASK 0x0070 /* Wait State */ -#define CSC_WS_SHIFT 4 -#define CSC_BSW 0x0080 /* Data Bus Width */ -#define CSC_FLASH 0x0100 /* FLASH Memory Support */ -#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSC_UPSIZ_SHIFT 11 -#define CSC_ROP 0x2000 /* Readonly if protected */ -#define CSC_SOP 0x4000 /* Supervisor only if protected */ -#define CSC_RO 0x8000 /* Read-Only */ - -#define CSD_EN 0x0001 /* Chip-Select Enable */ -#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSD_SIZ_SHIFT 1 -#define CSD_WS_MASK 0x0070 /* Wait State */ -#define CSD_WS_SHIFT 4 -#define CSD_BSW 0x0080 /* Data Bus Width */ -#define CSD_FLASH 0x0100 /* FLASH Memory Support */ -#define CSD_DRAM 0x0200 /* Dram Selection */ -#define CSD_COMB 0x0400 /* Combining */ -#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSD_UPSIZ_SHIFT 11 -#define CSD_ROP 0x2000 /* Readonly if protected */ -#define CSD_SOP 0x4000 /* Supervisor only if protected */ -#define CSD_RO 0x8000 /* Read-Only */ - -/* - * Emulation Chip-Select Register - */ -#define EMUCS_ADDR 0xfffff118 -#define EMUCS WORD_REF(EMUCS_ADDR) - -#define EMUCS_WS_MASK 0x0070 -#define EMUCS_WS_SHIFT 4 - -/********** - * - * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control - * - **********/ - -/* - * PLL Control Register - */ -#define PLLCR_ADDR 0xfffff200 -#define PLLCR WORD_REF(PLLCR_ADDR) - -#define PLLCR_DISPLL 0x0008 /* Disable PLL */ -#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ -#define PLLCR_PRESC 0x0020 /* VCO prescaler */ -#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ -#define PLLCR_SYSCLK_SEL_SHIFT 8 -#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ -#define PLLCR_LCDCLK_SEL_SHIFT 11 - -/* '328-compatible definitions */ -#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK -#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT - -/* - * PLL Frequency Select Register - */ -#define PLLFSR_ADDR 0xfffff202 -#define PLLFSR WORD_REF(PLLFSR_ADDR) - -#define PLLFSR_PC_MASK 0x00ff /* P Count */ -#define PLLFSR_PC_SHIFT 0 -#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ -#define PLLFSR_QC_SHIFT 8 -#define PLLFSR_PROT 0x4000 /* Protect P & Q */ -#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ - -/* - * Power Control Register - */ -#define PCTRL_ADDR 0xfffff207 -#define PCTRL BYTE_REF(PCTRL_ADDR) - -#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ -#define PCTRL_WIDTH_SHIFT 0 -#define PCTRL_PCEN 0x80 /* Power Control Enable */ - -/********** - * - * 0xFFFFF3xx -- Interrupt Controller - * - **********/ - -/* - * Interrupt Vector Register - */ -#define IVR_ADDR 0xfffff300 -#define IVR BYTE_REF(IVR_ADDR) - -#define IVR_VECTOR_MASK 0xF8 - -/* - * Interrupt control Register - */ -#define ICR_ADDR 0xfffff302 -#define ICR WORD_REF(ICR_ADDR) - -#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ -#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ -#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ -#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ -#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ -#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ -#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ -#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ -#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ - -/* - * Interrupt Mask Register - */ -#define IMR_ADDR 0xfffff304 -#define IMR LONG_REF(IMR_ADDR) - -/* - * Define the names for bit positions first. This is useful for - * request_irq - */ -#define SPI_IRQ_NUM 0 /* SPI interrupt */ -#define TMR_IRQ_NUM 1 /* Timer interrupt */ -#define UART_IRQ_NUM 2 /* UART interrupt */ -#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ -#define RTC_IRQ_NUM 4 /* RTC interrupt */ -#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ -#define PWM_IRQ_NUM 7 /* Pulse-Width Modulator int. */ -#define INT0_IRQ_NUM 8 /* External INT0 */ -#define INT1_IRQ_NUM 9 /* External INT1 */ -#define INT2_IRQ_NUM 10 /* External INT2 */ -#define INT3_IRQ_NUM 11 /* External INT3 */ -#define IRQ1_IRQ_NUM 16 /* IRQ1 */ -#define IRQ2_IRQ_NUM 17 /* IRQ2 */ -#define IRQ3_IRQ_NUM 18 /* IRQ3 */ -#define IRQ6_IRQ_NUM 19 /* IRQ6 */ -#define IRQ5_IRQ_NUM 20 /* IRQ5 */ -#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ -#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ - -/* '328-compatible definitions */ -#define SPIM_IRQ_NUM SPI_IRQ_NUM -#define TMR1_IRQ_NUM TMR_IRQ_NUM - -/* - * Here go the bitmasks themselves - */ -#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ -#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ -#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ -#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ -#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ -#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ -#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ -#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ -#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ -#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ -#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ -#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ -#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ -#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ -#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ -#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ -#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ -#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ - -/* '328-compatible definitions */ -#define IMR_MSPIM IMR_MSPI -#define IMR_MTMR1 IMR_MTMR - -/* - * Interrupt Status Register - */ -#define ISR_ADDR 0xfffff30c -#define ISR LONG_REF(ISR_ADDR) - -#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ -#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ -#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ -#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ -#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ -#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ - -/* '328-compatible definitions */ -#define ISR_SPIM ISR_SPI -#define ISR_TMR1 ISR_TMR - -/* - * Interrupt Pending Register - */ -#define IPR_ADDR 0xfffff30c -#define IPR LONG_REF(IPR_ADDR) - -#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ -#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ -#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ -#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ -#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ -#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ - -/* '328-compatible definitions */ -#define IPR_SPIM IPR_SPI -#define IPR_TMR1 IPR_TMR - -/********** - * - * 0xFFFFF4xx -- Parallel Ports - * - **********/ - -/* - * Port A - */ -#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ -#define PADATA_ADDR 0xfffff401 /* Port A data register */ -#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ - -#define PADIR BYTE_REF(PADIR_ADDR) -#define PADATA BYTE_REF(PADATA_ADDR) -#define PAPUEN BYTE_REF(PAPUEN_ADDR) - -#define PA(x) (1 << (x)) - -/* - * Port B - */ -#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ -#define PBDATA_ADDR 0xfffff409 /* Port B data register */ -#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ -#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ - -#define PBDIR BYTE_REF(PBDIR_ADDR) -#define PBDATA BYTE_REF(PBDATA_ADDR) -#define PBPUEN BYTE_REF(PBPUEN_ADDR) -#define PBSEL BYTE_REF(PBSEL_ADDR) - -#define PB(x) (1 << (x)) - -#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ -#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ -#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ -#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ -#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ -#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ -#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ -#define PB_PWMO 0x80 /* Use PWMO as PB[7] */ - -/* - * Port C - */ -#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ -#define PCDATA_ADDR 0xfffff411 /* Port C data register */ -#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ -#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ - -#define PCDIR BYTE_REF(PCDIR_ADDR) -#define PCDATA BYTE_REF(PCDATA_ADDR) -#define PCPDEN BYTE_REF(PCPDEN_ADDR) -#define PCSEL BYTE_REF(PCSEL_ADDR) - -#define PC(x) (1 << (x)) - -#define PC_LD0 0x01 /* Use LD0 as PC[0] */ -#define PC_LD1 0x02 /* Use LD1 as PC[1] */ -#define PC_LD2 0x04 /* Use LD2 as PC[2] */ -#define PC_LD3 0x08 /* Use LD3 as PC[3] */ -#define PC_LFLM 0x10 /* Use LFLM as PC[4] */ -#define PC_LLP 0x20 /* Use LLP as PC[5] */ -#define PC_LCLK 0x40 /* Use LCLK as PC[6] */ -#define PC_LACD 0x80 /* Use LACD as PC[7] */ - -/* - * Port D - */ -#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ -#define PDDATA_ADDR 0xfffff419 /* Port D data register */ -#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ -#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ -#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ -#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ -#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ -#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ - -#define PDDIR BYTE_REF(PDDIR_ADDR) -#define PDDATA BYTE_REF(PDDATA_ADDR) -#define PDPUEN BYTE_REF(PDPUEN_ADDR) -#define PDSEL BYTE_REF(PDSEL_ADDR) -#define PDPOL BYTE_REF(PDPOL_ADDR) -#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) -#define PDKBEN BYTE_REF(PDKBEN_ADDR) -#define PDIQEG BYTE_REF(PDIQEG_ADDR) - -#define PD(x) (1 << (x)) - -#define PD_INT0 0x01 /* Use INT0 as PD[0] */ -#define PD_INT1 0x02 /* Use INT1 as PD[1] */ -#define PD_INT2 0x04 /* Use INT2 as PD[2] */ -#define PD_INT3 0x08 /* Use INT3 as PD[3] */ -#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ -#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ -#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ -#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ - -/* - * Port E - */ -#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ -#define PEDATA_ADDR 0xfffff421 /* Port E data register */ -#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ -#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ - -#define PEDIR BYTE_REF(PEDIR_ADDR) -#define PEDATA BYTE_REF(PEDATA_ADDR) -#define PEPUEN BYTE_REF(PEPUEN_ADDR) -#define PESEL BYTE_REF(PESEL_ADDR) - -#define PE(x) (1 << (x)) - -#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ -#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ -#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ -#define PE_DWE 0x08 /* Use DWE as PE[3] */ -#define PE_RXD 0x10 /* Use RXD as PE[4] */ -#define PE_TXD 0x20 /* Use TXD as PE[5] */ -#define PE_RTS 0x40 /* Use RTS as PE[6] */ -#define PE_CTS 0x80 /* Use CTS as PE[7] */ - -/* - * Port F - */ -#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ -#define PFDATA_ADDR 0xfffff429 /* Port F data register */ -#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ -#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ - -#define PFDIR BYTE_REF(PFDIR_ADDR) -#define PFDATA BYTE_REF(PFDATA_ADDR) -#define PFPUEN BYTE_REF(PFPUEN_ADDR) -#define PFSEL BYTE_REF(PFSEL_ADDR) - -#define PF(x) (1 << (x)) - -#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ -#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ -#define PF_CLKO 0x04 /* Use CLKO as PF[2] */ -#define PF_A20 0x08 /* Use A20 as PF[3] */ -#define PF_A21 0x10 /* Use A21 as PF[4] */ -#define PF_A22 0x20 /* Use A22 as PF[5] */ -#define PF_A23 0x40 /* Use A23 as PF[6] */ -#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ - -/* - * Port G - */ -#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ -#define PGDATA_ADDR 0xfffff431 /* Port G data register */ -#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ -#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ - -#define PGDIR BYTE_REF(PGDIR_ADDR) -#define PGDATA BYTE_REF(PGDATA_ADDR) -#define PGPUEN BYTE_REF(PGPUEN_ADDR) -#define PGSEL BYTE_REF(PGSEL_ADDR) - -#define PG(x) (1 << (x)) - -#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ -#define PG_A0 0x02 /* Use A0 as PG[1] */ -#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ -#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ -#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ -#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ - -/********** - * - * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) - * - **********/ - -/* - * PWM Control Register - */ -#define PWMC_ADDR 0xfffff500 -#define PWMC WORD_REF(PWMC_ADDR) - -#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ -#define PWMC_CLKSEL_SHIFT 0 -#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ -#define PWMC_REPEAT_SHIFT 2 -#define PWMC_EN 0x0010 /* Enable PWM */ -#define PMNC_FIFOAV 0x0020 /* FIFO Available */ -#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ -#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ -#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ -#define PWMC_PRESCALER_SHIFT 8 -#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ - -/* '328-compatible definitions */ -#define PWMC_PWMEN PWMC_EN - -/* - * PWM Sample Register - */ -#define PWMS_ADDR 0xfffff502 -#define PWMS WORD_REF(PWMS_ADDR) - -/* - * PWM Period Register - */ -#define PWMP_ADDR 0xfffff504 -#define PWMP BYTE_REF(PWMP_ADDR) - -/* - * PWM Counter Register - */ -#define PWMCNT_ADDR 0xfffff505 -#define PWMCNT BYTE_REF(PWMCNT_ADDR) - -/********** - * - * 0xFFFFF6xx -- General-Purpose Timer - * - **********/ - -/* - * Timer Control register - */ -#define TCTL_ADDR 0xfffff600 -#define TCTL WORD_REF(TCTL_ADDR) - -#define TCTL_TEN 0x0001 /* Timer Enable */ -#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ -#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ -#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ -#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ -#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ -#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ -#define TCTL_IRQEN 0x0010 /* IRQ Enable */ -#define TCTL_OM 0x0020 /* Output Mode */ -#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ -#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ -#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ -#define TCTL_FRR 0x0010 /* Free-Run Mode */ - -/* '328-compatible definitions */ -#define TCTL1_ADDR TCTL_ADDR -#define TCTL1 TCTL - -/* - * Timer Prescaler Register - */ -#define TPRER_ADDR 0xfffff602 -#define TPRER WORD_REF(TPRER_ADDR) - -/* '328-compatible definitions */ -#define TPRER1_ADDR TPRER_ADDR -#define TPRER1 TPRER - -/* - * Timer Compare Register - */ -#define TCMP_ADDR 0xfffff604 -#define TCMP WORD_REF(TCMP_ADDR) - -/* '328-compatible definitions */ -#define TCMP1_ADDR TCMP_ADDR -#define TCMP1 TCMP - -/* - * Timer Capture register - */ -#define TCR_ADDR 0xfffff606 -#define TCR WORD_REF(TCR_ADDR) - -/* '328-compatible definitions */ -#define TCR1_ADDR TCR_ADDR -#define TCR1 TCR - -/* - * Timer Counter Register - */ -#define TCN_ADDR 0xfffff608 -#define TCN WORD_REF(TCN_ADDR) - -/* '328-compatible definitions */ -#define TCN1_ADDR TCN_ADDR -#define TCN1 TCN - -/* - * Timer Status Register - */ -#define TSTAT_ADDR 0xfffff60a -#define TSTAT WORD_REF(TSTAT_ADDR) - -#define TSTAT_COMP 0x0001 /* Compare Event occurred */ -#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ - -/* '328-compatible definitions */ -#define TSTAT1_ADDR TSTAT_ADDR -#define TSTAT1 TSTAT - -/********** - * - * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) - * - **********/ - -/* - * SPIM Data Register - */ -#define SPIMDATA_ADDR 0xfffff800 -#define SPIMDATA WORD_REF(SPIMDATA_ADDR) - -/* - * SPIM Control/Status Register - */ -#define SPIMCONT_ADDR 0xfffff802 -#define SPIMCONT WORD_REF(SPIMCONT_ADDR) - -#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ -#define SPIMCONT_BIT_COUNT_SHIFT 0 -#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ -#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ -#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ -#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ -#define SPIMCONT_XCH 0x0100 /* Exchange */ -#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ -#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ -#define SPIMCONT_DATA_RATE_SHIFT 13 - -/* '328-compatible definitions */ -#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ -#define SPIMCONT_SPIMEN SPIMCONT_ENABLE - -/********** - * - * 0xFFFFF9xx -- UART - * - **********/ - -/* - * UART Status/Control Register - */ -#define USTCNT_ADDR 0xfffff900 -#define USTCNT WORD_REF(USTCNT_ADDR) - -#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ -#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ -#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ -#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ -#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ -#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ -#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ -#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ -#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ -#define USTCNT_STOP 0x0200 /* Stop bit transmission */ -#define USTCNT_ODD 0x0400 /* Odd Parity */ -#define USTCNT_PEN 0x0800 /* Parity Enable */ -#define USTCNT_CLKM 0x1000 /* Clock Mode Select */ -#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ -#define USTCNT_RXEN 0x4000 /* Receiver Enable */ -#define USTCNT_UEN 0x8000 /* UART Enable */ - -/* '328-compatible definitions */ -#define USTCNT_TXAVAILEN USTCNT_TXAE -#define USTCNT_TXHALFEN USTCNT_TXHE -#define USTCNT_TXEMPTYEN USTCNT_TXEE -#define USTCNT_RXREADYEN USTCNT_RXRE -#define USTCNT_RXHALFEN USTCNT_RXHE -#define USTCNT_RXFULLEN USTCNT_RXFE -#define USTCNT_CTSDELTAEN USTCNT_CTSD -#define USTCNT_ODD_EVEN USTCNT_ODD -#define USTCNT_PARITYEN USTCNT_PEN -#define USTCNT_CLKMODE USTCNT_CLKM -#define USTCNT_UARTEN USTCNT_UEN - -/* - * UART Baud Control Register - */ -#define UBAUD_ADDR 0xfffff902 -#define UBAUD WORD_REF(UBAUD_ADDR) - -#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ -#define UBAUD_PRESCALER_SHIFT 0 -#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ -#define UBAUD_DIVIDE_SHIFT 8 -#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ -#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ - -/* - * UART Receiver Register - */ -#define URX_ADDR 0xfffff904 -#define URX WORD_REF(URX_ADDR) - -#define URX_RXDATA_ADDR 0xfffff905 -#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) - -#define URX_RXDATA_MASK 0x00ff /* Received data */ -#define URX_RXDATA_SHIFT 0 -#define URX_PARITY_ERROR 0x0100 /* Parity Error */ -#define URX_BREAK 0x0200 /* Break Detected */ -#define URX_FRAME_ERROR 0x0400 /* Framing Error */ -#define URX_OVRUN 0x0800 /* Serial Overrun */ -#define URX_OLD_DATA 0x1000 /* Old data in FIFO */ -#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ -#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ -#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ - -/* - * UART Transmitter Register - */ -#define UTX_ADDR 0xfffff906 -#define UTX WORD_REF(UTX_ADDR) - -#define UTX_TXDATA_ADDR 0xfffff907 -#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) - -#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ -#define UTX_TXDATA_SHIFT 0 -#define UTX_CTS_DELTA 0x0100 /* CTS changed */ -#define UTX_CTS_STAT 0x0200 /* CTS State */ -#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ -#define UTX_NOCTS 0x0800 /* Ignore CTS */ -#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ -#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ -#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ -#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ - -/* '328-compatible definitions */ -#define UTX_CTS_STATUS UTX_CTS_STAT -#define UTX_IGNORE_CTS UTX_NOCTS - -/* - * UART Miscellaneous Register - */ -#define UMISC_ADDR 0xfffff908 -#define UMISC WORD_REF(UMISC_ADDR) - -#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ -#define UMISC_RX_POL 0x0008 /* Receive Polarity */ -#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ -#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ -#define UMISC_RTS 0x0040 /* Set RTS status */ -#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ -#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ -#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ -#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ -#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ -#define UMISC_CLKSRC 0x4000 /* Clock Source */ -#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ - -/* - * UART Non-integer Prescaler Register - */ -#define NIPR_ADDR 0xfffff90a -#define NIPR WORD_REF(NIPR_ADDR) - -#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ -#define NIPR_STEP_VALUE_SHIFT 0 -#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ -#define NIPR_SELECT_SHIFT 8 -#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ - - -/* generalization of uart control registers to support multiple ports: */ -typedef volatile struct { - volatile unsigned short int ustcnt; - volatile unsigned short int ubaud; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char rxdata; - } b; - } urx; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char txdata; - } b; - } utx; - volatile unsigned short int umisc; - volatile unsigned short int nipr; - volatile unsigned short int pad1; - volatile unsigned short int pad2; -} __attribute__((packed)) m68328_uart; - - -/********** - * - * 0xFFFFFAxx -- LCD Controller - * - **********/ - -/* - * LCD Screen Starting Address Register - */ -#define LSSA_ADDR 0xfffffa00 -#define LSSA LONG_REF(LSSA_ADDR) - -#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ - -/* - * LCD Virtual Page Width Register - */ -#define LVPW_ADDR 0xfffffa05 -#define LVPW BYTE_REF(LVPW_ADDR) - -/* - * LCD Screen Width Register (not compatible with '328 !!!) - */ -#define LXMAX_ADDR 0xfffffa08 -#define LXMAX WORD_REF(LXMAX_ADDR) - -#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ - -/* - * LCD Screen Height Register - */ -#define LYMAX_ADDR 0xfffffa0a -#define LYMAX WORD_REF(LYMAX_ADDR) - -#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ - -/* - * LCD Cursor X Position Register - */ -#define LCXP_ADDR 0xfffffa18 -#define LCXP WORD_REF(LCXP_ADDR) - -#define LCXP_CC_MASK 0xc000 /* Cursor Control */ -#define LCXP_CC_TRAMSPARENT 0x0000 -#define LCXP_CC_BLACK 0x4000 -#define LCXP_CC_REVERSED 0x8000 -#define LCXP_CC_WHITE 0xc000 -#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ - -/* - * LCD Cursor Y Position Register - */ -#define LCYP_ADDR 0xfffffa1a -#define LCYP WORD_REF(LCYP_ADDR) - -#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ - -/* - * LCD Cursor Width and Heigth Register - */ -#define LCWCH_ADDR 0xfffffa1c -#define LCWCH WORD_REF(LCWCH_ADDR) - -#define LCWCH_CH_MASK 0x001f /* Cursor Height */ -#define LCWCH_CH_SHIFT 0 -#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ -#define LCWCH_CW_SHIFT 8 - -/* - * LCD Blink Control Register - */ -#define LBLKC_ADDR 0xfffffa1f -#define LBLKC BYTE_REF(LBLKC_ADDR) - -#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ -#define LBLKC_BD_SHIFT 0 -#define LBLKC_BKEN 0x80 /* Blink Enabled */ - -/* - * LCD Panel Interface Configuration Register - */ -#define LPICF_ADDR 0xfffffa20 -#define LPICF BYTE_REF(LPICF_ADDR) - -#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ -#define LPICF_GS_BW 0x00 -#define LPICF_GS_GRAY_4 0x01 -#define LPICF_GS_GRAY_16 0x02 -#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ -#define LPICF_PBSIZ_1 0x00 -#define LPICF_PBSIZ_2 0x04 -#define LPICF_PBSIZ_4 0x08 - -/* - * LCD Polarity Configuration Register - */ -#define LPOLCF_ADDR 0xfffffa21 -#define LPOLCF BYTE_REF(LPOLCF_ADDR) - -#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ -#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ -#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ -#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ - -/* - * LACD (LCD Alternate Crystal Direction) Rate Control Register - */ -#define LACDRC_ADDR 0xfffffa23 -#define LACDRC BYTE_REF(LACDRC_ADDR) - -#define LACDRC_ACDSLT 0x80 /* Signal Source Select */ -#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ -#define LACDRC_ACD_SHIFT 0 - -/* - * LCD Pixel Clock Divider Register - */ -#define LPXCD_ADDR 0xfffffa25 -#define LPXCD BYTE_REF(LPXCD_ADDR) - -#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ -#define LPXCD_PCD_SHIFT 0 - -/* - * LCD Clocking Control Register - */ -#define LCKCON_ADDR 0xfffffa27 -#define LCKCON BYTE_REF(LCKCON_ADDR) - -#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ -#define LCKCON_DWS_SHIFT 0 -#define LCKCON_DWIDTH 0x40 /* Display Memory Width */ -#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ - -/* '328-compatible definitions */ -#define LCKCON_DW_MASK LCKCON_DWS_MASK -#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT - -/* - * LCD Refresh Rate Adjustment Register - */ -#define LRRA_ADDR 0xfffffa29 -#define LRRA BYTE_REF(LRRA_ADDR) - -/* - * LCD Panning Offset Register - */ -#define LPOSR_ADDR 0xfffffa2d -#define LPOSR BYTE_REF(LPOSR_ADDR) - -#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ -#define LPOSR_POS_SHIFT 0 - -/* - * LCD Frame Rate Control Modulation Register - */ -#define LFRCM_ADDR 0xfffffa31 -#define LFRCM BYTE_REF(LFRCM_ADDR) - -#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ -#define LFRCM_YMOD_SHIFT 0 -#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ -#define LFRCM_XMOD_SHIFT 4 - -/* - * LCD Gray Palette Mapping Register - */ -#define LGPMR_ADDR 0xfffffa33 -#define LGPMR BYTE_REF(LGPMR_ADDR) - -#define LGPMR_G1_MASK 0x0f -#define LGPMR_G1_SHIFT 0 -#define LGPMR_G2_MASK 0xf0 -#define LGPMR_G2_SHIFT 4 - -/* - * PWM Contrast Control Register - */ -#define PWMR_ADDR 0xfffffa36 -#define PWMR WORD_REF(PWMR_ADDR) - -#define PWMR_PW_MASK 0x00ff /* Pulse Width */ -#define PWMR_PW_SHIFT 0 -#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ -#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ -#define PWMR_SRC_LINE 0x0000 /* Line Pulse */ -#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ -#define PWMR_SRC_LCD 0x4000 /* LCD clock */ - -/********** - * - * 0xFFFFFBxx -- Real-Time Clock (RTC) - * - **********/ - -/* - * RTC Hours Minutes and Seconds Register - */ -#define RTCTIME_ADDR 0xfffffb00 -#define RTCTIME LONG_REF(RTCTIME_ADDR) - -#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCTIME_SECONDS_SHIFT 0 -#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCTIME_MINUTES_SHIFT 16 -#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCTIME_HOURS_SHIFT 24 - -/* - * RTC Alarm Register - */ -#define RTCALRM_ADDR 0xfffffb04 -#define RTCALRM LONG_REF(RTCALRM_ADDR) - -#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCALRM_SECONDS_SHIFT 0 -#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCALRM_MINUTES_SHIFT 16 -#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCALRM_HOURS_SHIFT 24 - -/* - * Watchdog Timer Register - */ -#define WATCHDOG_ADDR 0xfffffb0a -#define WATCHDOG WORD_REF(WATCHDOG_ADDR) - -#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ -#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ -#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ -#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ -#define WATCHDOG_CNT_SHIFT 8 - -/* - * RTC Control Register - */ -#define RTCCTL_ADDR 0xfffffb0c -#define RTCCTL WORD_REF(RTCCTL_ADDR) - -#define RTCCTL_XTL 0x0020 /* Crystal Selection */ -#define RTCCTL_EN 0x0080 /* RTC Enable */ - -/* '328-compatible definitions */ -#define RTCCTL_384 RTCCTL_XTL -#define RTCCTL_ENABLE RTCCTL_EN - -/* - * RTC Interrupt Status Register - */ -#define RTCISR_ADDR 0xfffffb0e -#define RTCISR WORD_REF(RTCISR_ADDR) - -#define RTCISR_SW 0x0001 /* Stopwatch timed out */ -#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ -#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ -#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ -#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ -#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ -#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ -#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ -#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ -#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ -#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ -#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ -#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ -#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ - -/* - * RTC Interrupt Enable Register - */ -#define RTCIENR_ADDR 0xfffffb10 -#define RTCIENR WORD_REF(RTCIENR_ADDR) - -#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ -#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ -#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ -#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ -#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ -#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ -#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ -#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ -#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ -#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ -#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ -#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ -#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ -#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ - -/* - * Stopwatch Minutes Register - */ -#define STPWCH_ADDR 0xfffffb12 -#define STPWCH WORD_REF(STPWCH) - -#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ -#define SPTWCH_CNT_SHIFT 0 - -/* - * RTC Day Count Register - */ -#define DAYR_ADDR 0xfffffb1a -#define DAYR WORD_REF(DAYR_ADDR) - -#define DAYR_DAYS_MASK 0x1ff /* Day Setting */ -#define DAYR_DAYS_SHIFT 0 - -/* - * RTC Day Alarm Register - */ -#define DAYALARM_ADDR 0xfffffb1c -#define DAYALARM WORD_REF(DAYALARM_ADDR) - -#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ -#define DAYALARM_DAYSAL_SHIFT 0 - -/********** - * - * 0xFFFFFCxx -- DRAM Controller - * - **********/ - -/* - * DRAM Memory Configuration Register - */ -#define DRAMMC_ADDR 0xfffffc00 -#define DRAMMC WORD_REF(DRAMMC_ADDR) - -#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ -#define DRAMMC_ROW12_PA10 0x0000 -#define DRAMMC_ROW12_PA21 0x4000 -#define DRAMMC_ROW12_PA23 0x8000 -#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ -#define DRAMMC_ROW0_PA11 0x0000 -#define DRAMMC_ROW0_PA22 0x1000 -#define DRAMMC_ROW0_PA23 0x2000 -#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ -#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ -#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ -#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ -#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ -#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ -#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ -#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ -#define DRAMMC_REF_SHIFT 0 - -/* - * DRAM Control Register - */ -#define DRAMC_ADDR 0xfffffc02 -#define DRAMC WORD_REF(DRAMC_ADDR) - -#define DRAMC_DWE 0x0001 /* DRAM Write Enable */ -#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ -#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ -#define DRAMC_SLW 0x0008 /* Slow RAM */ -#define DRAMC_LSP 0x0010 /* Light Sleep */ -#define DRAMC_MSW 0x0020 /* Slow Multiplexing */ -#define DRAMC_WS_MASK 0x00c0 /* Wait-states */ -#define DRAMC_WS_SHIFT 6 -#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ -#define DRAMC_PGSZ_SHIFT 8 -#define DRAMC_PGSZ_256K 0x0000 -#define DRAMC_PGSZ_512K 0x0100 -#define DRAMC_PGSZ_1024K 0x0200 -#define DRAMC_PGSZ_2048K 0x0300 -#define DRAMC_EDO 0x0400 /* EDO DRAM */ -#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ -#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ -#define DRAMC_BC_SHIFT 12 -#define DRAMC_RM 0x4000 /* Refresh Mode */ -#define DRAMC_EN 0x8000 /* DRAM Controller enable */ - - -/********** - * - * 0xFFFFFDxx -- In-Circuit Emulation (ICE) - * - **********/ - -/* - * ICE Module Address Compare Register - */ -#define ICEMACR_ADDR 0xfffffd00 -#define ICEMACR LONG_REF(ICEMACR_ADDR) - -/* - * ICE Module Address Mask Register - */ -#define ICEMAMR_ADDR 0xfffffd04 -#define ICEMAMR LONG_REF(ICEMAMR_ADDR) - -/* - * ICE Module Control Compare Register - */ -#define ICEMCCR_ADDR 0xfffffd08 -#define ICEMCCR WORD_REF(ICEMCCR_ADDR) - -#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ -#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ - -/* - * ICE Module Control Mask Register - */ -#define ICEMCMR_ADDR 0xfffffd0a -#define ICEMCMR WORD_REF(ICEMCMR_ADDR) - -#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ -#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ - -/* - * ICE Module Control Register - */ -#define ICEMCR_ADDR 0xfffffd0c -#define ICEMCR WORD_REF(ICEMCR_ADDR) - -#define ICEMCR_CEN 0x0001 /* Compare Enable */ -#define ICEMCR_PBEN 0x0002 /* Program Break Enable */ -#define ICEMCR_SB 0x0004 /* Single Breakpoint */ -#define ICEMCR_HMDIS 0x0008 /* HardMap disable */ -#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ - -/* - * ICE Module Status Register - */ -#define ICEMSR_ADDR 0xfffffd0e -#define ICEMSR WORD_REF(ICEMSR_ADDR) - -#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ -#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ -#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ -#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ - -#endif /* _MC68EZ328_H_ */ diff --git a/include/asm-m68knommu/MC68VZ328.h b/include/asm-m68knommu/MC68VZ328.h deleted file mode 100644 index 2b9bf626a0a5..000000000000 --- a/include/asm-m68knommu/MC68VZ328.h +++ /dev/null @@ -1,1349 +0,0 @@ - -/* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers - * - * Copyright (c) 2000-2001 Lineo Inc. - * Copyright (c) 2000-2001 Lineo Canada Corp. - * Copyright (C) 1999 Vladimir Gurevich - * Bare & Hare Software, Inc. - * Based on include/asm-m68knommu/MC68332.h - * Copyright (C) 1998 Kenneth Albanowski , - * The Silver Hammer Group, Ltd. - * - * M68VZ328 fixes by Evan Stawnyczy - * vz multiport fixes by Michael Leslie - */ - -#ifndef _MC68VZ328_H_ -#define _MC68VZ328_H_ - -#define BYTE_REF(addr) (*((volatile unsigned char*)addr)) -#define WORD_REF(addr) (*((volatile unsigned short*)addr)) -#define LONG_REF(addr) (*((volatile unsigned long*)addr)) - -#define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) -#define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) - -/********** - * - * 0xFFFFF0xx -- System Control - * - **********/ - -/* - * System Control Register (SCR) - */ -#define SCR_ADDR 0xfffff000 -#define SCR BYTE_REF(SCR_ADDR) - -#define SCR_WDTH8 0x01 /* 8-Bit Width Select */ -#define SCR_DMAP 0x04 /* Double Map */ -#define SCR_SO 0x08 /* Supervisor Only */ -#define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */ -#define SCR_PRV 0x20 /* Privilege Violation */ -#define SCR_WPV 0x40 /* Write Protect Violation */ -#define SCR_BETO 0x80 /* Bus-Error TimeOut */ - -/* - * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility) - */ -#define MRR_ADDR 0xfffff004 -#define MRR LONG_REF(MRR_ADDR) - -/********** - * - * 0xFFFFF1xx -- Chip-Select logic - * - **********/ - -/* - * Chip Select Group Base Registers - */ -#define CSGBA_ADDR 0xfffff100 -#define CSGBB_ADDR 0xfffff102 - -#define CSGBC_ADDR 0xfffff104 -#define CSGBD_ADDR 0xfffff106 - -#define CSGBA WORD_REF(CSGBA_ADDR) -#define CSGBB WORD_REF(CSGBB_ADDR) -#define CSGBC WORD_REF(CSGBC_ADDR) -#define CSGBD WORD_REF(CSGBD_ADDR) - -/* - * Chip Select Registers - */ -#define CSA_ADDR 0xfffff110 -#define CSB_ADDR 0xfffff112 -#define CSC_ADDR 0xfffff114 -#define CSD_ADDR 0xfffff116 - -#define CSA WORD_REF(CSA_ADDR) -#define CSB WORD_REF(CSB_ADDR) -#define CSC WORD_REF(CSC_ADDR) -#define CSD WORD_REF(CSD_ADDR) - -#define CSA_EN 0x0001 /* Chip-Select Enable */ -#define CSA_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSA_SIZ_SHIFT 1 -#define CSA_WS_MASK 0x0070 /* Wait State */ -#define CSA_WS_SHIFT 4 -#define CSA_BSW 0x0080 /* Data Bus Width */ -#define CSA_FLASH 0x0100 /* FLASH Memory Support */ -#define CSA_RO 0x8000 /* Read-Only */ - -#define CSB_EN 0x0001 /* Chip-Select Enable */ -#define CSB_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSB_SIZ_SHIFT 1 -#define CSB_WS_MASK 0x0070 /* Wait State */ -#define CSB_WS_SHIFT 4 -#define CSB_BSW 0x0080 /* Data Bus Width */ -#define CSB_FLASH 0x0100 /* FLASH Memory Support */ -#define CSB_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSB_UPSIZ_SHIFT 11 -#define CSB_ROP 0x2000 /* Readonly if protected */ -#define CSB_SOP 0x4000 /* Supervisor only if protected */ -#define CSB_RO 0x8000 /* Read-Only */ - -#define CSC_EN 0x0001 /* Chip-Select Enable */ -#define CSC_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSC_SIZ_SHIFT 1 -#define CSC_WS_MASK 0x0070 /* Wait State */ -#define CSC_WS_SHIFT 4 -#define CSC_BSW 0x0080 /* Data Bus Width */ -#define CSC_FLASH 0x0100 /* FLASH Memory Support */ -#define CSC_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSC_UPSIZ_SHIFT 11 -#define CSC_ROP 0x2000 /* Readonly if protected */ -#define CSC_SOP 0x4000 /* Supervisor only if protected */ -#define CSC_RO 0x8000 /* Read-Only */ - -#define CSD_EN 0x0001 /* Chip-Select Enable */ -#define CSD_SIZ_MASK 0x000e /* Chip-Select Size */ -#define CSD_SIZ_SHIFT 1 -#define CSD_WS_MASK 0x0070 /* Wait State */ -#define CSD_WS_SHIFT 4 -#define CSD_BSW 0x0080 /* Data Bus Width */ -#define CSD_FLASH 0x0100 /* FLASH Memory Support */ -#define CSD_DRAM 0x0200 /* Dram Selection */ -#define CSD_COMB 0x0400 /* Combining */ -#define CSD_UPSIZ_MASK 0x1800 /* Unprotected memory block size */ -#define CSD_UPSIZ_SHIFT 11 -#define CSD_ROP 0x2000 /* Readonly if protected */ -#define CSD_SOP 0x4000 /* Supervisor only if protected */ -#define CSD_RO 0x8000 /* Read-Only */ - -/* - * Emulation Chip-Select Register - */ -#define EMUCS_ADDR 0xfffff118 -#define EMUCS WORD_REF(EMUCS_ADDR) - -#define EMUCS_WS_MASK 0x0070 -#define EMUCS_WS_SHIFT 4 - -/********** - * - * 0xFFFFF2xx -- Phase Locked Loop (PLL) & Power Control - * - **********/ - -/* - * PLL Control Register - */ -#define PLLCR_ADDR 0xfffff200 -#define PLLCR WORD_REF(PLLCR_ADDR) - -#define PLLCR_DISPLL 0x0008 /* Disable PLL */ -#define PLLCR_CLKEN 0x0010 /* Clock (CLKO pin) enable */ -#define PLLCR_PRESC 0x0020 /* VCO prescaler */ -#define PLLCR_SYSCLK_SEL_MASK 0x0700 /* System Clock Selection */ -#define PLLCR_SYSCLK_SEL_SHIFT 8 -#define PLLCR_LCDCLK_SEL_MASK 0x3800 /* LCD Clock Selection */ -#define PLLCR_LCDCLK_SEL_SHIFT 11 - -/* '328-compatible definitions */ -#define PLLCR_PIXCLK_SEL_MASK PLLCR_LCDCLK_SEL_MASK -#define PLLCR_PIXCLK_SEL_SHIFT PLLCR_LCDCLK_SEL_SHIFT - -/* - * PLL Frequency Select Register - */ -#define PLLFSR_ADDR 0xfffff202 -#define PLLFSR WORD_REF(PLLFSR_ADDR) - -#define PLLFSR_PC_MASK 0x00ff /* P Count */ -#define PLLFSR_PC_SHIFT 0 -#define PLLFSR_QC_MASK 0x0f00 /* Q Count */ -#define PLLFSR_QC_SHIFT 8 -#define PLLFSR_PROT 0x4000 /* Protect P & Q */ -#define PLLFSR_CLK32 0x8000 /* Clock 32 (kHz) */ - -/* - * Power Control Register - */ -#define PCTRL_ADDR 0xfffff207 -#define PCTRL BYTE_REF(PCTRL_ADDR) - -#define PCTRL_WIDTH_MASK 0x1f /* CPU Clock bursts width */ -#define PCTRL_WIDTH_SHIFT 0 -#define PCTRL_PCEN 0x80 /* Power Control Enable */ - -/********** - * - * 0xFFFFF3xx -- Interrupt Controller - * - **********/ - -/* - * Interrupt Vector Register - */ -#define IVR_ADDR 0xfffff300 -#define IVR BYTE_REF(IVR_ADDR) - -#define IVR_VECTOR_MASK 0xF8 - -/* - * Interrupt control Register - */ -#define ICR_ADDR 0xfffff302 -#define ICR WORD_REF(ICR_ADDR) - -#define ICR_POL5 0x0080 /* Polarity Control for IRQ5 */ -#define ICR_ET6 0x0100 /* Edge Trigger Select for IRQ6 */ -#define ICR_ET3 0x0200 /* Edge Trigger Select for IRQ3 */ -#define ICR_ET2 0x0400 /* Edge Trigger Select for IRQ2 */ -#define ICR_ET1 0x0800 /* Edge Trigger Select for IRQ1 */ -#define ICR_POL6 0x1000 /* Polarity Control for IRQ6 */ -#define ICR_POL3 0x2000 /* Polarity Control for IRQ3 */ -#define ICR_POL2 0x4000 /* Polarity Control for IRQ2 */ -#define ICR_POL1 0x8000 /* Polarity Control for IRQ1 */ - -/* - * Interrupt Mask Register - */ -#define IMR_ADDR 0xfffff304 -#define IMR LONG_REF(IMR_ADDR) - -/* - * Define the names for bit positions first. This is useful for - * request_irq - */ -#define SPI2_IRQ_NUM 0 /* SPI 2 interrupt */ -#define TMR_IRQ_NUM 1 /* Timer 1 interrupt */ -#define UART1_IRQ_NUM 2 /* UART 1 interrupt */ -#define WDT_IRQ_NUM 3 /* Watchdog Timer interrupt */ -#define RTC_IRQ_NUM 4 /* RTC interrupt */ -#define TMR2_IRQ_NUM 5 /* Timer 2 interrupt */ -#define KB_IRQ_NUM 6 /* Keyboard Interrupt */ -#define PWM1_IRQ_NUM 7 /* Pulse-Width Modulator 1 int. */ -#define INT0_IRQ_NUM 8 /* External INT0 */ -#define INT1_IRQ_NUM 9 /* External INT1 */ -#define INT2_IRQ_NUM 10 /* External INT2 */ -#define INT3_IRQ_NUM 11 /* External INT3 */ -#define UART2_IRQ_NUM 12 /* UART 2 interrupt */ -#define PWM2_IRQ_NUM 13 /* Pulse-Width Modulator 1 int. */ -#define IRQ1_IRQ_NUM 16 /* IRQ1 */ -#define IRQ2_IRQ_NUM 17 /* IRQ2 */ -#define IRQ3_IRQ_NUM 18 /* IRQ3 */ -#define IRQ6_IRQ_NUM 19 /* IRQ6 */ -#define IRQ5_IRQ_NUM 20 /* IRQ5 */ -#define SPI1_IRQ_NUM 21 /* SPI 1 interrupt */ -#define SAM_IRQ_NUM 22 /* Sampling Timer for RTC */ -#define EMIQ_IRQ_NUM 23 /* Emulator Interrupt */ - -#define SPI_IRQ_NUM SPI2_IRQ_NUM - -/* '328-compatible definitions */ -#define SPIM_IRQ_NUM SPI_IRQ_NUM -#define TMR1_IRQ_NUM TMR_IRQ_NUM -#define UART_IRQ_NUM UART1_IRQ_NUM - -/* - * Here go the bitmasks themselves - */ -#define IMR_MSPI (1 << SPI_IRQ_NUM) /* Mask SPI interrupt */ -#define IMR_MTMR (1 << TMR_IRQ_NUM) /* Mask Timer interrupt */ -#define IMR_MUART (1 << UART_IRQ_NUM) /* Mask UART interrupt */ -#define IMR_MWDT (1 << WDT_IRQ_NUM) /* Mask Watchdog Timer interrupt */ -#define IMR_MRTC (1 << RTC_IRQ_NUM) /* Mask RTC interrupt */ -#define IMR_MKB (1 << KB_IRQ_NUM) /* Mask Keyboard Interrupt */ -#define IMR_MPWM (1 << PWM_IRQ_NUM) /* Mask Pulse-Width Modulator int. */ -#define IMR_MINT0 (1 << INT0_IRQ_NUM) /* Mask External INT0 */ -#define IMR_MINT1 (1 << INT1_IRQ_NUM) /* Mask External INT1 */ -#define IMR_MINT2 (1 << INT2_IRQ_NUM) /* Mask External INT2 */ -#define IMR_MINT3 (1 << INT3_IRQ_NUM) /* Mask External INT3 */ -#define IMR_MIRQ1 (1 << IRQ1_IRQ_NUM) /* Mask IRQ1 */ -#define IMR_MIRQ2 (1 << IRQ2_IRQ_NUM) /* Mask IRQ2 */ -#define IMR_MIRQ3 (1 << IRQ3_IRQ_NUM) /* Mask IRQ3 */ -#define IMR_MIRQ6 (1 << IRQ6_IRQ_NUM) /* Mask IRQ6 */ -#define IMR_MIRQ5 (1 << IRQ5_IRQ_NUM) /* Mask IRQ5 */ -#define IMR_MSAM (1 << SAM_IRQ_NUM) /* Mask Sampling Timer for RTC */ -#define IMR_MEMIQ (1 << EMIQ_IRQ_NUM) /* Mask Emulator Interrupt */ - -/* '328-compatible definitions */ -#define IMR_MSPIM IMR_MSPI -#define IMR_MTMR1 IMR_MTMR - -/* - * Interrupt Status Register - */ -#define ISR_ADDR 0xfffff30c -#define ISR LONG_REF(ISR_ADDR) - -#define ISR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ -#define ISR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ -#define ISR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define ISR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define ISR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define ISR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define ISR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ -#define ISR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define ISR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define ISR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define ISR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define ISR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define ISR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define ISR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define ISR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define ISR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ -#define ISR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ -#define ISR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ - -/* '328-compatible definitions */ -#define ISR_SPIM ISR_SPI -#define ISR_TMR1 ISR_TMR - -/* - * Interrupt Pending Register - */ -#define IPR_ADDR 0xfffff30c -#define IPR LONG_REF(IPR_ADDR) - -#define IPR_SPI (1 << SPI_IRQ_NUM) /* SPI interrupt */ -#define IPR_TMR (1 << TMR_IRQ_NUM) /* Timer interrupt */ -#define IPR_UART (1 << UART_IRQ_NUM) /* UART interrupt */ -#define IPR_WDT (1 << WDT_IRQ_NUM) /* Watchdog Timer interrupt */ -#define IPR_RTC (1 << RTC_IRQ_NUM) /* RTC interrupt */ -#define IPR_KB (1 << KB_IRQ_NUM) /* Keyboard Interrupt */ -#define IPR_PWM (1 << PWM_IRQ_NUM) /* Pulse-Width Modulator interrupt */ -#define IPR_INT0 (1 << INT0_IRQ_NUM) /* External INT0 */ -#define IPR_INT1 (1 << INT1_IRQ_NUM) /* External INT1 */ -#define IPR_INT2 (1 << INT2_IRQ_NUM) /* External INT2 */ -#define IPR_INT3 (1 << INT3_IRQ_NUM) /* External INT3 */ -#define IPR_IRQ1 (1 << IRQ1_IRQ_NUM) /* IRQ1 */ -#define IPR_IRQ2 (1 << IRQ2_IRQ_NUM) /* IRQ2 */ -#define IPR_IRQ3 (1 << IRQ3_IRQ_NUM) /* IRQ3 */ -#define IPR_IRQ6 (1 << IRQ6_IRQ_NUM) /* IRQ6 */ -#define IPR_IRQ5 (1 << IRQ5_IRQ_NUM) /* IRQ5 */ -#define IPR_SAM (1 << SAM_IRQ_NUM) /* Sampling Timer for RTC */ -#define IPR_EMIQ (1 << EMIQ_IRQ_NUM) /* Emulator Interrupt */ - -/* '328-compatible definitions */ -#define IPR_SPIM IPR_SPI -#define IPR_TMR1 IPR_TMR - -/********** - * - * 0xFFFFF4xx -- Parallel Ports - * - **********/ - -/* - * Port A - */ -#define PADIR_ADDR 0xfffff400 /* Port A direction reg */ -#define PADATA_ADDR 0xfffff401 /* Port A data register */ -#define PAPUEN_ADDR 0xfffff402 /* Port A Pull-Up enable reg */ - -#define PADIR BYTE_REF(PADIR_ADDR) -#define PADATA BYTE_REF(PADATA_ADDR) -#define PAPUEN BYTE_REF(PAPUEN_ADDR) - -#define PA(x) (1 << (x)) - -/* - * Port B - */ -#define PBDIR_ADDR 0xfffff408 /* Port B direction reg */ -#define PBDATA_ADDR 0xfffff409 /* Port B data register */ -#define PBPUEN_ADDR 0xfffff40a /* Port B Pull-Up enable reg */ -#define PBSEL_ADDR 0xfffff40b /* Port B Select Register */ - -#define PBDIR BYTE_REF(PBDIR_ADDR) -#define PBDATA BYTE_REF(PBDATA_ADDR) -#define PBPUEN BYTE_REF(PBPUEN_ADDR) -#define PBSEL BYTE_REF(PBSEL_ADDR) - -#define PB(x) (1 << (x)) - -#define PB_CSB0 0x01 /* Use CSB0 as PB[0] */ -#define PB_CSB1 0x02 /* Use CSB1 as PB[1] */ -#define PB_CSC0_RAS0 0x04 /* Use CSC0/RAS0 as PB[2] */ -#define PB_CSC1_RAS1 0x08 /* Use CSC1/RAS1 as PB[3] */ -#define PB_CSD0_CAS0 0x10 /* Use CSD0/CAS0 as PB[4] */ -#define PB_CSD1_CAS1 0x20 /* Use CSD1/CAS1 as PB[5] */ -#define PB_TIN_TOUT 0x40 /* Use TIN/TOUT as PB[6] */ -#define PB_PWMO 0x80 /* Use PWMO as PB[7] */ - -/* - * Port C - */ -#define PCDIR_ADDR 0xfffff410 /* Port C direction reg */ -#define PCDATA_ADDR 0xfffff411 /* Port C data register */ -#define PCPDEN_ADDR 0xfffff412 /* Port C Pull-Down enb. reg */ -#define PCSEL_ADDR 0xfffff413 /* Port C Select Register */ - -#define PCDIR BYTE_REF(PCDIR_ADDR) -#define PCDATA BYTE_REF(PCDATA_ADDR) -#define PCPDEN BYTE_REF(PCPDEN_ADDR) -#define PCSEL BYTE_REF(PCSEL_ADDR) - -#define PC(x) (1 << (x)) - -#define PC_LD0 0x01 /* Use LD0 as PC[0] */ -#define PC_LD1 0x02 /* Use LD1 as PC[1] */ -#define PC_LD2 0x04 /* Use LD2 as PC[2] */ -#define PC_LD3 0x08 /* Use LD3 as PC[3] */ -#define PC_LFLM 0x10 /* Use LFLM as PC[4] */ -#define PC_LLP 0x20 /* Use LLP as PC[5] */ -#define PC_LCLK 0x40 /* Use LCLK as PC[6] */ -#define PC_LACD 0x80 /* Use LACD as PC[7] */ - -/* - * Port D - */ -#define PDDIR_ADDR 0xfffff418 /* Port D direction reg */ -#define PDDATA_ADDR 0xfffff419 /* Port D data register */ -#define PDPUEN_ADDR 0xfffff41a /* Port D Pull-Up enable reg */ -#define PDSEL_ADDR 0xfffff41b /* Port D Select Register */ -#define PDPOL_ADDR 0xfffff41c /* Port D Polarity Register */ -#define PDIRQEN_ADDR 0xfffff41d /* Port D IRQ enable register */ -#define PDKBEN_ADDR 0xfffff41e /* Port D Keyboard Enable reg */ -#define PDIQEG_ADDR 0xfffff41f /* Port D IRQ Edge Register */ - -#define PDDIR BYTE_REF(PDDIR_ADDR) -#define PDDATA BYTE_REF(PDDATA_ADDR) -#define PDPUEN BYTE_REF(PDPUEN_ADDR) -#define PDSEL BYTE_REF(PDSEL_ADDR) -#define PDPOL BYTE_REF(PDPOL_ADDR) -#define PDIRQEN BYTE_REF(PDIRQEN_ADDR) -#define PDKBEN BYTE_REF(PDKBEN_ADDR) -#define PDIQEG BYTE_REF(PDIQEG_ADDR) - -#define PD(x) (1 << (x)) - -#define PD_INT0 0x01 /* Use INT0 as PD[0] */ -#define PD_INT1 0x02 /* Use INT1 as PD[1] */ -#define PD_INT2 0x04 /* Use INT2 as PD[2] */ -#define PD_INT3 0x08 /* Use INT3 as PD[3] */ -#define PD_IRQ1 0x10 /* Use IRQ1 as PD[4] */ -#define PD_IRQ2 0x20 /* Use IRQ2 as PD[5] */ -#define PD_IRQ3 0x40 /* Use IRQ3 as PD[6] */ -#define PD_IRQ6 0x80 /* Use IRQ6 as PD[7] */ - -/* - * Port E - */ -#define PEDIR_ADDR 0xfffff420 /* Port E direction reg */ -#define PEDATA_ADDR 0xfffff421 /* Port E data register */ -#define PEPUEN_ADDR 0xfffff422 /* Port E Pull-Up enable reg */ -#define PESEL_ADDR 0xfffff423 /* Port E Select Register */ - -#define PEDIR BYTE_REF(PEDIR_ADDR) -#define PEDATA BYTE_REF(PEDATA_ADDR) -#define PEPUEN BYTE_REF(PEPUEN_ADDR) -#define PESEL BYTE_REF(PESEL_ADDR) - -#define PE(x) (1 << (x)) - -#define PE_SPMTXD 0x01 /* Use SPMTXD as PE[0] */ -#define PE_SPMRXD 0x02 /* Use SPMRXD as PE[1] */ -#define PE_SPMCLK 0x04 /* Use SPMCLK as PE[2] */ -#define PE_DWE 0x08 /* Use DWE as PE[3] */ -#define PE_RXD 0x10 /* Use RXD as PE[4] */ -#define PE_TXD 0x20 /* Use TXD as PE[5] */ -#define PE_RTS 0x40 /* Use RTS as PE[6] */ -#define PE_CTS 0x80 /* Use CTS as PE[7] */ - -/* - * Port F - */ -#define PFDIR_ADDR 0xfffff428 /* Port F direction reg */ -#define PFDATA_ADDR 0xfffff429 /* Port F data register */ -#define PFPUEN_ADDR 0xfffff42a /* Port F Pull-Up enable reg */ -#define PFSEL_ADDR 0xfffff42b /* Port F Select Register */ - -#define PFDIR BYTE_REF(PFDIR_ADDR) -#define PFDATA BYTE_REF(PFDATA_ADDR) -#define PFPUEN BYTE_REF(PFPUEN_ADDR) -#define PFSEL BYTE_REF(PFSEL_ADDR) - -#define PF(x) (1 << (x)) - -#define PF_LCONTRAST 0x01 /* Use LCONTRAST as PF[0] */ -#define PF_IRQ5 0x02 /* Use IRQ5 as PF[1] */ -#define PF_CLKO 0x04 /* Use CLKO as PF[2] */ -#define PF_A20 0x08 /* Use A20 as PF[3] */ -#define PF_A21 0x10 /* Use A21 as PF[4] */ -#define PF_A22 0x20 /* Use A22 as PF[5] */ -#define PF_A23 0x40 /* Use A23 as PF[6] */ -#define PF_CSA1 0x80 /* Use CSA1 as PF[7] */ - -/* - * Port G - */ -#define PGDIR_ADDR 0xfffff430 /* Port G direction reg */ -#define PGDATA_ADDR 0xfffff431 /* Port G data register */ -#define PGPUEN_ADDR 0xfffff432 /* Port G Pull-Up enable reg */ -#define PGSEL_ADDR 0xfffff433 /* Port G Select Register */ - -#define PGDIR BYTE_REF(PGDIR_ADDR) -#define PGDATA BYTE_REF(PGDATA_ADDR) -#define PGPUEN BYTE_REF(PGPUEN_ADDR) -#define PGSEL BYTE_REF(PGSEL_ADDR) - -#define PG(x) (1 << (x)) - -#define PG_BUSW_DTACK 0x01 /* Use BUSW/DTACK as PG[0] */ -#define PG_A0 0x02 /* Use A0 as PG[1] */ -#define PG_EMUIRQ 0x04 /* Use EMUIRQ as PG[2] */ -#define PG_HIZ_P_D 0x08 /* Use HIZ/P/D as PG[3] */ -#define PG_EMUCS 0x10 /* Use EMUCS as PG[4] */ -#define PG_EMUBRK 0x20 /* Use EMUBRK as PG[5] */ - -/* - * Port J - */ -#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ -#define PJDATA_ADDR 0xfffff439 /* Port J data register */ -#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enb. reg */ -#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ - -#define PJDIR BYTE_REF(PJDIR_ADDR) -#define PJDATA BYTE_REF(PJDATA_ADDR) -#define PJPUEN BYTE_REF(PJPUEN_ADDR) -#define PJSEL BYTE_REF(PJSEL_ADDR) - -#define PJ(x) (1 << (x)) - -/* - * Port K - */ -#define PKDIR_ADDR 0xfffff440 /* Port K direction reg */ -#define PKDATA_ADDR 0xfffff441 /* Port K data register */ -#define PKPUEN_ADDR 0xfffff442 /* Port K Pull-Up enb. reg */ -#define PKSEL_ADDR 0xfffff443 /* Port K Select Register */ - -#define PKDIR BYTE_REF(PKDIR_ADDR) -#define PKDATA BYTE_REF(PKDATA_ADDR) -#define PKPUEN BYTE_REF(PKPUEN_ADDR) -#define PKSEL BYTE_REF(PKSEL_ADDR) - -#define PK(x) (1 << (x)) - -#define PK_DATAREADY 0x01 /* Use ~DATA_READY as PK[0] */ -#define PK_PWM2 0x01 /* Use PWM2 as PK[0] */ -#define PK_R_W 0x02 /* Use R/W as PK[1] */ -#define PK_LDS 0x04 /* Use /LDS as PK[2] */ -#define PK_UDS 0x08 /* Use /UDS as PK[3] */ -#define PK_LD4 0x10 /* Use LD4 as PK[4] */ -#define PK_LD5 0x20 /* Use LD5 as PK[5] */ -#define PK_LD6 0x40 /* Use LD6 as PK[6] */ -#define PK_LD7 0x80 /* Use LD7 as PK[7] */ - -#define PJDIR_ADDR 0xfffff438 /* Port J direction reg */ -#define PJDATA_ADDR 0xfffff439 /* Port J data register */ -#define PJPUEN_ADDR 0xfffff43A /* Port J Pull-Up enable reg */ -#define PJSEL_ADDR 0xfffff43B /* Port J Select Register */ - -#define PJDIR BYTE_REF(PJDIR_ADDR) -#define PJDATA BYTE_REF(PJDATA_ADDR) -#define PJPUEN BYTE_REF(PJPUEN_ADDR) -#define PJSEL BYTE_REF(PJSEL_ADDR) - -#define PJ(x) (1 << (x)) - -#define PJ_MOSI 0x01 /* Use MOSI as PJ[0] */ -#define PJ_MISO 0x02 /* Use MISO as PJ[1] */ -#define PJ_SPICLK1 0x04 /* Use SPICLK1 as PJ[2] */ -#define PJ_SS 0x08 /* Use SS as PJ[3] */ -#define PJ_RXD2 0x10 /* Use RXD2 as PJ[4] */ -#define PJ_TXD2 0x20 /* Use TXD2 as PJ[5] */ -#define PJ_RTS2 0x40 /* Use RTS2 as PJ[5] */ -#define PJ_CTS2 0x80 /* Use CTS2 as PJ[5] */ - -/* - * Port M - */ -#define PMDIR_ADDR 0xfffff448 /* Port M direction reg */ -#define PMDATA_ADDR 0xfffff449 /* Port M data register */ -#define PMPUEN_ADDR 0xfffff44a /* Port M Pull-Up enable reg */ -#define PMSEL_ADDR 0xfffff44b /* Port M Select Register */ - -#define PMDIR BYTE_REF(PMDIR_ADDR) -#define PMDATA BYTE_REF(PMDATA_ADDR) -#define PMPUEN BYTE_REF(PMPUEN_ADDR) -#define PMSEL BYTE_REF(PMSEL_ADDR) - -#define PM(x) (1 << (x)) - -#define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */ -#define PM_SDCE 0x02 /* Use SDCE as PM[1] */ -#define PM_DQMH 0x04 /* Use DQMH as PM[2] */ -#define PM_DQML 0x08 /* Use DQML as PM[3] */ -#define PM_SDA10 0x10 /* Use SDA10 as PM[4] */ -#define PM_DMOE 0x20 /* Use DMOE as PM[5] */ - -/********** - * - * 0xFFFFF5xx -- Pulse-Width Modulator (PWM) - * - **********/ - -/* - * PWM Control Register - */ -#define PWMC_ADDR 0xfffff500 -#define PWMC WORD_REF(PWMC_ADDR) - -#define PWMC_CLKSEL_MASK 0x0003 /* Clock Selection */ -#define PWMC_CLKSEL_SHIFT 0 -#define PWMC_REPEAT_MASK 0x000c /* Sample Repeats */ -#define PWMC_REPEAT_SHIFT 2 -#define PWMC_EN 0x0010 /* Enable PWM */ -#define PMNC_FIFOAV 0x0020 /* FIFO Available */ -#define PWMC_IRQEN 0x0040 /* Interrupt Request Enable */ -#define PWMC_IRQ 0x0080 /* Interrupt Request (FIFO empty) */ -#define PWMC_PRESCALER_MASK 0x7f00 /* Incoming Clock prescaler */ -#define PWMC_PRESCALER_SHIFT 8 -#define PWMC_CLKSRC 0x8000 /* Clock Source Select */ - -/* '328-compatible definitions */ -#define PWMC_PWMEN PWMC_EN - -/* - * PWM Sample Register - */ -#define PWMS_ADDR 0xfffff502 -#define PWMS WORD_REF(PWMS_ADDR) - -/* - * PWM Period Register - */ -#define PWMP_ADDR 0xfffff504 -#define PWMP BYTE_REF(PWMP_ADDR) - -/* - * PWM Counter Register - */ -#define PWMCNT_ADDR 0xfffff505 -#define PWMCNT BYTE_REF(PWMCNT_ADDR) - -/********** - * - * 0xFFFFF6xx -- General-Purpose Timer - * - **********/ - -/* - * Timer Control register - */ -#define TCTL_ADDR 0xfffff600 -#define TCTL WORD_REF(TCTL_ADDR) - -#define TCTL_TEN 0x0001 /* Timer Enable */ -#define TCTL_CLKSOURCE_MASK 0x000e /* Clock Source: */ -#define TCTL_CLKSOURCE_STOP 0x0000 /* Stop count (disabled) */ -#define TCTL_CLKSOURCE_SYSCLK 0x0002 /* SYSCLK to prescaler */ -#define TCTL_CLKSOURCE_SYSCLK_16 0x0004 /* SYSCLK/16 to prescaler */ -#define TCTL_CLKSOURCE_TIN 0x0006 /* TIN to prescaler */ -#define TCTL_CLKSOURCE_32KHZ 0x0008 /* 32kHz clock to prescaler */ -#define TCTL_IRQEN 0x0010 /* IRQ Enable */ -#define TCTL_OM 0x0020 /* Output Mode */ -#define TCTL_CAP_MASK 0x00c0 /* Capture Edge: */ -#define TCTL_CAP_RE 0x0040 /* Capture on rizing edge */ -#define TCTL_CAP_FE 0x0080 /* Capture on falling edge */ -#define TCTL_FRR 0x0010 /* Free-Run Mode */ - -/* '328-compatible definitions */ -#define TCTL1_ADDR TCTL_ADDR -#define TCTL1 TCTL - -/* - * Timer Prescaler Register - */ -#define TPRER_ADDR 0xfffff602 -#define TPRER WORD_REF(TPRER_ADDR) - -/* '328-compatible definitions */ -#define TPRER1_ADDR TPRER_ADDR -#define TPRER1 TPRER - -/* - * Timer Compare Register - */ -#define TCMP_ADDR 0xfffff604 -#define TCMP WORD_REF(TCMP_ADDR) - -/* '328-compatible definitions */ -#define TCMP1_ADDR TCMP_ADDR -#define TCMP1 TCMP - -/* - * Timer Capture register - */ -#define TCR_ADDR 0xfffff606 -#define TCR WORD_REF(TCR_ADDR) - -/* '328-compatible definitions */ -#define TCR1_ADDR TCR_ADDR -#define TCR1 TCR - -/* - * Timer Counter Register - */ -#define TCN_ADDR 0xfffff608 -#define TCN WORD_REF(TCN_ADDR) - -/* '328-compatible definitions */ -#define TCN1_ADDR TCN_ADDR -#define TCN1 TCN - -/* - * Timer Status Register - */ -#define TSTAT_ADDR 0xfffff60a -#define TSTAT WORD_REF(TSTAT_ADDR) - -#define TSTAT_COMP 0x0001 /* Compare Event occurred */ -#define TSTAT_CAPT 0x0001 /* Capture Event occurred */ - -/* '328-compatible definitions */ -#define TSTAT1_ADDR TSTAT_ADDR -#define TSTAT1 TSTAT - -/********** - * - * 0xFFFFF8xx -- Serial Periferial Interface Master (SPIM) - * - **********/ - -/* - * SPIM Data Register - */ -#define SPIMDATA_ADDR 0xfffff800 -#define SPIMDATA WORD_REF(SPIMDATA_ADDR) - -/* - * SPIM Control/Status Register - */ -#define SPIMCONT_ADDR 0xfffff802 -#define SPIMCONT WORD_REF(SPIMCONT_ADDR) - -#define SPIMCONT_BIT_COUNT_MASK 0x000f /* Transfer Length in Bytes */ -#define SPIMCONT_BIT_COUNT_SHIFT 0 -#define SPIMCONT_POL 0x0010 /* SPMCLK Signel Polarity */ -#define SPIMCONT_PHA 0x0020 /* Clock/Data phase relationship */ -#define SPIMCONT_IRQEN 0x0040 /* IRQ Enable */ -#define SPIMCONT_IRQ 0x0080 /* Interrupt Request */ -#define SPIMCONT_XCH 0x0100 /* Exchange */ -#define SPIMCONT_ENABLE 0x0200 /* Enable SPIM */ -#define SPIMCONT_DATA_RATE_MASK 0xe000 /* SPIM Data Rate */ -#define SPIMCONT_DATA_RATE_SHIFT 13 - -/* '328-compatible definitions */ -#define SPIMCONT_SPIMIRQ SPIMCONT_IRQ -#define SPIMCONT_SPIMEN SPIMCONT_ENABLE - -/********** - * - * 0xFFFFF9xx -- UART - * - **********/ - -/* - * UART Status/Control Register - */ - -#define USTCNT_ADDR 0xfffff900 -#define USTCNT WORD_REF(USTCNT_ADDR) - -#define USTCNT_TXAE 0x0001 /* Transmitter Available Interrupt Enable */ -#define USTCNT_TXHE 0x0002 /* Transmitter Half Empty Enable */ -#define USTCNT_TXEE 0x0004 /* Transmitter Empty Interrupt Enable */ -#define USTCNT_RXRE 0x0008 /* Receiver Ready Interrupt Enable */ -#define USTCNT_RXHE 0x0010 /* Receiver Half-Full Interrupt Enable */ -#define USTCNT_RXFE 0x0020 /* Receiver Full Interrupt Enable */ -#define USTCNT_CTSD 0x0040 /* CTS Delta Interrupt Enable */ -#define USTCNT_ODEN 0x0080 /* Old Data Interrupt Enable */ -#define USTCNT_8_7 0x0100 /* Eight or seven-bit transmission */ -#define USTCNT_STOP 0x0200 /* Stop bit transmission */ -#define USTCNT_ODD 0x0400 /* Odd Parity */ -#define USTCNT_PEN 0x0800 /* Parity Enable */ -#define USTCNT_CLKM 0x1000 /* Clock Mode Select */ -#define USTCNT_TXEN 0x2000 /* Transmitter Enable */ -#define USTCNT_RXEN 0x4000 /* Receiver Enable */ -#define USTCNT_UEN 0x8000 /* UART Enable */ - -/* '328-compatible definitions */ -#define USTCNT_TXAVAILEN USTCNT_TXAE -#define USTCNT_TXHALFEN USTCNT_TXHE -#define USTCNT_TXEMPTYEN USTCNT_TXEE -#define USTCNT_RXREADYEN USTCNT_RXRE -#define USTCNT_RXHALFEN USTCNT_RXHE -#define USTCNT_RXFULLEN USTCNT_RXFE -#define USTCNT_CTSDELTAEN USTCNT_CTSD -#define USTCNT_ODD_EVEN USTCNT_ODD -#define USTCNT_PARITYEN USTCNT_PEN -#define USTCNT_CLKMODE USTCNT_CLKM -#define USTCNT_UARTEN USTCNT_UEN - -/* - * UART Baud Control Register - */ -#define UBAUD_ADDR 0xfffff902 -#define UBAUD WORD_REF(UBAUD_ADDR) - -#define UBAUD_PRESCALER_MASK 0x003f /* Actual divisor is 65 - PRESCALER */ -#define UBAUD_PRESCALER_SHIFT 0 -#define UBAUD_DIVIDE_MASK 0x0700 /* Baud Rate freq. divizor */ -#define UBAUD_DIVIDE_SHIFT 8 -#define UBAUD_BAUD_SRC 0x0800 /* Baud Rate Source */ -#define UBAUD_UCLKDIR 0x2000 /* UCLK Direction */ - -/* - * UART Receiver Register - */ -#define URX_ADDR 0xfffff904 -#define URX WORD_REF(URX_ADDR) - -#define URX_RXDATA_ADDR 0xfffff905 -#define URX_RXDATA BYTE_REF(URX_RXDATA_ADDR) - -#define URX_RXDATA_MASK 0x00ff /* Received data */ -#define URX_RXDATA_SHIFT 0 -#define URX_PARITY_ERROR 0x0100 /* Parity Error */ -#define URX_BREAK 0x0200 /* Break Detected */ -#define URX_FRAME_ERROR 0x0400 /* Framing Error */ -#define URX_OVRUN 0x0800 /* Serial Overrun */ -#define URX_OLD_DATA 0x1000 /* Old data in FIFO */ -#define URX_DATA_READY 0x2000 /* Data Ready (FIFO not empty) */ -#define URX_FIFO_HALF 0x4000 /* FIFO is Half-Full */ -#define URX_FIFO_FULL 0x8000 /* FIFO is Full */ - -/* - * UART Transmitter Register - */ -#define UTX_ADDR 0xfffff906 -#define UTX WORD_REF(UTX_ADDR) - -#define UTX_TXDATA_ADDR 0xfffff907 -#define UTX_TXDATA BYTE_REF(UTX_TXDATA_ADDR) - -#define UTX_TXDATA_MASK 0x00ff /* Data to be transmitted */ -#define UTX_TXDATA_SHIFT 0 -#define UTX_CTS_DELTA 0x0100 /* CTS changed */ -#define UTX_CTS_STAT 0x0200 /* CTS State */ -#define UTX_BUSY 0x0400 /* FIFO is busy, sending a character */ -#define UTX_NOCTS 0x0800 /* Ignore CTS */ -#define UTX_SEND_BREAK 0x1000 /* Send a BREAK */ -#define UTX_TX_AVAIL 0x2000 /* Transmit FIFO has a slot available */ -#define UTX_FIFO_HALF 0x4000 /* Transmit FIFO is half empty */ -#define UTX_FIFO_EMPTY 0x8000 /* Transmit FIFO is empty */ - -/* '328-compatible definitions */ -#define UTX_CTS_STATUS UTX_CTS_STAT -#define UTX_IGNORE_CTS UTX_NOCTS - -/* - * UART Miscellaneous Register - */ -#define UMISC_ADDR 0xfffff908 -#define UMISC WORD_REF(UMISC_ADDR) - -#define UMISC_TX_POL 0x0004 /* Transmit Polarity */ -#define UMISC_RX_POL 0x0008 /* Receive Polarity */ -#define UMISC_IRDA_LOOP 0x0010 /* IrDA Loopback Enable */ -#define UMISC_IRDA_EN 0x0020 /* Infra-Red Enable */ -#define UMISC_RTS 0x0040 /* Set RTS status */ -#define UMISC_RTSCONT 0x0080 /* Choose RTS control */ -#define UMISC_IR_TEST 0x0400 /* IRDA Test Enable */ -#define UMISC_BAUD_RESET 0x0800 /* Reset Baud Rate Generation Counters */ -#define UMISC_LOOP 0x1000 /* Serial Loopback Enable */ -#define UMISC_FORCE_PERR 0x2000 /* Force Parity Error */ -#define UMISC_CLKSRC 0x4000 /* Clock Source */ -#define UMISC_BAUD_TEST 0x8000 /* Enable Baud Test Mode */ - -/* - * UART Non-integer Prescaler Register - */ -#define NIPR_ADDR 0xfffff90a -#define NIPR WORD_REF(NIPR_ADDR) - -#define NIPR_STEP_VALUE_MASK 0x00ff /* NI prescaler step value */ -#define NIPR_STEP_VALUE_SHIFT 0 -#define NIPR_SELECT_MASK 0x0700 /* Tap Selection */ -#define NIPR_SELECT_SHIFT 8 -#define NIPR_PRE_SEL 0x8000 /* Non-integer prescaler select */ - - -/* generalization of uart control registers to support multiple ports: */ -typedef struct { - volatile unsigned short int ustcnt; - volatile unsigned short int ubaud; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char rxdata; - } b; - } urx; - union { - volatile unsigned short int w; - struct { - volatile unsigned char status; - volatile unsigned char txdata; - } b; - } utx; - volatile unsigned short int umisc; - volatile unsigned short int nipr; - volatile unsigned short int hmark; - volatile unsigned short int unused; -} __attribute__((packed)) m68328_uart; - - - - -/********** - * - * 0xFFFFFAxx -- LCD Controller - * - **********/ - -/* - * LCD Screen Starting Address Register - */ -#define LSSA_ADDR 0xfffffa00 -#define LSSA LONG_REF(LSSA_ADDR) - -#define LSSA_SSA_MASK 0x1ffffffe /* Bits 0 and 29-31 are reserved */ - -/* - * LCD Virtual Page Width Register - */ -#define LVPW_ADDR 0xfffffa05 -#define LVPW BYTE_REF(LVPW_ADDR) - -/* - * LCD Screen Width Register (not compatible with '328 !!!) - */ -#define LXMAX_ADDR 0xfffffa08 -#define LXMAX WORD_REF(LXMAX_ADDR) - -#define LXMAX_XM_MASK 0x02f0 /* Bits 0-3 and 10-15 are reserved */ - -/* - * LCD Screen Height Register - */ -#define LYMAX_ADDR 0xfffffa0a -#define LYMAX WORD_REF(LYMAX_ADDR) - -#define LYMAX_YM_MASK 0x01ff /* Bits 9-15 are reserved */ - -/* - * LCD Cursor X Position Register - */ -#define LCXP_ADDR 0xfffffa18 -#define LCXP WORD_REF(LCXP_ADDR) - -#define LCXP_CC_MASK 0xc000 /* Cursor Control */ -#define LCXP_CC_TRAMSPARENT 0x0000 -#define LCXP_CC_BLACK 0x4000 -#define LCXP_CC_REVERSED 0x8000 -#define LCXP_CC_WHITE 0xc000 -#define LCXP_CXP_MASK 0x02ff /* Cursor X position */ - -/* - * LCD Cursor Y Position Register - */ -#define LCYP_ADDR 0xfffffa1a -#define LCYP WORD_REF(LCYP_ADDR) - -#define LCYP_CYP_MASK 0x01ff /* Cursor Y Position */ - -/* - * LCD Cursor Width and Heigth Register - */ -#define LCWCH_ADDR 0xfffffa1c -#define LCWCH WORD_REF(LCWCH_ADDR) - -#define LCWCH_CH_MASK 0x001f /* Cursor Height */ -#define LCWCH_CH_SHIFT 0 -#define LCWCH_CW_MASK 0x1f00 /* Cursor Width */ -#define LCWCH_CW_SHIFT 8 - -/* - * LCD Blink Control Register - */ -#define LBLKC_ADDR 0xfffffa1f -#define LBLKC BYTE_REF(LBLKC_ADDR) - -#define LBLKC_BD_MASK 0x7f /* Blink Divisor */ -#define LBLKC_BD_SHIFT 0 -#define LBLKC_BKEN 0x80 /* Blink Enabled */ - -/* - * LCD Panel Interface Configuration Register - */ -#define LPICF_ADDR 0xfffffa20 -#define LPICF BYTE_REF(LPICF_ADDR) - -#define LPICF_GS_MASK 0x03 /* Gray-Scale Mode */ -#define LPICF_GS_BW 0x00 -#define LPICF_GS_GRAY_4 0x01 -#define LPICF_GS_GRAY_16 0x02 -#define LPICF_PBSIZ_MASK 0x0c /* Panel Bus Width */ -#define LPICF_PBSIZ_1 0x00 -#define LPICF_PBSIZ_2 0x04 -#define LPICF_PBSIZ_4 0x08 - -/* - * LCD Polarity Configuration Register - */ -#define LPOLCF_ADDR 0xfffffa21 -#define LPOLCF BYTE_REF(LPOLCF_ADDR) - -#define LPOLCF_PIXPOL 0x01 /* Pixel Polarity */ -#define LPOLCF_LPPOL 0x02 /* Line Pulse Polarity */ -#define LPOLCF_FLMPOL 0x04 /* Frame Marker Polarity */ -#define LPOLCF_LCKPOL 0x08 /* LCD Shift Lock Polarity */ - -/* - * LACD (LCD Alternate Crystal Direction) Rate Control Register - */ -#define LACDRC_ADDR 0xfffffa23 -#define LACDRC BYTE_REF(LACDRC_ADDR) - -#define LACDRC_ACDSLT 0x80 /* Signal Source Select */ -#define LACDRC_ACD_MASK 0x0f /* Alternate Crystal Direction Control */ -#define LACDRC_ACD_SHIFT 0 - -/* - * LCD Pixel Clock Divider Register - */ -#define LPXCD_ADDR 0xfffffa25 -#define LPXCD BYTE_REF(LPXCD_ADDR) - -#define LPXCD_PCD_MASK 0x3f /* Pixel Clock Divider */ -#define LPXCD_PCD_SHIFT 0 - -/* - * LCD Clocking Control Register - */ -#define LCKCON_ADDR 0xfffffa27 -#define LCKCON BYTE_REF(LCKCON_ADDR) - -#define LCKCON_DWS_MASK 0x0f /* Display Wait-State */ -#define LCKCON_DWS_SHIFT 0 -#define LCKCON_DWIDTH 0x40 /* Display Memory Width */ -#define LCKCON_LCDON 0x80 /* Enable LCD Controller */ - -/* '328-compatible definitions */ -#define LCKCON_DW_MASK LCKCON_DWS_MASK -#define LCKCON_DW_SHIFT LCKCON_DWS_SHIFT - -/* - * LCD Refresh Rate Adjustment Register - */ -#define LRRA_ADDR 0xfffffa29 -#define LRRA BYTE_REF(LRRA_ADDR) - -/* - * LCD Panning Offset Register - */ -#define LPOSR_ADDR 0xfffffa2d -#define LPOSR BYTE_REF(LPOSR_ADDR) - -#define LPOSR_POS_MASK 0x0f /* Pixel Offset Code */ -#define LPOSR_POS_SHIFT 0 - -/* - * LCD Frame Rate Control Modulation Register - */ -#define LFRCM_ADDR 0xfffffa31 -#define LFRCM BYTE_REF(LFRCM_ADDR) - -#define LFRCM_YMOD_MASK 0x0f /* Vertical Modulation */ -#define LFRCM_YMOD_SHIFT 0 -#define LFRCM_XMOD_MASK 0xf0 /* Horizontal Modulation */ -#define LFRCM_XMOD_SHIFT 4 - -/* - * LCD Gray Palette Mapping Register - */ -#define LGPMR_ADDR 0xfffffa33 -#define LGPMR BYTE_REF(LGPMR_ADDR) - -#define LGPMR_G1_MASK 0x0f -#define LGPMR_G1_SHIFT 0 -#define LGPMR_G2_MASK 0xf0 -#define LGPMR_G2_SHIFT 4 - -/* - * PWM Contrast Control Register - */ -#define PWMR_ADDR 0xfffffa36 -#define PWMR WORD_REF(PWMR_ADDR) - -#define PWMR_PW_MASK 0x00ff /* Pulse Width */ -#define PWMR_PW_SHIFT 0 -#define PWMR_CCPEN 0x0100 /* Contrast Control Enable */ -#define PWMR_SRC_MASK 0x0600 /* Input Clock Source */ -#define PWMR_SRC_LINE 0x0000 /* Line Pulse */ -#define PWMR_SRC_PIXEL 0x0200 /* Pixel Clock */ -#define PWMR_SRC_LCD 0x4000 /* LCD clock */ - -/********** - * - * 0xFFFFFBxx -- Real-Time Clock (RTC) - * - **********/ - -/* - * RTC Hours Minutes and Seconds Register - */ -#define RTCTIME_ADDR 0xfffffb00 -#define RTCTIME LONG_REF(RTCTIME_ADDR) - -#define RTCTIME_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCTIME_SECONDS_SHIFT 0 -#define RTCTIME_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCTIME_MINUTES_SHIFT 16 -#define RTCTIME_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCTIME_HOURS_SHIFT 24 - -/* - * RTC Alarm Register - */ -#define RTCALRM_ADDR 0xfffffb04 -#define RTCALRM LONG_REF(RTCALRM_ADDR) - -#define RTCALRM_SECONDS_MASK 0x0000003f /* Seconds */ -#define RTCALRM_SECONDS_SHIFT 0 -#define RTCALRM_MINUTES_MASK 0x003f0000 /* Minutes */ -#define RTCALRM_MINUTES_SHIFT 16 -#define RTCALRM_HOURS_MASK 0x1f000000 /* Hours */ -#define RTCALRM_HOURS_SHIFT 24 - -/* - * Watchdog Timer Register - */ -#define WATCHDOG_ADDR 0xfffffb0a -#define WATCHDOG WORD_REF(WATCHDOG_ADDR) - -#define WATCHDOG_EN 0x0001 /* Watchdog Enabled */ -#define WATCHDOG_ISEL 0x0002 /* Select the watchdog interrupt */ -#define WATCHDOG_INTF 0x0080 /* Watchdog interrupt occcured */ -#define WATCHDOG_CNT_MASK 0x0300 /* Watchdog Counter */ -#define WATCHDOG_CNT_SHIFT 8 - -/* - * RTC Control Register - */ -#define RTCCTL_ADDR 0xfffffb0c -#define RTCCTL WORD_REF(RTCCTL_ADDR) - -#define RTCCTL_XTL 0x0020 /* Crystal Selection */ -#define RTCCTL_EN 0x0080 /* RTC Enable */ - -/* '328-compatible definitions */ -#define RTCCTL_384 RTCCTL_XTL -#define RTCCTL_ENABLE RTCCTL_EN - -/* - * RTC Interrupt Status Register - */ -#define RTCISR_ADDR 0xfffffb0e -#define RTCISR WORD_REF(RTCISR_ADDR) - -#define RTCISR_SW 0x0001 /* Stopwatch timed out */ -#define RTCISR_MIN 0x0002 /* 1-minute interrupt has occurred */ -#define RTCISR_ALM 0x0004 /* Alarm interrupt has occurred */ -#define RTCISR_DAY 0x0008 /* 24-hour rollover interrupt has occurred */ -#define RTCISR_1HZ 0x0010 /* 1Hz interrupt has occurred */ -#define RTCISR_HR 0x0020 /* 1-hour interrupt has occurred */ -#define RTCISR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt has occurred */ -#define RTCISR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt has occurred */ -#define RTCISR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt has occurred */ -#define RTCISR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt has occurred */ -#define RTCISR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt has occurred */ -#define RTCISR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt has occurred */ -#define RTCISR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt has occurred */ -#define RTCISR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt has occurred */ - -/* - * RTC Interrupt Enable Register - */ -#define RTCIENR_ADDR 0xfffffb10 -#define RTCIENR WORD_REF(RTCIENR_ADDR) - -#define RTCIENR_SW 0x0001 /* Stopwatch interrupt enable */ -#define RTCIENR_MIN 0x0002 /* 1-minute interrupt enable */ -#define RTCIENR_ALM 0x0004 /* Alarm interrupt enable */ -#define RTCIENR_DAY 0x0008 /* 24-hour rollover interrupt enable */ -#define RTCIENR_1HZ 0x0010 /* 1Hz interrupt enable */ -#define RTCIENR_HR 0x0020 /* 1-hour interrupt enable */ -#define RTCIENR_SAM0 0x0100 /* 4Hz / 4.6875Hz interrupt enable */ -#define RTCIENR_SAM1 0x0200 /* 8Hz / 9.3750Hz interrupt enable */ -#define RTCIENR_SAM2 0x0400 /* 16Hz / 18.7500Hz interrupt enable */ -#define RTCIENR_SAM3 0x0800 /* 32Hz / 37.5000Hz interrupt enable */ -#define RTCIENR_SAM4 0x1000 /* 64Hz / 75.0000Hz interrupt enable */ -#define RTCIENR_SAM5 0x2000 /* 128Hz / 150.0000Hz interrupt enable */ -#define RTCIENR_SAM6 0x4000 /* 256Hz / 300.0000Hz interrupt enable */ -#define RTCIENR_SAM7 0x8000 /* 512Hz / 600.0000Hz interrupt enable */ - -/* - * Stopwatch Minutes Register - */ -#define STPWCH_ADDR 0xfffffb12 -#define STPWCH WORD_REF(STPWCH_ADDR) - -#define STPWCH_CNT_MASK 0x003f /* Stopwatch countdown value */ -#define SPTWCH_CNT_SHIFT 0 - -/* - * RTC Day Count Register - */ -#define DAYR_ADDR 0xfffffb1a -#define DAYR WORD_REF(DAYR_ADDR) - -#define DAYR_DAYS_MASK 0x1ff /* Day Setting */ -#define DAYR_DAYS_SHIFT 0 - -/* - * RTC Day Alarm Register - */ -#define DAYALARM_ADDR 0xfffffb1c -#define DAYALARM WORD_REF(DAYALARM_ADDR) - -#define DAYALARM_DAYSAL_MASK 0x01ff /* Day Setting of the Alarm */ -#define DAYALARM_DAYSAL_SHIFT 0 - -/********** - * - * 0xFFFFFCxx -- DRAM Controller - * - **********/ - -/* - * DRAM Memory Configuration Register - */ -#define DRAMMC_ADDR 0xfffffc00 -#define DRAMMC WORD_REF(DRAMMC_ADDR) - -#define DRAMMC_ROW12_MASK 0xc000 /* Row address bit for MD12 */ -#define DRAMMC_ROW12_PA10 0x0000 -#define DRAMMC_ROW12_PA21 0x4000 -#define DRAMMC_ROW12_PA23 0x8000 -#define DRAMMC_ROW0_MASK 0x3000 /* Row address bit for MD0 */ -#define DRAMMC_ROW0_PA11 0x0000 -#define DRAMMC_ROW0_PA22 0x1000 -#define DRAMMC_ROW0_PA23 0x2000 -#define DRAMMC_ROW11 0x0800 /* Row address bit for MD11 PA20/PA22 */ -#define DRAMMC_ROW10 0x0400 /* Row address bit for MD10 PA19/PA21 */ -#define DRAMMC_ROW9 0x0200 /* Row address bit for MD9 PA9/PA19 */ -#define DRAMMC_ROW8 0x0100 /* Row address bit for MD8 PA10/PA20 */ -#define DRAMMC_COL10 0x0080 /* Col address bit for MD10 PA11/PA0 */ -#define DRAMMC_COL9 0x0040 /* Col address bit for MD9 PA10/PA0 */ -#define DRAMMC_COL8 0x0020 /* Col address bit for MD8 PA9/PA0 */ -#define DRAMMC_REF_MASK 0x001f /* Reresh Cycle */ -#define DRAMMC_REF_SHIFT 0 - -/* - * DRAM Control Register - */ -#define DRAMC_ADDR 0xfffffc02 -#define DRAMC WORD_REF(DRAMC_ADDR) - -#define DRAMC_DWE 0x0001 /* DRAM Write Enable */ -#define DRAMC_RST 0x0002 /* Reset Burst Refresh Enable */ -#define DRAMC_LPR 0x0004 /* Low-Power Refresh Enable */ -#define DRAMC_SLW 0x0008 /* Slow RAM */ -#define DRAMC_LSP 0x0010 /* Light Sleep */ -#define DRAMC_MSW 0x0020 /* Slow Multiplexing */ -#define DRAMC_WS_MASK 0x00c0 /* Wait-states */ -#define DRAMC_WS_SHIFT 6 -#define DRAMC_PGSZ_MASK 0x0300 /* Page Size for fast page mode */ -#define DRAMC_PGSZ_SHIFT 8 -#define DRAMC_PGSZ_256K 0x0000 -#define DRAMC_PGSZ_512K 0x0100 -#define DRAMC_PGSZ_1024K 0x0200 -#define DRAMC_PGSZ_2048K 0x0300 -#define DRAMC_EDO 0x0400 /* EDO DRAM */ -#define DRAMC_CLK 0x0800 /* Refresh Timer Clock source select */ -#define DRAMC_BC_MASK 0x3000 /* Page Access Clock Cycle (FP mode) */ -#define DRAMC_BC_SHIFT 12 -#define DRAMC_RM 0x4000 /* Refresh Mode */ -#define DRAMC_EN 0x8000 /* DRAM Controller enable */ - - -/********** - * - * 0xFFFFFDxx -- In-Circuit Emulation (ICE) - * - **********/ - -/* - * ICE Module Address Compare Register - */ -#define ICEMACR_ADDR 0xfffffd00 -#define ICEMACR LONG_REF(ICEMACR_ADDR) - -/* - * ICE Module Address Mask Register - */ -#define ICEMAMR_ADDR 0xfffffd04 -#define ICEMAMR LONG_REF(ICEMAMR_ADDR) - -/* - * ICE Module Control Compare Register - */ -#define ICEMCCR_ADDR 0xfffffd08 -#define ICEMCCR WORD_REF(ICEMCCR_ADDR) - -#define ICEMCCR_PD 0x0001 /* Program/Data Cycle Selection */ -#define ICEMCCR_RW 0x0002 /* Read/Write Cycle Selection */ - -/* - * ICE Module Control Mask Register - */ -#define ICEMCMR_ADDR 0xfffffd0a -#define ICEMCMR WORD_REF(ICEMCMR_ADDR) - -#define ICEMCMR_PDM 0x0001 /* Program/Data Cycle Mask */ -#define ICEMCMR_RWM 0x0002 /* Read/Write Cycle Mask */ - -/* - * ICE Module Control Register - */ -#define ICEMCR_ADDR 0xfffffd0c -#define ICEMCR WORD_REF(ICEMCR_ADDR) - -#define ICEMCR_CEN 0x0001 /* Compare Enable */ -#define ICEMCR_PBEN 0x0002 /* Program Break Enable */ -#define ICEMCR_SB 0x0004 /* Single Breakpoint */ -#define ICEMCR_HMDIS 0x0008 /* HardMap disable */ -#define ICEMCR_BBIEN 0x0010 /* Bus Break Interrupt Enable */ - -/* - * ICE Module Status Register - */ -#define ICEMSR_ADDR 0xfffffd0e -#define ICEMSR WORD_REF(ICEMSR_ADDR) - -#define ICEMSR_EMUEN 0x0001 /* Emulation Enable */ -#define ICEMSR_BRKIRQ 0x0002 /* A-Line Vector Fetch Detected */ -#define ICEMSR_BBIRQ 0x0004 /* Bus Break Interrupt Detected */ -#define ICEMSR_EMIRQ 0x0008 /* EMUIRQ Falling Edge Detected */ - -#endif /* _MC68VZ328_H_ */ diff --git a/include/asm-m68knommu/a.out.h b/include/asm-m68knommu/a.out.h deleted file mode 100644 index ce18ef99de04..000000000000 --- a/include/asm-m68knommu/a.out.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/anchor.h b/include/asm-m68knommu/anchor.h deleted file mode 100644 index 871c0d5cfc3d..000000000000 --- a/include/asm-m68knommu/anchor.h +++ /dev/null @@ -1,112 +0,0 @@ -/****************************************************************************/ - -/* - * anchor.h -- Anchor CO-MEM Lite PCI host bridge part. - * - * (C) Copyright 2000, Moreton Bay (www.moreton.com.au) - */ - -/****************************************************************************/ -#ifndef anchor_h -#define anchor_h -/****************************************************************************/ - -/* - * Define basic addressing info. - */ -#if defined(CONFIG_M5407C3) -#define COMEM_BASE 0xFFFF0000 /* Base of CO-MEM address space */ -#define COMEM_IRQ 25 /* IRQ of anchor part */ -#else -#define COMEM_BASE 0x80000000 /* Base of CO-MEM address space */ -#define COMEM_IRQ 25 /* IRQ of anchor part */ -#endif - -/****************************************************************************/ - -/* - * 4-byte registers of CO-MEM, so adjust register addresses for - * easy access. Handy macro for word access too. - */ -#define LREG(a) ((a) >> 2) -#define WREG(a) ((a) >> 1) - - -/* - * Define base addresses within CO-MEM Lite register address space. - */ -#define COMEM_I2O 0x0000 /* I2O registers */ -#define COMEM_OPREGS 0x0400 /* Operation registers */ -#define COMEM_PCIBUS 0x2000 /* Direct access to PCI bus */ -#define COMEM_SHMEM 0x4000 /* Shared memory region */ - -#define COMEM_SHMEMSIZE 0x4000 /* Size of shared memory */ - - -/* - * Define CO-MEM Registers. - */ -#define COMEM_I2OHISR 0x0030 /* I2O host interrupt status */ -#define COMEM_I2OHIMR 0x0034 /* I2O host interrupt mask */ -#define COMEM_I2OLISR 0x0038 /* I2O local interrupt status */ -#define COMEM_I2OLIMR 0x003c /* I2O local interrupt mask */ -#define COMEM_IBFPFIFO 0x0040 /* I2O inbound free/post FIFO */ -#define COMEM_OBPFFIFO 0x0044 /* I2O outbound post/free FIFO */ -#define COMEM_IBPFFIFO 0x0048 /* I2O inbound post/free FIFO */ -#define COMEM_OBFPFIFO 0x004c /* I2O outbound free/post FIFO */ - -#define COMEM_DAHBASE 0x0460 /* Direct access base address */ - -#define COMEM_NVCMD 0x04a0 /* I2C serial command */ -#define COMEM_NVREAD 0x04a4 /* I2C serial read */ -#define COMEM_NVSTAT 0x04a8 /* I2C status */ - -#define COMEM_DMALBASE 0x04b0 /* DMA local base address */ -#define COMEM_DMAHBASE 0x04b4 /* DMA host base address */ -#define COMEM_DMASIZE 0x04b8 /* DMA size */ -#define COMEM_DMACTL 0x04bc /* DMA control */ - -#define COMEM_HCTL 0x04e0 /* Host control */ -#define COMEM_HINT 0x04e4 /* Host interrupt control/status */ -#define COMEM_HLDATA 0x04e8 /* Host to local data mailbox */ -#define COMEM_LINT 0x04f4 /* Local interrupt contole status */ -#define COMEM_LHDATA 0x04f8 /* Local to host data mailbox */ - -#define COMEM_LBUSCFG 0x04fc /* Local bus configuration */ - - -/* - * Commands and flags for use with Direct Access Register. - */ -#define COMEM_DA_IACK 0x00000000 /* Interrupt acknowledge (read) */ -#define COMEM_DA_SPCL 0x00000010 /* Special cycle (write) */ -#define COMEM_DA_MEMRD 0x00000004 /* Memory read cycle */ -#define COMEM_DA_MEMWR 0x00000004 /* Memory write cycle */ -#define COMEM_DA_IORD 0x00000002 /* I/O read cycle */ -#define COMEM_DA_IOWR 0x00000002 /* I/O write cycle */ -#define COMEM_DA_CFGRD 0x00000006 /* Configuration read cycle */ -#define COMEM_DA_CFGWR 0x00000006 /* Configuration write cycle */ - -#define COMEM_DA_ADDR(a) ((a) & 0xffffe000) - -#define COMEM_DA_OFFSET(a) ((a) & 0x00001fff) - - -/* - * The PCI bus will be limited in what slots will actually be used. - * Define valid device numbers for different boards. - */ -#if defined(CONFIG_M5407C3) -#define COMEM_MINDEV 14 /* Minimum valid DEVICE */ -#define COMEM_MAXDEV 14 /* Maximum valid DEVICE */ -#define COMEM_BRIDGEDEV 15 /* Slot bridge is in */ -#else -#define COMEM_MINDEV 0 /* Minimum valid DEVICE */ -#define COMEM_MAXDEV 3 /* Maximum valid DEVICE */ -#endif - -#define COMEM_MAXPCI (COMEM_MAXDEV+1) /* Maximum PCI devices */ - - -/****************************************************************************/ -#endif /* anchor_h */ diff --git a/include/asm-m68knommu/atomic.h b/include/asm-m68knommu/atomic.h deleted file mode 100644 index d5632a305dae..000000000000 --- a/include/asm-m68knommu/atomic.h +++ /dev/null @@ -1,155 +0,0 @@ -#ifndef __ARCH_M68KNOMMU_ATOMIC__ -#define __ARCH_M68KNOMMU_ATOMIC__ - -#include - -/* - * Atomic operations that C can't guarantee us. Useful for - * resource counting etc.. - */ - -/* - * We do not have SMP m68k systems, so we don't have to deal with that. - */ - -typedef struct { int counter; } atomic_t; -#define ATOMIC_INIT(i) { (i) } - -#define atomic_read(v) ((v)->counter) -#define atomic_set(v, i) (((v)->counter) = i) - -static __inline__ void atomic_add(int i, atomic_t *v) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "d" (i)); -#else - __asm__ __volatile__("addl %1,%0" : "+m" (*v) : "di" (i)); -#endif -} - -static __inline__ void atomic_sub(int i, atomic_t *v) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "d" (i)); -#else - __asm__ __volatile__("subl %1,%0" : "+m" (*v) : "di" (i)); -#endif -} - -static __inline__ int atomic_sub_and_test(int i, atomic_t * v) -{ - char c; -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__("subl %2,%1; seq %0" - : "=d" (c), "+m" (*v) - : "d" (i)); -#else - __asm__ __volatile__("subl %2,%1; seq %0" - : "=d" (c), "+m" (*v) - : "di" (i)); -#endif - return c != 0; -} - -static __inline__ void atomic_inc(volatile atomic_t *v) -{ - __asm__ __volatile__("addql #1,%0" : "+m" (*v)); -} - -/* - * atomic_inc_and_test - increment and test - * @v: pointer of type atomic_t - * - * Atomically increments @v by 1 - * and returns true if the result is zero, or false for all - * other cases. - */ - -static __inline__ int atomic_inc_and_test(volatile atomic_t *v) -{ - char c; - __asm__ __volatile__("addql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -static __inline__ void atomic_dec(volatile atomic_t *v) -{ - __asm__ __volatile__("subql #1,%0" : "+m" (*v)); -} - -static __inline__ int atomic_dec_and_test(volatile atomic_t *v) -{ - char c; - __asm__ __volatile__("subql #1,%1; seq %0" : "=d" (c), "+m" (*v)); - return c != 0; -} - -static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); -} - -static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v) -{ - __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); -} - -/* Atomic operations are already serializing */ -#define smp_mb__before_atomic_dec() barrier() -#define smp_mb__after_atomic_dec() barrier() -#define smp_mb__before_atomic_inc() barrier() -#define smp_mb__after_atomic_inc() barrier() - -static inline int atomic_add_return(int i, atomic_t * v) -{ - unsigned long temp, flags; - - local_irq_save(flags); - temp = *(long *)v; - temp += i; - *(long *)v = temp; - local_irq_restore(flags); - - return temp; -} - -#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) - -static inline int atomic_sub_return(int i, atomic_t * v) -{ - unsigned long temp, flags; - - local_irq_save(flags); - temp = *(long *)v; - temp -= i; - *(long *)v = temp; - local_irq_restore(flags); - - return temp; -} - -#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) -#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) - -static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) -{ - int c, old; - c = atomic_read(v); - for (;;) { - if (unlikely(c == (u))) - break; - old = atomic_cmpxchg((v), c, c + (a)); - if (likely(old == c)) - break; - c = old; - } - return c != (u); -} - -#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0) - -#define atomic_dec_return(v) atomic_sub_return(1,(v)) -#define atomic_inc_return(v) atomic_add_return(1,(v)) - -#include -#endif /* __ARCH_M68KNOMMU_ATOMIC __ */ diff --git a/include/asm-m68knommu/auxvec.h b/include/asm-m68knommu/auxvec.h deleted file mode 100644 index 844d6d52204b..000000000000 --- a/include/asm-m68knommu/auxvec.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASMm68k_AUXVEC_H -#define __ASMm68k_AUXVEC_H - -#endif diff --git a/include/asm-m68knommu/bitops.h b/include/asm-m68knommu/bitops.h deleted file mode 100644 index 6f3685eab44c..000000000000 --- a/include/asm-m68knommu/bitops.h +++ /dev/null @@ -1,336 +0,0 @@ -#ifndef _M68KNOMMU_BITOPS_H -#define _M68KNOMMU_BITOPS_H - -/* - * Copyright 1992, Linus Torvalds. - */ - -#include -#include /* swab32 */ - -#ifdef __KERNEL__ - -#ifndef _LINUX_BITOPS_H -#error only can be included directly -#endif - -#if defined (__mcfisaaplus__) || defined (__mcfisac__) -static inline int ffs(unsigned int val) -{ - if (!val) - return 0; - - asm volatile( - "bitrev %0\n\t" - "ff1 %0\n\t" - : "=d" (val) - : "0" (val) - ); - val++; - return val; -} - -static inline int __ffs(unsigned int val) -{ - asm volatile( - "bitrev %0\n\t" - "ff1 %0\n\t" - : "=d" (val) - : "0" (val) - ); - return val; -} - -#else -#include -#include -#endif - -#include -#include - -static __inline__ void set_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bset %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bset %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __set_bit(nr, addr) set_bit(nr, addr) - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() - -static __inline__ void clear_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bclr %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bclr %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __clear_bit(nr, addr) clear_bit(nr, addr) - -static __inline__ void change_bit(int nr, volatile unsigned long * addr) -{ -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %0,%%a0; bchg %1,(%%a0)" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0", "cc"); -#else - __asm__ __volatile__ ("bchg %1,%0" - : "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - : "cc"); -#endif -} - -#define __change_bit(nr, addr) change_bit(nr, addr) - -static __inline__ int test_and_set_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_set_bit(nr, addr) test_and_set_bit(nr, addr) - -static __inline__ int test_and_clear_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_clear_bit(nr, addr) test_and_clear_bit(nr, addr) - -static __inline__ int test_and_change_bit(int nr, volatile unsigned long * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0\n\tbchg %2,(%%a0)\n\tsne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bchg %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[(nr^31) >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define __test_and_change_bit(nr, addr) test_and_change_bit(nr, addr) - -/* - * This routine doesn't need to be atomic. - */ -static __inline__ int __constant_test_bit(int nr, const volatile unsigned long * addr) -{ - return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0; -} - -static __inline__ int __test_bit(int nr, const volatile unsigned long * addr) -{ - int * a = (int *) addr; - int mask; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - return ((mask & *a) != 0); -} - -#define test_bit(nr,addr) \ -(__builtin_constant_p(nr) ? \ - __constant_test_bit((nr),(addr)) : \ - __test_bit((nr),(addr))) - -#include -#include -#include - -static __inline__ int ext2_set_bit(int nr, volatile void * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bset %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bset %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -static __inline__ int ext2_clear_bit(int nr, volatile void * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; bclr %2,(%%a0); sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("bclr %2,%1; sne %0" - : "=d" (retval), "+m" (((volatile char *)addr)[nr >> 3]) - : "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define ext2_set_bit_atomic(lock, nr, addr) \ - ({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_set_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ - }) - -#define ext2_clear_bit_atomic(lock, nr, addr) \ - ({ \ - int ret; \ - spin_lock(lock); \ - ret = ext2_clear_bit((nr), (addr)); \ - spin_unlock(lock); \ - ret; \ - }) - -static __inline__ int ext2_test_bit(int nr, const volatile void * addr) -{ - char retval; - -#ifdef CONFIG_COLDFIRE - __asm__ __volatile__ ("lea %1,%%a0; btst %2,(%%a0); sne %0" - : "=d" (retval) - : "m" (((const volatile char *)addr)[nr >> 3]), "d" (nr) - : "%a0"); -#else - __asm__ __volatile__ ("btst %2,%1; sne %0" - : "=d" (retval) - : "m" (((const volatile char *)addr)[nr >> 3]), "di" (nr) - /* No clobber */); -#endif - - return retval; -} - -#define ext2_find_first_zero_bit(addr, size) \ - ext2_find_next_zero_bit((addr), (size), 0) - -static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) -{ - unsigned long *p = ((unsigned long *) addr) + (offset >> 5); - unsigned long result = offset & ~31UL; - unsigned long tmp; - - if (offset >= size) - return size; - size -= result; - offset &= 31UL; - if(offset) { - /* We hold the little endian value in tmp, but then the - * shift is illegal. So we could keep a big endian value - * in tmp, like this: - * - * tmp = __swab32(*(p++)); - * tmp |= ~0UL >> (32-offset); - * - * but this would decrease performance, so we change the - * shift: - */ - tmp = *(p++); - tmp |= __swab32(~0UL >> (32-offset)); - if(size < 32) - goto found_first; - if(~tmp) - goto found_middle; - size -= 32; - result += 32; - } - while(size & ~31UL) { - if(~(tmp = *(p++))) - goto found_middle; - result += 32; - size -= 32; - } - if(!size) - return result; - tmp = *p; - -found_first: - /* tmp is little endian, so we would have to swab the shift, - * see above. But then we have to swab tmp below for ffz, so - * we might as well do this here. - */ - return result + ffz(__swab32(tmp) | (~0UL << size)); -found_middle: - return result + ffz(__swab32(tmp)); -} - -#define ext2_find_next_bit(addr, size, off) \ - generic_find_next_le_bit((unsigned long *)(addr), (size), (off)) -#include - -#endif /* __KERNEL__ */ - -#include -#include - -#endif /* _M68KNOMMU_BITOPS_H */ diff --git a/include/asm-m68knommu/bootinfo.h b/include/asm-m68knommu/bootinfo.h deleted file mode 100644 index c12e526f5189..000000000000 --- a/include/asm-m68knommu/bootinfo.h +++ /dev/null @@ -1,2 +0,0 @@ - -/* Nothing for m68knommu */ diff --git a/include/asm-m68knommu/bootstd.h b/include/asm-m68knommu/bootstd.h deleted file mode 100644 index bdc1a4ac4fe9..000000000000 --- a/include/asm-m68knommu/bootstd.h +++ /dev/null @@ -1,132 +0,0 @@ -/* bootstd.h: Bootloader system call interface - * - * (c) 1999, Rt-Control, Inc. - */ - -#ifndef __BOOTSTD_H__ -#define __BOOTSTD_H__ - -#define NR_BSC 21 /* last used bootloader system call */ - -#define __BN_reset 0 /* reset and start the bootloader */ -#define __BN_test 1 /* tests the system call interface */ -#define __BN_exec 2 /* executes a bootloader image */ -#define __BN_exit 3 /* terminates a bootloader image */ -#define __BN_program 4 /* program FLASH from a chain */ -#define __BN_erase 5 /* erase sector(s) of FLASH */ -#define __BN_open 6 -#define __BN_write 7 -#define __BN_read 8 -#define __BN_close 9 -#define __BN_mmap 10 /* map a file descriptor into memory */ -#define __BN_munmap 11 /* remove a file to memory mapping */ -#define __BN_gethwaddr 12 /* get the hardware address of my interfaces */ -#define __BN_getserialnum 13 /* get the serial number of this board */ -#define __BN_getbenv 14 /* get a bootloader envvar */ -#define __BN_setbenv 15 /* get a bootloader envvar */ -#define __BN_setpmask 16 /* set the protection mask */ -#define __BN_readenv 17 /* read environment variables */ -#define __BN_flash_chattr_range 18 -#define __BN_flash_erase_range 19 -#define __BN_flash_write_range 20 - -/* Calling conventions compatible to (uC)linux/68k - * We use simmilar macros to call into the bootloader as for uClinux - */ - -#define __bsc_return(type, res) \ -do { \ - if ((unsigned long)(res) >= (unsigned long)(-64)) { \ - /* let errno be a function, preserve res in %d0 */ \ - int __err = -(res); \ - errno = __err; \ - res = -1; \ - } \ - return (type)(res); \ -} while (0) - -#define _bsc0(type,name) \ -type name(void) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res) \ - ); \ - __bsc_return(type,__res); \ -} - -#define _bsc1(type,name,atype,a) \ -type name(atype a) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - register long __a __asm__ ("%d1") = (long)a; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res), "d" (__a) \ - ); \ - __bsc_return(type,__res); \ -} - -#define _bsc2(type,name,atype,a,btype,b) \ -type name(atype a, btype b) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - register long __a __asm__ ("%d1") = (long)a; \ - register long __b __asm__ ("%d2") = (long)b; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res), "d" (__a), "d" (__b) \ - ); \ - __bsc_return(type,__res); \ -} - -#define _bsc3(type,name,atype,a,btype,b,ctype,c) \ -type name(atype a, btype b, ctype c) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - register long __a __asm__ ("%d1") = (long)a; \ - register long __b __asm__ ("%d2") = (long)b; \ - register long __c __asm__ ("%d3") = (long)c; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res), "d" (__a), "d" (__b), \ - "d" (__c) \ - ); \ - __bsc_return(type,__res); \ -} - -#define _bsc4(type,name,atype,a,btype,b,ctype,c,dtype,d) \ -type name(atype a, btype b, ctype c, dtype d) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - register long __a __asm__ ("%d1") = (long)a; \ - register long __b __asm__ ("%d2") = (long)b; \ - register long __c __asm__ ("%d3") = (long)c; \ - register long __d __asm__ ("%d4") = (long)d; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res), "d" (__a), "d" (__b), \ - "d" (__c), "d" (__d) \ - ); \ - __bsc_return(type,__res); \ -} - -#define _bsc5(type,name,atype,a,btype,b,ctype,c,dtype,d,etype,e) \ -type name(atype a, btype b, ctype c, dtype d, etype e) \ -{ \ - register long __res __asm__ ("%d0") = __BN_##name; \ - register long __a __asm__ ("%d1") = (long)a; \ - register long __b __asm__ ("%d2") = (long)b; \ - register long __c __asm__ ("%d3") = (long)c; \ - register long __d __asm__ ("%d4") = (long)d; \ - register long __e __asm__ ("%d5") = (long)e; \ - __asm__ __volatile__ ("trap #2" \ - : "=g" (__res) \ - : "0" (__res), "d" (__a), "d" (__b), \ - "d" (__c), "d" (__d), "d" (__e) \ - ); \ - __bsc_return(type,__res); \ -} - -#endif /* __BOOTSTD_H__ */ diff --git a/include/asm-m68knommu/bug.h b/include/asm-m68knommu/bug.h deleted file mode 100644 index 70e7dc0af21a..000000000000 --- a/include/asm-m68knommu/bug.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _M68KNOMMU_BUG_H -#define _M68KNOMMU_BUG_H -#include -#endif diff --git a/include/asm-m68knommu/bugs.h b/include/asm-m68knommu/bugs.h deleted file mode 100644 index 5f382dac3a60..000000000000 --- a/include/asm-m68knommu/bugs.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * include/asm-m68k/bugs.h - * - * Copyright (C) 1994 Linus Torvalds - */ - -/* - * This is included by init/main.c to check for architecture-dependent bugs. - * - * Needs: - * void check_bugs(void); - */ - -static void check_bugs(void) -{ -} diff --git a/include/asm-m68knommu/byteorder.h b/include/asm-m68knommu/byteorder.h deleted file mode 100644 index 20bb4426b610..000000000000 --- a/include/asm-m68knommu/byteorder.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef _M68KNOMMU_BYTEORDER_H -#define _M68KNOMMU_BYTEORDER_H - -#include - -#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__) -# define __BYTEORDER_HAS_U64__ -# define __SWAB_64_THRU_32__ -#endif - -#if defined (__mcfisaaplus__) || defined (__mcfisac__) -static inline __attribute_const__ __u32 ___arch__swab32(__u32 val) -{ - asm( - "byterev %0" - : "=d" (val) - : "0" (val) - ); - return val; -} - -#define __arch__swab32(x) ___arch__swab32(x) -#endif - -#include - -#endif /* _M68KNOMMU_BYTEORDER_H */ diff --git a/include/asm-m68knommu/cache.h b/include/asm-m68knommu/cache.h deleted file mode 100644 index 24e9eace5f8c..000000000000 --- a/include/asm-m68knommu/cache.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef __ARCH_M68KNOMMU_CACHE_H -#define __ARCH_M68KNOMMU_CACHE_H - -/* bytes per L1 cache line */ -#define L1_CACHE_BYTES 16 /* this need to be at least 1 */ - -/* m68k-elf-gcc 2.95.2 doesn't like these */ - -#define __cacheline_aligned -#define ____cacheline_aligned - -#endif diff --git a/include/asm-m68knommu/cachectl.h b/include/asm-m68knommu/cachectl.h deleted file mode 100644 index bcf5a6a9dd52..000000000000 --- a/include/asm-m68knommu/cachectl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/cacheflush.h b/include/asm-m68knommu/cacheflush.h deleted file mode 100644 index 87e5dc0413b4..000000000000 --- a/include/asm-m68knommu/cacheflush.h +++ /dev/null @@ -1,84 +0,0 @@ -#ifndef _M68KNOMMU_CACHEFLUSH_H -#define _M68KNOMMU_CACHEFLUSH_H - -/* - * (C) Copyright 2000-2004, Greg Ungerer - */ -#include - -#define flush_cache_all() __flush_cache_all() -#define flush_cache_mm(mm) do { } while (0) -#define flush_cache_dup_mm(mm) do { } while (0) -#define flush_cache_range(vma, start, end) __flush_cache_all() -#define flush_cache_page(vma, vmaddr) do { } while (0) -#define flush_dcache_range(start,len) __flush_cache_all() -#define flush_dcache_page(page) do { } while (0) -#define flush_dcache_mmap_lock(mapping) do { } while (0) -#define flush_dcache_mmap_unlock(mapping) do { } while (0) -#define flush_icache_range(start,len) __flush_cache_all() -#define flush_icache_page(vma,pg) do { } while (0) -#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) -#define flush_cache_vmap(start, end) do { } while (0) -#define flush_cache_vunmap(start, end) do { } while (0) - -#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) -#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ - memcpy(dst, src, len) - -static inline void __flush_cache_all(void) -{ -#ifdef CONFIG_M5407 - /* - * Use cpushl to push and invalidate all cache lines. - * Gas doesn't seem to know how to generate the ColdFire - * cpushl instruction... Oh well, bit stuff it for now. - */ - __asm__ __volatile__ ( - "nop\n\t" - "clrl %%d0\n\t" - "1:\n\t" - "movel %%d0,%%a0\n\t" - "2:\n\t" - ".word 0xf468\n\t" - "addl #0x10,%%a0\n\t" - "cmpl #0x00000800,%%a0\n\t" - "blt 2b\n\t" - "addql #1,%%d0\n\t" - "cmpil #4,%%d0\n\t" - "bne 1b\n\t" - "movel #0xb6088500,%%d0\n\t" - "movec %%d0,%%CACR\n\t" - : : : "d0", "a0" ); -#endif /* CONFIG_M5407 */ -#if defined(CONFIG_M527x) || defined(CONFIG_M528x) - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M527x || CONFIG_M528x */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) - __asm__ __volatile__ ( - "movel #0x81000100, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ -#ifdef CONFIG_M5249 - __asm__ __volatile__ ( - "movel #0xa1000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M5249 */ -#ifdef CONFIG_M532x - __asm__ __volatile__ ( - "movel #0x81000200, %%d0\n\t" - "movec %%d0, %%CACR\n\t" - "nop\n\t" - : : : "d0" ); -#endif /* CONFIG_M532x */ -} - -#endif /* _M68KNOMMU_CACHEFLUSH_H */ diff --git a/include/asm-m68knommu/checksum.h b/include/asm-m68knommu/checksum.h deleted file mode 100644 index 81883482ffb1..000000000000 --- a/include/asm-m68knommu/checksum.h +++ /dev/null @@ -1,132 +0,0 @@ -#ifndef _M68K_CHECKSUM_H -#define _M68K_CHECKSUM_H - -#include - -/* - * computes the checksum of a memory block at buff, length len, - * and adds in "sum" (32-bit) - * - * returns a 32-bit number suitable for feeding into itself - * or csum_tcpudp_magic - * - * this function must be called with even lengths, except - * for the last fragment, which may be odd - * - * it's best to have buff aligned on a 32-bit boundary - */ -__wsum csum_partial(const void *buff, int len, __wsum sum); - -/* - * the same as csum_partial, but copies from src while it - * checksums - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -__wsum csum_partial_copy_nocheck(const void *src, void *dst, - int len, __wsum sum); - - -/* - * the same as csum_partial_copy, but copies from user space. - * - * here even more important to align src and dst on a 32-bit (or even - * better 64-bit) boundary - */ - -extern __wsum csum_partial_copy_from_user(const void __user *src, - void *dst, int len, __wsum sum, int *csum_err); - -__sum16 ip_fast_csum(const void *iph, unsigned int ihl); - -/* - * Fold a partial checksum - */ - -static inline __sum16 csum_fold(__wsum sum) -{ - unsigned int tmp = (__force u32)sum; -#ifdef CONFIG_COLDFIRE - tmp = (tmp & 0xffff) + (tmp >> 16); - tmp = (tmp & 0xffff) + (tmp >> 16); - return (__force __sum16)~tmp; -#else - __asm__("swap %1\n\t" - "addw %1, %0\n\t" - "clrw %1\n\t" - "addxw %1, %0" - : "=&d" (sum), "=&d" (tmp) - : "0" (sum), "1" (sum)); - return (__force __sum16)~sum; -#endif -} - - -/* - * computes the checksum of the TCP/UDP pseudo-header - * returns a 16-bit checksum, already complemented - */ - -static inline __wsum -csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - __asm__ ("addl %1,%0\n\t" - "addxl %4,%0\n\t" - "addxl %5,%0\n\t" - "clrl %1\n\t" - "addxl %1,%0" - : "=&d" (sum), "=&d" (saddr) - : "0" (daddr), "1" (saddr), "d" (len + proto), - "d"(sum)); - return sum; -} - -static inline __sum16 -csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len, - unsigned short proto, __wsum sum) -{ - return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); -} - -/* - * this routine is used for miscellaneous IP-like checksums, mainly - * in icmp.c - */ - -extern __sum16 ip_compute_csum(const void *buff, int len); - -#define _HAVE_ARCH_IPV6_CSUM -static __inline__ __sum16 -csum_ipv6_magic(const struct in6_addr *saddr, const struct in6_addr *daddr, - __u32 len, unsigned short proto, __wsum sum) -{ - register unsigned long tmp; - __asm__("addl %2@,%0\n\t" - "movel %2@(4),%1\n\t" - "addxl %1,%0\n\t" - "movel %2@(8),%1\n\t" - "addxl %1,%0\n\t" - "movel %2@(12),%1\n\t" - "addxl %1,%0\n\t" - "movel %3@,%1\n\t" - "addxl %1,%0\n\t" - "movel %3@(4),%1\n\t" - "addxl %1,%0\n\t" - "movel %3@(8),%1\n\t" - "addxl %1,%0\n\t" - "movel %3@(12),%1\n\t" - "addxl %1,%0\n\t" - "addxl %4,%0\n\t" - "clrl %1\n\t" - "addxl %1,%0" - : "=&d" (sum), "=&d" (tmp) - : "a" (saddr), "a" (daddr), "d" (len + proto), - "0" (sum)); - - return csum_fold(sum); -} - -#endif /* _M68K_CHECKSUM_H */ diff --git a/include/asm-m68knommu/coldfire.h b/include/asm-m68knommu/coldfire.h deleted file mode 100644 index 83a9fa4e618a..000000000000 --- a/include/asm-m68knommu/coldfire.h +++ /dev/null @@ -1,51 +0,0 @@ -/****************************************************************************/ - -/* - * coldfire.h -- Motorola ColdFire CPU sepecific defines - * - * (C) Copyright 1999-2006, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef coldfire_h -#define coldfire_h -/****************************************************************************/ - - -/* - * Define master clock frequency. This is essentially done at config - * time now. No point enumerating dozens of possible clock options - * here. Also the peripheral clock (bus clock) divide ratio is set - * at config time too. - */ -#ifdef CONFIG_CLOCK_SET -#define MCF_CLK CONFIG_CLOCK_FREQ -#define MCF_BUSCLK (CONFIG_CLOCK_FREQ / CONFIG_CLOCK_DIV) -#else -#error "Don't know what your ColdFire CPU clock frequency is??" -#endif - -/* - * Define the processor support peripherals base address. - * This is generally setup by the boards start up code. - */ -#define MCF_MBAR 0x10000000 -#define MCF_MBAR2 0x80000000 -#if defined(CONFIG_M520x) -#define MCF_IPSBAR 0xFC000000 -#else -#define MCF_IPSBAR 0x40000000 -#endif - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ - defined(CONFIG_M520x) -#undef MCF_MBAR -#define MCF_MBAR MCF_IPSBAR -#elif defined(CONFIG_M532x) -#undef MCF_MBAR -#define MCF_MBAR 0x00000000 -#endif - -/****************************************************************************/ -#endif /* coldfire_h */ diff --git a/include/asm-m68knommu/commproc.h b/include/asm-m68knommu/commproc.h deleted file mode 100644 index edf5eb6c08d2..000000000000 --- a/include/asm-m68knommu/commproc.h +++ /dev/null @@ -1,703 +0,0 @@ - -/* - * 68360 Communication Processor Module. - * Copyright (c) 2000 Michael Leslie (mc68360) after: - * Copyright (c) 1997 Dan Malek (mpc8xx) - * - * This file contains structures and information for the communication - * processor channels. Some CPM control and status is available - * through the 68360 internal memory map. See include/asm/360_immap.h for details. - * This file is not a complete map of all of the 360 QUICC's capabilities - * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. - */ -#ifndef __CPM_360__ -#define __CPM_360__ - - -/* CPM Command register masks: */ -#define CPM_CR_RST ((ushort)0x8000) -#define CPM_CR_OPCODE ((ushort)0x0f00) -#define CPM_CR_CHAN ((ushort)0x00f0) -#define CPM_CR_FLG ((ushort)0x0001) - -/* CPM Command set (opcodes): */ -#define CPM_CR_INIT_TRX ((ushort)0x0000) -#define CPM_CR_INIT_RX ((ushort)0x0001) -#define CPM_CR_INIT_TX ((ushort)0x0002) -#define CPM_CR_HUNT_MODE ((ushort)0x0003) -#define CPM_CR_STOP_TX ((ushort)0x0004) -#define CPM_CR_GRSTOP_TX ((ushort)0x0005) -#define CPM_CR_RESTART_TX ((ushort)0x0006) -#define CPM_CR_CLOSE_RXBD ((ushort)0x0007) -#define CPM_CR_SET_GADDR ((ushort)0x0008) -#define CPM_CR_GCI_TIMEOUT ((ushort)0x0009) -#define CPM_CR_GCI_ABORT ((ushort)0x000a) -#define CPM_CR_RESET_BCS ((ushort)0x000a) - -/* CPM Channel numbers. */ -#define CPM_CR_CH_SCC1 ((ushort)0x0000) -#define CPM_CR_CH_SCC2 ((ushort)0x0004) -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / Timers */ -#define CPM_CR_CH_TMR ((ushort)0x0005) -#define CPM_CR_CH_SCC3 ((ushort)0x0008) -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / IDMA1 */ -#define CPM_CR_CH_IDMA1 ((ushort)0x0009) -#define CPM_CR_CH_SCC4 ((ushort)0x000c) -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / IDMA2 */ -#define CPM_CR_CH_IDMA2 ((ushort)0x000d) - - -#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4)) - -#if 1 /* mleslie: I dinna think we have any such restrictions on - * DP RAM aboard the 360 board - see the MC68360UM p.3-3 */ - -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -/* mleslie: The uCquicc board is using no extra microcode in DPRAM */ -#define CPM_DATAONLY_BASE ((uint)0x0000) -#define CPM_DATAONLY_SIZE ((uint)0x0800) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) - -#endif - - -/* Export the base address of the communication processor registers - * and dual port ram. */ -/* extern cpm360_t *cpmp; */ /* Pointer to comm processor */ -extern QUICC *pquicc; -uint m360_cpm_dpalloc(uint size); -/* void *m360_cpm_hostalloc(uint size); */ -void m360_cpm_setbrg(uint brg, uint rate); - -#if 0 /* use QUICC_BD declared in include/asm/m68360_quicc.h */ -/* Buffer descriptors used by many of the CPM protocols. */ -typedef struct cpm_buf_desc { - ushort cbd_sc; /* Status and Control */ - ushort cbd_datlen; /* Data length in buffer */ - uint cbd_bufaddr; /* Buffer address in host memory */ -} cbd_t; -#endif - - -/* rx bd status/control bits */ -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ -#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor in table */ -#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ -#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame OR control char */ - -#define BD_SC_FIRST ((ushort)0x0400) /* 1st buffer in an HDLC frame */ -#define BD_SC_ADDR ((ushort)0x0400) /* 1st byte is a multidrop address */ - -#define BD_SC_CM ((ushort)0x0200) /* Continous mode */ -#define BD_SC_ID ((ushort)0x0100) /* Received too many idles */ - -#define BD_SC_AM ((ushort)0x0080) /* Multidrop address match */ -#define BD_SC_DE ((ushort)0x0080) /* DPLL Error (HDLC) */ - -#define BD_SC_BR ((ushort)0x0020) /* Break received */ -#define BD_SC_LG ((ushort)0x0020) /* Frame length violation (HDLC) */ - -#define BD_SC_FR ((ushort)0x0010) /* Framing error */ -#define BD_SC_NO ((ushort)0x0010) /* Nonoctet aligned frame (HDLC) */ - -#define BD_SC_PR ((ushort)0x0008) /* Parity error */ -#define BD_SC_AB ((ushort)0x0008) /* Received abort Sequence (HDLC) */ - -#define BD_SC_OV ((ushort)0x0002) /* Overrun */ -#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */ - -/* tx bd status/control bits (as differ from rx bd) */ -#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ -#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */ -#define BD_SC_P ((ushort)0x0100) /* xmt preamble */ -#define BD_SC_UN ((ushort)0x0002) /* Underrun */ - - - - -/* Parameter RAM offsets. */ - - - -/* In 2.4 ppc, the PROFF_S?C? are used as byte offsets into DPRAM. - * In 2.0, we use a more structured C struct map of DPRAM, and so - * instead, we need only a parameter ram `slot' */ - -#define PRSLOT_SCC1 0 -#define PRSLOT_SCC2 1 -#define PRSLOT_SCC3 2 -#define PRSLOT_SMC1 2 -#define PRSLOT_SCC4 3 -#define PRSLOT_SMC2 3 - - -/* #define PROFF_SCC1 ((uint)0x0000) */ -/* #define PROFF_SCC2 ((uint)0x0100) */ -/* #define PROFF_SCC3 ((uint)0x0200) */ -/* #define PROFF_SMC1 ((uint)0x0280) */ -/* #define PROFF_SCC4 ((uint)0x0300) */ -/* #define PROFF_SMC2 ((uint)0x0380) */ - - -/* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. - */ -typedef struct smc_uart { - ushort smc_rbase; /* Rx Buffer descriptor base address */ - ushort smc_tbase; /* Tx Buffer descriptor base address */ - u_char smc_rfcr; /* Rx function code */ - u_char smc_tfcr; /* Tx function code */ - ushort smc_mrblr; /* Max receive buffer length */ - uint smc_rstate; /* Internal */ - uint smc_idp; /* Internal */ - ushort smc_rbptr; /* Internal */ - ushort smc_ibc; /* Internal */ - uint smc_rxtmp; /* Internal */ - uint smc_tstate; /* Internal */ - uint smc_tdp; /* Internal */ - ushort smc_tbptr; /* Internal */ - ushort smc_tbc; /* Internal */ - uint smc_txtmp; /* Internal */ - ushort smc_maxidl; /* Maximum idle characters */ - ushort smc_tmpidl; /* Temporary idle counter */ - ushort smc_brklen; /* Last received break length */ - ushort smc_brkec; /* rcv'd break condition counter */ - ushort smc_brkcr; /* xmt break count register */ - ushort smc_rmask; /* Temporary bit mask */ -} smc_uart_t; - -/* Function code bits. -*/ -#define SMC_EB ((u_char)0x10) /* Set big endian byte order */ - -/* SMC uart mode register. -*/ -#define SMCMR_REN ((ushort)0x0001) -#define SMCMR_TEN ((ushort)0x0002) -#define SMCMR_DM ((ushort)0x000c) -#define SMCMR_SM_GCI ((ushort)0x0000) -#define SMCMR_SM_UART ((ushort)0x0020) -#define SMCMR_SM_TRANS ((ushort)0x0030) -#define SMCMR_SM_MASK ((ushort)0x0030) -#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */ -#define SMCMR_REVD SMCMR_PM_EVEN -#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */ -#define SMCMR_BS SMCMR_PEN -#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */ -#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */ -#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK) - -/* SMC2 as Centronics parallel printer. It is half duplex, in that - * it can only receive or transmit. The parameter ram values for - * each direction are either unique or properly overlap, so we can - * include them in one structure. - */ -typedef struct smc_centronics { - ushort scent_rbase; - ushort scent_tbase; - u_char scent_cfcr; - u_char scent_smask; - ushort scent_mrblr; - uint scent_rstate; - uint scent_r_ptr; - ushort scent_rbptr; - ushort scent_r_cnt; - uint scent_rtemp; - uint scent_tstate; - uint scent_t_ptr; - ushort scent_tbptr; - ushort scent_t_cnt; - uint scent_ttemp; - ushort scent_max_sl; - ushort scent_sl_cnt; - ushort scent_character1; - ushort scent_character2; - ushort scent_character3; - ushort scent_character4; - ushort scent_character5; - ushort scent_character6; - ushort scent_character7; - ushort scent_character8; - ushort scent_rccm; - ushort scent_rccr; -} smc_cent_t; - -/* Centronics Status Mask Register. -*/ -#define SMC_CENT_F ((u_char)0x08) -#define SMC_CENT_PE ((u_char)0x04) -#define SMC_CENT_S ((u_char)0x02) - -/* SMC Event and Mask register. -*/ -#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */ -#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */ -#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */ -#define SMCM_BSY ((unsigned char)0x04) -#define SMCM_TX ((unsigned char)0x02) -#define SMCM_RX ((unsigned char)0x01) - -/* Baud rate generators. -*/ -#define CPM_BRG_RST ((uint)0x00020000) -#define CPM_BRG_EN ((uint)0x00010000) -#define CPM_BRG_EXTC_INT ((uint)0x00000000) -#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000) -#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000) -#define CPM_BRG_ATB ((uint)0x00002000) -#define CPM_BRG_CD_MASK ((uint)0x00001ffe) -#define CPM_BRG_DIV16 ((uint)0x00000001) - -/* SCCs. -*/ -#define SCC_GSMRH_IRP ((uint)0x00040000) -#define SCC_GSMRH_GDE ((uint)0x00010000) -#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000) -#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000) -#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000) -#define SCC_GSMRH_REVD ((uint)0x00002000) -#define SCC_GSMRH_TRX ((uint)0x00001000) -#define SCC_GSMRH_TTX ((uint)0x00000800) -#define SCC_GSMRH_CDP ((uint)0x00000400) -#define SCC_GSMRH_CTSP ((uint)0x00000200) -#define SCC_GSMRH_CDS ((uint)0x00000100) -#define SCC_GSMRH_CTSS ((uint)0x00000080) -#define SCC_GSMRH_TFL ((uint)0x00000040) -#define SCC_GSMRH_RFW ((uint)0x00000020) -#define SCC_GSMRH_TXSY ((uint)0x00000010) -#define SCC_GSMRH_SYNL16 ((uint)0x0000000c) -#define SCC_GSMRH_SYNL8 ((uint)0x00000008) -#define SCC_GSMRH_SYNL4 ((uint)0x00000004) -#define SCC_GSMRH_RTSM ((uint)0x00000002) -#define SCC_GSMRH_RSYN ((uint)0x00000001) - -#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */ -#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000) -#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000) -#define SCC_GSMRL_EDGE_POS ((uint)0x20000000) -#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000) -#define SCC_GSMRL_TCI ((uint)0x10000000) -#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000) -#define SCC_GSMRL_TSNC_4 ((uint)0x08000000) -#define SCC_GSMRL_TSNC_14 ((uint)0x04000000) -#define SCC_GSMRL_TSNC_INF ((uint)0x00000000) -#define SCC_GSMRL_RINV ((uint)0x02000000) -#define SCC_GSMRL_TINV ((uint)0x01000000) -#define SCC_GSMRL_TPL_128 ((uint)0x00c00000) -#define SCC_GSMRL_TPL_64 ((uint)0x00a00000) -#define SCC_GSMRL_TPL_48 ((uint)0x00800000) -#define SCC_GSMRL_TPL_32 ((uint)0x00600000) -#define SCC_GSMRL_TPL_16 ((uint)0x00400000) -#define SCC_GSMRL_TPL_8 ((uint)0x00200000) -#define SCC_GSMRL_TPL_NONE ((uint)0x00000000) -#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000) -#define SCC_GSMRL_TPP_01 ((uint)0x00100000) -#define SCC_GSMRL_TPP_10 ((uint)0x00080000) -#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000) -#define SCC_GSMRL_TEND ((uint)0x00040000) -#define SCC_GSMRL_TDCR_32 ((uint)0x00030000) -#define SCC_GSMRL_TDCR_16 ((uint)0x00020000) -#define SCC_GSMRL_TDCR_8 ((uint)0x00010000) -#define SCC_GSMRL_TDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000) -#define SCC_GSMRL_RDCR_16 ((uint)0x00008000) -#define SCC_GSMRL_RDCR_8 ((uint)0x00004000) -#define SCC_GSMRL_RDCR_1 ((uint)0x00000000) -#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000) -#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000) -#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000) -#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800) -#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600) -#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400) -#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200) -#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100) -#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000) -#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */ -#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080) -#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040) -#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000) -#define SCC_GSMRL_ENR ((uint)0x00000020) -#define SCC_GSMRL_ENT ((uint)0x00000010) -#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c) -#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009) -#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008) -#define SCC_GSMRL_MODE_V14 ((uint)0x00000007) -#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006) -#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005) -#define SCC_GSMRL_MODE_UART ((uint)0x00000004) -#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003) -#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002) -#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000) - -#define SCC_TODR_TOD ((ushort)0x8000) - -/* SCC Event and Mask register. -*/ -#define SCCM_TXE ((unsigned char)0x10) -#define SCCM_BSY ((unsigned char)0x04) -#define SCCM_TX ((unsigned char)0x02) -#define SCCM_RX ((unsigned char)0x01) - -typedef struct scc_param { - ushort scc_rbase; /* Rx Buffer descriptor base address */ - ushort scc_tbase; /* Tx Buffer descriptor base address */ - u_char scc_rfcr; /* Rx function code */ - u_char scc_tfcr; /* Tx function code */ - ushort scc_mrblr; /* Max receive buffer length */ - uint scc_rstate; /* Internal */ - uint scc_idp; /* Internal */ - ushort scc_rbptr; /* Internal */ - ushort scc_ibc; /* Internal */ - uint scc_rxtmp; /* Internal */ - uint scc_tstate; /* Internal */ - uint scc_tdp; /* Internal */ - ushort scc_tbptr; /* Internal */ - ushort scc_tbc; /* Internal */ - uint scc_txtmp; /* Internal */ - uint scc_rcrc; /* Internal */ - uint scc_tcrc; /* Internal */ -} sccp_t; - - -/* Function code bits. - */ -#define SCC_EB ((u_char)0x10) /* Set big endian byte order */ -#define SCC_FC_DMA ((u_char)0x08) /* Set SDMA */ - -/* CPM Ethernet through SCC1. - */ -typedef struct scc_enet { - sccp_t sen_genscc; - uint sen_cpres; /* Preset CRC */ - uint sen_cmask; /* Constant mask for CRC */ - uint sen_crcec; /* CRC Error counter */ - uint sen_alec; /* alignment error counter */ - uint sen_disfc; /* discard frame counter */ - ushort sen_pads; /* Tx short frame pad character */ - ushort sen_retlim; /* Retry limit threshold */ - ushort sen_retcnt; /* Retry limit counter */ - ushort sen_maxflr; /* maximum frame length register */ - ushort sen_minflr; /* minimum frame length register */ - ushort sen_maxd1; /* maximum DMA1 length */ - ushort sen_maxd2; /* maximum DMA2 length */ - ushort sen_maxd; /* Rx max DMA */ - ushort sen_dmacnt; /* Rx DMA counter */ - ushort sen_maxb; /* Max BD byte count */ - ushort sen_gaddr1; /* Group address filter */ - ushort sen_gaddr2; - ushort sen_gaddr3; - ushort sen_gaddr4; - uint sen_tbuf0data0; /* Save area 0 - current frame */ - uint sen_tbuf0data1; /* Save area 1 - current frame */ - uint sen_tbuf0rba; /* Internal */ - uint sen_tbuf0crc; /* Internal */ - ushort sen_tbuf0bcnt; /* Internal */ - ushort sen_paddrh; /* physical address (MSB) */ - ushort sen_paddrm; - ushort sen_paddrl; /* physical address (LSB) */ - ushort sen_pper; /* persistence */ - ushort sen_rfbdptr; /* Rx first BD pointer */ - ushort sen_tfbdptr; /* Tx first BD pointer */ - ushort sen_tlbdptr; /* Tx last BD pointer */ - uint sen_tbuf1data0; /* Save area 0 - current frame */ - uint sen_tbuf1data1; /* Save area 1 - current frame */ - uint sen_tbuf1rba; /* Internal */ - uint sen_tbuf1crc; /* Internal */ - ushort sen_tbuf1bcnt; /* Internal */ - ushort sen_txlen; /* Tx Frame length counter */ - ushort sen_iaddr1; /* Individual address filter */ - ushort sen_iaddr2; - ushort sen_iaddr3; - ushort sen_iaddr4; - ushort sen_boffcnt; /* Backoff counter */ - - /* NOTE: Some versions of the manual have the following items - * incorrectly documented. Below is the proper order. - */ - ushort sen_taddrh; /* temp address (MSB) */ - ushort sen_taddrm; - ushort sen_taddrl; /* temp address (LSB) */ -} scc_enet_t; - - - -#if defined (CONFIG_UCQUICC) -/* uCquicc has the following signals connected to Ethernet: - * 68360 - lxt905 - * PA0/RXD1 - rxd - * PA1/TXD1 - txd - * PA8/CLK1 - tclk - * PA9/CLK2 - rclk - * PC0/!RTS1 - t_en - * PC1/!CTS1 - col - * PC5/!CD1 - cd - */ -#define PA_ENET_RXD PA_RXD1 -#define PA_ENET_TXD PA_TXD1 -#define PA_ENET_TCLK PA_CLK1 -#define PA_ENET_RCLK PA_CLK2 -#define PC_ENET_TENA PC_RTS1 -#define PC_ENET_CLSN PC_CTS1 -#define PC_ENET_RENA PC_CD1 - -/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to - * SCC1. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - -#endif /* config_ucquicc */ - - -#ifdef MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif - -/* SCC Event register as used by Ethernet. -*/ -#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ -#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */ -#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */ -#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */ -#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */ -#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */ - -/* SCC Mode Register (PMSR) as used by Ethernet. -*/ -#define SCC_PMSR_HBC ((ushort)0x8000) /* Enable heartbeat */ -#define SCC_PMSR_FC ((ushort)0x4000) /* Force collision */ -#define SCC_PMSR_RSH ((ushort)0x2000) /* Receive short frames */ -#define SCC_PMSR_IAM ((ushort)0x1000) /* Check individual hash */ -#define SCC_PMSR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */ -#define SCC_PMSR_PRO ((ushort)0x0200) /* Promiscuous mode */ -#define SCC_PMSR_BRO ((ushort)0x0100) /* Catch broadcast pkts */ -#define SCC_PMSR_SBT ((ushort)0x0080) /* Special backoff timer */ -#define SCC_PMSR_LPB ((ushort)0x0040) /* Set Loopback mode */ -#define SCC_PMSR_SIP ((ushort)0x0020) /* Sample Input Pins */ -#define SCC_PMSR_LCW ((ushort)0x0010) /* Late collision window */ -#define SCC_PMSR_NIB22 ((ushort)0x000a) /* Start frame search */ -#define SCC_PMSR_FDE ((ushort)0x0001) /* Full duplex enable */ - -/* Buffer descriptor control/status used by Ethernet receive. -*/ -#define BD_ENET_RX_EMPTY ((ushort)0x8000) -#define BD_ENET_RX_WRAP ((ushort)0x2000) -#define BD_ENET_RX_INTR ((ushort)0x1000) -#define BD_ENET_RX_LAST ((ushort)0x0800) -#define BD_ENET_RX_FIRST ((ushort)0x0400) -#define BD_ENET_RX_MISS ((ushort)0x0100) -#define BD_ENET_RX_LG ((ushort)0x0020) -#define BD_ENET_RX_NO ((ushort)0x0010) -#define BD_ENET_RX_SH ((ushort)0x0008) -#define BD_ENET_RX_CR ((ushort)0x0004) -#define BD_ENET_RX_OV ((ushort)0x0002) -#define BD_ENET_RX_CL ((ushort)0x0001) -#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ - -/* Buffer descriptor control/status used by Ethernet transmit. -*/ -#define BD_ENET_TX_READY ((ushort)0x8000) -#define BD_ENET_TX_PAD ((ushort)0x4000) -#define BD_ENET_TX_WRAP ((ushort)0x2000) -#define BD_ENET_TX_INTR ((ushort)0x1000) -#define BD_ENET_TX_LAST ((ushort)0x0800) -#define BD_ENET_TX_TC ((ushort)0x0400) -#define BD_ENET_TX_DEF ((ushort)0x0200) -#define BD_ENET_TX_HB ((ushort)0x0100) -#define BD_ENET_TX_LC ((ushort)0x0080) -#define BD_ENET_TX_RL ((ushort)0x0040) -#define BD_ENET_TX_RCMASK ((ushort)0x003c) -#define BD_ENET_TX_UN ((ushort)0x0002) -#define BD_ENET_TX_CSL ((ushort)0x0001) -#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */ - -/* SCC as UART -*/ -typedef struct scc_uart { - sccp_t scc_genscc; - uint scc_res1; /* Reserved */ - uint scc_res2; /* Reserved */ - ushort scc_maxidl; /* Maximum idle chars */ - ushort scc_idlc; /* temp idle counter */ - ushort scc_brkcr; /* Break count register */ - ushort scc_parec; /* receive parity error counter */ - ushort scc_frmec; /* receive framing error counter */ - ushort scc_nosec; /* receive noise counter */ - ushort scc_brkec; /* receive break condition counter */ - ushort scc_brkln; /* last received break length */ - ushort scc_uaddr1; /* UART address character 1 */ - ushort scc_uaddr2; /* UART address character 2 */ - ushort scc_rtemp; /* Temp storage */ - ushort scc_toseq; /* Transmit out of sequence char */ - ushort scc_char1; /* control character 1 */ - ushort scc_char2; /* control character 2 */ - ushort scc_char3; /* control character 3 */ - ushort scc_char4; /* control character 4 */ - ushort scc_char5; /* control character 5 */ - ushort scc_char6; /* control character 6 */ - ushort scc_char7; /* control character 7 */ - ushort scc_char8; /* control character 8 */ - ushort scc_rccm; /* receive control character mask */ - ushort scc_rccr; /* receive control character register */ - ushort scc_rlbc; /* receive last break character */ -} scc_uart_t; - -/* SCC Event and Mask registers when it is used as a UART. -*/ -#define UART_SCCM_GLR ((ushort)0x1000) -#define UART_SCCM_GLT ((ushort)0x0800) -#define UART_SCCM_AB ((ushort)0x0200) -#define UART_SCCM_IDL ((ushort)0x0100) -#define UART_SCCM_GRA ((ushort)0x0080) -#define UART_SCCM_BRKE ((ushort)0x0040) -#define UART_SCCM_BRKS ((ushort)0x0020) -#define UART_SCCM_CCR ((ushort)0x0008) -#define UART_SCCM_BSY ((ushort)0x0004) -#define UART_SCCM_TX ((ushort)0x0002) -#define UART_SCCM_RX ((ushort)0x0001) - -/* The SCC PMSR when used as a UART. -*/ -#define SCU_PMSR_FLC ((ushort)0x8000) -#define SCU_PMSR_SL ((ushort)0x4000) -#define SCU_PMSR_CL ((ushort)0x3000) -#define SCU_PMSR_UM ((ushort)0x0c00) -#define SCU_PMSR_FRZ ((ushort)0x0200) -#define SCU_PMSR_RZS ((ushort)0x0100) -#define SCU_PMSR_SYN ((ushort)0x0080) -#define SCU_PMSR_DRT ((ushort)0x0040) -#define SCU_PMSR_PEN ((ushort)0x0010) -#define SCU_PMSR_RPM ((ushort)0x000c) -#define SCU_PMSR_REVP ((ushort)0x0008) -#define SCU_PMSR_TPM ((ushort)0x0003) -#define SCU_PMSR_TEVP ((ushort)0x0003) - -/* CPM Transparent mode SCC. - */ -typedef struct scc_trans { - sccp_t st_genscc; - uint st_cpres; /* Preset CRC */ - uint st_cmask; /* Constant mask for CRC */ -} scc_trans_t; - -#define BD_SCC_TX_LAST ((ushort)0x0800) - - - -/* CPM interrupts. There are nearly 32 interrupts generated by CPM - * channels or devices. All of these are presented to the PPC core - * as a single interrupt. The CPM interrupt handler dispatches its - * own handlers, in a similar fashion to the PPC core handler. We - * use the table as defined in the manuals (i.e. no special high - * priority and SCC1 == SCCa, etc...). - */ -/* #define CPMVEC_NR 32 */ -/* #define CPMVEC_PIO_PC15 ((ushort)0x1f) */ -/* #define CPMVEC_SCC1 ((ushort)0x1e) */ -/* #define CPMVEC_SCC2 ((ushort)0x1d) */ -/* #define CPMVEC_SCC3 ((ushort)0x1c) */ -/* #define CPMVEC_SCC4 ((ushort)0x1b) */ -/* #define CPMVEC_PIO_PC14 ((ushort)0x1a) */ -/* #define CPMVEC_TIMER1 ((ushort)0x19) */ -/* #define CPMVEC_PIO_PC13 ((ushort)0x18) */ -/* #define CPMVEC_PIO_PC12 ((ushort)0x17) */ -/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ -/* #define CPMVEC_IDMA1 ((ushort)0x15) */ -/* #define CPMVEC_IDMA2 ((ushort)0x14) */ -/* #define CPMVEC_TIMER2 ((ushort)0x12) */ -/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ -/* #define CPMVEC_I2C ((ushort)0x10) */ -/* #define CPMVEC_PIO_PC11 ((ushort)0x0f) */ -/* #define CPMVEC_PIO_PC10 ((ushort)0x0e) */ -/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ -/* #define CPMVEC_PIO_PC9 ((ushort)0x0b) */ -/* #define CPMVEC_PIO_PC8 ((ushort)0x0a) */ -/* #define CPMVEC_PIO_PC7 ((ushort)0x09) */ -/* #define CPMVEC_TIMER4 ((ushort)0x07) */ -/* #define CPMVEC_PIO_PC6 ((ushort)0x06) */ -/* #define CPMVEC_SPI ((ushort)0x05) */ -/* #define CPMVEC_SMC1 ((ushort)0x04) */ -/* #define CPMVEC_SMC2 ((ushort)0x03) */ -/* #define CPMVEC_PIO_PC5 ((ushort)0x02) */ -/* #define CPMVEC_PIO_PC4 ((ushort)0x01) */ -/* #define CPMVEC_ERROR ((ushort)0x00) */ - -extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id); - -/* CPM interrupt configuration vector. -*/ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_IEN ((uint)0x00000080) /* Int. enable */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ -#endif /* __CPM_360__ */ diff --git a/include/asm-m68knommu/cputime.h b/include/asm-m68knommu/cputime.h deleted file mode 100644 index a0c4a660878d..000000000000 --- a/include/asm-m68knommu/cputime.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __M68KNOMMU_CPUTIME_H -#define __M68KNOMMU_CPUTIME_H - -#include - -#endif /* __M68KNOMMU_CPUTIME_H */ diff --git a/include/asm-m68knommu/current.h b/include/asm-m68knommu/current.h deleted file mode 100644 index 53ee0f9f7cef..000000000000 --- a/include/asm-m68knommu/current.h +++ /dev/null @@ -1,24 +0,0 @@ -#ifndef _M68KNOMMU_CURRENT_H -#define _M68KNOMMU_CURRENT_H -/* - * current.h - * (C) Copyright 2000, Lineo, David McCullough - * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) - * - * rather than dedicate a register (as the m68k source does), we - * just keep a global, we should probably just change it all to be - * current and lose _current_task. - */ - -#include - -struct task_struct; - -static inline struct task_struct *get_current(void) -{ - return(current_thread_info()->task); -} - -#define current get_current() - -#endif /* _M68KNOMMU_CURRENT_H */ diff --git a/include/asm-m68knommu/dbg.h b/include/asm-m68knommu/dbg.h deleted file mode 100644 index 27af3270f671..000000000000 --- a/include/asm-m68knommu/dbg.h +++ /dev/null @@ -1,6 +0,0 @@ -#define DEBUG 1 -#ifdef CONFIG_COLDFIRE -#define BREAK asm volatile ("halt") -#else -#define BREAK *(volatile unsigned char *)0xdeadbee0 = 0 -#endif diff --git a/include/asm-m68knommu/delay.h b/include/asm-m68knommu/delay.h deleted file mode 100644 index 55cbd6294ab6..000000000000 --- a/include/asm-m68knommu/delay.h +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef _M68KNOMMU_DELAY_H -#define _M68KNOMMU_DELAY_H - -/* - * Copyright (C) 1994 Hamish Macdonald - * Copyright (C) 2004 Greg Ungerer - */ - -#include - -static inline void __delay(unsigned long loops) -{ -#if defined(CONFIG_COLDFIRE) - /* The coldfire runs this loop at significantly different speeds - * depending upon long word alignment or not. We'll pad it to - * long word alignment which is the faster version. - * The 0x4a8e is of course a 'tstl %fp' instruction. This is better - * than using a NOP (0x4e71) instruction because it executes in one - * cycle not three and doesn't allow for an arbitary delay waiting - * for bus cycles to finish. Also fp/a6 isn't likely to cause a - * stall waiting for the register to become valid if such is added - * to the coldfire at some stage. - */ - __asm__ __volatile__ ( ".balignw 4, 0x4a8e\n\t" - "1: subql #1, %0\n\t" - "jcc 1b" - : "=d" (loops) : "0" (loops)); -#else - __asm__ __volatile__ ( "1: subql #1, %0\n\t" - "jcc 1b" - : "=d" (loops) : "0" (loops)); -#endif -} - -/* - * Ideally we use a 32*32->64 multiply to calculate the number of - * loop iterations, but the older standard 68k and ColdFire do not - * have this instruction. So for them we have a clsoe approximation - * loop using 32*32->32 multiplies only. This calculation based on - * the ARM version of delay. - * - * We want to implement: - * - * loops = (usecs * 0x10c6 * HZ * loops_per_jiffy) / 2^32 - */ - -#define HZSCALE (268435456 / (1000000/HZ)) - -extern unsigned long loops_per_jiffy; - -static inline void _udelay(unsigned long usecs) -{ -#if defined(CONFIG_M68328) || defined(CONFIG_M68EZ328) || \ - defined(CONFIG_M68VZ328) || defined(CONFIG_M68360) || \ - defined(CONFIG_COLDFIRE) - __delay((((usecs * HZSCALE) >> 11) * (loops_per_jiffy >> 11)) >> 6); -#else - unsigned long tmp; - - usecs *= 4295; /* 2**32 / 1000000 */ - __asm__ ("mulul %2,%0:%1" - : "=d" (usecs), "=d" (tmp) - : "d" (usecs), "1" (loops_per_jiffy*HZ)); - __delay(usecs); -#endif -} - -/* - * Moved the udelay() function into library code, no longer inlined. - * I had to change the algorithm because we are overflowing now on - * the faster ColdFire parts. The code is a little bigger, so it makes - * sense to library it. - */ -extern void udelay(unsigned long usecs); - -#endif /* defined(_M68KNOMMU_DELAY_H) */ diff --git a/include/asm-m68knommu/device.h b/include/asm-m68knommu/device.h deleted file mode 100644 index d8f9872b0e2d..000000000000 --- a/include/asm-m68knommu/device.h +++ /dev/null @@ -1,7 +0,0 @@ -/* - * Arch specific extensions to struct device - * - * This file is released under the GPLv2 - */ -#include - diff --git a/include/asm-m68knommu/div64.h b/include/asm-m68knommu/div64.h deleted file mode 100644 index 6cd978cefb28..000000000000 --- a/include/asm-m68knommu/div64.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/dma-mapping.h b/include/asm-m68knommu/dma-mapping.h deleted file mode 100644 index 6aeab18e58bd..000000000000 --- a/include/asm-m68knommu/dma-mapping.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifndef _M68KNOMMU_DMA_MAPPING_H -#define _M68KNOMMU_DMA_MAPPING_H - -#ifdef CONFIG_PCI -#include -#else -#include -#endif - -#endif /* _M68KNOMMU_DMA_MAPPING_H */ diff --git a/include/asm-m68knommu/dma.h b/include/asm-m68knommu/dma.h deleted file mode 100644 index 939a02056217..000000000000 --- a/include/asm-m68knommu/dma.h +++ /dev/null @@ -1,494 +0,0 @@ -#ifndef _M68K_DMA_H -#define _M68K_DMA_H 1 - -//#define DMA_DEBUG 1 - - -#ifdef CONFIG_COLDFIRE -/* - * ColdFire DMA Model: - * ColdFire DMA supports two forms of DMA: Single and Dual address. Single - * address mode emits a source address, and expects that the device will either - * pick up the data (DMA READ) or source data (DMA WRITE). This implies that - * the device will place data on the correct byte(s) of the data bus, as the - * memory transactions are always 32 bits. This implies that only 32 bit - * devices will find single mode transfers useful. Dual address DMA mode - * performs two cycles: source read and destination write. ColdFire will - * align the data so that the device will always get the correct bytes, thus - * is useful for 8 and 16 bit devices. This is the mode that is supported - * below. - * - * AUG/22/2000 : added support for 32-bit Dual-Address-Mode (K) 2000 - * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) - * - * AUG/25/2000 : addad support for 8, 16 and 32-bit Single-Address-Mode (K)2000 - * Oliver Kamphenkel (O.Kamphenkel@tu-bs.de) - * - * APR/18/2002 : added proper support for MCF5272 DMA controller. - * Arthur Shipkowski (art@videon-central.com) - */ - -#include -#include -#include - -/* - * Set number of channels of DMA on ColdFire for different implementations. - */ -#if defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) || \ - defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -#define MAX_M68K_DMA_CHANNELS 4 -#elif defined(CONFIG_M5272) -#define MAX_M68K_DMA_CHANNELS 1 -#elif defined(CONFIG_M532x) -#define MAX_M68K_DMA_CHANNELS 0 -#else -#define MAX_M68K_DMA_CHANNELS 2 -#endif - -extern unsigned int dma_base_addr[MAX_M68K_DMA_CHANNELS]; -extern unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS]; - -#if !defined(CONFIG_M5272) -#define DMA_MODE_WRITE_BIT 0x01 /* Memory/IO to IO/Memory select */ -#define DMA_MODE_WORD_BIT 0x02 /* 8 or 16 bit transfers */ -#define DMA_MODE_LONG_BIT 0x04 /* or 32 bit transfers */ -#define DMA_MODE_SINGLE_BIT 0x08 /* single-address-mode */ - -/* I/O to memory, 8 bits, mode */ -#define DMA_MODE_READ 0 -/* memory to I/O, 8 bits, mode */ -#define DMA_MODE_WRITE 1 -/* I/O to memory, 16 bits, mode */ -#define DMA_MODE_READ_WORD 2 -/* memory to I/O, 16 bits, mode */ -#define DMA_MODE_WRITE_WORD 3 -/* I/O to memory, 32 bits, mode */ -#define DMA_MODE_READ_LONG 4 -/* memory to I/O, 32 bits, mode */ -#define DMA_MODE_WRITE_LONG 5 -/* I/O to memory, 8 bits, single-address-mode */ -#define DMA_MODE_READ_SINGLE 8 -/* memory to I/O, 8 bits, single-address-mode */ -#define DMA_MODE_WRITE_SINGLE 9 -/* I/O to memory, 16 bits, single-address-mode */ -#define DMA_MODE_READ_WORD_SINGLE 10 -/* memory to I/O, 16 bits, single-address-mode */ -#define DMA_MODE_WRITE_WORD_SINGLE 11 -/* I/O to memory, 32 bits, single-address-mode */ -#define DMA_MODE_READ_LONG_SINGLE 12 -/* memory to I/O, 32 bits, single-address-mode */ -#define DMA_MODE_WRITE_LONG_SINGLE 13 - -#else /* CONFIG_M5272 is defined */ - -/* Source static-address mode */ -#define DMA_MODE_SRC_SA_BIT 0x01 -/* Two bits to select between all four modes */ -#define DMA_MODE_SSIZE_MASK 0x06 -/* Offset to shift bits in */ -#define DMA_MODE_SSIZE_OFF 0x01 -/* Destination static-address mode */ -#define DMA_MODE_DES_SA_BIT 0x10 -/* Two bits to select between all four modes */ -#define DMA_MODE_DSIZE_MASK 0x60 -/* Offset to shift bits in */ -#define DMA_MODE_DSIZE_OFF 0x05 -/* Size modifiers */ -#define DMA_MODE_SIZE_LONG 0x00 -#define DMA_MODE_SIZE_BYTE 0x01 -#define DMA_MODE_SIZE_WORD 0x02 -#define DMA_MODE_SIZE_LINE 0x03 - -/* - * Aliases to help speed quick ports; these may be suboptimal, however. They - * do not include the SINGLE mode modifiers since the MCF5272 does not have a - * mode where the device is in control of its addressing. - */ - -/* I/O to memory, 8 bits, mode */ -#define DMA_MODE_READ ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) -/* memory to I/O, 8 bits, mode */ -#define DMA_MODE_WRITE ((DMA_MODE_SIZE_BYTE << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_BYTE << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) -/* I/O to memory, 16 bits, mode */ -#define DMA_MODE_READ_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) -/* memory to I/O, 16 bits, mode */ -#define DMA_MODE_WRITE_WORD ((DMA_MODE_SIZE_WORD << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_WORD << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) -/* I/O to memory, 32 bits, mode */ -#define DMA_MODE_READ_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_SRC_SA_BIT) -/* memory to I/O, 32 bits, mode */ -#define DMA_MODE_WRITE_LONG ((DMA_MODE_SIZE_LONG << DMA_MODE_DSIZE_OFF) | (DMA_MODE_SIZE_LONG << DMA_MODE_SSIZE_OFF) | DMA_DES_SA_BIT) - -#endif /* !defined(CONFIG_M5272) */ - -#if !defined(CONFIG_M5272) -/* enable/disable a specific DMA channel */ -static __inline__ void enable_dma(unsigned int dmanr) -{ - volatile unsigned short *dmawp; - -#ifdef DMA_DEBUG - printk("enable_dma(dmanr=%d)\n", dmanr); -#endif - - dmawp = (unsigned short *) dma_base_addr[dmanr]; - dmawp[MCFDMA_DCR] |= MCFDMA_DCR_EEXT; -} - -static __inline__ void disable_dma(unsigned int dmanr) -{ - volatile unsigned short *dmawp; - volatile unsigned char *dmapb; - -#ifdef DMA_DEBUG - printk("disable_dma(dmanr=%d)\n", dmanr); -#endif - - dmawp = (unsigned short *) dma_base_addr[dmanr]; - dmapb = (unsigned char *) dma_base_addr[dmanr]; - - /* Turn off external requests, and stop any DMA in progress */ - dmawp[MCFDMA_DCR] &= ~MCFDMA_DCR_EEXT; - dmapb[MCFDMA_DSR] = MCFDMA_DSR_DONE; -} - -/* - * Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * Use this once to initialize the FF to a known state. - * After that, keep track of it. :-) - * --- In order to do that, the DMA routines below should --- - * --- only be used while interrupts are disabled! --- - * - * This is a NOP for ColdFire. Provide a stub for compatibility. - */ -static __inline__ void clear_dma_ff(unsigned int dmanr) -{ -} - -/* set mode (above) for a specific DMA channel */ -static __inline__ void set_dma_mode(unsigned int dmanr, char mode) -{ - - volatile unsigned char *dmabp; - volatile unsigned short *dmawp; - -#ifdef DMA_DEBUG - printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); -#endif - - dmabp = (unsigned char *) dma_base_addr[dmanr]; - dmawp = (unsigned short *) dma_base_addr[dmanr]; - - // Clear config errors - dmabp[MCFDMA_DSR] = MCFDMA_DSR_DONE; - - // Set command register - dmawp[MCFDMA_DCR] = - MCFDMA_DCR_INT | // Enable completion irq - MCFDMA_DCR_CS | // Force one xfer per request - MCFDMA_DCR_AA | // Enable auto alignment - // single-address-mode - ((mode & DMA_MODE_SINGLE_BIT) ? MCFDMA_DCR_SAA : 0) | - // sets s_rw (-> r/w) high if Memory to I/0 - ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_S_RW : 0) | - // Memory to I/O or I/O to Memory - ((mode & DMA_MODE_WRITE_BIT) ? MCFDMA_DCR_SINC : MCFDMA_DCR_DINC) | - // 32 bit, 16 bit or 8 bit transfers - ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_SSIZE_WORD : - ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_SSIZE_LONG : - MCFDMA_DCR_SSIZE_BYTE)) | - ((mode & DMA_MODE_WORD_BIT) ? MCFDMA_DCR_DSIZE_WORD : - ((mode & DMA_MODE_LONG_BIT) ? MCFDMA_DCR_DSIZE_LONG : - MCFDMA_DCR_DSIZE_BYTE)); - -#ifdef DEBUG_DMA - printk("%s(%d): dmanr=%d DSR[%x]=%x DCR[%x]=%x\n", __FILE__, __LINE__, - dmanr, (int) &dmabp[MCFDMA_DSR], dmabp[MCFDMA_DSR], - (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR]); -#endif -} - -/* Set transfer address for specific DMA channel */ -static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) -{ - volatile unsigned short *dmawp; - volatile unsigned int *dmalp; - -#ifdef DMA_DEBUG - printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); -#endif - - dmawp = (unsigned short *) dma_base_addr[dmanr]; - dmalp = (unsigned int *) dma_base_addr[dmanr]; - - // Determine which address registers are used for memory/device accesses - if (dmawp[MCFDMA_DCR] & MCFDMA_DCR_SINC) { - // Source incrementing, must be memory - dmalp[MCFDMA_SAR] = a; - // Set dest address, must be device - dmalp[MCFDMA_DAR] = dma_device_address[dmanr]; - } else { - // Destination incrementing, must be memory - dmalp[MCFDMA_DAR] = a; - // Set source address, must be device - dmalp[MCFDMA_SAR] = dma_device_address[dmanr]; - } - -#ifdef DEBUG_DMA - printk("%s(%d): dmanr=%d DCR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", - __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DCR], dmawp[MCFDMA_DCR], - (int) &dmalp[MCFDMA_SAR], dmalp[MCFDMA_SAR], - (int) &dmalp[MCFDMA_DAR], dmalp[MCFDMA_DAR]); -#endif -} - -/* - * Specific for Coldfire - sets device address. - * Should be called after the mode set call, and before set DMA address. - */ -static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) -{ -#ifdef DMA_DEBUG - printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); -#endif - - dma_device_address[dmanr] = a; -} - -/* - * NOTE 2: "count" represents _bytes_. - */ -static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) -{ - volatile unsigned short *dmawp; - -#ifdef DMA_DEBUG - printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); -#endif - - dmawp = (unsigned short *) dma_base_addr[dmanr]; - dmawp[MCFDMA_BCR] = (unsigned short)count; -} - -/* - * Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * Otherwise, it returns the number of _bytes_ left to transfer. - */ -static __inline__ int get_dma_residue(unsigned int dmanr) -{ - volatile unsigned short *dmawp; - unsigned short count; - -#ifdef DMA_DEBUG - printk("get_dma_residue(dmanr=%d)\n", dmanr); -#endif - - dmawp = (unsigned short *) dma_base_addr[dmanr]; - count = dmawp[MCFDMA_BCR]; - return((int) count); -} -#else /* CONFIG_M5272 is defined */ - -/* - * The MCF5272 DMA controller is very different than the controller defined above - * in terms of register mapping. For instance, with the exception of the 16-bit - * interrupt register (IRQ#85, for reference), all of the registers are 32-bit. - * - * The big difference, however, is the lack of device-requested DMA. All modes - * are dual address transfer, and there is no 'device' setup or direction bit. - * You can DMA between a device and memory, between memory and memory, or even between - * two devices directly, with any combination of incrementing and non-incrementing - * addresses you choose. This puts a crimp in distinguishing between the 'device - * address' set up by set_dma_device_addr. - * - * Therefore, there are two options. One is to use set_dma_addr and set_dma_device_addr, - * which will act exactly as above in -- it will look to see if the source is set to - * autoincrement, and if so it will make the source use the set_dma_addr value and the - * destination the set_dma_device_addr value. Otherwise the source will be set to the - * set_dma_device_addr value and the destination will get the set_dma_addr value. - * - * The other is to use the provided set_dma_src_addr and set_dma_dest_addr functions - * and make it explicit. Depending on what you're doing, one of these two should work - * for you, but don't mix them in the same transfer setup. - */ - -/* enable/disable a specific DMA channel */ -static __inline__ void enable_dma(unsigned int dmanr) -{ - volatile unsigned int *dmalp; - -#ifdef DMA_DEBUG - printk("enable_dma(dmanr=%d)\n", dmanr); -#endif - - dmalp = (unsigned int *) dma_base_addr[dmanr]; - dmalp[MCFDMA_DMR] |= MCFDMA_DMR_EN; -} - -static __inline__ void disable_dma(unsigned int dmanr) -{ - volatile unsigned int *dmalp; - -#ifdef DMA_DEBUG - printk("disable_dma(dmanr=%d)\n", dmanr); -#endif - - dmalp = (unsigned int *) dma_base_addr[dmanr]; - - /* Turn off external requests, and stop any DMA in progress */ - dmalp[MCFDMA_DMR] &= ~MCFDMA_DMR_EN; - dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; -} - -/* - * Clear the 'DMA Pointer Flip Flop'. - * Write 0 for LSB/MSB, 1 for MSB/LSB access. - * Use this once to initialize the FF to a known state. - * After that, keep track of it. :-) - * --- In order to do that, the DMA routines below should --- - * --- only be used while interrupts are disabled! --- - * - * This is a NOP for ColdFire. Provide a stub for compatibility. - */ -static __inline__ void clear_dma_ff(unsigned int dmanr) -{ -} - -/* set mode (above) for a specific DMA channel */ -static __inline__ void set_dma_mode(unsigned int dmanr, char mode) -{ - - volatile unsigned int *dmalp; - volatile unsigned short *dmawp; - -#ifdef DMA_DEBUG - printk("set_dma_mode(dmanr=%d,mode=%d)\n", dmanr, mode); -#endif - dmalp = (unsigned int *) dma_base_addr[dmanr]; - dmawp = (unsigned short *) dma_base_addr[dmanr]; - - // Clear config errors - dmalp[MCFDMA_DMR] |= MCFDMA_DMR_RESET; - - // Set command register - dmalp[MCFDMA_DMR] = - MCFDMA_DMR_RQM_DUAL | // Mandatory Request Mode setting - MCFDMA_DMR_DSTT_SD | // Set up addressing types; set to supervisor-data. - MCFDMA_DMR_SRCT_SD | // Set up addressing types; set to supervisor-data. - // source static-address-mode - ((mode & DMA_MODE_SRC_SA_BIT) ? MCFDMA_DMR_SRCM_SA : MCFDMA_DMR_SRCM_IA) | - // dest static-address-mode - ((mode & DMA_MODE_DES_SA_BIT) ? MCFDMA_DMR_DSTM_SA : MCFDMA_DMR_DSTM_IA) | - // burst, 32 bit, 16 bit or 8 bit transfers are separately configurable on the MCF5272 - (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_DSTS_OFF) | - (((mode & DMA_MODE_SSIZE_MASK) >> DMA_MODE_SSIZE_OFF) << MCFDMA_DMR_SRCS_OFF); - - dmawp[MCFDMA_DIR] |= MCFDMA_DIR_ASCEN; /* Enable completion interrupts */ - -#ifdef DEBUG_DMA - printk("%s(%d): dmanr=%d DMR[%x]=%x DIR[%x]=%x\n", __FILE__, __LINE__, - dmanr, (int) &dmalp[MCFDMA_DMR], dmabp[MCFDMA_DMR], - (int) &dmawp[MCFDMA_DIR], dmawp[MCFDMA_DIR]); -#endif -} - -/* Set transfer address for specific DMA channel */ -static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) -{ - volatile unsigned int *dmalp; - -#ifdef DMA_DEBUG - printk("set_dma_addr(dmanr=%d,a=%x)\n", dmanr, a); -#endif - - dmalp = (unsigned int *) dma_base_addr[dmanr]; - - // Determine which address registers are used for memory/device accesses - if (dmalp[MCFDMA_DMR] & MCFDMA_DMR_SRCM) { - // Source incrementing, must be memory - dmalp[MCFDMA_DSAR] = a; - // Set dest address, must be device - dmalp[MCFDMA_DDAR] = dma_device_address[dmanr]; - } else { - // Destination incrementing, must be memory - dmalp[MCFDMA_DDAR] = a; - // Set source address, must be device - dmalp[MCFDMA_DSAR] = dma_device_address[dmanr]; - } - -#ifdef DEBUG_DMA - printk("%s(%d): dmanr=%d DMR[%x]=%x SAR[%x]=%08x DAR[%x]=%08x\n", - __FILE__, __LINE__, dmanr, (int) &dmawp[MCFDMA_DMR], dmawp[MCFDMA_DMR], - (int) &dmalp[MCFDMA_DSAR], dmalp[MCFDMA_DSAR], - (int) &dmalp[MCFDMA_DDAR], dmalp[MCFDMA_DDAR]); -#endif -} - -/* - * Specific for Coldfire - sets device address. - * Should be called after the mode set call, and before set DMA address. - */ -static __inline__ void set_dma_device_addr(unsigned int dmanr, unsigned int a) -{ -#ifdef DMA_DEBUG - printk("set_dma_device_addr(dmanr=%d,a=%x)\n", dmanr, a); -#endif - - dma_device_address[dmanr] = a; -} - -/* - * NOTE 2: "count" represents _bytes_. - * - * NOTE 3: While a 32-bit register, "count" is only a maximum 24-bit value. - */ -static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) -{ - volatile unsigned int *dmalp; - -#ifdef DMA_DEBUG - printk("set_dma_count(dmanr=%d,count=%d)\n", dmanr, count); -#endif - - dmalp = (unsigned int *) dma_base_addr[dmanr]; - dmalp[MCFDMA_DBCR] = count; -} - -/* - * Get DMA residue count. After a DMA transfer, this - * should return zero. Reading this while a DMA transfer is - * still in progress will return unpredictable results. - * Otherwise, it returns the number of _bytes_ left to transfer. - */ -static __inline__ int get_dma_residue(unsigned int dmanr) -{ - volatile unsigned int *dmalp; - unsigned int count; - -#ifdef DMA_DEBUG - printk("get_dma_residue(dmanr=%d)\n", dmanr); -#endif - - dmalp = (unsigned int *) dma_base_addr[dmanr]; - count = dmalp[MCFDMA_DBCR]; - return(count); -} - -#endif /* !defined(CONFIG_M5272) */ -#endif /* CONFIG_COLDFIRE */ - -#define MAX_DMA_CHANNELS 8 - -/* Don't define MAX_DMA_ADDRESS; it's useless on the m68k/coldfire and any - occurrence should be flagged as an error. */ -/* under 2.4 it is actually needed by the new bootmem allocator */ -#define MAX_DMA_ADDRESS PAGE_OFFSET - -/* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char *device_id); /* reserve a DMA channel */ -extern void free_dma(unsigned int dmanr); /* release it again */ - -#endif /* _M68K_DMA_H */ diff --git a/include/asm-m68knommu/elf.h b/include/asm-m68knommu/elf.h deleted file mode 100644 index 27f0ec70fba8..000000000000 --- a/include/asm-m68knommu/elf.h +++ /dev/null @@ -1,110 +0,0 @@ -#ifndef __ASMm68k_ELF_H -#define __ASMm68k_ELF_H - -/* - * ELF register definitions.. - */ - -#include -#include - -/* - * 68k ELF relocation types - */ -#define R_68K_NONE 0 -#define R_68K_32 1 -#define R_68K_16 2 -#define R_68K_8 3 -#define R_68K_PC32 4 -#define R_68K_PC16 5 -#define R_68K_PC8 6 -#define R_68K_GOT32 7 -#define R_68K_GOT16 8 -#define R_68K_GOT8 9 -#define R_68K_GOT32O 10 -#define R_68K_GOT16O 11 -#define R_68K_GOT8O 12 -#define R_68K_PLT32 13 -#define R_68K_PLT16 14 -#define R_68K_PLT8 15 -#define R_68K_PLT32O 16 -#define R_68K_PLT16O 17 -#define R_68K_PLT8O 18 -#define R_68K_COPY 19 -#define R_68K_GLOB_DAT 20 -#define R_68K_JMP_SLOT 21 -#define R_68K_RELATIVE 22 - -typedef unsigned long elf_greg_t; - -#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t)) -typedef elf_greg_t elf_gregset_t[ELF_NGREG]; - -typedef struct user_m68kfp_struct elf_fpregset_t; - -/* - * This is used to ensure we don't load something for the wrong architecture. - */ -#define elf_check_arch(x) ((x)->e_machine == EM_68K) - -/* - * These are used to set parameters in the core dumps. - */ -#define ELF_CLASS ELFCLASS32 -#define ELF_DATA ELFDATA2MSB -#define ELF_ARCH EM_68K - -/* For SVR4/m68k the function pointer to be registered with `atexit' is - passed in %a1. Although my copy of the ABI has no such statement, it - is actually used on ASV. */ -#define ELF_PLAT_INIT(_r, load_addr) _r->a1 = 0 - -#define USE_ELF_CORE_DUMP -#define ELF_EXEC_PAGESIZE 4096 - -/* This is the location that an ET_DYN program is loaded if exec'ed. Typical - use of this is to invoke "./ld.so someprog" to test out a new version of - the loader. We need to make sure that it is out of the way of the program - that it will "exec", and that there is sufficient room for the brk. */ - -#define ELF_ET_DYN_BASE 0xD0000000UL - -#define ELF_CORE_COPY_REGS(pr_reg, regs) \ - /* Bleech. */ \ - pr_reg[0] = regs->d1; \ - pr_reg[1] = regs->d2; \ - pr_reg[2] = regs->d3; \ - pr_reg[3] = regs->d4; \ - pr_reg[4] = regs->d5; \ - pr_reg[7] = regs->a0; \ - pr_reg[8] = regs->a1; \ - pr_reg[14] = regs->d0; \ - pr_reg[15] = rdusp(); \ - pr_reg[16] = 0 /* regs->orig_d0 */; \ - pr_reg[17] = regs->sr; \ - pr_reg[18] = regs->pc; \ - /* pr_reg[19] = (regs->format << 12) | regs->vector; */ \ - { \ - struct switch_stack *sw = ((struct switch_stack *)regs) - 1; \ - pr_reg[5] = sw->d6; \ - pr_reg[6] = sw->d7; \ - pr_reg[10] = sw->a3; \ - pr_reg[11] = sw->a4; \ - pr_reg[12] = sw->a5; \ - pr_reg[13] = sw->a6; \ - } - -/* This yields a mask that user programs can use to figure out what - instruction set this cpu supports. */ - -#define ELF_HWCAP (0) - -/* This yields a string that ld.so will use to load implementation - specific libraries for optimization. This is more specific in - intent than poking at uname or /proc/cpuinfo. */ - -#define ELF_PLATFORM (NULL) - -#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX) - -#endif diff --git a/include/asm-m68knommu/elia.h b/include/asm-m68knommu/elia.h deleted file mode 100644 index e037d4e2de33..000000000000 --- a/include/asm-m68knommu/elia.h +++ /dev/null @@ -1,41 +0,0 @@ -/****************************************************************************/ - -/* - * elia.h -- Lineo (formerly Moreton Bay) eLIA platform support. - * - * (C) Copyright 1999-2000, Moreton Bay (www.moreton.com.au) - * (C) Copyright 1999-2000, Lineo (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef elia_h -#define elia_h -/****************************************************************************/ - -#include - -#ifdef CONFIG_eLIA - -/* - * The serial port DTR and DCD lines are also on the Parallel I/O - * as well, so define those too. - */ - -#define eLIA_DCD1 0x0001 -#define eLIA_DCD0 0x0002 -#define eLIA_DTR1 0x0004 -#define eLIA_DTR0 0x0008 - -#define eLIA_PCIRESET 0x0020 - -/* - * Kernel macros to set and unset the LEDs. - */ -#ifndef __ASSEMBLY__ -extern unsigned short ppdata; -#endif /* __ASSEMBLY__ */ - -#endif /* CONFIG_eLIA */ - -/****************************************************************************/ -#endif /* elia_h */ diff --git a/include/asm-m68knommu/emergency-restart.h b/include/asm-m68knommu/emergency-restart.h deleted file mode 100644 index 108d8c48e42e..000000000000 --- a/include/asm-m68knommu/emergency-restart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_EMERGENCY_RESTART_H -#define _ASM_EMERGENCY_RESTART_H - -#include - -#endif /* _ASM_EMERGENCY_RESTART_H */ diff --git a/include/asm-m68knommu/entry.h b/include/asm-m68knommu/entry.h deleted file mode 100644 index c2553d26273d..000000000000 --- a/include/asm-m68knommu/entry.h +++ /dev/null @@ -1,182 +0,0 @@ -#ifndef __M68KNOMMU_ENTRY_H -#define __M68KNOMMU_ENTRY_H - -#include -#include - -/* - * Stack layout in 'ret_from_exception': - * - * This allows access to the syscall arguments in registers d1-d5 - * - * 0(sp) - d1 - * 4(sp) - d2 - * 8(sp) - d3 - * C(sp) - d4 - * 10(sp) - d5 - * 14(sp) - a0 - * 18(sp) - a1 - * 1C(sp) - a2 - * 20(sp) - d0 - * 24(sp) - orig_d0 - * 28(sp) - stack adjustment - * 2C(sp) - [ sr ] [ format & vector ] - * 2E(sp) - [ pc-hiword ] [ sr ] - * 30(sp) - [ pc-loword ] [ pc-hiword ] - * 32(sp) - [ format & vector ] [ pc-loword ] - * ^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^ - * M68K COLDFIRE - */ - -#define ALLOWINT 0xf8ff - -#ifdef __ASSEMBLY__ - -/* process bits for task_struct.flags */ -PF_TRACESYS_OFF = 3 -PF_TRACESYS_BIT = 5 -PF_PTRACED_OFF = 3 -PF_PTRACED_BIT = 4 -PF_DTRACE_OFF = 1 -PF_DTRACE_BIT = 5 - -LENOSYS = 38 - -#define SWITCH_STACK_SIZE (6*4+4) /* Includes return address */ - -/* - * This defines the normal kernel pt-regs layout. - * - * regs are a2-a6 and d6-d7 preserved by C code - * the kernel doesn't mess with usp unless it needs to - */ - -#ifdef CONFIG_COLDFIRE -/* - * This is made a little more tricky on the ColdFire. There is no - * separate kernel and user stack pointers. Need to artificially - * construct a usp in software... When doing this we need to disable - * interrupts, otherwise bad things could happen. - */ -.macro SAVE_ALL - move #0x2700,%sr /* disable intrs */ - btst #5,%sp@(2) /* from user? */ - bnes 6f /* no, skip */ - movel %sp,sw_usp /* save user sp */ - addql #8,sw_usp /* remove exception */ - movel sw_ksp,%sp /* kernel sp */ - subql #8,%sp /* room for exception */ - clrl %sp@- /* stkadj */ - movel %d0,%sp@- /* orig d0 */ - movel %d0,%sp@- /* d0 */ - lea %sp@(-32),%sp /* space for 8 regs */ - moveml %d1-%d5/%a0-%a2,%sp@ - movel sw_usp,%a0 /* get usp */ - movel %a0@-,%sp@(PT_PC) /* copy exception program counter */ - movel %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */ - bra 7f - 6: - clrl %sp@- /* stkadj */ - movel %d0,%sp@- /* orig d0 */ - movel %d0,%sp@- /* d0 */ - lea %sp@(-32),%sp /* space for 8 regs */ - moveml %d1-%d5/%a0-%a2,%sp@ - 7: -.endm - -.macro RESTORE_ALL - btst #5,%sp@(PT_SR) /* going user? */ - bnes 8f /* no, skip */ - move #0x2700,%sr /* disable intrs */ - movel sw_usp,%a0 /* get usp */ - movel %sp@(PT_PC),%a0@- /* copy exception program counter */ - movel %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */ - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - addql #8,%sp /* remove exception */ - movel %sp,sw_ksp /* save ksp */ - subql #8,sw_usp /* set exception */ - movel sw_usp,%sp /* restore usp */ - rte - 8: - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - rte -.endm - -/* - * Quick exception save, use current stack only. - */ -.macro SAVE_LOCAL - move #0x2700,%sr /* disable intrs */ - clrl %sp@- /* stkadj */ - movel %d0,%sp@- /* orig d0 */ - movel %d0,%sp@- /* d0 */ - lea %sp@(-32),%sp /* space for 8 regs */ - moveml %d1-%d5/%a0-%a2,%sp@ -.endm - -.macro RESTORE_LOCAL - moveml %sp@,%d1-%d5/%a0-%a2 - lea %sp@(32),%sp /* space for 8 regs */ - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - rte -.endm - -.macro SAVE_SWITCH_STACK - lea %sp@(-24),%sp /* 6 regs */ - moveml %a3-%a6/%d6-%d7,%sp@ -.endm - -.macro RESTORE_SWITCH_STACK - moveml %sp@,%a3-%a6/%d6-%d7 - lea %sp@(24),%sp /* 6 regs */ -.endm - -/* - * Software copy of the user and kernel stack pointers... Ugh... - * Need these to get around ColdFire not having separate kernel - * and user stack pointers. - */ -.globl sw_usp -.globl sw_ksp - -#else /* !CONFIG_COLDFIRE */ - -/* - * Standard 68k interrupt entry and exit macros. - */ -.macro SAVE_ALL - clrl %sp@- /* stkadj */ - movel %d0,%sp@- /* orig d0 */ - movel %d0,%sp@- /* d0 */ - moveml %d1-%d5/%a0-%a2,%sp@- -.endm - -.macro RESTORE_ALL - moveml %sp@+,%a0-%a2/%d1-%d5 - movel %sp@+,%d0 - addql #4,%sp /* orig d0 */ - addl %sp@+,%sp /* stkadj */ - rte -.endm - -.macro SAVE_SWITCH_STACK - moveml %a3-%a6/%d6-%d7,%sp@- -.endm - -.macro RESTORE_SWITCH_STACK - moveml %sp@+,%a3-%a6/%d6-%d7 -.endm - -#endif /* !CONFIG_COLDFIRE */ -#endif /* __ASSEMBLY__ */ -#endif /* __M68KNOMMU_ENTRY_H */ diff --git a/include/asm-m68knommu/errno.h b/include/asm-m68knommu/errno.h deleted file mode 100644 index 7e8c22b9a5e6..000000000000 --- a/include/asm-m68knommu/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/fb.h b/include/asm-m68knommu/fb.h deleted file mode 100644 index c7df38030992..000000000000 --- a/include/asm-m68knommu/fb.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_FB_H_ -#define _ASM_FB_H_ -#include - -#define fb_pgprotect(...) do {} while (0) - -static inline int fb_is_primary_device(struct fb_info *info) -{ - return 0; -} - -#endif /* _ASM_FB_H_ */ diff --git a/include/asm-m68knommu/fcntl.h b/include/asm-m68knommu/fcntl.h deleted file mode 100644 index f6a552cda4cd..000000000000 --- a/include/asm-m68knommu/fcntl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/flat.h b/include/asm-m68knommu/flat.h deleted file mode 100644 index 814b5174a8e0..000000000000 --- a/include/asm-m68knommu/flat.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * include/asm-m68knommu/flat.h -- uClinux flat-format executables - */ - -#ifndef __M68KNOMMU_FLAT_H__ -#define __M68KNOMMU_FLAT_H__ - -#define flat_stack_align(sp) /* nothing needed */ -#define flat_argvp_envp_on_stack() 1 -#define flat_old_ram_flag(flags) (flags) -#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) -#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp) -#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) -#define flat_get_relocate_addr(rel) (rel) -#define flat_set_persistent(relval, p) 0 - -#endif /* __M68KNOMMU_FLAT_H__ */ diff --git a/include/asm-m68knommu/fpu.h b/include/asm-m68knommu/fpu.h deleted file mode 100644 index b16b2e4fca2a..000000000000 --- a/include/asm-m68knommu/fpu.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __M68KNOMMU_FPU_H -#define __M68KNOMMU_FPU_H - - -/* - * MAX floating point unit state size (FSAVE/FRESTORE) - */ -#if defined(CONFIG_M68020) || defined(CONFIG_M68030) -#define FPSTATESIZE (216/sizeof(unsigned char)) -#elif defined(CONFIG_M68040) -#define FPSTATESIZE (96/sizeof(unsigned char)) -#elif defined(CONFIG_M68KFPU_EMU) -#define FPSTATESIZE (28/sizeof(unsigned char)) -#elif defined(CONFIG_M68060) -#define FPSTATESIZE (12/sizeof(unsigned char)) -#else -/* Assume no FP unit present then... */ -#define FPSTATESIZE (2) /* dummy size */ -#endif - -#endif /* __M68K_FPU_H */ diff --git a/include/asm-m68knommu/futex.h b/include/asm-m68knommu/futex.h deleted file mode 100644 index 6a332a9f099c..000000000000 --- a/include/asm-m68knommu/futex.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_FUTEX_H -#define _ASM_FUTEX_H - -#include - -#endif diff --git a/include/asm-m68knommu/hardirq.h b/include/asm-m68knommu/hardirq.h deleted file mode 100644 index bfad28149a49..000000000000 --- a/include/asm-m68knommu/hardirq.h +++ /dev/null @@ -1,27 +0,0 @@ -#ifndef __M68K_HARDIRQ_H -#define __M68K_HARDIRQ_H - -#include -#include -#include - -typedef struct { - unsigned int __softirq_pending; -} ____cacheline_aligned irq_cpustat_t; - -#include /* Standard mappings for irq_cpustat_t above */ - -#define HARDIRQ_BITS 8 - -/* - * The hardirq mask has to be large enough to have - * space for potentially all IRQ sources in the system - * nesting on a single CPU: - */ -#if (1 << HARDIRQ_BITS) < NR_IRQS -# error HARDIRQ_BITS is too low! -#endif - -void ack_bad_irq(unsigned int irq); - -#endif /* __M68K_HARDIRQ_H */ diff --git a/include/asm-m68knommu/hw_irq.h b/include/asm-m68knommu/hw_irq.h deleted file mode 100644 index f3ec9e5ae049..000000000000 --- a/include/asm-m68knommu/hw_irq.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __M68KNOMMU_HW_IRQ_H__ -#define __M68KNOMMU_HW_IRQ_H__ - -#endif /* __M68KNOMMU_HW_IRQ_H__ */ diff --git a/include/asm-m68knommu/hwtest.h b/include/asm-m68knommu/hwtest.h deleted file mode 100644 index 700626a1b1bf..000000000000 --- a/include/asm-m68knommu/hwtest.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/io.h b/include/asm-m68knommu/io.h deleted file mode 100644 index 6adef1ee2082..000000000000 --- a/include/asm-m68knommu/io.h +++ /dev/null @@ -1,194 +0,0 @@ -#ifndef _M68KNOMMU_IO_H -#define _M68KNOMMU_IO_H - -#ifdef __KERNEL__ - - -/* - * These are for ISA/PCI shared memory _only_ and should never be used - * on any other type of memory, including Zorro memory. They are meant to - * access the bus in the bus byte order which is little-endian!. - * - * readX/writeX() are used to access memory mapped devices. On some - * architectures the memory mapped IO stuff needs to be accessed - * differently. On the m68k architecture, we just read/write the - * memory location directly. - */ -/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates - * two accesses to memory, which may be undesireable for some devices. - */ - -/* - * swap functions are sometimes needed to interface little-endian hardware - */ -static inline unsigned short _swapw(volatile unsigned short v) -{ - return ((v << 8) | (v >> 8)); -} - -static inline unsigned int _swapl(volatile unsigned long v) -{ - return ((v << 24) | ((v & 0xff00) << 8) | ((v & 0xff0000) >> 8) | (v >> 24)); -} - -#define readb(addr) \ - ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; }) -#define readw(addr) \ - ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; }) -#define readl(addr) \ - ({ unsigned int __v = (*(volatile unsigned int *) (addr)); __v; }) - -#define readb_relaxed(addr) readb(addr) -#define readw_relaxed(addr) readw(addr) -#define readl_relaxed(addr) readl(addr) - -#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b)) -#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b)) -#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b)) - -#define __raw_readb readb -#define __raw_readw readw -#define __raw_readl readl -#define __raw_writeb writeb -#define __raw_writew writew -#define __raw_writel writel - -static inline void io_outsb(unsigned int addr, void *buf, int len) -{ - volatile unsigned char *ap = (volatile unsigned char *) addr; - unsigned char *bp = (unsigned char *) buf; - while (len--) - *ap = *bp++; -} - -static inline void io_outsw(unsigned int addr, void *buf, int len) -{ - volatile unsigned short *ap = (volatile unsigned short *) addr; - unsigned short *bp = (unsigned short *) buf; - while (len--) - *ap = _swapw(*bp++); -} - -static inline void io_outsl(unsigned int addr, void *buf, int len) -{ - volatile unsigned int *ap = (volatile unsigned int *) addr; - unsigned int *bp = (unsigned int *) buf; - while (len--) - *ap = _swapl(*bp++); -} - -static inline void io_insb(unsigned int addr, void *buf, int len) -{ - volatile unsigned char *ap = (volatile unsigned char *) addr; - unsigned char *bp = (unsigned char *) buf; - while (len--) - *bp++ = *ap; -} - -static inline void io_insw(unsigned int addr, void *buf, int len) -{ - volatile unsigned short *ap = (volatile unsigned short *) addr; - unsigned short *bp = (unsigned short *) buf; - while (len--) - *bp++ = _swapw(*ap); -} - -static inline void io_insl(unsigned int addr, void *buf, int len) -{ - volatile unsigned int *ap = (volatile unsigned int *) addr; - unsigned int *bp = (unsigned int *) buf; - while (len--) - *bp++ = _swapl(*ap); -} - -#define mmiowb() - -/* - * make the short names macros so specific devices - * can override them as required - */ - -#define memset_io(a,b,c) memset((void *)(a),(b),(c)) -#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) -#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) - -#define inb(addr) readb(addr) -#define inw(addr) readw(addr) -#define inl(addr) readl(addr) -#define outb(x,addr) ((void) writeb(x,addr)) -#define outw(x,addr) ((void) writew(x,addr)) -#define outl(x,addr) ((void) writel(x,addr)) - -#define inb_p(addr) inb(addr) -#define inw_p(addr) inw(addr) -#define inl_p(addr) inl(addr) -#define outb_p(x,addr) outb(x,addr) -#define outw_p(x,addr) outw(x,addr) -#define outl_p(x,addr) outl(x,addr) - -#define outsb(a,b,l) io_outsb(a,b,l) -#define outsw(a,b,l) io_outsw(a,b,l) -#define outsl(a,b,l) io_outsl(a,b,l) - -#define insb(a,b,l) io_insb(a,b,l) -#define insw(a,b,l) io_insw(a,b,l) -#define insl(a,b,l) io_insl(a,b,l) - -#define IO_SPACE_LIMIT 0xffff - - -/* Values for nocacheflag and cmode */ -#define IOMAP_FULL_CACHING 0 -#define IOMAP_NOCACHE_SER 1 -#define IOMAP_NOCACHE_NONSER 2 -#define IOMAP_WRITETHROUGH 3 - -extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag); -extern void __iounmap(void *addr, unsigned long size); - -static inline void *ioremap(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_NOCACHE_SER); -} -static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_WRITETHROUGH); -} -static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size) -{ - return __ioremap(physaddr, size, IOMAP_FULL_CACHING); -} - -extern void iounmap(void *addr); - -/* Pages to physical address... */ -#define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT) -#define page_to_bus(page) ((page - mem_map) << PAGE_SHIFT) - -/* - * Macros used for converting between virtual and physical mappings. - */ -#define phys_to_virt(vaddr) ((void *) (vaddr)) -#define virt_to_phys(vaddr) ((unsigned long) (vaddr)) - -#define virt_to_bus virt_to_phys -#define bus_to_virt phys_to_virt - -/* - * Convert a physical pointer to a virtual kernel pointer for /dev/mem - * access - */ -#define xlate_dev_mem_ptr(p) __va(p) - -/* - * Convert a virtual cached pointer to an uncached pointer - */ -#define xlate_dev_kmem_ptr(p) p - -#endif /* __KERNEL__ */ - -#endif /* _M68KNOMMU_IO_H */ diff --git a/include/asm-m68knommu/ioctl.h b/include/asm-m68knommu/ioctl.h deleted file mode 100644 index b279fe06dfe5..000000000000 --- a/include/asm-m68knommu/ioctl.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/ioctls.h b/include/asm-m68knommu/ioctls.h deleted file mode 100644 index 0b1eb4d85059..000000000000 --- a/include/asm-m68knommu/ioctls.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/ipcbuf.h b/include/asm-m68knommu/ipcbuf.h deleted file mode 100644 index e4a7be6dd706..000000000000 --- a/include/asm-m68knommu/ipcbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/irq.h b/include/asm-m68knommu/irq.h deleted file mode 100644 index 9373c31ac87d..000000000000 --- a/include/asm-m68knommu/irq.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _M68KNOMMU_IRQ_H_ -#define _M68KNOMMU_IRQ_H_ - -#ifdef CONFIG_COLDFIRE -/* - * On the ColdFire we keep track of all vectors. That way drivers - * can register whatever vector number they wish, and we can deal - * with it. - */ -#define SYS_IRQS 256 -#define NR_IRQS SYS_IRQS - -#else - -/* - * # of m68k interrupts - */ -#define SYS_IRQS 8 -#define NR_IRQS (24 + SYS_IRQS) - -#endif /* CONFIG_COLDFIRE */ - - -#define irq_canonicalize(irq) (irq) - -#endif /* _M68KNOMMU_IRQ_H_ */ diff --git a/include/asm-m68knommu/irq_regs.h b/include/asm-m68knommu/irq_regs.h deleted file mode 100644 index 3dd9c0b70270..000000000000 --- a/include/asm-m68knommu/irq_regs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/kdebug.h b/include/asm-m68knommu/kdebug.h deleted file mode 100644 index 6ece1b037665..000000000000 --- a/include/asm-m68knommu/kdebug.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/kmap_types.h b/include/asm-m68knommu/kmap_types.h deleted file mode 100644 index bfb6707575d1..000000000000 --- a/include/asm-m68knommu/kmap_types.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __ASM_M68K_KMAP_TYPES_H -#define __ASM_M68K_KMAP_TYPES_H - -enum km_type { - KM_BOUNCE_READ, - KM_SKB_SUNRPC_DATA, - KM_SKB_DATA_SOFTIRQ, - KM_USER0, - KM_USER1, - KM_BIO_SRC_IRQ, - KM_BIO_DST_IRQ, - KM_PTE0, - KM_PTE1, - KM_IRQ0, - KM_IRQ1, - KM_SOFTIRQ0, - KM_SOFTIRQ1, - KM_TYPE_NR -}; - -#endif diff --git a/include/asm-m68knommu/linkage.h b/include/asm-m68knommu/linkage.h deleted file mode 100644 index c288a19ff489..000000000000 --- a/include/asm-m68knommu/linkage.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/local.h b/include/asm-m68knommu/local.h deleted file mode 100644 index 84a39c1b86f8..000000000000 --- a/include/asm-m68knommu/local.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __M68KNOMMU_LOCAL_H -#define __M68KNOMMU_LOCAL_H - -#include - -#endif /* __M68KNOMMU_LOCAL_H */ diff --git a/include/asm-m68knommu/m5206sim.h b/include/asm-m68knommu/m5206sim.h deleted file mode 100644 index 7e3594dea88b..000000000000 --- a/include/asm-m68knommu/m5206sim.h +++ /dev/null @@ -1,131 +0,0 @@ -/****************************************************************************/ - -/* - * m5206sim.h -- ColdFire 5206 System Integration Module support. - * - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef m5206sim_h -#define m5206sim_h -/****************************************************************************/ - - -/* - * Define the 5206 SIM register set addresses. - */ -#define MCFSIM_SIMR 0x03 /* SIM Config reg (r/w) */ -#define MCFSIM_ICR1 0x14 /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x15 /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x16 /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x17 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x18 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x19 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x1a /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x1b /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x1c /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x1d /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x1e /* Intr Ctrl reg 11 (r/w) */ -#define MCFSIM_ICR12 0x1f /* Intr Ctrl reg 12 (r/w) */ -#define MCFSIM_ICR13 0x20 /* Intr Ctrl reg 13 (r/w) */ -#ifdef CONFIG_M5206e -#define MCFSIM_ICR14 0x21 /* Intr Ctrl reg 14 (r/w) */ -#define MCFSIM_ICR15 0x22 /* Intr Ctrl reg 15 (r/w) */ -#endif - -#define MCFSIM_IMR 0x36 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_IPR 0x3a /* Interrupt Pend reg (r/w) */ - -#define MCFSIM_RSR 0x40 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x41 /* System Protection reg (r/w)*/ - -#define MCFSIM_SWIVR 0x42 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x43 /* SW Watchdog service (r/w) */ - -#define MCFSIM_DCRR 0x46 /* DRAM Refresh reg (r/w) */ -#define MCFSIM_DCTR 0x4a /* DRAM Timing reg (r/w) */ -#define MCFSIM_DAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCR1 0x63 /* DRAM 1 Control reg (r/w) */ - -#define MCFSIM_CSAR0 0x64 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x68 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x6e /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x70 /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x74 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x7a /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x7c /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x80 /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0x86 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0x88 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0x8c /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0x92 /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0x94 /* CS 4 Address reg (r/w) */ -#define MCFSIM_CSMR4 0x98 /* CS 4 Mask reg (r/w) */ -#define MCFSIM_CSCR4 0x9e /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xa0 /* CS 5 Address reg (r/w) */ -#define MCFSIM_CSMR5 0xa4 /* CS 5 Mask reg (r/w) */ -#define MCFSIM_CSCR5 0xaa /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xac /* CS 6 Address reg (r/w) */ -#define MCFSIM_CSMR6 0xb0 /* CS 6 Mask reg (r/w) */ -#define MCFSIM_CSCR6 0xb6 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xb8 /* CS 7 Address reg (r/w) */ -#define MCFSIM_CSMR7 0xbc /* CS 7 Mask reg (r/w) */ -#define MCFSIM_CSCR7 0xc2 /* CS 7 Control reg (r/w) */ -#define MCFSIM_DMCR 0xc6 /* Default control */ - -#ifdef CONFIG_M5206e -#define MCFSIM_PAR 0xca /* Pin Assignment reg (r/w) */ -#else -#define MCFSIM_PAR 0xcb /* Pin Assignment reg (r/w) */ -#endif - -#define MCFSIM_PADDR 0x1c5 /* Parallel Direction (r/w) */ -#define MCFSIM_PADAT 0x1c9 /* Parallel Port Value (r/w) */ - -/* - * Some symbol defines for the Parallel Port Pin Assignment Register - */ -#ifdef CONFIG_M5206e -#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */ - /* Clear to select T0 input */ -#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */ - /* Clear to select T0 output */ -#endif - -/* - * Some symbol defines for the Interrupt Control Register - */ -#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */ -#ifdef CONFIG_M5206e -#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */ -#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */ -#endif - -#if defined(CONFIG_M5206e) -#define MCFSIM_IMR_MASKALL 0xfffe /* All SIM intr sources */ -#endif - -/* - * Macro to get and set IMR register. It is 16 bits on the 5206. - */ -#define mcf_getimr() \ - *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IMR)) = (imr) - -#define mcf_getipr() \ - *((volatile unsigned short *) (MCF_MBAR + MCFSIM_IPR)) - -/****************************************************************************/ -#endif /* m5206sim_h */ diff --git a/include/asm-m68knommu/m520xsim.h b/include/asm-m68knommu/m520xsim.h deleted file mode 100644 index 49d016e6391a..000000000000 --- a/include/asm-m68knommu/m520xsim.h +++ /dev/null @@ -1,63 +0,0 @@ -/****************************************************************************/ - -/* - * m520xsim.h -- ColdFire 5207/5208 System Integration Module support. - * - * (C) Copyright 2005, Intec Automation (mike@steroidmicros.com) - */ - -/****************************************************************************/ -#ifndef m520xsim_h -#define m520xsim_h -/****************************************************************************/ - - -/* - * Define the 5282 SIM register set addresses. - */ -#define MCFICM_INTC0 0x48000 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -#define MCFINT_VECBASE 64 -#define MCFINT_UART0 26 /* Interrupt number for UART0 */ -#define MCFINT_UART1 27 /* Interrupt number for UART1 */ -#define MCFINT_UART2 28 /* Interrupt number for UART2 */ -#define MCFINT_QSPI 31 /* Interrupt number for QSPI */ -#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */ - -/* - * SDRAM configuration registers. - */ -#define MCFSIM_SDMR 0x000a8000 /* SDRAM Mode/Extended Mode Register */ -#define MCFSIM_SDCR 0x000a8004 /* SDRAM Control Register */ -#define MCFSIM_SDCFG1 0x000a8008 /* SDRAM Configuration Register 1 */ -#define MCFSIM_SDCFG2 0x000a800c /* SDRAM Configuration Register 2 */ -#define MCFSIM_SDCS0 0x000a8110 /* SDRAM Chip Select 0 Configuration */ -#define MCFSIM_SDCS1 0x000a8114 /* SDRAM Chip Select 1 Configuration */ - - -#define MCF_GPIO_PAR_UART (0xA4036) -#define MCF_GPIO_PAR_FECI2C (0xA4033) -#define MCF_GPIO_PAR_FEC (0xA4038) - -#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001) -#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002) - -#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040) -#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080) - -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) - -#define ICR_INTRCONF 0x05 -#define MCFPIT_IMR MCFINTC_IMRL -#define MCFPIT_IMR_IBIT (1 << MCFINT_PIT1) - -/****************************************************************************/ -#endif /* m520xsim_h */ diff --git a/include/asm-m68knommu/m523xsim.h b/include/asm-m68knommu/m523xsim.h deleted file mode 100644 index bf397313e93f..000000000000 --- a/include/asm-m68knommu/m523xsim.h +++ /dev/null @@ -1,45 +0,0 @@ -/****************************************************************************/ - -/* - * m523xsim.h -- ColdFire 523x System Integration Module support. - * - * (C) Copyright 2003-2005, Greg Ungerer - */ - -/****************************************************************************/ -#ifndef m523xsim_h -#define m523xsim_h -/****************************************************************************/ - - -/* - * Define the 523x SIM register set addresses. - */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -#define MCFINT_VECBASE 64 /* Vector base number */ -#define MCFINT_UART0 13 /* Interrupt number for UART0 */ -#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ -#define MCFINT_QSPI 18 /* Interrupt number for QSPI */ - -/* - * SDRAM configuration registers. - */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ - -/****************************************************************************/ -#endif /* m523xsim_h */ diff --git a/include/asm-m68knommu/m5249sim.h b/include/asm-m68knommu/m5249sim.h deleted file mode 100644 index 366eb8602d2f..000000000000 --- a/include/asm-m68knommu/m5249sim.h +++ /dev/null @@ -1,209 +0,0 @@ -/****************************************************************************/ - -/* - * m5249sim.h -- ColdFire 5249 System Integration Module support. - * - * (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com) - */ - -/****************************************************************************/ -#ifndef m5249sim_h -#define m5249sim_h -/****************************************************************************/ - -/* - * Define the 5249 SIM register set addresses. - */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ -#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ - -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ - -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - - -/* - * Some symbol defines for the above... - */ -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ -#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ -#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ -#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ -#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ - -/* - * General purpose IO registers (in MBAR2). - */ -#define MCFSIM2_GPIOREAD 0x0 /* GPIO read values */ -#define MCFSIM2_GPIOWRITE 0x4 /* GPIO write values */ -#define MCFSIM2_GPIOENABLE 0x8 /* GPIO enabled */ -#define MCFSIM2_GPIOFUNC 0xc /* GPIO function */ -#define MCFSIM2_GPIO1READ 0xb0 /* GPIO1 read values */ -#define MCFSIM2_GPIO1WRITE 0xb4 /* GPIO1 write values */ -#define MCFSIM2_GPIO1ENABLE 0xb8 /* GPIO1 enabled */ -#define MCFSIM2_GPIO1FUNC 0xbc /* GPIO1 function */ - -#define MCFSIM2_GPIOINTSTAT 0xc0 /* GPIO interrupt status */ -#define MCFSIM2_GPIOINTCLEAR 0xc0 /* GPIO interrupt clear */ -#define MCFSIM2_GPIOINTENABLE 0xc4 /* GPIO interrupt enable */ - -#define MCFSIM2_INTLEVEL1 0x140 /* Interrupt level reg 1 */ -#define MCFSIM2_INTLEVEL2 0x144 /* Interrupt level reg 2 */ -#define MCFSIM2_INTLEVEL3 0x148 /* Interrupt level reg 3 */ -#define MCFSIM2_INTLEVEL4 0x14c /* Interrupt level reg 4 */ -#define MCFSIM2_INTLEVEL5 0x150 /* Interrupt level reg 5 */ -#define MCFSIM2_INTLEVEL6 0x154 /* Interrupt level reg 6 */ -#define MCFSIM2_INTLEVEL7 0x158 /* Interrupt level reg 7 */ -#define MCFSIM2_INTLEVEL8 0x15c /* Interrupt level reg 8 */ - -#define MCFSIM2_DMAROUTE 0x188 /* DMA routing */ - -#define MCFSIM2_IDECONFIG1 0x18c /* IDEconfig1 */ -#define MCFSIM2_IDECONFIG2 0x190 /* IDEconfig2 */ - - -/* - * Macro to set IMR register. It is 32 bits on the 5249. - */ -#define MCFSIM_IMR_MASKALL 0x7fffe /* All SIM intr sources */ - -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - -/****************************************************************************/ - -#ifdef __ASSEMBLER__ - -/* - * The M5249C3 board needs a little help getting all its SIM devices - * initialized at kernel start time. dBUG doesn't set much up, so - * we need to do it manually. - */ -.macro m5249c3_setup - /* - * Set MBAR1 and MBAR2, just incase they are not set. - */ - movel #0x10000001,%a0 - movec %a0,%MBAR /* map MBAR region */ - subql #1,%a0 /* get MBAR address in a0 */ - - movel #0x80000001,%a1 - movec %a1,#3086 /* map MBAR2 region */ - subql #1,%a1 /* get MBAR2 address in a1 */ - - /* - * Move secondary interrupts to base at 128. - */ - moveb #0x80,%d0 - moveb %d0,0x16b(%a1) /* interrupt base register */ - - /* - * Work around broken CSMR0/DRAM vector problem. - */ - movel #0x001F0021,%d0 /* disable C/I bit */ - movel %d0,0x84(%a0) /* set CSMR0 */ - - /* - * Disable the PLL firstly. (Who knows what state it is - * in here!). - */ - movel 0x180(%a1),%d0 /* get current PLL value */ - andl #0xfffffffe,%d0 /* PLL bypass first */ - movel %d0,0x180(%a1) /* set PLL register */ - nop - -#if CONFIG_CLOCK_FREQ == 140000000 - /* - * Set initial clock frequency. This assumes M5249C3 board - * is fitted with 11.2896MHz crystal. It will program the - * PLL for 140MHz. Lets go fast :-) - */ - movel #0x125a40f0,%d0 /* set for 140MHz */ - movel %d0,0x180(%a1) /* set PLL register */ - orl #0x1,%d0 - movel %d0,0x180(%a1) /* set PLL register */ -#endif - - /* - * Setup CS1 for ethernet controller. - * (Setup as per M5249C3 doco). - */ - movel #0xe0000000,%d0 /* CS1 mapped at 0xe0000000 */ - movel %d0,0x8c(%a0) - movel #0x001f0021,%d0 /* CS1 size of 1Mb */ - movel %d0,0x90(%a0) - movew #0x0080,%d0 /* CS1 = 16bit port, AA */ - movew %d0,0x96(%a0) - - /* - * Setup CS2 for IDE interface. - */ - movel #0x50000000,%d0 /* CS2 mapped at 0x50000000 */ - movel %d0,0x98(%a0) - movel #0x001f0001,%d0 /* CS2 size of 1MB */ - movel %d0,0x9c(%a0) - movew #0x0080,%d0 /* CS2 = 16bit, TA */ - movew %d0,0xa2(%a0) - - movel #0x00107000,%d0 /* IDEconfig1 */ - movel %d0,0x18c(%a1) - movel #0x000c0400,%d0 /* IDEconfig2 */ - movel %d0,0x190(%a1) - - movel #0x00080000,%d0 /* GPIO19, IDE reset bit */ - orl %d0,0xc(%a1) /* function GPIO19 */ - orl %d0,0x8(%a1) /* enable GPIO19 as output */ - orl %d0,0x4(%a1) /* de-assert IDE reset */ -.endm - -#define PLATFORM_SETUP m5249c3_setup - -#endif /* __ASSEMBLER__ */ - -/****************************************************************************/ -#endif /* m5249sim_h */ diff --git a/include/asm-m68knommu/m5272sim.h b/include/asm-m68knommu/m5272sim.h deleted file mode 100644 index 6217edc21139..000000000000 --- a/include/asm-m68knommu/m5272sim.h +++ /dev/null @@ -1,78 +0,0 @@ -/****************************************************************************/ - -/* - * m5272sim.h -- ColdFire 5272 System Integration Module support. - * - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef m5272sim_h -#define m5272sim_h -/****************************************************************************/ - - -/* - * Define the 5272 SIM register set addresses. - */ -#define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ -#define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ -#define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ -#define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ -#define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ - -#define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ - -#define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ -#define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ -#define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ -#define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ - -#define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ -#define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ -#define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ -#define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ - -#define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ -#define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ -#define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ -#define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ -#define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ -#define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ -#define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ -#define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ -#define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ -#define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ -#define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ -#define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ -#define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ -#define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ -#define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ -#define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ - -#define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ -#define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ -#define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ -#define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ -#define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ -#define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ -#define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ - -#define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ -#define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ -#define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ -#define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ -#define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ -#define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ -#define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ -#define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ -#define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ - - -/****************************************************************************/ -#endif /* m5272sim_h */ diff --git a/include/asm-m68knommu/m527xsim.h b/include/asm-m68knommu/m527xsim.h deleted file mode 100644 index 1f63ab3fb3e6..000000000000 --- a/include/asm-m68knommu/m527xsim.h +++ /dev/null @@ -1,74 +0,0 @@ -/****************************************************************************/ - -/* - * m527xsim.h -- ColdFire 5270/5271 System Integration Module support. - * - * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com) - */ - -/****************************************************************************/ -#ifndef m527xsim_h -#define m527xsim_h -/****************************************************************************/ - - -/* - * Define the 5270/5271 SIM register set addresses. - */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -#define MCFINT_VECBASE 64 /* Vector base number */ -#define MCFINT_UART0 13 /* Interrupt number for UART0 */ -#define MCFINT_UART1 14 /* Interrupt number for UART1 */ -#define MCFINT_UART2 15 /* Interrupt number for UART2 */ -#define MCFINT_PIT1 36 /* Interrupt number for PIT1 */ - -/* - * SDRAM configuration registers. - */ -#ifdef CONFIG_M5271 -#define MCFSIM_DCR 0x40 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ -#endif -#ifdef CONFIG_M5275 -#define MCFSIM_DMR 0x40 /* SDRAM mode */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DCFG1 0x48 /* SDRAM configuration 1 */ -#define MCFSIM_DCFG2 0x4c /* SDRAM configuration 2 */ -#define MCFSIM_DBAR0 0x50 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x54 /* SDRAM address mask 0 */ -#define MCFSIM_DBAR1 0x58 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x5c /* SDRAM address mask 1 */ -#endif - -/* - * GPIO pins setups to enable the UARTs. - */ -#ifdef CONFIG_M5271 -#define MCF_GPIO_PAR_UART 0x100048 /* PAR UART address */ -#define UART0_ENABLE_MASK 0x000f -#define UART1_ENABLE_MASK 0x0ff0 -#define UART2_ENABLE_MASK 0x3000 -#endif -#ifdef CONFIG_M5275 -#define MCF_GPIO_PAR_UART 0x10007c /* PAR UART address */ -#define UART0_ENABLE_MASK 0x000f -#define UART1_ENABLE_MASK 0x00f0 -#define UART2_ENABLE_MASK 0x3f00 -#endif - -/****************************************************************************/ -#endif /* m527xsim_h */ diff --git a/include/asm-m68knommu/m528xsim.h b/include/asm-m68knommu/m528xsim.h deleted file mode 100644 index 28bf783a5d6d..000000000000 --- a/include/asm-m68knommu/m528xsim.h +++ /dev/null @@ -1,159 +0,0 @@ -/****************************************************************************/ - -/* - * m528xsim.h -- ColdFire 5280/5282 System Integration Module support. - * - * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) - */ - -/****************************************************************************/ -#ifndef m528xsim_h -#define m528xsim_h -/****************************************************************************/ - - -/* - * Define the 5280/5282 SIM register set addresses. - */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -#define MCFINT_VECBASE 64 /* Vector base number */ -#define MCFINT_UART0 13 /* Interrupt number for UART0 */ -#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ - -/* - * SDRAM configuration registers. - */ -#define MCFSIM_DCR 0x44 /* SDRAM control */ -#define MCFSIM_DACR0 0x48 /* SDRAM base address 0 */ -#define MCFSIM_DMR0 0x4c /* SDRAM address mask 0 */ -#define MCFSIM_DACR1 0x50 /* SDRAM base address 1 */ -#define MCFSIM_DMR1 0x54 /* SDRAM address mask 1 */ - -/* - * Derek Cheung - 6 Feb 2005 - * add I2C and QSPI register definition using Freescale's MCF5282 - */ -/* set Port AS pin for I2C or UART */ -#define MCF5282_GPIO_PASPAR (volatile u16 *) (MCF_IPSBAR + 0x00100056) - -/* Port UA Pin Assignment Register (8 Bit) */ -#define MCF5282_GPIO_PUAPAR 0x10005C - -/* Interrupt Mask Register Register Low */ -#define MCF5282_INTC0_IMRL (volatile u32 *) (MCF_IPSBAR + 0x0C0C) -/* Interrupt Control Register 7 */ -#define MCF5282_INTC0_ICR17 (volatile u8 *) (MCF_IPSBAR + 0x0C51) - - - -/********************************************************************* -* -* Inter-IC (I2C) Module -* -*********************************************************************/ -/* Read/Write access macros for general use */ -#define MCF5282_I2C_I2ADR (volatile u8 *) (MCF_IPSBAR + 0x0300) // Address -#define MCF5282_I2C_I2FDR (volatile u8 *) (MCF_IPSBAR + 0x0304) // Freq Divider -#define MCF5282_I2C_I2CR (volatile u8 *) (MCF_IPSBAR + 0x0308) // Control -#define MCF5282_I2C_I2SR (volatile u8 *) (MCF_IPSBAR + 0x030C) // Status -#define MCF5282_I2C_I2DR (volatile u8 *) (MCF_IPSBAR + 0x0310) // Data I/O - -/* Bit level definitions and macros */ -#define MCF5282_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) - -#define MCF5282_I2C_I2FDR_IC(x) (((x)&0x3F)) - -#define MCF5282_I2C_I2CR_IEN (0x80) // I2C enable -#define MCF5282_I2C_I2CR_IIEN (0x40) // interrupt enable -#define MCF5282_I2C_I2CR_MSTA (0x20) // master/slave mode -#define MCF5282_I2C_I2CR_MTX (0x10) // transmit/receive mode -#define MCF5282_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable -#define MCF5282_I2C_I2CR_RSTA (0x04) // repeat start - -#define MCF5282_I2C_I2SR_ICF (0x80) // data transfer bit -#define MCF5282_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave -#define MCF5282_I2C_I2SR_IBB (0x20) // I2C bus busy -#define MCF5282_I2C_I2SR_IAL (0x10) // aribitration lost -#define MCF5282_I2C_I2SR_SRW (0x04) // slave read/write -#define MCF5282_I2C_I2SR_IIF (0x02) // I2C interrupt -#define MCF5282_I2C_I2SR_RXAK (0x01) // received acknowledge - - - -/********************************************************************* -* -* Queued Serial Peripheral Interface (QSPI) Module -* -*********************************************************************/ -/* Derek - 21 Feb 2005 */ -/* change to the format used in I2C */ -/* Read/Write access macros for general use */ -#define MCF5282_QSPI_QMR MCF_IPSBAR + 0x0340 -#define MCF5282_QSPI_QDLYR MCF_IPSBAR + 0x0344 -#define MCF5282_QSPI_QWR MCF_IPSBAR + 0x0348 -#define MCF5282_QSPI_QIR MCF_IPSBAR + 0x034C -#define MCF5282_QSPI_QAR MCF_IPSBAR + 0x0350 -#define MCF5282_QSPI_QDR MCF_IPSBAR + 0x0354 -#define MCF5282_QSPI_QCR MCF_IPSBAR + 0x0354 - -/* Bit level definitions and macros */ -#define MCF5282_QSPI_QMR_MSTR (0x8000) -#define MCF5282_QSPI_QMR_DOHIE (0x4000) -#define MCF5282_QSPI_QMR_BITS_16 (0x0000) -#define MCF5282_QSPI_QMR_BITS_8 (0x2000) -#define MCF5282_QSPI_QMR_BITS_9 (0x2400) -#define MCF5282_QSPI_QMR_BITS_10 (0x2800) -#define MCF5282_QSPI_QMR_BITS_11 (0x2C00) -#define MCF5282_QSPI_QMR_BITS_12 (0x3000) -#define MCF5282_QSPI_QMR_BITS_13 (0x3400) -#define MCF5282_QSPI_QMR_BITS_14 (0x3800) -#define MCF5282_QSPI_QMR_BITS_15 (0x3C00) -#define MCF5282_QSPI_QMR_CPOL (0x0200) -#define MCF5282_QSPI_QMR_CPHA (0x0100) -#define MCF5282_QSPI_QMR_BAUD(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QDLYR_SPE (0x80) -#define MCF5282_QSPI_QDLYR_QCD(x) (((x)&0x007F)<<8) -#define MCF5282_QSPI_QDLYR_DTL(x) (((x)&0x00FF)) - -#define MCF5282_QSPI_QWR_HALT (0x8000) -#define MCF5282_QSPI_QWR_WREN (0x4000) -#define MCF5282_QSPI_QWR_WRTO (0x2000) -#define MCF5282_QSPI_QWR_CSIV (0x1000) -#define MCF5282_QSPI_QWR_ENDQP(x) (((x)&0x000F)<<8) -#define MCF5282_QSPI_QWR_CPTQP(x) (((x)&0x000F)<<4) -#define MCF5282_QSPI_QWR_NEWQP(x) (((x)&0x000F)) - -#define MCF5282_QSPI_QIR_WCEFB (0x8000) -#define MCF5282_QSPI_QIR_ABRTB (0x4000) -#define MCF5282_QSPI_QIR_ABRTL (0x1000) -#define MCF5282_QSPI_QIR_WCEFE (0x0800) -#define MCF5282_QSPI_QIR_ABRTE (0x0400) -#define MCF5282_QSPI_QIR_SPIFE (0x0100) -#define MCF5282_QSPI_QIR_WCEF (0x0008) -#define MCF5282_QSPI_QIR_ABRT (0x0004) -#define MCF5282_QSPI_QIR_SPIF (0x0001) - -#define MCF5282_QSPI_QAR_ADDR(x) (((x)&0x003F)) - -#define MCF5282_QSPI_QDR_COMMAND(x) (((x)&0xFF00)) -#define MCF5282_QSPI_QCR_DATA(x) (((x)&0x00FF)<<8) -#define MCF5282_QSPI_QCR_CONT (0x8000) -#define MCF5282_QSPI_QCR_BITSE (0x4000) -#define MCF5282_QSPI_QCR_DT (0x2000) -#define MCF5282_QSPI_QCR_DSCK (0x1000) -#define MCF5282_QSPI_QCR_CS (((x)&0x000F)<<8) - -/****************************************************************************/ -#endif /* m528xsim_h */ diff --git a/include/asm-m68knommu/m5307sim.h b/include/asm-m68knommu/m5307sim.h deleted file mode 100644 index 5886728409c0..000000000000 --- a/include/asm-m68knommu/m5307sim.h +++ /dev/null @@ -1,181 +0,0 @@ -/****************************************************************************/ - -/* - * m5307sim.h -- ColdFire 5307 System Integration Module support. - * - * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. - * (C) Copyright 1999, Lineo (www.lineo.com) - * - * Modified by David W. Miller for the MCF5307 Eval Board. - */ - -/****************************************************************************/ -#ifndef m5307sim_h -#define m5307sim_h -/****************************************************************************/ - -/* - * Define the 5307 SIM register set addresses. - */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ -#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ -#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ - -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ - -#ifdef CONFIG_OLDMASK -#define MCFSIM_CSBAR 0x98 /* CS Base Address reg (r/w) */ -#define MCFSIM_CSBAMR 0x9c /* CS Base Mask reg (r/w) */ -#define MCFSIM_CSMR2 0x9e /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSMR3 0xaa /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSMR4 0xb6 /* CS 4 Mask reg (r/w) */ -#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSMR5 0xc2 /* CS 5 Mask reg (r/w) */ -#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSMR6 0xce /* CS 6 Mask reg (r/w) */ -#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSMR7 0xda /* CS 7 Mask reg (r/w) */ -#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ -#else -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ -#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ -#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ -#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ -#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ -#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ -#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ -#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ -#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ -#endif /* CONFIG_OLDMASK */ - -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - -#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ -#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ - - -/* Definition offset address for CS2-7 -- old mask 5307 */ - -#define MCF5307_CS2 (0x400000) -#define MCF5307_CS3 (0x600000) -#define MCF5307_CS4 (0x800000) -#define MCF5307_CS5 (0xA00000) -#define MCF5307_CS6 (0xC00000) -#define MCF5307_CS7 (0xE00000) - - -/* - * Some symbol defines for the above... - */ -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ -#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ -#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ -#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ -#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ - -#if defined(CONFIG_M5307) -#define MCFSIM_IMR_MASKALL 0x3fffe /* All SIM intr sources */ -#endif - -/* - * Macro to set IMR register. It is 32 bits on the 5307. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - - -/* - * Some symbol defines for the Parallel Port Pin Assignment Register - */ -#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ - /* Clear to select par I/O */ -#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ - /* Clear to select par I/O */ - -/* - * Defines for the IRQPAR Register - */ -#define IRQ5_LEVEL4 0x80 -#define IRQ3_LEVEL6 0x40 -#define IRQ1_LEVEL2 0x20 - - -/* - * Define the Cache register flags. - */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) - -/****************************************************************************/ -#endif /* m5307sim_h */ diff --git a/include/asm-m68knommu/m532xsim.h b/include/asm-m68knommu/m532xsim.h deleted file mode 100644 index 1835fd20a82c..000000000000 --- a/include/asm-m68knommu/m532xsim.h +++ /dev/null @@ -1,2238 +0,0 @@ -/****************************************************************************/ - -/* - * m532xsim.h -- ColdFire 5329 registers - */ - -/****************************************************************************/ -#ifndef m532xsim_h -#define m532xsim_h -/****************************************************************************/ - -#define MCF_REG32(x) (*(volatile unsigned long *)(x)) -#define MCF_REG16(x) (*(volatile unsigned short *)(x)) -#define MCF_REG08(x) (*(volatile unsigned char *)(x)) - -#define MCFINT_VECBASE 64 -#define MCFINT_UART0 26 /* Interrupt number for UART0 */ -#define MCFINT_UART1 27 /* Interrupt number for UART1 */ - -#define MCF_WTM_WCR MCF_REG16(0xFC098000) - -/* - * Define the 532x SIM register set addresses. - */ -#define MCFSIM_IPRL 0xFC048004 -#define MCFSIM_IPRH 0xFC048000 -#define MCFSIM_IPR MCFSIM_IPRL -#define MCFSIM_IMRL 0xFC04800C -#define MCFSIM_IMRH 0xFC048008 -#define MCFSIM_IMR MCFSIM_IMRL -#define MCFSIM_ICR0 0xFC048040 -#define MCFSIM_ICR1 0xFC048041 -#define MCFSIM_ICR2 0xFC048042 -#define MCFSIM_ICR3 0xFC048043 -#define MCFSIM_ICR4 0xFC048044 -#define MCFSIM_ICR5 0xFC048045 -#define MCFSIM_ICR6 0xFC048046 -#define MCFSIM_ICR7 0xFC048047 -#define MCFSIM_ICR8 0xFC048048 -#define MCFSIM_ICR9 0xFC048049 -#define MCFSIM_ICR10 0xFC04804A -#define MCFSIM_ICR11 0xFC04804B - -/* - * Some symbol defines for the above... - */ -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ -#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ -#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ -#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ -#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ - - -#define MCFSIM_IMR_MASKALL 0xFFFFFFFF /* All SIM intr sources */ - -#define MCFSIM_IMR_SIMR0 0xFC04801C -#define MCFSIM_IMR_SIMR1 0xFC04C01C -#define MCFSIM_IMR_CIMR0 0xFC04801D -#define MCFSIM_IMR_CIMR1 0xFC04C01D - -#define MCFSIM_ICR_TIMER1 (0xFC048040+32) -#define MCFSIM_ICR_TIMER2 (0xFC048040+33) - - -/* - * Macro to set IMR register. It is 32 bits on the 5307. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - -#define mcf_getiprl() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRL)) - -#define mcf_getiprh() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPRH)) - - -#define mcf_enable_irq0(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_CIMR0)) = (irq); - -#define mcf_enable_irq1(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_CIMR1)) = (irq); - -#define mcf_disable_irq0(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_SIMR0)) = (irq); - -#define mcf_disable_irq1(irq) \ - *((volatile unsigned char*) (MCFSIM_IMR_SIMR1)) = (irq); - -/* - * Define the Cache register flags. - */ -#define CACR_EC (1<<31) -#define CACR_ESB (1<<29) -#define CACR_DPI (1<<28) -#define CACR_HLCK (1<<27) -#define CACR_CINVA (1<<24) -#define CACR_DNFB (1<<10) -#define CACR_DCM_WTHRU (0<<8) -#define CACR_DCM_WBACK (1<<8) -#define CACR_DCM_OFF_PRE (2<<8) -#define CACR_DCM_OFF_IMP (3<<8) -#define CACR_DW (1<<5) - -#define ACR_BASE_POS 24 -#define ACR_MASK_POS 16 -#define ACR_ENABLE (1<<15) -#define ACR_USER (0<<13) -#define ACR_SUPER (1<<13) -#define ACR_ANY (2<<13) -#define ACR_CM_WTHRU (0<<5) -#define ACR_CM_WBACK (1<<5) -#define ACR_CM_OFF_PRE (2<<5) -#define ACR_CM_OFF_IMP (3<<5) -#define ACR_WPROTECT (1<<2) - -/********************************************************************* - * - * Inter-IC (I2C) Module - * - *********************************************************************/ - -/* Read/Write access macros for general use */ -#define MCF532x_I2C_I2ADR (volatile u8 *) (0xFC058000) // Address -#define MCF532x_I2C_I2FDR (volatile u8 *) (0xFC058004) // Freq Divider -#define MCF532x_I2C_I2CR (volatile u8 *) (0xFC058008) // Control -#define MCF532x_I2C_I2SR (volatile u8 *) (0xFC05800C) // Status -#define MCF532x_I2C_I2DR (volatile u8 *) (0xFC058010) // Data I/O - -/* Bit level definitions and macros */ -#define MCF532x_I2C_I2ADR_ADDR(x) (((x)&0x7F)<<0x01) - -#define MCF532x_I2C_I2FDR_IC(x) (((x)&0x3F)) - -#define MCF532x_I2C_I2CR_IEN (0x80) // I2C enable -#define MCF532x_I2C_I2CR_IIEN (0x40) // interrupt enable -#define MCF532x_I2C_I2CR_MSTA (0x20) // master/slave mode -#define MCF532x_I2C_I2CR_MTX (0x10) // transmit/receive mode -#define MCF532x_I2C_I2CR_TXAK (0x08) // transmit acknowledge enable -#define MCF532x_I2C_I2CR_RSTA (0x04) // repeat start - -#define MCF532x_I2C_I2SR_ICF (0x80) // data transfer bit -#define MCF532x_I2C_I2SR_IAAS (0x40) // I2C addressed as a slave -#define MCF532x_I2C_I2SR_IBB (0x20) // I2C bus busy -#define MCF532x_I2C_I2SR_IAL (0x10) // aribitration lost -#define MCF532x_I2C_I2SR_SRW (0x04) // slave read/write -#define MCF532x_I2C_I2SR_IIF (0x02) // I2C interrupt -#define MCF532x_I2C_I2SR_RXAK (0x01) // received acknowledge - -#define MCF532x_PAR_FECI2C (volatile u8 *) (0xFC0A4053) - - -/* - * The M5329EVB board needs a help getting its devices initialized - * at kernel start time if dBUG doesn't set it up (for example - * it is not used), so we need to do it manually. - */ -#ifdef __ASSEMBLER__ -.macro m5329EVB_setup - movel #0xFC098000, %a7 - movel #0x0, (%a7) -#define CORE_SRAM 0x80000000 -#define CORE_SRAM_SIZE 0x8000 - movel #CORE_SRAM, %d0 - addl #0x221, %d0 - movec %d0,%RAMBAR1 - movel #CORE_SRAM, %sp - addl #CORE_SRAM_SIZE, %sp - jsr sysinit -.endm -#define PLATFORM_SETUP m5329EVB_setup - -#endif /* __ASSEMBLER__ */ - -/********************************************************************* - * - * Chip Configuration Module (CCM) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_CCM_CCR MCF_REG16(0xFC0A0004) -#define MCF_CCM_RCON MCF_REG16(0xFC0A0008) -#define MCF_CCM_CIR MCF_REG16(0xFC0A000A) -#define MCF_CCM_MISCCR MCF_REG16(0xFC0A0010) -#define MCF_CCM_CDR MCF_REG16(0xFC0A0012) -#define MCF_CCM_UHCSR MCF_REG16(0xFC0A0014) -#define MCF_CCM_UOCSR MCF_REG16(0xFC0A0016) - -/* Bit definitions and macros for MCF_CCM_CCR */ -#define MCF_CCM_CCR_RESERVED (0x0001) -#define MCF_CCM_CCR_PLL_MODE (0x0003) -#define MCF_CCM_CCR_OSC_MODE (0x0005) -#define MCF_CCM_CCR_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define MCF_CCM_CCR_LOAD (0x0021) -#define MCF_CCM_CCR_LIMP (0x0041) -#define MCF_CCM_CCR_CSC(x) (((x)&0x0003)<<8|0x0001) - -/* Bit definitions and macros for MCF_CCM_RCON */ -#define MCF_CCM_RCON_RESERVED (0x0001) -#define MCF_CCM_RCON_PLL_MODE (0x0003) -#define MCF_CCM_RCON_OSC_MODE (0x0005) -#define MCF_CCM_RCON_BOOTPS(x) (((x)&0x0003)<<3|0x0001) -#define MCF_CCM_RCON_LOAD (0x0021) -#define MCF_CCM_RCON_LIMP (0x0041) -#define MCF_CCM_RCON_CSC(x) (((x)&0x0003)<<8|0x0001) - -/* Bit definitions and macros for MCF_CCM_CIR */ -#define MCF_CCM_CIR_PRN(x) (((x)&0x003F)<<0) -#define MCF_CCM_CIR_PIN(x) (((x)&0x03FF)<<6) - -/* Bit definitions and macros for MCF_CCM_MISCCR */ -#define MCF_CCM_MISCCR_USBSRC (0x0001) -#define MCF_CCM_MISCCR_USBDIV (0x0002) -#define MCF_CCM_MISCCR_SSI_SRC (0x0010) -#define MCF_CCM_MISCCR_TIM_DMA (0x0020) -#define MCF_CCM_MISCCR_SSI_PUS (0x0040) -#define MCF_CCM_MISCCR_SSI_PUE (0x0080) -#define MCF_CCM_MISCCR_LCD_CHEN (0x0100) -#define MCF_CCM_MISCCR_LIMP (0x1000) -#define MCF_CCM_MISCCR_PLL_LOCK (0x2000) - -/* Bit definitions and macros for MCF_CCM_CDR */ -#define MCF_CCM_CDR_SSIDIV(x) (((x)&0x000F)<<0) -#define MCF_CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) - -/* Bit definitions and macros for MCF_CCM_UHCSR */ -#define MCF_CCM_UHCSR_XPDE (0x0001) -#define MCF_CCM_UHCSR_UHMIE (0x0002) -#define MCF_CCM_UHCSR_WKUP (0x0004) -#define MCF_CCM_UHCSR_PORTIND(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_CCM_UOCSR */ -#define MCF_CCM_UOCSR_XPDE (0x0001) -#define MCF_CCM_UOCSR_UOMIE (0x0002) -#define MCF_CCM_UOCSR_WKUP (0x0004) -#define MCF_CCM_UOCSR_PWRFLT (0x0008) -#define MCF_CCM_UOCSR_SEND (0x0010) -#define MCF_CCM_UOCSR_VVLD (0x0020) -#define MCF_CCM_UOCSR_BVLD (0x0040) -#define MCF_CCM_UOCSR_AVLD (0x0080) -#define MCF_CCM_UOCSR_DPPU (0x0100) -#define MCF_CCM_UOCSR_DCR_VBUS (0x0200) -#define MCF_CCM_UOCSR_CRG_VBUS (0x0400) -#define MCF_CCM_UOCSR_DRV_VBUS (0x0800) -#define MCF_CCM_UOCSR_DMPD (0x1000) -#define MCF_CCM_UOCSR_DPPD (0x2000) -#define MCF_CCM_UOCSR_PORTIND(x) (((x)&0x0003)<<14) - -/********************************************************************* - * - * DMA Timers (DTIM) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_DTIM0_DTMR MCF_REG16(0xFC070000) -#define MCF_DTIM0_DTXMR MCF_REG08(0xFC070002) -#define MCF_DTIM0_DTER MCF_REG08(0xFC070003) -#define MCF_DTIM0_DTRR MCF_REG32(0xFC070004) -#define MCF_DTIM0_DTCR MCF_REG32(0xFC070008) -#define MCF_DTIM0_DTCN MCF_REG32(0xFC07000C) -#define MCF_DTIM1_DTMR MCF_REG16(0xFC074000) -#define MCF_DTIM1_DTXMR MCF_REG08(0xFC074002) -#define MCF_DTIM1_DTER MCF_REG08(0xFC074003) -#define MCF_DTIM1_DTRR MCF_REG32(0xFC074004) -#define MCF_DTIM1_DTCR MCF_REG32(0xFC074008) -#define MCF_DTIM1_DTCN MCF_REG32(0xFC07400C) -#define MCF_DTIM2_DTMR MCF_REG16(0xFC078000) -#define MCF_DTIM2_DTXMR MCF_REG08(0xFC078002) -#define MCF_DTIM2_DTER MCF_REG08(0xFC078003) -#define MCF_DTIM2_DTRR MCF_REG32(0xFC078004) -#define MCF_DTIM2_DTCR MCF_REG32(0xFC078008) -#define MCF_DTIM2_DTCN MCF_REG32(0xFC07800C) -#define MCF_DTIM3_DTMR MCF_REG16(0xFC07C000) -#define MCF_DTIM3_DTXMR MCF_REG08(0xFC07C002) -#define MCF_DTIM3_DTER MCF_REG08(0xFC07C003) -#define MCF_DTIM3_DTRR MCF_REG32(0xFC07C004) -#define MCF_DTIM3_DTCR MCF_REG32(0xFC07C008) -#define MCF_DTIM3_DTCN MCF_REG32(0xFC07C00C) -#define MCF_DTIM_DTMR(x) MCF_REG16(0xFC070000+((x)*0x4000)) -#define MCF_DTIM_DTXMR(x) MCF_REG08(0xFC070002+((x)*0x4000)) -#define MCF_DTIM_DTER(x) MCF_REG08(0xFC070003+((x)*0x4000)) -#define MCF_DTIM_DTRR(x) MCF_REG32(0xFC070004+((x)*0x4000)) -#define MCF_DTIM_DTCR(x) MCF_REG32(0xFC070008+((x)*0x4000)) -#define MCF_DTIM_DTCN(x) MCF_REG32(0xFC07000C+((x)*0x4000)) - -/* Bit definitions and macros for MCF_DTIM_DTMR */ -#define MCF_DTIM_DTMR_RST (0x0001) -#define MCF_DTIM_DTMR_CLK(x) (((x)&0x0003)<<1) -#define MCF_DTIM_DTMR_FRR (0x0008) -#define MCF_DTIM_DTMR_ORRI (0x0010) -#define MCF_DTIM_DTMR_OM (0x0020) -#define MCF_DTIM_DTMR_CE(x) (((x)&0x0003)<<6) -#define MCF_DTIM_DTMR_PS(x) (((x)&0x00FF)<<8) -#define MCF_DTIM_DTMR_CE_ANY (0x00C0) -#define MCF_DTIM_DTMR_CE_FALL (0x0080) -#define MCF_DTIM_DTMR_CE_RISE (0x0040) -#define MCF_DTIM_DTMR_CE_NONE (0x0000) -#define MCF_DTIM_DTMR_CLK_DTIN (0x0006) -#define MCF_DTIM_DTMR_CLK_DIV16 (0x0004) -#define MCF_DTIM_DTMR_CLK_DIV1 (0x0002) -#define MCF_DTIM_DTMR_CLK_STOP (0x0000) - -/* Bit definitions and macros for MCF_DTIM_DTXMR */ -#define MCF_DTIM_DTXMR_MODE16 (0x01) -#define MCF_DTIM_DTXMR_DMAEN (0x80) - -/* Bit definitions and macros for MCF_DTIM_DTER */ -#define MCF_DTIM_DTER_CAP (0x01) -#define MCF_DTIM_DTER_REF (0x02) - -/* Bit definitions and macros for MCF_DTIM_DTRR */ -#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCR */ -#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_DTIM_DTCN */ -#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* - * - * FlexBus Chip Selects (FBCS) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_FBCS0_CSAR MCF_REG32(0xFC008000) -#define MCF_FBCS0_CSMR MCF_REG32(0xFC008004) -#define MCF_FBCS0_CSCR MCF_REG32(0xFC008008) -#define MCF_FBCS1_CSAR MCF_REG32(0xFC00800C) -#define MCF_FBCS1_CSMR MCF_REG32(0xFC008010) -#define MCF_FBCS1_CSCR MCF_REG32(0xFC008014) -#define MCF_FBCS2_CSAR MCF_REG32(0xFC008018) -#define MCF_FBCS2_CSMR MCF_REG32(0xFC00801C) -#define MCF_FBCS2_CSCR MCF_REG32(0xFC008020) -#define MCF_FBCS3_CSAR MCF_REG32(0xFC008024) -#define MCF_FBCS3_CSMR MCF_REG32(0xFC008028) -#define MCF_FBCS3_CSCR MCF_REG32(0xFC00802C) -#define MCF_FBCS4_CSAR MCF_REG32(0xFC008030) -#define MCF_FBCS4_CSMR MCF_REG32(0xFC008034) -#define MCF_FBCS4_CSCR MCF_REG32(0xFC008038) -#define MCF_FBCS5_CSAR MCF_REG32(0xFC00803C) -#define MCF_FBCS5_CSMR MCF_REG32(0xFC008040) -#define MCF_FBCS5_CSCR MCF_REG32(0xFC008044) -#define MCF_FBCS_CSAR(x) MCF_REG32(0xFC008000+((x)*0x00C)) -#define MCF_FBCS_CSMR(x) MCF_REG32(0xFC008004+((x)*0x00C)) -#define MCF_FBCS_CSCR(x) MCF_REG32(0xFC008008+((x)*0x00C)) - -/* Bit definitions and macros for MCF_FBCS_CSAR */ -#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000) - -/* Bit definitions and macros for MCF_FBCS_CSMR */ -#define MCF_FBCS_CSMR_V (0x00000001) -#define MCF_FBCS_CSMR_WP (0x00000100) -#define MCF_FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) -#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000) -#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000) -#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000) -#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000) -#define MCF_FBCS_CSMR_BAM_256M (0x0FFF0000) -#define MCF_FBCS_CSMR_BAM_128M (0x07FF0000) -#define MCF_FBCS_CSMR_BAM_64M (0x03FF0000) -#define MCF_FBCS_CSMR_BAM_32M (0x01FF0000) -#define MCF_FBCS_CSMR_BAM_16M (0x00FF0000) -#define MCF_FBCS_CSMR_BAM_8M (0x007F0000) -#define MCF_FBCS_CSMR_BAM_4M (0x003F0000) -#define MCF_FBCS_CSMR_BAM_2M (0x001F0000) -#define MCF_FBCS_CSMR_BAM_1M (0x000F0000) -#define MCF_FBCS_CSMR_BAM_1024K (0x000F0000) -#define MCF_FBCS_CSMR_BAM_512K (0x00070000) -#define MCF_FBCS_CSMR_BAM_256K (0x00030000) -#define MCF_FBCS_CSMR_BAM_128K (0x00010000) -#define MCF_FBCS_CSMR_BAM_64K (0x00000000) - -/* Bit definitions and macros for MCF_FBCS_CSCR */ -#define MCF_FBCS_CSCR_BSTW (0x00000008) -#define MCF_FBCS_CSCR_BSTR (0x00000010) -#define MCF_FBCS_CSCR_BEM (0x00000020) -#define MCF_FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) -#define MCF_FBCS_CSCR_AA (0x00000100) -#define MCF_FBCS_CSCR_SBM (0x00000200) -#define MCF_FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) -#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) -#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) -#define MCF_FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) -#define MCF_FBCS_CSCR_SWSEN (0x00800000) -#define MCF_FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) -#define MCF_FBCS_CSCR_PS_8 (0x0040) -#define MCF_FBCS_CSCR_PS_16 (0x0080) -#define MCF_FBCS_CSCR_PS_32 (0x0000) - -/********************************************************************* - * - * General Purpose I/O (GPIO) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_GPIO_PODR_FECH MCF_REG08(0xFC0A4000) -#define MCF_GPIO_PODR_FECL MCF_REG08(0xFC0A4001) -#define MCF_GPIO_PODR_SSI MCF_REG08(0xFC0A4002) -#define MCF_GPIO_PODR_BUSCTL MCF_REG08(0xFC0A4003) -#define MCF_GPIO_PODR_BE MCF_REG08(0xFC0A4004) -#define MCF_GPIO_PODR_CS MCF_REG08(0xFC0A4005) -#define MCF_GPIO_PODR_PWM MCF_REG08(0xFC0A4006) -#define MCF_GPIO_PODR_FECI2C MCF_REG08(0xFC0A4007) -#define MCF_GPIO_PODR_UART MCF_REG08(0xFC0A4009) -#define MCF_GPIO_PODR_QSPI MCF_REG08(0xFC0A400A) -#define MCF_GPIO_PODR_TIMER MCF_REG08(0xFC0A400B) -#define MCF_GPIO_PODR_LCDDATAH MCF_REG08(0xFC0A400D) -#define MCF_GPIO_PODR_LCDDATAM MCF_REG08(0xFC0A400E) -#define MCF_GPIO_PODR_LCDDATAL MCF_REG08(0xFC0A400F) -#define MCF_GPIO_PODR_LCDCTLH MCF_REG08(0xFC0A4010) -#define MCF_GPIO_PODR_LCDCTLL MCF_REG08(0xFC0A4011) -#define MCF_GPIO_PDDR_FECH MCF_REG08(0xFC0A4014) -#define MCF_GPIO_PDDR_FECL MCF_REG08(0xFC0A4015) -#define MCF_GPIO_PDDR_SSI MCF_REG08(0xFC0A4016) -#define MCF_GPIO_PDDR_BUSCTL MCF_REG08(0xFC0A4017) -#define MCF_GPIO_PDDR_BE MCF_REG08(0xFC0A4018) -#define MCF_GPIO_PDDR_CS MCF_REG08(0xFC0A4019) -#define MCF_GPIO_PDDR_PWM MCF_REG08(0xFC0A401A) -#define MCF_GPIO_PDDR_FECI2C MCF_REG08(0xFC0A401B) -#define MCF_GPIO_PDDR_UART MCF_REG08(0xFC0A401C) -#define MCF_GPIO_PDDR_QSPI MCF_REG08(0xFC0A401E) -#define MCF_GPIO_PDDR_TIMER MCF_REG08(0xFC0A401F) -#define MCF_GPIO_PDDR_LCDDATAH MCF_REG08(0xFC0A4021) -#define MCF_GPIO_PDDR_LCDDATAM MCF_REG08(0xFC0A4022) -#define MCF_GPIO_PDDR_LCDDATAL MCF_REG08(0xFC0A4023) -#define MCF_GPIO_PDDR_LCDCTLH MCF_REG08(0xFC0A4024) -#define MCF_GPIO_PDDR_LCDCTLL MCF_REG08(0xFC0A4025) -#define MCF_GPIO_PPDSDR_FECH MCF_REG08(0xFC0A4028) -#define MCF_GPIO_PPDSDR_FECL MCF_REG08(0xFC0A4029) -#define MCF_GPIO_PPDSDR_SSI MCF_REG08(0xFC0A402A) -#define MCF_GPIO_PPDSDR_BUSCTL MCF_REG08(0xFC0A402B) -#define MCF_GPIO_PPDSDR_BE MCF_REG08(0xFC0A402C) -#define MCF_GPIO_PPDSDR_CS MCF_REG08(0xFC0A402D) -#define MCF_GPIO_PPDSDR_PWM MCF_REG08(0xFC0A402E) -#define MCF_GPIO_PPDSDR_FECI2C MCF_REG08(0xFC0A402F) -#define MCF_GPIO_PPDSDR_UART MCF_REG08(0xFC0A4031) -#define MCF_GPIO_PPDSDR_QSPI MCF_REG08(0xFC0A4032) -#define MCF_GPIO_PPDSDR_TIMER MCF_REG08(0xFC0A4033) -#define MCF_GPIO_PPDSDR_LCDDATAH MCF_REG08(0xFC0A4035) -#define MCF_GPIO_PPDSDR_LCDDATAM MCF_REG08(0xFC0A4036) -#define MCF_GPIO_PPDSDR_LCDDATAL MCF_REG08(0xFC0A4037) -#define MCF_GPIO_PPDSDR_LCDCTLH MCF_REG08(0xFC0A4038) -#define MCF_GPIO_PPDSDR_LCDCTLL MCF_REG08(0xFC0A4039) -#define MCF_GPIO_PCLRR_FECH MCF_REG08(0xFC0A403C) -#define MCF_GPIO_PCLRR_FECL MCF_REG08(0xFC0A403D) -#define MCF_GPIO_PCLRR_SSI MCF_REG08(0xFC0A403E) -#define MCF_GPIO_PCLRR_BUSCTL MCF_REG08(0xFC0A403F) -#define MCF_GPIO_PCLRR_BE MCF_REG08(0xFC0A4040) -#define MCF_GPIO_PCLRR_CS MCF_REG08(0xFC0A4041) -#define MCF_GPIO_PCLRR_PWM MCF_REG08(0xFC0A4042) -#define MCF_GPIO_PCLRR_FECI2C MCF_REG08(0xFC0A4043) -#define MCF_GPIO_PCLRR_UART MCF_REG08(0xFC0A4045) -#define MCF_GPIO_PCLRR_QSPI MCF_REG08(0xFC0A4046) -#define MCF_GPIO_PCLRR_TIMER MCF_REG08(0xFC0A4047) -#define MCF_GPIO_PCLRR_LCDDATAH MCF_REG08(0xFC0A4049) -#define MCF_GPIO_PCLRR_LCDDATAM MCF_REG08(0xFC0A404A) -#define MCF_GPIO_PCLRR_LCDDATAL MCF_REG08(0xFC0A404B) -#define MCF_GPIO_PCLRR_LCDCTLH MCF_REG08(0xFC0A404C) -#define MCF_GPIO_PCLRR_LCDCTLL MCF_REG08(0xFC0A404D) -#define MCF_GPIO_PAR_FEC MCF_REG08(0xFC0A4050) -#define MCF_GPIO_PAR_PWM MCF_REG08(0xFC0A4051) -#define MCF_GPIO_PAR_BUSCTL MCF_REG08(0xFC0A4052) -#define MCF_GPIO_PAR_FECI2C MCF_REG08(0xFC0A4053) -#define MCF_GPIO_PAR_BE MCF_REG08(0xFC0A4054) -#define MCF_GPIO_PAR_CS MCF_REG08(0xFC0A4055) -#define MCF_GPIO_PAR_SSI MCF_REG16(0xFC0A4056) -#define MCF_GPIO_PAR_UART MCF_REG16(0xFC0A4058) -#define MCF_GPIO_PAR_QSPI MCF_REG16(0xFC0A405A) -#define MCF_GPIO_PAR_TIMER MCF_REG08(0xFC0A405C) -#define MCF_GPIO_PAR_LCDDATA MCF_REG08(0xFC0A405D) -#define MCF_GPIO_PAR_LCDCTL MCF_REG16(0xFC0A405E) -#define MCF_GPIO_PAR_IRQ MCF_REG16(0xFC0A4060) -#define MCF_GPIO_MSCR_FLEXBUS MCF_REG08(0xFC0A4064) -#define MCF_GPIO_MSCR_SDRAM MCF_REG08(0xFC0A4065) -#define MCF_GPIO_DSCR_I2C MCF_REG08(0xFC0A4068) -#define MCF_GPIO_DSCR_PWM MCF_REG08(0xFC0A4069) -#define MCF_GPIO_DSCR_FEC MCF_REG08(0xFC0A406A) -#define MCF_GPIO_DSCR_UART MCF_REG08(0xFC0A406B) -#define MCF_GPIO_DSCR_QSPI MCF_REG08(0xFC0A406C) -#define MCF_GPIO_DSCR_TIMER MCF_REG08(0xFC0A406D) -#define MCF_GPIO_DSCR_SSI MCF_REG08(0xFC0A406E) -#define MCF_GPIO_DSCR_LCD MCF_REG08(0xFC0A406F) -#define MCF_GPIO_DSCR_DEBUG MCF_REG08(0xFC0A4070) -#define MCF_GPIO_DSCR_CLKRST MCF_REG08(0xFC0A4071) -#define MCF_GPIO_DSCR_IRQ MCF_REG08(0xFC0A4072) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECH */ -#define MCF_GPIO_PODR_FECH_PODR_FECH0 (0x01) -#define MCF_GPIO_PODR_FECH_PODR_FECH1 (0x02) -#define MCF_GPIO_PODR_FECH_PODR_FECH2 (0x04) -#define MCF_GPIO_PODR_FECH_PODR_FECH3 (0x08) -#define MCF_GPIO_PODR_FECH_PODR_FECH4 (0x10) -#define MCF_GPIO_PODR_FECH_PODR_FECH5 (0x20) -#define MCF_GPIO_PODR_FECH_PODR_FECH6 (0x40) -#define MCF_GPIO_PODR_FECH_PODR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECL */ -#define MCF_GPIO_PODR_FECL_PODR_FECL0 (0x01) -#define MCF_GPIO_PODR_FECL_PODR_FECL1 (0x02) -#define MCF_GPIO_PODR_FECL_PODR_FECL2 (0x04) -#define MCF_GPIO_PODR_FECL_PODR_FECL3 (0x08) -#define MCF_GPIO_PODR_FECL_PODR_FECL4 (0x10) -#define MCF_GPIO_PODR_FECL_PODR_FECL5 (0x20) -#define MCF_GPIO_PODR_FECL_PODR_FECL6 (0x40) -#define MCF_GPIO_PODR_FECL_PODR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_SSI */ -#define MCF_GPIO_PODR_SSI_PODR_SSI0 (0x01) -#define MCF_GPIO_PODR_SSI_PODR_SSI1 (0x02) -#define MCF_GPIO_PODR_SSI_PODR_SSI2 (0x04) -#define MCF_GPIO_PODR_SSI_PODR_SSI3 (0x08) -#define MCF_GPIO_PODR_SSI_PODR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PODR_BUSCTL */ -#define MCF_GPIO_PODR_BUSCTL_POSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL1 (0x02) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL2 (0x04) -#define MCF_GPIO_PODR_BUSCTL_PODR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_BE */ -#define MCF_GPIO_PODR_BE_PODR_BE0 (0x01) -#define MCF_GPIO_PODR_BE_PODR_BE1 (0x02) -#define MCF_GPIO_PODR_BE_PODR_BE2 (0x04) -#define MCF_GPIO_PODR_BE_PODR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_CS */ -#define MCF_GPIO_PODR_CS_PODR_CS1 (0x02) -#define MCF_GPIO_PODR_CS_PODR_CS2 (0x04) -#define MCF_GPIO_PODR_CS_PODR_CS3 (0x08) -#define MCF_GPIO_PODR_CS_PODR_CS4 (0x10) -#define MCF_GPIO_PODR_CS_PODR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_PWM */ -#define MCF_GPIO_PODR_PWM_PODR_PWM2 (0x04) -#define MCF_GPIO_PODR_PWM_PODR_PWM3 (0x08) -#define MCF_GPIO_PODR_PWM_PODR_PWM4 (0x10) -#define MCF_GPIO_PODR_PWM_PODR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */ -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x01) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x02) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x04) -#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_UART */ -#define MCF_GPIO_PODR_UART_PODR_UART0 (0x01) -#define MCF_GPIO_PODR_UART_PODR_UART1 (0x02) -#define MCF_GPIO_PODR_UART_PODR_UART2 (0x04) -#define MCF_GPIO_PODR_UART_PODR_UART3 (0x08) -#define MCF_GPIO_PODR_UART_PODR_UART4 (0x10) -#define MCF_GPIO_PODR_UART_PODR_UART5 (0x20) -#define MCF_GPIO_PODR_UART_PODR_UART6 (0x40) -#define MCF_GPIO_PODR_UART_PODR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_QSPI */ -#define MCF_GPIO_PODR_QSPI_PODR_QSPI0 (0x01) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI1 (0x02) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI2 (0x04) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI3 (0x08) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI4 (0x10) -#define MCF_GPIO_PODR_QSPI_PODR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PODR_TIMER */ -#define MCF_GPIO_PODR_TIMER_PODR_TIMER0 (0x01) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER1 (0x02) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER2 (0x04) -#define MCF_GPIO_PODR_TIMER_PODR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAH */ -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH0 (0x01) -#define MCF_GPIO_PODR_LCDDATAH_PODR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAM */ -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM0 (0x01) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM1 (0x02) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM2 (0x04) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM3 (0x08) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM4 (0x10) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM5 (0x20) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM6 (0x40) -#define MCF_GPIO_PODR_LCDDATAM_PODR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDDATAL */ -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL0 (0x01) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL1 (0x02) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL2 (0x04) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL3 (0x08) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL4 (0x10) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL5 (0x20) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL6 (0x40) -#define MCF_GPIO_PODR_LCDDATAL_PODR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLH */ -#define MCF_GPIO_PODR_LCDCTLH_PODR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PODR_LCDCTLL */ -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL0 (0x01) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL1 (0x02) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL2 (0x04) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL3 (0x08) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL4 (0x10) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL5 (0x20) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL6 (0x40) -#define MCF_GPIO_PODR_LCDCTLL_PODR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECH */ -#define MCF_GPIO_PDDR_FECH_PDDR_FECH0 (0x01) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH1 (0x02) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH2 (0x04) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH3 (0x08) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH4 (0x10) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH5 (0x20) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH6 (0x40) -#define MCF_GPIO_PDDR_FECH_PDDR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECL */ -#define MCF_GPIO_PDDR_FECL_PDDR_FECL0 (0x01) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL1 (0x02) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL2 (0x04) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL3 (0x08) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL4 (0x10) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL5 (0x20) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL6 (0x40) -#define MCF_GPIO_PDDR_FECL_PDDR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_SSI */ -#define MCF_GPIO_PDDR_SSI_PDDR_SSI0 (0x01) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI1 (0x02) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI2 (0x04) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI3 (0x08) -#define MCF_GPIO_PDDR_SSI_PDDR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BUSCTL */ -#define MCF_GPIO_PDDR_BUSCTL_POSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL1 (0x02) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL2 (0x04) -#define MCF_GPIO_PDDR_BUSCTL_PDDR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_BE */ -#define MCF_GPIO_PDDR_BE_PDDR_BE0 (0x01) -#define MCF_GPIO_PDDR_BE_PDDR_BE1 (0x02) -#define MCF_GPIO_PDDR_BE_PDDR_BE2 (0x04) -#define MCF_GPIO_PDDR_BE_PDDR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_CS */ -#define MCF_GPIO_PDDR_CS_PDDR_CS1 (0x02) -#define MCF_GPIO_PDDR_CS_PDDR_CS2 (0x04) -#define MCF_GPIO_PDDR_CS_PDDR_CS3 (0x08) -#define MCF_GPIO_PDDR_CS_PDDR_CS4 (0x10) -#define MCF_GPIO_PDDR_CS_PDDR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_PWM */ -#define MCF_GPIO_PDDR_PWM_PDDR_PWM2 (0x04) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM3 (0x08) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM4 (0x10) -#define MCF_GPIO_PDDR_PWM_PDDR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */ -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x01) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x02) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x04) -#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_UART */ -#define MCF_GPIO_PDDR_UART_PDDR_UART0 (0x01) -#define MCF_GPIO_PDDR_UART_PDDR_UART1 (0x02) -#define MCF_GPIO_PDDR_UART_PDDR_UART2 (0x04) -#define MCF_GPIO_PDDR_UART_PDDR_UART3 (0x08) -#define MCF_GPIO_PDDR_UART_PDDR_UART4 (0x10) -#define MCF_GPIO_PDDR_UART_PDDR_UART5 (0x20) -#define MCF_GPIO_PDDR_UART_PDDR_UART6 (0x40) -#define MCF_GPIO_PDDR_UART_PDDR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_QSPI */ -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI0 (0x01) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI1 (0x02) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI2 (0x04) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI3 (0x08) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI4 (0x10) -#define MCF_GPIO_PDDR_QSPI_PDDR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PDDR_TIMER */ -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER0 (0x01) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 (0x02) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 (0x04) -#define MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAH */ -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAH_PDDR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAM */ -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM1 (0x02) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM2 (0x04) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM3 (0x08) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM4 (0x10) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM5 (0x20) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM6 (0x40) -#define MCF_GPIO_PDDR_LCDDATAM_PDDR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDDATAL */ -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL0 (0x01) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL1 (0x02) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL2 (0x04) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL3 (0x08) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL4 (0x10) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL5 (0x20) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL6 (0x40) -#define MCF_GPIO_PDDR_LCDDATAL_PDDR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLH */ -#define MCF_GPIO_PDDR_LCDCTLH_PDDR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PDDR_LCDCTLL */ -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL0 (0x01) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL1 (0x02) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL2 (0x04) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL3 (0x08) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL4 (0x10) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL5 (0x20) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL6 (0x40) -#define MCF_GPIO_PDDR_LCDCTLL_PDDR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECH */ -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH0 (0x01) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH1 (0x02) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH2 (0x04) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH3 (0x08) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH4 (0x10) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH5 (0x20) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH6 (0x40) -#define MCF_GPIO_PPDSDR_FECH_PPDSDR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECL */ -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL0 (0x01) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL1 (0x02) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL2 (0x04) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL3 (0x08) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL4 (0x10) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL5 (0x20) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL6 (0x40) -#define MCF_GPIO_PPDSDR_FECL_PPDSDR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_SSI */ -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI0 (0x01) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI1 (0x02) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI2 (0x04) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI3 (0x08) -#define MCF_GPIO_PPDSDR_SSI_PPDSDR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BUSCTL */ -#define MCF_GPIO_PPDSDR_BUSCTL_POSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL1 (0x02) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL2 (0x04) -#define MCF_GPIO_PPDSDR_BUSCTL_PPDSDR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_BE */ -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE0 (0x01) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE1 (0x02) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE2 (0x04) -#define MCF_GPIO_PPDSDR_BE_PPDSDR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_CS */ -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS1 (0x02) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS2 (0x04) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS3 (0x08) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS4 (0x10) -#define MCF_GPIO_PPDSDR_CS_PPDSDR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_PWM */ -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM2 (0x04) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM3 (0x08) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM4 (0x10) -#define MCF_GPIO_PPDSDR_PWM_PPDSDR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */ -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x01) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x02) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x04) -#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_UART */ -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART0 (0x01) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART1 (0x02) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART2 (0x04) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART3 (0x08) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART4 (0x10) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART5 (0x20) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART6 (0x40) -#define MCF_GPIO_PPDSDR_UART_PPDSDR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_QSPI */ -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI0 (0x01) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI1 (0x02) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI2 (0x04) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI3 (0x08) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI4 (0x10) -#define MCF_GPIO_PPDSDR_QSPI_PPDSDR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_TIMER */ -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER0 (0x01) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER1 (0x02) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER2 (0x04) -#define MCF_GPIO_PPDSDR_TIMER_PPDSDR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAH */ -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAH_PPDSDR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAM */ -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM1 (0x02) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM2 (0x04) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM3 (0x08) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM4 (0x10) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM5 (0x20) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM6 (0x40) -#define MCF_GPIO_PPDSDR_LCDDATAM_PPDSDR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDDATAL */ -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL0 (0x01) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL1 (0x02) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL2 (0x04) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL3 (0x08) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL4 (0x10) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL5 (0x20) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL6 (0x40) -#define MCF_GPIO_PPDSDR_LCDDATAL_PPDSDR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLH */ -#define MCF_GPIO_PPDSDR_LCDCTLH_PPDSDR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PPDSDR_LCDCTLL */ -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL0 (0x01) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL1 (0x02) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL2 (0x04) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL3 (0x08) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL4 (0x10) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL5 (0x20) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL6 (0x40) -#define MCF_GPIO_PPDSDR_LCDCTLL_PPDSDR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECH */ -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH0 (0x01) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH1 (0x02) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH2 (0x04) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH3 (0x08) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH4 (0x10) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH5 (0x20) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH6 (0x40) -#define MCF_GPIO_PCLRR_FECH_PCLRR_FECH7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECL */ -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL0 (0x01) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL1 (0x02) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL2 (0x04) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL3 (0x08) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL4 (0x10) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL5 (0x20) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL6 (0x40) -#define MCF_GPIO_PCLRR_FECL_PCLRR_FECL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_SSI */ -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI0 (0x01) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI1 (0x02) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI2 (0x04) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI3 (0x08) -#define MCF_GPIO_PCLRR_SSI_PCLRR_SSI4 (0x10) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BUSCTL */ -#define MCF_GPIO_PCLRR_BUSCTL_POSDR_BUSCTL0 (0x01) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL1 (0x02) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL2 (0x04) -#define MCF_GPIO_PCLRR_BUSCTL_PCLRR_BUSCTL3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_BE */ -#define MCF_GPIO_PCLRR_BE_PCLRR_BE0 (0x01) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE1 (0x02) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE2 (0x04) -#define MCF_GPIO_PCLRR_BE_PCLRR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_CS */ -#define MCF_GPIO_PCLRR_CS_PCLRR_CS1 (0x02) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS2 (0x04) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS3 (0x08) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS4 (0x10) -#define MCF_GPIO_PCLRR_CS_PCLRR_CS5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_PWM */ -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM2 (0x04) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM3 (0x08) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM4 (0x10) -#define MCF_GPIO_PCLRR_PWM_PCLRR_PWM5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */ -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x01) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x02) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x04) -#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_UART */ -#define MCF_GPIO_PCLRR_UART_PCLRR_UART0 (0x01) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART1 (0x02) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART2 (0x04) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART3 (0x08) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART4 (0x10) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART5 (0x20) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART6 (0x40) -#define MCF_GPIO_PCLRR_UART_PCLRR_UART7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_QSPI */ -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI0 (0x01) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI1 (0x02) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI2 (0x04) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI3 (0x08) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI4 (0x10) -#define MCF_GPIO_PCLRR_QSPI_PCLRR_QSPI5 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_TIMER */ -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER0 (0x01) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER1 (0x02) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER2 (0x04) -#define MCF_GPIO_PCLRR_TIMER_PCLRR_TIMER3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAH */ -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAH_PCLRR_LCDDATAH1 (0x02) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAM */ -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM1 (0x02) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM2 (0x04) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM3 (0x08) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM4 (0x10) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM5 (0x20) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM6 (0x40) -#define MCF_GPIO_PCLRR_LCDDATAM_PCLRR_LCDDATAM7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDDATAL */ -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL0 (0x01) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL1 (0x02) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL2 (0x04) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL3 (0x08) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL4 (0x10) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL5 (0x20) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL6 (0x40) -#define MCF_GPIO_PCLRR_LCDDATAL_PCLRR_LCDDATAL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLH */ -#define MCF_GPIO_PCLRR_LCDCTLH_PCLRR_LCDCTLH0 (0x01) - -/* Bit definitions and macros for MCF_GPIO_PCLRR_LCDCTLL */ -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL0 (0x01) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL1 (0x02) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL2 (0x04) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL3 (0x08) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL4 (0x10) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL5 (0x20) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL6 (0x40) -#define MCF_GPIO_PCLRR_LCDCTLL_PCLRR_LCDCTLL7 (0x80) - -/* Bit definitions and macros for MCF_GPIO_PAR_FEC */ -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_GPIO (0x00) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_URTS1 (0x04) -#define MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC (0x0C) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_GPIO (0x00) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_UART (0x01) -#define MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_PWM */ -#define MCF_GPIO_PAR_PWM_PAR_PWM1(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_PWM_PAR_PWM3(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_PWM_PAR_PWM5 (0x10) -#define MCF_GPIO_PAR_PWM_PAR_PWM7 (0x20) - -/* Bit definitions and macros for MCF_GPIO_PAR_BUSCTL */ -#define MCF_GPIO_PAR_BUSCTL_PAR_TS(x) (((x)&0x03)<<3) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB (0x20) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA (0x40) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE (0x80) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_OE_OE (0x80) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TA_TA (0x40) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_RWB_RWB (0x20) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_GPIO (0x00) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_DACK0 (0x10) -#define MCF_GPIO_PAR_BUSCTL_PAR_TS_TS (0x18) - -/* Bit definitions and macros for MCF_GPIO_PAR_FECI2C */ -#define MCF_GPIO_PAR_FECI2C_PAR_SDA(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_UTXD2 (0x40) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_SCL (0x80) -#define MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC (0xC0) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_URXD2 (0x10) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_SDA (0x20) -#define MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO (0x30) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04) -#define MCF_GPIO_PAR_FECI2C_PAR_SCL_SCL (0x0C) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_GPIO (0x00) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02) -#define MCF_GPIO_PAR_FECI2C_PAR_SDA_SDA (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_BE */ -#define MCF_GPIO_PAR_BE_PAR_BE0 (0x01) -#define MCF_GPIO_PAR_BE_PAR_BE1 (0x02) -#define MCF_GPIO_PAR_BE_PAR_BE2 (0x04) -#define MCF_GPIO_PAR_BE_PAR_BE3 (0x08) - -/* Bit definitions and macros for MCF_GPIO_PAR_CS */ -#define MCF_GPIO_PAR_CS_PAR_CS1 (0x02) -#define MCF_GPIO_PAR_CS_PAR_CS2 (0x04) -#define MCF_GPIO_PAR_CS_PAR_CS3 (0x08) -#define MCF_GPIO_PAR_CS_PAR_CS4 (0x10) -#define MCF_GPIO_PAR_CS_PAR_CS5 (0x20) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_GPIO (0x00) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_SDCS1 (0x01) -#define MCF_GPIO_PAR_CS_PAR_CS_CS1_CS1 (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_SSI */ -#define MCF_GPIO_PAR_SSI_PAR_MCLK (0x0080) -#define MCF_GPIO_PAR_SSI_PAR_TXD(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_SSI_PAR_RXD(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_SSI_PAR_FS(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_SSI_PAR_BCLK(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_GPIO_PAR_UART */ -#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0001) -#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0002) -#define MCF_GPIO_PAR_UART_PAR_URTS0 (0x0004) -#define MCF_GPIO_PAR_UART_PAR_UCTS0 (0x0008) -#define MCF_GPIO_PAR_UART_PAR_UTXD1(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_UART_PAR_URXD1(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_UART_PAR_URTS1(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_UART_PAR_UCTS1(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_SSI_BCLK (0x0800) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_ULPI_D7 (0x0400) -#define MCF_GPIO_PAR_UART_PAR_UCTS1_UCTS1 (0x0C00) -#define MCF_GPIO_PAR_UART_PAR_URTS1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_URTS1_SSI_FS (0x0200) -#define MCF_GPIO_PAR_UART_PAR_URTS1_ULPI_D6 (0x0100) -#define MCF_GPIO_PAR_UART_PAR_URTS1_URTS1 (0x0300) -#define MCF_GPIO_PAR_UART_PAR_URXD1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_URXD1_SSI_RXD (0x0080) -#define MCF_GPIO_PAR_UART_PAR_URXD1_ULPI_D5 (0x0040) -#define MCF_GPIO_PAR_UART_PAR_URXD1_URXD1 (0x00C0) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_GPIO (0x0000) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_SSI_TXD (0x0020) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_ULPI_D4 (0x0010) -#define MCF_GPIO_PAR_UART_PAR_UTXD1_UTXD1 (0x0030) - -/* Bit definitions and macros for MCF_GPIO_PAR_QSPI */ -#define MCF_GPIO_PAR_QSPI_PAR_SCK(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_QSPI_PAR_DOUT(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_QSPI_PAR_DIN(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_QSPI_PAR_PCS0(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_QSPI_PAR_PCS1(x) (((x)&0x0003)<<12) -#define MCF_GPIO_PAR_QSPI_PAR_PCS2(x) (((x)&0x0003)<<14) - -/* Bit definitions and macros for MCF_GPIO_PAR_TIMER */ -#define MCF_GPIO_PAR_TIMER_PAR_TIN0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3(x) (((x)&0x03)<<6) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TOUT3 (0x80) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_URXD2 (0x40) -#define MCF_GPIO_PAR_TIMER_PAR_TIN3_TIN3 (0xC0) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TOUT2 (0x20) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_UTXD2 (0x10) -#define MCF_GPIO_PAR_TIMER_PAR_TIN2_TIN2 (0x30) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TOUT1 (0x08) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_DACK1 (0x04) -#define MCF_GPIO_PAR_TIMER_PAR_TIN1_TIN1 (0x0C) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_GPIO (0x00) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TOUT0 (0x02) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_DREQ0 (0x01) -#define MCF_GPIO_PAR_TIMER_PAR_TIN0_TIN0 (0x03) - -/* Bit definitions and macros for MCF_GPIO_PAR_LCDDATA */ -#define MCF_GPIO_PAR_LCDDATA_PAR_LD7_0(x) (((x)&0x03)<<0) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD15_8(x) (((x)&0x03)<<2) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD16(x) (((x)&0x03)<<4) -#define MCF_GPIO_PAR_LCDDATA_PAR_LD17(x) (((x)&0x03)<<6) - -/* Bit definitions and macros for MCF_GPIO_PAR_LCDCTL */ -#define MCF_GPIO_PAR_LCDCTL_PAR_CLS (0x0001) -#define MCF_GPIO_PAR_LCDCTL_PAR_PS (0x0002) -#define MCF_GPIO_PAR_LCDCTL_PAR_REV (0x0004) -#define MCF_GPIO_PAR_LCDCTL_PAR_SPL_SPR (0x0008) -#define MCF_GPIO_PAR_LCDCTL_PAR_CONTRAST (0x0010) -#define MCF_GPIO_PAR_LCDCTL_PAR_LSCLK (0x0020) -#define MCF_GPIO_PAR_LCDCTL_PAR_LP_HSYNC (0x0040) -#define MCF_GPIO_PAR_LCDCTL_PAR_FLM_VSYNC (0x0080) -#define MCF_GPIO_PAR_LCDCTL_PAR_ACD_OE (0x0100) - -/* Bit definitions and macros for MCF_GPIO_PAR_IRQ */ -#define MCF_GPIO_PAR_IRQ_PAR_IRQ1(x) (((x)&0x0003)<<4) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ2(x) (((x)&0x0003)<<6) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ4(x) (((x)&0x0003)<<8) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ5(x) (((x)&0x0003)<<10) -#define MCF_GPIO_PAR_IRQ_PAR_IRQ6(x) (((x)&0x0003)<<12) - -/* Bit definitions and macros for MCF_GPIO_MSCR_FLEXBUS */ -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_ADDRCTL(x) (((x)&0x03)<<0) -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DLOWER(x) (((x)&0x03)<<2) -#define MCF_GPIO_MSCR_FLEXBUS_MSCR_DUPPER(x) (((x)&0x03)<<4) - -/* Bit definitions and macros for MCF_GPIO_MSCR_SDRAM */ -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDRAM(x) (((x)&0x03)<<0) -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLK(x) (((x)&0x03)<<2) -#define MCF_GPIO_MSCR_SDRAM_MSCR_SDCLKB(x) (((x)&0x03)<<4) - -/* Bit definitions and macros for MCF_GPIO_DSCR_I2C */ -#define MCF_GPIO_DSCR_I2C_I2C_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_PWM */ -#define MCF_GPIO_DSCR_PWM_PWM_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_FEC */ -#define MCF_GPIO_DSCR_FEC_FEC_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_UART */ -#define MCF_GPIO_DSCR_UART_UART0_DSE(x) (((x)&0x03)<<0) -#define MCF_GPIO_DSCR_UART_UART1_DSE(x) (((x)&0x03)<<2) - -/* Bit definitions and macros for MCF_GPIO_DSCR_QSPI */ -#define MCF_GPIO_DSCR_QSPI_QSPI_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_TIMER */ -#define MCF_GPIO_DSCR_TIMER_TIMER_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_SSI */ -#define MCF_GPIO_DSCR_SSI_SSI_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_LCD */ -#define MCF_GPIO_DSCR_LCD_LCD_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_DEBUG */ -#define MCF_GPIO_DSCR_DEBUG_DEBUG_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_CLKRST */ -#define MCF_GPIO_DSCR_CLKRST_CLKRST_DSE(x) (((x)&0x03)<<0) - -/* Bit definitions and macros for MCF_GPIO_DSCR_IRQ */ -#define MCF_GPIO_DSCR_IRQ_IRQ_DSE(x) (((x)&0x03)<<0) - -/********************************************************************* - * - * Interrupt Controller (INTC) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_INTC0_IPRH MCF_REG32(0xFC048000) -#define MCF_INTC0_IPRL MCF_REG32(0xFC048004) -#define MCF_INTC0_IMRH MCF_REG32(0xFC048008) -#define MCF_INTC0_IMRL MCF_REG32(0xFC04800C) -#define MCF_INTC0_INTFRCH MCF_REG32(0xFC048010) -#define MCF_INTC0_INTFRCL MCF_REG32(0xFC048014) -#define MCF_INTC0_ICONFIG MCF_REG16(0xFC04801A) -#define MCF_INTC0_SIMR MCF_REG08(0xFC04801C) -#define MCF_INTC0_CIMR MCF_REG08(0xFC04801D) -#define MCF_INTC0_CLMASK MCF_REG08(0xFC04801E) -#define MCF_INTC0_SLMASK MCF_REG08(0xFC04801F) -#define MCF_INTC0_ICR0 MCF_REG08(0xFC048040) -#define MCF_INTC0_ICR1 MCF_REG08(0xFC048041) -#define MCF_INTC0_ICR2 MCF_REG08(0xFC048042) -#define MCF_INTC0_ICR3 MCF_REG08(0xFC048043) -#define MCF_INTC0_ICR4 MCF_REG08(0xFC048044) -#define MCF_INTC0_ICR5 MCF_REG08(0xFC048045) -#define MCF_INTC0_ICR6 MCF_REG08(0xFC048046) -#define MCF_INTC0_ICR7 MCF_REG08(0xFC048047) -#define MCF_INTC0_ICR8 MCF_REG08(0xFC048048) -#define MCF_INTC0_ICR9 MCF_REG08(0xFC048049) -#define MCF_INTC0_ICR10 MCF_REG08(0xFC04804A) -#define MCF_INTC0_ICR11 MCF_REG08(0xFC04804B) -#define MCF_INTC0_ICR12 MCF_REG08(0xFC04804C) -#define MCF_INTC0_ICR13 MCF_REG08(0xFC04804D) -#define MCF_INTC0_ICR14 MCF_REG08(0xFC04804E) -#define MCF_INTC0_ICR15 MCF_REG08(0xFC04804F) -#define MCF_INTC0_ICR16 MCF_REG08(0xFC048050) -#define MCF_INTC0_ICR17 MCF_REG08(0xFC048051) -#define MCF_INTC0_ICR18 MCF_REG08(0xFC048052) -#define MCF_INTC0_ICR19 MCF_REG08(0xFC048053) -#define MCF_INTC0_ICR20 MCF_REG08(0xFC048054) -#define MCF_INTC0_ICR21 MCF_REG08(0xFC048055) -#define MCF_INTC0_ICR22 MCF_REG08(0xFC048056) -#define MCF_INTC0_ICR23 MCF_REG08(0xFC048057) -#define MCF_INTC0_ICR24 MCF_REG08(0xFC048058) -#define MCF_INTC0_ICR25 MCF_REG08(0xFC048059) -#define MCF_INTC0_ICR26 MCF_REG08(0xFC04805A) -#define MCF_INTC0_ICR27 MCF_REG08(0xFC04805B) -#define MCF_INTC0_ICR28 MCF_REG08(0xFC04805C) -#define MCF_INTC0_ICR29 MCF_REG08(0xFC04805D) -#define MCF_INTC0_ICR30 MCF_REG08(0xFC04805E) -#define MCF_INTC0_ICR31 MCF_REG08(0xFC04805F) -#define MCF_INTC0_ICR32 MCF_REG08(0xFC048060) -#define MCF_INTC0_ICR33 MCF_REG08(0xFC048061) -#define MCF_INTC0_ICR34 MCF_REG08(0xFC048062) -#define MCF_INTC0_ICR35 MCF_REG08(0xFC048063) -#define MCF_INTC0_ICR36 MCF_REG08(0xFC048064) -#define MCF_INTC0_ICR37 MCF_REG08(0xFC048065) -#define MCF_INTC0_ICR38 MCF_REG08(0xFC048066) -#define MCF_INTC0_ICR39 MCF_REG08(0xFC048067) -#define MCF_INTC0_ICR40 MCF_REG08(0xFC048068) -#define MCF_INTC0_ICR41 MCF_REG08(0xFC048069) -#define MCF_INTC0_ICR42 MCF_REG08(0xFC04806A) -#define MCF_INTC0_ICR43 MCF_REG08(0xFC04806B) -#define MCF_INTC0_ICR44 MCF_REG08(0xFC04806C) -#define MCF_INTC0_ICR45 MCF_REG08(0xFC04806D) -#define MCF_INTC0_ICR46 MCF_REG08(0xFC04806E) -#define MCF_INTC0_ICR47 MCF_REG08(0xFC04806F) -#define MCF_INTC0_ICR48 MCF_REG08(0xFC048070) -#define MCF_INTC0_ICR49 MCF_REG08(0xFC048071) -#define MCF_INTC0_ICR50 MCF_REG08(0xFC048072) -#define MCF_INTC0_ICR51 MCF_REG08(0xFC048073) -#define MCF_INTC0_ICR52 MCF_REG08(0xFC048074) -#define MCF_INTC0_ICR53 MCF_REG08(0xFC048075) -#define MCF_INTC0_ICR54 MCF_REG08(0xFC048076) -#define MCF_INTC0_ICR55 MCF_REG08(0xFC048077) -#define MCF_INTC0_ICR56 MCF_REG08(0xFC048078) -#define MCF_INTC0_ICR57 MCF_REG08(0xFC048079) -#define MCF_INTC0_ICR58 MCF_REG08(0xFC04807A) -#define MCF_INTC0_ICR59 MCF_REG08(0xFC04807B) -#define MCF_INTC0_ICR60 MCF_REG08(0xFC04807C) -#define MCF_INTC0_ICR61 MCF_REG08(0xFC04807D) -#define MCF_INTC0_ICR62 MCF_REG08(0xFC04807E) -#define MCF_INTC0_ICR63 MCF_REG08(0xFC04807F) -#define MCF_INTC0_ICR(x) MCF_REG08(0xFC048040+((x)*0x001)) -#define MCF_INTC0_SWIACK MCF_REG08(0xFC0480E0) -#define MCF_INTC0_L1IACK MCF_REG08(0xFC0480E4) -#define MCF_INTC0_L2IACK MCF_REG08(0xFC0480E8) -#define MCF_INTC0_L3IACK MCF_REG08(0xFC0480EC) -#define MCF_INTC0_L4IACK MCF_REG08(0xFC0480F0) -#define MCF_INTC0_L5IACK MCF_REG08(0xFC0480F4) -#define MCF_INTC0_L6IACK MCF_REG08(0xFC0480F8) -#define MCF_INTC0_L7IACK MCF_REG08(0xFC0480FC) -#define MCF_INTC0_LIACK(x) MCF_REG08(0xFC0480E4+((x)*0x004)) -#define MCF_INTC1_IPRH MCF_REG32(0xFC04C000) -#define MCF_INTC1_IPRL MCF_REG32(0xFC04C004) -#define MCF_INTC1_IMRH MCF_REG32(0xFC04C008) -#define MCF_INTC1_IMRL MCF_REG32(0xFC04C00C) -#define MCF_INTC1_INTFRCH MCF_REG32(0xFC04C010) -#define MCF_INTC1_INTFRCL MCF_REG32(0xFC04C014) -#define MCF_INTC1_ICONFIG MCF_REG16(0xFC04C01A) -#define MCF_INTC1_SIMR MCF_REG08(0xFC04C01C) -#define MCF_INTC1_CIMR MCF_REG08(0xFC04C01D) -#define MCF_INTC1_CLMASK MCF_REG08(0xFC04C01E) -#define MCF_INTC1_SLMASK MCF_REG08(0xFC04C01F) -#define MCF_INTC1_ICR0 MCF_REG08(0xFC04C040) -#define MCF_INTC1_ICR1 MCF_REG08(0xFC04C041) -#define MCF_INTC1_ICR2 MCF_REG08(0xFC04C042) -#define MCF_INTC1_ICR3 MCF_REG08(0xFC04C043) -#define MCF_INTC1_ICR4 MCF_REG08(0xFC04C044) -#define MCF_INTC1_ICR5 MCF_REG08(0xFC04C045) -#define MCF_INTC1_ICR6 MCF_REG08(0xFC04C046) -#define MCF_INTC1_ICR7 MCF_REG08(0xFC04C047) -#define MCF_INTC1_ICR8 MCF_REG08(0xFC04C048) -#define MCF_INTC1_ICR9 MCF_REG08(0xFC04C049) -#define MCF_INTC1_ICR10 MCF_REG08(0xFC04C04A) -#define MCF_INTC1_ICR11 MCF_REG08(0xFC04C04B) -#define MCF_INTC1_ICR12 MCF_REG08(0xFC04C04C) -#define MCF_INTC1_ICR13 MCF_REG08(0xFC04C04D) -#define MCF_INTC1_ICR14 MCF_REG08(0xFC04C04E) -#define MCF_INTC1_ICR15 MCF_REG08(0xFC04C04F) -#define MCF_INTC1_ICR16 MCF_REG08(0xFC04C050) -#define MCF_INTC1_ICR17 MCF_REG08(0xFC04C051) -#define MCF_INTC1_ICR18 MCF_REG08(0xFC04C052) -#define MCF_INTC1_ICR19 MCF_REG08(0xFC04C053) -#define MCF_INTC1_ICR20 MCF_REG08(0xFC04C054) -#define MCF_INTC1_ICR21 MCF_REG08(0xFC04C055) -#define MCF_INTC1_ICR22 MCF_REG08(0xFC04C056) -#define MCF_INTC1_ICR23 MCF_REG08(0xFC04C057) -#define MCF_INTC1_ICR24 MCF_REG08(0xFC04C058) -#define MCF_INTC1_ICR25 MCF_REG08(0xFC04C059) -#define MCF_INTC1_ICR26 MCF_REG08(0xFC04C05A) -#define MCF_INTC1_ICR27 MCF_REG08(0xFC04C05B) -#define MCF_INTC1_ICR28 MCF_REG08(0xFC04C05C) -#define MCF_INTC1_ICR29 MCF_REG08(0xFC04C05D) -#define MCF_INTC1_ICR30 MCF_REG08(0xFC04C05E) -#define MCF_INTC1_ICR31 MCF_REG08(0xFC04C05F) -#define MCF_INTC1_ICR32 MCF_REG08(0xFC04C060) -#define MCF_INTC1_ICR33 MCF_REG08(0xFC04C061) -#define MCF_INTC1_ICR34 MCF_REG08(0xFC04C062) -#define MCF_INTC1_ICR35 MCF_REG08(0xFC04C063) -#define MCF_INTC1_ICR36 MCF_REG08(0xFC04C064) -#define MCF_INTC1_ICR37 MCF_REG08(0xFC04C065) -#define MCF_INTC1_ICR38 MCF_REG08(0xFC04C066) -#define MCF_INTC1_ICR39 MCF_REG08(0xFC04C067) -#define MCF_INTC1_ICR40 MCF_REG08(0xFC04C068) -#define MCF_INTC1_ICR41 MCF_REG08(0xFC04C069) -#define MCF_INTC1_ICR42 MCF_REG08(0xFC04C06A) -#define MCF_INTC1_ICR43 MCF_REG08(0xFC04C06B) -#define MCF_INTC1_ICR44 MCF_REG08(0xFC04C06C) -#define MCF_INTC1_ICR45 MCF_REG08(0xFC04C06D) -#define MCF_INTC1_ICR46 MCF_REG08(0xFC04C06E) -#define MCF_INTC1_ICR47 MCF_REG08(0xFC04C06F) -#define MCF_INTC1_ICR48 MCF_REG08(0xFC04C070) -#define MCF_INTC1_ICR49 MCF_REG08(0xFC04C071) -#define MCF_INTC1_ICR50 MCF_REG08(0xFC04C072) -#define MCF_INTC1_ICR51 MCF_REG08(0xFC04C073) -#define MCF_INTC1_ICR52 MCF_REG08(0xFC04C074) -#define MCF_INTC1_ICR53 MCF_REG08(0xFC04C075) -#define MCF_INTC1_ICR54 MCF_REG08(0xFC04C076) -#define MCF_INTC1_ICR55 MCF_REG08(0xFC04C077) -#define MCF_INTC1_ICR56 MCF_REG08(0xFC04C078) -#define MCF_INTC1_ICR57 MCF_REG08(0xFC04C079) -#define MCF_INTC1_ICR58 MCF_REG08(0xFC04C07A) -#define MCF_INTC1_ICR59 MCF_REG08(0xFC04C07B) -#define MCF_INTC1_ICR60 MCF_REG08(0xFC04C07C) -#define MCF_INTC1_ICR61 MCF_REG08(0xFC04C07D) -#define MCF_INTC1_ICR62 MCF_REG08(0xFC04C07E) -#define MCF_INTC1_ICR63 MCF_REG08(0xFC04C07F) -#define MCF_INTC1_ICR(x) MCF_REG08(0xFC04C040+((x)*0x001)) -#define MCF_INTC1_SWIACK MCF_REG08(0xFC04C0E0) -#define MCF_INTC1_L1IACK MCF_REG08(0xFC04C0E4) -#define MCF_INTC1_L2IACK MCF_REG08(0xFC04C0E8) -#define MCF_INTC1_L3IACK MCF_REG08(0xFC04C0EC) -#define MCF_INTC1_L4IACK MCF_REG08(0xFC04C0F0) -#define MCF_INTC1_L5IACK MCF_REG08(0xFC04C0F4) -#define MCF_INTC1_L6IACK MCF_REG08(0xFC04C0F8) -#define MCF_INTC1_L7IACK MCF_REG08(0xFC04C0FC) -#define MCF_INTC1_LIACK(x) MCF_REG08(0xFC04C0E4+((x)*0x004)) -#define MCF_INTC_IPRH(x) MCF_REG32(0xFC048000+((x)*0x4000)) -#define MCF_INTC_IPRL(x) MCF_REG32(0xFC048004+((x)*0x4000)) -#define MCF_INTC_IMRH(x) MCF_REG32(0xFC048008+((x)*0x4000)) -#define MCF_INTC_IMRL(x) MCF_REG32(0xFC04800C+((x)*0x4000)) -#define MCF_INTC_INTFRCH(x) MCF_REG32(0xFC048010+((x)*0x4000)) -#define MCF_INTC_INTFRCL(x) MCF_REG32(0xFC048014+((x)*0x4000)) -#define MCF_INTC_ICONFIG(x) MCF_REG16(0xFC04801A+((x)*0x4000)) -#define MCF_INTC_SIMR(x) MCF_REG08(0xFC04801C+((x)*0x4000)) -#define MCF_INTC_CIMR(x) MCF_REG08(0xFC04801D+((x)*0x4000)) -#define MCF_INTC_CLMASK(x) MCF_REG08(0xFC04801E+((x)*0x4000)) -#define MCF_INTC_SLMASK(x) MCF_REG08(0xFC04801F+((x)*0x4000)) -#define MCF_INTC_ICR0(x) MCF_REG08(0xFC048040+((x)*0x4000)) -#define MCF_INTC_ICR1(x) MCF_REG08(0xFC048041+((x)*0x4000)) -#define MCF_INTC_ICR2(x) MCF_REG08(0xFC048042+((x)*0x4000)) -#define MCF_INTC_ICR3(x) MCF_REG08(0xFC048043+((x)*0x4000)) -#define MCF_INTC_ICR4(x) MCF_REG08(0xFC048044+((x)*0x4000)) -#define MCF_INTC_ICR5(x) MCF_REG08(0xFC048045+((x)*0x4000)) -#define MCF_INTC_ICR6(x) MCF_REG08(0xFC048046+((x)*0x4000)) -#define MCF_INTC_ICR7(x) MCF_REG08(0xFC048047+((x)*0x4000)) -#define MCF_INTC_ICR8(x) MCF_REG08(0xFC048048+((x)*0x4000)) -#define MCF_INTC_ICR9(x) MCF_REG08(0xFC048049+((x)*0x4000)) -#define MCF_INTC_ICR10(x) MCF_REG08(0xFC04804A+((x)*0x4000)) -#define MCF_INTC_ICR11(x) MCF_REG08(0xFC04804B+((x)*0x4000)) -#define MCF_INTC_ICR12(x) MCF_REG08(0xFC04804C+((x)*0x4000)) -#define MCF_INTC_ICR13(x) MCF_REG08(0xFC04804D+((x)*0x4000)) -#define MCF_INTC_ICR14(x) MCF_REG08(0xFC04804E+((x)*0x4000)) -#define MCF_INTC_ICR15(x) MCF_REG08(0xFC04804F+((x)*0x4000)) -#define MCF_INTC_ICR16(x) MCF_REG08(0xFC048050+((x)*0x4000)) -#define MCF_INTC_ICR17(x) MCF_REG08(0xFC048051+((x)*0x4000)) -#define MCF_INTC_ICR18(x) MCF_REG08(0xFC048052+((x)*0x4000)) -#define MCF_INTC_ICR19(x) MCF_REG08(0xFC048053+((x)*0x4000)) -#define MCF_INTC_ICR20(x) MCF_REG08(0xFC048054+((x)*0x4000)) -#define MCF_INTC_ICR21(x) MCF_REG08(0xFC048055+((x)*0x4000)) -#define MCF_INTC_ICR22(x) MCF_REG08(0xFC048056+((x)*0x4000)) -#define MCF_INTC_ICR23(x) MCF_REG08(0xFC048057+((x)*0x4000)) -#define MCF_INTC_ICR24(x) MCF_REG08(0xFC048058+((x)*0x4000)) -#define MCF_INTC_ICR25(x) MCF_REG08(0xFC048059+((x)*0x4000)) -#define MCF_INTC_ICR26(x) MCF_REG08(0xFC04805A+((x)*0x4000)) -#define MCF_INTC_ICR27(x) MCF_REG08(0xFC04805B+((x)*0x4000)) -#define MCF_INTC_ICR28(x) MCF_REG08(0xFC04805C+((x)*0x4000)) -#define MCF_INTC_ICR29(x) MCF_REG08(0xFC04805D+((x)*0x4000)) -#define MCF_INTC_ICR30(x) MCF_REG08(0xFC04805E+((x)*0x4000)) -#define MCF_INTC_ICR31(x) MCF_REG08(0xFC04805F+((x)*0x4000)) -#define MCF_INTC_ICR32(x) MCF_REG08(0xFC048060+((x)*0x4000)) -#define MCF_INTC_ICR33(x) MCF_REG08(0xFC048061+((x)*0x4000)) -#define MCF_INTC_ICR34(x) MCF_REG08(0xFC048062+((x)*0x4000)) -#define MCF_INTC_ICR35(x) MCF_REG08(0xFC048063+((x)*0x4000)) -#define MCF_INTC_ICR36(x) MCF_REG08(0xFC048064+((x)*0x4000)) -#define MCF_INTC_ICR37(x) MCF_REG08(0xFC048065+((x)*0x4000)) -#define MCF_INTC_ICR38(x) MCF_REG08(0xFC048066+((x)*0x4000)) -#define MCF_INTC_ICR39(x) MCF_REG08(0xFC048067+((x)*0x4000)) -#define MCF_INTC_ICR40(x) MCF_REG08(0xFC048068+((x)*0x4000)) -#define MCF_INTC_ICR41(x) MCF_REG08(0xFC048069+((x)*0x4000)) -#define MCF_INTC_ICR42(x) MCF_REG08(0xFC04806A+((x)*0x4000)) -#define MCF_INTC_ICR43(x) MCF_REG08(0xFC04806B+((x)*0x4000)) -#define MCF_INTC_ICR44(x) MCF_REG08(0xFC04806C+((x)*0x4000)) -#define MCF_INTC_ICR45(x) MCF_REG08(0xFC04806D+((x)*0x4000)) -#define MCF_INTC_ICR46(x) MCF_REG08(0xFC04806E+((x)*0x4000)) -#define MCF_INTC_ICR47(x) MCF_REG08(0xFC04806F+((x)*0x4000)) -#define MCF_INTC_ICR48(x) MCF_REG08(0xFC048070+((x)*0x4000)) -#define MCF_INTC_ICR49(x) MCF_REG08(0xFC048071+((x)*0x4000)) -#define MCF_INTC_ICR50(x) MCF_REG08(0xFC048072+((x)*0x4000)) -#define MCF_INTC_ICR51(x) MCF_REG08(0xFC048073+((x)*0x4000)) -#define MCF_INTC_ICR52(x) MCF_REG08(0xFC048074+((x)*0x4000)) -#define MCF_INTC_ICR53(x) MCF_REG08(0xFC048075+((x)*0x4000)) -#define MCF_INTC_ICR54(x) MCF_REG08(0xFC048076+((x)*0x4000)) -#define MCF_INTC_ICR55(x) MCF_REG08(0xFC048077+((x)*0x4000)) -#define MCF_INTC_ICR56(x) MCF_REG08(0xFC048078+((x)*0x4000)) -#define MCF_INTC_ICR57(x) MCF_REG08(0xFC048079+((x)*0x4000)) -#define MCF_INTC_ICR58(x) MCF_REG08(0xFC04807A+((x)*0x4000)) -#define MCF_INTC_ICR59(x) MCF_REG08(0xFC04807B+((x)*0x4000)) -#define MCF_INTC_ICR60(x) MCF_REG08(0xFC04807C+((x)*0x4000)) -#define MCF_INTC_ICR61(x) MCF_REG08(0xFC04807D+((x)*0x4000)) -#define MCF_INTC_ICR62(x) MCF_REG08(0xFC04807E+((x)*0x4000)) -#define MCF_INTC_ICR63(x) MCF_REG08(0xFC04807F+((x)*0x4000)) -#define MCF_INTC_SWIACK(x) MCF_REG08(0xFC0480E0+((x)*0x4000)) -#define MCF_INTC_L1IACK(x) MCF_REG08(0xFC0480E4+((x)*0x4000)) -#define MCF_INTC_L2IACK(x) MCF_REG08(0xFC0480E8+((x)*0x4000)) -#define MCF_INTC_L3IACK(x) MCF_REG08(0xFC0480EC+((x)*0x4000)) -#define MCF_INTC_L4IACK(x) MCF_REG08(0xFC0480F0+((x)*0x4000)) -#define MCF_INTC_L5IACK(x) MCF_REG08(0xFC0480F4+((x)*0x4000)) -#define MCF_INTC_L6IACK(x) MCF_REG08(0xFC0480F8+((x)*0x4000)) -#define MCF_INTC_L7IACK(x) MCF_REG08(0xFC0480FC+((x)*0x4000)) - -/* Bit definitions and macros for MCF_INTC_IPRH */ -#define MCF_INTC_IPRH_INT32 (0x00000001) -#define MCF_INTC_IPRH_INT33 (0x00000002) -#define MCF_INTC_IPRH_INT34 (0x00000004) -#define MCF_INTC_IPRH_INT35 (0x00000008) -#define MCF_INTC_IPRH_INT36 (0x00000010) -#define MCF_INTC_IPRH_INT37 (0x00000020) -#define MCF_INTC_IPRH_INT38 (0x00000040) -#define MCF_INTC_IPRH_INT39 (0x00000080) -#define MCF_INTC_IPRH_INT40 (0x00000100) -#define MCF_INTC_IPRH_INT41 (0x00000200) -#define MCF_INTC_IPRH_INT42 (0x00000400) -#define MCF_INTC_IPRH_INT43 (0x00000800) -#define MCF_INTC_IPRH_INT44 (0x00001000) -#define MCF_INTC_IPRH_INT45 (0x00002000) -#define MCF_INTC_IPRH_INT46 (0x00004000) -#define MCF_INTC_IPRH_INT47 (0x00008000) -#define MCF_INTC_IPRH_INT48 (0x00010000) -#define MCF_INTC_IPRH_INT49 (0x00020000) -#define MCF_INTC_IPRH_INT50 (0x00040000) -#define MCF_INTC_IPRH_INT51 (0x00080000) -#define MCF_INTC_IPRH_INT52 (0x00100000) -#define MCF_INTC_IPRH_INT53 (0x00200000) -#define MCF_INTC_IPRH_INT54 (0x00400000) -#define MCF_INTC_IPRH_INT55 (0x00800000) -#define MCF_INTC_IPRH_INT56 (0x01000000) -#define MCF_INTC_IPRH_INT57 (0x02000000) -#define MCF_INTC_IPRH_INT58 (0x04000000) -#define MCF_INTC_IPRH_INT59 (0x08000000) -#define MCF_INTC_IPRH_INT60 (0x10000000) -#define MCF_INTC_IPRH_INT61 (0x20000000) -#define MCF_INTC_IPRH_INT62 (0x40000000) -#define MCF_INTC_IPRH_INT63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IPRL */ -#define MCF_INTC_IPRL_INT0 (0x00000001) -#define MCF_INTC_IPRL_INT1 (0x00000002) -#define MCF_INTC_IPRL_INT2 (0x00000004) -#define MCF_INTC_IPRL_INT3 (0x00000008) -#define MCF_INTC_IPRL_INT4 (0x00000010) -#define MCF_INTC_IPRL_INT5 (0x00000020) -#define MCF_INTC_IPRL_INT6 (0x00000040) -#define MCF_INTC_IPRL_INT7 (0x00000080) -#define MCF_INTC_IPRL_INT8 (0x00000100) -#define MCF_INTC_IPRL_INT9 (0x00000200) -#define MCF_INTC_IPRL_INT10 (0x00000400) -#define MCF_INTC_IPRL_INT11 (0x00000800) -#define MCF_INTC_IPRL_INT12 (0x00001000) -#define MCF_INTC_IPRL_INT13 (0x00002000) -#define MCF_INTC_IPRL_INT14 (0x00004000) -#define MCF_INTC_IPRL_INT15 (0x00008000) -#define MCF_INTC_IPRL_INT16 (0x00010000) -#define MCF_INTC_IPRL_INT17 (0x00020000) -#define MCF_INTC_IPRL_INT18 (0x00040000) -#define MCF_INTC_IPRL_INT19 (0x00080000) -#define MCF_INTC_IPRL_INT20 (0x00100000) -#define MCF_INTC_IPRL_INT21 (0x00200000) -#define MCF_INTC_IPRL_INT22 (0x00400000) -#define MCF_INTC_IPRL_INT23 (0x00800000) -#define MCF_INTC_IPRL_INT24 (0x01000000) -#define MCF_INTC_IPRL_INT25 (0x02000000) -#define MCF_INTC_IPRL_INT26 (0x04000000) -#define MCF_INTC_IPRL_INT27 (0x08000000) -#define MCF_INTC_IPRL_INT28 (0x10000000) -#define MCF_INTC_IPRL_INT29 (0x20000000) -#define MCF_INTC_IPRL_INT30 (0x40000000) -#define MCF_INTC_IPRL_INT31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRH */ -#define MCF_INTC_IMRH_INT_MASK32 (0x00000001) -#define MCF_INTC_IMRH_INT_MASK33 (0x00000002) -#define MCF_INTC_IMRH_INT_MASK34 (0x00000004) -#define MCF_INTC_IMRH_INT_MASK35 (0x00000008) -#define MCF_INTC_IMRH_INT_MASK36 (0x00000010) -#define MCF_INTC_IMRH_INT_MASK37 (0x00000020) -#define MCF_INTC_IMRH_INT_MASK38 (0x00000040) -#define MCF_INTC_IMRH_INT_MASK39 (0x00000080) -#define MCF_INTC_IMRH_INT_MASK40 (0x00000100) -#define MCF_INTC_IMRH_INT_MASK41 (0x00000200) -#define MCF_INTC_IMRH_INT_MASK42 (0x00000400) -#define MCF_INTC_IMRH_INT_MASK43 (0x00000800) -#define MCF_INTC_IMRH_INT_MASK44 (0x00001000) -#define MCF_INTC_IMRH_INT_MASK45 (0x00002000) -#define MCF_INTC_IMRH_INT_MASK46 (0x00004000) -#define MCF_INTC_IMRH_INT_MASK47 (0x00008000) -#define MCF_INTC_IMRH_INT_MASK48 (0x00010000) -#define MCF_INTC_IMRH_INT_MASK49 (0x00020000) -#define MCF_INTC_IMRH_INT_MASK50 (0x00040000) -#define MCF_INTC_IMRH_INT_MASK51 (0x00080000) -#define MCF_INTC_IMRH_INT_MASK52 (0x00100000) -#define MCF_INTC_IMRH_INT_MASK53 (0x00200000) -#define MCF_INTC_IMRH_INT_MASK54 (0x00400000) -#define MCF_INTC_IMRH_INT_MASK55 (0x00800000) -#define MCF_INTC_IMRH_INT_MASK56 (0x01000000) -#define MCF_INTC_IMRH_INT_MASK57 (0x02000000) -#define MCF_INTC_IMRH_INT_MASK58 (0x04000000) -#define MCF_INTC_IMRH_INT_MASK59 (0x08000000) -#define MCF_INTC_IMRH_INT_MASK60 (0x10000000) -#define MCF_INTC_IMRH_INT_MASK61 (0x20000000) -#define MCF_INTC_IMRH_INT_MASK62 (0x40000000) -#define MCF_INTC_IMRH_INT_MASK63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_IMRL */ -#define MCF_INTC_IMRL_INT_MASK0 (0x00000001) -#define MCF_INTC_IMRL_INT_MASK1 (0x00000002) -#define MCF_INTC_IMRL_INT_MASK2 (0x00000004) -#define MCF_INTC_IMRL_INT_MASK3 (0x00000008) -#define MCF_INTC_IMRL_INT_MASK4 (0x00000010) -#define MCF_INTC_IMRL_INT_MASK5 (0x00000020) -#define MCF_INTC_IMRL_INT_MASK6 (0x00000040) -#define MCF_INTC_IMRL_INT_MASK7 (0x00000080) -#define MCF_INTC_IMRL_INT_MASK8 (0x00000100) -#define MCF_INTC_IMRL_INT_MASK9 (0x00000200) -#define MCF_INTC_IMRL_INT_MASK10 (0x00000400) -#define MCF_INTC_IMRL_INT_MASK11 (0x00000800) -#define MCF_INTC_IMRL_INT_MASK12 (0x00001000) -#define MCF_INTC_IMRL_INT_MASK13 (0x00002000) -#define MCF_INTC_IMRL_INT_MASK14 (0x00004000) -#define MCF_INTC_IMRL_INT_MASK15 (0x00008000) -#define MCF_INTC_IMRL_INT_MASK16 (0x00010000) -#define MCF_INTC_IMRL_INT_MASK17 (0x00020000) -#define MCF_INTC_IMRL_INT_MASK18 (0x00040000) -#define MCF_INTC_IMRL_INT_MASK19 (0x00080000) -#define MCF_INTC_IMRL_INT_MASK20 (0x00100000) -#define MCF_INTC_IMRL_INT_MASK21 (0x00200000) -#define MCF_INTC_IMRL_INT_MASK22 (0x00400000) -#define MCF_INTC_IMRL_INT_MASK23 (0x00800000) -#define MCF_INTC_IMRL_INT_MASK24 (0x01000000) -#define MCF_INTC_IMRL_INT_MASK25 (0x02000000) -#define MCF_INTC_IMRL_INT_MASK26 (0x04000000) -#define MCF_INTC_IMRL_INT_MASK27 (0x08000000) -#define MCF_INTC_IMRL_INT_MASK28 (0x10000000) -#define MCF_INTC_IMRL_INT_MASK29 (0x20000000) -#define MCF_INTC_IMRL_INT_MASK30 (0x40000000) -#define MCF_INTC_IMRL_INT_MASK31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCH */ -#define MCF_INTC_INTFRCH_INTFRC32 (0x00000001) -#define MCF_INTC_INTFRCH_INTFRC33 (0x00000002) -#define MCF_INTC_INTFRCH_INTFRC34 (0x00000004) -#define MCF_INTC_INTFRCH_INTFRC35 (0x00000008) -#define MCF_INTC_INTFRCH_INTFRC36 (0x00000010) -#define MCF_INTC_INTFRCH_INTFRC37 (0x00000020) -#define MCF_INTC_INTFRCH_INTFRC38 (0x00000040) -#define MCF_INTC_INTFRCH_INTFRC39 (0x00000080) -#define MCF_INTC_INTFRCH_INTFRC40 (0x00000100) -#define MCF_INTC_INTFRCH_INTFRC41 (0x00000200) -#define MCF_INTC_INTFRCH_INTFRC42 (0x00000400) -#define MCF_INTC_INTFRCH_INTFRC43 (0x00000800) -#define MCF_INTC_INTFRCH_INTFRC44 (0x00001000) -#define MCF_INTC_INTFRCH_INTFRC45 (0x00002000) -#define MCF_INTC_INTFRCH_INTFRC46 (0x00004000) -#define MCF_INTC_INTFRCH_INTFRC47 (0x00008000) -#define MCF_INTC_INTFRCH_INTFRC48 (0x00010000) -#define MCF_INTC_INTFRCH_INTFRC49 (0x00020000) -#define MCF_INTC_INTFRCH_INTFRC50 (0x00040000) -#define MCF_INTC_INTFRCH_INTFRC51 (0x00080000) -#define MCF_INTC_INTFRCH_INTFRC52 (0x00100000) -#define MCF_INTC_INTFRCH_INTFRC53 (0x00200000) -#define MCF_INTC_INTFRCH_INTFRC54 (0x00400000) -#define MCF_INTC_INTFRCH_INTFRC55 (0x00800000) -#define MCF_INTC_INTFRCH_INTFRC56 (0x01000000) -#define MCF_INTC_INTFRCH_INTFRC57 (0x02000000) -#define MCF_INTC_INTFRCH_INTFRC58 (0x04000000) -#define MCF_INTC_INTFRCH_INTFRC59 (0x08000000) -#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000) -#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000) -#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000) -#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_INTFRCL */ -#define MCF_INTC_INTFRCL_INTFRC0 (0x00000001) -#define MCF_INTC_INTFRCL_INTFRC1 (0x00000002) -#define MCF_INTC_INTFRCL_INTFRC2 (0x00000004) -#define MCF_INTC_INTFRCL_INTFRC3 (0x00000008) -#define MCF_INTC_INTFRCL_INTFRC4 (0x00000010) -#define MCF_INTC_INTFRCL_INTFRC5 (0x00000020) -#define MCF_INTC_INTFRCL_INTFRC6 (0x00000040) -#define MCF_INTC_INTFRCL_INTFRC7 (0x00000080) -#define MCF_INTC_INTFRCL_INTFRC8 (0x00000100) -#define MCF_INTC_INTFRCL_INTFRC9 (0x00000200) -#define MCF_INTC_INTFRCL_INTFRC10 (0x00000400) -#define MCF_INTC_INTFRCL_INTFRC11 (0x00000800) -#define MCF_INTC_INTFRCL_INTFRC12 (0x00001000) -#define MCF_INTC_INTFRCL_INTFRC13 (0x00002000) -#define MCF_INTC_INTFRCL_INTFRC14 (0x00004000) -#define MCF_INTC_INTFRCL_INTFRC15 (0x00008000) -#define MCF_INTC_INTFRCL_INTFRC16 (0x00010000) -#define MCF_INTC_INTFRCL_INTFRC17 (0x00020000) -#define MCF_INTC_INTFRCL_INTFRC18 (0x00040000) -#define MCF_INTC_INTFRCL_INTFRC19 (0x00080000) -#define MCF_INTC_INTFRCL_INTFRC20 (0x00100000) -#define MCF_INTC_INTFRCL_INTFRC21 (0x00200000) -#define MCF_INTC_INTFRCL_INTFRC22 (0x00400000) -#define MCF_INTC_INTFRCL_INTFRC23 (0x00800000) -#define MCF_INTC_INTFRCL_INTFRC24 (0x01000000) -#define MCF_INTC_INTFRCL_INTFRC25 (0x02000000) -#define MCF_INTC_INTFRCL_INTFRC26 (0x04000000) -#define MCF_INTC_INTFRCL_INTFRC27 (0x08000000) -#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000) -#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000) -#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000) -#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000) - -/* Bit definitions and macros for MCF_INTC_ICONFIG */ -#define MCF_INTC_ICONFIG_EMASK (0x0020) -#define MCF_INTC_ICONFIG_ELVLPRI1 (0x0200) -#define MCF_INTC_ICONFIG_ELVLPRI2 (0x0400) -#define MCF_INTC_ICONFIG_ELVLPRI3 (0x0800) -#define MCF_INTC_ICONFIG_ELVLPRI4 (0x1000) -#define MCF_INTC_ICONFIG_ELVLPRI5 (0x2000) -#define MCF_INTC_ICONFIG_ELVLPRI6 (0x4000) -#define MCF_INTC_ICONFIG_ELVLPRI7 (0x8000) - -/* Bit definitions and macros for MCF_INTC_SIMR */ -#define MCF_INTC_SIMR_SIMR(x) (((x)&0x7F)<<0) - -/* Bit definitions and macros for MCF_INTC_CIMR */ -#define MCF_INTC_CIMR_CIMR(x) (((x)&0x7F)<<0) - -/* Bit definitions and macros for MCF_INTC_CLMASK */ -#define MCF_INTC_CLMASK_CLMASK(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_INTC_SLMASK */ -#define MCF_INTC_SLMASK_SLMASK(x) (((x)&0x0F)<<0) - -/* Bit definitions and macros for MCF_INTC_ICR */ -#define MCF_INTC_ICR_IL(x) (((x)&0x07)<<0) - -/* Bit definitions and macros for MCF_INTC_SWIACK */ -#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_INTC_LIACK */ -#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0) - -/********************************************************************/ -/********************************************************************* -* -* LCD Controller (LCDC) -* -*********************************************************************/ - -/* Register read/write macros */ -#define MCF_LCDC_LSSAR MCF_REG32(0xFC0AC000) -#define MCF_LCDC_LSR MCF_REG32(0xFC0AC004) -#define MCF_LCDC_LVPWR MCF_REG32(0xFC0AC008) -#define MCF_LCDC_LCPR MCF_REG32(0xFC0AC00C) -#define MCF_LCDC_LCWHBR MCF_REG32(0xFC0AC010) -#define MCF_LCDC_LCCMR MCF_REG32(0xFC0AC014) -#define MCF_LCDC_LPCR MCF_REG32(0xFC0AC018) -#define MCF_LCDC_LHCR MCF_REG32(0xFC0AC01C) -#define MCF_LCDC_LVCR MCF_REG32(0xFC0AC020) -#define MCF_LCDC_LPOR MCF_REG32(0xFC0AC024) -#define MCF_LCDC_LSCR MCF_REG32(0xFC0AC028) -#define MCF_LCDC_LPCCR MCF_REG32(0xFC0AC02C) -#define MCF_LCDC_LDCR MCF_REG32(0xFC0AC030) -#define MCF_LCDC_LRMCR MCF_REG32(0xFC0AC034) -#define MCF_LCDC_LICR MCF_REG32(0xFC0AC038) -#define MCF_LCDC_LIER MCF_REG32(0xFC0AC03C) -#define MCF_LCDC_LISR MCF_REG32(0xFC0AC040) -#define MCF_LCDC_LGWSAR MCF_REG32(0xFC0AC050) -#define MCF_LCDC_LGWSR MCF_REG32(0xFC0AC054) -#define MCF_LCDC_LGWVPWR MCF_REG32(0xFC0AC058) -#define MCF_LCDC_LGWPOR MCF_REG32(0xFC0AC05C) -#define MCF_LCDC_LGWPR MCF_REG32(0xFC0AC060) -#define MCF_LCDC_LGWCR MCF_REG32(0xFC0AC064) -#define MCF_LCDC_LGWDCR MCF_REG32(0xFC0AC068) -#define MCF_LCDC_BPLUT_BASE MCF_REG32(0xFC0AC800) -#define MCF_LCDC_GWLUT_BASE MCF_REG32(0xFC0ACC00) - -/* Bit definitions and macros for MCF_LCDC_LSSAR */ -#define MCF_LCDC_LSSAR_SSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_LCDC_LSR */ -#define MCF_LCDC_LSR_YMAX(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LSR_XMAX(x) (((x)&0x0000003F)<<20) - -/* Bit definitions and macros for MCF_LCDC_LVPWR */ -#define MCF_LCDC_LVPWR_VPW(x) (((x)&0x000003FF)<<0) - -/* Bit definitions and macros for MCF_LCDC_LCPR */ -#define MCF_LCDC_LCPR_CYP(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LCPR_CXP(x) (((x)&0x000003FF)<<16) -#define MCF_LCDC_LCPR_OP (0x10000000) -#define MCF_LCDC_LCPR_CC(x) (((x)&0x00000003)<<30) -#define MCF_LCDC_LCPR_CC_TRANSPARENT (0x00000000) -#define MCF_LCDC_LCPR_CC_OR (0x40000000) -#define MCF_LCDC_LCPR_CC_XOR (0x80000000) -#define MCF_LCDC_LCPR_CC_AND (0xC0000000) -#define MCF_LCDC_LCPR_OP_ON (0x10000000) -#define MCF_LCDC_LCPR_OP_OFF (0x00000000) - -/* Bit definitions and macros for MCF_LCDC_LCWHBR */ -#define MCF_LCDC_LCWHBR_BD(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LCWHBR_CH(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LCWHBR_CW(x) (((x)&0x0000001F)<<24) -#define MCF_LCDC_LCWHBR_BK_EN (0x80000000) -#define MCF_LCDC_LCWHBR_BK_EN_ON (0x80000000) -#define MCF_LCDC_LCWHBR_BK_EN_OFF (0x00000000) - -/* Bit definitions and macros for MCF_LCDC_LCCMR */ -#define MCF_LCDC_LCCMR_CUR_COL_B(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LCCMR_CUR_COL_G(x) (((x)&0x0000003F)<<6) -#define MCF_LCDC_LCCMR_CUR_COL_R(x) (((x)&0x0000003F)<<12) - -/* Bit definitions and macros for MCF_LCDC_LPCR */ -#define MCF_LCDC_LPCR_PCD(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LPCR_SHARP (0x00000040) -#define MCF_LCDC_LPCR_SCLKSEL (0x00000080) -#define MCF_LCDC_LPCR_ACD(x) (((x)&0x0000007F)<<8) -#define MCF_LCDC_LPCR_ACDSEL (0x00008000) -#define MCF_LCDC_LPCR_REV_VS (0x00010000) -#define MCF_LCDC_LPCR_SWAP_SEL (0x00020000) -#define MCF_LCDC_LPCR_ENDSEL (0x00040000) -#define MCF_LCDC_LPCR_SCLKIDLE (0x00080000) -#define MCF_LCDC_LPCR_OEPOL (0x00100000) -#define MCF_LCDC_LPCR_CLKPOL (0x00200000) -#define MCF_LCDC_LPCR_LPPOL (0x00400000) -#define MCF_LCDC_LPCR_FLM (0x00800000) -#define MCF_LCDC_LPCR_PIXPOL (0x01000000) -#define MCF_LCDC_LPCR_BPIX(x) (((x)&0x00000007)<<25) -#define MCF_LCDC_LPCR_PBSIZ(x) (((x)&0x00000003)<<28) -#define MCF_LCDC_LPCR_COLOR (0x40000000) -#define MCF_LCDC_LPCR_TFT (0x80000000) -#define MCF_LCDC_LPCR_MODE_MONOCGROME (0x00000000) -#define MCF_LCDC_LPCR_MODE_CSTN (0x40000000) -#define MCF_LCDC_LPCR_MODE_TFT (0xC0000000) -#define MCF_LCDC_LPCR_PBSIZ_1 (0x00000000) -#define MCF_LCDC_LPCR_PBSIZ_2 (0x10000000) -#define MCF_LCDC_LPCR_PBSIZ_4 (0x20000000) -#define MCF_LCDC_LPCR_PBSIZ_8 (0x30000000) -#define MCF_LCDC_LPCR_BPIX_1bpp (0x00000000) -#define MCF_LCDC_LPCR_BPIX_2bpp (0x02000000) -#define MCF_LCDC_LPCR_BPIX_4bpp (0x04000000) -#define MCF_LCDC_LPCR_BPIX_8bpp (0x06000000) -#define MCF_LCDC_LPCR_BPIX_12bpp (0x08000000) -#define MCF_LCDC_LPCR_BPIX_16bpp (0x0A000000) -#define MCF_LCDC_LPCR_BPIX_18bpp (0x0C000000) - -#define MCF_LCDC_LPCR_PANEL_TYPE(x) (((x)&0x00000003)<<30) - -/* Bit definitions and macros for MCF_LCDC_LHCR */ -#define MCF_LCDC_LHCR_H_WAIT_2(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LHCR_H_WAIT_1(x) (((x)&0x000000FF)<<8) -#define MCF_LCDC_LHCR_H_WIDTH(x) (((x)&0x0000003F)<<26) - -/* Bit definitions and macros for MCF_LCDC_LVCR */ -#define MCF_LCDC_LVCR_V_WAIT_2(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LVCR_V_WAIT_1(x) (((x)&0x000000FF)<<8) -#define MCF_LCDC_LVCR_V_WIDTH(x) (((x)&0x0000003F)<<26) - -/* Bit definitions and macros for MCF_LCDC_LPOR */ -#define MCF_LCDC_LPOR_POS(x) (((x)&0x0000001F)<<0) - -/* Bit definitions and macros for MCF_LCDC_LPCCR */ -#define MCF_LCDC_LPCCR_PW(x) (((x)&0x000000FF)<<0) -#define MCF_LCDC_LPCCR_CC_EN (0x00000100) -#define MCF_LCDC_LPCCR_SCR(x) (((x)&0x00000003)<<9) -#define MCF_LCDC_LPCCR_LDMSK (0x00008000) -#define MCF_LCDC_LPCCR_CLS_HI_WIDTH(x) (((x)&0x000001FF)<<16) -#define MCF_LCDC_LPCCR_SCR_LINEPULSE (0x00000000) -#define MCF_LCDC_LPCCR_SCR_PIXELCLK (0x00002000) -#define MCF_LCDC_LPCCR_SCR_LCDCLOCK (0x00004000) - -/* Bit definitions and macros for MCF_LCDC_LDCR */ -#define MCF_LCDC_LDCR_TM(x) (((x)&0x0000001F)<<0) -#define MCF_LCDC_LDCR_HM(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LDCR_BURST (0x80000000) - -/* Bit definitions and macros for MCF_LCDC_LRMCR */ -#define MCF_LCDC_LRMCR_SEL_REF (0x00000001) - -/* Bit definitions and macros for MCF_LCDC_LICR */ -#define MCF_LCDC_LICR_INTCON (0x00000001) -#define MCF_LCDC_LICR_INTSYN (0x00000004) -#define MCF_LCDC_LICR_GW_INT_CON (0x00000010) - -/* Bit definitions and macros for MCF_LCDC_LIER */ -#define MCF_LCDC_LIER_BOF_EN (0x00000001) -#define MCF_LCDC_LIER_EOF_EN (0x00000002) -#define MCF_LCDC_LIER_ERR_RES_EN (0x00000004) -#define MCF_LCDC_LIER_UDR_ERR_EN (0x00000008) -#define MCF_LCDC_LIER_GW_BOF_EN (0x00000010) -#define MCF_LCDC_LIER_GW_EOF_EN (0x00000020) -#define MCF_LCDC_LIER_GW_ERR_RES_EN (0x00000040) -#define MCF_LCDC_LIER_GW_UDR_ERR_EN (0x00000080) - -/* Bit definitions and macros for MCF_LCDC_LISR */ -#define MCF_LCDC_LISR_BOF (0x00000001) -#define MCF_LCDC_LISR_EOF (0x00000002) -#define MCF_LCDC_LISR_ERR_RES (0x00000004) -#define MCF_LCDC_LISR_UDR_ERR (0x00000008) -#define MCF_LCDC_LISR_GW_BOF (0x00000010) -#define MCF_LCDC_LISR_GW_EOF (0x00000020) -#define MCF_LCDC_LISR_GW_ERR_RES (0x00000040) -#define MCF_LCDC_LISR_GW_UDR_ERR (0x00000080) - -/* Bit definitions and macros for MCF_LCDC_LGWSAR */ -#define MCF_LCDC_LGWSAR_GWSA(x) (((x)&0x3FFFFFFF)<<2) - -/* Bit definitions and macros for MCF_LCDC_LGWSR */ -#define MCF_LCDC_LGWSR_GWH(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LGWSR_GWW(x) (((x)&0x0000003F)<<20) - -/* Bit definitions and macros for MCF_LCDC_LGWVPWR */ -#define MCF_LCDC_LGWVPWR_GWVPW(x) (((x)&0x000003FF)<<0) - -/* Bit definitions and macros for MCF_LCDC_LGWPOR */ -#define MCF_LCDC_LGWPOR_GWPO(x) (((x)&0x0000001F)<<0) - -/* Bit definitions and macros for MCF_LCDC_LGWPR */ -#define MCF_LCDC_LGWPR_GWYP(x) (((x)&0x000003FF)<<0) -#define MCF_LCDC_LGWPR_GWXP(x) (((x)&0x000003FF)<<16) - -/* Bit definitions and macros for MCF_LCDC_LGWCR */ -#define MCF_LCDC_LGWCR_GWCKB(x) (((x)&0x0000003F)<<0) -#define MCF_LCDC_LGWCR_GWCKG(x) (((x)&0x0000003F)<<6) -#define MCF_LCDC_LGWCR_GWCKR(x) (((x)&0x0000003F)<<12) -#define MCF_LCDC_LGWCR_GW_RVS (0x00200000) -#define MCF_LCDC_LGWCR_GWE (0x00400000) -#define MCF_LCDC_LGWCR_GWCKE (0x00800000) -#define MCF_LCDC_LGWCR_GWAV(x) (((x)&0x000000FF)<<24) - -/* Bit definitions and macros for MCF_LCDC_LGWDCR */ -#define MCF_LCDC_LGWDCR_GWTM(x) (((x)&0x0000001F)<<0) -#define MCF_LCDC_LGWDCR_GWHM(x) (((x)&0x0000001F)<<16) -#define MCF_LCDC_LGWDCR_GWBT (0x80000000) - -/* Bit definitions and macros for MCF_LCDC_LSCR */ -#define MCF_LCDC_LSCR_PS_RISE_DELAY(x) (((x)&0x0000003F)<<26) -#define MCF_LCDC_LSCR_CLS_RISE_DELAY(x) (((x)&0x000000FF)<<16) -#define MCF_LCDC_LSCR_REV_TOGGLE_DELAY(x) (((x)&0x0000000F)<<8) -#define MCF_LCDC_LSCR_GRAY_2(x) (((x)&0x0000000F)<<4) -#define MCF_LCDC_LSCR_GRAY_1(x) (((x)&0x0000000F)<<0) - -/* Bit definitions and macros for MCF_LCDC_BPLUT_BASE */ -#define MCF_LCDC_BPLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/* Bit definitions and macros for MCF_LCDC_GWLUT_BASE */ -#define MCF_LCDC_GWLUT_BASE_BASE(x) (((x)&0xFFFFFFFF)<<0) - -/********************************************************************* - * - * Phase Locked Loop (PLL) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_PLL_PODR MCF_REG08(0xFC0C0000) -#define MCF_PLL_PLLCR MCF_REG08(0xFC0C0004) -#define MCF_PLL_PMDR MCF_REG08(0xFC0C0008) -#define MCF_PLL_PFDR MCF_REG08(0xFC0C000C) - -/* Bit definitions and macros for MCF_PLL_PODR */ -#define MCF_PLL_PODR_BUSDIV(x) (((x)&0x0F)<<0) -#define MCF_PLL_PODR_CPUDIV(x) (((x)&0x0F)<<4) - -/* Bit definitions and macros for MCF_PLL_PLLCR */ -#define MCF_PLL_PLLCR_DITHDEV(x) (((x)&0x07)<<0) -#define MCF_PLL_PLLCR_DITHEN (0x80) - -/* Bit definitions and macros for MCF_PLL_PMDR */ -#define MCF_PLL_PMDR_MODDIV(x) (((x)&0xFF)<<0) - -/* Bit definitions and macros for MCF_PLL_PFDR */ -#define MCF_PLL_PFDR_MFD(x) (((x)&0xFF)<<0) - -/********************************************************************* - * - * System Control Module Registers (SCM) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_SCM_MPR MCF_REG32(0xFC000000) -#define MCF_SCM_PACRA MCF_REG32(0xFC000020) -#define MCF_SCM_PACRB MCF_REG32(0xFC000024) -#define MCF_SCM_PACRC MCF_REG32(0xFC000028) -#define MCF_SCM_PACRD MCF_REG32(0xFC00002C) -#define MCF_SCM_PACRE MCF_REG32(0xFC000040) -#define MCF_SCM_PACRF MCF_REG32(0xFC000044) - -#define MCF_SCM_BCR MCF_REG32(0xFC040024) - -/********************************************************************* - * - * SDRAM Controller (SDRAMC) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_SDRAMC_SDMR MCF_REG32(0xFC0B8000) -#define MCF_SDRAMC_SDCR MCF_REG32(0xFC0B8004) -#define MCF_SDRAMC_SDCFG1 MCF_REG32(0xFC0B8008) -#define MCF_SDRAMC_SDCFG2 MCF_REG32(0xFC0B800C) -#define MCF_SDRAMC_LIMP_FIX MCF_REG32(0xFC0B8080) -#define MCF_SDRAMC_SDDS MCF_REG32(0xFC0B8100) -#define MCF_SDRAMC_SDCS0 MCF_REG32(0xFC0B8110) -#define MCF_SDRAMC_SDCS1 MCF_REG32(0xFC0B8114) -#define MCF_SDRAMC_SDCS2 MCF_REG32(0xFC0B8118) -#define MCF_SDRAMC_SDCS3 MCF_REG32(0xFC0B811C) -#define MCF_SDRAMC_SDCS(x) MCF_REG32(0xFC0B8110+((x)*0x004)) - -/* Bit definitions and macros for MCF_SDRAMC_SDMR */ -#define MCF_SDRAMC_SDMR_CMD (0x00010000) -#define MCF_SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) -#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x00000003)<<30) -#define MCF_SDRAMC_SDMR_BNKAD_LMR (0x00000000) -#define MCF_SDRAMC_SDMR_BNKAD_LEMR (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCR */ -#define MCF_SDRAMC_SDCR_IPALL (0x00000002) -#define MCF_SDRAMC_SDCR_IREF (0x00000004) -#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCR_PS(x) (((x)&0x00000003)<<12) -#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x0000003F)<<16) -#define MCF_SDRAMC_SDCR_OE_RULE (0x00400000) -#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x00000003)<<24) -#define MCF_SDRAMC_SDCR_REF (0x10000000) -#define MCF_SDRAMC_SDCR_DDR (0x20000000) -#define MCF_SDRAMC_SDCR_CKE (0x40000000) -#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000) -#define MCF_SDRAMC_SDCR_PS_16 (0x00002000) -#define MCF_SDRAMC_SDCR_PS_32 (0x00000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */ -#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x00000007)<<4) -#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) -#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) -#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) -#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x00000007)<<24) -#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0x0000000F)<<28) - -/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */ -#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) -#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0x0000000F)<<20) -#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0x0000000F)<<24) -#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0x0000000F)<<28) - -/* Device Errata - LIMP mode work around */ -#define MCF_SDRAMC_REFRESH (0x40000000) - -/* Bit definitions and macros for MCF_SDRAMC_SDDS */ -#define MCF_SDRAMC_SDDS_SB_D(x) (((x)&0x00000003)<<0) -#define MCF_SDRAMC_SDDS_SB_S(x) (((x)&0x00000003)<<2) -#define MCF_SDRAMC_SDDS_SB_A(x) (((x)&0x00000003)<<4) -#define MCF_SDRAMC_SDDS_SB_C(x) (((x)&0x00000003)<<6) -#define MCF_SDRAMC_SDDS_SB_E(x) (((x)&0x00000003)<<8) - -/* Bit definitions and macros for MCF_SDRAMC_SDCS */ -#define MCF_SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)<<0) -#define MCF_SDRAMC_SDCS_BASE(x) (((x)&0x00000FFF)<<20) -#define MCF_SDRAMC_SDCS_BA(x) ((x)&0xFFF00000) -#define MCF_SDRAMC_SDCS_CSSZ_DIABLE (0x00000000) -#define MCF_SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013) -#define MCF_SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014) -#define MCF_SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015) -#define MCF_SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016) -#define MCF_SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017) -#define MCF_SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018) -#define MCF_SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019) -#define MCF_SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A) -#define MCF_SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B) -#define MCF_SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C) -#define MCF_SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D) -#define MCF_SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E) -#define MCF_SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F) - -/********************************************************************* - * - * FlexCAN module registers - * - *********************************************************************/ -#define MCF_FLEXCAN_BASEADDR(x) (0xFC020000+(x)*0x0800) -#define MCF_FLEXCAN_CANMCR(x) MCF_REG32(0xFC020000+(x)*0x0800+0x00) -#define MCF_FLEXCAN_CANCTRL(x) MCF_REG32(0xFC020000+(x)*0x0800+0x04) -#define MCF_FLEXCAN_TIMER(x) MCF_REG32(0xFC020000+(x)*0x0800+0x08) -#define MCF_FLEXCAN_RXGMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x10) -#define MCF_FLEXCAN_RX14MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x14) -#define MCF_FLEXCAN_RX15MASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x18) -#define MCF_FLEXCAN_ERRCNT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x1C) -#define MCF_FLEXCAN_ERRSTAT(x) MCF_REG32(0xFC020000+(x)*0x0800+0x20) -#define MCF_FLEXCAN_IMASK(x) MCF_REG32(0xFC020000+(x)*0x0800+0x28) -#define MCF_FLEXCAN_IFLAG(x) MCF_REG32(0xFC020000+(x)*0x0800+0x30) - -#define MCF_FLEXCAN_MB_CNT(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x0) -#define MCF_FLEXCAN_MB_ID(x,y) MCF_REG32(0xFC020080+(x)*0x0800+(y)*0x10+0x4) -#define MCF_FLEXCAN_MB_DB(x,y,z) MCF_REG08(0xFC020080+(x)*0x0800+(y)*0x10+0x8+(z)*0x1) - -/* - * FlexCAN Module Configuration Register - */ -#define CANMCR_MDIS (0x80000000) -#define CANMCR_FRZ (0x40000000) -#define CANMCR_HALT (0x10000000) -#define CANMCR_SOFTRST (0x02000000) -#define CANMCR_FRZACK (0x01000000) -#define CANMCR_SUPV (0x00800000) -#define CANMCR_MAXMB(x) ((x)&0x0F) - -/* - * FlexCAN Control Register - */ -#define CANCTRL_PRESDIV(x) (((x)&0xFF)<<24) -#define CANCTRL_RJW(x) (((x)&0x03)<<22) -#define CANCTRL_PSEG1(x) (((x)&0x07)<<19) -#define CANCTRL_PSEG2(x) (((x)&0x07)<<16) -#define CANCTRL_BOFFMSK (0x00008000) -#define CANCTRL_ERRMSK (0x00004000) -#define CANCTRL_CLKSRC (0x00002000) -#define CANCTRL_LPB (0x00001000) -#define CANCTRL_SAMP (0x00000080) -#define CANCTRL_BOFFREC (0x00000040) -#define CANCTRL_TSYNC (0x00000020) -#define CANCTRL_LBUF (0x00000010) -#define CANCTRL_LOM (0x00000008) -#define CANCTRL_PROPSEG(x) ((x)&0x07) - -/* - * FlexCAN Error Counter Register - */ -#define ERRCNT_RXECTR(x) (((x)&0xFF)<<8) -#define ERRCNT_TXECTR(x) ((x)&0xFF) - -/* - * FlexCAN Error and Status Register - */ -#define ERRSTAT_BITERR(x) (((x)&0x03)<<14) -#define ERRSTAT_ACKERR (0x00002000) -#define ERRSTAT_CRCERR (0x00001000) -#define ERRSTAT_FRMERR (0x00000800) -#define ERRSTAT_STFERR (0x00000400) -#define ERRSTAT_TXWRN (0x00000200) -#define ERRSTAT_RXWRN (0x00000100) -#define ERRSTAT_IDLE (0x00000080) -#define ERRSTAT_TXRX (0x00000040) -#define ERRSTAT_FLTCONF(x) (((x)&0x03)<<4) -#define ERRSTAT_BOFFINT (0x00000004) -#define ERRSTAT_ERRINT (0x00000002) - -/* - * Interrupt Mask Register - */ -#define IMASK_BUF15M (0x8000) -#define IMASK_BUF14M (0x4000) -#define IMASK_BUF13M (0x2000) -#define IMASK_BUF12M (0x1000) -#define IMASK_BUF11M (0x0800) -#define IMASK_BUF10M (0x0400) -#define IMASK_BUF9M (0x0200) -#define IMASK_BUF8M (0x0100) -#define IMASK_BUF7M (0x0080) -#define IMASK_BUF6M (0x0040) -#define IMASK_BUF5M (0x0020) -#define IMASK_BUF4M (0x0010) -#define IMASK_BUF3M (0x0008) -#define IMASK_BUF2M (0x0004) -#define IMASK_BUF1M (0x0002) -#define IMASK_BUF0M (0x0001) -#define IMASK_BUFnM(x) (0x1<<(x)) -#define IMASK_BUFF_ENABLE_ALL (0x1111) -#define IMASK_BUFF_DISABLE_ALL (0x0000) - -/* - * Interrupt Flag Register - */ -#define IFLAG_BUF15M (0x8000) -#define IFLAG_BUF14M (0x4000) -#define IFLAG_BUF13M (0x2000) -#define IFLAG_BUF12M (0x1000) -#define IFLAG_BUF11M (0x0800) -#define IFLAG_BUF10M (0x0400) -#define IFLAG_BUF9M (0x0200) -#define IFLAG_BUF8M (0x0100) -#define IFLAG_BUF7M (0x0080) -#define IFLAG_BUF6M (0x0040) -#define IFLAG_BUF5M (0x0020) -#define IFLAG_BUF4M (0x0010) -#define IFLAG_BUF3M (0x0008) -#define IFLAG_BUF2M (0x0004) -#define IFLAG_BUF1M (0x0002) -#define IFLAG_BUF0M (0x0001) -#define IFLAG_BUFF_SET_ALL (0xFFFF) -#define IFLAG_BUFF_CLEAR_ALL (0x0000) -#define IFLAG_BUFnM(x) (0x1<<(x)) - -/* - * Message Buffers - */ -#define MB_CNT_CODE(x) (((x)&0x0F)<<24) -#define MB_CNT_SRR (0x00400000) -#define MB_CNT_IDE (0x00200000) -#define MB_CNT_RTR (0x00100000) -#define MB_CNT_LENGTH(x) (((x)&0x0F)<<16) -#define MB_CNT_TIMESTAMP(x) ((x)&0xFFFF) -#define MB_ID_STD(x) (((x)&0x07FF)<<18) -#define MB_ID_EXT(x) ((x)&0x3FFFF) - -/********************************************************************* - * - * Edge Port Module (EPORT) - * - *********************************************************************/ - -/* Register read/write macros */ -#define MCF_EPORT_EPPAR MCF_REG16(0xFC094000) -#define MCF_EPORT_EPDDR MCF_REG08(0xFC094002) -#define MCF_EPORT_EPIER MCF_REG08(0xFC094003) -#define MCF_EPORT_EPDR MCF_REG08(0xFC094004) -#define MCF_EPORT_EPPDR MCF_REG08(0xFC094005) -#define MCF_EPORT_EPFR MCF_REG08(0xFC094006) - -/* Bit definitions and macros for MCF_EPORT_EPPAR */ -#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2) -#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4) -#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6) -#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8) -#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10) -#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12) -#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14) -#define MCF_EPORT_EPPAR_LEVEL (0) -#define MCF_EPORT_EPPAR_RISING (1) -#define MCF_EPORT_EPPAR_FALLING (2) -#define MCF_EPORT_EPPAR_BOTH (3) -#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000) -#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000) -#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000) -#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000) -#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000) -#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000) -#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA5_RISING (0x0400) -#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x0800) -#define MCF_EPORT_EPPAR_EPPA5_BOTH (0x0C00) -#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA4_RISING (0x0100) -#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x0200) -#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x0300) -#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA3_RISING (0x0040) -#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x0080) -#define MCF_EPORT_EPPAR_EPPA3_BOTH (0x00C0) -#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA2_RISING (0x0010) -#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x0020) -#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x0030) -#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0x0000) -#define MCF_EPORT_EPPAR_EPPA1_RISING (0x0004) -#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x0008) -#define MCF_EPORT_EPPAR_EPPA1_BOTH (0x000C) - -/* Bit definitions and macros for MCF_EPORT_EPDDR */ -#define MCF_EPORT_EPDDR_EPDD1 (0x02) -#define MCF_EPORT_EPDDR_EPDD2 (0x04) -#define MCF_EPORT_EPDDR_EPDD3 (0x08) -#define MCF_EPORT_EPDDR_EPDD4 (0x10) -#define MCF_EPORT_EPDDR_EPDD5 (0x20) -#define MCF_EPORT_EPDDR_EPDD6 (0x40) -#define MCF_EPORT_EPDDR_EPDD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPIER */ -#define MCF_EPORT_EPIER_EPIE1 (0x02) -#define MCF_EPORT_EPIER_EPIE2 (0x04) -#define MCF_EPORT_EPIER_EPIE3 (0x08) -#define MCF_EPORT_EPIER_EPIE4 (0x10) -#define MCF_EPORT_EPIER_EPIE5 (0x20) -#define MCF_EPORT_EPIER_EPIE6 (0x40) -#define MCF_EPORT_EPIER_EPIE7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPDR */ -#define MCF_EPORT_EPDR_EPD1 (0x02) -#define MCF_EPORT_EPDR_EPD2 (0x04) -#define MCF_EPORT_EPDR_EPD3 (0x08) -#define MCF_EPORT_EPDR_EPD4 (0x10) -#define MCF_EPORT_EPDR_EPD5 (0x20) -#define MCF_EPORT_EPDR_EPD6 (0x40) -#define MCF_EPORT_EPDR_EPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPPDR */ -#define MCF_EPORT_EPPDR_EPPD1 (0x02) -#define MCF_EPORT_EPPDR_EPPD2 (0x04) -#define MCF_EPORT_EPPDR_EPPD3 (0x08) -#define MCF_EPORT_EPPDR_EPPD4 (0x10) -#define MCF_EPORT_EPPDR_EPPD5 (0x20) -#define MCF_EPORT_EPPDR_EPPD6 (0x40) -#define MCF_EPORT_EPPDR_EPPD7 (0x80) - -/* Bit definitions and macros for MCF_EPORT_EPFR */ -#define MCF_EPORT_EPFR_EPF1 (0x02) -#define MCF_EPORT_EPFR_EPF2 (0x04) -#define MCF_EPORT_EPFR_EPF3 (0x08) -#define MCF_EPORT_EPFR_EPF4 (0x10) -#define MCF_EPORT_EPFR_EPF5 (0x20) -#define MCF_EPORT_EPFR_EPF6 (0x40) -#define MCF_EPORT_EPFR_EPF7 (0x80) - -/********************************************************************/ -#endif /* m532xsim_h */ diff --git a/include/asm-m68knommu/m5407sim.h b/include/asm-m68knommu/m5407sim.h deleted file mode 100644 index cc22c4a53005..000000000000 --- a/include/asm-m68knommu/m5407sim.h +++ /dev/null @@ -1,157 +0,0 @@ -/****************************************************************************/ - -/* - * m5407sim.h -- ColdFire 5407 System Integration Module support. - * - * (C) Copyright 2000, Lineo (www.lineo.com) - * (C) Copyright 1999, Moreton Bay Ventures Pty Ltd. - * - * Modified by David W. Miller for the MCF5307 Eval Board. - */ - -/****************************************************************************/ -#ifndef m5407sim_h -#define m5407sim_h -/****************************************************************************/ - -/* - * Define the 5407 SIM register set addresses. - */ -#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ -#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/ -#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ -#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ -#define MCFSIM_PAR 0x04 /* Pin Assignment reg (r/w) */ -#define MCFSIM_IRQPAR 0x06 /* Interrupt Assignment reg (r/w) */ -#define MCFSIM_PLLCR 0x08 /* PLL Controll Reg*/ -#define MCFSIM_MPARK 0x0C /* BUS Master Control Reg*/ -#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ -#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ -#define MCFSIM_AVR 0x4b /* Autovector Ctrl reg (r/w) */ -#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ -#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ -#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ -#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ -#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ -#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ -#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ -#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ -#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ -#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ -#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ -#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ - -#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */ -#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */ -#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */ -#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */ -#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */ -#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */ - -#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */ -#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */ -#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */ -#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */ -#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */ -#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */ -#define MCFSIM_CSAR4 0xb0 /* CS 4 Address reg (r/w) */ -#define MCFSIM_CSMR4 0xb4 /* CS 4 Mask reg (r/w) */ -#define MCFSIM_CSCR4 0xba /* CS 4 Control reg (r/w) */ -#define MCFSIM_CSAR5 0xbc /* CS 5 Address reg (r/w) */ -#define MCFSIM_CSMR5 0xc0 /* CS 5 Mask reg (r/w) */ -#define MCFSIM_CSCR5 0xc6 /* CS 5 Control reg (r/w) */ -#define MCFSIM_CSAR6 0xc8 /* CS 6 Address reg (r/w) */ -#define MCFSIM_CSMR6 0xcc /* CS 6 Mask reg (r/w) */ -#define MCFSIM_CSCR6 0xd2 /* CS 6 Control reg (r/w) */ -#define MCFSIM_CSAR7 0xd4 /* CS 7 Address reg (r/w) */ -#define MCFSIM_CSMR7 0xd8 /* CS 7 Mask reg (r/w) */ -#define MCFSIM_CSCR7 0xde /* CS 7 Control reg (r/w) */ - -#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ -#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ -#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ -#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ - -#define MCFSIM_PADDR 0x244 /* Parallel Direction (r/w) */ -#define MCFSIM_PADAT 0x248 /* Parallel Data (r/w) */ - - -/* - * Some symbol defines for the above... - */ -#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ -#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ -#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ -#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ -#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ -#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */ -#define MCFSIM_DMA1ICR MCFSIM_ICR7 /* DMA 1 ICR */ -#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */ -#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */ - -/* - * Macro to set IMR register. It is 32 bits on the 5407. - */ -#define mcf_getimr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) - -#define mcf_setimr(imr) \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); - -#define mcf_getipr() \ - *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IPR)) - - -/* - * Some symbol defines for the Parallel Port Pin Assignment Register - */ -#define MCFSIM_PAR_DREQ0 0x40 /* Set to select DREQ0 input */ - /* Clear to select par I/O */ -#define MCFSIM_PAR_DREQ1 0x20 /* Select DREQ1 input */ - /* Clear to select par I/O */ - -/* - * Defines for the IRQPAR Register - */ -#define IRQ5_LEVEL4 0x80 -#define IRQ3_LEVEL6 0x40 -#define IRQ1_LEVEL2 0x20 - - -/* - * Define the Cache register flags. - */ -#define CACR_DEC 0x80000000 /* Enable data cache */ -#define CACR_DWP 0x40000000 /* Data write protection */ -#define CACR_DESB 0x20000000 /* Enable data store buffer */ -#define CACR_DDPI 0x10000000 /* Disable CPUSHL */ -#define CACR_DHCLK 0x08000000 /* Half data cache lock mode */ -#define CACR_DDCM_WT 0x00000000 /* Write through cache*/ -#define CACR_DDCM_CP 0x02000000 /* Copyback cache */ -#define CACR_DDCM_P 0x04000000 /* No cache, precise */ -#define CACR_DDCM_IMP 0x06000000 /* No cache, imprecise */ -#define CACR_DCINVA 0x01000000 /* Invalidate data cache */ -#define CACR_BEC 0x00080000 /* Enable branch cache */ -#define CACR_BCINVA 0x00040000 /* Invalidate branch cache */ -#define CACR_IEC 0x00008000 /* Enable instruction cache */ -#define CACR_DNFB 0x00002000 /* Inhibited fill buffer */ -#define CACR_IDPI 0x00001000 /* Disable CPUSHL */ -#define CACR_IHLCK 0x00000800 /* Intruction cache half lock */ -#define CACR_IDCM 0x00000400 /* Intruction cache inhibit */ -#define CACR_ICINVA 0x00000100 /* Invalidate instr cache */ - -#define ACR_BASE_POS 24 /* Address Base */ -#define ACR_MASK_POS 16 /* Address Mask */ -#define ACR_ENABLE 0x00008000 /* Enable address */ -#define ACR_USER 0x00000000 /* User mode access only */ -#define ACR_SUPER 0x00002000 /* Supervisor mode only */ -#define ACR_ANY 0x00004000 /* Match any access mode */ -#define ACR_CM_WT 0x00000000 /* Write through mode */ -#define ACR_CM_CP 0x00000020 /* Copyback mode */ -#define ACR_CM_OFF_PRE 0x00000040 /* No cache, precise */ -#define ACR_CM_OFF_IMP 0x00000060 /* No cache, imprecise */ -#define ACR_WPROTECT 0x00000004 /* Write protect */ - -/****************************************************************************/ -#endif /* m5407sim_h */ diff --git a/include/asm-m68knommu/m68360.h b/include/asm-m68knommu/m68360.h deleted file mode 100644 index eb7d39ef2855..000000000000 --- a/include/asm-m68knommu/m68360.h +++ /dev/null @@ -1,13 +0,0 @@ -#include "m68360_regs.h" -#include "m68360_pram.h" -#include "m68360_quicc.h" -#include "m68360_enet.h" - -#ifdef CONFIG_M68360 - -#define CPM_INTERRUPT 4 - -/* see MC68360 User's Manual, p. 7-377 */ -#define CPM_VECTOR_BASE 0x04 /* 3 MSbits of CPM vector */ - -#endif /* CONFIG_M68360 */ diff --git a/include/asm-m68knommu/m68360_enet.h b/include/asm-m68knommu/m68360_enet.h deleted file mode 100644 index c36f4d059203..000000000000 --- a/include/asm-m68knommu/m68360_enet.h +++ /dev/null @@ -1,177 +0,0 @@ -/*********************************** - * $Id: m68360_enet.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ - *********************************** - * - *************************************** - * Definitions for the ETHERNET controllers - *************************************** - */ - -#ifndef __ETHER_H -#define __ETHER_H - -#include "quicc_simple.h" - -/* - * transmit BD's - */ -#define T_R 0x8000 /* ready bit */ -#define E_T_PAD 0x4000 /* short frame padding */ -#define T_W 0x2000 /* wrap bit */ -#define T_I 0x1000 /* interrupt on completion */ -#define T_L 0x0800 /* last in frame */ -#define T_TC 0x0400 /* transmit CRC (when last) */ - -#define T_DEF 0x0200 /* defer indication */ -#define T_HB 0x0100 /* heartbeat */ -#define T_LC 0x0080 /* error: late collision */ -#define T_RL 0x0040 /* error: retransmission limit */ -#define T_RC 0x003c /* retry count */ -#define T_UN 0x0002 /* error: underrun */ -#define T_CSL 0x0001 /* carier sense lost */ -#define T_ERROR (T_HB | T_LC | T_RL | T_UN | T_CSL) - -/* - * receive BD's - */ -#define R_E 0x8000 /* buffer empty */ -#define R_W 0x2000 /* wrap bit */ -#define R_I 0x1000 /* interrupt on reception */ -#define R_L 0x0800 /* last BD in frame */ -#define R_F 0x0400 /* first BD in frame */ -#define R_M 0x0100 /* received because of promisc. mode */ - -#define R_LG 0x0020 /* frame too long */ -#define R_NO 0x0010 /* non-octet aligned */ -#define R_SH 0x0008 /* short frame */ -#define R_CR 0x0004 /* receive CRC error */ -#define R_OV 0x0002 /* receive overrun */ -#define R_CL 0x0001 /* collision */ -#define ETHER_R_ERROR (R_LG | R_NO | R_SH | R_CR | R_OV | R_CL) - - -/* - * ethernet interrupts - */ -#define ETHERNET_GRA 0x0080 /* graceful stop complete */ -#define ETHERNET_TXE 0x0010 /* transmit error */ -#define ETHERNET_RXF 0x0008 /* receive frame */ -#define ETHERNET_BSY 0x0004 /* busy condition */ -#define ETHERNET_TXB 0x0002 /* transmit buffer */ -#define ETHERNET_RXB 0x0001 /* receive buffer */ - -/* - * ethernet protocol specific mode register (PSMR) - */ -#define ETHER_HBC 0x8000 /* heartbeat checking */ -#define ETHER_FC 0x4000 /* force collision */ -#define ETHER_RSH 0x2000 /* receive short frames */ -#define ETHER_IAM 0x1000 /* individual address mode */ -#define ETHER_CRC_32 (0x2<<10) /* Enable CRC */ -#define ETHER_PRO 0x0200 /* promiscuous */ -#define ETHER_BRO 0x0100 /* broadcast address */ -#define ETHER_SBT 0x0080 /* stop backoff timer */ -#define ETHER_LPB 0x0040 /* Loop Back Mode */ -#define ETHER_SIP 0x0020 /* sample input pins */ -#define ETHER_LCW 0x0010 /* late collision window */ -#define ETHER_NIB_13 (0x0<<1) /* # of ignored bits 13 */ -#define ETHER_NIB_14 (0x1<<1) /* # of ignored bits 14 */ -#define ETHER_NIB_15 (0x2<<1) /* # of ignored bits 15 */ -#define ETHER_NIB_16 (0x3<<1) /* # of ignored bits 16 */ -#define ETHER_NIB_21 (0x4<<1) /* # of ignored bits 21 */ -#define ETHER_NIB_22 (0x5<<1) /* # of ignored bits 22 */ -#define ETHER_NIB_23 (0x6<<1) /* # of ignored bits 23 */ -#define ETHER_NIB_24 (0x7<<1) /* # of ignored bits 24 */ - -/* - * ethernet specific parameters - */ -#define CRC_WORD 4 /* Length in bytes of CRC */ -#define C_PRES 0xffffffff /* preform 32 bit CRC */ -#define C_MASK 0xdebb20e3 /* comply with 32 bit CRC */ -#define CRCEC 0x00000000 -#define ALEC 0x00000000 -#define DISFC 0x00000000 -#define PADS 0x00000000 -#define RET_LIM 0x000f /* retry 15 times to send a frame before interrupt */ -#define ETH_MFLR 0x05ee /* 1518 max frame size */ -#define MINFLR 0x0040 /* Minimum frame size 64 */ -#define MAXD1 0x05ee /* Max dma count 1518 */ -#define MAXD2 0x05ee -#define GADDR1 0x00000000 /* Clear group address */ -#define GADDR2 0x00000000 -#define GADDR3 0x00000000 -#define GADDR4 0x00000000 -#define P_PER 0x00000000 /*not used */ -#define IADDR1 0x00000000 /* Individual hash table not used */ -#define IADDR2 0x00000000 -#define IADDR3 0x00000000 -#define IADDR4 0x00000000 -#define TADDR_H 0x00000000 /* clear this regs */ -#define TADDR_M 0x00000000 -#define TADDR_L 0x00000000 - -/* SCC Parameter Ram */ -#define RFCR 0x18 /* normal operation */ -#define TFCR 0x18 /* normal operation */ -#define E_MRBLR 1518 /* Max ethernet frame length */ - -/* - * ethernet specific structure - */ -typedef union { - unsigned char b[6]; - struct { - unsigned short high; - unsigned short middl; - unsigned short low; - } w; -} ETHER_ADDR; - -typedef struct { - int max_frame_length; - int promisc_mode; - int reject_broadcast; - ETHER_ADDR phys_adr; -} ETHER_SPECIFIC; - -typedef struct { - ETHER_ADDR dst_addr; - ETHER_ADDR src_addr; - unsigned short type_or_len; - unsigned char data[1]; -} ETHER_FRAME; - -#define MAX_DATALEN 1500 -typedef struct { - ETHER_ADDR dst_addr; - ETHER_ADDR src_addr; - unsigned short type_or_len; - unsigned char data[MAX_DATALEN]; - unsigned char fcs[CRC_WORD]; -} ETHER_MAX_FRAME; - - -/* - * Internal ethernet function prototypes - */ -void ether_interrupt(int scc_num); -/* mleslie: debug */ -/* static void ethernet_rx_internal(int scc_num); */ -/* static void ethernet_tx_internal(int scc_num); */ - -/* - * User callable routines prototypes (ethernet specific) - */ -void ethernet_init(int scc_number, - alloc_routine *alloc_buffer, - free_routine *free_buffer, - store_rx_buffer_routine *store_rx_buffer, - handle_tx_error_routine *handle_tx_error, - handle_rx_error_routine *handle_rx_error, - handle_lost_error_routine *handle_lost_error, - ETHER_SPECIFIC *ether_spec); -int ethernet_tx(int scc_number, void *buf, int length); - -#endif - diff --git a/include/asm-m68knommu/m68360_pram.h b/include/asm-m68knommu/m68360_pram.h deleted file mode 100644 index e6088bbce93d..000000000000 --- a/include/asm-m68knommu/m68360_pram.h +++ /dev/null @@ -1,431 +0,0 @@ -/*********************************** - * $Id: m68360_pram.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ - *********************************** - * - *************************************** - * Definitions of the parameter area RAM. - * Note that different structures are overlaid - * at the same offsets for the different modes - * of operation. - *************************************** - */ - -#ifndef __PRAM_H -#define __PRAM_H - -/* Time slot assignment table */ -#define VALID_SLOT 0x8000 -#define WRAP_SLOT 0x4000 - -/***************************************************************** - Global Multichannel parameter RAM -*****************************************************************/ -struct global_multi_pram { - /* - * Global Multichannel parameter RAM - */ - unsigned long mcbase; /* Multichannel Base pointer */ - unsigned short qmcstate; /* Multichannel Controller state */ - unsigned short mrblr; /* Maximum Receive Buffer Length */ - unsigned short tx_s_ptr; /* TSTATx Pointer */ - unsigned short rxptr; /* Current Time slot entry in TSATRx */ - unsigned short grfthr; /* Global Receive frame threshold */ - unsigned short grfcnt; /* Global Receive Frame Count */ - unsigned long intbase; /* Multichannel Base address */ - unsigned long iintptr; /* Pointer to interrupt queue */ - unsigned short rx_s_ptr; /* TSTARx Pointer */ - - unsigned short txptr; /* Current Time slot entry in TSATTx */ - unsigned long c_mask32; /* CRC Constant (debb20e3) */ - unsigned short tsatrx[32]; /* Time Slot Assignment Table Rx */ - unsigned short tsattx[32]; /* Time Slot Assignment Table Tx */ - unsigned short c_mask16; /* CRC Constant (f0b8) */ -}; - -/***************************************************************** - Quicc32 HDLC parameter RAM -*****************************************************************/ -struct quicc32_pram { - - unsigned short tbase; /* Tx Buffer Descriptors Base Address */ - unsigned short chamr; /* Channel Mode Register */ - unsigned long tstate; /* Tx Internal State */ - unsigned long txintr; /* Tx Internal Data Pointer */ - unsigned short tbptr; /* Tx Buffer Descriptor Pointer */ - unsigned short txcntr; /* Tx Internal Byte Count */ - unsigned long tupack; /* (Tx Temp) */ - unsigned long zistate; /* Zero Insertion machine state */ - unsigned long tcrc; /* Temp Transmit CRC */ - unsigned short intmask; /* Channel's interrupt mask flags */ - unsigned short bdflags; - unsigned short rbase; /* Rx Buffer Descriptors Base Address */ - unsigned short mflr; /* Max Frame Length Register */ - unsigned long rstate; /* Rx Internal State */ - unsigned long rxintr; /* Rx Internal Data Pointer */ - unsigned short rbptr; /* Rx Buffer Descriptor Pointer */ - unsigned short rxbyc; /* Rx Internal Byte Count */ - unsigned long rpack; /* (Rx Temp) */ - unsigned long zdstate; /* Zero Deletion machine state */ - unsigned long rcrc; /* Temp Transmit CRC */ - unsigned short maxc; /* Max_length counter */ - unsigned short tmp_mb; /* Temp */ -}; - - -/***************************************************************** - HDLC parameter RAM -*****************************************************************/ - -struct hdlc_pram { - /* - * SCC parameter RAM - */ - unsigned short rbase; /* RX BD base address */ - unsigned short tbase; /* TX BD base address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned long rcrc; /* temp receive CRC */ - unsigned long tcrc; /* temp transmit CRC */ - - /* - * HDLC specific parameter RAM - */ - unsigned char RESERVED1[4]; /* Reserved area */ - unsigned long c_mask; /* CRC constant */ - unsigned long c_pres; /* CRC preset */ - unsigned short disfc; /* discarded frame counter */ - unsigned short crcec; /* CRC error counter */ - unsigned short abtsc; /* abort sequence counter */ - unsigned short nmarc; /* nonmatching address rx cnt */ - unsigned short retrc; /* frame retransmission cnt */ - unsigned short mflr; /* maximum frame length reg */ - unsigned short max_cnt; /* maximum length counter */ - unsigned short rfthr; /* received frames threshold */ - unsigned short rfcnt; /* received frames count */ - unsigned short hmask; /* user defined frm addr mask */ - unsigned short haddr1; /* user defined frm address 1 */ - unsigned short haddr2; /* user defined frm address 2 */ - unsigned short haddr3; /* user defined frm address 3 */ - unsigned short haddr4; /* user defined frm address 4 */ - unsigned short tmp; /* temp */ - unsigned short tmp_mb; /* temp */ -}; - - - -/***************************************************************** - UART parameter RAM -*****************************************************************/ - -/* - * bits in uart control characters table - */ -#define CC_INVALID 0x8000 /* control character is valid */ -#define CC_REJ 0x4000 /* don't store char in buffer */ -#define CC_CHAR 0x00ff /* control character */ - -/* UART */ -struct uart_pram { - /* - * SCC parameter RAM - */ - unsigned short rbase; /* RX BD base address */ - unsigned short tbase; /* TX BD base address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rx_temp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned long rcrc; /* temp receive CRC */ - unsigned long tcrc; /* temp transmit CRC */ - - /* - * UART specific parameter RAM - */ - unsigned char RESERVED1[8]; /* Reserved area */ - unsigned short max_idl; /* maximum idle characters */ - unsigned short idlc; /* rx idle counter (internal) */ - unsigned short brkcr; /* break count register */ - - unsigned short parec; /* Rx parity error counter */ - unsigned short frmer; /* Rx framing error counter */ - unsigned short nosec; /* Rx noise counter */ - unsigned short brkec; /* Rx break character counter */ - unsigned short brkln; /* Reaceive break length */ - - unsigned short uaddr1; /* address character 1 */ - unsigned short uaddr2; /* address character 2 */ - unsigned short rtemp; /* temp storage */ - unsigned short toseq; /* Tx out of sequence char */ - unsigned short cc[8]; /* Rx control characters */ - unsigned short rccm; /* Rx control char mask */ - unsigned short rccr; /* Rx control char register */ - unsigned short rlbc; /* Receive last break char */ -}; - - - -/***************************************************************** - BISYNC parameter RAM -*****************************************************************/ - -struct bisync_pram { - /* - * SCC parameter RAM - */ - unsigned short rbase; /* RX BD base address */ - unsigned short tbase; /* TX BD base address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned long rcrc; /* temp receive CRC */ - unsigned long tcrc; /* temp transmit CRC */ - - /* - * BISYNC specific parameter RAM - */ - unsigned char RESERVED1[4]; /* Reserved area */ - unsigned long crcc; /* CRC Constant Temp Value */ - unsigned short prcrc; /* Preset Receiver CRC-16/LRC */ - unsigned short ptcrc; /* Preset Transmitter CRC-16/LRC */ - unsigned short parec; /* Receive Parity Error Counter */ - unsigned short bsync; /* BISYNC SYNC Character */ - unsigned short bdle; /* BISYNC DLE Character */ - unsigned short cc[8]; /* Rx control characters */ - unsigned short rccm; /* Receive Control Character Mask */ -}; - -/***************************************************************** - IOM2 parameter RAM - (overlaid on tx bd[5] of SCC channel[2]) -*****************************************************************/ -struct iom2_pram { - unsigned short ci_data; /* ci data */ - unsigned short monitor_data; /* monitor data */ - unsigned short tstate; /* transmitter state */ - unsigned short rstate; /* receiver state */ -}; - -/***************************************************************** - SPI/SMC parameter RAM - (overlaid on tx bd[6,7] of SCC channel[2]) -*****************************************************************/ - -#define SPI_R 0x8000 /* Ready bit in BD */ - -struct spi_pram { - unsigned short rbase; /* Rx BD Base Address */ - unsigned short tbase; /* Tx BD Base Address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ -}; - -struct smc_uart_pram { - unsigned short rbase; /* Rx BD Base Address */ - unsigned short tbase; /* Tx BD Base Address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned short max_idl; /* Maximum IDLE Characters */ - unsigned short idlc; /* Temporary IDLE Counter */ - unsigned short brkln; /* Last Rx Break Length */ - unsigned short brkec; /* Rx Break Condition Counter */ - unsigned short brkcr; /* Break Count Register (Tx) */ - unsigned short r_mask; /* Temporary bit mask */ -}; - -struct smc_trnsp_pram { - unsigned short rbase; /* rx BD Base Address */ - unsigned short tbase; /* Tx BD Base Address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned short reserved[5]; /* Reserved */ -}; - -struct idma_pram { - unsigned short ibase; /* IDMA BD Base Address */ - unsigned short ibptr; /* IDMA buffer descriptor pointer */ - unsigned long istate; /* IDMA internal state */ - unsigned long itemp; /* IDMA temp */ -}; - -struct ethernet_pram { - /* - * SCC parameter RAM - */ - unsigned short rbase; /* RX BD base address */ - unsigned short tbase; /* TX BD base address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned long rcrc; /* temp receive CRC */ - unsigned long tcrc; /* temp transmit CRC */ - - /* - * ETHERNET specific parameter RAM - */ - unsigned long c_pres; /* preset CRC */ - unsigned long c_mask; /* constant mask for CRC */ - unsigned long crcec; /* CRC error counter */ - unsigned long alec; /* alighnment error counter */ - unsigned long disfc; /* discard frame counter */ - unsigned short pads; /* short frame PAD characters */ - unsigned short ret_lim; /* retry limit threshold */ - unsigned short ret_cnt; /* retry limit counter */ - unsigned short mflr; /* maximum frame length reg */ - unsigned short minflr; /* minimum frame length reg */ - unsigned short maxd1; /* maximum DMA1 length reg */ - unsigned short maxd2; /* maximum DMA2 length reg */ - unsigned short maxd; /* rx max DMA */ - unsigned short dma_cnt; /* rx dma counter */ - unsigned short max_b; /* max bd byte count */ - unsigned short gaddr1; /* group address filter 1 */ - unsigned short gaddr2; /* group address filter 2 */ - unsigned short gaddr3; /* group address filter 3 */ - unsigned short gaddr4; /* group address filter 4 */ - unsigned long tbuf0_data0; /* save area 0 - current frm */ - unsigned long tbuf0_data1; /* save area 1 - current frm */ - unsigned long tbuf0_rba0; - unsigned long tbuf0_crc; - unsigned short tbuf0_bcnt; - union { - unsigned char b[6]; - struct { - unsigned short high; - unsigned short middl; - unsigned short low; - } w; - } paddr; - unsigned short p_per; /* persistence */ - unsigned short rfbd_ptr; /* rx first bd pointer */ - unsigned short tfbd_ptr; /* tx first bd pointer */ - unsigned short tlbd_ptr; /* tx last bd pointer */ - unsigned long tbuf1_data0; /* save area 0 - next frame */ - unsigned long tbuf1_data1; /* save area 1 - next frame */ - unsigned long tbuf1_rba0; - unsigned long tbuf1_crc; - unsigned short tbuf1_bcnt; - unsigned short tx_len; /* tx frame length counter */ - unsigned short iaddr1; /* individual address filter 1*/ - unsigned short iaddr2; /* individual address filter 2*/ - unsigned short iaddr3; /* individual address filter 3*/ - unsigned short iaddr4; /* individual address filter 4*/ - unsigned short boff_cnt; /* back-off counter */ - unsigned short taddr_h; /* temp address (MSB) */ - unsigned short taddr_m; /* temp address */ - unsigned short taddr_l; /* temp address (LSB) */ -}; - -struct transparent_pram { - /* - * SCC parameter RAM - */ - unsigned short rbase; /* RX BD base address */ - unsigned short tbase; /* TX BD base address */ - unsigned char rfcr; /* Rx function code */ - unsigned char tfcr; /* Tx function code */ - unsigned short mrblr; /* Rx buffer length */ - unsigned long rstate; /* Rx internal state */ - unsigned long rptr; /* Rx internal data pointer */ - unsigned short rbptr; /* rb BD Pointer */ - unsigned short rcount; /* Rx internal byte count */ - unsigned long rtemp; /* Rx temp */ - unsigned long tstate; /* Tx internal state */ - unsigned long tptr; /* Tx internal data pointer */ - unsigned short tbptr; /* Tx BD pointer */ - unsigned short tcount; /* Tx byte count */ - unsigned long ttemp; /* Tx temp */ - unsigned long rcrc; /* temp receive CRC */ - unsigned long tcrc; /* temp transmit CRC */ - - /* - * TRANSPARENT specific parameter RAM - */ - unsigned long crc_p; /* CRC Preset */ - unsigned long crc_c; /* CRC constant */ -}; - -struct timer_pram { - /* - * RISC timers parameter RAM - */ - unsigned short tm_base; /* RISC timer table base adr */ - unsigned short tm_ptr; /* RISC timer table pointer */ - unsigned short r_tmr; /* RISC timer mode register */ - unsigned short r_tmv; /* RISC timer valid register */ - unsigned long tm_cmd; /* RISC timer cmd register */ - unsigned long tm_cnt; /* RISC timer internal cnt */ -}; - -#endif diff --git a/include/asm-m68knommu/m68360_quicc.h b/include/asm-m68knommu/m68360_quicc.h deleted file mode 100644 index 6d40f4d18e10..000000000000 --- a/include/asm-m68knommu/m68360_quicc.h +++ /dev/null @@ -1,362 +0,0 @@ -/*********************************** - * $Id: m68360_quicc.h,v 1.1 2002/03/02 15:01:07 gerg Exp $ - *********************************** - * - *************************************** - * Definitions of QUICC memory structures - *************************************** - */ - -#ifndef __M68360_QUICC_H -#define __M68360_QUICC_H - -/* - * include registers and - * parameter ram definitions files - */ -#include -#include - - - -/* Buffer Descriptors */ -typedef struct quicc_bd { - volatile unsigned short status; - volatile unsigned short length; - volatile unsigned char *buf; /* WARNING: This is only true if *char is 32 bits */ -} QUICC_BD; - - -#ifdef MOTOROLA_ORIGINAL -struct user_data { - /* BASE + 0x000: user data memory */ - volatile unsigned char udata_bd_ucode[0x400]; /*user data bd's Ucode*/ - volatile unsigned char udata_bd[0x200]; /*user data Ucode */ - volatile unsigned char ucode_ext[0x100]; /*Ucode Extention ram */ - volatile unsigned char RESERVED1[0x500]; /* Reserved area */ -}; -#else -struct user_data { - /* BASE + 0x000: user data memory */ - volatile unsigned char udata_bd_ucode[0x400]; /* user data, bds, Ucode*/ - volatile unsigned char udata_bd1[0x200]; /* user, bds */ - volatile unsigned char ucode_bd_scratch[0x100]; /* user, bds, ucode scratch */ - volatile unsigned char udata_bd2[0x100]; /* user, bds */ - volatile unsigned char RESERVED1[0x400]; /* Reserved area */ -}; -#endif - - -/* - * internal ram - */ -typedef struct quicc { - union { - struct quicc32_pram ch_pram_tbl[32]; /* 32*64(bytes) per channel */ - struct user_data u; - }ch_or_u; /* multipul or user space */ - - /* BASE + 0xc00: PARAMETER RAM */ - union { - struct scc_pram { - union { - struct hdlc_pram h; - struct uart_pram u; - struct bisync_pram b; - struct transparent_pram t; - unsigned char RESERVED66[0x70]; - } pscc; /* scc parameter area (protocol dependent) */ - union { - struct { - unsigned char RESERVED70[0x10]; - struct spi_pram spi; - unsigned char RESERVED72[0x8]; - struct timer_pram timer; - } timer_spi; - struct { - struct idma_pram idma; - unsigned char RESERVED67[0x4]; - union { - struct smc_uart_pram u; - struct smc_trnsp_pram t; - } psmc; - } idma_smc; - } pothers; - } scc; - struct ethernet_pram enet_scc; - struct global_multi_pram m; - unsigned char pr[0x100]; - } pram[4]; - - /* reserved */ - - /* BASE + 0x1000: INTERNAL REGISTERS */ - /* SIM */ - volatile unsigned long sim_mcr; /* module configuration reg */ - volatile unsigned short sim_simtr; /* module test register */ - volatile unsigned char RESERVED2[0x2]; /* Reserved area */ - volatile unsigned char sim_avr; /* auto vector reg */ - volatile unsigned char sim_rsr; /* reset status reg */ - volatile unsigned char RESERVED3[0x2]; /* Reserved area */ - volatile unsigned char sim_clkocr; /* CLCO control register */ - volatile unsigned char RESERVED62[0x3]; /* Reserved area */ - volatile unsigned short sim_pllcr; /* PLL control register */ - volatile unsigned char RESERVED63[0x2]; /* Reserved area */ - volatile unsigned short sim_cdvcr; /* Clock devider control register */ - volatile unsigned short sim_pepar; /* Port E pin assignment register */ - volatile unsigned char RESERVED64[0xa]; /* Reserved area */ - volatile unsigned char sim_sypcr; /* system protection control*/ - volatile unsigned char sim_swiv; /* software interrupt vector*/ - volatile unsigned char RESERVED6[0x2]; /* Reserved area */ - volatile unsigned short sim_picr; /* periodic interrupt control reg */ - volatile unsigned char RESERVED7[0x2]; /* Reserved area */ - volatile unsigned short sim_pitr; /* periodic interrupt timing reg */ - volatile unsigned char RESERVED8[0x3]; /* Reserved area */ - volatile unsigned char sim_swsr; /* software service */ - volatile unsigned long sim_bkar; /* breakpoint address register*/ - volatile unsigned long sim_bkcr; /* breakpoint control register*/ - volatile unsigned char RESERVED10[0x8]; /* Reserved area */ - /* MEMC */ - volatile unsigned long memc_gmr; /* Global memory register */ - volatile unsigned short memc_mstat; /* MEMC status register */ - volatile unsigned char RESERVED11[0xa]; /* Reserved area */ - volatile unsigned long memc_br0; /* base register 0 */ - volatile unsigned long memc_or0; /* option register 0 */ - volatile unsigned char RESERVED12[0x8]; /* Reserved area */ - volatile unsigned long memc_br1; /* base register 1 */ - volatile unsigned long memc_or1; /* option register 1 */ - volatile unsigned char RESERVED13[0x8]; /* Reserved area */ - volatile unsigned long memc_br2; /* base register 2 */ - volatile unsigned long memc_or2; /* option register 2 */ - volatile unsigned char RESERVED14[0x8]; /* Reserved area */ - volatile unsigned long memc_br3; /* base register 3 */ - volatile unsigned long memc_or3; /* option register 3 */ - volatile unsigned char RESERVED15[0x8]; /* Reserved area */ - volatile unsigned long memc_br4; /* base register 3 */ - volatile unsigned long memc_or4; /* option register 3 */ - volatile unsigned char RESERVED16[0x8]; /* Reserved area */ - volatile unsigned long memc_br5; /* base register 3 */ - volatile unsigned long memc_or5; /* option register 3 */ - volatile unsigned char RESERVED17[0x8]; /* Reserved area */ - volatile unsigned long memc_br6; /* base register 3 */ - volatile unsigned long memc_or6; /* option register 3 */ - volatile unsigned char RESERVED18[0x8]; /* Reserved area */ - volatile unsigned long memc_br7; /* base register 3 */ - volatile unsigned long memc_or7; /* option register 3 */ - volatile unsigned char RESERVED9[0x28]; /* Reserved area */ - /* TEST */ - volatile unsigned short test_tstmra; /* master shift a */ - volatile unsigned short test_tstmrb; /* master shift b */ - volatile unsigned short test_tstsc; /* shift count */ - volatile unsigned short test_tstrc; /* repetition counter */ - volatile unsigned short test_creg; /* control */ - volatile unsigned short test_dreg; /* destributed register */ - volatile unsigned char RESERVED58[0x404]; /* Reserved area */ - /* IDMA1 */ - volatile unsigned short idma_iccr; /* channel configuration reg*/ - volatile unsigned char RESERVED19[0x2]; /* Reserved area */ - volatile unsigned short idma1_cmr; /* dma mode reg */ - volatile unsigned char RESERVED68[0x2]; /* Reserved area */ - volatile unsigned long idma1_sapr; /* dma source addr ptr */ - volatile unsigned long idma1_dapr; /* dma destination addr ptr */ - volatile unsigned long idma1_bcr; /* dma byte count reg */ - volatile unsigned char idma1_fcr; /* function code reg */ - volatile unsigned char RESERVED20; /* Reserved area */ - volatile unsigned char idma1_cmar; /* channel mask reg */ - volatile unsigned char RESERVED21; /* Reserved area */ - volatile unsigned char idma1_csr; /* channel status reg */ - volatile unsigned char RESERVED22[0x3]; /* Reserved area */ - /* SDMA */ - volatile unsigned char sdma_sdsr; /* status reg */ - volatile unsigned char RESERVED23; /* Reserved area */ - volatile unsigned short sdma_sdcr; /* configuration reg */ - volatile unsigned long sdma_sdar; /* address reg */ - /* IDMA2 */ - volatile unsigned char RESERVED69[0x2]; /* Reserved area */ - volatile unsigned short idma2_cmr; /* dma mode reg */ - volatile unsigned long idma2_sapr; /* dma source addr ptr */ - volatile unsigned long idma2_dapr; /* dma destination addr ptr */ - volatile unsigned long idma2_bcr; /* dma byte count reg */ - volatile unsigned char idma2_fcr; /* function code reg */ - volatile unsigned char RESERVED24; /* Reserved area */ - volatile unsigned char idma2_cmar; /* channel mask reg */ - volatile unsigned char RESERVED25; /* Reserved area */ - volatile unsigned char idma2_csr; /* channel status reg */ - volatile unsigned char RESERVED26[0x7]; /* Reserved area */ - /* Interrupt Controller */ - volatile unsigned long intr_cicr; /* CP interrupt configuration reg*/ - volatile unsigned long intr_cipr; /* CP interrupt pending reg */ - volatile unsigned long intr_cimr; /* CP interrupt mask reg */ - volatile unsigned long intr_cisr; /* CP interrupt in service reg*/ - /* Parallel I/O */ - volatile unsigned short pio_padir; /* port A data direction reg */ - volatile unsigned short pio_papar; /* port A pin assignment reg */ - volatile unsigned short pio_paodr; /* port A open drain reg */ - volatile unsigned short pio_padat; /* port A data register */ - volatile unsigned char RESERVED28[0x8]; /* Reserved area */ - volatile unsigned short pio_pcdir; /* port C data direction reg*/ - volatile unsigned short pio_pcpar; /* port C pin assignment reg*/ - volatile unsigned short pio_pcso; /* port C special options */ - volatile unsigned short pio_pcdat; /* port C data register */ - volatile unsigned short pio_pcint; /* port C interrupt cntrl reg */ - volatile unsigned char RESERVED29[0x16]; /* Reserved area */ - /* Timer */ - volatile unsigned short timer_tgcr; /* timer global configuration reg */ - volatile unsigned char RESERVED30[0xe]; /* Reserved area */ - volatile unsigned short timer_tmr1; /* timer 1 mode reg */ - volatile unsigned short timer_tmr2; /* timer 2 mode reg */ - volatile unsigned short timer_trr1; /* timer 1 referance reg */ - volatile unsigned short timer_trr2; /* timer 2 referance reg */ - volatile unsigned short timer_tcr1; /* timer 1 capture reg */ - volatile unsigned short timer_tcr2; /* timer 2 capture reg */ - volatile unsigned short timer_tcn1; /* timer 1 counter reg */ - volatile unsigned short timer_tcn2; /* timer 2 counter reg */ - volatile unsigned short timer_tmr3; /* timer 3 mode reg */ - volatile unsigned short timer_tmr4; /* timer 4 mode reg */ - volatile unsigned short timer_trr3; /* timer 3 referance reg */ - volatile unsigned short timer_trr4; /* timer 4 referance reg */ - volatile unsigned short timer_tcr3; /* timer 3 capture reg */ - volatile unsigned short timer_tcr4; /* timer 4 capture reg */ - volatile unsigned short timer_tcn3; /* timer 3 counter reg */ - volatile unsigned short timer_tcn4; /* timer 4 counter reg */ - volatile unsigned short timer_ter1; /* timer 1 event reg */ - volatile unsigned short timer_ter2; /* timer 2 event reg */ - volatile unsigned short timer_ter3; /* timer 3 event reg */ - volatile unsigned short timer_ter4; /* timer 4 event reg */ - volatile unsigned char RESERVED34[0x8]; /* Reserved area */ - /* CP */ - volatile unsigned short cp_cr; /* command register */ - volatile unsigned char RESERVED35[0x2]; /* Reserved area */ - volatile unsigned short cp_rccr; /* main configuration reg */ - volatile unsigned char RESERVED37; /* Reserved area */ - volatile unsigned char cp_rmds; /* development support status reg */ - volatile unsigned long cp_rmdr; /* development support control reg */ - volatile unsigned short cp_rctr1; /* ram break register 1 */ - volatile unsigned short cp_rctr2; /* ram break register 2 */ - volatile unsigned short cp_rctr3; /* ram break register 3 */ - volatile unsigned short cp_rctr4; /* ram break register 4 */ - volatile unsigned char RESERVED59[0x2]; /* Reserved area */ - volatile unsigned short cp_rter; /* RISC timers event reg */ - volatile unsigned char RESERVED38[0x2]; /* Reserved area */ - volatile unsigned short cp_rtmr; /* RISC timers mask reg */ - volatile unsigned char RESERVED39[0x14]; /* Reserved area */ - /* BRG */ - union { - volatile unsigned long l; - struct { - volatile unsigned short BRGC_RESERV:14; - volatile unsigned short rst:1; - volatile unsigned short en:1; - volatile unsigned short extc:2; - volatile unsigned short atb:1; - volatile unsigned short cd:12; - volatile unsigned short div16:1; - } b; - } brgc[4]; /* BRG1-BRG4 configuration regs*/ - /* SCC registers */ - struct scc_regs { - union { - struct { - /* Low word. */ - volatile unsigned short GSMR_RESERV2:1; - volatile unsigned short edge:2; - volatile unsigned short tci:1; - volatile unsigned short tsnc:2; - volatile unsigned short rinv:1; - volatile unsigned short tinv:1; - volatile unsigned short tpl:3; - volatile unsigned short tpp:2; - volatile unsigned short tend:1; - volatile unsigned short tdcr:2; - volatile unsigned short rdcr:2; - volatile unsigned short renc:3; - volatile unsigned short tenc:3; - volatile unsigned short diag:2; - volatile unsigned short enr:1; - volatile unsigned short ent:1; - volatile unsigned short mode:4; - /* High word. */ - volatile unsigned short GSMR_RESERV1:14; - volatile unsigned short pri:1; - volatile unsigned short gde:1; - volatile unsigned short tcrc:2; - volatile unsigned short revd:1; - volatile unsigned short trx:1; - volatile unsigned short ttx:1; - volatile unsigned short cdp:1; - volatile unsigned short ctsp:1; - volatile unsigned short cds:1; - volatile unsigned short ctss:1; - volatile unsigned short tfl:1; - volatile unsigned short rfw:1; - volatile unsigned short txsy:1; - volatile unsigned short synl:2; - volatile unsigned short rtsm:1; - volatile unsigned short rsyn:1; - } b; - struct { - volatile unsigned long low; - volatile unsigned long high; - } w; - } scc_gsmr; /* SCC general mode reg */ - volatile unsigned short scc_psmr; /* protocol specific mode reg */ - volatile unsigned char RESERVED42[0x2]; /* Reserved area */ - volatile unsigned short scc_todr; /* SCC transmit on demand */ - volatile unsigned short scc_dsr; /* SCC data sync reg */ - volatile unsigned short scc_scce; /* SCC event reg */ - volatile unsigned char RESERVED43[0x2];/* Reserved area */ - volatile unsigned short scc_sccm; /* SCC mask reg */ - volatile unsigned char RESERVED44[0x1];/* Reserved area */ - volatile unsigned char scc_sccs; /* SCC status reg */ - volatile unsigned char RESERVED45[0x8]; /* Reserved area */ - } scc_regs[4]; - /* SMC */ - struct smc_regs { - volatile unsigned char RESERVED46[0x2]; /* Reserved area */ - volatile unsigned short smc_smcmr; /* SMC mode reg */ - volatile unsigned char RESERVED60[0x2]; /* Reserved area */ - volatile unsigned char smc_smce; /* SMC event reg */ - volatile unsigned char RESERVED47[0x3]; /* Reserved area */ - volatile unsigned char smc_smcm; /* SMC mask reg */ - volatile unsigned char RESERVED48[0x5]; /* Reserved area */ - } smc_regs[2]; - /* SPI */ - volatile unsigned short spi_spmode; /* SPI mode reg */ - volatile unsigned char RESERVED51[0x4]; /* Reserved area */ - volatile unsigned char spi_spie; /* SPI event reg */ - volatile unsigned char RESERVED52[0x3]; /* Reserved area */ - volatile unsigned char spi_spim; /* SPI mask reg */ - volatile unsigned char RESERVED53[0x2]; /* Reserved area */ - volatile unsigned char spi_spcom; /* SPI command reg */ - volatile unsigned char RESERVED54[0x4]; /* Reserved area */ - /* PIP */ - volatile unsigned short pip_pipc; /* pip configuration reg */ - volatile unsigned char RESERVED65[0x2]; /* Reserved area */ - volatile unsigned short pip_ptpr; /* pip timing parameters reg */ - volatile unsigned long pip_pbdir; /* port b data direction reg */ - volatile unsigned long pip_pbpar; /* port b pin assignment reg */ - volatile unsigned long pip_pbodr; /* port b open drain reg */ - volatile unsigned long pip_pbdat; /* port b data reg */ - volatile unsigned char RESERVED71[0x18]; /* Reserved area */ - /* Serial Interface */ - volatile unsigned long si_simode; /* SI mode register */ - volatile unsigned char si_sigmr; /* SI global mode register */ - volatile unsigned char RESERVED55; /* Reserved area */ - volatile unsigned char si_sistr; /* SI status register */ - volatile unsigned char si_sicmr; /* SI command register */ - volatile unsigned char RESERVED56[0x4]; /* Reserved area */ - volatile unsigned long si_sicr; /* SI clock routing */ - volatile unsigned long si_sirp; /* SI ram pointers */ - volatile unsigned char RESERVED57[0xc]; /* Reserved area */ - volatile unsigned short si_siram[0x80]; /* SI routing ram */ -} QUICC; - -#endif - -/* - * Local variables: - * c-indent-level: 4 - * c-basic-offset: 4 - * tab-width: 4 - * End: - */ diff --git a/include/asm-m68knommu/m68360_regs.h b/include/asm-m68knommu/m68360_regs.h deleted file mode 100644 index d57217ca4f27..000000000000 --- a/include/asm-m68knommu/m68360_regs.h +++ /dev/null @@ -1,408 +0,0 @@ -/*********************************** - * $Id: m68360_regs.h,v 1.2 2002/10/26 15:03:55 gerg Exp $ - *********************************** - * - *************************************** - * Definitions of the QUICC registers - *************************************** - */ - -#ifndef __REGISTERS_H -#define __REGISTERS_H - -#define CLEAR_BIT(x, bit) x =bit - -/***************************************************************** - Command Register -*****************************************************************/ - -/* bit fields within command register */ -#define SOFTWARE_RESET 0x8000 -#define CMD_OPCODE 0x0f00 -#define CMD_CHANNEL 0x00f0 -#define CMD_FLAG 0x0001 - -/* general command opcodes */ -#define INIT_RXTX_PARAMS 0x0000 -#define INIT_RX_PARAMS 0x0100 -#define INIT_TX_PARAMS 0x0200 -#define ENTER_HUNT_MODE 0x0300 -#define STOP_TX 0x0400 -#define GR_STOP_TX 0x0500 -#define RESTART_TX 0x0600 -#define CLOSE_RX_BD 0x0700 -#define SET_ENET_GROUP 0x0800 -#define RESET_ENET_GROUP 0x0900 - -/* quicc32 CP commands */ -#define STOP_TX_32 0x0e00 /*add chan# bits 2-6 */ -#define ENTER_HUNT_MODE_32 0x1e00 - -/* quicc32 mask/event SCC register */ -#define GOV 0x01 -#define GUN 0x02 -#define GINT 0x04 -#define IQOV 0x08 - - -/* Timer commands */ -#define SET_TIMER 0x0800 - -/* Multi channel Interrupt structure */ -#define INTR_VALID 0x8000 /* Valid interrupt entry */ -#define INTR_WRAP 0x4000 /* Wrap bit in the interrupt entry table */ -#define INTR_CH_NU 0x07c0 /* Channel Num in interrupt table */ -#define INTR_MASK_BITS 0x383f - -/* - * General SCC mode register (GSMR) - */ - -#define MODE_HDLC 0x0 -#define MODE_APPLE_TALK 0x2 -#define MODE_SS7 0x3 -#define MODE_UART 0x4 -#define MODE_PROFIBUS 0x5 -#define MODE_ASYNC_HDLC 0x6 -#define MODE_V14 0x7 -#define MODE_BISYNC 0x8 -#define MODE_DDCMP 0x9 -#define MODE_MULTI_CHANNEL 0xa -#define MODE_ETHERNET 0xc - -#define DIAG_NORMAL 0x0 -#define DIAG_LOCAL_LPB 0x1 -#define DIAG_AUTO_ECHO 0x2 -#define DIAG_LBP_ECHO 0x3 - -/* For RENC and TENC fields in GSMR */ -#define ENC_NRZ 0x0 -#define ENC_NRZI 0x1 -#define ENC_FM0 0x2 -#define ENC_MANCH 0x4 -#define ENC_DIFF_MANC 0x6 - -/* For TDCR and RDCR fields in GSMR */ -#define CLOCK_RATE_1 0x0 -#define CLOCK_RATE_8 0x1 -#define CLOCK_RATE_16 0x2 -#define CLOCK_RATE_32 0x3 - -#define TPP_00 0x0 -#define TPP_10 0x1 -#define TPP_01 0x2 -#define TPP_11 0x3 - -#define TPL_NO 0x0 -#define TPL_8 0x1 -#define TPL_16 0x2 -#define TPL_32 0x3 -#define TPL_48 0x4 -#define TPL_64 0x5 -#define TPL_128 0x6 - -#define TSNC_INFINITE 0x0 -#define TSNC_14_65 0x1 -#define TSNC_4_15 0x2 -#define TSNC_3_1 0x3 - -#define EDGE_BOTH 0x0 -#define EDGE_POS 0x1 -#define EDGE_NEG 0x2 -#define EDGE_NO 0x3 - -#define SYNL_NO 0x0 -#define SYNL_4 0x1 -#define SYNL_8 0x2 -#define SYNL_16 0x3 - -#define TCRC_CCITT16 0x0 -#define TCRC_CRC16 0x1 -#define TCRC_CCITT32 0x2 - - -/***************************************************************** - TODR (Transmit on demand) Register -*****************************************************************/ -#define TODR_TOD 0x8000 /* Transmit on demand */ - - -/***************************************************************** - CICR register settings -*****************************************************************/ - -/* note that relative irq priorities of the SCCs can be reordered - * if desired - see p. 7-377 of the MC68360UM */ -#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */ -#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */ -#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */ -#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */ - -#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrupt */ -#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */ -#define CICR_VBA_MASK ((uint)0x000000e0) /* Vector Base Address */ -#define CICR_SPS ((uint)0x00000001) /* SCC Spread */ - - -/***************************************************************** - Interrupt bits for CIPR and CIMR (MC68360UM p. 7-379) -*****************************************************************/ - -#define INTR_PIO_PC0 0x80000000 /* parallel I/O C bit 0 */ -#define INTR_SCC1 0x40000000 /* SCC port 1 */ -#define INTR_SCC2 0x20000000 /* SCC port 2 */ -#define INTR_SCC3 0x10000000 /* SCC port 3 */ -#define INTR_SCC4 0x08000000 /* SCC port 4 */ -#define INTR_PIO_PC1 0x04000000 /* parallel i/o C bit 1 */ -#define INTR_TIMER1 0x02000000 /* timer 1 */ -#define INTR_PIO_PC2 0x01000000 /* parallel i/o C bit 2 */ -#define INTR_PIO_PC3 0x00800000 /* parallel i/o C bit 3 */ -#define INTR_SDMA_BERR 0x00400000 /* SDMA channel bus error */ -#define INTR_DMA1 0x00200000 /* idma 1 */ -#define INTR_DMA2 0x00100000 /* idma 2 */ -#define INTR_TIMER2 0x00040000 /* timer 2 */ -#define INTR_CP_TIMER 0x00020000 /* CP timer */ -#define INTR_PIP_STATUS 0x00010000 /* PIP status */ -#define INTR_PIO_PC4 0x00008000 /* parallel i/o C bit 4 */ -#define INTR_PIO_PC5 0x00004000 /* parallel i/o C bit 5 */ -#define INTR_TIMER3 0x00001000 /* timer 3 */ -#define INTR_PIO_PC6 0x00000800 /* parallel i/o C bit 6 */ -#define INTR_PIO_PC7 0x00000400 /* parallel i/o C bit 7 */ -#define INTR_PIO_PC8 0x00000200 /* parallel i/o C bit 8 */ -#define INTR_TIMER4 0x00000080 /* timer 4 */ -#define INTR_PIO_PC9 0x00000040 /* parallel i/o C bit 9 */ -#define INTR_SCP 0x00000020 /* SCP */ -#define INTR_SMC1 0x00000010 /* SMC 1 */ -#define INTR_SMC2 0x00000008 /* SMC 2 */ -#define INTR_PIO_PC10 0x00000004 /* parallel i/o C bit 10 */ -#define INTR_PIO_PC11 0x00000002 /* parallel i/o C bit 11 */ -#define INTR_ERR 0x00000001 /* error */ - - -/***************************************************************** - CPM Interrupt vector encodings (MC68360UM p. 7-376) -*****************************************************************/ - -#define CPMVEC_NR 32 -#define CPMVEC_PIO_PC0 0x1f -#define CPMVEC_SCC1 0x1e -#define CPMVEC_SCC2 0x1d -#define CPMVEC_SCC3 0x1c -#define CPMVEC_SCC4 0x1b -#define CPMVEC_PIO_PC1 0x1a -#define CPMVEC_TIMER1 0x19 -#define CPMVEC_PIO_PC2 0x18 -#define CPMVEC_PIO_PC3 0x17 -#define CPMVEC_SDMA_CB_ERR 0x16 -#define CPMVEC_IDMA1 0x15 -#define CPMVEC_IDMA2 0x14 -#define CPMVEC_RESERVED3 0x13 -#define CPMVEC_TIMER2 0x12 -#define CPMVEC_RISCTIMER 0x11 -#define CPMVEC_RESERVED2 0x10 -#define CPMVEC_PIO_PC4 0x0f -#define CPMVEC_PIO_PC5 0x0e -#define CPMVEC_TIMER3 0x0c -#define CPMVEC_PIO_PC6 0x0b -#define CPMVEC_PIO_PC7 0x0a -#define CPMVEC_PIO_PC8 0x09 -#define CPMVEC_RESERVED1 0x08 -#define CPMVEC_TIMER4 0x07 -#define CPMVEC_PIO_PC9 0x06 -#define CPMVEC_SPI 0x05 -#define CPMVEC_SMC1 0x04 -#define CPMVEC_SMC2 0x03 -#define CPMVEC_PIO_PC10 0x02 -#define CPMVEC_PIO_PC11 0x01 -#define CPMVEC_ERROR 0x00 - -/* #define CPMVEC_PIO_PC0 ((ushort)0x1f) */ -/* #define CPMVEC_SCC1 ((ushort)0x1e) */ -/* #define CPMVEC_SCC2 ((ushort)0x1d) */ -/* #define CPMVEC_SCC3 ((ushort)0x1c) */ -/* #define CPMVEC_SCC4 ((ushort)0x1b) */ -/* #define CPMVEC_PIO_PC1 ((ushort)0x1a) */ -/* #define CPMVEC_TIMER1 ((ushort)0x19) */ -/* #define CPMVEC_PIO_PC2 ((ushort)0x18) */ -/* #define CPMVEC_PIO_PC3 ((ushort)0x17) */ -/* #define CPMVEC_SDMA_CB_ERR ((ushort)0x16) */ -/* #define CPMVEC_IDMA1 ((ushort)0x15) */ -/* #define CPMVEC_IDMA2 ((ushort)0x14) */ -/* #define CPMVEC_RESERVED3 ((ushort)0x13) */ -/* #define CPMVEC_TIMER2 ((ushort)0x12) */ -/* #define CPMVEC_RISCTIMER ((ushort)0x11) */ -/* #define CPMVEC_RESERVED2 ((ushort)0x10) */ -/* #define CPMVEC_PIO_PC4 ((ushort)0x0f) */ -/* #define CPMVEC_PIO_PC5 ((ushort)0x0e) */ -/* #define CPMVEC_TIMER3 ((ushort)0x0c) */ -/* #define CPMVEC_PIO_PC6 ((ushort)0x0b) */ -/* #define CPMVEC_PIO_PC7 ((ushort)0x0a) */ -/* #define CPMVEC_PIO_PC8 ((ushort)0x09) */ -/* #define CPMVEC_RESERVED1 ((ushort)0x08) */ -/* #define CPMVEC_TIMER4 ((ushort)0x07) */ -/* #define CPMVEC_PIO_PC9 ((ushort)0x06) */ -/* #define CPMVEC_SPI ((ushort)0x05) */ -/* #define CPMVEC_SMC1 ((ushort)0x04) */ -/* #define CPMVEC_SMC2 ((ushort)0x03) */ -/* #define CPMVEC_PIO_PC10 ((ushort)0x02) */ -/* #define CPMVEC_PIO_PC11 ((ushort)0x01) */ -/* #define CPMVEC_ERROR ((ushort)0x00) */ - - -/***************************************************************** - * PIO control registers - *****************************************************************/ - -/* Port A - See 360UM p. 7-358 - * - * Note that most of these pins have alternate functions - */ - - -/* The macros are nice, but there are all sorts of references to 1-indexed - * facilities on the 68360... */ -/* #define PA_RXD(n) ((ushort)(0x01<<(2*n))) */ -/* #define PA_TXD(n) ((ushort)(0x02<<(2*n))) */ - -#define PA_RXD1 ((ushort)0x0001) -#define PA_TXD1 ((ushort)0x0002) -#define PA_RXD2 ((ushort)0x0004) -#define PA_TXD2 ((ushort)0x0008) -#define PA_RXD3 ((ushort)0x0010) -#define PA_TXD3 ((ushort)0x0020) -#define PA_RXD4 ((ushort)0x0040) -#define PA_TXD4 ((ushort)0x0080) - -#define PA_CLK1 ((ushort)0x0100) -#define PA_CLK2 ((ushort)0x0200) -#define PA_CLK3 ((ushort)0x0400) -#define PA_CLK4 ((ushort)0x0800) -#define PA_CLK5 ((ushort)0x1000) -#define PA_CLK6 ((ushort)0x2000) -#define PA_CLK7 ((ushort)0x4000) -#define PA_CLK8 ((ushort)0x8000) - - -/* Port B - See 360UM p. 7-362 - */ - - -/* Port C - See 360UM p. 7-365 - */ - -#define PC_RTS1 ((ushort)0x0001) -#define PC_RTS2 ((ushort)0x0002) -#define PC__RTS3 ((ushort)0x0004) /* !RTS3 */ -#define PC__RTS4 ((ushort)0x0008) /* !RTS4 */ - -#define PC_CTS1 ((ushort)0x0010) -#define PC_CD1 ((ushort)0x0020) -#define PC_CTS2 ((ushort)0x0040) -#define PC_CD2 ((ushort)0x0080) -#define PC_CTS3 ((ushort)0x0100) -#define PC_CD3 ((ushort)0x0200) -#define PC_CTS4 ((ushort)0x0400) -#define PC_CD4 ((ushort)0x0800) - - - -/***************************************************************** - chip select option register -*****************************************************************/ -#define DTACK 0xe000 -#define ADR_MASK 0x1ffc -#define RDWR_MASK 0x0002 -#define FC_MASK 0x0001 - -/***************************************************************** - tbase and rbase registers -*****************************************************************/ -#define TBD_ADDR(quicc,pram) ((struct quicc_bd *) \ - (quicc->ch_or_u.u.udata_bd_ucode + pram->tbase)) -#define RBD_ADDR(quicc,pram) ((struct quicc_bd *) \ - (quicc->ch_or_u.u.udata_bd_ucode + pram->rbase)) -#define TBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ - (quicc->ch_or_u.u.udata_bd_ucode + pram->tbptr)) -#define RBD_CUR_ADDR(quicc,pram) ((struct quicc_bd *) \ - (quicc->ch_or_u.u.udata_bd_ucode + pram->rbptr)) -#define TBD_SET_CUR_ADDR(bd,quicc,pram) pram->tbptr = \ - ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) -#define RBD_SET_CUR_ADDR(bd,quicc,pram) pram->rbptr = \ - ((unsigned short)((char *)(bd) - (char *)(quicc->ch_or_u.u.udata_bd_ucode))) -#define INCREASE_TBD(bd,quicc,pram) { \ - if((bd)->status & T_W) \ - (bd) = TBD_ADDR(quicc,pram); \ - else \ - (bd)++; \ -} -#define DECREASE_TBD(bd,quicc,pram) { \ - if ((bd) == TBD_ADDR(quicc, pram)) \ - while (!((bd)->status & T_W)) \ - (bd)++; \ - else \ - (bd)--; \ -} -#define INCREASE_RBD(bd,quicc,pram) { \ - if((bd)->status & R_W) \ - (bd) = RBD_ADDR(quicc,pram); \ - else \ - (bd)++; \ -} -#define DECREASE_RBD(bd,quicc,pram) { \ - if ((bd) == RBD_ADDR(quicc, pram)) \ - while (!((bd)->status & T_W)) \ - (bd)++; \ - else \ - (bd)--; \ -} - -/***************************************************************** - Macros for Multi channel -*****************************************************************/ -#define QMC_BASE(quicc,page) (struct global_multi_pram *)(&quicc->pram[page]) -#define MCBASE(quicc,page) (unsigned long)(quicc->pram[page].m.mcbase) -#define CHANNEL_PRAM_BASE(quicc,channel) ((struct quicc32_pram *) \ - (&(quicc->ch_or_u.ch_pram_tbl[channel]))) -#define TBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ - (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbase))) -#define RBD_32_ADDR(quicc,page,channel) ((struct quicc_bd *) \ - (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbase))) -#define TBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ - (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->tbptr))) -#define RBD_32_CUR_ADDR(quicc,page,channel) ((struct quicc_bd *) \ - (MCBASE(quicc,page) + (CHANNEL_PRAM_BASE(quicc,channel)->rbptr))) -#define TBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ - CHANNEL_PRAM_BASE(quicc,channel)->tbptr = \ - ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) -#define RBD_32_SET_CUR_ADDR(bd,quicc,page,channel) \ - CHANNEL_PRAM_BASE(quicc,channel)->rbptr = \ - ((unsigned short)((char *)(bd) - (char *)(MCBASE(quicc,page)))) - -#define INCREASE_TBD_32(bd,quicc,page,channel) { \ - if((bd)->status & T_W) \ - (bd) = TBD_32_ADDR(quicc,page,channel); \ - else \ - (bd)++; \ -} -#define DECREASE_TBD_32(bd,quicc,page,channel) { \ - if ((bd) == TBD_32_ADDR(quicc, page,channel)) \ - while (!((bd)->status & T_W)) \ - (bd)++; \ - else \ - (bd)--; \ -} -#define INCREASE_RBD_32(bd,quicc,page,channel) { \ - if((bd)->status & R_W) \ - (bd) = RBD_32_ADDR(quicc,page,channel); \ - else \ - (bd)++; \ -} -#define DECREASE_RBD_32(bd,quicc,page,channel) { \ - if ((bd) == RBD_32_ADDR(quicc, page,channel)) \ - while (!((bd)->status & T_W)) \ - (bd)++; \ - else \ - (bd)--; \ -} - -#endif diff --git a/include/asm-m68knommu/machdep.h b/include/asm-m68knommu/machdep.h deleted file mode 100644 index de9f47a51cc2..000000000000 --- a/include/asm-m68knommu/machdep.h +++ /dev/null @@ -1,26 +0,0 @@ -#ifndef _M68KNOMMU_MACHDEP_H -#define _M68KNOMMU_MACHDEP_H - -#include - -/* Hardware clock functions */ -extern void hw_timer_init(void); -extern unsigned long hw_timer_offset(void); - -extern irqreturn_t arch_timer_interrupt(int irq, void *dummy); - -/* Machine dependent time handling */ -extern void (*mach_gettod)(int *year, int *mon, int *day, int *hour, - int *min, int *sec); -extern int (*mach_set_clock_mmss)(unsigned long); - -/* machine dependent power off functions */ -extern void (*mach_reset)( void ); -extern void (*mach_halt)( void ); -extern void (*mach_power_off)( void ); - -extern void config_BSP(char *command, int len); - -extern void do_IRQ(int irq, struct pt_regs *fp); - -#endif /* _M68KNOMMU_MACHDEP_H */ diff --git a/include/asm-m68knommu/math-emu.h b/include/asm-m68knommu/math-emu.h deleted file mode 100644 index 7e7090517b72..000000000000 --- a/include/asm-m68knommu/math-emu.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/mc146818rtc.h b/include/asm-m68knommu/mc146818rtc.h deleted file mode 100644 index 907a0481a140..000000000000 --- a/include/asm-m68knommu/mc146818rtc.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef _M68KNOMMU_MC146818RTC_H -#define _M68KNOMMU_MC146818RTC_H - -/* empty include file to satisfy the include in genrtc.c/ide-geometry.c */ - -#endif /* _M68KNOMMU_MC146818RTC_H */ diff --git a/include/asm-m68knommu/mcfcache.h b/include/asm-m68knommu/mcfcache.h deleted file mode 100644 index c042634fadaa..000000000000 --- a/include/asm-m68knommu/mcfcache.h +++ /dev/null @@ -1,150 +0,0 @@ -/****************************************************************************/ - -/* - * mcfcache.h -- ColdFire CPU cache support code - * - * (C) Copyright 2004, Greg Ungerer - */ - -/****************************************************************************/ -#ifndef __M68KNOMMU_MCFCACHE_H -#define __M68KNOMMU_MCFCACHE_H -/****************************************************************************/ - - -/* - * The different ColdFire families have different cache arrangments. - * Everything from a small instruction only cache, to configurable - * data and/or instruction cache, to unified instruction/data, to - * harvard style separate instruction and data caches. - */ - -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || defined(CONFIG_M5272) -/* - * Simple version 2 core cache. These have instruction cache only, - * we just need to invalidate it and enable it. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - movel #0x80000100,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ -.endm -#endif /* CONFIG_M5206 || CONFIG_M5206e || CONFIG_M5272 */ - -#if defined(CONFIG_M523x) || defined(CONFIG_M527x) -/* - * New version 2 cores have a configurable split cache arrangement. - * For now I am just enabling instruction cache - but ultimately I - * think a split instruction/data cache would be better. - */ -.macro CACHE_ENABLE - movel #0x01400000,%d0 - movec %d0,%CACR /* invalidate cache */ - nop - movel #0x0000c000,%d0 /* set SDRAM cached only */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80400100,%d0 /* configure cache */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M523x || CONFIG_M527x */ - -#if defined(CONFIG_M528x) -.macro CACHE_ENABLE - nop - movel #0x01000000, %d0 - movec %d0, %CACR /* Invalidate cache */ - nop - movel #0x0000c020, %d0 /* Set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000, %d0 /* No other regions cached */ - movec %d0, %ACR1 - movel #0x80000200, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable cache */ - nop -.endm -#endif /* CONFIG_M528x */ - -#if defined(CONFIG_M5249) || defined(CONFIG_M5307) -/* - * The version 3 core cache. Oddly enough the version 2 core 5249 - * has the same SDRAM and cache setup as the version 3 cores. - * This is a single unified instruction/data cache. - */ -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop -#if defined(DEBUGGER_COMPATIBLE_CACHE) || defined(CONFIG_SECUREEDGEMP3) - movel #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ -#else - movel #0x0000c020,%d0 /* set SDRAM cached (copyback) */ -#endif - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0xa0000200,%d0 /* enable cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5249 || CONFIG_M5307 */ - -#if defined(CONFIG_M532x) -.macro CACHE_ENABLE - movel #0x01000000,%d0 /* invalidate cache cmd */ - movec %d0,%CACR /* do invalidate cache */ - nop - movel #0x4001C000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - movel #0x80000200,%d0 /* setup cache mask */ - movec %d0,%CACR /* enable cache */ - nop -.endm -#endif /* CONFIG_M532x */ - -#if defined(CONFIG_M5407) -/* - * Version 4 cores have a true harvard style separate instruction - * and data cache. Invalidate and enable cache, also enable write - * buffers and branch accelerator. - */ -.macro CACHE_ENABLE - movel #0x01040100,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - movel #0x000fc000,%d0 /* set SDRAM cached only */ - movec %d0, %ACR0 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR1 - movel #0x000fc000,%d0 /* set SDRAM cached only */ - movec %d0, %ACR2 - movel #0x00000000,%d0 /* no other regions cached */ - movec %d0, %ACR3 - movel #0xb6088400,%d0 /* enable caches */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M5407 */ - -#if defined(CONFIG_M520x) -.macro CACHE_ENABLE - move.l #0x01000000,%d0 /* invalidate whole cache */ - movec %d0,%CACR - nop - move.l #0x0000c000,%d0 /* set SDRAM cached (write-thru) */ - movec %d0,%ACR0 - move.l #0x00000000,%d0 /* no other regions cached */ - movec %d0,%ACR1 - move.l #0x80400000,%d0 /* enable 8K instruction cache */ - movec %d0,%CACR - nop -.endm -#endif /* CONFIG_M520x */ - -/****************************************************************************/ -#endif /* __M68KNOMMU_MCFCACHE_H */ diff --git a/include/asm-m68knommu/mcfdma.h b/include/asm-m68knommu/mcfdma.h deleted file mode 100644 index 705c52c79cd8..000000000000 --- a/include/asm-m68knommu/mcfdma.h +++ /dev/null @@ -1,144 +0,0 @@ -/****************************************************************************/ - -/* - * mcfdma.h -- Coldfire internal DMA support defines. - * - * (C) Copyright 1999, Rob Scott (rscott@mtrob.ml.org) - */ - -/****************************************************************************/ -#ifndef mcfdma_h -#define mcfdma_h -/****************************************************************************/ - - -/* - * Get address specific defines for this Coldfire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFDMA_BASE0 0x200 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x240 /* Base address of DMA 1 */ -#elif defined(CONFIG_M5272) -#define MCFDMA_BASE0 0x0e0 /* Base address of DMA 0 */ -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -/* These are relative to the IPSBAR, not MBAR */ -#define MCFDMA_BASE0 0x100 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x140 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x180 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x1C0 /* Base address of DMA 3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFDMA_BASE0 0x300 /* Base address of DMA 0 */ -#define MCFDMA_BASE1 0x340 /* Base address of DMA 1 */ -#define MCFDMA_BASE2 0x380 /* Base address of DMA 2 */ -#define MCFDMA_BASE3 0x3C0 /* Base address of DMA 3 */ -#endif - - -#if !defined(CONFIG_M5272) - -/* - * Define the DMA register set addresses. - * Note: these are longword registers, use unsigned long as data type - */ -#define MCFDMA_SAR 0x00 /* DMA source address (r/w) */ -#define MCFDMA_DAR 0x01 /* DMA destination adr (r/w) */ -/* these are word registers, use unsigned short data type */ -#define MCFDMA_DCR 0x04 /* DMA control reg (r/w) */ -#define MCFDMA_BCR 0x06 /* DMA byte count reg (r/w) */ -/* these are byte registers, use unsiged char data type */ -#define MCFDMA_DSR 0x10 /* DMA status reg (r/w) */ -#define MCFDMA_DIVR 0x14 /* DMA interrupt vec (r/w) */ - -/* - * Bit definitions for the DMA Control Register (DCR). - */ -#define MCFDMA_DCR_INT 0x8000 /* Enable completion irq */ -#define MCFDMA_DCR_EEXT 0x4000 /* Enable external DMA req */ -#define MCFDMA_DCR_CS 0x2000 /* Enable cycle steal */ -#define MCFDMA_DCR_AA 0x1000 /* Enable auto alignment */ -#define MCFDMA_DCR_BWC_MASK 0x0E00 /* Bandwidth ctl mask */ -#define MCFDMA_DCR_BWC_512 0x0200 /* Bandwidth: 512 Bytes */ -#define MCFDMA_DCR_BWC_1024 0x0400 /* Bandwidth: 1024 Bytes */ -#define MCFDMA_DCR_BWC_2048 0x0600 /* Bandwidth: 2048 Bytes */ -#define MCFDMA_DCR_BWC_4096 0x0800 /* Bandwidth: 4096 Bytes */ -#define MCFDMA_DCR_BWC_8192 0x0a00 /* Bandwidth: 8192 Bytes */ -#define MCFDMA_DCR_BWC_16384 0x0c00 /* Bandwidth: 16384 Bytes */ -#define MCFDMA_DCR_BWC_32768 0x0e00 /* Bandwidth: 32768 Bytes */ -#define MCFDMA_DCR_SAA 0x0100 /* Single Address Access */ -#define MCFDMA_DCR_S_RW 0x0080 /* SAA read/write value */ -#define MCFDMA_DCR_SINC 0x0040 /* Source addr inc enable */ -#define MCFDMA_DCR_SSIZE_MASK 0x0030 /* Src xfer size */ -#define MCFDMA_DCR_SSIZE_LONG 0x0000 /* Src xfer size, 00 = longw */ -#define MCFDMA_DCR_SSIZE_BYTE 0x0010 /* Src xfer size, 01 = byte */ -#define MCFDMA_DCR_SSIZE_WORD 0x0020 /* Src xfer size, 10 = word */ -#define MCFDMA_DCR_SSIZE_LINE 0x0030 /* Src xfer size, 11 = line */ -#define MCFDMA_DCR_DINC 0x0008 /* Dest addr inc enable */ -#define MCFDMA_DCR_DSIZE_MASK 0x0006 /* Dest xfer size */ -#define MCFDMA_DCR_DSIZE_LONG 0x0000 /* Dest xfer size, 00 = long */ -#define MCFDMA_DCR_DSIZE_BYTE 0x0002 /* Dest xfer size, 01 = byte */ -#define MCFDMA_DCR_DSIZE_WORD 0x0004 /* Dest xfer size, 10 = word */ -#define MCFDMA_DCR_DSIZE_LINE 0x0006 /* Dest xfer size, 11 = line */ -#define MCFDMA_DCR_START 0x0001 /* Start transfer */ - -/* - * Bit definitions for the DMA Status Register (DSR). - */ -#define MCFDMA_DSR_CE 0x40 /* Config error */ -#define MCFDMA_DSR_BES 0x20 /* Bus Error on source */ -#define MCFDMA_DSR_BED 0x10 /* Bus Error on dest */ -#define MCFDMA_DSR_REQ 0x04 /* Requests remaining */ -#define MCFDMA_DSR_BSY 0x02 /* Busy */ -#define MCFDMA_DSR_DONE 0x01 /* DMA transfer complete */ - -#else /* This is an MCF5272 */ - -#define MCFDMA_DMR 0x00 /* Mode Register (r/w) */ -#define MCFDMA_DIR 0x03 /* Interrupt trigger register (r/w) */ -#define MCFDMA_DSAR 0x03 /* Source Address register (r/w) */ -#define MCFDMA_DDAR 0x04 /* Destination Address register (r/w) */ -#define MCFDMA_DBCR 0x02 /* Byte Count Register (r/w) */ - -/* Bit definitions for the DMA Mode Register (DMR) */ -#define MCFDMA_DMR_RESET 0x80000000L /* Reset bit */ -#define MCFDMA_DMR_EN 0x40000000L /* DMA enable */ -#define MCFDMA_DMR_RQM 0x000C0000L /* Request Mode Mask */ -#define MCFDMA_DMR_RQM_DUAL 0x000C0000L /* Dual address mode, the only valid mode */ -#define MCFDMA_DMR_DSTM 0x00002000L /* Destination addressing mask */ -#define MCFDMA_DMR_DSTM_SA 0x00000000L /* Destination uses static addressing */ -#define MCFDMA_DMR_DSTM_IA 0x00002000L /* Destination uses incremental addressing */ -#define MCFDMA_DMR_DSTT_UD 0x00000400L /* Destination is user data */ -#define MCFDMA_DMR_DSTT_UC 0x00000800L /* Destination is user code */ -#define MCFDMA_DMR_DSTT_SD 0x00001400L /* Destination is supervisor data */ -#define MCFDMA_DMR_DSTT_SC 0x00001800L /* Destination is supervisor code */ -#define MCFDMA_DMR_DSTS_OFF 0x8 /* offset to the destination size bits */ -#define MCFDMA_DMR_DSTS_LONG 0x00000000L /* Long destination size */ -#define MCFDMA_DMR_DSTS_BYTE 0x00000100L /* Byte destination size */ -#define MCFDMA_DMR_DSTS_WORD 0x00000200L /* Word destination size */ -#define MCFDMA_DMR_DSTS_LINE 0x00000300L /* Line destination size */ -#define MCFDMA_DMR_SRCM 0x00000020L /* Source addressing mask */ -#define MCFDMA_DMR_SRCM_SA 0x00000000L /* Source uses static addressing */ -#define MCFDMA_DMR_SRCM_IA 0x00000020L /* Source uses incremental addressing */ -#define MCFDMA_DMR_SRCT_UD 0x00000004L /* Source is user data */ -#define MCFDMA_DMR_SRCT_UC 0x00000008L /* Source is user code */ -#define MCFDMA_DMR_SRCT_SD 0x00000014L /* Source is supervisor data */ -#define MCFDMA_DMR_SRCT_SC 0x00000018L /* Source is supervisor code */ -#define MCFDMA_DMR_SRCS_OFF 0x0 /* Offset to the source size bits */ -#define MCFDMA_DMR_SRCS_LONG 0x00000000L /* Long source size */ -#define MCFDMA_DMR_SRCS_BYTE 0x00000001L /* Byte source size */ -#define MCFDMA_DMR_SRCS_WORD 0x00000002L /* Word source size */ -#define MCFDMA_DMR_SRCS_LINE 0x00000003L /* Line source size */ - -/* Bit definitions for the DMA interrupt register (DIR) */ -#define MCFDMA_DIR_INVEN 0x1000 /* Invalid Combination interrupt enable */ -#define MCFDMA_DIR_ASCEN 0x0800 /* Address Sequence Complete (Completion) interrupt enable */ -#define MCFDMA_DIR_TEEN 0x0200 /* Transfer Error interrupt enable */ -#define MCFDMA_DIR_TCEN 0x0100 /* Transfer Complete (a bus transfer, that is) interrupt enable */ -#define MCFDMA_DIR_INV 0x0010 /* Invalid Combination */ -#define MCFDMA_DIR_ASC 0x0008 /* Address Sequence Complete (DMA Completion) */ -#define MCFDMA_DIR_TE 0x0002 /* Transfer Error */ -#define MCFDMA_DIR_TC 0x0001 /* Transfer Complete */ - -#endif /* !defined(CONFIG_M5272) */ - -/****************************************************************************/ -#endif /* mcfdma_h */ diff --git a/include/asm-m68knommu/mcfmbus.h b/include/asm-m68knommu/mcfmbus.h deleted file mode 100644 index 319899c47a2c..000000000000 --- a/include/asm-m68knommu/mcfmbus.h +++ /dev/null @@ -1,77 +0,0 @@ -/****************************************************************************/ - -/* - * mcfmbus.h -- Coldfire MBUS support defines. - * - * (C) Copyright 1999, Martin Floeer (mfloeer@axcent.de) - */ - -/****************************************************************************/ - - -#ifndef mcfmbus_h -#define mcfmbus_h - - -#define MCFMBUS_BASE 0x280 -#define MCFMBUS_IRQ_VECTOR 0x19 -#define MCFMBUS_IRQ 0x1 -#define MCFMBUS_CLK 0x3f -#define MCFMBUS_IRQ_LEVEL 0x07 /*IRQ Level 1*/ -#define MCFMBUS_ADDRESS 0x01 - - -/* -* Define the 5307 MBUS register set addresses -*/ - -#define MCFMBUS_MADR 0x00 -#define MCFMBUS_MFDR 0x04 -#define MCFMBUS_MBCR 0x08 -#define MCFMBUS_MBSR 0x0C -#define MCFMBUS_MBDR 0x10 - - -#define MCFMBUS_MADR_ADDR(a) (((a)&0x7F)<<0x01) /*Slave Address*/ - -#define MCFMBUS_MFDR_MBC(a) ((a)&0x3F) /*M-Bus Clock*/ - -/* -* Define bit flags in Control Register -*/ - -#define MCFMBUS_MBCR_MEN (0x80) /* M-Bus Enable */ -#define MCFMBUS_MBCR_MIEN (0x40) /* M-Bus Interrupt Enable */ -#define MCFMBUS_MBCR_MSTA (0x20) /* Master/Slave Mode Select Bit */ -#define MCFMBUS_MBCR_MTX (0x10) /* Transmit/Rcv Mode Select Bit */ -#define MCFMBUS_MBCR_TXAK (0x08) /* Transmit Acknowledge Enable */ -#define MCFMBUS_MBCR_RSTA (0x04) /* Repeat Start */ - -/* -* Define bit flags in Status Register -*/ - -#define MCFMBUS_MBSR_MCF (0x80) /* Data Transfer Complete */ -#define MCFMBUS_MBSR_MAAS (0x40) /* Addressed as a Slave */ -#define MCFMBUS_MBSR_MBB (0x20) /* Bus Busy */ -#define MCFMBUS_MBSR_MAL (0x10) /* Arbitration Lost */ -#define MCFMBUS_MBSR_SRW (0x04) /* Slave Transmit */ -#define MCFMBUS_MBSR_MIF (0x02) /* M-Bus Interrupt */ -#define MCFMBUS_MBSR_RXAK (0x01) /* No Acknowledge Received */ - -/* -* Define bit flags in DATA I/O Register -*/ - -#define MCFMBUS_MBDR_READ (0x01) /* 1=read 0=write MBUS */ - -#define MBUSIOCSCLOCK 1 -#define MBUSIOCGCLOCK 2 -#define MBUSIOCSADDR 3 -#define MBUSIOCGADDR 4 -#define MBUSIOCSSLADDR 5 -#define MBUSIOCGSLADDR 6 -#define MBUSIOCSSUBADDR 7 -#define MBUSIOCGSUBADDR 8 - -#endif diff --git a/include/asm-m68knommu/mcfne.h b/include/asm-m68knommu/mcfne.h deleted file mode 100644 index 431f63aadd0e..000000000000 --- a/include/asm-m68knommu/mcfne.h +++ /dev/null @@ -1,325 +0,0 @@ -/****************************************************************************/ - -/* - * mcfne.h -- NE2000 in ColdFire eval boards. - * - * (C) Copyright 1999-2000, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo (www.lineo.com) - * (C) Copyright 2001, SnapGear (www.snapgear.com) - * - * 19990409 David W. Miller Converted from m5206ne.h for 5307 eval board - * - * Hacked support for m5206e Cadre III evaluation board - * Fred Stevens (fred.stevens@pemstar.com) 13 April 1999 - */ - -/****************************************************************************/ -#ifndef mcfne_h -#define mcfne_h -/****************************************************************************/ - - -/* - * Support for NE2000 clones devices in ColdFire based boards. - * Not all boards address these parts the same way, some use a - * direct addressing method, others use a side-band address space - * to access odd address registers, some require byte swapping - * others do not. - */ -#define BSWAP(w) (((w) << 8) | ((w) >> 8)) -#define RSWAP(w) (w) - - -/* - * Define the basic hardware resources of NE2000 boards. - */ - -#if defined(CONFIG_ARN5206) -#define NE2000_ADDR 0x40000300 -#define NE2000_ODDOFFSET 0x00010000 -#define NE2000_IRQ_VECTOR 0xf0 -#define NE2000_IRQ_PRIORITY 2 -#define NE2000_IRQ_LEVEL 4 -#define NE2000_BYTE volatile unsigned short -#endif - -#if defined(CONFIG_M5206eC3) -#define NE2000_ADDR 0x40000300 -#define NE2000_ODDOFFSET 0x00010000 -#define NE2000_IRQ_VECTOR 0x1c -#define NE2000_IRQ_PRIORITY 2 -#define NE2000_IRQ_LEVEL 4 -#define NE2000_BYTE volatile unsigned short -#endif - -#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) -#define NE2000_ADDR 0x30000300 -#define NE2000_IRQ_VECTOR 25 -#define NE2000_IRQ_PRIORITY 1 -#define NE2000_IRQ_LEVEL 3 -#define NE2000_BYTE volatile unsigned char -#endif - -#if defined(CONFIG_M5307C3) -#define NE2000_ADDR 0x40000300 -#define NE2000_ODDOFFSET 0x00010000 -#define NE2000_IRQ_VECTOR 0x1b -#define NE2000_BYTE volatile unsigned short -#endif - -#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) -#define NE2000_ADDR 0x30600300 -#define NE2000_ODDOFFSET 0x00008000 -#define NE2000_IRQ_VECTOR 67 -#undef BSWAP -#define BSWAP(w) (w) -#define NE2000_BYTE volatile unsigned short -#undef RSWAP -#define RSWAP(w) (((w) << 8) | ((w) >> 8)) -#endif - -#if defined(CONFIG_M5307) && defined(CONFIG_NETtel) -#define NE2000_ADDR0 0x30600300 -#define NE2000_ADDR1 0x30800300 -#define NE2000_ODDOFFSET 0x00008000 -#define NE2000_IRQ_VECTOR0 27 -#define NE2000_IRQ_VECTOR1 29 -#undef BSWAP -#define BSWAP(w) (w) -#define NE2000_BYTE volatile unsigned short -#undef RSWAP -#define RSWAP(w) (((w) << 8) | ((w) >> 8)) -#endif - -#if defined(CONFIG_M5307) && defined(CONFIG_SECUREEDGEMP3) -#define NE2000_ADDR 0x30600300 -#define NE2000_ODDOFFSET 0x00008000 -#define NE2000_IRQ_VECTOR 27 -#undef BSWAP -#define BSWAP(w) (w) -#define NE2000_BYTE volatile unsigned short -#undef RSWAP -#define RSWAP(w) (((w) << 8) | ((w) >> 8)) -#endif - -#if defined(CONFIG_ARN5307) -#define NE2000_ADDR 0xfe600300 -#define NE2000_ODDOFFSET 0x00010000 -#define NE2000_IRQ_VECTOR 0x1b -#define NE2000_IRQ_PRIORITY 2 -#define NE2000_IRQ_LEVEL 3 -#define NE2000_BYTE volatile unsigned short -#endif - -#if defined(CONFIG_M5407C3) -#define NE2000_ADDR 0x40000300 -#define NE2000_ODDOFFSET 0x00010000 -#define NE2000_IRQ_VECTOR 0x1b -#define NE2000_BYTE volatile unsigned short -#endif - -/****************************************************************************/ - -/* - * Side-band address space for odd address requires re-mapping - * many of the standard ISA access functions. - */ -#ifdef NE2000_ODDOFFSET - -#undef outb -#undef outb_p -#undef inb -#undef inb_p -#undef outsb -#undef outsw -#undef insb -#undef insw - -#define outb ne2000_outb -#define inb ne2000_inb -#define outb_p ne2000_outb -#define inb_p ne2000_inb -#define outsb ne2000_outsb -#define outsw ne2000_outsw -#define insb ne2000_insb -#define insw ne2000_insw - - -#ifndef COLDFIRE_NE2000_FUNCS - -void ne2000_outb(unsigned int val, unsigned int addr); -int ne2000_inb(unsigned int addr); -void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len); -void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len); -void ne2000_outsb(unsigned int addr, void *vbuf, unsigned long len); -void ne2000_outsw(unsigned int addr, void *vbuf, unsigned long len); - -#else - -/* - * This macro converts a conventional register address into the - * real memory pointer of the mapped NE2000 device. - * On most NE2000 implementations on ColdFire boards the chip is - * mapped in kinda funny, due to its ISA heritage. - */ -#define NE2000_PTR(addr) ((addr&0x1)?(NE2000_ODDOFFSET+addr-1):(addr)) -#define NE2000_DATA_PTR(addr) (addr) - - -void ne2000_outb(unsigned int val, unsigned int addr) -{ - NE2000_BYTE *rp; - - rp = (NE2000_BYTE *) NE2000_PTR(addr); - *rp = RSWAP(val); -} - -int ne2000_inb(unsigned int addr) -{ - NE2000_BYTE *rp, val; - - rp = (NE2000_BYTE *) NE2000_PTR(addr); - val = *rp; - return((int) ((NE2000_BYTE) RSWAP(val))); -} - -void ne2000_insb(unsigned int addr, void *vbuf, int unsigned long len) -{ - NE2000_BYTE *rp, val; - unsigned char *buf; - - buf = (unsigned char *) vbuf; - rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); - for (; (len > 0); len--) { - val = *rp; - *buf++ = RSWAP(val); - } -} - -void ne2000_insw(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short w, *buf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); - for (; (len > 0); len--) { - w = *rp; - *buf++ = BSWAP(w); - } -} - -void ne2000_outsb(unsigned int addr, const void *vbuf, unsigned long len) -{ - NE2000_BYTE *rp, val; - unsigned char *buf; - - buf = (unsigned char *) vbuf; - rp = (NE2000_BYTE *) NE2000_DATA_PTR(addr); - for (; (len > 0); len--) { - val = *buf++; - *rp = RSWAP(val); - } -} - -void ne2000_outsw(unsigned int addr, const void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short w, *buf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) NE2000_DATA_PTR(addr); - for (; (len > 0); len--) { - w = *buf++; - *rp = BSWAP(w); - } -} - -#endif /* COLDFIRE_NE2000_FUNCS */ -#endif /* NE2000_OFFOFFSET */ - -/****************************************************************************/ - -#ifdef COLDFIRE_NE2000_FUNCS - -/* - * Lastly the interrupt set up code... - * Minor differences between the different board types. - */ - -#if defined(CONFIG_ARN5206) -void ne2000_irqsetup(int irq) -{ - volatile unsigned char *icrp; - - icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); - *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2; - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); -} -#endif - -#if defined(CONFIG_M5206eC3) -void ne2000_irqsetup(int irq) -{ - volatile unsigned char *icrp; - - icrp = (volatile unsigned char *) (MCF_MBAR + MCFSIM_ICR4); - *icrp = MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI2 | MCFSIM_ICR_AUTOVEC; - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT4); -} -#endif - -#if defined(CONFIG_M5206e) && defined(CONFIG_NETtel) -void ne2000_irqsetup(int irq) -{ - mcf_autovector(irq); -} -#endif - -#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) -void ne2000_irqsetup(int irq) -{ - volatile unsigned long *icrp; - volatile unsigned long *pitr; - - /* The NE2000 device uses external IRQ3 */ - icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); - *icrp = (*icrp & 0x77077777) | 0x00d00000; - - pitr = (volatile unsigned long *) (MCF_MBAR + MCFSIM_PITR); - *pitr = *pitr | 0x20000000; -} - -void ne2000_irqack(int irq) -{ - volatile unsigned long *icrp; - - /* The NE2000 device uses external IRQ3 */ - icrp = (volatile unsigned long *) (MCF_MBAR + MCFSIM_ICR1); - *icrp = (*icrp & 0x77777777) | 0x00800000; -} -#endif - -#if defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) - -void ne2000_irqsetup(int irq) -{ - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); - mcf_autovector(irq); -} - -#else - -void ne2000_irqsetup(int irq) -{ - mcf_setimr(mcf_getimr() & ~MCFSIM_IMR_EINT3); -} - -#endif /* ! CONFIG_NETtel || CONFIG_SECUREEDGEMP3 */ -#endif /* CONFIG_M5307 || CONFIG_M5407 */ - -#endif /* COLDFIRE_NE2000_FUNCS */ - -/****************************************************************************/ -#endif /* mcfne_h */ diff --git a/include/asm-m68knommu/mcfpci.h b/include/asm-m68knommu/mcfpci.h deleted file mode 100644 index f1507dd06ec6..000000000000 --- a/include/asm-m68knommu/mcfpci.h +++ /dev/null @@ -1,119 +0,0 @@ -/****************************************************************************/ - -/* - * mcfpci.h -- PCI bridge on ColdFire eval boards. - * - * (C) Copyright 2000, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfpci_h -#define mcfpci_h -/****************************************************************************/ - - -#ifdef CONFIG_PCI - -/* - * Address regions in the PCI address space are not mapped into the - * normal memory space of the ColdFire. They must be accessed via - * handler routines. This is easy for I/O space (inb/outb/etc) but - * needs some code changes to support ordinary memory. Interrupts - * also need to be vectored through the PCI handler first, then it - * will call the actual driver sub-handlers. - */ - -/* - * Un-define all the standard I/O access routines. - */ -#undef inb -#undef inw -#undef inl -#undef inb_p -#undef inw_p -#undef insb -#undef insw -#undef insl -#undef outb -#undef outw -#undef outl -#undef outb_p -#undef outw_p -#undef outsb -#undef outsw -#undef outsl - -#undef request_irq -#undef free_irq - -#undef bus_to_virt -#undef virt_to_bus - - -/* - * Re-direct all I/O memory accesses functions to PCI specific ones. - */ -#define inb pci_inb -#define inw pci_inw -#define inl pci_inl -#define inb_p pci_inb -#define inw_p pci_inw -#define insb pci_insb -#define insw pci_insw -#define insl pci_insl - -#define outb pci_outb -#define outw pci_outw -#define outl pci_outl -#define outb_p pci_outb -#define outw_p pci_outw -#define outsb pci_outsb -#define outsw pci_outsw -#define outsl pci_outsl - -#define request_irq pci_request_irq -#define free_irq pci_free_irq - -#define virt_to_bus pci_virt_to_bus -#define bus_to_virt pci_bus_to_virt - -#define CONFIG_COMEMPCI 1 - - -/* - * Prototypes of the real PCI functions (defined in bios32.c). - */ -unsigned char pci_inb(unsigned int addr); -unsigned short pci_inw(unsigned int addr); -unsigned int pci_inl(unsigned int addr); -void pci_insb(void *addr, void *buf, int len); -void pci_insw(void *addr, void *buf, int len); -void pci_insl(void *addr, void *buf, int len); - -void pci_outb(unsigned char val, unsigned int addr); -void pci_outw(unsigned short val, unsigned int addr); -void pci_outl(unsigned int val, unsigned int addr); -void pci_outsb(void *addr, void *buf, int len); -void pci_outsw(void *addr, void *buf, int len); -void pci_outsl(void *addr, void *buf, int len); - -int pci_request_irq(unsigned int irq, - void (*handler)(int, void *, struct pt_regs *), - unsigned long flags, - const char *device, - void *dev_id); -void pci_free_irq(unsigned int irq, void *dev_id); - -void *pci_bmalloc(int size); -void pci_bmfree(void *bmp, int len); -void pci_copytoshmem(unsigned long bmp, void *src, int size); -void pci_copyfromshmem(void *dst, unsigned long bmp, int size); -unsigned long pci_virt_to_bus(volatile void *address); -void *pci_bus_to_virt(unsigned long address); -void pci_bmcpyto(void *dst, void *src, int len); -void pci_bmcpyfrom(void *dst, void *src, int len); - -#endif /* CONFIG_PCI */ -/****************************************************************************/ -#endif /* mcfpci_h */ diff --git a/include/asm-m68knommu/mcfpit.h b/include/asm-m68knommu/mcfpit.h deleted file mode 100644 index f570cf64fd29..000000000000 --- a/include/asm-m68knommu/mcfpit.h +++ /dev/null @@ -1,64 +0,0 @@ -/****************************************************************************/ - -/* - * mcfpit.h -- ColdFire internal PIT timer support defines. - * - * (C) Copyright 2003, Greg Ungerer (gerg@snapgear.com) - */ - -/****************************************************************************/ -#ifndef mcfpit_h -#define mcfpit_h -/****************************************************************************/ - - -/* - * Get address specific defines for the 5270/5271, 5280/5282, and 5208. - */ -#if defined(CONFIG_M520x) -#define MCFPIT_BASE1 0x00080000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00084000 /* Base address of TIMER2 */ -#else -#define MCFPIT_BASE1 0x00150000 /* Base address of TIMER1 */ -#define MCFPIT_BASE2 0x00160000 /* Base address of TIMER2 */ -#define MCFPIT_BASE3 0x00170000 /* Base address of TIMER3 */ -#define MCFPIT_BASE4 0x00180000 /* Base address of TIMER4 */ -#endif - -/* - * Define the PIT timer register set addresses. - */ -#define MCFPIT_PCSR 0x0 /* PIT control register */ -#define MCFPIT_PMR 0x2 /* PIT modulus register */ -#define MCFPIT_PCNTR 0x4 /* PIT count register */ - -/* - * Bit definitions for the PIT Control and Status register. - */ -#define MCFPIT_PCSR_CLK1 0x0000 /* System clock divisor */ -#define MCFPIT_PCSR_CLK2 0x0100 /* System clock divisor */ -#define MCFPIT_PCSR_CLK4 0x0200 /* System clock divisor */ -#define MCFPIT_PCSR_CLK8 0x0300 /* System clock divisor */ -#define MCFPIT_PCSR_CLK16 0x0400 /* System clock divisor */ -#define MCFPIT_PCSR_CLK32 0x0500 /* System clock divisor */ -#define MCFPIT_PCSR_CLK64 0x0600 /* System clock divisor */ -#define MCFPIT_PCSR_CLK128 0x0700 /* System clock divisor */ -#define MCFPIT_PCSR_CLK256 0x0800 /* System clock divisor */ -#define MCFPIT_PCSR_CLK512 0x0900 /* System clock divisor */ -#define MCFPIT_PCSR_CLK1024 0x0a00 /* System clock divisor */ -#define MCFPIT_PCSR_CLK2048 0x0b00 /* System clock divisor */ -#define MCFPIT_PCSR_CLK4096 0x0c00 /* System clock divisor */ -#define MCFPIT_PCSR_CLK8192 0x0d00 /* System clock divisor */ -#define MCFPIT_PCSR_CLK16384 0x0e00 /* System clock divisor */ -#define MCFPIT_PCSR_CLK32768 0x0f00 /* System clock divisor */ -#define MCFPIT_PCSR_DOZE 0x0040 /* Clock run in doze mode */ -#define MCFPIT_PCSR_HALTED 0x0020 /* Clock run in halt mode */ -#define MCFPIT_PCSR_OVW 0x0010 /* Overwrite PIT counter now */ -#define MCFPIT_PCSR_PIE 0x0008 /* Enable PIT interrupt */ -#define MCFPIT_PCSR_PIF 0x0004 /* PIT interrupt flag */ -#define MCFPIT_PCSR_RLD 0x0002 /* Reload counter */ -#define MCFPIT_PCSR_EN 0x0001 /* Enable PIT */ -#define MCFPIT_PCSR_DISABLE 0x0000 /* Disable PIT */ - -/****************************************************************************/ -#endif /* mcfpit_h */ diff --git a/include/asm-m68knommu/mcfsim.h b/include/asm-m68knommu/mcfsim.h deleted file mode 100644 index da3f2ceff3a4..000000000000 --- a/include/asm-m68knommu/mcfsim.h +++ /dev/null @@ -1,126 +0,0 @@ -/****************************************************************************/ - -/* - * mcfsim.h -- ColdFire System Integration Module support. - * - * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfsim_h -#define mcfsim_h -/****************************************************************************/ - - -/* - * Include 5204, 5206/e, 5235, 5249, 5270/5271, 5272, 5280/5282, - * 5307 or 5407 specific addresses. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#include -#elif defined(CONFIG_M520x) -#include -#elif defined(CONFIG_M523x) -#include -#elif defined(CONFIG_M5249) -#include -#elif defined(CONFIG_M527x) -#include -#elif defined(CONFIG_M5272) -#include -#elif defined(CONFIG_M528x) -#include -#elif defined(CONFIG_M5307) -#include -#elif defined(CONFIG_M532x) -#include -#elif defined(CONFIG_M5407) -#include -#endif - - -/* - * Define the base address of the SIM within the MBAR address space. - */ -#define MCFSIM_BASE 0x0 /* Base address of SIM */ - - -/* - * Bit definitions for the ICR family of registers. - */ -#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ -#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ -#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ -#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ -#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ -#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ -#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ -#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ -#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ - -#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ -#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ -#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ -#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ - -/* - * Bit definitions for the Interrupt Mask register (IMR). - */ -#define MCFSIM_IMR_EINT1 0x0002 /* External intr # 1 */ -#define MCFSIM_IMR_EINT2 0x0004 /* External intr # 2 */ -#define MCFSIM_IMR_EINT3 0x0008 /* External intr # 3 */ -#define MCFSIM_IMR_EINT4 0x0010 /* External intr # 4 */ -#define MCFSIM_IMR_EINT5 0x0020 /* External intr # 5 */ -#define MCFSIM_IMR_EINT6 0x0040 /* External intr # 6 */ -#define MCFSIM_IMR_EINT7 0x0080 /* External intr # 7 */ - -#define MCFSIM_IMR_SWD 0x0100 /* Software Watchdog intr */ -#define MCFSIM_IMR_TIMER1 0x0200 /* TIMER 1 intr */ -#define MCFSIM_IMR_TIMER2 0x0400 /* TIMER 2 intr */ -#define MCFSIM_IMR_MBUS 0x0800 /* MBUS intr */ -#define MCFSIM_IMR_UART1 0x1000 /* UART 1 intr */ -#define MCFSIM_IMR_UART2 0x2000 /* UART 2 intr */ - -#if defined(CONFIG_M5206e) -#define MCFSIM_IMR_DMA1 0x4000 /* DMA 1 intr */ -#define MCFSIM_IMR_DMA2 0x8000 /* DMA 2 intr */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) -#define MCFSIM_IMR_DMA0 0x4000 /* DMA 0 intr */ -#define MCFSIM_IMR_DMA1 0x8000 /* DMA 1 intr */ -#define MCFSIM_IMR_DMA2 0x10000 /* DMA 2 intr */ -#define MCFSIM_IMR_DMA3 0x20000 /* DMA 3 intr */ -#endif - -/* - * Mask for all of the SIM devices. Some parts have more or less - * SIM devices. This is a catchall for the sandard set. - */ -#ifndef MCFSIM_IMR_MASKALL -#define MCFSIM_IMR_MASKALL 0x3ffe /* All intr sources */ -#endif - - -/* - * PIT interrupt settings, if not found in mXXXXsim.h file. - */ -#ifndef ICR_INTRCONF -#define ICR_INTRCONF 0x2b /* PIT1 level 5, priority 3 */ -#endif -#ifndef MCFPIT_IMR -#define MCFPIT_IMR MCFINTC_IMRH -#endif -#ifndef MCFPIT_IMR_IBIT -#define MCFPIT_IMR_IBIT (1 << (MCFINT_PIT1 - 32)) -#endif - - -#ifndef __ASSEMBLY__ -/* - * Definition for the interrupt auto-vectoring support. - */ -extern void mcf_autovector(unsigned int vec); -#endif /* __ASSEMBLY__ */ - -/****************************************************************************/ -#endif /* mcfsim_h */ diff --git a/include/asm-m68knommu/mcfsmc.h b/include/asm-m68knommu/mcfsmc.h deleted file mode 100644 index 2d7a4dbd9683..000000000000 --- a/include/asm-m68knommu/mcfsmc.h +++ /dev/null @@ -1,187 +0,0 @@ -/****************************************************************************/ - -/* - * mcfsmc.h -- SMC ethernet support for ColdFire environments. - * - * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfsmc_h -#define mcfsmc_h -/****************************************************************************/ - -/* - * None of the current ColdFire targets that use the SMC91x111 - * allow 8 bit accesses. So this code is 16bit access only. - */ - - -#undef outb -#undef inb -#undef outw -#undef outwd -#undef inw -#undef outl -#undef inl - -#undef outsb -#undef outsw -#undef outsl -#undef insb -#undef insw -#undef insl - -/* - * Re-defines for ColdFire environment... The SMC part is - * mapped into memory space, so remap the PC-style in/out - * routines to handle that. - */ -#define outb smc_outb -#define inb smc_inb -#define outw smc_outw -#define outwd smc_outwd -#define inw smc_inw -#define outl smc_outl -#define inl smc_inl - -#define outsb smc_outsb -#define outsw smc_outsw -#define outsl smc_outsl -#define insb smc_insb -#define insw smc_insw -#define insl smc_insl - - -static inline int smc_inb(unsigned int addr) -{ - register unsigned short w; - w = *((volatile unsigned short *) (addr & ~0x1)); - return(((addr & 0x1) ? w : (w >> 8)) & 0xff); -} - -static inline void smc_outw(unsigned int val, unsigned int addr) -{ - *((volatile unsigned short *) addr) = (val << 8) | (val >> 8); -} - -static inline int smc_inw(unsigned int addr) -{ - register unsigned short w; - w = *((volatile unsigned short *) addr); - return(((w << 8) | (w >> 8)) & 0xffff); -} - -static inline void smc_outl(unsigned long val, unsigned int addr) -{ - *((volatile unsigned long *) addr) = - ((val << 8) & 0xff000000) | ((val >> 8) & 0x00ff0000) | - ((val << 8) & 0x0000ff00) | ((val >> 8) & 0x000000ff); -} - -static inline void smc_outwd(unsigned int val, unsigned int addr) -{ - *((volatile unsigned short *) addr) = val; -} - - -/* - * The rep* functions are used to feed the data port with - * raw data. So we do not byte swap them when copying. - */ - -static inline void smc_insb(unsigned int addr, void *vbuf, int unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - - /* Copy as words for as long as possible */ - for (ebuf = buf + (len >> 1); (buf < ebuf); ) - *buf++ = *rp; - - /* Lastly, handle left over byte */ - if (len & 0x1) - *((unsigned char *) buf) = (*rp >> 8) & 0xff; -} - -static inline void smc_insw(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *buf++ = *rp; -} - -static inline void smc_insl(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned long *rp; - unsigned long *buf, *ebuf; - - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *buf++ = *rp; -} - -static inline void smc_outsw(unsigned int addr, const void *vbuf, unsigned long len) -{ - volatile unsigned short *rp; - unsigned short *buf, *ebuf; - - buf = (unsigned short *) vbuf; - rp = (volatile unsigned short *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *rp = *buf++; -} - -static inline void smc_outsl(unsigned int addr, void *vbuf, unsigned long len) -{ - volatile unsigned long *rp; - unsigned long *buf, *ebuf; - - buf = (unsigned long *) vbuf; - rp = (volatile unsigned long *) addr; - for (ebuf = buf + len; (buf < ebuf); ) - *rp = *buf++; -} - - -#ifdef CONFIG_NETtel -/* - * Re-map the address space of at least one of the SMC ethernet - * parts. Both parts power up decoding the same address, so we - * need to move one of them first, before doing enything else. - * - * We also increase the number of wait states for this part by one. - */ - -void smc_remap(unsigned int ioaddr) -{ - static int once = 0; - extern unsigned short ppdata; - if (once++ == 0) { - *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADDR)) = 0x00ec; - ppdata |= 0x0080; - *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; - outw(0x0001, ioaddr + BANK_SELECT); - outw(0x0001, ioaddr + BANK_SELECT); - outw(0x0067, ioaddr + BASE); - - ppdata &= ~0x0080; - *((volatile unsigned short *)(MCF_MBAR+MCFSIM_PADAT)) = ppdata; - } - - *((volatile unsigned short *)(MCF_MBAR+MCFSIM_CSCR3)) = 0x1180; -} - -#endif - -/****************************************************************************/ -#endif /* mcfsmc_h */ diff --git a/include/asm-m68knommu/mcftimer.h b/include/asm-m68knommu/mcftimer.h deleted file mode 100644 index 0f90f6d2227a..000000000000 --- a/include/asm-m68knommu/mcftimer.h +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************/ - -/* - * mcftimer.h -- ColdFire internal TIMER support defines. - * - * (C) Copyright 1999-2006, Greg Ungerer - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcftimer_h -#define mcftimer_h -/****************************************************************************/ - - -/* - * Get address specific defines for this ColdFire member. - */ -#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#define MCFTIMER_BASE1 0x100 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x120 /* Base address of TIMER2 */ -#elif defined(CONFIG_M5272) -#define MCFTIMER_BASE1 0x200 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x220 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0x240 /* Base address of TIMER4 */ -#define MCFTIMER_BASE4 0x260 /* Base address of TIMER3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#define MCFTIMER_BASE1 0x140 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0x180 /* Base address of TIMER2 */ -#elif defined(CONFIG_M532x) -#define MCFTIMER_BASE1 0xfc070000 /* Base address of TIMER1 */ -#define MCFTIMER_BASE2 0xfc074000 /* Base address of TIMER2 */ -#define MCFTIMER_BASE3 0xfc078000 /* Base address of TIMER3 */ -#define MCFTIMER_BASE4 0xfc07c000 /* Base address of TIMER4 */ -#endif - - -/* - * Define the TIMER register set addresses. - */ -#define MCFTIMER_TMR 0x00 /* Timer Mode reg (r/w) */ -#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */ -#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */ -#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */ -#if defined(CONFIG_M532x) -#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */ -#else -#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */ -#endif - -/* - * Bit definitions for the Timer Mode Register (TMR). - * Register bit flags are common accross ColdFires. - */ -#define MCFTIMER_TMR_PREMASK 0xff00 /* Prescalar mask */ -#define MCFTIMER_TMR_DISCE 0x0000 /* Disable capture */ -#define MCFTIMER_TMR_ANYCE 0x00c0 /* Capture any edge */ -#define MCFTIMER_TMR_FALLCE 0x0080 /* Capture fallingedge */ -#define MCFTIMER_TMR_RISECE 0x0040 /* Capture rising edge */ -#define MCFTIMER_TMR_ENOM 0x0020 /* Enable output toggle */ -#define MCFTIMER_TMR_DISOM 0x0000 /* Do single output pulse */ -#define MCFTIMER_TMR_ENORI 0x0010 /* Enable ref interrupt */ -#define MCFTIMER_TMR_DISORI 0x0000 /* Disable ref interrupt */ -#define MCFTIMER_TMR_RESTART 0x0008 /* Restart counter */ -#define MCFTIMER_TMR_FREERUN 0x0000 /* Free running counter */ -#define MCFTIMER_TMR_CLKTIN 0x0006 /* Input clock is TIN */ -#define MCFTIMER_TMR_CLK16 0x0004 /* Input clock is /16 */ -#define MCFTIMER_TMR_CLK1 0x0002 /* Input clock is /1 */ -#define MCFTIMER_TMR_CLKSTOP 0x0000 /* Stop counter */ -#define MCFTIMER_TMR_ENABLE 0x0001 /* Enable timer */ -#define MCFTIMER_TMR_DISABLE 0x0000 /* Disable timer */ - -/* - * Bit definitions for the Timer Event Registers (TER). - */ -#define MCFTIMER_TER_CAP 0x01 /* Capture event */ -#define MCFTIMER_TER_REF 0x02 /* Refernece event */ - -/****************************************************************************/ -#endif /* mcftimer_h */ diff --git a/include/asm-m68knommu/mcfuart.h b/include/asm-m68knommu/mcfuart.h deleted file mode 100644 index ef2293873612..000000000000 --- a/include/asm-m68knommu/mcfuart.h +++ /dev/null @@ -1,216 +0,0 @@ -/****************************************************************************/ - -/* - * mcfuart.h -- ColdFire internal UART support defines. - * - * (C) Copyright 1999-2003, Greg Ungerer (gerg@snapgear.com) - * (C) Copyright 2000, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfuart_h -#define mcfuart_h -/****************************************************************************/ - -/* - * Define the base address of the UARTS within the MBAR address - * space. - */ -#if defined(CONFIG_M5272) -#define MCFUART_BASE1 0x100 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) -#if defined(CONFIG_NETtel) -#define MCFUART_BASE1 0x180 /* Base address of UART1 */ -#define MCFUART_BASE2 0x140 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x140 /* Base address of UART1 */ -#define MCFUART_BASE2 0x180 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x240 /* Base address of UART2 */ -#define MCFUART_BASE3 0x280 /* Base address of UART3 */ -#elif defined(CONFIG_M5249) || defined(CONFIG_M5307) || defined(CONFIG_M5407) -#if defined(CONFIG_NETtel) || defined(CONFIG_SECUREEDGEMP3) -#define MCFUART_BASE1 0x200 /* Base address of UART1 */ -#define MCFUART_BASE2 0x1c0 /* Base address of UART2 */ -#else -#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */ -#define MCFUART_BASE2 0x200 /* Base address of UART2 */ -#endif -#elif defined(CONFIG_M520x) -#define MCFUART_BASE1 0x60000 /* Base address of UART1 */ -#define MCFUART_BASE2 0x64000 /* Base address of UART2 */ -#define MCFUART_BASE3 0x68000 /* Base address of UART2 */ -#elif defined(CONFIG_M532x) -#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ -#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ -#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ -#endif - - -#include -#include - -struct mcf_platform_uart { - unsigned long mapbase; /* Physical address base */ - void __iomem *membase; /* Virtual address if mapped */ - unsigned int irq; /* Interrupt vector */ - unsigned int uartclk; /* UART clock rate */ -}; - -/* - * Define the ColdFire UART register set addresses. - */ -#define MCFUART_UMR 0x00 /* Mode register (r/w) */ -#define MCFUART_USR 0x04 /* Status register (r) */ -#define MCFUART_UCSR 0x04 /* Clock Select (w) */ -#define MCFUART_UCR 0x08 /* Command register (w) */ -#define MCFUART_URB 0x0c /* Receiver Buffer (r) */ -#define MCFUART_UTB 0x0c /* Transmit Buffer (w) */ -#define MCFUART_UIPCR 0x10 /* Input Port Change (r) */ -#define MCFUART_UACR 0x10 /* Auxiliary Control (w) */ -#define MCFUART_UISR 0x14 /* Interrupt Status (r) */ -#define MCFUART_UIMR 0x14 /* Interrupt Mask (w) */ -#define MCFUART_UBG1 0x18 /* Baud Rate MSB (r/w) */ -#define MCFUART_UBG2 0x1c /* Baud Rate LSB (r/w) */ -#ifdef CONFIG_M5272 -#define MCFUART_UTF 0x28 /* Transmitter FIFO (r/w) */ -#define MCFUART_URF 0x2c /* Receiver FIFO (r/w) */ -#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */ -#else -#define MCFUART_UIVR 0x30 /* Interrupt Vector (r/w) */ -#endif -#define MCFUART_UIPR 0x34 /* Input Port (r) */ -#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */ -#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */ - - -/* - * Define bit flags in Mode Register 1 (MR1). - */ -#define MCFUART_MR1_RXRTS 0x80 /* Auto RTS flow control */ -#define MCFUART_MR1_RXIRQFULL 0x40 /* RX IRQ type FULL */ -#define MCFUART_MR1_RXIRQRDY 0x00 /* RX IRQ type RDY */ -#define MCFUART_MR1_RXERRBLOCK 0x20 /* RX block error mode */ -#define MCFUART_MR1_RXERRCHAR 0x00 /* RX char error mode */ - -#define MCFUART_MR1_PARITYNONE 0x10 /* No parity */ -#define MCFUART_MR1_PARITYEVEN 0x00 /* Even parity */ -#define MCFUART_MR1_PARITYODD 0x04 /* Odd parity */ -#define MCFUART_MR1_PARITYSPACE 0x08 /* Space parity */ -#define MCFUART_MR1_PARITYMARK 0x0c /* Mark parity */ - -#define MCFUART_MR1_CS5 0x00 /* 5 bits per char */ -#define MCFUART_MR1_CS6 0x01 /* 6 bits per char */ -#define MCFUART_MR1_CS7 0x02 /* 7 bits per char */ -#define MCFUART_MR1_CS8 0x03 /* 8 bits per char */ - -/* - * Define bit flags in Mode Register 2 (MR2). - */ -#define MCFUART_MR2_LOOPBACK 0x80 /* Loopback mode */ -#define MCFUART_MR2_REMOTELOOP 0xc0 /* Remote loopback mode */ -#define MCFUART_MR2_AUTOECHO 0x40 /* Automatic echo */ -#define MCFUART_MR2_TXRTS 0x20 /* Assert RTS on TX */ -#define MCFUART_MR2_TXCTS 0x10 /* Auto CTS flow control */ - -#define MCFUART_MR2_STOP1 0x07 /* 1 stop bit */ -#define MCFUART_MR2_STOP15 0x08 /* 1.5 stop bits */ -#define MCFUART_MR2_STOP2 0x0f /* 2 stop bits */ - -/* - * Define bit flags in Status Register (USR). - */ -#define MCFUART_USR_RXBREAK 0x80 /* Received BREAK */ -#define MCFUART_USR_RXFRAMING 0x40 /* Received framing error */ -#define MCFUART_USR_RXPARITY 0x20 /* Received parity error */ -#define MCFUART_USR_RXOVERRUN 0x10 /* Received overrun error */ -#define MCFUART_USR_TXEMPTY 0x08 /* Transmitter empty */ -#define MCFUART_USR_TXREADY 0x04 /* Transmitter ready */ -#define MCFUART_USR_RXFULL 0x02 /* Receiver full */ -#define MCFUART_USR_RXREADY 0x01 /* Receiver ready */ - -#define MCFUART_USR_RXERR (MCFUART_USR_RXBREAK | MCFUART_USR_RXFRAMING | \ - MCFUART_USR_RXPARITY | MCFUART_USR_RXOVERRUN) - -/* - * Define bit flags in Clock Select Register (UCSR). - */ -#define MCFUART_UCSR_RXCLKTIMER 0xd0 /* RX clock is timer */ -#define MCFUART_UCSR_RXCLKEXT16 0xe0 /* RX clock is external x16 */ -#define MCFUART_UCSR_RXCLKEXT1 0xf0 /* RX clock is external x1 */ - -#define MCFUART_UCSR_TXCLKTIMER 0x0d /* TX clock is timer */ -#define MCFUART_UCSR_TXCLKEXT16 0x0e /* TX clock is external x16 */ -#define MCFUART_UCSR_TXCLKEXT1 0x0f /* TX clock is external x1 */ - -/* - * Define bit flags in Command Register (UCR). - */ -#define MCFUART_UCR_CMDNULL 0x00 /* No command */ -#define MCFUART_UCR_CMDRESETMRPTR 0x10 /* Reset MR pointer */ -#define MCFUART_UCR_CMDRESETRX 0x20 /* Reset receiver */ -#define MCFUART_UCR_CMDRESETTX 0x30 /* Reset transmitter */ -#define MCFUART_UCR_CMDRESETERR 0x40 /* Reset error status */ -#define MCFUART_UCR_CMDRESETBREAK 0x50 /* Reset BREAK change */ -#define MCFUART_UCR_CMDBREAKSTART 0x60 /* Start BREAK */ -#define MCFUART_UCR_CMDBREAKSTOP 0x70 /* Stop BREAK */ - -#define MCFUART_UCR_TXNULL 0x00 /* No TX command */ -#define MCFUART_UCR_TXENABLE 0x04 /* Enable TX */ -#define MCFUART_UCR_TXDISABLE 0x08 /* Disable TX */ -#define MCFUART_UCR_RXNULL 0x00 /* No RX command */ -#define MCFUART_UCR_RXENABLE 0x01 /* Enable RX */ -#define MCFUART_UCR_RXDISABLE 0x02 /* Disable RX */ - -/* - * Define bit flags in Input Port Change Register (UIPCR). - */ -#define MCFUART_UIPCR_CTSCOS 0x10 /* CTS change of state */ -#define MCFUART_UIPCR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Input Port Register (UIP). - */ -#define MCFUART_UIPR_CTS 0x01 /* CTS value */ - -/* - * Define bit flags in Output Port Registers (UOP). - * Clear bit by writing to UOP0, set by writing to UOP1. - */ -#define MCFUART_UOP_RTS 0x01 /* RTS set or clear */ - -/* - * Define bit flags in the Auxiliary Control Register (UACR). - */ -#define MCFUART_UACR_IEC 0x01 /* Input enable control */ - -/* - * Define bit flags in Interrupt Status Register (UISR). - * These same bits are used for the Interrupt Mask Register (UIMR). - */ -#define MCFUART_UIR_COS 0x80 /* Change of state (CTS) */ -#define MCFUART_UIR_DELTABREAK 0x04 /* Break start or stop */ -#define MCFUART_UIR_RXREADY 0x02 /* Receiver ready */ -#define MCFUART_UIR_TXREADY 0x01 /* Transmitter ready */ - -#ifdef CONFIG_M5272 -/* - * Define bit flags in the Transmitter FIFO Register (UTF). - */ -#define MCFUART_UTF_TXB 0x1f /* Transmitter data level */ -#define MCFUART_UTF_FULL 0x20 /* Transmitter fifo full */ -#define MCFUART_UTF_TXS 0xc0 /* Transmitter status */ - -/* - * Define bit flags in the Receiver FIFO Register (URF). - */ -#define MCFUART_URF_RXB 0x1f /* Receiver data level */ -#define MCFUART_URF_FULL 0x20 /* Receiver fifo full */ -#define MCFUART_URF_RXS 0xc0 /* Receiver status */ -#endif - -/****************************************************************************/ -#endif /* mcfuart_h */ diff --git a/include/asm-m68knommu/mcfwdebug.h b/include/asm-m68knommu/mcfwdebug.h deleted file mode 100644 index 27f70e45d700..000000000000 --- a/include/asm-m68knommu/mcfwdebug.h +++ /dev/null @@ -1,118 +0,0 @@ -/****************************************************************************/ - -/* - * mcfdebug.h -- ColdFire Debug Module support. - * - * (C) Copyright 2001, Lineo Inc. (www.lineo.com) - */ - -/****************************************************************************/ -#ifndef mcfdebug_h -#define mcfdebug_h -/****************************************************************************/ - -/* Define the debug module registers */ -#define MCFDEBUG_CSR 0x0 /* Configuration status */ -#define MCFDEBUG_BAAR 0x5 /* BDM address attribute */ -#define MCFDEBUG_AATR 0x6 /* Address attribute trigger */ -#define MCFDEBUG_TDR 0x7 /* Trigger definition */ -#define MCFDEBUG_PBR 0x8 /* PC breakpoint */ -#define MCFDEBUG_PBMR 0x9 /* PC breakpoint mask */ -#define MCFDEBUG_ABHR 0xc /* High address breakpoint */ -#define MCFDEBUG_ABLR 0xd /* Low address breakpoint */ -#define MCFDEBUG_DBR 0xe /* Data breakpoint */ -#define MCFDEBUG_DBMR 0xf /* Data breakpoint mask */ - -/* Define some handy constants for the trigger definition register */ -#define MCFDEBUG_TDR_TRC_DISP 0x00000000 /* display on DDATA only */ -#define MCFDEBUG_TDR_TRC_HALT 0x40000000 /* Processor halt on BP */ -#define MCFDEBUG_TDR_TRC_INTR 0x80000000 /* Debug intr on BP */ -#define MCFDEBUG_TDR_LXT1 0x00004000 /* TDR level 1 */ -#define MCFDEBUG_TDR_LXT2 0x00008000 /* TDR level 2 */ -#define MCFDEBUG_TDR_EBL1 0x00002000 /* Enable breakpoint level 1 */ -#define MCFDEBUG_TDR_EBL2 0x20000000 /* Enable breakpoint level 2 */ -#define MCFDEBUG_TDR_EDLW1 0x00001000 /* Enable data BP longword */ -#define MCFDEBUG_TDR_EDLW2 0x10000000 -#define MCFDEBUG_TDR_EDWL1 0x00000800 /* Enable data BP lower word */ -#define MCFDEBUG_TDR_EDWL2 0x08000000 -#define MCFDEBUG_TDR_EDWU1 0x00000400 /* Enable data BP upper word */ -#define MCFDEBUG_TDR_EDWU2 0x04000000 -#define MCFDEBUG_TDR_EDLL1 0x00000200 /* Enable data BP low low byte */ -#define MCFDEBUG_TDR_EDLL2 0x02000000 -#define MCFDEBUG_TDR_EDLM1 0x00000100 /* Enable data BP low mid byte */ -#define MCFDEBUG_TDR_EDLM2 0x01000000 -#define MCFDEBUG_TDR_EDUM1 0x00000080 /* Enable data BP up mid byte */ -#define MCFDEBUG_TDR_EDUM2 0x00800000 -#define MCFDEBUG_TDR_EDUU1 0x00000040 /* Enable data BP up up byte */ -#define MCFDEBUG_TDR_EDUU2 0x00400000 -#define MCFDEBUG_TDR_DI1 0x00000020 /* Data BP invert */ -#define MCFDEBUG_TDR_DI2 0x00200000 -#define MCFDEBUG_TDR_EAI1 0x00000010 /* Enable address BP inverted */ -#define MCFDEBUG_TDR_EAI2 0x00100000 -#define MCFDEBUG_TDR_EAR1 0x00000008 /* Enable address BP range */ -#define MCFDEBUG_TDR_EAR2 0x00080000 -#define MCFDEBUG_TDR_EAL1 0x00000004 /* Enable address BP low */ -#define MCFDEBUG_TDR_EAL2 0x00040000 -#define MCFDEBUG_TDR_EPC1 0x00000002 /* Enable PC BP */ -#define MCFDEBUG_TDR_EPC2 0x00020000 -#define MCFDEBUG_TDR_PCI1 0x00000001 /* PC BP invert */ -#define MCFDEBUG_TDR_PCI2 0x00010000 - -/* Constants for the address attribute trigger register */ -#define MCFDEBUG_AAR_RESET 0x00000005 -/* Fields not yet implemented */ - -/* And some definitions for the writable sections of the CSR */ -#define MCFDEBUG_CSR_RESET 0x00100000 -#define MCFDEBUG_CSR_PSTCLK 0x00020000 /* PSTCLK disable */ -#define MCFDEBUG_CSR_IPW 0x00010000 /* Inhibit processor writes */ -#define MCFDEBUG_CSR_MAP 0x00008000 /* Processor refs in emul mode */ -#define MCFDEBUG_CSR_TRC 0x00004000 /* Emul mode on trace exception */ -#define MCFDEBUG_CSR_EMU 0x00002000 /* Force emulation mode */ -#define MCFDEBUG_CSR_DDC_READ 0x00000800 /* Debug data control */ -#define MCFDEBUG_CSR_DDC_WRITE 0x00001000 -#define MCFDEBUG_CSR_UHE 0x00000400 /* User mode halt enable */ -#define MCFDEBUG_CSR_BTB0 0x00000000 /* Branch target 0 bytes */ -#define MCFDEBUG_CSR_BTB2 0x00000100 /* Branch target 2 bytes */ -#define MCFDEBUG_CSR_BTB3 0x00000200 /* Branch target 3 bytes */ -#define MCFDEBUG_CSR_BTB4 0x00000300 /* Branch target 4 bytes */ -#define MCFDEBUG_CSR_NPL 0x00000040 /* Non-pipelined mode */ -#define MCFDEBUG_CSR_SSM 0x00000010 /* Single step mode */ - -/* Constants for the BDM address attribute register */ -#define MCFDEBUG_BAAR_RESET 0x00000005 -/* Fields not yet implemented */ - - -/* This routine wrappers up the wdebug asm instruction so that the register - * and value can be relatively easily specified. The biggest hassle here is - * that the debug module instructions (2 longs) must be long word aligned and - * some pointer fiddling is performed to ensure this. - */ -static inline void wdebug(int reg, unsigned long data) { - unsigned short dbg_spc[6]; - unsigned short *dbg; - - // Force alignment to long word boundary - dbg = (unsigned short *)((((unsigned long)dbg_spc) + 3) & 0xfffffffc); - - // Build up the debug instruction - dbg[0] = 0x2c80 | (reg & 0xf); - dbg[1] = (data >> 16) & 0xffff; - dbg[2] = data & 0xffff; - dbg[3] = 0; - - // Perform the wdebug instruction -#if 0 - // This strain is for gas which doesn't have the wdebug instructions defined - asm( "move.l %0, %%a0\n\t" - ".word 0xfbd0\n\t" - ".word 0x0003\n\t" - :: "g" (dbg) : "a0"); -#else - // And this is for when it does - asm( "wdebug (%0)" :: "a" (dbg)); -#endif -} - -#endif diff --git a/include/asm-m68knommu/md.h b/include/asm-m68knommu/md.h deleted file mode 100644 index d810c78de5ff..000000000000 --- a/include/asm-m68knommu/md.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/mman.h b/include/asm-m68knommu/mman.h deleted file mode 100644 index 4846c682efed..000000000000 --- a/include/asm-m68knommu/mman.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/mmu.h b/include/asm-m68knommu/mmu.h deleted file mode 100644 index 5fa6b68353ba..000000000000 --- a/include/asm-m68knommu/mmu.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __M68KNOMMU_MMU_H -#define __M68KNOMMU_MMU_H - -/* Copyright (C) 2002, David McCullough */ - -typedef struct { - struct vm_list_struct *vmlist; - unsigned long end_brk; -} mm_context_t; - -#endif /* __M68KNOMMU_MMU_H */ diff --git a/include/asm-m68knommu/mmu_context.h b/include/asm-m68knommu/mmu_context.h deleted file mode 100644 index 9ccee4278c97..000000000000 --- a/include/asm-m68knommu/mmu_context.h +++ /dev/null @@ -1,33 +0,0 @@ -#ifndef __M68KNOMMU_MMU_CONTEXT_H -#define __M68KNOMMU_MMU_CONTEXT_H - -#include -#include -#include -#include - -static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) -{ -} - -static inline int -init_new_context(struct task_struct *tsk, struct mm_struct *mm) -{ - // mm->context = virt_to_phys(mm->pgd); - return(0); -} - -#define destroy_context(mm) do { } while(0) - -static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk) -{ -} - -#define deactivate_mm(tsk,mm) do { } while (0) - -static inline void activate_mm(struct mm_struct *prev_mm, - struct mm_struct *next_mm) -{ -} - -#endif diff --git a/include/asm-m68knommu/module.h b/include/asm-m68knommu/module.h deleted file mode 100644 index 2e45ab50b232..000000000000 --- a/include/asm-m68knommu/module.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef ASM_M68KNOMMU_MODULE_H -#define ASM_M68KNOMMU_MODULE_H - -struct mod_arch_specific { -}; - -#define Elf_Shdr Elf32_Shdr -#define Elf_Sym Elf32_Sym -#define Elf_Ehdr Elf32_Ehdr - -#endif /* ASM_M68KNOMMU_MODULE_H */ diff --git a/include/asm-m68knommu/movs.h b/include/asm-m68knommu/movs.h deleted file mode 100644 index 81a16779e833..000000000000 --- a/include/asm-m68knommu/movs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/msgbuf.h b/include/asm-m68knommu/msgbuf.h deleted file mode 100644 index bdfadec4d52d..000000000000 --- a/include/asm-m68knommu/msgbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/mutex.h b/include/asm-m68knommu/mutex.h deleted file mode 100644 index 458c1f7fbc18..000000000000 --- a/include/asm-m68knommu/mutex.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Pull in the generic implementation for the mutex fastpath. - * - * TODO: implement optimized primitives instead, or leave the generic - * implementation in place, or pick the atomic_xchg() based generic - * implementation. (see asm-generic/mutex-xchg.h for details) - */ - -#include diff --git a/include/asm-m68knommu/nettel.h b/include/asm-m68knommu/nettel.h deleted file mode 100644 index 0299f6a2deeb..000000000000 --- a/include/asm-m68knommu/nettel.h +++ /dev/null @@ -1,108 +0,0 @@ -/****************************************************************************/ - -/* - * nettel.h -- Lineo (formerly Moreton Bay) NETtel support. - * - * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com) - * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com) - * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com) - */ - -/****************************************************************************/ -#ifndef nettel_h -#define nettel_h -/****************************************************************************/ - - -/****************************************************************************/ -#ifdef CONFIG_NETtel -/****************************************************************************/ - -#ifdef CONFIG_COLDFIRE -#include -#include -#endif - -/*---------------------------------------------------------------------------*/ -#if defined(CONFIG_M5307) -/* - * NETtel/5307 based hardware first. DTR/DCD lines are wired to - * GPIO lines. Most of the LED's are driver through a latch - * connected to CS2. - */ -#define MCFPP_DCD1 0x0001 -#define MCFPP_DCD0 0x0002 -#define MCFPP_DTR1 0x0004 -#define MCFPP_DTR0 0x0008 - -#define NETtel_LEDADDR 0x30400000 - -#ifndef __ASSEMBLY__ - -extern volatile unsigned short ppdata; - -/* - * These functions defined to give quasi generic access to the - * PPIO bits used for DTR/DCD. - */ -static __inline__ unsigned int mcf_getppdata(void) -{ - volatile unsigned short *pp; - pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); - return((unsigned int) *pp); -} - -static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) -{ - volatile unsigned short *pp; - pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PADAT); - ppdata = (ppdata & ~mask) | bits; - *pp = ppdata; -} -#endif - -/*---------------------------------------------------------------------------*/ -#elif defined(CONFIG_M5206e) -/* - * NETtel/5206e based hardware has leds on latch on CS3. - * No support modem for lines?? - */ -#define NETtel_LEDADDR 0x50000000 - -/*---------------------------------------------------------------------------*/ -#elif defined(CONFIG_M5272) -/* - * NETtel/5272 based hardware. DTR/DCD lines are wired to GPB lines. - */ -#define MCFPP_DCD0 0x0080 -#define MCFPP_DCD1 0x0000 /* Port 1 no DCD support */ -#define MCFPP_DTR0 0x0040 -#define MCFPP_DTR1 0x0000 /* Port 1 no DTR support */ - -#ifndef __ASSEMBLY__ -/* - * These functions defined to give quasi generic access to the - * PPIO bits used for DTR/DCD. - */ -static __inline__ unsigned int mcf_getppdata(void) -{ - volatile unsigned short *pp; - pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); - return((unsigned int) *pp); -} - -static __inline__ void mcf_setppdata(unsigned int mask, unsigned int bits) -{ - volatile unsigned short *pp; - pp = (volatile unsigned short *) (MCF_MBAR + MCFSIM_PBDAT); - *pp = (*pp & ~mask) | bits; -} -#endif - -#endif -/*---------------------------------------------------------------------------*/ - -/****************************************************************************/ -#endif /* CONFIG_NETtel */ -/****************************************************************************/ -#endif /* nettel_h */ diff --git a/include/asm-m68knommu/openprom.h b/include/asm-m68knommu/openprom.h deleted file mode 100644 index fdba7953ff9f..000000000000 --- a/include/asm-m68knommu/openprom.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/oplib.h b/include/asm-m68knommu/oplib.h deleted file mode 100644 index ce079dc332d9..000000000000 --- a/include/asm-m68knommu/oplib.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/page.h b/include/asm-m68knommu/page.h deleted file mode 100644 index 3a1ede4544cb..000000000000 --- a/include/asm-m68knommu/page.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef _M68KNOMMU_PAGE_H -#define _M68KNOMMU_PAGE_H - -/* PAGE_SHIFT determines the page size */ - -#define PAGE_SHIFT (12) -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define PAGE_MASK (~(PAGE_SIZE-1)) - -#include - -#ifndef __ASSEMBLY__ - -#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) -#define free_user_page(page, addr) free_page(addr) - -#define clear_page(page) memset((page), 0, PAGE_SIZE) -#define copy_page(to,from) memcpy((to), (from), PAGE_SIZE) - -#define clear_user_page(page, vaddr, pg) clear_page(page) -#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) - -#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \ - alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) -#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE - -/* - * These are used to make use of C type-checking.. - */ -typedef struct { unsigned long pte; } pte_t; -typedef struct { unsigned long pmd[16]; } pmd_t; -typedef struct { unsigned long pgd; } pgd_t; -typedef struct { unsigned long pgprot; } pgprot_t; -typedef struct page *pgtable_t; - -#define pte_val(x) ((x).pte) -#define pmd_val(x) ((&x)->pmd[0]) -#define pgd_val(x) ((x).pgd) -#define pgprot_val(x) ((x).pgprot) - -#define __pte(x) ((pte_t) { (x) } ) -#define __pmd(x) ((pmd_t) { (x) } ) -#define __pgd(x) ((pgd_t) { (x) } ) -#define __pgprot(x) ((pgprot_t) { (x) } ) - -extern unsigned long memory_start; -extern unsigned long memory_end; - -#endif /* !__ASSEMBLY__ */ - -#include - -#define PAGE_OFFSET (PAGE_OFFSET_RAW) - -#ifndef __ASSEMBLY__ - -#define __pa(vaddr) virt_to_phys((void *)(vaddr)) -#define __va(paddr) phys_to_virt((unsigned long)(paddr)) - -#define virt_to_pfn(kaddr) (__pa(kaddr) >> PAGE_SHIFT) -#define pfn_to_virt(pfn) __va((pfn) << PAGE_SHIFT) - -#define virt_to_page(addr) (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)) -#define page_to_virt(page) ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET) - -#define pfn_to_page(pfn) virt_to_page(pfn_to_virt(pfn)) -#define page_to_pfn(page) virt_to_pfn(page_to_virt(page)) -#define pfn_valid(pfn) ((pfn) < max_mapnr) - -#define virt_addr_valid(kaddr) (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \ - ((void *)(kaddr) < (void *)memory_end)) - -#endif /* __ASSEMBLY__ */ - -#include - -#endif /* _M68KNOMMU_PAGE_H */ diff --git a/include/asm-m68knommu/page_offset.h b/include/asm-m68knommu/page_offset.h deleted file mode 100644 index d4e73e0ba646..000000000000 --- a/include/asm-m68knommu/page_offset.h +++ /dev/null @@ -1,5 +0,0 @@ - - -/* This handles the memory map.. */ -#define PAGE_OFFSET_RAW CONFIG_RAMBASE - diff --git a/include/asm-m68knommu/param.h b/include/asm-m68knommu/param.h deleted file mode 100644 index 6044397adb64..000000000000 --- a/include/asm-m68knommu/param.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _M68KNOMMU_PARAM_H -#define _M68KNOMMU_PARAM_H - -#ifdef __KERNEL__ -#define HZ CONFIG_HZ -#define USER_HZ HZ -#define CLOCKS_PER_SEC (USER_HZ) -#endif - -#ifndef HZ -#define HZ 100 -#endif - -#define EXEC_PAGESIZE 4096 - -#ifndef NOGROUP -#define NOGROUP (-1) -#endif - -#define MAXHOSTNAMELEN 64 /* max length of hostname */ - -#endif /* _M68KNOMMU_PARAM_H */ diff --git a/include/asm-m68knommu/pci.h b/include/asm-m68knommu/pci.h deleted file mode 100644 index a13f3cc87451..000000000000 --- a/include/asm-m68knommu/pci.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef M68KNOMMU_PCI_H -#define M68KNOMMU_PCI_H - -#include - -#ifdef CONFIG_COMEMPCI -/* - * These are pretty much arbitary with the CoMEM implementation. - * We have the whole address space to ourselves. - */ -#define PCIBIOS_MIN_IO 0x100 -#define PCIBIOS_MIN_MEM 0x00010000 - -#define pcibios_scan_all_fns(a, b) 0 - -/* - * Return whether the given PCI device DMA address mask can - * be supported properly. For example, if your device can - * only drive the low 24-bits during PCI bus mastering, then - * you would pass 0x00ffffff as the mask to this function. - */ -static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask) -{ - return 1; -} - -#endif /* CONFIG_COMEMPCI */ - -#endif /* M68KNOMMU_PCI_H */ diff --git a/include/asm-m68knommu/percpu.h b/include/asm-m68knommu/percpu.h deleted file mode 100644 index 5de72c327efd..000000000000 --- a/include/asm-m68knommu/percpu.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef __ARCH_M68KNOMMU_PERCPU__ -#define __ARCH_M68KNOMMU_PERCPU__ - -#include - -#endif /* __ARCH_M68KNOMMU_PERCPU__ */ diff --git a/include/asm-m68knommu/pgalloc.h b/include/asm-m68knommu/pgalloc.h deleted file mode 100644 index d6352f671ec0..000000000000 --- a/include/asm-m68knommu/pgalloc.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _M68KNOMMU_PGALLOC_H -#define _M68KNOMMU_PGALLOC_H - -#include - -#define check_pgt_cache() do { } while (0) - -#endif /* _M68KNOMMU_PGALLOC_H */ diff --git a/include/asm-m68knommu/pgtable.h b/include/asm-m68knommu/pgtable.h deleted file mode 100644 index 46251016e821..000000000000 --- a/include/asm-m68knommu/pgtable.h +++ /dev/null @@ -1,70 +0,0 @@ -#ifndef _M68KNOMMU_PGTABLE_H -#define _M68KNOMMU_PGTABLE_H - -#include - -/* - * (C) Copyright 2000-2002, Greg Ungerer - */ - -#include -#include -#include -#include - -/* - * Trivial page table functions. - */ -#define pgd_present(pgd) (1) -#define pgd_none(pgd) (0) -#define pgd_bad(pgd) (0) -#define pgd_clear(pgdp) -#define kern_addr_valid(addr) (1) -#define pmd_offset(a, b) ((void *)0) - -#define PAGE_NONE __pgprot(0) -#define PAGE_SHARED __pgprot(0) -#define PAGE_COPY __pgprot(0) -#define PAGE_READONLY __pgprot(0) -#define PAGE_KERNEL __pgprot(0) - -extern void paging_init(void); -#define swapper_pg_dir ((pgd_t *) 0) - -#define __swp_type(x) (0) -#define __swp_offset(x) (0) -#define __swp_entry(typ,off) ((swp_entry_t) { ((typ) | ((off) << 7)) }) -#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) -#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) - -static inline int pte_file(pte_t pte) { return 0; } - -/* - * ZERO_PAGE is a global shared page that is always zero: used - * for zero-mapped memory areas etc.. - */ -#define ZERO_PAGE(vaddr) (virt_to_page(0)) - -/* - * These would be in other places but having them here reduces the diffs. - */ -extern unsigned int kobjsize(const void *objp); - -/* - * No page table caches to initialise. - */ -#define pgtable_cache_init() do { } while (0) - -#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ - remap_pfn_range(vma, vaddr, pfn, size, prot) - -/* - * All 32bit addresses are effectively valid for vmalloc... - * Sort of meaningless for non-VM targets. - */ -#define VMALLOC_START 0 -#define VMALLOC_END 0xffffffff - -#include - -#endif /* _M68KNOMMU_PGTABLE_H */ diff --git a/include/asm-m68knommu/poll.h b/include/asm-m68knommu/poll.h deleted file mode 100644 index ee1b6cb549ca..000000000000 --- a/include/asm-m68knommu/poll.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/posix_types.h b/include/asm-m68knommu/posix_types.h deleted file mode 100644 index 6205fb9392a3..000000000000 --- a/include/asm-m68knommu/posix_types.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/processor.h b/include/asm-m68knommu/processor.h deleted file mode 100644 index 91cba18acdd3..000000000000 --- a/include/asm-m68knommu/processor.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * include/asm-m68knommu/processor.h - * - * Copyright (C) 1995 Hamish Macdonald - */ - -#ifndef __ASM_M68K_PROCESSOR_H -#define __ASM_M68K_PROCESSOR_H - -/* - * Default implementation of macro that returns current - * instruction pointer ("program counter"). - */ -#define current_text_addr() ({ __label__ _l; _l: &&_l;}) - -#include -#include -#include -#include -#include -#include -#include - -static inline unsigned long rdusp(void) -{ -#ifdef CONFIG_COLDFIRE - extern unsigned int sw_usp; - return(sw_usp); -#else - unsigned long usp; - __asm__ __volatile__("move %/usp,%0" : "=a" (usp)); - return usp; -#endif -} - -static inline void wrusp(unsigned long usp) -{ -#ifdef CONFIG_COLDFIRE - extern unsigned int sw_usp; - sw_usp = usp; -#else - __asm__ __volatile__("move %0,%/usp" : : "a" (usp)); -#endif -} - -/* - * User space process size: 3.75GB. This is hardcoded into a few places, - * so don't change it unless you know what you are doing. - */ -#define TASK_SIZE (0xF0000000UL) - -/* - * This decides where the kernel will search for a free chunk of vm - * space during mmap's. We won't be using it - */ -#define TASK_UNMAPPED_BASE 0 - -/* - * if you change this structure, you must change the code and offsets - * in m68k/machasm.S - */ - -struct thread_struct { - unsigned long ksp; /* kernel stack pointer */ - unsigned long usp; /* user stack pointer */ - unsigned short sr; /* saved status register */ - unsigned short fs; /* saved fs (sfc, dfc) */ - unsigned long crp[2]; /* cpu root pointer */ - unsigned long esp0; /* points to SR of stack frame */ - unsigned long fp[8*3]; - unsigned long fpcntl[3]; /* fp control regs */ - unsigned char fpstate[FPSTATESIZE]; /* floating point state */ -}; - -#define INIT_THREAD { \ - sizeof(init_stack) + (unsigned long) init_stack, 0, \ - PS_S, __KERNEL_DS, \ - {0, 0}, 0, {0,}, {0, 0, 0}, {0,}, \ -} - -/* - * Coldfire stacks need to be re-aligned on trap exit, conventional - * 68k can handle this case cleanly. - */ -#if defined(CONFIG_COLDFIRE) -#define reformat(_regs) do { (_regs)->format = 0x4; } while(0) -#else -#define reformat(_regs) do { } while (0) -#endif - -/* - * Do necessary setup to start up a newly executed thread. - * - * pass the data segment into user programs if it exists, - * it can't hurt anything as far as I can tell - */ -#define start_thread(_regs, _pc, _usp) \ -do { \ - set_fs(USER_DS); /* reads from user space */ \ - (_regs)->pc = (_pc); \ - ((struct switch_stack *)(_regs))[-1].a6 = 0; \ - reformat(_regs); \ - if (current->mm) \ - (_regs)->d5 = current->mm->start_data; \ - (_regs)->sr &= ~0x2000; \ - wrusp(_usp); \ -} while(0) - -/* Forward declaration, a strange C thing */ -struct task_struct; - -/* Free all resources held by a thread. */ -static inline void release_thread(struct task_struct *dead_task) -{ -} - -/* Prepare to copy thread state - unlazy all lazy status */ -#define prepare_to_copy(tsk) do { } while (0) - -extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); - -/* - * Free current thread data structures etc.. - */ -static inline void exit_thread(void) -{ -} - -unsigned long thread_saved_pc(struct task_struct *tsk); -unsigned long get_wchan(struct task_struct *p); - -#define KSTK_EIP(tsk) \ - ({ \ - unsigned long eip = 0; \ - if ((tsk)->thread.esp0 > PAGE_SIZE && \ - (virt_addr_valid((tsk)->thread.esp0))) \ - eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \ - eip; }) -#define KSTK_ESP(tsk) ((tsk) == current ? rdusp() : (tsk)->thread.usp) - -#define cpu_relax() barrier() - -#endif diff --git a/include/asm-m68knommu/ptrace.h b/include/asm-m68knommu/ptrace.h deleted file mode 100644 index 8c9194b98548..000000000000 --- a/include/asm-m68knommu/ptrace.h +++ /dev/null @@ -1,87 +0,0 @@ -#ifndef _M68K_PTRACE_H -#define _M68K_PTRACE_H - -#define PT_D1 0 -#define PT_D2 1 -#define PT_D3 2 -#define PT_D4 3 -#define PT_D5 4 -#define PT_D6 5 -#define PT_D7 6 -#define PT_A0 7 -#define PT_A1 8 -#define PT_A2 9 -#define PT_A3 10 -#define PT_A4 11 -#define PT_A5 12 -#define PT_A6 13 -#define PT_D0 14 -#define PT_USP 15 -#define PT_ORIG_D0 16 -#define PT_SR 17 -#define PT_PC 18 - -#ifndef __ASSEMBLY__ - -/* this struct defines the way the registers are stored on the - stack during a system call. */ - -struct pt_regs { - long d1; - long d2; - long d3; - long d4; - long d5; - long a0; - long a1; - long a2; - long d0; - long orig_d0; - long stkadj; -#ifdef CONFIG_COLDFIRE - unsigned format : 4; /* frame format specifier */ - unsigned vector : 12; /* vector offset */ - unsigned short sr; - unsigned long pc; -#else - unsigned short sr; - unsigned long pc; - unsigned format : 4; /* frame format specifier */ - unsigned vector : 12; /* vector offset */ -#endif -}; - -/* - * This is the extended stack used by signal handlers and the context - * switcher: it's pushed after the normal "struct pt_regs". - */ -struct switch_stack { - unsigned long d6; - unsigned long d7; - unsigned long a3; - unsigned long a4; - unsigned long a5; - unsigned long a6; - unsigned long retpc; -}; - -/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ -#define PTRACE_GETREGS 12 -#define PTRACE_SETREGS 13 -#define PTRACE_GETFPREGS 14 -#define PTRACE_SETFPREGS 15 - -#ifdef __KERNEL__ - -#ifndef PS_S -#define PS_S (0x2000) -#define PS_M (0x1000) -#endif - -#define user_mode(regs) (!((regs)->sr & PS_S)) -#define instruction_pointer(regs) ((regs)->pc) -#define profile_pc(regs) instruction_pointer(regs) -extern void show_regs(struct pt_regs *); -#endif /* __KERNEL__ */ -#endif /* __ASSEMBLY__ */ -#endif /* _M68K_PTRACE_H */ diff --git a/include/asm-m68knommu/quicc_simple.h b/include/asm-m68knommu/quicc_simple.h deleted file mode 100644 index c3636932d4bc..000000000000 --- a/include/asm-m68knommu/quicc_simple.h +++ /dev/null @@ -1,52 +0,0 @@ -/*********************************** - * $Id: quicc_simple.h,v 1.1 2002/03/02 15:01:10 gerg Exp $ - *********************************** - * - *************************************** - * Simple drivers common header - *************************************** - */ - -#ifndef __SIMPLE_H -#define __SIMPLE_H - -/* #include "quicc.h" */ - -#define GLB_SCC_0 0 -#define GLB_SCC_1 1 -#define GLB_SCC_2 2 -#define GLB_SCC_3 3 - -typedef void (int_routine)(unsigned short interrupt_event); -typedef int_routine *int_routine_ptr; -typedef void *(alloc_routine)(int length); -typedef void (free_routine)(int scc_num, int channel_num, void *buf); -typedef void (store_rx_buffer_routine)(int scc_num, int channel_num, void *buff, int length); -typedef int (handle_tx_error_routine)(int scc_num, int channel_num, QUICC_BD *tbd); -typedef void (handle_rx_error_routine)(int scc_num, int channel_num, QUICC_BD *rbd); -typedef void (handle_lost_error_routine)(int scc_num, int channel_num); - -/* user defined functions for global errors */ -typedef void (handle_glob_overrun_routine)(int scc_number); -typedef void (handle_glob_underrun_routine)(int scc_number); -typedef void (glob_intr_q_overflow_routine)(int scc_number); - -/* - * General initialization and command routines - */ -void quicc_issue_cmd (unsigned short cmd, int scc_num); -void quicc_init(void); -void quicc_scc_init(int scc_number, int number_of_rx_buf, int number_of_tx_buf); -void quicc_smc_init(int smc_number, int number_of_rx_buf, int number_of_tx_buf); -void quicc_scc_start(int scc_num); -void quicc_scc_loopback(int scc_num); - -/* Interrupt enable/disable routines for critical pieces of code*/ -unsigned short IntrDis(void); -void IntrEna(unsigned short old_sr); - -/* For debugging */ -void print_rbd(int scc_num); -void print_tbd(int scc_num); - -#endif diff --git a/include/asm-m68knommu/resource.h b/include/asm-m68knommu/resource.h deleted file mode 100644 index 7fa63d5ea576..000000000000 --- a/include/asm-m68knommu/resource.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/rtc.h b/include/asm-m68knommu/rtc.h deleted file mode 100644 index eaf18ec83c8e..000000000000 --- a/include/asm-m68knommu/rtc.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/scatterlist.h b/include/asm-m68knommu/scatterlist.h deleted file mode 100644 index afc4788b0d2c..000000000000 --- a/include/asm-m68knommu/scatterlist.h +++ /dev/null @@ -1,22 +0,0 @@ -#ifndef _M68KNOMMU_SCATTERLIST_H -#define _M68KNOMMU_SCATTERLIST_H - -#include -#include - -struct scatterlist { -#ifdef CONFIG_DEBUG_SG - unsigned long sg_magic; -#endif - unsigned long page_link; - unsigned int offset; - dma_addr_t dma_address; - unsigned int length; -}; - -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - -#define ISA_DMA_THRESHOLD (0xffffffff) - -#endif /* !(_M68KNOMMU_SCATTERLIST_H) */ diff --git a/include/asm-m68knommu/sections.h b/include/asm-m68knommu/sections.h deleted file mode 100644 index dd0ecb98ec08..000000000000 --- a/include/asm-m68knommu/sections.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _M68KNOMMU_SECTIONS_H -#define _M68KNOMMU_SECTIONS_H - -/* nothing to see, move along */ -#include - -#endif diff --git a/include/asm-m68knommu/segment.h b/include/asm-m68knommu/segment.h deleted file mode 100644 index 42318ebec7ec..000000000000 --- a/include/asm-m68knommu/segment.h +++ /dev/null @@ -1,51 +0,0 @@ -#ifndef _M68K_SEGMENT_H -#define _M68K_SEGMENT_H - -/* define constants */ -/* Address spaces (FC0-FC2) */ -#define USER_DATA (1) -#ifndef __USER_DS -#define __USER_DS (USER_DATA) -#endif -#define USER_PROGRAM (2) -#define SUPER_DATA (5) -#ifndef __KERNEL_DS -#define __KERNEL_DS (SUPER_DATA) -#endif -#define SUPER_PROGRAM (6) -#define CPU_SPACE (7) - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long seg; -} mm_segment_t; - -#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) -#define USER_DS MAKE_MM_SEG(__USER_DS) -#define KERNEL_DS MAKE_MM_SEG(__KERNEL_DS) - -/* - * Get/set the SFC/DFC registers for MOVES instructions - */ - -static inline mm_segment_t get_fs(void) -{ - return USER_DS; -} - -static inline mm_segment_t get_ds(void) -{ - /* return the supervisor data space code */ - return KERNEL_DS; -} - -static inline void set_fs(mm_segment_t val) -{ -} - -#define segment_eq(a,b) ((a).seg == (b).seg) - -#endif /* __ASSEMBLY__ */ - -#endif /* _M68K_SEGMENT_H */ diff --git a/include/asm-m68knommu/sembuf.h b/include/asm-m68knommu/sembuf.h deleted file mode 100644 index 3a634f9ecf50..000000000000 --- a/include/asm-m68knommu/sembuf.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/setup.h b/include/asm-m68knommu/setup.h deleted file mode 100644 index fb86bb2a6078..000000000000 --- a/include/asm-m68knommu/setup.h +++ /dev/null @@ -1,10 +0,0 @@ -#ifdef __KERNEL__ - -#include - -/* We have a bigger command line buffer. */ -#undef COMMAND_LINE_SIZE - -#endif /* __KERNEL__ */ - -#define COMMAND_LINE_SIZE 512 diff --git a/include/asm-m68knommu/shm.h b/include/asm-m68knommu/shm.h deleted file mode 100644 index cc8e522d9050..000000000000 --- a/include/asm-m68knommu/shm.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/shmbuf.h b/include/asm-m68knommu/shmbuf.h deleted file mode 100644 index bc34cf8eefce..000000000000 --- a/include/asm-m68knommu/shmbuf.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/shmparam.h b/include/asm-m68knommu/shmparam.h deleted file mode 100644 index d7ee69648ebf..000000000000 --- a/include/asm-m68knommu/shmparam.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/sigcontext.h b/include/asm-m68knommu/sigcontext.h deleted file mode 100644 index 36c293fc133d..000000000000 --- a/include/asm-m68knommu/sigcontext.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _ASM_M68KNOMMU_SIGCONTEXT_H -#define _ASM_M68KNOMMU_SIGCONTEXT_H - -struct sigcontext { - unsigned long sc_mask; /* old sigmask */ - unsigned long sc_usp; /* old user stack pointer */ - unsigned long sc_d0; - unsigned long sc_d1; - unsigned long sc_a0; - unsigned long sc_a1; - unsigned long sc_a5; - unsigned short sc_sr; - unsigned long sc_pc; - unsigned short sc_formatvec; -}; - -#endif diff --git a/include/asm-m68knommu/siginfo.h b/include/asm-m68knommu/siginfo.h deleted file mode 100644 index b18e5f4064ae..000000000000 --- a/include/asm-m68knommu/siginfo.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _M68KNOMMU_SIGINFO_H -#define _M68KNOMMU_SIGINFO_H - -#include - -#endif diff --git a/include/asm-m68knommu/signal.h b/include/asm-m68knommu/signal.h deleted file mode 100644 index 216c08be54a0..000000000000 --- a/include/asm-m68knommu/signal.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef _M68KNOMMU_SIGNAL_H -#define _M68KNOMMU_SIGNAL_H - -#include - -/* Avoid too many header ordering problems. */ -struct siginfo; - -#ifdef __KERNEL__ -/* Most things should be clean enough to redefine this at will, if care - is taken to make libc match. */ - -#define _NSIG 64 -#define _NSIG_BPW 32 -#define _NSIG_WORDS (_NSIG / _NSIG_BPW) - -typedef unsigned long old_sigset_t; /* at least 32 bits */ - -typedef struct { - unsigned long sig[_NSIG_WORDS]; -} sigset_t; - -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -#define NSIG 32 -typedef unsigned long sigset_t; - -#endif /* __KERNEL__ */ - -#define SIGHUP 1 -#define SIGINT 2 -#define SIGQUIT 3 -#define SIGILL 4 -#define SIGTRAP 5 -#define SIGABRT 6 -#define SIGIOT 6 -#define SIGBUS 7 -#define SIGFPE 8 -#define SIGKILL 9 -#define SIGUSR1 10 -#define SIGSEGV 11 -#define SIGUSR2 12 -#define SIGPIPE 13 -#define SIGALRM 14 -#define SIGTERM 15 -#define SIGSTKFLT 16 -#define SIGCHLD 17 -#define SIGCONT 18 -#define SIGSTOP 19 -#define SIGTSTP 20 -#define SIGTTIN 21 -#define SIGTTOU 22 -#define SIGURG 23 -#define SIGXCPU 24 -#define SIGXFSZ 25 -#define SIGVTALRM 26 -#define SIGPROF 27 -#define SIGWINCH 28 -#define SIGIO 29 -#define SIGPOLL SIGIO -/* -#define SIGLOST 29 -*/ -#define SIGPWR 30 -#define SIGSYS 31 -#define SIGUNUSED 31 - -/* These should not be considered constants from userland. */ -#define SIGRTMIN 32 -#define SIGRTMAX _NSIG - -/* - * SA_FLAGS values: - * - * SA_ONSTACK indicates that a registered stack_t will be used. - * SA_RESTART flag to get restarting signals (which were the default long ago) - * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. - * SA_RESETHAND clears the handler when the signal is delivered. - * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. - * SA_NODEFER prevents the current signal from being masked in the handler. - * - * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single - * Unix names RESETHAND and NODEFER respectively. - */ -#define SA_NOCLDSTOP 0x00000001 -#define SA_NOCLDWAIT 0x00000002 -#define SA_SIGINFO 0x00000004 -#define SA_ONSTACK 0x08000000 -#define SA_RESTART 0x10000000 -#define SA_NODEFER 0x40000000 -#define SA_RESETHAND 0x80000000 - -#define SA_NOMASK SA_NODEFER -#define SA_ONESHOT SA_RESETHAND - -/* - * sigaltstack controls - */ -#define SS_ONSTACK 1 -#define SS_DISABLE 2 - -#define MINSIGSTKSZ 2048 -#define SIGSTKSZ 8192 - -#include - -#ifdef __KERNEL__ -struct old_sigaction { - __sighandler_t sa_handler; - old_sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -struct sigaction { - __sighandler_t sa_handler; - unsigned long sa_flags; - void (*sa_restorer)(void); - sigset_t sa_mask; /* mask last for extensibility */ -}; - -struct k_sigaction { - struct sigaction sa; -}; -#else -/* Here we must cater to libcs that poke about in kernel headers. */ - -struct sigaction { - union { - __sighandler_t _sa_handler; - void (*_sa_sigaction)(int, struct siginfo *, void *); - } _u; - sigset_t sa_mask; - unsigned long sa_flags; - void (*sa_restorer)(void); -}; - -#define sa_handler _u._sa_handler -#define sa_sigaction _u._sa_sigaction - -#endif /* __KERNEL__ */ - -typedef struct sigaltstack { - void *ss_sp; - int ss_flags; - size_t ss_size; -} stack_t; - -#ifdef __KERNEL__ - -#include -#undef __HAVE_ARCH_SIG_BITOPS - -#define ptrace_signal_deliver(regs, cookie) do { } while (0) - -#endif /* __KERNEL__ */ - -#endif /* _M68KNOMMU_SIGNAL_H */ diff --git a/include/asm-m68knommu/smp.h b/include/asm-m68knommu/smp.h deleted file mode 100644 index 9e9bd7e58922..000000000000 --- a/include/asm-m68knommu/smp.h +++ /dev/null @@ -1 +0,0 @@ -/* nothing required here yet */ diff --git a/include/asm-m68knommu/socket.h b/include/asm-m68knommu/socket.h deleted file mode 100644 index ac5478bf6371..000000000000 --- a/include/asm-m68knommu/socket.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/sockios.h b/include/asm-m68knommu/sockios.h deleted file mode 100644 index dcc6a8900ce2..000000000000 --- a/include/asm-m68knommu/sockios.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/spinlock.h b/include/asm-m68knommu/spinlock.h deleted file mode 100644 index 6bb1f06c4781..000000000000 --- a/include/asm-m68knommu/spinlock.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/stat.h b/include/asm-m68knommu/stat.h deleted file mode 100644 index 3d4b260e7c03..000000000000 --- a/include/asm-m68knommu/stat.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/statfs.h b/include/asm-m68knommu/statfs.h deleted file mode 100644 index 2ce99eaf0970..000000000000 --- a/include/asm-m68knommu/statfs.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/string.h b/include/asm-m68knommu/string.h deleted file mode 100644 index af09e17000fc..000000000000 --- a/include/asm-m68knommu/string.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef _M68KNOMMU_STRING_H_ -#define _M68KNOMMU_STRING_H_ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#include -#include - -#define __HAVE_ARCH_STRCPY -static inline char * strcpy(char * dest,const char *src) -{ - char *xdest = dest; - - __asm__ __volatile__ - ("1:\tmoveb %1@+,%0@+\n\t" - "jne 1b" - : "=a" (dest), "=a" (src) - : "0" (dest), "1" (src) : "memory"); - return xdest; -} - -#define __HAVE_ARCH_STRNCPY -static inline char * strncpy(char *dest, const char *src, size_t n) -{ - char *xdest = dest; - - if (n == 0) - return xdest; - - __asm__ __volatile__ - ("1:\tmoveb %1@+,%0@+\n\t" - "jeq 2f\n\t" - "subql #1,%2\n\t" - "jne 1b\n\t" - "2:" - : "=a" (dest), "=a" (src), "=d" (n) - : "0" (dest), "1" (src), "2" (n) - : "memory"); - return xdest; -} - - -#ifndef CONFIG_COLDFIRE - -#define __HAVE_ARCH_STRCMP -static inline int strcmp(const char * cs,const char * ct) -{ - char __res; - - __asm__ - ("1:\tmoveb %0@+,%2\n\t" /* get *cs */ - "cmpb %1@+,%2\n\t" /* compare a byte */ - "jne 2f\n\t" /* not equal, break out */ - "tstb %2\n\t" /* at end of cs? */ - "jne 1b\n\t" /* no, keep going */ - "jra 3f\n\t" /* strings are equal */ - "2:\tsubb %1@-,%2\n\t" /* *cs - *ct */ - "3:" - : "=a" (cs), "=a" (ct), "=d" (__res) - : "0" (cs), "1" (ct)); - - return __res; -} - -#define __HAVE_ARCH_STRNCMP -static inline int strncmp(const char * cs,const char * ct,size_t count) -{ - char __res; - - if (!count) - return 0; - __asm__ - ("1:\tmovb %0@+,%3\n\t" /* get *cs */ - "cmpb %1@+,%3\n\t" /* compare a byte */ - "jne 3f\n\t" /* not equal, break out */ - "tstb %3\n\t" /* at end of cs? */ - "jeq 4f\n\t" /* yes, all done */ - "subql #1,%2\n\t" /* no, adjust count */ - "jne 1b\n\t" /* more to do, keep going */ - "2:\tmoveq #0,%3\n\t" /* strings are equal */ - "jra 4f\n\t" - "3:\tsubb %1@-,%3\n\t" /* *cs - *ct */ - "4:" - : "=a" (cs), "=a" (ct), "=d" (count), "=d" (__res) - : "0" (cs), "1" (ct), "2" (count)); - return __res; -} - -#endif /* CONFIG_COLDFIRE */ - -#define __HAVE_ARCH_MEMSET -extern void * memset(void * s, int c, size_t count); - -#define __HAVE_ARCH_MEMCPY -extern void * memcpy(void *d, const void *s, size_t count); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ - -#endif /* _M68K_STRING_H_ */ diff --git a/include/asm-m68knommu/system.h b/include/asm-m68knommu/system.h deleted file mode 100644 index 40f49de69821..000000000000 --- a/include/asm-m68knommu/system.h +++ /dev/null @@ -1,324 +0,0 @@ -#ifndef _M68KNOMMU_SYSTEM_H -#define _M68KNOMMU_SYSTEM_H - -#include -#include -#include - -/* - * switch_to(n) should switch tasks to task ptr, first checking that - * ptr isn't the current task, in which case it does nothing. This - * also clears the TS-flag if the task we switched to has used the - * math co-processor latest. - */ -/* - * switch_to() saves the extra registers, that are not saved - * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and - * a0-a1. Some of these are used by schedule() and its predecessors - * and so we might get see unexpected behaviors when a task returns - * with unexpected register values. - * - * syscall stores these registers itself and none of them are used - * by syscall after the function in the syscall has been called. - * - * Beware that resume now expects *next to be in d1 and the offset of - * tss to be in a1. This saves a few instructions as we no longer have - * to push them onto the stack and read them back right after. - * - * 02/17/96 - Jes Sorensen (jds@kom.auc.dk) - * - * Changed 96/09/19 by Andreas Schwab - * pass prev in a0, next in a1, offset of tss in d1, and whether - * the mm structures are shared in d2 (to avoid atc flushing). - */ -asmlinkage void resume(void); -#define switch_to(prev,next,last) \ -{ \ - void *_last; \ - __asm__ __volatile__( \ - "movel %1, %%a0\n\t" \ - "movel %2, %%a1\n\t" \ - "jbsr resume\n\t" \ - "movel %%d1, %0\n\t" \ - : "=d" (_last) \ - : "d" (prev), "d" (next) \ - : "cc", "d0", "d1", "d2", "d3", "d4", "d5", "a0", "a1"); \ - (last) = _last; \ -} - -#ifdef CONFIG_COLDFIRE -#define local_irq_enable() __asm__ __volatile__ ( \ - "move %/sr,%%d0\n\t" \ - "andi.l #0xf8ff,%%d0\n\t" \ - "move %%d0,%/sr\n" \ - : /* no outputs */ \ - : \ - : "cc", "%d0", "memory") -#define local_irq_disable() __asm__ __volatile__ ( \ - "move %/sr,%%d0\n\t" \ - "ori.l #0x0700,%%d0\n\t" \ - "move %%d0,%/sr\n" \ - : /* no outputs */ \ - : \ - : "cc", "%d0", "memory") -/* For spinlocks etc */ -#define local_irq_save(x) __asm__ __volatile__ ( \ - "movew %%sr,%0\n\t" \ - "movew #0x0700,%%d0\n\t" \ - "or.l %0,%%d0\n\t" \ - "movew %%d0,%/sr" \ - : "=d" (x) \ - : \ - : "cc", "%d0", "memory") -#else - -/* portable version */ /* FIXME - see entry.h*/ -#define ALLOWINT 0xf8ff - -#define local_irq_enable() asm volatile ("andiw %0,%%sr": : "i" (ALLOWINT) : "memory") -#define local_irq_disable() asm volatile ("oriw #0x0700,%%sr": : : "memory") -#endif - -#define local_save_flags(x) asm volatile ("movew %%sr,%0":"=d" (x) : : "memory") -#define local_irq_restore(x) asm volatile ("movew %0,%%sr": :"d" (x) : "memory") - -/* For spinlocks etc */ -#ifndef local_irq_save -#define local_irq_save(x) do { local_save_flags(x); local_irq_disable(); } while (0) -#endif - -#define irqs_disabled() \ -({ \ - unsigned long flags; \ - local_save_flags(flags); \ - ((flags & 0x0700) == 0x0700); \ -}) - -#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc") - -/* - * Force strict CPU ordering. - * Not really required on m68k... - */ -#define nop() asm volatile ("nop"::) -#define mb() asm volatile ("" : : :"memory") -#define rmb() asm volatile ("" : : :"memory") -#define wmb() asm volatile ("" : : :"memory") -#define set_mb(var, value) ({ (var) = (value); wmb(); }) - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define read_barrier_depends() ((void)0) - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((volatile struct __xchg_dummy *)(x)) - -#ifndef CONFIG_RMW_INSNS -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - unsigned long tmp, flags; - - local_irq_save(flags); - - switch (size) { - case 1: - __asm__ __volatile__ - ("moveb %2,%0\n\t" - "moveb %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("movew %2,%0\n\t" - "movew %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("movel %2,%0\n\t" - "movel %1,%2" - : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - local_irq_restore(flags); - return tmp; -} -#else -static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size) -{ - switch (size) { - case 1: - __asm__ __volatile__ - ("moveb %2,%0\n\t" - "1:\n\t" - "casb %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 2: - __asm__ __volatile__ - ("movew %2,%0\n\t" - "1:\n\t" - "casw %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - case 4: - __asm__ __volatile__ - ("movel %2,%0\n\t" - "1:\n\t" - "casl %0,%1,%2\n\t" - "jne 1b" - : "=&d" (x) : "d" (x), "m" (*__xg(ptr)) : "memory"); - break; - } - return x; -} -#endif - -#include - -/* - * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make - * them available. - */ -#define cmpxchg_local(ptr, o, n) \ - ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\ - (unsigned long)(n), sizeof(*(ptr)))) -#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n)) - -#ifndef CONFIG_SMP -#include -#endif - -#if defined( CONFIG_M68328 ) || defined( CONFIG_M68EZ328 ) || \ - defined (CONFIG_M68360) || defined( CONFIG_M68VZ328 ) -#define HARD_RESET_NOW() ({ \ - local_irq_disable(); \ - asm(" \ - moveal #0x10c00000, %a0; \ - moveb #0, 0xFFFFF300; \ - moveal 0(%a0), %sp; \ - moveal 4(%a0), %a0; \ - jmp (%a0); \ - "); \ -}) -#endif - -#ifdef CONFIG_COLDFIRE -#if defined(CONFIG_M5272) && defined(CONFIG_NETtel) -/* - * Need to account for broken early mask of 5272 silicon. So don't - * jump through the original start address. Jump strait into the - * known start of the FLASH code. - */ -#define HARD_RESET_NOW() ({ \ - asm(" \ - movew #0x2700, %sr; \ - jmp 0xf0000400; \ - "); \ -}) -#elif defined(CONFIG_NETtel) || defined(CONFIG_eLIA) || \ - defined(CONFIG_SECUREEDGEMP3) || defined(CONFIG_CLEOPATRA) -#define HARD_RESET_NOW() ({ \ - asm(" \ - movew #0x2700, %sr; \ - moveal #0x10000044, %a0; \ - movel #0xffffffff, (%a0); \ - moveal #0x10000001, %a0; \ - moveb #0x00, (%a0); \ - moveal #0xf0000004, %a0; \ - moveal (%a0), %a0; \ - jmp (%a0); \ - "); \ -}) -#elif defined(CONFIG_M5272) -/* - * Retrieve the boot address in flash using CSBR0 and CSOR0 - * find the reset vector at flash_address + 4 (e.g. 0x400) - * remap it in the flash's current location (e.g. 0xf0000400) - * and jump there. - */ -#define HARD_RESET_NOW() ({ \ - asm(" \ - movew #0x2700, %%sr; \ - move.l %0+0x40,%%d0; \ - and.l %0+0x44,%%d0; \ - andi.l #0xfffff000,%%d0; \ - mov.l %%d0,%%a0; \ - or.l 4(%%a0),%%d0; \ - mov.l %%d0,%%a0; \ - jmp (%%a0);" \ - : /* No output */ \ - : "o" (*(char *)MCF_MBAR) ); \ -}) -#elif defined(CONFIG_M528x) -/* - * The MCF528x has a bit (SOFTRST) in memory (Reset Control Register RCR), - * that when set, resets the MCF528x. - */ -#define HARD_RESET_NOW() \ -({ \ - unsigned char volatile *reset; \ - asm("move.w #0x2700, %sr"); \ - reset = ((volatile unsigned char *)(MCF_IPSBAR + 0x110000)); \ - while(1) \ - *reset |= (0x01 << 7);\ -}) -#elif defined(CONFIG_M523x) -#define HARD_RESET_NOW() ({ \ - asm(" \ - movew #0x2700, %sr; \ - movel #0x01000000, %sp; \ - moveal #0x40110000, %a0; \ - moveb #0x80, (%a0); \ - "); \ -}) -#elif defined(CONFIG_M520x) - /* - * The MCF5208 has a bit (SOFTRST) in memory (Reset Control Register - * RCR), that when set, resets the MCF5208. - */ -#define HARD_RESET_NOW() \ -({ \ - unsigned char volatile *reset; \ - asm("move.w #0x2700, %sr"); \ - reset = ((volatile unsigned char *)(MCF_IPSBAR + 0xA0000)); \ - while(1) \ - *reset |= 0x80; \ -}) -#else -#define HARD_RESET_NOW() ({ \ - asm(" \ - movew #0x2700, %sr; \ - moveal #0x4, %a0; \ - moveal (%a0), %a0; \ - jmp (%a0); \ - "); \ -}) -#endif -#endif -#define arch_align_stack(x) (x) - - -static inline int irqs_disabled_flags(unsigned long flags) -{ - if (flags & 0x0700) - return 0; - else - return 1; -} - -#endif /* _M68KNOMMU_SYSTEM_H */ diff --git a/include/asm-m68knommu/termbits.h b/include/asm-m68knommu/termbits.h deleted file mode 100644 index 05dd6bc27285..000000000000 --- a/include/asm-m68knommu/termbits.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/termios.h b/include/asm-m68knommu/termios.h deleted file mode 100644 index e7337881a985..000000000000 --- a/include/asm-m68knommu/termios.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/thread_info.h b/include/asm-m68knommu/thread_info.h deleted file mode 100644 index 0c9bc095f3f0..000000000000 --- a/include/asm-m68knommu/thread_info.h +++ /dev/null @@ -1,98 +0,0 @@ -/* thread_info.h: m68knommu low-level thread information - * adapted from the i386 and PPC versions by Greg Ungerer (gerg@snapgear.com) - * - * Copyright (C) 2002 David Howells (dhowells@redhat.com) - * - Incorporating suggestions made by Linus Torvalds and Dave Miller - */ - -#ifndef _ASM_THREAD_INFO_H -#define _ASM_THREAD_INFO_H - -#include - -#ifdef __KERNEL__ - -#ifndef __ASSEMBLY__ - -/* - * Size of kernel stack for each process. This must be a power of 2... - */ -#ifdef CONFIG_4KSTACKS -#define THREAD_SIZE_ORDER (0) -#else -#define THREAD_SIZE_ORDER (1) -#endif - -/* - * for asm files, THREAD_SIZE is now generated by asm-offsets.c - */ -#define THREAD_SIZE (PAGE_SIZE< preemptable, <0 => BUG */ - struct restart_block restart_block; -}; - -/* - * macros/functions for gaining access to the thread information structure - */ -#define INIT_THREAD_INFO(tsk) \ -{ \ - .task = &tsk, \ - .exec_domain = &default_exec_domain, \ - .flags = 0, \ - .cpu = 0, \ - .restart_block = { \ - .fn = do_no_restart_syscall, \ - }, \ -} - -#define init_thread_info (init_thread_union.thread_info) -#define init_stack (init_thread_union.stack) - - -/* how to get the thread information struct from C */ -static inline struct thread_info *current_thread_info(void) -{ - struct thread_info *ti; - __asm__( - "move.l %%sp, %0 \n\t" - "and.l %1, %0" - : "=&d"(ti) - : "di" (~(THREAD_SIZE-1)) - ); - return ti; -} - -#endif /* __ASSEMBLY__ */ - -#define PREEMPT_ACTIVE 0x4000000 - -/* - * thread information flag bit numbers - */ -#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_POLLING_NRFLAG 3 /* true if poll_idle() is polling - TIF_NEED_RESCHED */ -#define TIF_MEMDIE 4 - -/* as above, but as bit values */ -#define _TIF_SYSCALL_TRACE (1< -#define CLOCK_TICK_RATE MCF_CLK -#else -#define CLOCK_TICK_RATE 1193180 /* Underlying HZ */ -#endif - -typedef unsigned long cycles_t; - -static inline cycles_t get_cycles(void) -{ - return 0; -} - -#endif diff --git a/include/asm-m68knommu/tlb.h b/include/asm-m68knommu/tlb.h deleted file mode 100644 index 77a7c51ca299..000000000000 --- a/include/asm-m68knommu/tlb.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/tlbflush.h b/include/asm-m68knommu/tlbflush.h deleted file mode 100644 index a470cfb803eb..000000000000 --- a/include/asm-m68knommu/tlbflush.h +++ /dev/null @@ -1,55 +0,0 @@ -#ifndef _M68KNOMMU_TLBFLUSH_H -#define _M68KNOMMU_TLBFLUSH_H - -/* - * Copyright (C) 2000 Lineo, David McCullough - * Copyright (C) 2000-2002, Greg Ungerer - */ - -#include - -/* - * flush all user-space atc entries. - */ -static inline void __flush_tlb(void) -{ - BUG(); -} - -static inline void __flush_tlb_one(unsigned long addr) -{ - BUG(); -} - -#define flush_tlb() __flush_tlb() - -/* - * flush all atc entries (both kernel and user-space entries). - */ -static inline void flush_tlb_all(void) -{ - BUG(); -} - -static inline void flush_tlb_mm(struct mm_struct *mm) -{ - BUG(); -} - -static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) -{ - BUG(); -} - -static inline void flush_tlb_range(struct mm_struct *mm, - unsigned long start, unsigned long end) -{ - BUG(); -} - -static inline void flush_tlb_kernel_page(unsigned long addr) -{ - BUG(); -} - -#endif /* _M68KNOMMU_TLBFLUSH_H */ diff --git a/include/asm-m68knommu/topology.h b/include/asm-m68knommu/topology.h deleted file mode 100644 index ca173e9f26ff..000000000000 --- a/include/asm-m68knommu/topology.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _ASM_M68K_TOPOLOGY_H -#define _ASM_M68K_TOPOLOGY_H - -#include - -#endif /* _ASM_M68K_TOPOLOGY_H */ diff --git a/include/asm-m68knommu/traps.h b/include/asm-m68knommu/traps.h deleted file mode 100644 index d0671e5f8e29..000000000000 --- a/include/asm-m68knommu/traps.h +++ /dev/null @@ -1,154 +0,0 @@ -/* - * linux/include/asm/traps.h - * - * Copyright (C) 1993 Hamish Macdonald - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#ifndef _M68KNOMMU_TRAPS_H -#define _M68KNOMMU_TRAPS_H - -#ifndef __ASSEMBLY__ - -typedef void (*e_vector)(void); - -extern e_vector vectors[]; -extern void init_vectors(void); -extern void enable_vector(unsigned int irq); -extern void disable_vector(unsigned int irq); -extern void ack_vector(unsigned int irq); - -#endif - -#define VEC_BUSERR (2) -#define VEC_ADDRERR (3) -#define VEC_ILLEGAL (4) -#define VEC_ZERODIV (5) -#define VEC_CHK (6) -#define VEC_TRAP (7) -#define VEC_PRIV (8) -#define VEC_TRACE (9) -#define VEC_LINE10 (10) -#define VEC_LINE11 (11) -#define VEC_RESV1 (12) -#define VEC_COPROC (13) -#define VEC_FORMAT (14) -#define VEC_UNINT (15) -#define VEC_SPUR (24) -#define VEC_INT1 (25) -#define VEC_INT2 (26) -#define VEC_INT3 (27) -#define VEC_INT4 (28) -#define VEC_INT5 (29) -#define VEC_INT6 (30) -#define VEC_INT7 (31) -#define VEC_SYS (32) -#define VEC_TRAP1 (33) -#define VEC_TRAP2 (34) -#define VEC_TRAP3 (35) -#define VEC_TRAP4 (36) -#define VEC_TRAP5 (37) -#define VEC_TRAP6 (38) -#define VEC_TRAP7 (39) -#define VEC_TRAP8 (40) -#define VEC_TRAP9 (41) -#define VEC_TRAP10 (42) -#define VEC_TRAP11 (43) -#define VEC_TRAP12 (44) -#define VEC_TRAP13 (45) -#define VEC_TRAP14 (46) -#define VEC_TRAP15 (47) -#define VEC_FPBRUC (48) -#define VEC_FPIR (49) -#define VEC_FPDIVZ (50) -#define VEC_FPUNDER (51) -#define VEC_FPOE (52) -#define VEC_FPOVER (53) -#define VEC_FPNAN (54) -#define VEC_FPUNSUP (55) -#define VEC_UNIMPEA (60) -#define VEC_UNIMPII (61) -#define VEC_USER (64) - -#define VECOFF(vec) ((vec)<<2) - -#ifndef __ASSEMBLY__ - -/* Status register bits */ -#define PS_T (0x8000) -#define PS_S (0x2000) -#define PS_M (0x1000) -#define PS_C (0x0001) - -/* structure for stack frames */ - -struct frame { - struct pt_regs ptregs; - union { - struct { - unsigned long iaddr; /* instruction address */ - } fmt2; - struct { - unsigned long effaddr; /* effective address */ - } fmt3; - struct { - unsigned long effaddr; /* effective address */ - unsigned long pc; /* pc of faulted instr */ - } fmt4; - struct { - unsigned long effaddr; /* effective address */ - unsigned short ssw; /* special status word */ - unsigned short wb3s; /* write back 3 status */ - unsigned short wb2s; /* write back 2 status */ - unsigned short wb1s; /* write back 1 status */ - unsigned long faddr; /* fault address */ - unsigned long wb3a; /* write back 3 address */ - unsigned long wb3d; /* write back 3 data */ - unsigned long wb2a; /* write back 2 address */ - unsigned long wb2d; /* write back 2 data */ - unsigned long wb1a; /* write back 1 address */ - unsigned long wb1dpd0; /* write back 1 data/push data 0*/ - unsigned long pd1; /* push data 1*/ - unsigned long pd2; /* push data 2*/ - unsigned long pd3; /* push data 3*/ - } fmt7; - struct { - unsigned long iaddr; /* instruction address */ - unsigned short int1[4]; /* internal registers */ - } fmt9; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[2]; - } fmta; - struct { - unsigned short int1; - unsigned short ssw; /* special status word */ - unsigned short isc; /* instruction stage c */ - unsigned short isb; /* instruction stage b */ - unsigned long daddr; /* data cycle fault address */ - unsigned short int2[2]; - unsigned long dobuf; /* data cycle output buffer */ - unsigned short int3[4]; - unsigned long baddr; /* stage B address */ - unsigned short int4[2]; - unsigned long dibuf; /* data cycle input buffer */ - unsigned short int5[3]; - unsigned ver : 4; /* stack frame version # */ - unsigned int6:12; - unsigned short int7[18]; - } fmtb; - } un; -}; - -#endif /* __ASSEMBLY__ */ - -#endif /* _M68KNOMMU_TRAPS_H */ diff --git a/include/asm-m68knommu/types.h b/include/asm-m68knommu/types.h deleted file mode 100644 index 031238c2d180..000000000000 --- a/include/asm-m68knommu/types.h +++ /dev/null @@ -1 +0,0 @@ -#include diff --git a/include/asm-m68knommu/uaccess.h b/include/asm-m68knommu/uaccess.h deleted file mode 100644 index 68bbe9b312f1..000000000000 --- a/include/asm-m68knommu/uaccess.h +++ /dev/null @@ -1,181 +0,0 @@ -#ifndef __M68KNOMMU_UACCESS_H -#define __M68KNOMMU_UACCESS_H - -/* - * User space memory access functions - */ -#include -#include -#include - -#include - -#define VERIFY_READ 0 -#define VERIFY_WRITE 1 - -#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size)) - -/* - * It is not enough to just have access_ok check for a real RAM address. - * This would disallow the case of code/ro-data running XIP in flash/rom. - * Ideally we would check the possible flash ranges too, but that is - * currently not so easy. - */ -static inline int _access_ok(unsigned long addr, unsigned long size) -{ - return 1; -} - -/* - * The exception table consists of pairs of addresses: the first is the - * address of an instruction that is allowed to fault, and the second is - * the address at which the program should continue. No registers are - * modified, so it is entirely up to the continuation code to figure out - * what to do. - * - * All the routines below use bits of fixup code that are out of line - * with the main instruction path. This means when everything is well, - * we don't even have to jump over them. Further, they do not intrude - * on our cache or tlb entries. - */ - -struct exception_table_entry -{ - unsigned long insn, fixup; -}; - -/* Returns 0 if exception not found and fixup otherwise. */ -extern unsigned long search_exception_table(unsigned long); - - -/* - * These are the main single-value transfer routines. They automatically - * use the right size if we just have the right pointer type. - */ - -#define put_user(x, ptr) \ -({ \ - int __pu_err = 0; \ - typeof(*(ptr)) __pu_val = (x); \ - switch (sizeof (*(ptr))) { \ - case 1: \ - __put_user_asm(__pu_err, __pu_val, ptr, b); \ - break; \ - case 2: \ - __put_user_asm(__pu_err, __pu_val, ptr, w); \ - break; \ - case 4: \ - __put_user_asm(__pu_err, __pu_val, ptr, l); \ - break; \ - case 8: \ - memcpy(ptr, &__pu_val, sizeof (*(ptr))); \ - break; \ - default: \ - __pu_err = __put_user_bad(); \ - break; \ - } \ - __pu_err; \ -}) -#define __put_user(x, ptr) put_user(x, ptr) - -extern int __put_user_bad(void); - -/* - * Tell gcc we read from memory instead of writing: this is because - * we do not write to any memory gcc knows about, so there are no - * aliasing issues. - */ - -#define __ptr(x) ((unsigned long *)(x)) - -#define __put_user_asm(err,x,ptr,bwl) \ - __asm__ ("move" #bwl " %0,%1" \ - : /* no outputs */ \ - :"d" (x),"m" (*__ptr(ptr)) : "memory") - -#define get_user(x, ptr) \ -({ \ - int __gu_err = 0; \ - typeof(x) __gu_val = 0; \ - switch (sizeof(*(ptr))) { \ - case 1: \ - __get_user_asm(__gu_err, __gu_val, ptr, b, "=d"); \ - break; \ - case 2: \ - __get_user_asm(__gu_err, __gu_val, ptr, w, "=r"); \ - break; \ - case 4: \ - __get_user_asm(__gu_err, __gu_val, ptr, l, "=r"); \ - break; \ - case 8: \ - memcpy((void *) &__gu_val, ptr, sizeof (*(ptr))); \ - break; \ - default: \ - __gu_val = 0; \ - __gu_err = __get_user_bad(); \ - break; \ - } \ - (x) = (typeof(*(ptr))) __gu_val; \ - __gu_err; \ -}) -#define __get_user(x, ptr) get_user(x, ptr) - -extern int __get_user_bad(void); - -#define __get_user_asm(err,x,ptr,bwl,reg) \ - __asm__ ("move" #bwl " %1,%0" \ - : "=d" (x) \ - : "m" (*__ptr(ptr))) - -#define copy_from_user(to, from, n) (memcpy(to, from, n), 0) -#define copy_to_user(to, from, n) (memcpy(to, from, n), 0) - -#define __copy_from_user(to, from, n) copy_from_user(to, from, n) -#define __copy_to_user(to, from, n) copy_to_user(to, from, n) -#define __copy_to_user_inatomic __copy_to_user -#define __copy_from_user_inatomic __copy_from_user - -#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; }) - -#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; }) - -/* - * Copy a null terminated string from userspace. - */ - -static inline long -strncpy_from_user(char *dst, const char *src, long count) -{ - char *tmp; - strncpy(dst, src, count); - for (tmp = dst; *tmp && count > 0; tmp++, count--) - ; - return(tmp - dst); /* DAVIDM should we count a NUL ? check getname */ -} - -/* - * Return the size of a string (including the ending 0) - * - * Return 0 on exception, a value greater than N if too long - */ -static inline long strnlen_user(const char *src, long n) -{ - return(strlen(src) + 1); /* DAVIDM make safer */ -} - -#define strlen_user(str) strnlen_user(str, 32767) - -/* - * Zero Userspace - */ - -static inline unsigned long -__clear_user(void *to, unsigned long n) -{ - memset(to, 0, n); - return 0; -} - -#define clear_user(to,n) __clear_user(to,n) - -#endif /* _M68KNOMMU_UACCESS_H */ diff --git a/include/asm-m68knommu/ucontext.h b/include/asm-m68knommu/ucontext.h deleted file mode 100644 index 713a27f901cd..000000000000 --- a/include/asm-m68knommu/ucontext.h +++ /dev/null @@ -1,32 +0,0 @@ -#ifndef _M68KNOMMU_UCONTEXT_H -#define _M68KNOMMU_UCONTEXT_H - -typedef int greg_t; -#define NGREG 18 -typedef greg_t gregset_t[NGREG]; - -typedef struct fpregset { - int f_pcr; - int f_psr; - int f_fpiaddr; - int f_fpregs[8][3]; -} fpregset_t; - -struct mcontext { - int version; - gregset_t gregs; - fpregset_t fpregs; -}; - -#define MCONTEXT_VERSION 2 - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct mcontext uc_mcontext; - unsigned long uc_filler[80]; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif diff --git a/include/asm-m68knommu/unaligned.h b/include/asm-m68knommu/unaligned.h deleted file mode 100644 index eb1ea4cb9a59..000000000000 --- a/include/asm-m68knommu/unaligned.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASM_M68KNOMMU_UNALIGNED_H -#define _ASM_M68KNOMMU_UNALIGNED_H - - -#ifdef CONFIG_COLDFIRE -#include -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#else -/* - * The m68k can do unaligned accesses itself. - */ -#include -#include - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif - -#endif /* _ASM_M68KNOMMU_UNALIGNED_H */ diff --git a/include/asm-m68knommu/unistd.h b/include/asm-m68knommu/unistd.h deleted file mode 100644 index 4ba98b9c5d79..000000000000 --- a/include/asm-m68knommu/unistd.h +++ /dev/null @@ -1,366 +0,0 @@ -#ifndef _ASM_M68K_UNISTD_H_ -#define _ASM_M68K_UNISTD_H_ - -/* - * This file contains the system call numbers. - */ - -#define __NR_restart_syscall 0 -#define __NR_exit 1 -#define __NR_fork 2 -#define __NR_read 3 -#define __NR_write 4 -#define __NR_open 5 -#define __NR_close 6 -#define __NR_waitpid 7 -#define __NR_creat 8 -#define __NR_link 9 -#define __NR_unlink 10 -#define __NR_execve 11 -#define __NR_chdir 12 -#define __NR_time 13 -#define __NR_mknod 14 -#define __NR_chmod 15 -#define __NR_chown 16 -#define __NR_break 17 -#define __NR_oldstat 18 -#define __NR_lseek 19 -#define __NR_getpid 20 -#define __NR_mount 21 -#define __NR_umount 22 -#define __NR_setuid 23 -#define __NR_getuid 24 -#define __NR_stime 25 -#define __NR_ptrace 26 -#define __NR_alarm 27 -#define __NR_oldfstat 28 -#define __NR_pause 29 -#define __NR_utime 30 -#define __NR_stty 31 -#define __NR_gtty 32 -#define __NR_access 33 -#define __NR_nice 34 -#define __NR_ftime 35 -#define __NR_sync 36 -#define __NR_kill 37 -#define __NR_rename 38 -#define __NR_mkdir 39 -#define __NR_rmdir 40 -#define __NR_dup 41 -#define __NR_pipe 42 -#define __NR_times 43 -#define __NR_prof 44 -#define __NR_brk 45 -#define __NR_setgid 46 -#define __NR_getgid 47 -#define __NR_signal 48 -#define __NR_geteuid 49 -#define __NR_getegid 50 -#define __NR_acct 51 -#define __NR_umount2 52 -#define __NR_lock 53 -#define __NR_ioctl 54 -#define __NR_fcntl 55 -#define __NR_mpx 56 -#define __NR_setpgid 57 -#define __NR_ulimit 58 -#define __NR_oldolduname 59 -#define __NR_umask 60 -#define __NR_chroot 61 -#define __NR_ustat 62 -#define __NR_dup2 63 -#define __NR_getppid 64 -#define __NR_getpgrp 65 -#define __NR_setsid 66 -#define __NR_sigaction 67 -#define __NR_sgetmask 68 -#define __NR_ssetmask 69 -#define __NR_setreuid 70 -#define __NR_setregid 71 -#define __NR_sigsuspend 72 -#define __NR_sigpending 73 -#define __NR_sethostname 74 -#define __NR_setrlimit 75 -#define __NR_getrlimit 76 -#define __NR_getrusage 77 -#define __NR_gettimeofday 78 -#define __NR_settimeofday 79 -#define __NR_getgroups 80 -#define __NR_setgroups 81 -#define __NR_select 82 -#define __NR_symlink 83 -#define __NR_oldlstat 84 -#define __NR_readlink 85 -#define __NR_uselib 86 -#define __NR_swapon 87 -#define __NR_reboot 88 -#define __NR_readdir 89 -#define __NR_mmap 90 -#define __NR_munmap 91 -#define __NR_truncate 92 -#define __NR_ftruncate 93 -#define __NR_fchmod 94 -#define __NR_fchown 95 -#define __NR_getpriority 96 -#define __NR_setpriority 97 -#define __NR_profil 98 -#define __NR_statfs 99 -#define __NR_fstatfs 100 -#define __NR_ioperm 101 -#define __NR_socketcall 102 -#define __NR_syslog 103 -#define __NR_setitimer 104 -#define __NR_getitimer 105 -#define __NR_stat 106 -#define __NR_lstat 107 -#define __NR_fstat 108 -#define __NR_olduname 109 -#define __NR_iopl /* 110 */ not supported -#define __NR_vhangup 111 -#define __NR_idle /* 112 */ Obsolete -#define __NR_vm86 /* 113 */ not supported -#define __NR_wait4 114 -#define __NR_swapoff 115 -#define __NR_sysinfo 116 -#define __NR_ipc 117 -#define __NR_fsync 118 -#define __NR_sigreturn 119 -#define __NR_clone 120 -#define __NR_setdomainname 121 -#define __NR_uname 122 -#define __NR_cacheflush 123 -#define __NR_adjtimex 124 -#define __NR_mprotect 125 -#define __NR_sigprocmask 126 -#define __NR_create_module 127 -#define __NR_init_module 128 -#define __NR_delete_module 129 -#define __NR_get_kernel_syms 130 -#define __NR_quotactl 131 -#define __NR_getpgid 132 -#define __NR_fchdir 133 -#define __NR_bdflush 134 -#define __NR_sysfs 135 -#define __NR_personality 136 -#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ -#define __NR_setfsuid 138 -#define __NR_setfsgid 139 -#define __NR__llseek 140 -#define __NR_getdents 141 -#define __NR__newselect 142 -#define __NR_flock 143 -#define __NR_msync 144 -#define __NR_readv 145 -#define __NR_writev 146 -#define __NR_getsid 147 -#define __NR_fdatasync 148 -#define __NR__sysctl 149 -#define __NR_mlock 150 -#define __NR_munlock 151 -#define __NR_mlockall 152 -#define __NR_munlockall 153 -#define __NR_sched_setparam 154 -#define __NR_sched_getparam 155 -#define __NR_sched_setscheduler 156 -#define __NR_sched_getscheduler 157 -#define __NR_sched_yield 158 -#define __NR_sched_get_priority_max 159 -#define __NR_sched_get_priority_min 160 -#define __NR_sched_rr_get_interval 161 -#define __NR_nanosleep 162 -#define __NR_mremap 163 -#define __NR_setresuid 164 -#define __NR_getresuid 165 -#define __NR_getpagesize 166 -#define __NR_query_module 167 -#define __NR_poll 168 -#define __NR_nfsservctl 169 -#define __NR_setresgid 170 -#define __NR_getresgid 171 -#define __NR_prctl 172 -#define __NR_rt_sigreturn 173 -#define __NR_rt_sigaction 174 -#define __NR_rt_sigprocmask 175 -#define __NR_rt_sigpending 176 -#define __NR_rt_sigtimedwait 177 -#define __NR_rt_sigqueueinfo 178 -#define __NR_rt_sigsuspend 179 -#define __NR_pread64 180 -#define __NR_pwrite64 181 -#define __NR_lchown 182 -#define __NR_getcwd 183 -#define __NR_capget 184 -#define __NR_capset 185 -#define __NR_sigaltstack 186 -#define __NR_sendfile 187 -#define __NR_getpmsg 188 /* some people actually want streams */ -#define __NR_putpmsg 189 /* some people actually want streams */ -#define __NR_vfork 190 -#define __NR_ugetrlimit 191 -#define __NR_mmap2 192 -#define __NR_truncate64 193 -#define __NR_ftruncate64 194 -#define __NR_stat64 195 -#define __NR_lstat64 196 -#define __NR_fstat64 197 -#define __NR_chown32 198 -#define __NR_getuid32 199 -#define __NR_getgid32 200 -#define __NR_geteuid32 201 -#define __NR_getegid32 202 -#define __NR_setreuid32 203 -#define __NR_setregid32 204 -#define __NR_getgroups32 205 -#define __NR_setgroups32 206 -#define __NR_fchown32 207 -#define __NR_setresuid32 208 -#define __NR_getresuid32 209 -#define __NR_setresgid32 210 -#define __NR_getresgid32 211 -#define __NR_lchown32 212 -#define __NR_setuid32 213 -#define __NR_setgid32 214 -#define __NR_setfsuid32 215 -#define __NR_setfsgid32 216 -#define __NR_pivot_root 217 -#define __NR_getdents64 220 -#define __NR_gettid 221 -#define __NR_tkill 222 -#define __NR_setxattr 223 -#define __NR_lsetxattr 224 -#define __NR_fsetxattr 225 -#define __NR_getxattr 226 -#define __NR_lgetxattr 227 -#define __NR_fgetxattr 228 -#define __NR_listxattr 229 -#define __NR_llistxattr 230 -#define __NR_flistxattr 231 -#define __NR_removexattr 232 -#define __NR_lremovexattr 233 -#define __NR_fremovexattr 234 -#define __NR_futex 235 -#define __NR_sendfile64 236 -#define __NR_mincore 237 -#define __NR_madvise 238 -#define __NR_fcntl64 239 -#define __NR_readahead 240 -#define __NR_io_setup 241 -#define __NR_io_destroy 242 -#define __NR_io_getevents 243 -#define __NR_io_submit 244 -#define __NR_io_cancel 245 -#define __NR_fadvise64 246 -#define __NR_exit_group 247 -#define __NR_lookup_dcookie 248 -#define __NR_epoll_create 249 -#define __NR_epoll_ctl 250 -#define __NR_epoll_wait 251 -#define __NR_remap_file_pages 252 -#define __NR_set_tid_address 253 -#define __NR_timer_create 254 -#define __NR_timer_settime 255 -#define __NR_timer_gettime 256 -#define __NR_timer_getoverrun 257 -#define __NR_timer_delete 258 -#define __NR_clock_settime 259 -#define __NR_clock_gettime 260 -#define __NR_clock_getres 261 -#define __NR_clock_nanosleep 262 -#define __NR_statfs64 263 -#define __NR_fstatfs64 264 -#define __NR_tgkill 265 -#define __NR_utimes 266 -#define __NR_fadvise64_64 267 -#define __NR_mbind 268 -#define __NR_get_mempolicy 269 -#define __NR_set_mempolicy 270 -#define __NR_mq_open 271 -#define __NR_mq_unlink 272 -#define __NR_mq_timedsend 273 -#define __NR_mq_timedreceive 274 -#define __NR_mq_notify 275 -#define __NR_mq_getsetattr 276 -#define __NR_waitid 277 -#define __NR_vserver 278 -#define __NR_add_key 279 -#define __NR_request_key 280 -#define __NR_keyctl 281 -#define __NR_ioprio_set 282 -#define __NR_ioprio_get 283 -#define __NR_inotify_init 284 -#define __NR_inotify_add_watch 285 -#define __NR_inotify_rm_watch 286 -#define __NR_migrate_pages 287 -#define __NR_openat 288 -#define __NR_mkdirat 289 -#define __NR_mknodat 290 -#define __NR_fchownat 291 -#define __NR_futimesat 292 -#define __NR_fstatat64 293 -#define __NR_unlinkat 294 -#define __NR_renameat 295 -#define __NR_linkat 296 -#define __NR_symlinkat 297 -#define __NR_readlinkat 298 -#define __NR_fchmodat 299 -#define __NR_faccessat 300 -#define __NR_pselect6 301 -#define __NR_ppoll 302 -#define __NR_unshare 303 -#define __NR_set_robust_list 304 -#define __NR_get_robust_list 305 -#define __NR_splice 306 -#define __NR_sync_file_range 307 -#define __NR_tee 308 -#define __NR_vmsplice 309 -#define __NR_move_pages 310 -#define __NR_sched_setaffinity 311 -#define __NR_sched_getaffinity 312 -#define __NR_kexec_load 313 -#define __NR_getcpu 314 -#define __NR_epoll_pwait 315 -#define __NR_utimensat 316 -#define __NR_signalfd 317 -#define __NR_timerfd_create 318 -#define __NR_eventfd 319 -#define __NR_fallocate 320 -#define __NR_timerfd_settime 321 -#define __NR_timerfd_gettime 322 - -#ifdef __KERNEL__ - -#define NR_syscalls 323 - -#define __ARCH_WANT_IPC_PARSE_VERSION -#define __ARCH_WANT_OLD_READDIR -#define __ARCH_WANT_OLD_STAT -#define __ARCH_WANT_STAT64 -#define __ARCH_WANT_SYS_ALARM -#define __ARCH_WANT_SYS_GETHOSTNAME -#define __ARCH_WANT_SYS_PAUSE -#define __ARCH_WANT_SYS_SGETMASK -#define __ARCH_WANT_SYS_SIGNAL -#define __ARCH_WANT_SYS_TIME -#define __ARCH_WANT_SYS_UTIME -#define __ARCH_WANT_SYS_WAITPID -#define __ARCH_WANT_SYS_SOCKETCALL -#define __ARCH_WANT_SYS_FADVISE64 -#define __ARCH_WANT_SYS_GETPGRP -#define __ARCH_WANT_SYS_LLSEEK -#define __ARCH_WANT_SYS_NICE -#define __ARCH_WANT_SYS_OLD_GETRLIMIT -#define __ARCH_WANT_SYS_OLDUMOUNT -#define __ARCH_WANT_SYS_SIGPENDING -#define __ARCH_WANT_SYS_SIGPROCMASK -#define __ARCH_WANT_SYS_RT_SIGACTION - -/* - * "Conditional" syscalls - * - * What we want is __attribute__((weak,alias("sys_ni_syscall"))), - * but it doesn't work on all toolchains, so we just do it by hand - */ -#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") - -#endif /* __KERNEL__ */ -#endif /* _ASM_M68K_UNISTD_H_ */ diff --git a/include/asm-m68knommu/user.h b/include/asm-m68knommu/user.h deleted file mode 100644 index a5a555b761c4..000000000000 --- a/include/asm-m68knommu/user.h +++ /dev/null @@ -1 +0,0 @@ -#include -- cgit v1.2.3 From 6e0d733d921526e628107fb8b1aff5f7de870d6f Mon Sep 17 00:00:00 2001 From: Alex Naslednikov Date: Thu, 7 Aug 2008 14:06:50 -0700 Subject: IB/mlx4: Allow 4K messages for UD QPs Current code limits the max message size to 2K for UD QPs, while MTU might be as big as 4K. This patch sets the maximum message size to 4K, which is needed for UD to work correctly on fabrics with a 4K MTU. Signed-off-by: Alex Naslednikov Signed-off-by: Eli Cohen Signed-off-by: Roland Dreier --- drivers/infiniband/hw/mlx4/qp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/hw/mlx4/qp.c b/drivers/infiniband/hw/mlx4/qp.c index f7bc7dd8578a..f29dbb767e87 100644 --- a/drivers/infiniband/hw/mlx4/qp.c +++ b/drivers/infiniband/hw/mlx4/qp.c @@ -902,7 +902,7 @@ static int __mlx4_ib_modify_qp(struct ib_qp *ibqp, context->mtu_msgmax = (IB_MTU_4096 << 5) | ilog2(dev->dev->caps.max_gso_sz); else - context->mtu_msgmax = (IB_MTU_4096 << 5) | 11; + context->mtu_msgmax = (IB_MTU_4096 << 5) | 12; } else if (attr_mask & IB_QP_PATH_MTU) { if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { printk(KERN_ERR "path MTU (%u) is invalid\n", -- cgit v1.2.3 From cd55ef5a10d1a2ea09853bc5fa40aadaf9f80614 Mon Sep 17 00:00:00 2001 From: Julien Brunel Date: Thu, 7 Aug 2008 14:11:56 -0700 Subject: IB/mad: Test ib_create_send_mad() return with IS_ERR(), not == NULL In case of error, the function ib_create_send_mad() returns an ERR pointer, but never returns a NULL pointer. So testing the return value for error should be done with IS_ERR, not by comparing with NULL. A simplified version of the semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // @correct_null_test@ expression x,E; statement S1, S2; @@ x = ib_create_send_mad(...) <... when != x = E if ( ( - x@p2 != NULL + ! IS_ERR ( x ) | - x@p2 == NULL + IS_ERR( x ) ) ) S1 else S2 ...> ? x = E; // Signed-off-by: Julien Brunel Signed-off-by: Julia Lawall Signed-off-by: Roland Dreier --- drivers/infiniband/core/mad_rmpp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/infiniband/core/mad_rmpp.c b/drivers/infiniband/core/mad_rmpp.c index d0ef7d61c037..3af2b84cd838 100644 --- a/drivers/infiniband/core/mad_rmpp.c +++ b/drivers/infiniband/core/mad_rmpp.c @@ -133,7 +133,7 @@ static void ack_recv(struct mad_rmpp_recv *rmpp_recv, msg = ib_create_send_mad(&rmpp_recv->agent->agent, recv_wc->wc->src_qp, recv_wc->wc->pkey_index, 1, hdr_len, 0, GFP_KERNEL); - if (!msg) + if (IS_ERR(msg)) return; format_ack(msg, (struct ib_rmpp_mad *) recv_wc->recv_buf.mad, rmpp_recv); -- cgit v1.2.3 From 5861bbfcc10fc0358abf52c7d22850c8d180f0b0 Mon Sep 17 00:00:00 2001 From: Roland McGrath Date: Thu, 7 Aug 2008 16:55:03 -0700 Subject: tracehook: fix CLONE_PTRACE In the change in commit 09a05394fe2448a4139b014936330af23fa7ec83, I overlooked two nits in the logic and this broke using CLONE_PTRACE when PTRACE_O_TRACE* are not being used. A parent that is itself traced at all but not using PTRACE_O_TRACE*, using CLONE_PTRACE would have its new child fail to be traced. A parent that is not itself traced at all that uses CLONE_PTRACE (which should be a no-op in this case) would confuse the bookkeeping and lead to a crash at exit time. This restores the missing checks and fixes both failure modes. Reported-by: Eduardo Habkost Signed-off-by: Roland McGrath --- include/linux/ptrace.h | 2 +- include/linux/tracehook.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h index fd31756e1a00..ea7416c901d1 100644 --- a/include/linux/ptrace.h +++ b/include/linux/ptrace.h @@ -172,7 +172,7 @@ static inline void ptrace_init_task(struct task_struct *child, bool ptrace) child->ptrace = 0; if (unlikely(ptrace)) { child->ptrace = current->ptrace; - __ptrace_link(child, current->parent); + ptrace_link(child, current->parent); } } diff --git a/include/linux/tracehook.h b/include/linux/tracehook.h index ab3ef7aefa95..b48d81969574 100644 --- a/include/linux/tracehook.h +++ b/include/linux/tracehook.h @@ -280,7 +280,7 @@ static inline void tracehook_report_clone(int trace, struct pt_regs *regs, unsigned long clone_flags, pid_t pid, struct task_struct *child) { - if (unlikely(trace)) { + if (unlikely(trace) || unlikely(clone_flags & CLONE_PTRACE)) { /* * The child starts up with an immediate SIGSTOP. */ -- cgit v1.2.3 From 4c514a5ad1314b872e3185dabaf105c81d39d7e8 Mon Sep 17 00:00:00 2001 From: Stephen Rothwell Date: Thu, 7 Aug 2008 14:08:27 +1000 Subject: powerpc/iseries: remove the old viocons driver This driver was declared obsolete over 2 years ago, the alternative console driver for legacy iSeries (hvc_iseries) was made the default over 1 year ago and this driver has been build broken for over 3 months, so remove it. Signed-off-by: Stephen Rothwell Signed-off-by: Linus Torvalds --- arch/powerpc/platforms/iseries/Kconfig | 11 +- drivers/char/Kconfig | 2 +- drivers/char/Makefile | 1 - drivers/char/viocons.c | 1167 -------------------------------- 4 files changed, 2 insertions(+), 1179 deletions(-) delete mode 100644 drivers/char/viocons.c diff --git a/arch/powerpc/platforms/iseries/Kconfig b/arch/powerpc/platforms/iseries/Kconfig index ea3e541ac74f..45ffd8e542f4 100644 --- a/arch/powerpc/platforms/iseries/Kconfig +++ b/arch/powerpc/platforms/iseries/Kconfig @@ -7,15 +7,6 @@ config PPC_ISERIES menu "iSeries device drivers" depends on PPC_ISERIES -config VIOCONS - bool "iSeries Virtual Console Support (Obsolete)" - depends on !HVC_ISERIES - default n - help - This is the old virtual console driver for legacy iSeries. - You should use the iSeries Hypervisor Virtual Console - support instead. - config VIODASD tristate "iSeries Virtual I/O disk support" help @@ -38,5 +29,5 @@ endmenu config VIOPATH bool - depends on VIOCONS || VIODASD || VIOCD || VIOTAPE || ISERIES_VETH + depends on VIODASD || VIOCD || VIOTAPE || ISERIES_VETH default y diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig index d0ac944e1696..caff85149b9d 100644 --- a/drivers/char/Kconfig +++ b/drivers/char/Kconfig @@ -8,7 +8,7 @@ config VT bool "Virtual terminal" if EMBEDDED depends on !S390 select INPUT - default y if !VIOCONS + default y ---help--- If you say Y here, you will get support for terminal devices with display and keyboard devices. These are called "virtual" because you diff --git a/drivers/char/Makefile b/drivers/char/Makefile index 8a161c30e1dc..6850f6da7576 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -55,7 +55,6 @@ obj-$(CONFIG_RAW_DRIVER) += raw.o obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o obj-$(CONFIG_MSPEC) += mspec.o obj-$(CONFIG_MMTIMER) += mmtimer.o -obj-$(CONFIG_VIOCONS) += viocons.o obj-$(CONFIG_VIOTAPE) += viotape.o obj-$(CONFIG_HVCS) += hvcs.o obj-$(CONFIG_IBM_BSR) += bsr.o diff --git a/drivers/char/viocons.c b/drivers/char/viocons.c deleted file mode 100644 index 7feeb774a101..000000000000 --- a/drivers/char/viocons.c +++ /dev/null @@ -1,1167 +0,0 @@ -/* -*- linux-c -*- - * - * drivers/char/viocons.c - * - * iSeries Virtual Terminal - * - * Authors: Dave Boutcher - * Ryan Arnold - * Colin Devilbiss - * Stephen Rothwell - * - * (C) Copyright 2000, 2001, 2002, 2003, 2004 IBM Corporation - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of the - * License, or (at your option) anyu later version. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software Foundation, - * Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_VT -#error You must turn off CONFIG_VT to use CONFIG_VIOCONS -#endif - -#define VIOTTY_MAGIC (0x0DCB) -#define VTTY_PORTS 10 - -#define VIOCONS_KERN_WARN KERN_WARNING "viocons: " -#define VIOCONS_KERN_INFO KERN_INFO "viocons: " - -static DEFINE_SPINLOCK(consolelock); -static DEFINE_SPINLOCK(consoleloglock); - -static int vio_sysrq_pressed; - -#define VIOCHAR_NUM_BUF 16 - -/* - * Our port information. We store a pointer to one entry in the - * tty_driver_data - */ -static struct port_info { - int magic; - struct tty_struct *tty; - HvLpIndex lp; - u8 vcons; - u64 seq; /* sequence number of last HV send */ - u64 ack; /* last ack from HV */ -/* - * When we get writes faster than we can send it to the partition, - * buffer the data here. Note that used is a bit map of used buffers. - * It had better have enough bits to hold VIOCHAR_NUM_BUF the bitops assume - * it is a multiple of unsigned long - */ - unsigned long used; - u8 *buffer[VIOCHAR_NUM_BUF]; - int bufferBytes[VIOCHAR_NUM_BUF]; - int curbuf; - int bufferOverflow; - int overflowMessage; -} port_info[VTTY_PORTS]; - -#define viochar_is_console(pi) ((pi) == &port_info[0]) -#define viochar_port(pi) ((pi) - &port_info[0]) - -static void initDataEvent(struct viocharlpevent *viochar, HvLpIndex lp); - -static struct tty_driver *viotty_driver; - -static void hvlog(char *fmt, ...) -{ - int i; - unsigned long flags; - va_list args; - static char buf[256]; - - spin_lock_irqsave(&consoleloglock, flags); - va_start(args, fmt); - i = vscnprintf(buf, sizeof(buf) - 1, fmt, args); - va_end(args); - buf[i++] = '\r'; - HvCall_writeLogBuffer(buf, i); - spin_unlock_irqrestore(&consoleloglock, flags); -} - -static void hvlogOutput(const char *buf, int count) -{ - unsigned long flags; - int begin; - int index; - static const char cr = '\r'; - - begin = 0; - spin_lock_irqsave(&consoleloglock, flags); - for (index = 0; index < count; index++) { - if (buf[index] == '\n') { - /* - * Start right after the last '\n' or at the zeroth - * array position and output the number of characters - * including the newline. - */ - HvCall_writeLogBuffer(&buf[begin], index - begin + 1); - begin = index + 1; - HvCall_writeLogBuffer(&cr, 1); - } - } - if ((index - begin) > 0) - HvCall_writeLogBuffer(&buf[begin], index - begin); - spin_unlock_irqrestore(&consoleloglock, flags); -} - -/* - * Make sure we're pointing to a valid port_info structure. Shamelessly - * plagerized from serial.c - */ -static inline int viotty_paranoia_check(struct port_info *pi, - char *name, const char *routine) -{ - static const char *bad_pi_addr = VIOCONS_KERN_WARN - "warning: bad address for port_info struct (%s) in %s\n"; - static const char *badmagic = VIOCONS_KERN_WARN - "warning: bad magic number for port_info struct (%s) in %s\n"; - - if ((pi < &port_info[0]) || (viochar_port(pi) > VTTY_PORTS)) { - printk(bad_pi_addr, name, routine); - return 1; - } - if (pi->magic != VIOTTY_MAGIC) { - printk(badmagic, name, routine); - return 1; - } - return 0; -} - -/* - * Add data to our pending-send buffers. - * - * NOTE: Don't use printk in here because it gets nastily recursive. - * hvlog can be used to log to the hypervisor buffer - */ -static int buffer_add(struct port_info *pi, const char *buf, size_t len) -{ - size_t bleft; - size_t curlen; - const char *curbuf; - int nextbuf; - - curbuf = buf; - bleft = len; - while (bleft > 0) { - /* - * If there is no space left in the current buffer, we have - * filled everything up, so return. If we filled the previous - * buffer we would already have moved to the next one. - */ - if (pi->bufferBytes[pi->curbuf] == VIOCHAR_MAX_DATA) { - hvlog ("\n\rviocons: No overflow buffer available for memcpy().\n"); - pi->bufferOverflow++; - pi->overflowMessage = 1; - break; - } - - /* - * Turn on the "used" bit for this buffer. If it's already on, - * that's fine. - */ - set_bit(pi->curbuf, &pi->used); - - /* - * See if this buffer has been allocated. If not, allocate it. - */ - if (pi->buffer[pi->curbuf] == NULL) { - pi->buffer[pi->curbuf] = - kmalloc(VIOCHAR_MAX_DATA, GFP_ATOMIC); - if (pi->buffer[pi->curbuf] == NULL) { - hvlog("\n\rviocons: kmalloc failed allocating spaces for buffer %d.", - pi->curbuf); - break; - } - } - - /* Figure out how much we can copy into this buffer. */ - if (bleft < (VIOCHAR_MAX_DATA - pi->bufferBytes[pi->curbuf])) - curlen = bleft; - else - curlen = VIOCHAR_MAX_DATA - pi->bufferBytes[pi->curbuf]; - - /* Copy the data into the buffer. */ - memcpy(pi->buffer[pi->curbuf] + pi->bufferBytes[pi->curbuf], - curbuf, curlen); - - pi->bufferBytes[pi->curbuf] += curlen; - curbuf += curlen; - bleft -= curlen; - - /* - * Now see if we've filled this buffer. If not then - * we'll try to use it again later. If we've filled it - * up then we'll advance the curbuf to the next in the - * circular queue. - */ - if (pi->bufferBytes[pi->curbuf] == VIOCHAR_MAX_DATA) { - nextbuf = (pi->curbuf + 1) % VIOCHAR_NUM_BUF; - /* - * Move to the next buffer if it hasn't been used yet - */ - if (test_bit(nextbuf, &pi->used) == 0) - pi->curbuf = nextbuf; - } - } - return len - bleft; -} - -/* - * Send pending data - * - * NOTE: Don't use printk in here because it gets nastily recursive. - * hvlog can be used to log to the hypervisor buffer - */ -static void send_buffers(struct port_info *pi) -{ - HvLpEvent_Rc hvrc; - int nextbuf; - struct viocharlpevent *viochar; - unsigned long flags; - - spin_lock_irqsave(&consolelock, flags); - - viochar = (struct viocharlpevent *) - vio_get_event_buffer(viomajorsubtype_chario); - - /* Make sure we got a buffer */ - if (viochar == NULL) { - hvlog("\n\rviocons: Can't get viochar buffer in sendBuffers()."); - spin_unlock_irqrestore(&consolelock, flags); - return; - } - - if (pi->used == 0) { - hvlog("\n\rviocons: in sendbuffers(), but no buffers used.\n"); - vio_free_event_buffer(viomajorsubtype_chario, viochar); - spin_unlock_irqrestore(&consolelock, flags); - return; - } - - /* - * curbuf points to the buffer we're filling. We want to - * start sending AFTER this one. - */ - nextbuf = (pi->curbuf + 1) % VIOCHAR_NUM_BUF; - - /* - * Loop until we find a buffer with the used bit on - */ - while (test_bit(nextbuf, &pi->used) == 0) - nextbuf = (nextbuf + 1) % VIOCHAR_NUM_BUF; - - initDataEvent(viochar, pi->lp); - - /* - * While we have buffers with data, and our send window - * is open, send them - */ - while ((test_bit(nextbuf, &pi->used)) && - ((pi->seq - pi->ack) < VIOCHAR_WINDOW)) { - viochar->len = pi->bufferBytes[nextbuf]; - viochar->event.xCorrelationToken = pi->seq++; - viochar->event.xSizeMinus1 = - offsetof(struct viocharlpevent, data) + viochar->len; - - memcpy(viochar->data, pi->buffer[nextbuf], viochar->len); - - hvrc = HvCallEvent_signalLpEvent(&viochar->event); - if (hvrc) { - /* - * MUST unlock the spinlock before doing a printk - */ - vio_free_event_buffer(viomajorsubtype_chario, viochar); - spin_unlock_irqrestore(&consolelock, flags); - - printk(VIOCONS_KERN_WARN - "error sending event! return code %d\n", - (int)hvrc); - return; - } - - /* - * clear the used bit, zero the number of bytes in - * this buffer, and move to the next buffer - */ - clear_bit(nextbuf, &pi->used); - pi->bufferBytes[nextbuf] = 0; - nextbuf = (nextbuf + 1) % VIOCHAR_NUM_BUF; - } - - /* - * If we have emptied all the buffers, start at 0 again. - * this will re-use any allocated buffers - */ - if (pi->used == 0) { - pi->curbuf = 0; - - if (pi->overflowMessage) - pi->overflowMessage = 0; - - if (pi->tty) { - tty_wakeup(pi->tty); - } - } - - vio_free_event_buffer(viomajorsubtype_chario, viochar); - spin_unlock_irqrestore(&consolelock, flags); -} - -/* - * Our internal writer. Gets called both from the console device and - * the tty device. the tty pointer will be NULL if called from the console. - * Return total number of bytes "written". - * - * NOTE: Don't use printk in here because it gets nastily recursive. hvlog - * can be used to log to the hypervisor buffer - */ -static int internal_write(struct port_info *pi, const char *buf, size_t len) -{ - HvLpEvent_Rc hvrc; - size_t bleft; - size_t curlen; - const char *curbuf; - unsigned long flags; - struct viocharlpevent *viochar; - - /* - * Write to the hvlog of inbound data are now done prior to - * calling internal_write() since internal_write() is only called in - * the event that an lp event path is active, which isn't the case for - * logging attempts prior to console initialization. - * - * If there is already data queued for this port, send it prior to - * attempting to send any new data. - */ - if (pi->used) - send_buffers(pi); - - spin_lock_irqsave(&consolelock, flags); - - viochar = vio_get_event_buffer(viomajorsubtype_chario); - if (viochar == NULL) { - spin_unlock_irqrestore(&consolelock, flags); - hvlog("\n\rviocons: Can't get vio buffer in internal_write()."); - return -EAGAIN; - } - initDataEvent(viochar, pi->lp); - - curbuf = buf; - bleft = len; - - while ((bleft > 0) && (pi->used == 0) && - ((pi->seq - pi->ack) < VIOCHAR_WINDOW)) { - if (bleft > VIOCHAR_MAX_DATA) - curlen = VIOCHAR_MAX_DATA; - else - curlen = bleft; - - viochar->event.xCorrelationToken = pi->seq++; - memcpy(viochar->data, curbuf, curlen); - viochar->len = curlen; - viochar->event.xSizeMinus1 = - offsetof(struct viocharlpevent, data) + curlen; - - hvrc = HvCallEvent_signalLpEvent(&viochar->event); - if (hvrc) { - hvlog("viocons: error sending event! %d\n", (int)hvrc); - goto out; - } - curbuf += curlen; - bleft -= curlen; - } - - /* If we didn't send it all, buffer as much of it as we can. */ - if (bleft > 0) - bleft -= buffer_add(pi, curbuf, bleft); -out: - vio_free_event_buffer(viomajorsubtype_chario, viochar); - spin_unlock_irqrestore(&consolelock, flags); - return len - bleft; -} - -static struct port_info *get_port_data(struct tty_struct *tty) -{ - unsigned long flags; - struct port_info *pi; - - spin_lock_irqsave(&consolelock, flags); - if (tty) { - pi = (struct port_info *)tty->driver_data; - if (!pi || viotty_paranoia_check(pi, tty->name, - "get_port_data")) { - pi = NULL; - } - } else - /* - * If this is the console device, use the lp from - * the first port entry - */ - pi = &port_info[0]; - spin_unlock_irqrestore(&consolelock, flags); - return pi; -} - -/* - * Initialize the common fields in a charLpEvent - */ -static void initDataEvent(struct viocharlpevent *viochar, HvLpIndex lp) -{ - struct HvLpEvent *hev = &viochar->event; - - memset(viochar, 0, sizeof(struct viocharlpevent)); - - hev->flags = HV_LP_EVENT_VALID | HV_LP_EVENT_DEFERRED_ACK | - HV_LP_EVENT_INT; - hev->xType = HvLpEvent_Type_VirtualIo; - hev->xSubtype = viomajorsubtype_chario | viochardata; - hev->xSourceLp = HvLpConfig_getLpIndex(); - hev->xTargetLp = lp; - hev->xSizeMinus1 = sizeof(struct viocharlpevent); - hev->xSourceInstanceId = viopath_sourceinst(lp); - hev->xTargetInstanceId = viopath_targetinst(lp); -} - -/* - * early console device write - */ -static void viocons_write_early(struct console *co, const char *s, unsigned count) -{ - hvlogOutput(s, count); -} - -/* - * console device write - */ -static void viocons_write(struct console *co, const char *s, unsigned count) -{ - int index; - int begin; - struct port_info *pi; - - static const char cr = '\r'; - - /* - * Check port data first because the target LP might be valid but - * simply not active, in which case we want to hvlog the output. - */ - pi = get_port_data(NULL); - if (pi == NULL) { - hvlog("\n\rviocons_write: unable to get port data."); - return; - } - - hvlogOutput(s, count); - - if (!viopath_isactive(pi->lp)) - return; - - /* - * Any newline character found will cause a - * carriage return character to be emitted as well. - */ - begin = 0; - for (index = 0; index < count; index++) { - if (s[index] == '\n') { - /* - * Newline found. Print everything up to and - * including the newline - */ - internal_write(pi, &s[begin], index - begin + 1); - begin = index + 1; - /* Emit a carriage return as well */ - internal_write(pi, &cr, 1); - } - } - - /* If any characters left to write, write them now */ - if ((index - begin) > 0) - internal_write(pi, &s[begin], index - begin); -} - -/* - * Work out the device associate with this console - */ -static struct tty_driver *viocons_device(struct console *c, int *index) -{ - *index = c->index; - return viotty_driver; -} - -/* - * console device I/O methods - */ -static struct console viocons_early = { - .name = "viocons", - .write = viocons_write_early, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -static struct console viocons = { - .name = "viocons", - .write = viocons_write, - .device = viocons_device, - .flags = CON_PRINTBUFFER, - .index = -1, -}; - -/* - * TTY Open method - */ -static int viotty_open(struct tty_struct *tty, struct file *filp) -{ - int port; - unsigned long flags; - struct port_info *pi; - - port = tty->index; - - if ((port < 0) || (port >= VTTY_PORTS)) - return -ENODEV; - - spin_lock_irqsave(&consolelock, flags); - - pi = &port_info[port]; - /* If some other TTY is already connected here, reject the open */ - if ((pi->tty) && (pi->tty != tty)) { - spin_unlock_irqrestore(&consolelock, flags); - printk(VIOCONS_KERN_WARN - "attempt to open device twice from different ttys\n"); - return -EBUSY; - } - tty->driver_data = pi; - pi->tty = tty; - spin_unlock_irqrestore(&consolelock, flags); - - return 0; -} - -/* - * TTY Close method - */ -static void viotty_close(struct tty_struct *tty, struct file *filp) -{ - unsigned long flags; - struct port_info *pi; - - spin_lock_irqsave(&consolelock, flags); - pi = (struct port_info *)tty->driver_data; - - if (!pi || viotty_paranoia_check(pi, tty->name, "viotty_close")) { - spin_unlock_irqrestore(&consolelock, flags); - return; - } - if (tty->count == 1) - pi->tty = NULL; - spin_unlock_irqrestore(&consolelock, flags); -} - -/* - * TTY Write method - */ -static int viotty_write(struct tty_struct *tty, const unsigned char *buf, - int count) -{ - struct port_info *pi; - - pi = get_port_data(tty); - if (pi == NULL) { - hvlog("\n\rviotty_write: no port data."); - return -ENODEV; - } - - if (viochar_is_console(pi)) - hvlogOutput(buf, count); - - /* - * If the path to this LP is closed, don't bother doing anything more. - * just dump the data on the floor and return count. For some reason - * some user level programs will attempt to probe available tty's and - * they'll attempt a viotty_write on an invalid port which maps to an - * invalid target lp. If this is the case then ignore the - * viotty_write call and, since the viopath isn't active to this - * partition, return count. - */ - if (!viopath_isactive(pi->lp)) - return count; - - return internal_write(pi, buf, count); -} - -/* - * TTY put_char method - */ -static int viotty_put_char(struct tty_struct *tty, unsigned char ch) -{ - struct port_info *pi; - - pi = get_port_data(tty); - if (pi == NULL) - return 0; - - /* This will append '\r' as well if the char is '\n' */ - if (viochar_is_console(pi)) - hvlogOutput(&ch, 1); - - if (viopath_isactive(pi->lp)) - internal_write(pi, &ch, 1); - return 1; -} - -/* - * TTY write_room method - */ -static int viotty_write_room(struct tty_struct *tty) -{ - int i; - int room = 0; - struct port_info *pi; - unsigned long flags; - - spin_lock_irqsave(&consolelock, flags); - pi = (struct port_info *)tty->driver_data; - if (!pi || viotty_paranoia_check(pi, tty->name, "viotty_write_room")) { - spin_unlock_irqrestore(&consolelock, flags); - return 0; - } - - /* If no buffers are used, return the max size. */ - if (pi->used == 0) { - spin_unlock_irqrestore(&consolelock, flags); - return VIOCHAR_MAX_DATA * VIOCHAR_NUM_BUF; - } - - /* - * We retain the spinlock because we want to get an accurate - * count and it can change on us between each operation if we - * don't hold the spinlock. - */ - for (i = 0; ((i < VIOCHAR_NUM_BUF) && (room < VIOCHAR_MAX_DATA)); i++) - room += (VIOCHAR_MAX_DATA - pi->bufferBytes[i]); - spin_unlock_irqrestore(&consolelock, flags); - - if (room > VIOCHAR_MAX_DATA) - room = VIOCHAR_MAX_DATA; - return room; -} - -/* - * TTY chars_in_buffer method - */ -static int viotty_chars_in_buffer(struct tty_struct *tty) -{ - return 0; -} - -static int viotty_ioctl(struct tty_struct *tty, struct file *file, - unsigned int cmd, unsigned long arg) -{ - switch (cmd) { - /* - * the ioctls below read/set the flags usually shown in the leds - * don't use them - they will go away without warning - */ - case KDGETLED: - case KDGKBLED: - return put_user(0, (char *)arg); - - case KDSKBLED: - return 0; - } - return -ENOIOCTLCMD; -} - -/* - * Handle an open charLpEvent. Could be either interrupt or ack - */ -static void vioHandleOpenEvent(struct HvLpEvent *event) -{ - unsigned long flags; - struct viocharlpevent *cevent = (struct viocharlpevent *)event; - u8 port = cevent->virtual_device; - struct port_info *pi; - int reject = 0; - - if (hvlpevent_is_ack(event)) { - if (port >= VTTY_PORTS) - return; - - spin_lock_irqsave(&consolelock, flags); - /* Got the lock, don't cause console output */ - - pi = &port_info[port]; - if (event->xRc == HvLpEvent_Rc_Good) { - pi->seq = pi->ack = 0; - /* - * This line allows connections from the primary - * partition but once one is connected from the - * primary partition nothing short of a reboot - * of linux will allow access from the hosting - * partition again without a required iSeries fix. - */ - pi->lp = event->xTargetLp; - } - - spin_unlock_irqrestore(&consolelock, flags); - if (event->xRc != HvLpEvent_Rc_Good) - printk(VIOCONS_KERN_WARN - "handle_open_event: event->xRc == (%d).\n", - event->xRc); - - if (event->xCorrelationToken != 0) { - atomic_t *aptr= (atomic_t *)event->xCorrelationToken; - atomic_set(aptr, 1); - } else - printk(VIOCONS_KERN_WARN - "weird...got open ack without atomic\n"); - return; - } - - /* This had better require an ack, otherwise complain */ - if (!hvlpevent_need_ack(event)) { - printk(VIOCONS_KERN_WARN "viocharopen without ack bit!\n"); - return; - } - - spin_lock_irqsave(&consolelock, flags); - /* Got the lock, don't cause console output */ - - /* Make sure this is a good virtual tty */ - if (port >= VTTY_PORTS) { - event->xRc = HvLpEvent_Rc_SubtypeError; - cevent->subtype_result_code = viorc_openRejected; - /* - * Flag state here since we can't printk while holding - * a spinlock. - */ - reject = 1; - } else { - pi = &port_info[port]; - if ((pi->lp != HvLpIndexInvalid) && - (pi->lp != event->xSourceLp)) { - /* - * If this is tty is already connected to a different - * partition, fail. - */ - event->xRc = HvLpEvent_Rc_SubtypeError; - cevent->subtype_result_code = viorc_openRejected; - reject = 2; - } else { - pi->lp = event->xSourceLp; - event->xRc = HvLpEvent_Rc_Good; - cevent->subtype_result_code = viorc_good; - pi->seq = pi->ack = 0; - reject = 0; - } - } - - spin_unlock_irqrestore(&consolelock, flags); - - if (reject == 1) - printk(VIOCONS_KERN_WARN "open rejected: bad virtual tty.\n"); - else if (reject == 2) - printk(VIOCONS_KERN_WARN - "open rejected: console in exclusive use by another partition.\n"); - - /* Return the acknowledgement */ - HvCallEvent_ackLpEvent(event); -} - -/* - * Handle a close charLpEvent. This should ONLY be an Interrupt because the - * virtual console should never actually issue a close event to the hypervisor - * because the virtual console never goes away. A close event coming from the - * hypervisor simply means that there are no client consoles connected to the - * virtual console. - * - * Regardless of the number of connections masqueraded on the other side of - * the hypervisor ONLY ONE close event should be called to accompany the ONE - * open event that is called. The close event should ONLY be called when NO - * MORE connections (masqueraded or not) exist on the other side of the - * hypervisor. - */ -static void vioHandleCloseEvent(struct HvLpEvent *event) -{ - unsigned long flags; - struct viocharlpevent *cevent = (struct viocharlpevent *)event; - u8 port = cevent->virtual_device; - - if (hvlpevent_is_int(event)) { - if (port >= VTTY_PORTS) { - printk(VIOCONS_KERN_WARN - "close message from invalid virtual device.\n"); - return; - } - - /* For closes, just mark the console partition invalid */ - spin_lock_irqsave(&consolelock, flags); - /* Got the lock, don't cause console output */ - - if (port_info[port].lp == event->xSourceLp) - port_info[port].lp = HvLpIndexInvalid; - - spin_unlock_irqrestore(&consolelock, flags); - printk(VIOCONS_KERN_INFO "close from %d\n", event->xSourceLp); - } else - printk(VIOCONS_KERN_WARN - "got unexpected close acknowlegement\n"); -} - -/* - * Handle a config charLpEvent. Could be either interrupt or ack - */ -static void vioHandleConfig(struct HvLpEvent *event) -{ - struct viocharlpevent *cevent = (struct viocharlpevent *)event; - - HvCall_writeLogBuffer(cevent->data, cevent->len); - - if (cevent->data[0] == 0x01) - printk(VIOCONS_KERN_INFO "window resized to %d: %d: %d: %d\n", - cevent->data[1], cevent->data[2], - cevent->data[3], cevent->data[4]); - else - printk(VIOCONS_KERN_WARN "unknown config event\n"); -} - -/* - * Handle a data charLpEvent. - */ -static void vioHandleData(struct HvLpEvent *event) -{ - struct tty_struct *tty; - unsigned long flags; - struct viocharlpevent *cevent = (struct viocharlpevent *)event; - struct port_info *pi; - int index; - int num_pushed; - u8 port = cevent->virtual_device; - - if (port >= VTTY_PORTS) { - printk(VIOCONS_KERN_WARN "data on invalid virtual device %d\n", - port); - return; - } - - /* - * Hold the spinlock so that we don't take an interrupt that - * changes tty between the time we fetch the port_info - * pointer and the time we paranoia check. - */ - spin_lock_irqsave(&consolelock, flags); - pi = &port_info[port]; - - /* - * Change 05/01/2003 - Ryan Arnold: If a partition other than - * the current exclusive partition tries to send us data - * events then just drop them on the floor because we don't - * want his stinking data. He isn't authorized to receive - * data because he wasn't the first one to get the console, - * therefore he shouldn't be allowed to send data either. - * This will work without an iSeries fix. - */ - if (pi->lp != event->xSourceLp) { - spin_unlock_irqrestore(&consolelock, flags); - return; - } - - tty = pi->tty; - if (tty == NULL) { - spin_unlock_irqrestore(&consolelock, flags); - printk(VIOCONS_KERN_WARN "no tty for virtual device %d\n", - port); - return; - } - - if (tty->magic != TTY_MAGIC) { - spin_unlock_irqrestore(&consolelock, flags); - printk(VIOCONS_KERN_WARN "tty bad magic\n"); - return; - } - - /* - * Just to be paranoid, make sure the tty points back to this port - */ - pi = (struct port_info *)tty->driver_data; - if (!pi || viotty_paranoia_check(pi, tty->name, "vioHandleData")) { - spin_unlock_irqrestore(&consolelock, flags); - return; - } - spin_unlock_irqrestore(&consolelock, flags); - - /* - * Change 07/21/2003 - Ryan Arnold: functionality added to - * support sysrq utilizing ^O as the sysrq key. The sysrq - * functionality will only work if built into the kernel and - * then only if sysrq is enabled through the proc filesystem. - */ - num_pushed = 0; - for (index = 0; index < cevent->len; index++) { - /* - * Will be optimized away if !CONFIG_MAGIC_SYSRQ: - */ - if (sysrq_on()) { - /* 0x0f is the ascii character for ^O */ - if (cevent->data[index] == '\x0f') { - vio_sysrq_pressed = 1; - /* - * continue because we don't want to add - * the sysrq key into the data string. - */ - continue; - } else if (vio_sysrq_pressed) { - handle_sysrq(cevent->data[index], tty); - vio_sysrq_pressed = 0; - /* - * continue because we don't want to add - * the sysrq sequence into the data string. - */ - continue; - } - } - /* - * The sysrq sequence isn't included in this check if - * sysrq is enabled and compiled into the kernel because - * the sequence will never get inserted into the buffer. - * Don't attempt to copy more data into the buffer than we - * have room for because it would fail without indication. - */ - if(tty_insert_flip_char(tty, cevent->data[index], TTY_NORMAL) == 0) { - printk(VIOCONS_KERN_WARN "input buffer overflow!\n"); - break; - } - num_pushed++; - } - - if (num_pushed) - tty_flip_buffer_push(tty); -} - -/* - * Handle an ack charLpEvent. - */ -static void vioHandleAck(struct HvLpEvent *event) -{ - struct viocharlpevent *cevent = (struct viocharlpevent *)event; - unsigned long flags; - u8 port = cevent->virtual_device; - - if (port >= VTTY_PORTS) { - printk(VIOCONS_KERN_WARN "data on invalid virtual device\n"); - return; - } - - spin_lock_irqsave(&consolelock, flags); - port_info[port].ack = event->xCorrelationToken; - spin_unlock_irqrestore(&consolelock, flags); - - if (port_info[port].used) - send_buffers(&port_info[port]); -} - -/* - * Handle charLpEvents and route to the appropriate routine - */ -static void vioHandleCharEvent(struct HvLpEvent *event) -{ - int charminor; - - if (event == NULL) - return; - - charminor = event->xSubtype & VIOMINOR_SUBTYPE_MASK; - switch (charminor) { - case viocharopen: - vioHandleOpenEvent(event); - break; - case viocharclose: - vioHandleCloseEvent(event); - break; - case viochardata: - vioHandleData(event); - break; - case viocharack: - vioHandleAck(event); - break; - case viocharconfig: - vioHandleConfig(event); - break; - default: - if (hvlpevent_is_int(event) && hvlpevent_need_ack(event)) { - event->xRc = HvLpEvent_Rc_InvalidSubtype; - HvCallEvent_ackLpEvent(event); - } - } -} - -/* - * Send an open event - */ -static int send_open(HvLpIndex remoteLp, void *sem) -{ - return HvCallEvent_signalLpEventFast(remoteLp, - HvLpEvent_Type_VirtualIo, - viomajorsubtype_chario | viocharopen, - HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck, - viopath_sourceinst(remoteLp), - viopath_targetinst(remoteLp), - (u64)(unsigned long)sem, VIOVERSION << 16, - 0, 0, 0, 0); -} - -static const struct tty_operations serial_ops = { - .open = viotty_open, - .close = viotty_close, - .write = viotty_write, - .put_char = viotty_put_char, - .write_room = viotty_write_room, - .chars_in_buffer = viotty_chars_in_buffer, - .ioctl = viotty_ioctl, -}; - -static int __init viocons_init2(void) -{ - atomic_t wait_flag; - int rc; - - if (!firmware_has_feature(FW_FEATURE_ISERIES)) - return -ENODEV; - - /* +2 for fudge */ - rc = viopath_open(HvLpConfig_getPrimaryLpIndex(), - viomajorsubtype_chario, VIOCHAR_WINDOW + 2); - if (rc) - printk(VIOCONS_KERN_WARN "error opening to primary %d\n", rc); - - if (viopath_hostLp == HvLpIndexInvalid) - vio_set_hostlp(); - - /* - * And if the primary is not the same as the hosting LP, open to the - * hosting lp - */ - if ((viopath_hostLp != HvLpIndexInvalid) && - (viopath_hostLp != HvLpConfig_getPrimaryLpIndex())) { - printk(VIOCONS_KERN_INFO "open path to hosting (%d)\n", - viopath_hostLp); - rc = viopath_open(viopath_hostLp, viomajorsubtype_chario, - VIOCHAR_WINDOW + 2); /* +2 for fudge */ - if (rc) - printk(VIOCONS_KERN_WARN - "error opening to partition %d: %d\n", - viopath_hostLp, rc); - } - - if (vio_setHandler(viomajorsubtype_chario, vioHandleCharEvent) < 0) - printk(VIOCONS_KERN_WARN - "error seting handler for console events!\n"); - - /* - * First, try to open the console to the hosting lp. - * Wait on a semaphore for the response. - */ - atomic_set(&wait_flag, 0); - if ((viopath_isactive(viopath_hostLp)) && - (send_open(viopath_hostLp, (void *)&wait_flag) == 0)) { - printk(VIOCONS_KERN_INFO "hosting partition %d\n", - viopath_hostLp); - while (atomic_read(&wait_flag) == 0) - mb(); - atomic_set(&wait_flag, 0); - } - - /* - * If we don't have an active console, try the primary - */ - if ((!viopath_isactive(port_info[0].lp)) && - (viopath_isactive(HvLpConfig_getPrimaryLpIndex())) && - (send_open(HvLpConfig_getPrimaryLpIndex(), (void *)&wait_flag) - == 0)) { - printk(VIOCONS_KERN_INFO "opening console to primary partition\n"); - while (atomic_read(&wait_flag) == 0) - mb(); - } - - /* Initialize the tty_driver structure */ - viotty_driver = alloc_tty_driver(VTTY_PORTS); - viotty_driver->owner = THIS_MODULE; - viotty_driver->driver_name = "vioconsole"; - viotty_driver->name = "tty"; - viotty_driver->name_base = 1; - viotty_driver->major = TTY_MAJOR; - viotty_driver->minor_start = 1; - viotty_driver->type = TTY_DRIVER_TYPE_CONSOLE; - viotty_driver->subtype = 1; - viotty_driver->init_termios = tty_std_termios; - viotty_driver->flags = TTY_DRIVER_REAL_RAW | TTY_DRIVER_RESET_TERMIOS; - tty_set_operations(viotty_driver, &serial_ops); - - if (tty_register_driver(viotty_driver)) { - printk(VIOCONS_KERN_WARN "couldn't register console driver\n"); - put_tty_driver(viotty_driver); - viotty_driver = NULL; - } - - unregister_console(&viocons_early); - register_console(&viocons); - - return 0; -} - -static int __init viocons_init(void) -{ - int i; - - if (!firmware_has_feature(FW_FEATURE_ISERIES)) - return -ENODEV; - - printk(VIOCONS_KERN_INFO "registering console\n"); - for (i = 0; i < VTTY_PORTS; i++) { - port_info[i].lp = HvLpIndexInvalid; - port_info[i].magic = VIOTTY_MAGIC; - } - HvCall_setLogBufferFormatAndCodepage(HvCall_LogBuffer_ASCII, 437); - add_preferred_console("viocons", 0, NULL); - register_console(&viocons_early); - return 0; -} - -console_initcall(viocons_init); -module_init(viocons_init2); -- cgit v1.2.3 From c1ec8295f6e8c888230bbc9b7a416dc26d03688e Mon Sep 17 00:00:00 2001 From: Linus Torvalds Date: Thu, 7 Aug 2008 18:10:12 -0700 Subject: Fix up duplicate '__s3c2410wdt_stop()' function Looks like somebody didn't get enough sleep. Noticed-by: Stephen Rothwell Signed-off-by: Linus Torvalds --- drivers/watchdog/s3c2410_wdt.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 44bf5e4282e1..c417fb5e913f 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -115,17 +115,6 @@ static void s3c2410wdt_keepalive(void) spin_unlock(&wdt_lock); } -static void __s3c2410wdt_stop(void) -{ - unsigned long wtcon; - - spin_lock(&wdt_lock); - wtcon = readl(wdt_base + S3C2410_WTCON); - wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); - writel(wtcon, wdt_base + S3C2410_WTCON); - spin_unlock(&wdt_lock); -} - static void __s3c2410wdt_stop(void) { unsigned long wtcon; -- cgit v1.2.3