From ea6e3c31548ebd9be3d2405c680cac1706e7c7b2 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Wed, 19 Aug 2020 10:17:46 +0200 Subject: dt-bindings: mediatek: add mt7623 display-nodes mt7623 uses mt2701/mt8173 for drm, but have own compatibles Signed-off-by: Frank Wunderlich Acked-by: Rob Herring Signed-off-by: Chun-Kuang Hu --- Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt') diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt index 8e4729de8c85..f06f24d405a5 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt @@ -7,7 +7,7 @@ channel output. Required properties: - compatible: "mediatek,-dsi" - the supported chips are mt2701, mt8173 and mt8183. +- the supported chips are mt2701, mt7623, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - interrupts: The interrupt signal from the function block. - clocks: device clocks @@ -26,7 +26,7 @@ The MIPI TX configuration module controls the MIPI D-PHY. Required properties: - compatible: "mediatek,-mipi-tx" - the supported chips are mt2701, mt8173 and mt8183. +- the supported chips are mt2701, 7623, mt8173 and mt8183. - reg: Physical base address and length of the controller's registers - clocks: PLL reference clock - clock-output-names: name of the output clock line to the DSI encoder -- cgit v1.2.3