From 824590249b3cdf57d090d4c912f1497b8e61458f Mon Sep 17 00:00:00 2001 From: Amit Kumar Mahapatra Date: Tue, 11 Oct 2022 11:50:39 +0530 Subject: spi: dt-bindings: zynqmp-qspi: Add support for Xilinx Versal QSPI Add new compatible to support QSPI controller on Xilinx Versal SoCs. Signed-off-by: Amit Kumar Mahapatra Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221011062040.12116-7-amit.kumar-mahapatra@amd.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml index 6bf0edc57f4a..546c416cdb55 100644 --- a/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-zynqmp-qspi.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: xlnx,zynqmp-qspi-1.0 + enum: + - xlnx,versal-qspi-1.0 + - xlnx,zynqmp-qspi-1.0 reg: maxItems: 2 -- cgit v1.2.3 From 031837826886e254fefff7d8b849dc63b6a7e2b9 Mon Sep 17 00:00:00 2001 From: Amjad Ouled-Ameur Date: Fri, 21 Oct 2022 15:31:25 +0200 Subject: spi: dt-bindings: amlogic, meson-gx-spicc: Add pinctrl names for SPI signal states SPI pins of the SPICC Controller in Meson-GX needs to be controlled by pin biais when idle. Therefore define three pinctrl names: - default: SPI pins are controlled by spi function. - idle-high: SCLK pin is pulled-up, but MOSI/MISO are still controlled by spi function. - idle-low: SCLK pin is pulled-down, but MOSI/MISO are still controlled by spi function. Reported-by: Da Xue Signed-off-by: Neil Armstrong Signed-off-by: Amjad Ouled-Ameur Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221004-up-aml-fix-spi-v4-1-0342d8e10c49@baylibre.com Signed-off-by: Mark Brown --- .../bindings/spi/amlogic,meson-gx-spicc.yaml | 75 ++++++++++++++-------- 1 file changed, 47 insertions(+), 28 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml index 0c10f7678178..53eb6562b979 100644 --- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml @@ -10,9 +10,6 @@ title: Amlogic Meson SPI Communication Controller maintainers: - Neil Armstrong -allOf: - - $ref: "spi-controller.yaml#" - description: | The Meson SPICC is a generic SPI controller for general purpose Full-Duplex communications with dedicated 16 words RX/TX PIO FIFOs. @@ -43,31 +40,53 @@ properties: minItems: 1 maxItems: 2 -if: - properties: - compatible: - contains: - enum: - - amlogic,meson-g12a-spicc - -then: - properties: - clocks: - minItems: 2 - - clock-names: - items: - - const: core - - const: pclk - -else: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: core +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-g12a-spicc + + then: + properties: + clocks: + minItems: 2 + + clock-names: + items: + - const: core + - const: pclk + + else: + properties: + clocks: + maxItems: 1 + + clock-names: + items: + - const: core + + - if: + properties: + compatible: + contains: + enum: + - amlogic,meson-gx-spicc + + then: + properties: + pinctrl-0: true + pinctrl-1: true + pinctrl-2: true + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: idle-high + - const: idle-low required: - compatible -- cgit v1.2.3 From e8d6e1dd609696128e646a8c747b0f3fb1e02545 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Mon, 31 Oct 2022 23:25:59 +0100 Subject: spi: nuvoton,npcm-fiu: Change spi-nor@0 name to flash@0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The node name for flash memories has been standardized to "flash@...". Fix the example in nuvoton,npcm-fiu.txt accordingly. Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20221031222559.199509-1-j.neuschaefer@gmx.net Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt index c63ce4cc0a80..fb38e96d395f 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt @@ -51,7 +51,7 @@ fiu3: spi@c00000000 { clocks = <&clk NPCM7XX_CLK_AHB>; pinctrl-names = "default"; pinctrl-0 = <&spi3_pins>; - spi-nor@0 { + flash@0 { ... }; }; -- cgit v1.2.3 From bf585ccee22faf469d82727cf375868105b362f7 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 1 Nov 2022 18:32:51 +0100 Subject: spi: Update reference to struct spi_controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit struct spi_master has been renamed to struct spi_controller. Update the reference in spi.rst to make it clickable again. Fixes: 8caab75fd2c2 ("spi: Generalize SPI "master" to "controller"") Signed-off-by: Jonathan Neuschäfer Link: https://lore.kernel.org/r/20221101173252.1069294-1-j.neuschaefer@gmx.net Signed-off-by: Mark Brown --- Documentation/driver-api/spi.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/driver-api/spi.rst b/Documentation/driver-api/spi.rst index f64cb666498a..f28887045049 100644 --- a/Documentation/driver-api/spi.rst +++ b/Documentation/driver-api/spi.rst @@ -25,8 +25,8 @@ hardware, which may be as simple as a set of GPIO pins or as complex as a pair of FIFOs connected to dual DMA engines on the other side of the SPI shift register (maximizing throughput). Such drivers bridge between whatever bus they sit on (often the platform bus) and SPI, and expose -the SPI side of their device as a :c:type:`struct spi_master -`. SPI devices are children of that master, +the SPI side of their device as a :c:type:`struct spi_controller +`. SPI devices are children of that master, represented as a :c:type:`struct spi_device ` and manufactured from :c:type:`struct spi_board_info ` descriptors which are usually provided by -- cgit v1.2.3 From f6c911f3308c1cfb97ae1da6654080d7104e2df2 Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Thu, 17 Nov 2022 12:52:42 +0200 Subject: spi: dt-bindings: Introduce spi-cs-setup-ns property SPI NOR flashes have specific cs-setup time requirements without which they can't work at frequencies close to their maximum supported frequency, as they miss the first bits of the instruction command. Unrecognized commands are ignored, thus the flash will be unresponsive. Introduce the spi-cs-setup-ns property to allow spi devices to specify their cs setup time. Signed-off-by: Tudor Ambarus Link: https://lore.kernel.org/r/20221117105249.115649-2-tudor.ambarus@microchip.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index dca677f9e1b9..ead2cccf658f 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -44,6 +44,11 @@ properties: description: Maximum SPI clocking speed of the device in Hz. + spi-cs-setup-ns: + description: + Delay in nanosecods to be introduced by the controller after CS is + asserted. + spi-rx-bus-width: description: Bus width to the SPI bus used for read transfers. -- cgit v1.2.3 From bcd58c8ca0f89fe6a890f909916bc97561341a06 Mon Sep 17 00:00:00 2001 From: Kunihiko Hayashi Date: Thu, 24 Nov 2022 09:33:50 +0900 Subject: spi: Add Socionext F_OSPI controller bindings Add devicetree binding documentation for Socionext F_OSPI SPI flash controller. Signed-off-by: Kunihiko Hayashi Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221124003351.7792-2-hayashi.kunihiko@socionext.com Signed-off-by: Mark Brown --- .../devicetree/bindings/spi/socionext,f-ospi.yaml | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml b/Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml new file mode 100644 index 000000000000..9878d1446552 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/socionext,f-ospi.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext F_OSPI controller + +description: | + The Socionext F_OSPI is a controller used to interface with flash + memories using the SPI communication interface. + +maintainers: + - Kunihiko Hayashi + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: socionext,f-ospi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + num-cs: + minimum: 1 + maximum: 4 + +required: + - compatible + - reg + - clocks + - "#address-cells" + - "#size-cells" + +unevaluatedProperties: false + +examples: + - | + ospi0: spi@80000000 { + compatible = "socionext,f-ospi"; + reg = <0x80000000 0x1000>; + clocks = <&clks 0>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spansion,s25fl128s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; + }; -- cgit v1.2.3 From dd71cd4dd6c9bede8ee8277d650fcb9c1b12702c Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Thu, 24 Nov 2022 20:13:58 +0100 Subject: spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Flash Interface Unit (FIU) is the SPI flash controller in the Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct (memory-mapped) access to 16 MiB per chip. Larger flash chips can be accessed by software-defined SPI transfers. The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221124191400.287918-2-j.neuschaefer@gmx.net Signed-off-by: Mark Brown --- .../bindings/spi/nuvoton,wpcm450-fiu.yaml | 66 ++++++++++++++++++++++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml new file mode 100644 index 000000000000..ef94803e75d9 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,wpcm450-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton WPCM450 Flash Interface Unit (FIU) + +maintainers: + - Jonathan Neuschäfer + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: nuvoton,wpcm450-fiu + + reg: + items: + - description: FIU registers + - description: Memory-mapped flash contents + + reg-names: + items: + - const: control + - const: memory + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + nuvoton,shm: + $ref: /schemas/types.yaml#/definitions/phandle + description: a phandle to the SHM block (see ../arm/nuvoton,shm.yaml) + +required: + - compatible + - reg + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@c8000000 { + compatible = "nuvoton,wpcm450-fiu"; + reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "control", "memory"; + clocks = <&clk WPCM450_CLK_FIU>; + nuvoton,shm = <&shm>; + + flash@0 { + compatible = "jedec,spi-nor"; + }; + }; + + shm: syscon@c8001000 { + compatible = "nuvoton,wpcm450-shm", "syscon"; + reg = <0xc8001000 0x1000>; + }; -- cgit v1.2.3 From 1e2872f5912fbc87a00d00d49af98e428f4ff8b7 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 29 Nov 2022 11:22:24 +0100 Subject: spi: dt-bindings: nuvoton,wpcm450-fiu: Fix error in example (bogus include) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The nuvoton,wpcm450-fiu binding's example includes nuvoton,wpcm450-clk.h, which has not been merged yet, thus causing a dt_binding_check error on -next. Fix this error by simply hardcoding the clock index in the example, before the breakage spreads any further. Fixes: dd71cd4dd6c9b ("spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings") Reported-by: Rob Herring Reported-by: Conor Dooley Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221129102225.3598044-2-j.neuschaefer@gmx.net Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml index ef94803e75d9..e4162845fcc1 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -45,14 +45,13 @@ unevaluatedProperties: false examples: - | - #include spi@c8000000 { compatible = "nuvoton,wpcm450-fiu"; reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; reg-names = "control", "memory"; - clocks = <&clk WPCM450_CLK_FIU>; + clocks = <&clk 0>; nuvoton,shm = <&shm>; flash@0 { -- cgit v1.2.3 From c771b4eabd6a52afff0b6f01c361a9d04fa8cd9d Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 29 Nov 2022 11:22:25 +0100 Subject: spi: dt-bindings: nuvoton,wpcm450-fiu: Fix warning in example (missing reg property) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing "reg = <0>;" property to the flash@0 node in the example. Fixes: dd71cd4dd6c9b ("spi: Add Nuvoton WPCM450 Flash Interface Unit (FIU) bindings") Signed-off-by: Jonathan Neuschäfer Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221129102225.3598044-3-j.neuschaefer@gmx.net Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml | 1 + 1 file changed, 1 insertion(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml index e4162845fcc1..4e0d391e1d69 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,wpcm450-fiu.yaml @@ -56,6 +56,7 @@ examples: flash@0 { compatible = "jedec,spi-nor"; + reg = <0>; }; }; -- cgit v1.2.3 From bc9ab1b7a6c687370b5d4edf34064bf04af8d369 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Tue, 6 Dec 2022 16:54:10 -0600 Subject: spi: spi-fsl-lpspi: add num-cs binding for lpspi Add num-cs property to support multiple cs for lpspi. This property is optional. Signed-off-by: Han Xu Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20221206225410.604482-2-han.xu@nxp.com Signed-off-by: Mark Brown --- Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index 8b44284d30c6..94caa2b7e241 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -56,6 +56,13 @@ properties: this property to re-config the chipselect value in the LPSPI driver. type: boolean + num-cs: + description: + number of chip selects. + minimum: 1 + maximum: 2 + default: 1 + required: - compatible - reg @@ -80,4 +87,5 @@ examples: clock-names = "per", "ipg"; spi-slave; fsl,spi-only-use-cs1-sel; + num-cs = <2>; }; -- cgit v1.2.3 From 3cf241c3d56ff19f5192cb42a025bc6582b6e8fa Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 9 Dec 2022 11:16:43 -0600 Subject: spi: dt-bindings: Convert Synquacer SPI to DT schema Convert the Socionext Synquacer SPI binding to DT format. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20221209171644.3351787-1-robh@kernel.org Signed-off-by: Mark Brown --- .../bindings/spi/socionext,synquacer-spi.yaml | 73 ++++++++++++++++++++++ .../devicetree/bindings/spi/spi-synquacer.txt | 27 -------- MAINTAINERS | 2 +- 3 files changed, 74 insertions(+), 28 deletions(-) create mode 100644 Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml delete mode 100644 Documentation/devicetree/bindings/spi/spi-synquacer.txt (limited to 'Documentation') diff --git a/Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml b/Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml new file mode 100644 index 000000000000..45cbe744c7ff --- /dev/null +++ b/Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/socionext,synquacer-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext SynQuacer HS-SPI Controller + +maintainers: + - Masahisa Kojima + - Jassi Brar + +allOf: + - $ref: spi-controller.yaml# + +properties: + compatible: + const: socionext,synquacer-spi + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: core clock + - description: rate clock + + clock-names: + minItems: 1 + items: + - const: iHCLK + - const: iPCLK + + interrupts: + items: + - description: Receive Interrupt + - description: Transmit Interrupt + - description: Fault Interrupt + + socionext,use-rtm: + type: boolean + description: Enable using "retimed clock" for RX + + socionext,set-aces: + type: boolean + description: Enable same active clock edges field to be set + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + spi@ff110000 { + compatible = "socionext,synquacer-spi"; + reg = <0xff110000 0x1000>; + interrupts = , + , + ; + clocks = <&clk_hsspi>; + clock-names = "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + }; +... diff --git a/Documentation/devicetree/bindings/spi/spi-synquacer.txt b/Documentation/devicetree/bindings/spi/spi-synquacer.txt deleted file mode 100644 index 291dfa692d0a..000000000000 --- a/Documentation/devicetree/bindings/spi/spi-synquacer.txt +++ /dev/null @@ -1,27 +0,0 @@ -* Socionext Synquacer HS-SPI bindings - -Required Properties: -- compatible: should be "socionext,synquacer-spi" -- reg: physical base address of the controller and length of memory mapped - region. -- interrupts: should contain the "spi_rx", "spi_tx" and "spi_fault" interrupts. -- clocks: core clock iHCLK. Optional rate clock iPCLK (default is iHCLK) -- clock-names: Shall be "iHCLK" and "iPCLK" respectively - -Optional Properties: -- socionext,use-rtm: boolean, if required to use "retimed clock" for RX -- socionext,set-aces: boolean, if same active clock edges field to be set. - -Example: - - spi0: spi@ff110000 { - compatible = "socionext,synquacer-spi"; - reg = <0xff110000 0x1000>; - interrupts = , - , - ; - clocks = <&clk_hsspi>; - clock-names = "iHCLK"; - socionext,use-rtm; - socionext,set-aces; - }; diff --git a/MAINTAINERS b/MAINTAINERS index 046ff06ff97f..715636748f79 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19041,7 +19041,7 @@ M: Masahisa Kojima M: Jassi Brar L: linux-spi@vger.kernel.org S: Maintained -F: Documentation/devicetree/bindings/spi/spi-synquacer.txt +F: Documentation/devicetree/bindings/spi/socionext,synquacer-spi.yaml F: drivers/spi/spi-synquacer.c SOCIONEXT SYNQUACER I2C DRIVER -- cgit v1.2.3