From c00e4c54d56cdce018e9b09614511e5ad17e2f8c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sat, 18 Jun 2016 18:09:27 -0700 Subject: ARM: i.MX: system.c: Convert goto to if statement Using goto here doesn't bring any advantages and only makes the code flow less clear. No functional changes. Acked-by: Arnd Bergmann Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/system.c | 36 +++++++++++++++++------------------- 1 file changed, 17 insertions(+), 19 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 105d1ce4ed9d..d9f8b0e1d96a 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -106,26 +106,24 @@ void __init imx_init_l2cache(void) goto out; } - if (readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN) - goto skip_if_enabled; - - /* Configure the L2 PREFETCH and POWER registers */ - val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); - val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); - writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { + /* Configure the L2 PREFETCH and POWER registers */ + val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); + val |= 0x70800000; + /* + * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 + * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 + * But according to ARM PL310 errata: 752271 + * ID: 752271: Double linefill feature can cause data corruption + * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 + * Workaround: The only workaround to this erratum is to disable the + * double linefill feature. This is the default behavior. + */ + if (cpu_is_imx6q()) + val &= ~(1 << 30 | 1 << 23); + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); + } -skip_if_enabled: iounmap(l2x0_base); of_node_put(np); -- cgit v1.2.3 From cf30056384dfb2e3efc0cf0404979a24a1f5c194 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sat, 18 Jun 2016 18:09:28 -0700 Subject: ARM: i.MX: system.c: Remove redundant errata 752271 code Applying a fix for ARM errata 752271 would already be taken care by a call to a 'fixup' hook as a part of l2x0_of_init() -> __l2c_init() call chain. Moreso the code in 'fixup' function would do that based on the PL310's revsion information, whereas removed code does so based on SoC version which does not work very well on i.MX6Q+ which identifies itself as i.MX6Q as well but is not affected by 752271. Acked-by: Arnd Bergmann Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/system.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index d9f8b0e1d96a..b1533768adb0 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -110,17 +110,6 @@ void __init imx_init_l2cache(void) /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= 0x70800000; - /* - * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 - * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 - * But according to ARM PL310 errata: 752271 - * ID: 752271: Double linefill feature can cause data corruption - * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2 - * Workaround: The only workaround to this erratum is to disable the - * double linefill feature. This is the default behavior. - */ - if (cpu_is_imx6q()) - val &= ~(1 << 30 | 1 << 23); writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); } -- cgit v1.2.3 From b829037136766abf34456e2406bab67d689b3538 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sat, 18 Jun 2016 18:09:29 -0700 Subject: ARM: i.MX: system.c: Replace magic numbers Replace magic numbers used to form L310 Prefetch Control Register value. Acked-by: Arnd Bergmann Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/system.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index b1533768adb0..76d7ebe883d7 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -109,7 +109,10 @@ void __init imx_init_l2cache(void) if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { /* Configure the L2 PREFETCH and POWER registers */ val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); - val |= 0x70800000; + val |= L310_PREFETCH_CTRL_DBL_LINEFILL | + L310_PREFETCH_CTRL_INSTR_PREFETCH | + L310_PREFETCH_CTRL_DATA_PREFETCH | + L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); } -- cgit v1.2.3 From 1d9e94779956b765d316924cc39af2165ad631fb Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sat, 18 Jun 2016 18:09:30 -0700 Subject: ARM: i.MX: system.c: Tweak prefetch settings for performance Update Prefetch Control Register settings to match that of Freescale's Linux tree. As the commit e3addf1b773964eac7f797e8538c69481be4279c states (author Nitin Garg): "... set Prefetch offset to 15, since it improves memcpy performance by 35%. Don't enable Incr double Linefill enable since it adversely affects memcpy performance by about 32MB/s and reads by 90MB/s. Tested with 4K to 16MB sized src and dst aligned buffer..." Those results are also corroborated by our own testing. Acked-by: Arnd Bergmann Tested-by: Chris Healy Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/system.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index 76d7ebe883d7..bf7ab779d5bf 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -111,8 +111,12 @@ void __init imx_init_l2cache(void) val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL); val |= L310_PREFETCH_CTRL_DBL_LINEFILL | L310_PREFETCH_CTRL_INSTR_PREFETCH | - L310_PREFETCH_CTRL_DATA_PREFETCH | - L310_PREFETCH_CTRL_DBL_LINEFILL_INCR; + L310_PREFETCH_CTRL_DATA_PREFETCH; + + /* Set perfetch offset to improve performance */ + val &= ~L310_PREFETCH_CTRL_OFFSET_MASK; + val |= 15; + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL); } -- cgit v1.2.3 From 510aca642040cfb05e392218f6540ea35af51916 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sat, 18 Jun 2016 18:09:31 -0700 Subject: ARM: i.MX: Do not explicitly call l2x0_of_init() There's no need to explicitly call l2x0_of_init() since it will be called as a part of init_IRQ() (see arch/arm/kernel/irq.c for details). This way we can simplify imx_init_l2cache() and ditch the call to it on i.MX35 (which does not claim compatibility with "arm,pl310-cache") alltogether. Acked-by: Arnd Bergmann Suggested-by: Arnd Bergmann Signed-off-by: Andrey Smirnov Signed-off-by: Shawn Guo --- arch/arm/mach-imx/imx35-dt.c | 10 +++------- arch/arm/mach-imx/mach-imx6q.c | 2 ++ arch/arm/mach-imx/mach-imx6sl.c | 2 ++ arch/arm/mach-imx/mach-imx6sx.c | 2 ++ arch/arm/mach-imx/system.c | 12 ++++-------- 5 files changed, 13 insertions(+), 15 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c index e9396037235d..99bb63dedb87 100644 --- a/arch/arm/mach-imx/imx35-dt.c +++ b/arch/arm/mach-imx/imx35-dt.c @@ -20,20 +20,16 @@ #include "common.h" #include "mx35.h" -static void __init imx35_irq_init(void) -{ - imx_init_l2cache(); - mx35_init_irq(); -} - static const char * const imx35_dt_board_compat[] __initconst = { "fsl,imx35", NULL }; DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .map_io = mx35_map_io, .init_early = imx35_init_early, - .init_irq = imx35_irq_init, + .init_irq = mx35_init_irq, .dt_compat = imx35_dt_board_compat, MACHINE_END diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index cb27d566d5ab..b31890f1e4a4 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -407,6 +407,8 @@ static const char * const imx6q_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c index 300326373166..f9a9a362a88a 100644 --- a/arch/arm/mach-imx/mach-imx6sl.c +++ b/arch/arm/mach-imx/mach-imx6sl.c @@ -75,6 +75,8 @@ static const char * const imx6sl_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX6SL, "Freescale i.MX6 SoloLite (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_irq = imx6sl_init_irq, .init_machine = imx6sl_init_machine, .init_late = imx6sl_init_late, diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c index 6a0b0614de29..07a3a340f151 100644 --- a/arch/arm/mach-imx/mach-imx6sx.c +++ b/arch/arm/mach-imx/mach-imx6sx.c @@ -103,6 +103,8 @@ static const char * const imx6sx_dt_compat[] __initconst = { }; DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)") + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, .init_irq = imx6sx_init_irq, .init_machine = imx6sx_init_machine, .dt_compat = imx6sx_dt_compat, diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index bf7ab779d5bf..e442ed7f7ff5 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -98,13 +98,11 @@ void __init imx_init_l2cache(void) np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); if (!np) - goto out; + return; l2x0_base = of_iomap(np, 0); - if (!l2x0_base) { - of_node_put(np); - goto out; - } + if (!l2x0_base) + goto put_node; if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) { /* Configure the L2 PREFETCH and POWER registers */ @@ -121,9 +119,7 @@ void __init imx_init_l2cache(void) } iounmap(l2x0_base); +put_node: of_node_put(np); - -out: - l2x0_of_init(0, ~0); } #endif -- cgit v1.2.3 From 6f98cb22e4089c3eb63ff86fac010291a0e30241 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Fri, 24 Jun 2016 12:49:56 +0200 Subject: ARM: imx: remove cpu_is_mx1 check There is only one call site for this, and it's easily replaced by initializing the reset value at boot time. Signed-off-by: Arnd Bergmann Signed-off-by: Shawn Guo --- arch/arm/mach-imx/common.h | 1 + arch/arm/mach-imx/mm-imx1.c | 2 +- arch/arm/mach-imx/system.c | 16 +++++++++------- 3 files changed, 11 insertions(+), 8 deletions(-) (limited to 'arch/arm/mach-imx/system.c') diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 60d9ae63f76e..0a1d1f175b7a 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -54,6 +54,7 @@ struct platform_device *mxc_register_gpio(char *name, int id, void mxc_set_cpu_type(unsigned int type); void mxc_restart(enum reboot_mode, const char *); void mxc_arch_reset_init(void __iomem *); +void imx1_reset_init(void __iomem *); void imx_set_aips(void __iomem *); void imx_aips_allow_unprivileged_access(const char *compat); int mxc_device_init(void); diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c index e065fedb3ad4..9a42f19be81e 100644 --- a/arch/arm/mach-imx/mm-imx1.c +++ b/arch/arm/mach-imx/mm-imx1.c @@ -50,7 +50,7 @@ void __init mx1_init_irq(void) void __init imx1_soc_init(void) { - mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); + imx1_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR)); mxc_device_init(); mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256, diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c index e442ed7f7ff5..c06af650e6b1 100644 --- a/arch/arm/mach-imx/system.c +++ b/arch/arm/mach-imx/system.c @@ -34,25 +34,19 @@ static void __iomem *wdog_base; static struct clk *wdog_clk; +static int wcr_enable = (1 << 2); /* * Reset the system. It is called by machine_restart(). */ void mxc_restart(enum reboot_mode mode, const char *cmd) { - unsigned int wcr_enable; - if (!wdog_base) goto reset_fallback; if (!IS_ERR(wdog_clk)) clk_enable(wdog_clk); - if (cpu_is_mx1()) - wcr_enable = (1 << 0); - else - wcr_enable = (1 << 2); - /* Assert SRS signal */ imx_writew(wcr_enable, wdog_base); /* @@ -89,6 +83,14 @@ void __init mxc_arch_reset_init(void __iomem *base) clk_prepare(wdog_clk); } +#ifdef CONFIG_SOC_IMX1 +void __init imx1_reset_init(void __iomem *base) +{ + wcr_enable = (1 << 0); + mxc_arch_reset_init(base); +} +#endif + #ifdef CONFIG_CACHE_L2X0 void __init imx_init_l2cache(void) { -- cgit v1.2.3