From 2bda08dfc501967a7a7bd6f77f04afef14dc7271 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:07 +0300 Subject: arm64: meson: add dts bluetooth node for JetHub H1 Add bluetooth node for RTL8822CS uart to JetHub H1 dts file. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-2-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts index 6eafb908695f..fcb304c5a40f 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-jethome-jethub-j80.dts @@ -213,6 +213,12 @@ pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; pinctrl-names = "default"; uart-has-rtscts; + + bluetooth { + compatible = "realtek,rtl8822cs-bt"; + enable-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>; + host-wake-gpios = <&gpio GPIOX_18 GPIO_ACTIVE_HIGH>; + }; }; &uart_C { -- cgit v1.2.3 From cf94e26508ad411c2a618b00dfaae515affd0ca7 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:08 +0300 Subject: arm64: meson: dts: update serial alias in dts for JetHub D1 Change zigbee serial port alias to ttyAML2 for backward compatibility. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-3-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 561eec21b4de..9951217ef997 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -18,7 +18,7 @@ model = "JetHome JetHub J100"; aliases { serial0 = &uart_AO; /* Console */ - serial1 = &uart_AO_B; /* External UART (Wireless Module) */ + serial2 = &uart_AO_B; /* External UART (Wireless Module) */ ethernet0 = ðmac; }; -- cgit v1.2.3 From 81bbd2bd24a9ebac3871b293060df50445458c79 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:09 +0300 Subject: arm64: meson: update SDIO voltage in dts for JetHub D1 Fix the dts to match board's reference design: - update vddio_boot regulator to 3.3v (Wi-Fi SDIO module) - add vccq_1v8 regulator with 1.8v for eMMC SDIO In the first revision of JetHub D1 the vccq_1v8 regulator was 3.3v. All installed eMMC modules were tested to work in HS200 mode at 3.3v supply voltage. In the next revisions of the board eMMC will be powered with 1.8v according to the standard. Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-4-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 9951217ef997..1ab3cedfbee5 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -81,6 +81,15 @@ vddio_boot: regulator-vddio_boot { compatible = "regulator-fixed"; regulator-name = "VDDIO_BOOT"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vddao_3v3>; + regulator-always-on; + }; + + vccq_1v8: regulator-vccq_1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCCQ_1V8"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; vin-supply = <&vddao_3v3>; @@ -282,7 +291,7 @@ mmc-pwrseq = <&emmc_pwrseq>; vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vddio_boot>; + vqmmc-supply = <&vccq_1v8>; }; /* UART Bluetooth */ -- cgit v1.2.3 From 87a87657249316616138c103c2bdb7525c34d987 Mon Sep 17 00:00:00 2001 From: Vyacheslav Bocharov Date: Sat, 26 Mar 2022 10:51:10 +0300 Subject: arm64: meson: update WiFi SDIO in dts for JetHub D1 Fix the dts to match board's reference design: - update the maximum SDIO frequency to match 3.3v regulator (Wi-Fi SDIO module) Signed-off-by: Vyacheslav Bocharov Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220326075110.1462301-5-adeep@lexina.in --- arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts index 1ab3cedfbee5..8b0d586aa84e 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts +++ b/arch/arm64/boot/dts/amlogic/meson-axg-jethome-jethub-j100.dts @@ -257,8 +257,7 @@ bus-width = <4>; cap-sd-highspeed; - sd-uhs-sdr104; - max-frequency = <200000000>; + max-frequency = <50000000>; non-removable; disable-wp; -- cgit v1.2.3 From 4246d0bab2a8685e3d4aec2cb0ef8c526689ce96 Mon Sep 17 00:00:00 2001 From: Shawn Lin Date: Tue, 15 Mar 2022 17:27:06 +0800 Subject: arm64: dts: rockchip: Move drive-impedance-ohm to emmc phy on rk3399 drive-impedance-ohm is introduced for emmc phy instead of pcie phy. Fixes: fb8b7460c995 ("arm64: dts: rockchip: Define drive-impedance-ohm for RK3399's emmc-phy.") Signed-off-by: Shawn Lin Link: https://lore.kernel.org/r/1647336426-154797-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 080457a68e3c..88f26d89eea1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1534,6 +1534,7 @@ reg = <0xf780 0x24>; clocks = <&sdhci>; clock-names = "emmcclk"; + drive-impedance-ohm = <50>; #phy-cells = <0>; status = "disabled"; }; @@ -1544,7 +1545,6 @@ clock-names = "refclk"; #phy-cells = <1>; resets = <&cru SRST_PCIEPHY>; - drive-impedance-ohm = <50>; reset-names = "phy"; status = "disabled"; }; -- cgit v1.2.3 From 16c0f95d9ed14f033b5f1bd37e96d257b60c198c Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 11 Mar 2022 22:03:57 +0100 Subject: arm64: dts: rockchip: Add sata nodes to rk356x RK356x supports up to 3 sata controllers which were compatible with the existing snps,dwc-ahci binding. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220311210357.222830-7-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 5b0f528d6818..3e07d9f6a2d1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -8,6 +8,20 @@ / { compatible = "rockchip,rk3568"; + sata0: sata@fc000000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc000000 0 0x1000>; + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, + <&cru CLK_SATA0_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy0 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + pipe_phy_grf0: syscon@fdc70000 { compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; reg = <0x0 0xfdc70000 0x0 0x1000>; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 7cdef800cb3c..264dd030e703 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -230,6 +230,34 @@ }; }; + sata1: sata@fc400000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc400000 0 0x1000>; + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, + <&cru CLK_SATA1_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy1 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + + sata2: sata@fc800000 { + compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci"; + reg = <0 0xfc800000 0 0x1000>; + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, + <&cru CLK_SATA2_RXOOB>; + clock-names = "sata", "pmalive", "rxoob"; + interrupts = ; + phys = <&combphy2 PHY_TYPE_SATA>; + phy-names = "sata-phy"; + ports-implemented = <0x1>; + power-domains = <&power RK3568_PD_PIPE>; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ -- cgit v1.2.3 From a070d3b857d4961e1202754f7a86a0f796f808cd Mon Sep 17 00:00:00 2001 From: Robin Murphy Date: Tue, 15 Mar 2022 22:08:10 +0000 Subject: arm64: dts: rockchip: Add some pins for NanoPi4 The NanoPi4 boards have the RK808's always-on 32KHz clock wired to the SoC, so have it claim the relevant pinctrl to actually enable the CLK32K_IN input. The RK808's SLEEP pin is also wired to the SoC's AP_PWROFF output, so we may as well claim that too. Signed-off-by: Robin Murphy Link: https://lore.kernel.org/r/e870284a872567f163868b77267c01b77ed6f22a.1647381986.git.robin.murphy@arm.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi index 8c0ff6c96e03..248ad41a976b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi @@ -267,7 +267,7 @@ interrupt-parent = <&gpio1>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "default"; - pinctrl-0 = <&pmic_int_l>; + pinctrl-0 = <&pmic_int_l>, <&ap_pwroff>, <&clk_32k>; rockchip,system-power-controller; wakeup-source; -- cgit v1.2.3 From 6383f5a212a6b569ff15bc98ba8b3041a35db6ee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 11:04:10 +0800 Subject: arm64: dts: meson-s4: add pinctrl node Add pinctrl node for mesonn-s4 Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310030410.718-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index bf9ae1e1016b..e440efcf7a92 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { cpus { @@ -85,6 +86,22 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>; + periphs_pinctrl: pinctrl@4000 { + compatible = "amlogic,meson-s4-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@4000 { + reg = <0x0 0x4000 0x0 0x004c>, + <0x0 0x40c0 0x0 0x0220>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 82>; + }; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; -- cgit v1.2.3 From 393633936976fb8bd2c26ae76fa8d30822bb7fee Mon Sep 17 00:00:00 2001 From: Qianggui Song Date: Thu, 10 Mar 2022 17:26:45 +0800 Subject: arm64: dts: meson-s4: add gpio_intc node Add gpio interrupt controller node Signed-off-by: Qianggui Song Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220310092645.4303-1-qianggui.song@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index e440efcf7a92..dcaf7d98a6f1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -102,6 +102,16 @@ }; }; + gpio_intc: interrupt-controller@4080 { + compatible = "amlogic,meson-s4-gpio-intc", + "amlogic,meson-gpio-intc"; + reg = <0x0 0x4080 0x0 0x20>; + interrupt-controller; + #interrupt-cells = <2>; + amlogic,channel-interrupts = + <10 11 12 13 14 15 16 17 18 19 20 21>; + }; + uart_B: serial@7a000 { compatible = "amlogic,meson-s4-uart", "amlogic,meson-ao-uart"; -- cgit v1.2.3 From 085f7a298a14ed2a088c8ba01d2feda2499cbc72 Mon Sep 17 00:00:00 2001 From: Shunzhou Jiang Date: Fri, 1 Apr 2022 19:03:06 +0800 Subject: arm64: dts: add support for S4 power domain controller Enable power domain controller for Meson s4 SoC Signed-off-by: Shunzhou Jiang Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220401110306.3364551-1-shunzhou.jiang@amlogic.com --- arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi index dcaf7d98a6f1..2e45a8ecd9a0 100644 --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi @@ -61,6 +61,12 @@ #clock-cells = <0>; }; + pwrc: power-controller { + compatible = "amlogic,meson-s4-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + soc { compatible = "simple-bus"; #address-cells = <2>; -- cgit v1.2.3 From 8eb5092e64de30c003d8fe16a7eeacbfe29b7b84 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Thu, 24 Feb 2022 12:58:43 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the ADC stub node Fillup the ADC stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220224125843.29733-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 39 +++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 5d39e765c291..3ddf0f24071c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -260,8 +260,45 @@ }; adc: adc@10059000 { + compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc"; reg = <0 0x10059000 0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>, + <&cpg CPG_MOD R9A07G054_ADC_PCLK>; + clock-names = "adclk", "pclk"; + resets = <&cpg R9A07G054_ADC_PRESETN>, + <&cpg R9A07G054_ADC_ADRST_N>; + reset-names = "presetn", "adrst-n"; + power-domains = <&cpg>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + }; + channel@1 { + reg = <1>; + }; + channel@2 { + reg = <2>; + }; + channel@3 { + reg = <3>; + }; + channel@4 { + reg = <4>; + }; + channel@5 { + reg = <5>; + }; + channel@6 { + reg = <6>; + }; + channel@7 { + reg = <7>; + }; }; sbc: spi@10060000 { -- cgit v1.2.3 From ffe3f135dd28295114233d2a8073b3b15774b528 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:33 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the SDHI{0,1} stub nodes Fillup the SDHI{0,1} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 3ddf0f24071c..0b0e924e28ae 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,13 +398,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g054", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G054_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; eth0: ethernet@11c20000 { -- cgit v1.2.3 From b0bb96e5162368814acdc76da7fdb2cd574f58c2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:34 +0000 Subject: arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting gpio-hog pins related to SDHI Drop deleting gpio-hog pins related to SDHI0/1 so that SDHI functionality gets enabled on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index fc334b4c2aa4..191ce17fbeac 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -20,7 +20,4 @@ &pinctrl { /delete-node/ can0-stb-hog; /delete-node/ can1-stb-hog; - /delete-node/ gpio-sd0-pwr-en-hog; - /delete-node/ sd0-dev-sel-hog; - /delete-node/ sd1-pwr-en-hog; }; -- cgit v1.2.3 From 791b7e1dcb9fe9f9e7f7dd1b6714cd8e0f6ee349 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:35 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 31 +++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0b0e924e28ae..6e89bd126788 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -234,8 +234,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G054_CANFD_RSTP_N>, + <&cpg R9A07G054_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { -- cgit v1.2.3 From e3ab4573761418ba1b853ec33e5db723db279ff5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:36 +0000 Subject: arm64: dts: renesas: r9a07g054l2-smarc: Drop deleting can{0,1}-stb-hog nodes Drop deleting can{0,1}-stb-hog nodes so that CAN becomes operational on Renesas RZ/V2L SMARC EVK. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts index 191ce17fbeac..4e07e1a0fb66 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts @@ -16,8 +16,3 @@ model = "Renesas SMARC EVK based on r9a07g054l2"; compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054"; }; - -&pinctrl { - /delete-node/ can0-stb-hog; - /delete-node/ can1-stb-hog; -}; -- cgit v1.2.3 From e46a72e0398e570fbab5905ea6be67dc76d678f4 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:37 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the I2C{0,1,2,3} stub nodes Fillup the I2C{0,1,2,3} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 73 ++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 6e89bd126788..fafb986fe3bc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -270,22 +270,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g054", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G054_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { -- cgit v1.2.3 From 8d3da65c4c40d77977799f58fa6465bdc723536f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:38 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the sbc stub node Fillup the sbc stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index fafb986fe3bc..1207a99bf3fe 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -398,12 +398,20 @@ }; sbc: spi@10060000 { + compatible = "renesas,r9a07g054-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>, + <&cpg CPG_MOD R9A07G054_SPI_CLK>; + resets = <&cpg R9A07G054_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { -- cgit v1.2.3 From f458b7707c9c4acabb7cdf6c0fcfde1a506b360f Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:39 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the OSTM{0,1,2} stub nodes Fillup the OSTM{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 1207a99bf3fe..50cb2f0e6e73 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -629,18 +629,36 @@ }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>; + resets = <&cpg R9A07G054_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>; + resets = <&cpg R9A07G054_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g054-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>; + resets = <&cpg R9A07G054_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; }; -- cgit v1.2.3 From f35a868bcf95c066a00dcae9e7ee42d85eaf05b2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:40 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the WDT{0,1,2} stub nodes Fillup the WDT{0,1,2} stub nodes in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 36 +++++++++++++++++++++++++++--- 1 file changed, 33 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 50cb2f0e6e73..a3623e70f02c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -614,18 +614,48 @@ }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt1: watchdog@12800c00 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800C00 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT1_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT1_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g054-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G054_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G054_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { -- cgit v1.2.3 From cd0339ec25895c0be45656908442bc121bbadacb Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:41 +0000 Subject: arm64: dts: renesas: r9a07g054: Add SSI{1,2,3} nodes and fillup the SSI0 stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 80 +++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index a3623e70f02c..e3a9f78b7fb8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -96,9 +96,87 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g054-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G054_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { -- cgit v1.2.3 From a8e2a77b644ac23319f0e7c3e8d9dcd6dc9aebd1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:42 +0000 Subject: arm64: dts: renesas: r9a07g054: Add USB2.0 phy and host support Add USB2.0 phy and host support to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-11-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 74 +++++++++++++++++++++++++++--- 1 file changed, 67 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e3a9f78b7fb8..7d9ea17352a4 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -652,38 +652,98 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g054-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>; + resets = <&cpg R9A07G054_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G054_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g054", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { -- cgit v1.2.3 From c9c4e5b7d202cce2f488a56c06332016380890b3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:43 +0000 Subject: arm64: dts: renesas: r9a07g054: Add USB2.0 device support Fillup the hsusb stub node in RZ/V2L (R9A07G054) SoC DTSI which enables USB2.0 device support. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-12-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 7d9ea17352a4..8bbdcf48bb61 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -747,8 +747,22 @@ }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g054", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>, + <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G054_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { -- cgit v1.2.3 From 3f3c46d4e2cb38bfa7d1f24c2099a20229867d9d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Sun, 27 Feb 2022 20:37:44 +0000 Subject: arm64: dts: renesas: r9a07g054: Add SPI{0,2} nodes and fillup SPI1 stub node Add SPI{0,2} nodes and fillup SPI1 stub node in RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220227203744.18355-13-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 43 +++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 8bbdcf48bb61..9e730171efa8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -179,11 +179,52 @@ status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; + resets = <&cpg R9A07G054_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@1004b000 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; + resets = <&cpg R9A07G054_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; + resets = <&cpg R9A07G054_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { -- cgit v1.2.3 From 1889f4798c443dfd4993ba9bbbf4ed7bf801d94b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 2 Mar 2022 07:40:43 +0000 Subject: arm64: dts: renesas: r9a07g044c2-smarc: Enable usb2.0 Enable usb2.0 host/device functionality on RZ/G2LC SMARC EVK by deleting phyrst, usb2_phy{0,1}, ehci/ohci{0,1} and hsusb entries from board DT, so that entries from common dtsi kick in and make USB2.0 functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220302074043.21525-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 46 ---------------------- .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 11 ++++++ 2 files changed, 11 insertions(+), 46 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 5a5cea82a5d9..d5254b16b0b3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,24 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &i2c0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -50,22 +32,6 @@ status = "disabled"; }; -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; @@ -77,15 +43,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 37ff2091582e..5f5ec21e655c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -90,5 +90,16 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* VBUS */ + ; /* OVC */ + }; }; -- cgit v1.2.3 From a2b642d89e4beeddbfbd7be6108db2b7aaef78b6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:52 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-pinfunction: Sort the nodes Sort the pinctrl nodes alphabetically. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 24 +++++++++++----------- 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 5f5ec21e655c..53759c3ddecb 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -12,11 +12,6 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; - scif0_pins: scif0 { - pinmux = , /* TxD */ - ; /* RxD */ - }; - #if SW_SCIF_CAN /* SW8 should be at position 2->1 */ can1_pins: can1 { @@ -25,13 +20,6 @@ }; #endif - scif1_pins: scif1 { - pinmux = , /* TxD */ - , /* RxD */ - , /* CTS# */ - ; /* RTS# */ - }; - #if SW_RSPI_CAN /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ can1-stb-hog { @@ -47,6 +35,18 @@ }; #endif + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + scif1_pins: scif1 { + pinmux = , /* TxD */ + , /* RxD */ + , /* CTS# */ + ; /* RTS# */ + }; + sd1-pwr-en-hog { gpio-hog; gpios = ; -- cgit v1.2.3 From 0a7c1c888a0c0276837f2cd7190683474a136506 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:53 +0000 Subject: arm64: dts: renesas: rzg2l-smarc: Move out i2c3 and Audio codec from common dtsi On RZ/G2L SoM module, the Audio codec is connected to i2c3 bus whereas on RZ/G2LC, it is connected to i2c2 bus. So move out i2c3 and wm8978 nodes from common dtsi to soc specific dtsi. While at it add wm8978 node to RZ/G2LC SoC specific dtsi to fix the build error. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 15 --------------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++ 4 files changed, 26 insertions(+), 21 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index d5254b16b0b3..dc39b05e9256 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -26,12 +26,6 @@ status = "disabled"; }; -&i2c3 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 588117aafaca..8dd1c69a6749 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -26,7 +26,6 @@ serial0 = &scif0; i2c0 = &i2c0; i2c1 = &i2c1; - i2c3 = &i2c3; }; chosen { @@ -131,20 +130,6 @@ status = "okay"; }; -&i2c3 { - pinctrl-0 = <&i2c3_pins>; - pinctrl-names = "default"; - clock-frequency = <400000>; - - status = "okay"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { dr_mode = "otg"; status = "okay"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 33ddfd18bd56..c934cd3633a4 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -14,6 +14,21 @@ / { aliases { serial1 = &scif2; + i2c3 = &i2c3; + }; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index df7631fe5fac..55d3b73f84e7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -43,6 +43,7 @@ / { aliases { serial1 = &scif1; + i2c2 = &i2c2; }; }; @@ -59,6 +60,16 @@ }; #endif +&i2c2 { + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + /* * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board * SW1 should be at position 2->3 so that SER0_CTS# line is activated -- cgit v1.2.3 From 4fa1edc83b2b2b467ed47bd682c7beab81a38ef5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:54 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable i2c{0,1,2} Enable i2c{0,1} on RZ/G2LC SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable i2c2 by adding to soc dtsi. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 12 ------------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 6 +++++- 3 files changed, 20 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index dc39b05e9256..52b834205126 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -14,18 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 53759c3ddecb..1322e5bcd456 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -35,6 +35,21 @@ }; #endif + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 55d3b73f84e7..f73b4acb8f9e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -61,7 +61,11 @@ #endif &i2c2 { - status = "disabled"; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; wm8978: codec@1a { compatible = "wlf,wm8978"; -- cgit v1.2.3 From 4eb6a6bb8ef31491c217167ecce2c0a26fd4f34e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 3 Mar 2022 16:41:55 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable Audio Enable Audio on RZ/G2LC SMARC EVK by deleting ssi0 entries from board DT and adding pincontrol entries to the soc-pinctrl dtsi, so that entries from common dtsi kick in and make audio functionality operational. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220303164155.7706-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++ 2 files changed, 7 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 52b834205126..74a2f2bade10 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -19,9 +19,3 @@ /delete-property/ pinctrl-names; status = "disabled"; }; - -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index 1322e5bcd456..d275a55333e3 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -106,6 +106,13 @@ input-enable; }; + ssi0_pins: ssi0 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; + usb0_pins: usb0 { pinmux = , /* VBUS */ , /* OVC */ -- cgit v1.2.3 From 018d7b93477fbb04ba7b4bc4c355793d644e45da Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:33 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-som: Enable serial NOR flash Enable mt25qu512a flash connected to QSPI0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 40 +++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 88a7938017aa..80c9a1146cb7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -110,6 +110,18 @@ line-name = "gpio_sd0_pwr_en"; }; + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + /* * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] * The below switch logic can be used to select the device between @@ -175,6 +187,34 @@ }; }; +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + #if (!SW_SD0_DEV_SEL) &sdhi0 { pinctrl-0 = <&sdhi0_pins>; -- cgit v1.2.3 From a081c4fe98f6662fbddb1597a6203be669641af1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:34 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2LC SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 80c9a1146cb7..05b117ac414c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -84,6 +84,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ -- cgit v1.2.3 From 6f57895c49bc36a6ba125b9926d4b9699376e656 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 7 Mar 2022 19:24:35 +0000 Subject: arm64: dts: renesas: rzg2lc-smarc-som: Add vdd core regulator Add vdd core regulator (1.1 V) for GPU. This patch add regulator support for GPU. The H/W manual mentions nothing about a GPU regulator. So using vdd core regulator for GPU. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220307192436.13237-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 05b117ac414c..959a0ad1d367 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -41,6 +41,15 @@ regulator-always-on; }; + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + vccq_sdhi0: regulator-vccq-sdhi0 { compatible = "regulator-gpio"; @@ -84,6 +93,10 @@ clock-frequency = <24000000>; }; +&gpu { + mali-supply = <®_1p1v>; +}; + &ostm1 { status = "okay"; }; -- cgit v1.2.3 From 809823b853a2559d04948ea43800408f00c8db23 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:22 +0000 Subject: arm64: dts: renesas: r9a07g054: Fillup the GPU node Renesas RZ/V2L SoC has Mali-G31 GPU, this patch fills up the GPU node and adds opp table to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 62 +++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 9e730171efa8..e4f1defa0ff8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -83,6 +83,50 @@ }; }; + gpu_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1100000>; + }; + + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1100000>; + }; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1100000>; + }; + + opp-62500000 { + opp-hz = /bits/ 64 <62500000>; + opp-microvolt = <1100000>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <1100000>; + }; + }; + psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; @@ -606,8 +650,24 @@ }; gpu: gpu@11840000 { + compatible = "renesas,r9a07g054-mali", + "arm,mali-bifrost"; reg = <0x0 0x11840000 0x0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + interrupt-names = "job", "mmu", "gpu", "event"; + clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>, + <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>; + clock-names = "gpu", "bus", "bus_ace"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_GPU_RESETN>, + <&cpg R9A07G054_GPU_AXI_RESETN>, + <&cpg R9A07G054_GPU_ACE_RESETN>; + reset-names = "rst", "axi_rst", "ace_rst"; + operating-points-v2 = <&gpu_opp_table>; }; gic: interrupt-controller@11900000 { -- cgit v1.2.3 From 4b7e7f10835a504501a04a82498234da78c4117e Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:23 +0000 Subject: arm64: dts: renesas: r9a07g054: Add OPP table Add OPP table for RZ/V2L SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index e4f1defa0ff8..bdf0a104e82c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -65,6 +92,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; cpu1: cpu@100 { @@ -74,6 +102,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G054_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { -- cgit v1.2.3 From f6a2f28ab19ca5ce5bbd3a821fe19468d7c921dc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 8 Mar 2022 22:33:24 +0000 Subject: arm64: dts: renesas: r9a07g054: Add TSU node Add TSU and thermal-zones nodes to RZ/V2L (R9A07G054) SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220308223324.7456-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 41 ++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index bdf0a104e82c..f35aa0311e9c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -589,6 +589,16 @@ }; }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g054-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>; + resets = <&cpg R9A07G054_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { compatible = "renesas,r9a07g054-rpc-if", "renesas,rzg2l-rpc-if"; @@ -974,6 +984,37 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -- cgit v1.2.3 From 9a4259e59694136add708608fce861a1beff9635 Mon Sep 17 00:00:00 2001 From: Kieran Bingham Date: Wed, 9 Mar 2022 19:06:31 +0000 Subject: arm64: dts: renesas: falcon-cpu: Use INTC_EX for SN65DSI86 The INTC block is a better choice for handling the interrupts on the V3U as the INTC will always be powered, while the GPIO block may be de-clocked if not in use. Further more, it may be likely to have a lower power consumption as it does not need to drive the pins. Switch the interrupt parent and interrupts definition from gpio1 to irq0 on intc_ex, and configure the PFC accordingly. Signed-off-by: Kieran Bingham Link: https://lore.kernel.org/r/20220309190631.1576372-1-kieran.bingham+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 6af3f4f4f268..53c4a26198e3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -192,14 +192,17 @@ clock-frequency = <400000>; bridge@2c { + pinctrl-0 = <&irq0_pins>; + pinctrl-names = "default"; + compatible = "ti,sn65dsi86"; reg = <0x2c>; clocks = <&sn65dsi86_refclk>; clock-names = "refclk"; - interrupt-parent = <&gpio1>; - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; vccio-supply = <®_1p8v>; vpll-supply = <®_1p8v>; @@ -271,6 +274,11 @@ function = "i2c6"; }; + irq0_pins: irq0 { + groups = "intc_ex_irq0"; + function = "intc_ex"; + }; + keys_pins: keys { pins = "GP_6_18", "GP_6_19", "GP_6_20"; bias-pull-up; -- cgit v1.2.3 From d63833b8699c585d9ed32d968563b5eba69df9f6 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:07 +0100 Subject: arm64: dts: renesas: r8a779a0: Add CANFD device node This patch adds a CANFD device node for r8a779a0. Based on patch by Kazuya Mizuguchi. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-3-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 56 +++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c4be288b1912..c80f4584035e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -24,6 +24,13 @@ i2c6 = &i2c6; }; + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -596,6 +603,55 @@ status = "disabled"; }; + canfd: can@e6660000 { + compatible = "renesas,r8a779a0-canfd"; + reg = <0 0xe6660000 0 0x8000>; + interrupts = , + ; + interrupt-names = "ch_int", "g_int"; + clocks = <&cpg CPG_MOD 328>, + <&cpg CPG_CORE R8A779A0_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>; + assigned-clock-rates = <80000000>; + power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + + channel2 { + status = "disabled"; + }; + + channel3 { + status = "disabled"; + }; + + channel4 { + status = "disabled"; + }; + + channel5 { + status = "disabled"; + }; + + channel6 { + status = "disabled"; + }; + + channel7 { + status = "disabled"; + }; + }; + avb0: ethernet@e6800000 { compatible = "renesas,etheravb-r8a779a0", "renesas,etheravb-rcar-gen3"; -- cgit v1.2.3 From d2194187aa4f9a4c2df010962e4e008efc3f930b Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 9 Mar 2022 17:26:08 +0100 Subject: arm64: dts: renesas: falcon: Enable CANFD 0 and 1 Enables confirmed-working CAN interfaces 0 and 1 on the Falcon board. Signed-off-by: Ulrich Hecht Link: https://lore.kernel.org/r/20220309162609.3726306-4-uli+renesas@fpond.eu Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts index e46dc9aa0a43..b2e67b82caf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts @@ -37,6 +37,20 @@ }; }; +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; + + channel1 { + status = "okay"; + }; +}; + &i2c0 { eeprom@51 { compatible = "rohm,br24g01", "atmel,24c01"; @@ -65,4 +79,14 @@ }; }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; }; -- cgit v1.2.3 From 0182581a9f63764bcbdbc68e98881b50e03fc4c4 Mon Sep 17 00:00:00 2001 From: Koji Matsuoka Date: Sat, 19 Mar 2022 23:33:05 +0100 Subject: arm64: dts: renesas: r8a77961: Add CAN-FD node Add the device node for the CAN-FD device on R-Car M3-W+. Signed-off-by: Koji Matsuoka Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220319223306.60782-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 68cbbb322acf..7d522ea5fca2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1222,6 +1222,31 @@ status = "disabled"; }; + canfd: can@e66c0000 { + compatible = "renesas,r8a77961-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A77961_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + pwm0: pwm@e6e30000 { compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; reg = <0 0xe6e30000 0 8>; -- cgit v1.2.3 From 33c7874b44324fe9657d19ca01ef4ae4403a5a4b Mon Sep 17 00:00:00 2001 From: "Nícolas F. R. A. Prado" Date: Tue, 1 Mar 2022 15:31:47 -0500 Subject: arm64: dts: mediatek: Format mediatek,larbs as an array of phandles MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas") updated the mediatek,larbs property in the mediatek,iommu.yaml dt-binding to make it clearer that the phandles passed to the property are independent, rather than subsequent arguments to the first phandle. Update the mediatek,larbs property in the arm64 Devicetrees to use the same formatting. This change doesn't impact any behavior: the compiled dtb is exactly the same. It does however fix the warnings generated by dtbs_check. Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220301203147.1143782-2-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 6 +++--- arch/arm64/boot/dts/mediatek/mt8167.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index a27b7628c5f7..86579330a8bd 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -329,8 +329,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb6>; #iommu-cells = <1>; }; @@ -346,7 +346,7 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb4 &larb5 &larb7>; + mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi index 9029051624a6..54655f2feb04 100644 --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi @@ -174,7 +174,7 @@ iommu: m4u@10203000 { compatible = "mediatek,mt8167-m4u"; reg = <0 0x10203000 0 0x1000>; - mediatek,larbs = <&larb0 &larb1 &larb2>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>; interrupts = ; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 2b7d331a4588..042feaedda4a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -588,8 +588,8 @@ interrupts = ; clocks = <&infracfg CLK_INFRA_M4U>; clock-names = "bclk"; - mediatek,larbs = <&larb0 &larb1 &larb2 - &larb3 &larb4 &larb5>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb3>, <&larb4>, <&larb5>; #iommu-cells = <1>; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 4b08691ed39e..5d4a1dd55adc 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -682,8 +682,8 @@ compatible = "mediatek,mt8183-m4u"; reg = <0 0x10205000 0 0x1000>; interrupts = ; - mediatek,larbs = <&larb0 &larb1 &larb2 &larb3 - &larb4 &larb5 &larb6>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, + <&larb4>, <&larb5>, <&larb6>; #iommu-cells = <1>; }; -- cgit v1.2.3 From 261691b40128e6b76bb94d562457d8a5236cc7fa Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:13 +0800 Subject: arm64: dts: mt8192: Add pwrap node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add pwrap node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 411feb294613..76428599444e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -523,6 +523,18 @@ clock-names = "clk13m"; }; + pwrap: pwrap@10026000 { + compatible = "mediatek,mt6873-pwrap"; + reg = <0 0x10026000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; -- cgit v1.2.3 From c63556ec6bfe21cde6ab2fb0b651112bc5e99e56 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:16 +0800 Subject: arm64: dts: mt8192: Add SCP node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add SCP node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-5-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 76428599444e..4f26a398d970 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -679,6 +679,18 @@ status = "disabled"; }; + scp: scp@10500000 { + compatible = "mediatek,mt8192-scp"; + reg = <0 0x10500000 0 0x100000>, + <0 0x10700000 0 0x8000>, + <0 0x10720000 0 0xe0000>; + reg-names = "sram", "l1tcm", "cfg"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_SCPSYS>; + clock-names = "main"; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; -- cgit v1.2.3 From 40de66b8bbbb6137022652954167d5c570bb93c2 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:17 +0800 Subject: arm64: dts: mt8192: Add usb-phy node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-6-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 4f26a398d970..946ebcb2bb5f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -848,6 +848,28 @@ #clock-cells = <1>; }; + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x11e40000 0x1000>; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + i2c0: i2c@11f00000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11f00000 0 0x1000>, -- cgit v1.2.3 From e5aac2258e666cdfe7e027766b89af639cd5fb08 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:18 +0800 Subject: arm64: dts: mt8192: Add xhci node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add xhci node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-7-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 946ebcb2bb5f..be82e0766129 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include #include / { @@ -691,6 +692,29 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "host"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + wakeup-source; + mediatek,syscon-wakeup = <&pericfg 0x420 102>; + status = "disabled"; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; -- cgit v1.2.3 From 27f0eb16b0d417c155e96b5d3b89074699944e09 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:22 +0800 Subject: arm64: dts: mt8192: Fix nor_flash status disable typo MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correct nor_flash status disable typo of mt8192 SoC. Fixes: d0a197a0d064a ("arm64: dts: mt8192: add nor_flash device node") Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Miles Chen Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-11-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index be82e0766129..a3721f442138 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -727,7 +727,7 @@ assigned-clock-parents = <&clk26m>; #address-cells = <1>; #size-cells = <0>; - status = "disable"; + status = "disabled"; }; audsys: clock-controller@11210000 { -- cgit v1.2.3 From 4d50a433d0fde2c610628a7b40a0291899861482 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:23 +0800 Subject: arm64: dts: mt8192: Add efuse node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add efuse node for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220318144534.17996-12-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a3721f442138..3d51e1ef7a6f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -736,6 +736,21 @@ #clock-cells = <1>; }; + efuse: efuse@11c10000 { + compatible = "mediatek,efuse"; + reg = <0 0x11c10000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + lvts_e_data1: data1@1c0 { + reg = <0x1c0 0x58>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x68>; + }; + }; + i2c3: i2c@11cb0000 { compatible = "mediatek,mt8192-i2c"; reg = <0 0x11cb0000 0 0x1000>, -- cgit v1.2.3 From 4a65b0f1bec51872b406a8f74a66c0e6e298423c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:26 +0800 Subject: arm64: dts: mt8192: Add m4u and smi nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add m4u and smi nodes for mt8192 SoC Signed-off-by: Allen-KH Cheng Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-15-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++++++++++ 1 file changed, 190 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 3d51e1ef7a6f..579abbf4488e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -967,24 +968,114 @@ #clock-cells = <1>; }; + smi_common: smi@14002000 { + compatible = "mediatek,mt8192-smi-common"; + reg = <0 0x14002000 0 0x1000>; + clocks = <&mmsys CLK_MM_SMI_COMMON>, + <&mmsys CLK_MM_SMI_INFRA>, + <&mmsys CLK_MM_SMI_GALS>, + <&mmsys CLK_MM_SMI_GALS>; + clock-names = "apb", "smi", "gals0", "gals1"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb0: larb@14003000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14003000 0 0x1000>; + mediatek,larb-id = <0>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + larb1: larb@14004000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x14004000 0 0x1000>; + mediatek,larb-id = <1>; + mediatek,smi = <&smi_common>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + }; + + iommu0: m4u@1401d000 { + compatible = "mediatek,mt8192-m4u"; + reg = <0 0x1401d000 0 0x1000>; + mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, + <&larb4>, <&larb5>, <&larb7>, + <&larb9>, <&larb11>, <&larb13>, + <&larb14>, <&larb16>, <&larb17>, + <&larb18>, <&larb19>, <&larb20>; + interrupts = ; + clocks = <&mmsys CLK_MM_SMI_IOMMU>; + clock-names = "bclk"; + power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; + #iommu-cells = <1>; + }; + imgsys: clock-controller@15020000 { compatible = "mediatek,mt8192-imgsys"; reg = <0 0x15020000 0 0x1000>; #clock-cells = <1>; }; + larb9: larb@1502e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1502e000 0 0x1000>; + mediatek,larb-id = <9>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys CLK_IMG_LARB9>, + <&imgsys CLK_IMG_LARB9>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP>; + }; + imgsys2: clock-controller@15820000 { compatible = "mediatek,mt8192-imgsys2"; reg = <0 0x15820000 0 0x1000>; #clock-cells = <1>; }; + larb11: larb@1582e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1582e000 0 0x1000>; + mediatek,larb-id = <11>; + mediatek,smi = <&smi_common>; + clocks = <&imgsys2 CLK_IMG2_LARB11>, + <&imgsys2 CLK_IMG2_LARB11>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>; + }; + + larb5: larb@1600d000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1600d000 0 0x1000>; + mediatek,larb-id = <5>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; + }; + vdecsys_soc: clock-controller@1600f000 { compatible = "mediatek,mt8192-vdecsys_soc"; reg = <0 0x1600f000 0 0x1000>; #clock-cells = <1>; }; + larb4: larb@1602e000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1602e000 0 0x1000>; + mediatek,larb-id = <4>; + mediatek,smi = <&smi_common>; + clocks = <&vdecsys CLK_VDEC_SOC_LARB1>, + <&vdecsys CLK_VDEC_SOC_LARB1>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; + }; + vdecsys: clock-controller@1602f000 { compatible = "mediatek,mt8192-vdecsys"; reg = <0 0x1602f000 0 0x1000>; @@ -997,12 +1088,78 @@ #clock-cells = <1>; }; + larb7: larb@17010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x17010000 0 0x1000>; + mediatek,larb-id = <7>; + mediatek,smi = <&smi_common>; + clocks = <&vencsys CLK_VENC_SET0_LARB>, + <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + larb13: larb@1a001000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a001000 0 0x1000>; + mediatek,larb-id = <13>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB13>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb14: larb@1a002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a002000 0 0x1000>; + mediatek,larb-id = <14>; + mediatek,smi = <&smi_common>; + clocks = <&camsys CLK_CAM_CAM>, + <&camsys CLK_CAM_LARB14>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM>; + }; + + larb16: larb@1a00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a00f000 0 0x1000>; + mediatek,larb-id = <16>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>; + }; + + larb17: larb@1a010000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a010000 0 0x1000>; + mediatek,larb-id = <17>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>; + }; + + larb18: larb@1a011000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1a011000 0 0x1000>; + mediatek,larb-id = <18>; + mediatek,smi = <&smi_common>; + clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>, + <&camsys_rawc CLK_CAM_RAWC_CAM>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>; + }; + camsys_rawa: clock-controller@1a04f000 { compatible = "mediatek,mt8192-camsys_rawa"; reg = <0 0x1a04f000 0 0x1000>; @@ -1027,10 +1184,43 @@ #clock-cells = <1>; }; + larb20: larb@1b00f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b00f000 0 0x1000>; + mediatek,larb-id = <20>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB20>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + + larb19: larb@1b10f000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1b10f000 0 0x1000>; + mediatek,larb-id = <19>; + mediatek,smi = <&smi_common>; + clocks = <&ipesys CLK_IPE_SMI_SUBCOM>, + <&ipesys CLK_IPE_LARB19>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_IPE>; + }; + mdpsys: clock-controller@1f000000 { compatible = "mediatek,mt8192-mdpsys"; reg = <0 0x1f000000 0 0x1000>; #clock-cells = <1>; }; + + larb2: larb@1f002000 { + compatible = "mediatek,mt8192-smi-larb"; + reg = <0 0x1f002000 0 0x1000>; + mediatek,larb-id = <2>; + mediatek,smi = <&smi_common>; + clocks = <&mdpsys CLK_MDP_SMI0>, + <&mdpsys CLK_MDP_SMI0>; + clock-names = "apb", "smi"; + power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; + }; }; }; -- cgit v1.2.3 From b2edd51979d2861e75a9b20ac0e566e9a0770d81 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Fri, 18 Mar 2022 22:45:29 +0800 Subject: arm64: dts: mt8192: Add dpi node Add dpi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220318144534.17996-18-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 579abbf4488e..c6439a010e06 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -999,6 +999,17 @@ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>; }; + dpi0: dpi@14016000 { + compatible = "mediatek,mt8192-dpi"; + reg = <0 0x14016000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI_DPI0>, + <&mmsys CLK_MM_DISP_DPI0>, + <&apmixedsys CLK_APMIXED_TVDPLL>; + clock-names = "pixel", "engine", "pll"; + status = "disabled"; + }; + iommu0: m4u@1401d000 { compatible = "mediatek,mt8192-m4u"; reg = <0 0x1401d000 0 0x1000>; -- cgit v1.2.3 From e530d080932d0db52071c9bec20d60b4a3d9035c Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:13 +0800 Subject: arm64: dts: mt8192: Add PCIe node MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PCIe node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220330133816.30806-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index c6439a010e06..0d32df382f10 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -716,6 +716,41 @@ status = "disabled"; }; + pcie: pcie@11230000 { + compatible = "mediatek,mt8192-pcie"; + device_type = "pci"; + reg = <0 0x11230000 0 0x2000>; + reg-names = "pcie-mac"; + #address-cells = <3>; + #size-cells = <2>; + clocks = <&infracfg CLK_INFRA_PCIE_PL_P_250M>, + <&infracfg CLK_INFRA_PCIE_TL_26M>, + <&infracfg CLK_INFRA_PCIE_TL_96M>, + <&infracfg CLK_INFRA_PCIE_TL_32K>, + <&infracfg CLK_INFRA_PCIE_PERI_26M>, + <&infracfg CLK_INFRA_PCIE_TOP_H_133M>; + clock-names = "pl_250m", "tl_26m", "tl_96m", + "tl_32k", "peri_26m", "top_133m"; + assigned-clocks = <&topckgen CLK_TOP_TL_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D6_D4>; + interrupts = ; + bus-range = <0x00 0xff>; + ranges = <0x82000000 0 0x12000000 0x0 0x12000000 0 0x0800000>, + <0x81000000 0 0x12800000 0x0 0x12800000 0 0x0800000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, + <0 0 0 2 &pcie_intc0 1>, + <0 0 0 3 &pcie_intc0 2>, + <0 0 0 4 &pcie_intc0 3>; + + pcie_intc0: interrupt-controller { + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + nor_flash: spi@11234000 { compatible = "mediatek,mt8192-nor"; reg = <0 0x11234000 0 0xe0>; -- cgit v1.2.3 From aa8f3711fc87f7d9b8edee6f09e44b3f9113f081 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Wed, 30 Mar 2022 21:38:15 +0800 Subject: arm64: dts: mt8192: Add H264 venc device node Adds H264 venc node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220330133816.30806-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 0d32df382f10..a6da7b04b9d4 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1145,6 +1145,29 @@ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; }; + vcodec_enc: vcodec@17020000 { + compatible = "mediatek,mt8192-vcodec-enc"; + reg = <0 0x17020000 0 0x2000>; + iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU>, + <&iommu0 M4U_PORT_L7_VENC_REC>, + <&iommu0 M4U_PORT_L7_VENC_BSDMA>, + <&iommu0 M4U_PORT_L7_VENC_SV_COMV>, + <&iommu0 M4U_PORT_L7_VENC_RD_COMV>, + <&iommu0 M4U_PORT_L7_VENC_CUR_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_REF_CHROMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA>, + <&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA>; + interrupts = ; + mediatek,scp = <&scp>; + power-domains = <&spm MT8192_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC_SET1_VENC>; + clock-names = "venc-set1"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + }; + camsys: clock-controller@1a000000 { compatible = "mediatek,mt8192-camsys"; reg = <0 0x1a000000 0 0x1000>; -- cgit v1.2.3 From f4324583cd4d4979ff2e885a44b8335eb4c4bfa3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:47:40 +0200 Subject: arm64: dts: exynos: move aliases to board in Exynos850 The aliases for typical blocks which are disabled by default in DTSI (like I2C, UART and MMC) should be defined in the board DTS. The board should add aliases only for enabled blocks according to its specific order. On Exynos850, move aliases of enabled blocks to E850-96 board and remove unused ones. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220221075219.10827-1-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 5 +++++ arch/arm64/boot/dts/exynos/exynos850.dtsi | 16 ---------------- 2 files changed, 5 insertions(+), 16 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts index 7b5a61d22cc5..f52a55f644f7 100644 --- a/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts +++ b/arch/arm64/boot/dts/exynos/exynos850-e850-96.dts @@ -20,6 +20,11 @@ model = "WinLink E850-96 board"; compatible = "winlink,e850-96", "samsung,exynos850"; + aliases { + mmc0 = &mmc_0; + serial0 = &serial_0; + }; + chosen { stdout-path = &serial_0; }; diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index d1700e96fee2..1c6d8fdf453c 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -29,22 +29,6 @@ pinctrl3 = &pinctrl_hsi; pinctrl4 = &pinctrl_core; pinctrl5 = &pinctrl_peri; - mmc0 = &mmc_0; - serial0 = &serial_0; - serial1 = &serial_1; - serial2 = &serial_2; - i2c0 = &i2c_0; - i2c1 = &i2c_1; - i2c2 = &i2c_2; - i2c3 = &i2c_3; - i2c4 = &i2c_4; - i2c5 = &i2c_5; - i2c6 = &i2c_6; - i2c7 = &hsi2c_0; - i2c8 = &hsi2c_1; - i2c9 = &hsi2c_2; - i2c10 = &hsi2c_3; - i2c11 = &hsi2c_4; }; arm-pmu { -- cgit v1.2.3 From 2616922241706ec5c2c5ae95d5ac1d3120575ded Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:52:55 +0200 Subject: arm64: dts: exynos: add a specific compatible to MCT One compatible is used for the Multi-Core Timer on most of the Samsung Exynos SoCs, which is correct but not specific enough. These MCT blocks have different number of interrupts, so add a second specific compatible to Exynos5433 and Exynos850. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-4-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++- arch/arm64/boot/dts/exynos/exynos850.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 661567d2dd7a..017ccc2f4650 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -806,7 +806,8 @@ }; timer@101c0000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos5433-mct", + "samsung,exynos4210-mct"; reg = <0x101c0000 0x800>; interrupts = , , diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index 1c6d8fdf453c..9076afd4bb3e 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -165,7 +165,8 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "samsung,exynos850-mct", + "samsung,exynos4210-mct"; reg = <0x10040000 0x800>; interrupts = , , -- cgit v1.2.3 From 22cbcb8f4a17c194d208f686fc3ea37fc860bd71 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Apr 2022 18:53:08 +0200 Subject: arm64: dts: tesla: add a specific compatible to MCT on FSD One compatible is used for the Multi-Core Timer on Tesla FSD SoC, which is correct but not specific enough. The MCT blocks have different number of interrupts, so add a second specific compatible to Tesla FSD. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Alim Akhtar Link: https://lore.kernel.org/r/20220304122424.307885-5-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 9a652abcbcac..10c217a57a7d 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -727,7 +727,7 @@ }; timer@10040000 { - compatible = "samsung,exynos4210-mct"; + compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; reg = <0x0 0x10040000 0x0 0x800>; interrupts = , , -- cgit v1.2.3 From 236b8cfac4e3f007b9c4f014b3d25e63cc376ef7 Mon Sep 17 00:00:00 2001 From: Ariel D'Alessandro Date: Wed, 23 Mar 2022 10:56:01 -0300 Subject: arm64: dts: imx8mn-bsh-smm-s2pro: Add tlv320aic31xx audio card node BSH SystemMaster (SMM) S2 PRO board comes with an audio card based on tlv320aic31xx family codec. The audio card exposes two playback devices, one of them using the EASRC (Enhanced Asynchronous Sample Rate Converter) module. Note that this would require SDMA and EASRC firmware in order to work. Signed-off-by: Ariel D'Alessandro Signed-off-by: Michael Trimarchi Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts | 90 ++++++++++++++++++++++ 1 file changed, 90 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts index c6a8ed6745c1..fbbb3367037b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2pro.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn-bsh-smm-s2-common.dtsi" +#include / { model = "BSH SMM S2 PRO"; @@ -16,6 +17,65 @@ device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; + + sound-tlv320aic31xx { + compatible = "fsl,imx-audio-tlv320aic31xx"; + model = "tlv320aic31xx-hifi"; + audio-cpu = <&sai3>; + audio-codec = <&tlv320dac3101>; + audio-asrc = <&easrc>; + audio-routing = + "Ext Spk", "SPL", + "Ext Spk", "SPR"; + mclk-id = ; + }; + + vdd_input: vdd_input { + compatible = "regulator-fixed"; + regulator-name = "vdd_input"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&easrc { + fsl,asrc-rate = <48000>; + fsl,asrc-format = <10>; + status = "okay"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320dac3101: audio-codec@18 { + compatible = "ti,tlv320dac3101"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dac_rst>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <&buck4_reg>; + SPRVDD-supply = <&vdd_input>; + SPLVDD-supply = <&vdd_input>; + AVDD-supply = <&buck4_reg>; + IOVDD-supply = <&buck4_reg>; + DVDD-supply = <&buck5_reg>; + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + ai31xx-micbias-vg = ; + clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; + }; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clk IMX8MN_CLK_SAI3>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <24576000>; + fsl,sai-mclk-direction-output; + status = "okay"; }; /* eMMC */ @@ -30,6 +90,36 @@ }; &iomuxc { + pinctrl_dac_rst: dacrstgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 /* DAC_RST */ + >; + }; + + pinctrl_espi2: espi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082 + MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400000c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400000c3 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6 + MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6 + MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090 -- cgit v1.2.3 From 583f24ae42a0786dbb70fde03a3652059811a9c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 21 Feb 2022 01:17:38 +0100 Subject: arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC Add support for Data Modul i.MX8M Mini eDM SBC board. This is an evaluation board for various custom display units. Currently supported are serial console, ethernet, eMMC, SD, PCIe, SPI NOR, USB host and USB OTG. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Reviewed-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mm-data-modul-edm-sbc.dts | 996 +++++++++++++++++++++ 2 files changed, 997 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 7f51b537df40..52ce0f798657 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-emcon-avari.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts new file mode 100644 index 000000000000..154116d01c94 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -0,0 +1,996 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Marek Vasut + */ + +/dts-v1/; + +#include +#include +#include "imx8mm.dtsi" + +/ { + model = "Data Modul i.MX8M Mini eDM SBC"; + compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm"; + + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = &uart3; + }; + + memory@40000000 { + device_type = "memory"; + /* There are 1/2/4 GiB options, adjusted by bootloader. */ + reg = <0x0 0x40000000 0 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_backlight>; + brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; + default-brightness-level = <7>; + enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + pwms = <&pwm1 0 5000000>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + clk_xtal25: clk-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + panel: panel { + backlight = <&backlight>; + power-supply = <®_panel_vcc>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_vcc_reg>; + regulator-name = "PANEL_VCC"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 6 0>; + enable-active-high; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; + }; + + reg_usdhc2_vcc: regulator-usdhc2-vcc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 0>; + enable-active-high; + }; + + watchdog-gpio { + /* TPS3813 */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_watchdog_gpio>; + compatible = "linux,wdt-gpio"; + always-enabled; + gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; + hw_algo = "level"; + /* Reset triggers in 2..3 seconds */ + hw_margin_ms = <1500>; + /* Disabled by default */ + status = "disabled"; + }; +}; + +&A53_0 { + cpu-supply = <&buck2_reg>; +}; + +&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-25M { + opp-hz = /bits/ 64 <25000000>; + }; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { /* W25Q128FVSI */ + compatible = "jedec,spi-nor"; + m25p,fast-read; + spi-max-frequency = <50000000>; + reg = <0>; + }; +}; + +&ecspi2 { /* Feature connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless feature board plugged in. */ + status = "disabled"; +}; + +&ecspi3 { /* Display connector SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <&fec1_phy>; + phy-supply = <&buck4_reg>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + /* Atheros AR8031 PHY */ + fec1_phy: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + /* + * Dedicated ENET_WOL# signal is unused, the PHY + * can wake the SoC up via INT signal as well. + */ + interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "ENET_RST#", "WDOG_B#", "PMIC_INT#", + "", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#", + "WDOG_KICK#", "M2-B_PCIE_CLKREQ#", + "USB1_OTG_ID_3V3", "ENET_WOL#", + "", "", "", "ENET_INT#", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#", + "M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#", + "PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#", + "MEMCFG0", "WDOG_EN", + "M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#", + "", "", "", "", + "", "", "", "SD2_RESET#", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "", + "", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8", + "CSI_PD_1V8", "CSI_RESET_1V8#", "", "", + "", "", "", "", + "", "", "", "M2-B_WAKE_WWAN_1V8#", + "M2-B_RESET_1V8#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "NC0", "NC1", "BOOTCFG0", "BOOTCFG1", + "BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5", + "BOOTCFG6", "BOOTCFG7", "NC10", "NC11", + "BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11", + "BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15", + "NC20", "", "", "", + "", "CAN_INT#", "CAN_RST#", "GPIO4_IO27", + "DIS_USB_DN2", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03", + "GPIO5_IO04", "", "", "", + "", "SPI1_CS#", "", "", + "", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3", + "I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3", + "I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "", + "", "SPI3_CS#", "", "", "", "", "", ""; +}; + +&i2c1 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <100000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic: pmic@4b { + compatible = "rohm,bd71847"; + reg = <0x4b>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + rohm,reset-snvs-powered; + + /* + * i.MX 8M Mini Data Sheet for Consumer Products + * 3.1.3 Operating ranges + * MIMX8MM4DVTLZAA + */ + regulators { + /* VDD_SOC */ + buck1_reg: BUCK1 { + regulator-name = "buck1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + }; + + /* VDD_ARM */ + buck2_reg: BUCK2 { + regulator-name = "buck2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1250>; + rohm,dvs-run-voltage = <1000000>; + rohm,dvs-idle-voltage = <950000>; + }; + + /* VDD_DRAM, BUCK5 */ + buck3_reg: BUCK3 { + regulator-name = "buck3"; + /* 1.5 GHz DDR bus clock */ + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 3V3_VDD, BUCK6 */ + buck4_reg: BUCK4 { + regulator-name = "buck4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDD, BUCK7 */ + buck5_reg: BUCK5 { + regulator-name = "buck5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V1_NVCC_DRAM, BUCK8 */ + buck6_reg: BUCK6 { + regulator-name = "buck6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_NVCC_SNVS */ + ldo1_reg: LDO1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V8_VDD_SNVS */ + ldo2_reg: LDO2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V8_VDDA */ + ldo3_reg: LDO3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 0V9_VDD_PHY */ + ldo4_reg: LDO4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + /* 1V2_VDD_PHY */ + ldo6_reg: LDO6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c2 { + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + usb-hub@2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_hub>; + compatible = "microchip,usb2514bi"; + reg = <0x2c>; + individual-port-switching; + reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + self-powered; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc: rtc@68 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + compatible = "st,m41t62"; + reg = <0x68>; + interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>; + }; + + pcieclk: clk@6a { + compatible = "renesas,9fgv0241"; + reg = <0x6a>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; +}; + +&i2c3 { /* Display connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { /* Feature connector I2C */ + /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ + clock-frequency = <320000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>, + <&pinctrl_hog_panel>, <&pinctrl_hog_sbc>, + <&pinctrl_panel_expansion>; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40 + >; + }; + + pinctrl_ecspi2: ecspi2-grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44 + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 + >; + }; + + pinctrl_ecspi3: ecspi3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40 + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + /* ENET_RST# */ + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6 + /* ENET_WOL# */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090 + /* ENET_INT# */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090 + >; + }; + + pinctrl_hog_feature: hog-feature-grp { + fsl,pins = < + /* GPIO4_IO27 */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006 + /* GPIO5_IO03 */ + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006 + /* GPIO5_IO04 */ + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006 + + /* CAN_INT# */ + MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090 + /* CAN_RST# */ + MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26 + >; + }; + + pinctrl_hog_panel: hog-panel-grp { + fsl,pins = < + /* GRAPHICS_GPIO0_1V8 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26 + >; + }; + + pinctrl_hog_misc: hog-misc-grp { + fsl,pins = < + /* PG_V_IN_VAR# */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000 + /* CSI_PD_1V8 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0 + /* CSI_RESET_1V8# */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0 + + /* DIS_USB_DN1 */ + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0 + /* DIS_USB_DN2 */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0 + + /* EEPROM_WP_1V8# */ + MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100 + /* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0 + /* GRAPHICS_PRSNT_1V8# */ + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000 + + /* CLK_CCM_CLKO1_3V3 */ + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10 + >; + }; + + pinctrl_hog_sbc: hog-sbc-grp { + fsl,pins = < + /* MEMCFG[0..2] straps */ + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140 + MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140 + MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140 + + /* BOOT_CFG[0..15] straps */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000 + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000 + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000 + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000 + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000 + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000 + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000 + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000 + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000 + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000 + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000 + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000 + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000 + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000 + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000 + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000 + + /* Not connected pins */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0 + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0 + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0 + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84 + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84 + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84 + >; + }; + + pinctrl_i2c3: i2c3-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084 + >; + }; + + pinctrl_i2c3_gpio: i2c3-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84 + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84 + >; + }; + + pinctrl_i2c4: i2c4-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084 + >; + }; + + pinctrl_i2c4_gpio: i2c4-gpio-grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84 + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84 + >; + }; + + pinctrl_panel_backlight: panel-backlight-grp { + fsl,pins = < + /* BL_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104 + >; + }; + + pinctrl_panel_expansion: panel-expansion-grp { + fsl,pins = < + /* DSI_RESET_1V8# */ + MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2 + /* DSI_IRQ_1V8# */ + MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090 + >; + }; + + pinctrl_panel_vcc_reg: panel-vcc-grp { + fsl,pins = < + /* TFT_ENABLE_1V8 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104 + >; + }; + + pinctrl_panel_pwm: panel-pwm-grp { + fsl,pins = < + /* BL_PWM_3V3 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12 + >; + }; + + pinctrl_pcie0: pcie-grp { + fsl,pins = < + /* M2-B_RESET_1V8# */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102 + /* M2-B_PCIE_RST# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2 + /* M2-B_FULL_CARD_PWROFF_1V8# */ + MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102 + /* M2-B_W_DISABLE1_WWAN_1V8# */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102 + /* M2-B_W_DISABLE2_GPS_1V8# */ + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102 + /* CLK_M2_32K768 */ + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14 + /* M2-B_WAKE_WWAN_1V8# */ + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140 + /* M2-B_PCIE_WAKE# */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140 + /* M2-B_PCIE_CLKREQ# */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140 + >; + }; + + pinctrl_pmic: pmic-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090 + >; + }; + + pinctrl_rtc: rtc-grp { + fsl,pins = < + /* RTC_IRQ# */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090 + >; + }; + + pinctrl_sai5: sai5-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0 + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100 + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100 + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50 + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50 + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90 + >; + }; + + pinctrl_uart3: uart3-grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40 + >; + }; + + pinctrl_uart4: uart4-grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40 + >; + }; + + pinctrl_usb_hub: usb-hub-grp { + fsl,pins = < + /* USBHUB_RESET# */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4 + >; + }; + + pinctrl_usb_otg1: usb-otg1-grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000 + MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4 + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090 + >; + }; + + pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6 + MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40 + >; + }; + + pinctrl_watchdog_gpio: watchdog-gpio-grp { + fsl,pins = < + /* WDOG_B# */ + MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26 + /* WDOG_EN -- ungate WDT RESET# signal propagation */ + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6 + /* WDOG_KICK# / WDI */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26 + >; + }; +}; + +&pcie_phy { + fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */ + fsl,refclk-pad-mode = ; + fsl,tx-deemph-gen1 = <0x2d>; + fsl,tx-deemph-gen2 = <0xf>; + clocks = <&pcieclk 0>; + status = "okay"; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, + <&pcieclk 0>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-rates = <10000000>, <250000000>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_250M>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel_pwm>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + fsl,sai-mclk-direction-output; + /* Input into codec PLL */ + assigned-clocks = <&clk IMX8MM_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>; + assigned-clock-rates = <22579200>; + /* Disabled by default, unless display board plugged in. */ + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "disabled"; +}; + +&uart3 { /* A53 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { /* M4 Debug */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + /* UART4 is reserved for CM and RDC blocks CA access to UART4. */ + status = "disabled"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1>; + dr_mode = "otg"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { /* MicroSD */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <4>; + vmmc-supply = <®_usdhc2_vcc>; + status = "okay"; +}; + +&usdhc3 { /* eMMC */ + assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + vmmc-supply = <&buck4_reg>; + vqmmc-supply = <&buck5_reg>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; -- cgit v1.2.3 From 1c6add99c2bf1b19175e80826534b025c967afdd Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Wed, 16 Feb 2022 08:49:27 +0100 Subject: arm64: dts: imx8mm-kontron: fix ethernet node name The node name of Ethernet controller should be "ethernet" instead of "usbether" as required by Ethernet controller devicetree schema: Documentation/devicetree/bindings/net/ethernet-controller.yaml This patch can potentially affect boot loaders patching against full node path instead of using device aliases. Signed-off-by: Oleksij Rempel Acked-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index d40caf14ac4a..23be1ec538ba 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -182,7 +182,7 @@ #address-cells = <1>; #size-cells = <0>; - usbnet: usbether@1 { + usbnet: ethernet@1 { compatible = "usb424,ec00"; reg = <1>; local-mac-address = [ 00 00 00 00 00 00 ]; -- cgit v1.2.3 From 1cfa1e68af8d40ab233d5d27bc8446e4c5107571 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:29 +0100 Subject: arm64: dts: imx8mn-evk: use proper names for PMIC outputs Use the power signal names as given in the schematics of the reference board. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index b4225cfcb6d9..2b685c0c7eeb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -41,7 +41,7 @@ regulators { buck1: BUCK1{ - regulator-name = "BUCK1"; + regulator-name = "VDD_SOC"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -50,7 +50,7 @@ }; buck2: BUCK2 { - regulator-name = "BUCK2"; + regulator-name = "VDD_ARM_0V9"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <2187500>; regulator-boot-on; @@ -61,7 +61,7 @@ }; buck4: BUCK4{ - regulator-name = "BUCK4"; + regulator-name = "VDD_3V3"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -69,7 +69,7 @@ }; buck5: BUCK5{ - regulator-name = "BUCK5"; + regulator-name = "VDD_1V8"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -77,7 +77,7 @@ }; buck6: BUCK6 { - regulator-name = "BUCK6"; + regulator-name = "NVCC_DRAM_1V1"; regulator-min-microvolt = <600000>; regulator-max-microvolt = <3400000>; regulator-boot-on; @@ -85,7 +85,7 @@ }; ldo1: LDO1 { - regulator-name = "LDO1"; + regulator-name = "NVCC_SNVS_1V8"; regulator-min-microvolt = <1600000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -93,7 +93,7 @@ }; ldo2: LDO2 { - regulator-name = "LDO2"; + regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <1150000>; regulator-boot-on; @@ -101,7 +101,7 @@ }; ldo3: LDO3 { - regulator-name = "LDO3"; + regulator-name = "VDDA_1V8"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -109,7 +109,7 @@ }; ldo4: LDO4 { - regulator-name = "LDO4"; + regulator-name = "VDD_PHY_1V2"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -117,7 +117,7 @@ }; ldo5: LDO5 { - regulator-name = "LDO5"; + regulator-name = "NVCC_SD2"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; -- cgit v1.2.3 From bc046b952a5494b0dc53be28779460cee1214a3f Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 24 Feb 2022 11:30:30 +0100 Subject: arm64: dts: imx8mn-evk: fix the min/max voltages of the PMIC Use the proper voltages as supported by the board instead of the ones supported by the PMIC. The voltages were taken from both the schematic of the 8MNANOLPD4-EVK eval board and the datasheet of the IMX8MN SoC. Signed-off-by: Michael Walle Reviewed-by: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 34 ++++++++++++++-------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts index 2b685c0c7eeb..4eb467df5ba7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts @@ -42,8 +42,8 @@ regulators { buck1: BUCK1{ regulator-name = "VDD_SOC"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -51,8 +51,8 @@ buck2: BUCK2 { regulator-name = "VDD_ARM_0V9"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <2187500>; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; regulator-boot-on; regulator-always-on; regulator-ramp-delay = <3125>; @@ -62,32 +62,32 @@ buck4: BUCK4{ regulator-name = "VDD_3V3"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-boot-on; regulator-always-on; }; buck5: BUCK5{ regulator-name = "VDD_1V8"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; buck6: BUCK6 { regulator-name = "NVCC_DRAM_1V1"; - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <3400000>; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; regulator-boot-on; regulator-always-on; }; ldo1: LDO1 { regulator-name = "NVCC_SNVS_1V8"; - regulator-min-microvolt = <1600000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -95,23 +95,23 @@ ldo2: LDO2 { regulator-name = "VDD_SNVS_0V8"; regulator-min-microvolt = <800000>; - regulator-max-microvolt = <1150000>; + regulator-max-microvolt = <800000>; regulator-boot-on; regulator-always-on; }; ldo3: LDO3 { regulator-name = "VDDA_1V8"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; ldo4: LDO4 { regulator-name = "VDD_PHY_1V2"; - regulator-min-microvolt = <800000>; - regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; regulator-boot-on; regulator-always-on; }; -- cgit v1.2.3 From 7ac853ba789d1d9fb22b05f4ebd3a37fd1bb11c1 Mon Sep 17 00:00:00 2001 From: Aniruddha Rao Date: Wed, 16 Mar 2022 15:14:45 +0530 Subject: arm64: tegra: Update SDMMC1/3 clock source for Tegra194 The default parent for SDMMC1/3 clock sources can provide maximum frequency of 136MHz for SDR104 mode. Update parent clock source for SDMMC1/SDMMC3 instances to increase the output clock frequency to 195MHz and improve the perf. Signed-off-by: Aniruddha Rao Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 751ebe5e9506..1d6be5774fac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -934,6 +934,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC1>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC1>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC1>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCRA &emc>, @@ -968,6 +973,11 @@ clocks = <&bpmp TEGRA194_CLK_SDMMC3>, <&bpmp TEGRA194_CLK_SDMMC_LEGACY_TM>; clock-names = "sdhci", "tmclk"; + assigned-clocks = <&bpmp TEGRA194_CLK_SDMMC3>, + <&bpmp TEGRA194_CLK_PLLC4_MUXED>; + assigned-clock-parents = + <&bpmp TEGRA194_CLK_PLLC4_MUXED>, + <&bpmp TEGRA194_CLK_PLLC4_VCO_DIV2>; resets = <&bpmp TEGRA194_RESET_SDMMC3>; reset-names = "sdhci"; interconnects = <&mc TEGRA194_MEMORY_CLIENT_SDMMCR &emc>, -- cgit v1.2.3 From 5472b7df7c795352f73e9dfa68c6e5eb5db7fac8 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 25 Feb 2022 17:00:01 +0800 Subject: arm64: dts: imx8mq: add hdmi phy 27m clock The i.MX8MQ PLL support hdmi phy 27m as pll reference clock, so add a fixed clock for it. Signed-off-by: Peng Fan Reviewed-by: Abel Vesa Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 5b3e849f554d..1eca2b431467 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -63,6 +63,13 @@ clock-output-names = "osc_27m"; }; + hdmi_phy_27m: clock-hdmi-phy-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "hdmi_phy_27m"; + }; + clk_ext1: clock-ext1 { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3 From 71f69ffa0129bf04205edf0e7dc73dc4777b2588 Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Wed, 9 Mar 2022 00:00:26 +0530 Subject: arm64: tegra: Add QSPI controllers on Tegra234 This adds the QSPI controllers on the Tegra234 SoC and populates the SPI NOR flash device for the Jetson AGX Orin platform. Signed-off-by: Ashish Singhal Signed-off-by: Jon Hunter Signed-off-by: Krishna Yarlagadda Reviewed-by: Jon Hunter Acked-by: Rob Herring Signed-off-by: Thierry Reding --- .../arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi | 12 ++++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 28 ++++++++++++++++++++++ include/dt-bindings/clock/tegra234-clock.h | 8 +++++++ include/dt-bindings/reset/tegra234-reset.h | 2 ++ 4 files changed, 50 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi index d95a542c0bca..798de9226ba5 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3701-0000.dtsi @@ -7,6 +7,18 @@ compatible = "nvidia,p3701-0000", "nvidia,tegra234"; bus@0 { + spi@3270000 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <102000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + mmc@3460000 { status = "okay"; bus-width = <8>; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index aaace605bdaa..448512af7dea 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -654,6 +654,20 @@ reset-names = "i2c"; }; + spi@3270000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3270000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI0>; + reset-names = "qspi"; + status = "disabled"; + }; + pwm1: pwm@3280000 { compatible = "nvidia,tegra194-pwm", "nvidia,tegra186-pwm"; @@ -666,6 +680,20 @@ #pwm-cells = <2>; }; + spi@3300000 { + compatible = "nvidia,tegra234-qspi"; + reg = <0x3300000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + clock-names = "qspi", "qspi_out"; + resets = <&bpmp TEGRA234_RESET_QSPI1>; + reset-names = "qspi"; + status = "disabled"; + }; + mmc@3460000 { compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci"; reg = <0x03460000 0x20000>; diff --git a/include/dt-bindings/clock/tegra234-clock.h b/include/dt-bindings/clock/tegra234-clock.h index 8cae969e8cba..bd4c3086a2da 100644 --- a/include/dt-bindings/clock/tegra234-clock.h +++ b/include/dt-bindings/clock/tegra234-clock.h @@ -140,6 +140,14 @@ #define TEGRA234_CLK_PEX2_C9_CORE 173U /** @brief output of gate CLK_ENB_PEX2_CORE_10 */ #define TEGRA234_CLK_PEX2_C10_CORE 187U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 switch divider output */ +#define TEGRA234_CLK_QSPI0_2X_PM 192U +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 switch divider output */ +#define TEGRA234_CLK_QSPI1_2X_PM 193U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI0 */ +#define TEGRA234_CLK_QSPI0_PM 194U +/** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI1 */ +#define TEGRA234_CLK_QSPI1_PM 195U /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */ #define TEGRA234_CLK_SDMMC_LEGACY_TM 219U /** @brief output of gate CLK_ENB_PEX0_CORE_0 */ diff --git a/include/dt-bindings/reset/tegra234-reset.h b/include/dt-bindings/reset/tegra234-reset.h index 1362cd5e03f0..547ca3b60caa 100644 --- a/include/dt-bindings/reset/tegra234-reset.h +++ b/include/dt-bindings/reset/tegra234-reset.h @@ -40,6 +40,8 @@ #define TEGRA234_RESET_PWM6 73U #define TEGRA234_RESET_PWM7 74U #define TEGRA234_RESET_PWM8 75U +#define TEGRA234_RESET_QSPI0 76U +#define TEGRA234_RESET_QSPI1 77U #define TEGRA234_RESET_SDMMC4 85U #define TEGRA234_RESET_UARTA 100U #define TEGRA234_RESET_PEX0_CORE_0 116U -- cgit v1.2.3 From ad2c6e3cdd6121bdabf0726355dbe04b987c92e0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:11 +0200 Subject: arm64: dts: broadcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Florian Fainelli --- arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts | 2 +- arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts | 2 +- arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index 12a4b1c03390..e34172e3117e 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -203,7 +203,7 @@ &qspi { bspi-sel = <0>; - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts index f00c21e0767e..7bf26f3e36bf 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-xmc.dts @@ -146,7 +146,7 @@ }; &qspi { - flash: m25p80@0 { + flash: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p80"; diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts index 77efa28c4dd5..dfac910a45d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts +++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts @@ -61,7 +61,7 @@ cs-gpios = <&gpio_hsls 34 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; @@ -76,7 +76,7 @@ cs-gpios = <&gpio_hsls 96 0>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <20000000>; -- cgit v1.2.3 From 8771ce5eadb5b73daab190c2451172e43e16ae41 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:21:59 +0200 Subject: arm64: dts: meson: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220407142159.293836-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 2 +- arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 2 +- arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi index 2d7032f41e4b..bcdf55f48a83 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx-libretech-pc.dtsi @@ -416,7 +416,7 @@ pinctrl-names = "default"; status = "okay"; - gd25lq128: spi-flash@0 { + gd25lq128: flash@0 { compatible = "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts index 2d769203f671..213a0705ebdc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s805x-libretech-ac.dts @@ -298,7 +298,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts index 93d8f8aff70d..874f91c348ec 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc-v2.dts @@ -284,7 +284,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - nor_4u1: spi-flash@0 { + nor_4u1: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts index 86bdc0baf032..f43c45daf7eb 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts @@ -374,7 +374,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q32: spi-flash@0 { + w25q32: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q16", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi index 3cf4ecb6d52e..c9705941e4ab 100644 --- a/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi @@ -458,7 +458,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - w25q128: spi-flash@0 { + w25q128: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "winbond,w25q128fw", "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts index f3f953225bf5..e3486f60645a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-odroid-hc4.dts @@ -121,7 +121,7 @@ pinctrl-0 = <&nor_pins>; pinctrl-names = "default"; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; -- cgit v1.2.3 From a3b2fc4f76de7d307a5ed865b88fb35c69ebd172 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 28 Feb 2022 14:12:18 +0100 Subject: arm64: dts: imx8mq-librem5: make the volume buttons a wakeup source They turn on the display currently so to be consistent, let's make them wake the system from suspend as well. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 05c16376b4d8..0d391468bf21 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -42,6 +42,7 @@ gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; }; vol-up { @@ -49,6 +50,7 @@ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <50>; + wakeup-source; }; }; -- cgit v1.2.3 From b019694c8be088bef1011fb21ea6fc4180727c6e Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Mon, 28 Feb 2022 14:12:19 +0100 Subject: arm64: dts: imx8mq-librem5: remove description of CHG_STATUS_B That pin is not connected on the board so no need to describe it. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0d391468bf21..b7d9edc1358b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -389,8 +389,6 @@ fsl,pins = < /* CHRG_INT */ MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x80 - /* CHG_STATUS_B */ - MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x80 >; }; -- cgit v1.2.3 From 2bf475ce12e6a67b971045f3ed53494bbcbf0b65 Mon Sep 17 00:00:00 2001 From: Guido Günther Date: Mon, 28 Feb 2022 14:12:20 +0100 Subject: arm64: dts: imx8mq-librem5: higher boost regulation current MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 1,5A is what's used by the type-c controller on the Librem 5 board so increase ti,boost-max-current to 1,5A too. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index b7d9edc1358b..a0c8191bd33c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1098,7 +1098,7 @@ ti,precharge-current = <130000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ - ti,boost-max-current = <500000>; /* uA */ + ti,boost-max-current = <1500000>; /* uA */ ti,use-vinmin-threshold = <1>; /* enable VINDPM */ ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; -- cgit v1.2.3 From c3e9d4547a9e15b56c2ceefa54ec04057b3276eb Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Mon, 28 Feb 2022 14:12:21 +0100 Subject: arm64: dts: imx8mq-librem5: add a RO firmware partition This partition will hold a squashfs firmware jail. Only one read-only partition is needed. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index a0c8191bd33c..587e55aaa57b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -325,15 +325,10 @@ }; partition@30000 { - label = "protected1"; - reg = <0x30000 0x10000>; + label = "firmware"; + reg = <0x30000 0x1d0000>; read-only; }; - - partition@40000 { - label = "rw"; - reg = <0x40000 0x1C0000>; - }; }; }; -- cgit v1.2.3 From 9694ed9bcf3b761c05d7787739eb4e77bd86c367 Mon Sep 17 00:00:00 2001 From: Guido Günther Date: Mon, 28 Feb 2022 14:12:22 +0100 Subject: arm64: dts: imx8mq-librem5-r4: add the correct panel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The r4 ("Evergreen") hardware revision of the Librem 5 phone includes a slightly different panel than the revisions before it. Since its' description is available, describe it properly for the board. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts index 30d65bef6939..1056b7981bdb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-r4.dts @@ -18,6 +18,10 @@ led-max-microamp = <25000>; }; +&lcd_panel { + compatible = "ys,ys57pss36bh5gq"; +}; + &proximity { proximity-near-level = <10>; }; -- cgit v1.2.3 From 579df4288896f22c5e8c38aee771edc5f25bf461 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 28 Feb 2022 14:25:23 +0100 Subject: arm64: dts: imx8mn-evk: add QSPI flash There is a 32MiB Micron MT25QU256ABA1 serial NOR flash on the EVK board. Add a device tree node for it. Tested on a 8MNANOD3L-EVK. Signed-off-by: Michael Walle Tested-by: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index c3f15192b76c..dc75d6d13bb3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -110,6 +110,22 @@ }; }; +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <166000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -267,6 +283,17 @@ >; }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + }; + pinctrl_gpio_led: gpioledgrp { fsl,pins = < MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 -- cgit v1.2.3 From fc0f051246212675de77c352ce955a5738e1419d Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Mar 2022 12:46:19 +0200 Subject: arm64: dts: imx8mp: add GPC node with GPU power domains Add the power domains for the GPUs, which do not require any interaction with a blk-ctrl, but are simply two PU domains nested inside a MIX domain. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 41 +++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 794d75173cf5..c6bfaacaeb7f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -475,6 +476,46 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mp-gpc"; + reg = <0x303a0000 0x1000>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_gpu2d: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; + power-domains = <&pgc_gpumix>; + }; + + pgc_gpumix: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, + <&clk IMX8MP_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu3d: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + power-domains = <&pgc_gpumix>; + }; + }; + }; }; aips2: bus@30400000 { -- cgit v1.2.3 From 4bdb11926e486757ae01312228df60d7a215b3e5 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 30 Mar 2022 12:46:20 +0200 Subject: arm64: dts: imx8mp: add GPU nodes Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP. etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0 Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Tested-by: Alexander Stein Tested-by: Peng Fan Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c6bfaacaeb7f..afd36374dccb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -933,6 +933,37 @@ }; }; + gpu3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "shader", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, + <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <800000000>; + power-domains = <&pgc_gpu3d>; + }; + + gpu2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, + <&clk IMX8MP_CLK_GPU_ROOT>, + <&clk IMX8MP_CLK_GPU_AHB>; + clock-names = "core", "bus", "reg"; + assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>; + power-domains = <&pgc_gpu2d>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, -- cgit v1.2.3 From 1ceaccf2b267165fcff39e374f8596dfccd2321b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 22:41:15 +0200 Subject: arm64: dts: synaptics: remove unused DTSI for AS370 The as370.dtsi for Synaptics AS370 SoC does not have a user (DTS board file), is uncompilable and untestable. It was added back in 2018. No user appeared since that time, so assume it won't be added. Signed-off-by: Krzysztof Kozlowski Acked-by: Rob Herring Signed-off-by: Arnd Bergmann --- Documentation/devicetree/bindings/arm/syna.txt | 4 - arch/arm64/boot/dts/synaptics/as370.dtsi | 173 ------------------------- 2 files changed, 177 deletions(-) delete mode 100644 arch/arm64/boot/dts/synaptics/as370.dtsi (limited to 'arch/arm64') diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt index d8b48f2edf1b..851f48ead927 100644 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ b/Documentation/devicetree/bindings/arm/syna.txt @@ -18,10 +18,6 @@ stable binding/ABI. --------------------------------------------------------------- -Boards with the Synaptics AS370 SoC shall have the following properties: - Required root node property: - compatible: "syna,as370" - Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 shall have the following properties: diff --git a/arch/arm64/boot/dts/synaptics/as370.dtsi b/arch/arm64/boot/dts/synaptics/as370.dtsi deleted file mode 100644 index 4bb5d650df9c..000000000000 --- a/arch/arm64/boot/dts/synaptics/as370.dtsi +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* - * Copyright (C) 2018 Synaptics Incorporated - * - * Author: Jisheng Zhang - */ - -#include - -/ { - compatible = "syna,as370"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - - psci { - compatible = "arm,psci-1.0"; - method = "smc"; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@0 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x0>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu1: cpu@1 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x1>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu2: cpu@2 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x2>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - cpu3: cpu@3 { - compatible = "arm,cortex-a53"; - device_type = "cpu"; - reg = <0x3>; - enable-method = "psci"; - next-level-cache = <&l2>; - cpu-idle-states = <&CPU_SLEEP_0>; - }; - - l2: cache { - compatible = "cache"; - }; - - idle-states { - entry-method = "psci"; - CPU_SLEEP_0: cpu-sleep-0 { - compatible = "arm,idle-state"; - local-timer-stop; - arm,psci-suspend-param = <0x0010000>; - entry-latency-us = <75>; - exit-latency-us = <155>; - min-residency-us = <1000>; - }; - }; - }; - - osc: osc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - }; - - pmu { - compatible = "arm,cortex-a53-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, - <&cpu1>, - <&cpu2>, - <&cpu3>; - }; - - timer { - compatible = "arm,armv8-timer"; - interrupts = , - , - , - ; - }; - - soc@f7000000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0 0xf7000000 0x1000000>; - - gic: interrupt-controller@901000 { - compatible = "arm,gic-400"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x901000 0x1000>, - <0x902000 0x2000>, - <0x904000 0x2000>, - <0x906000 0x2000>; - interrupts = ; - }; - - apb@e80000 { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0xe80000 0x10000>; - - uart0: serial@c00 { - compatible = "snps,dw-apb-uart"; - reg = <0xc00 0x100>; - interrupts = ; - clocks = <&osc>; - reg-shift = <2>; - status = "disabled"; - }; - - gpio0: gpio@1800 { - compatible = "snps,dw-apb-gpio"; - reg = <0x1800 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - porta: gpio-port@0 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - - gpio1: gpio@2000 { - compatible = "snps,dw-apb-gpio"; - reg = <0x2000 0x400>; - #address-cells = <1>; - #size-cells = <0>; - - portb: gpio-port@1 { - compatible = "snps,dw-apb-gpio-port"; - gpio-controller; - #gpio-cells = <2>; - ngpios = <32>; - reg = <0>; - interrupt-controller; - #interrupt-cells = <2>; - interrupts = ; - }; - }; - }; - }; -}; -- cgit v1.2.3 From 397ad94668c14b558d8dcf2bf29bce4bf78222ba Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Feb 2022 00:10:27 +0530 Subject: arm64: dts: qcom: sm8150: Add pdc interrupt controller node Add pdc interrupt controller for sm8150. Cc: Maulik Shah Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226184028.111566-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 15f3bf2e7ea0..a57b898ce5be 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3381,6 +3381,16 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8150-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x400>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8150-aoss-qmp"; reg = <0x0 0x0c300000 0x0 0x400>; -- cgit v1.2.3 From fe75b0c4a6911243fe239fd0c2b2bda4fd398f6e Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Thu, 24 Mar 2022 02:00:52 +0530 Subject: arm64: dts: qcom: sm8150: Add ufs power-domain entries Add power-domain entries for UFS phy node in sm8150 dts. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma [bjorn: Dropped power-domain-names] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323203052.1124683-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index a57b898ce5be..f4f639f3dc47 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1807,6 +1807,8 @@ clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + power-domains = <&gcc UFS_PHY_GDSC>; + resets = <&ufs_mem_hc 0>; reset-names = "ufsphy"; status = "disabled"; -- cgit v1.2.3 From a1c86c6805336503ad2460426736456cc324d4a3 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 26 Mar 2022 11:27:53 +0530 Subject: arm64: dts: qcom: sm8150: Add PCIe nodes Add nodes for the two PCIe controllers found on the SM8150 SoC. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220326055754.1796146-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f4f639f3dc47..13547c15f321 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1746,6 +1746,203 @@ interrupts = ; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + iommus = <&apps_smmu 0x1d80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>, + <0x100 &apps_smmu 0x1d81 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: phy@1c06200 { + reg = <0 0x1c06200 0 0x170>, /* tx */ + <0 0x1c06400 0 0x200>, /* rx */ + <0 0x1c06800 0 0x1f0>, /* pcs */ + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8150", "snps,dw-pcie"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; + clock-names = "pipe", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "tbu"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + iommus = <&apps_smmu 0x1e00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>, + <0x100 &apps_smmu 0x1e01 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>; + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x1c0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + clock-names = "aux", "cfg_ahb", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: phy@1c0e200 { + reg = <0 0x1c0e200 0 0x170>, /* tx0 */ + <0 0x1c0e400 0 0x200>, /* rx0 */ + <0 0x1c0ea00 0 0x1f0>, /* pcs */ + <0 0x1c0e600 0 0x170>, /* tx1 */ + <0 0x1c0e800 0 0x200>, /* rx1 */ + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; @@ -2450,6 +2647,52 @@ drive-strength = <6>; bias-disable; }; + + pcie0_default_state: pcie0-default { + perst { + pins = "gpio35"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio36"; + function = "pci_e0"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio37"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default { + perst { + pins = "gpio102"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio103"; + function = "pci_e1"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio104"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; }; remoteproc_mpss: remoteproc@4080000 { -- cgit v1.2.3 From 03d470ce2b70f269cecf2aeacee41e228cafde44 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 26 Mar 2022 11:27:54 +0530 Subject: arm64: dts: qcom: sa8155: Enable PCIe nodes SA8155p ADP board supports the PCIe0 controller in the RC mode (only). So add the support for the same. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220326055754.1796146-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8756c2b25c7e..676e4fe3f848 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -387,6 +387,21 @@ vdda-pll-supply = <&vdda_usb_ss_dp_core_1>; }; +&pcie0 { + status = "okay"; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l18c_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l18c_0p88>; + vdda-pll-supply = <&vreg_l8c_1p2>; +}; + &tlmm { gpio-reserved-ranges = <0 4>; -- cgit v1.2.3 From c043dee9cb6bc332746cd60ec42d5f8220d90332 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 17 Sep 2020 20:52:11 +0200 Subject: arm64: dts: rockchip: correct interrupt flags on rk3399 boards GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20200917185211.5483-2-krzk@kernel.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399-firefly.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts | 3 ++- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts | 2 +- arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 3 ++- 8 files changed, 14 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index c654b6b02f3f..b340c9e246c4 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include #include #include "rk3399.dtsi" @@ -786,7 +787,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts index bee45c17e2ca..7af27e8216f1 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dts @@ -2,6 +2,7 @@ /dts-v1/; #include #include +#include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -629,7 +630,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index 7ba3ed24084b..46c4581deb8d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -6,6 +6,7 @@ /dts-v1/; #include +#include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -682,7 +683,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; brcm,drive-strength = <5>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts index 5bbe74bed0ea..a21ac319f809 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -509,7 +510,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts index 9d3a718f66f6..ed856bfcfc33 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-orangepi.dts @@ -7,6 +7,7 @@ #include "dt-bindings/pwm/pwm.h" #include "dt-bindings/input/input.h" +#include #include "dt-bindings/usb/pd.h" #include "rk3399.dtsi" #include "rk3399-opp.dtsi" @@ -735,7 +736,7 @@ reg = <1>; compatible = "brcm,bcm4329-fmac"; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts index cf48746a3ad8..0806545922f5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts @@ -23,7 +23,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts index 793d84833921..4053ba72618c 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dts @@ -31,7 +31,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi index 25dc61c26a94..94e39ed63397 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi @@ -7,6 +7,7 @@ #include "rk3399.dtsi" #include "rk3399-opp.dtsi" +#include / { aliases { @@ -528,7 +529,7 @@ compatible = "brcm,bcm4329-fmac"; reg = <1>; interrupt-parent = <&gpio0>; - interrupts = ; + interrupts = ; interrupt-names = "host-wake"; pinctrl-names = "default"; pinctrl-0 = <&wifi_host_wake_l>; -- cgit v1.2.3 From ef5814e75b2bd9714dbfd60bfc360f940092ba62 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Mon, 4 Apr 2022 10:49:42 +0200 Subject: arm64: dts: rockchip: fix Makefile sorting for BananaPi R2 Pro Banana before evb of course. Fixes: f901aaadaa2a ("arm64: dts: rockchip: Add Bananapi R2 Pro") Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 4ae9f35434b8..a8893d1d0b9e 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,5 +59,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb -dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb -- cgit v1.2.3 From 22a442e6586c898a6da1fbc57fab1b31dfc3e4b5 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Thu, 10 Mar 2022 22:03:51 +0100 Subject: arm64: dts: rockchip: add basic dts for the radxa rock3 model a Add basic device tree for the Radxa ROCK3 Model A board (with the Rockchip RK3568 SoC) including Ethernet, USB2 and headphone connector. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220310210352.451136-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 502 ++++++++++++++++++++++++ 2 files changed, 503 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index a8893d1d0b9e..99941e9dbba1 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -61,3 +61,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts new file mode 100644 index 000000000000..53cf444ecb04 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -0,0 +1,502 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; +#include +#include +#include +#include "rk3568.dtsi" + +/ { + model = "Radxa ROCK3 Model A"; + compatible = "radxa,rock3a", "rockchip,rk3568"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_user: led-0 { + gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_HEARTBEAT; + color = ; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&led_user_en>; + }; + }; + + rk809-sound { + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,name = "Analog RK809"; + simple-audio-card,mclk-fs = <256>; + + simple-audio-card,cpu { + sound-dai = <&i2s1_8ch>; + }; + + simple-audio-card,codec { + sound-dai = <&rk809>; + }; + }; + + vcc12v_dcin: vcc12v-dcin { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + }; + + vcc3v3_sys: vcc3v3-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_sys: vcc5v0-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb: vcc5v0-usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; + assigned-clock-rates = <0>, <125000000>; + clock_in_out = "output"; + phy-handle = <&rgmii_phy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_rgmii_bus>; + status = "okay"; +}; + +&gpu { + mali-supply = <&vdd_gpu>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + assigned-clocks = <&cru I2S1_MCLKOUT_TX>; + assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; + clock-names = "mclk"; + clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>; + rockchip,system-power-controller; + #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + wakeup-source; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + codec { + mic-in-differential; + }; + }; +}; + +&i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth_phy_rst { + rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + led_user_en: led_user_en { + rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb2phy1_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; -- cgit v1.2.3 From 9f4c480f24e2ce1d464ff9d5f8a249a485acdc7f Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 8 Apr 2022 11:12:35 -0400 Subject: arm64: dts: rockchip: add rk356x dwc3 usb3 nodes Add the dwc3 device nodes to the rk356x device trees. The rk3566 has one usb2 capable dwc3 otg controller and one usb3 capable dwc3 host controller. The rk3568 has one usb3 capable dwc3 otg controller and one usb3 capable dwc3 host controller. Signed-off-by: Peter Geis Tested-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220408151237.3165046-4-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566.dtsi | 11 ++++++++++ arch/arm64/boot/dts/rockchip/rk3568.dtsi | 9 ++++++++ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 35 +++++++++++++++++++++++++++++++- 3 files changed, 54 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi index 3839eef5e4f7..0b957068ff89 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi @@ -6,6 +6,10 @@ compatible = "rockchip,rk3566"; }; +&pipegrf { + compatible = "rockchip,rk3566-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -18,3 +22,10 @@ #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>; + phy-names = "usb2-phy"; + extcon = <&usb2phy0>; + maximum-speed = "high-speed"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi index 3e07d9f6a2d1..5eafddf62edc 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi @@ -113,6 +113,10 @@ }; }; +&pipegrf { + compatible = "rockchip,rk3568-pipe-grf", "syscon"; +}; + &power { power-domain@RK3568_PD_PIPE { reg = ; @@ -128,3 +132,8 @@ #power-domain-cells = <0>; }; }; + +&usb_host0_xhci { + phys = <&usb2phy0_otg>, <&combphy0 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 264dd030e703..55e6dcb948cc 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -258,6 +258,40 @@ status = "disabled"; }; + usb_host0_xhci: usb@fcc00000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfcc00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>, + <&cru ACLK_USB3OTG0>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG0>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + + usb_host1_xhci: usb@fd000000 { + compatible = "rockchip,rk3568-dwc3", "snps,dwc3"; + reg = <0x0 0xfd000000 0x0 0x400000>; + interrupts = ; + clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>, + <&cru ACLK_USB3OTG1>; + clock-names = "ref_clk", "suspend_clk", + "bus_clk"; + dr_mode = "host"; + phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>; + phy-names = "usb2-phy", "usb3-phy"; + phy_type = "utmi_wide"; + power-domains = <&power RK3568_PD_PIPE>; + resets = <&cru SRST_USB3OTG1>; + snps,dis_u2_susphy_quirk; + status = "disabled"; + }; + gic: interrupt-controller@fd400000 { compatible = "arm,gic-v3"; reg = <0x0 0xfd400000 0 0x10000>, /* GICD */ @@ -325,7 +359,6 @@ }; pipegrf: syscon@fdc50000 { - compatible = "rockchip,rk3568-pipe-grf", "syscon"; reg = <0x0 0xfdc50000 0x0 0x1000>; }; -- cgit v1.2.3 From e432309ff8bf2a148bbdd4946ca1580c6b5b610c Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 8 Apr 2022 11:12:36 -0400 Subject: arm64: dts: rockchip: enable dwc3 on quartz64-a The quartz64 model a has support for both the dwc3 otg port and the dwc3 host port. Add the otg power supply and dwc3 nodes to the device tree to enable support for these. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220408151237.3165046-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index dd7f4b9b686b..141a433429b5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts @@ -151,6 +151,16 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb20_otg: vcc5v0_usb20_otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + regulator-name = "vcc5v0_usb20_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dcdc_boost>; + }; + vcc3v3_sd: vcc3v3_sd { compatible = "regulator-fixed"; enable-active-low; @@ -187,6 +197,10 @@ }; }; +&combphy1 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -672,6 +686,29 @@ status = "okay"; }; +&usb_host0_xhci { + status = "okay"; +}; + +/* usb3 controller is muxed with sata1 */ +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb20_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb20_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; -- cgit v1.2.3 From d6cfb110b0fdfb4e61ef4e3c3ab89a8f21b4d1b8 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Fri, 8 Apr 2022 11:12:37 -0400 Subject: arm64: dts: rockchip: add usb3 support to rk3568-evb1-v10 The Rockchip RK3568 EVB1 features one USB 3.0 device-only (USB 2.0 OTG) port and one USB 3.0 host-only port. Activate the USB 3.0 controller nodes and phy nodes in the device tree. Signed-off-by: Sascha Hauer Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220408151237.3165046-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts | 46 ++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts index a794a0ea5c70..622be8be9813 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts @@ -103,6 +103,18 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + vcc3v3_lcd0_n: vcc3v3-lcd0-n { compatible = "regulator-fixed"; regulator-name = "vcc3v3_lcd0_n"; @@ -136,6 +148,14 @@ }; }; +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; +}; + &cpu0 { cpu-supply = <&vdd_cpu>; }; @@ -507,6 +527,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; @@ -568,6 +591,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -576,6 +604,24 @@ status = "okay"; }; +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; -- cgit v1.2.3 From f29ffce32b4e1204b67f82fd80584ec4173cca54 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sat, 9 Apr 2022 13:21:35 +0200 Subject: arm64: dts: rockchip: Add USB nodes for BPI-R2-Pro Add usb2 nodes to Bananapi R2 Pro board Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220409112136.164481-2-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 93 ++++++++++++++++++++++ 1 file changed, 93 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index a01886b467ed..e96622c4c413 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -72,6 +72,50 @@ regulator-max-microvolt = <5000000>; vin-supply = <&dc_12v>; }; + + vcc5v0_usb: vcc5v0_usb { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&dc_12v>; + }; + + vcc5v0_usb_host: vcc5v0-usb-host { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_host_en>; + regulator-name = "vcc5v0_usb_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + /* used for USB3 */ + status = "okay"; +}; + +&combphy1 { + /* used for USB3 */ + status = "okay"; }; &gmac0 { @@ -338,6 +382,16 @@ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + + usb { + vcc5v0_usb_host_en: vcc5v0_usb_host_en { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &pmu_io_domains { @@ -455,3 +509,42 @@ pinctrl-0 = <&uart9m1_xfer>; status = "disabled"; }; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; + +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + +&usb_host1_ehci { + status = "okay"; +}; + +&usb_host1_ohci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; -- cgit v1.2.3 From 551e645fed5dd2ed4c81c9e3d3b4827862f51dc6 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Sat, 9 Apr 2022 13:21:36 +0200 Subject: arm64: dts: rockchip: Add SATA support to BPI-R2-Pro Enable the Combphy and Sata nodes in Bananapi R2 Pro Board. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20220409112136.164481-3-linux@fw-web.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts index e96622c4c413..a4aba63c7a1f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts @@ -118,6 +118,11 @@ status = "okay"; }; +&combphy2 { + /* used for SATA */ + status = "okay"; +}; + &gmac0 { assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; @@ -454,6 +459,10 @@ status = "okay"; }; +&sata2 { + status = "okay"; +}; + &sdhci { bus-width = <8>; max-frequency = <200000000>; -- cgit v1.2.3 From e03774ff21493f4f82ec7853b33fb3ccc35e4363 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 29 Mar 2022 17:07:41 +0200 Subject: arm64: dts: rockchip: use generic node name for pmucru on rk3399 The node names should be generic, so fix this for the rk3399 pmucru node and rename it to "clock-controller". Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20220329150742.22093-5-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 88f26d89eea1..01c08a2aaf73 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1413,7 +1413,7 @@ clock-names = "apb_pclk"; }; - pmucru: pmu-clock-controller@ff750000 { + pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; rockchip,grf = <&pmugrf>; -- cgit v1.2.3 From 14fc86b9aa5435bf7dd75839c9a73d9a85a98396 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Tue, 29 Mar 2022 17:07:42 +0200 Subject: arm64: dts: rockchip: add clocks property to cru nodes rk3399 Add clocks property to rk3399 cru nodes to fix warnings like: 'clocks' is a dependency of 'assigned-clocks'. Signed-off-by: Johan Jonker Link: https://lore.kernel.org/r/20220329150742.22093-6-jbx6244@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 01c08a2aaf73..56af1a1d65ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1416,6 +1416,8 @@ pmucru: clock-controller@ff750000 { compatible = "rockchip,rk3399-pmucru"; reg = <0x0 0xff750000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&pmugrf>; #clock-cells = <1>; #reset-cells = <1>; @@ -1426,6 +1428,8 @@ cru: clock-controller@ff760000 { compatible = "rockchip,rk3399-cru"; reg = <0x0 0xff760000 0x0 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; -- cgit v1.2.3 From 1b3f36854ab74839693582bc957930f4416ce8ff Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 8 Mar 2022 11:08:57 -0800 Subject: arm64: dts: rockchip: Add dfi and dmc nodes to rk3399 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These are required to support DDR DVFS on RK3399 platforms. Change since Daniel's posting: reordered by unit address, per existing style Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220308110825.v4.11.Ie97993621975c5463d7928a8646f3737c9f2921d@changeid Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 56af1a1d65ef..a90beec50f6a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -178,6 +178,15 @@ ports = <&vopl_out>, <&vopb_out>; }; + dmc: memory-controller { + compatible = "rockchip,rk3399-dmc"; + rockchip,pmu = <&pmugrf>; + devfreq-events = <&dfi>; + clocks = <&cru SCLK_DDRC>; + clock-names = "dmc_clk"; + status = "disabled"; + }; + pmu_a53 { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -1295,6 +1304,16 @@ status = "disabled"; }; + dfi: dfi@ff630000 { + reg = <0x00 0xff630000 0x00 0x4000>; + compatible = "rockchip,rk3399-dfi"; + rockchip,pmu = <&pmugrf>; + interrupts = ; + clocks = <&cru PCLK_DDR_MON>; + clock-names = "pclk_ddr_mon"; + status = "disabled"; + }; + vpu: video-codec@ff650000 { compatible = "rockchip,rk3399-vpu"; reg = <0x0 0xff650000 0x0 0x800>; -- cgit v1.2.3 From 80bc6f34c559c97069b75d6eb453d4218c3ed017 Mon Sep 17 00:00:00 2001 From: Lin Huang Date: Tue, 8 Mar 2022 11:08:58 -0800 Subject: arm64: dts: rockchip: Enable dmc and dfi nodes on gru MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable the DMC (Dynamic Memory Controller) and the DFI (DDR PHY Interface) nodes on gru boards so we can support DDR DVFS. Signed-off-by: Lin Huang Signed-off-by: Enric Balletbo i Serra Signed-off-by: Gaël PORTAY Signed-off-by: Daniel Lezcano Signed-off-by: Brian Norris Link: https://lore.kernel.org/r/20220308110825.v4.12.I3a5c7f21ecd8221b42c2dbcd618386bce7b3e9a6@changeid Signed-off-by: Heiko Stuebner --- .../boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 7 ++++++ .../boot/dts/rockchip/rk3399-gru-scarlet.dtsi | 12 ++++++++++ arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 28 ++++++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi | 25 +++++++++++++++++++ 4 files changed, 72 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi index 3355fb90fa54..50d459ee4831 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi @@ -234,6 +234,13 @@ extcon = <&usbc_extcon0>, <&usbc_extcon1>; }; +&dmc { + center-supply = <&ppvar_centerlogic>; + rockchip,pd-idle-dis-freq-hz = <800000000>; + rockchip,sr-idle-dis-freq-hz = <800000000>; + rockchip,sr-mc-gate-idle-dis-freq-hz = <800000000>; +}; + &edp { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi index a9817b3d7edc..913d845eb51a 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi @@ -391,6 +391,18 @@ camera: &i2c7 { <400000000>; }; +/* The center supply is fixed to .9V on scarlet */ +&dmc { + center-supply = <&pp900_s0>; +}; + +/* We don't need .925 V for 928 MHz on scarlet */ +&dmc_opp_table { + opp03 { + opp-microvolt = <900000>; + }; +}; + &gpio0 { gpio-line-names = /* GPIO0 A 0-7 */ "CLK_32K_AP", diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index 162f08bca0d4..23bfba86daab 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -373,6 +373,34 @@ <200000000>; }; +&dfi { + status = "okay"; +}; + +&dmc { + status = "okay"; + + rockchip,pd-idle-ns = <160>; + rockchip,sr-idle-ns = <10240>; + rockchip,sr-mc-gate-idle-ns = <40960>; + rockchip,srpd-lite-idle-ns = <61440>; + rockchip,standby-idle-ns = <81920>; + + rockchip,ddr3_odt_dis_freq = <666000000>; + rockchip,lpddr3_odt_dis_freq = <666000000>; + rockchip,lpddr4_odt_dis_freq = <666000000>; + + rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; + rockchip,srpd-lite-idle-dis-freq-hz = <0>; + rockchip,standby-idle-dis-freq-hz = <928000000>; +}; + +&dmc_opp_table { + opp03 { + opp-suspend; + }; +}; + &emmc_phy { status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi index 2180e0f75003..6e29e74f6fc6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-op1-opp.dtsi @@ -110,6 +110,27 @@ opp-microvolt = <1075000>; }; }; + + dmc_opp_table: dmc_opp_table { + compatible = "operating-points-v2"; + + opp00 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000>; + }; + opp01 { + opp-hz = /bits/ 64 <666000000>; + opp-microvolt = <900000>; + }; + opp02 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <900000>; + }; + opp03 { + opp-hz = /bits/ 64 <928000000>; + opp-microvolt = <925000>; + }; + }; }; &cpu_l0 { @@ -136,6 +157,10 @@ operating-points-v2 = <&cluster1_opp>; }; +&dmc { + operating-points-v2 = <&dmc_opp_table>; +}; + &gpu { operating-points-v2 = <&gpu_opp_table>; }; -- cgit v1.2.3 From f9814e2ef9056fd919e774e95f721e12420648e6 Mon Sep 17 00:00:00 2001 From: Philip Rinn Date: Thu, 7 Apr 2022 17:51:45 +0200 Subject: arm64: dts: allwinner: a64: olinuxino: Enable audio Enable the audio hardware on the Olimex A64-OLinuXino board family. Tested on the A64-OLinuXino-2Ge8G-IND variant. Signed-off-by: Philip Rinn Acked-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220407155145.10891-1-rinni@inventati.org --- .../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 30 ++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts index ec7e2c0e82c1..bfb806cf6d7a 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts @@ -58,6 +58,15 @@ }; }; +&codec { + status = "okay"; +}; + +&codec_analog { + cpvdd-supply = <®_eldo1>; + status = "okay"; +}; + &cpu0 { cpu-supply = <®_dcdc2>; }; @@ -74,6 +83,10 @@ cpu-supply = <®_dcdc2>; }; +&dai { + status = "okay"; +}; + &de { status = "okay"; }; @@ -328,6 +341,23 @@ vcc-hdmi-supply = <®_dldo1>; }; +&sound { + simple-audio-card,aux-devs = <&codec_analog>; + simple-audio-card,widgets = "Microphone", "Microphone Jack Left", + "Microphone", "Microphone Jack Right", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = "Left DAC", "DACL", + "Right DAC", "DACR", + "Headphone Jack", "HP", + "ADCL", "Left ADC", + "ADCR", "Right ADC", + "Microphone Jack Left", "MBIAS", + "MIC1", "Microphone Jack Left", + "Microphone Jack Right", "MBIAS", + "MIC2", "Microphone Jack Right"; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pb_pins>; -- cgit v1.2.3 From 9ad9773e89f8e06148b2a0e77fcdcd716f8f3b18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Mar 2022 18:23:51 +0100 Subject: arm64: dts: imx8mp: Add missing speed grade phandle And missing speed grade phandle to cpu@0 node. Signed-off-by: Marek Vasut Cc: Anson Huang Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index afd36374dccb..68e6c9099f65 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -59,6 +59,8 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + nvmem-cells = <&cpu_speed_grade>; + nvmem-cell-names = "speed_grade"; #cooling-cells = <2>; }; -- cgit v1.2.3 From 21a14c68f3a34e1ad06d05c153446644fefa748b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 11 Mar 2022 18:23:52 +0100 Subject: arm64: dts: imx8mp: Add cpu-freq support Add A53 OPP table and cpu regulator to support cpu-freq driver. Signed-off-by: Marek Vasut Cc: Anson Huang Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 33 +++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 68e6c9099f65..e910dc22bf43 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -61,6 +61,7 @@ next-level-cache = <&A53_L2>; nvmem-cells = <&cpu_speed_grade>; nvmem-cell-names = "speed_grade"; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -78,6 +79,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -95,6 +97,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -112,6 +115,7 @@ d-cache-line-size = <64>; d-cache-sets = <128>; next-level-cache = <&A53_L2>; + operating-points-v2 = <&a53_opp_table>; #cooling-cells = <2>; }; @@ -124,6 +128,35 @@ }; }; + a53_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x8a0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1600000000 { + opp-hz = /bits/ 64 <1600000000>; + opp-microvolt = <950000>; + opp-supported-hw = <0xa0>, <0x7>; + clock-latency-ns = <150000>; + opp-suspend; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1000000>; + opp-supported-hw = <0x20>, <0x3>; + clock-latency-ns = <150000>; + opp-suspend; + }; + }; + osc_32k: clock-osc-32k { compatible = "fixed-clock"; #clock-cells = <0>; -- cgit v1.2.3 From 68b7cf5d91d4c7e8a690693a53738e66d60113f1 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Mon, 21 Mar 2022 15:51:31 +0800 Subject: arm64: dts: imx8mp: add ddr controller node to support EDAC on imx8mp i.MX8MP use synopsys V3.70a ddr controller IP, so add edac support for i.MX8MP based on "snps,ddrc-3.80a" synopsys edac driver. Signed-off-by: Sherry Sun Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index e910dc22bf43..2c207bc27d70 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1009,6 +1009,12 @@ interrupt-parent = <&gic>; }; + edacmc: memory-controller@3d400000 { + compatible = "snps,ddrc-3.80a"; + reg = <0x3d400000 0x400000>; + interrupts = ; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; -- cgit v1.2.3 From 97a07703cf9674823f4432facc0fbcbaed683eeb Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:40 +0100 Subject: arm64: dts: imx8mm-verdin: update regulator names Annotate regulators which are on-module. Rename usb_otg{1/2}_vbus to USB_{1/2}_EN more in-line with Verdin spec. Annotate PMIC regulators with information on which BUCK/LDO they are on. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 28 ++++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 0d84d29e70f1..f70782d2a23d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -86,7 +86,7 @@ regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3_ETH"; + regulator-name = "On-module +V3.3_ETH"; startup-delay-us = <200000>; }; @@ -99,7 +99,7 @@ pinctrl-0 = <&pinctrl_reg_usb1_en>; regulator-max-microvolt = <5000000>; regulator-min-microvolt = <5000000>; - regulator-name = "usb_otg1_vbus"; + regulator-name = "USB_1_EN"; }; reg_usb_otg2_vbus: regulator-usb-otg2 { @@ -111,7 +111,7 @@ pinctrl-0 = <&pinctrl_reg_usb2_en>; regulator-max-microvolt = <5000000>; regulator-min-microvolt = <5000000>; - regulator-name = "usb_otg2_vbus"; + regulator-name = "USB_2_EN"; }; reg_usdhc2_vmmc: regulator-usdhc2 { @@ -345,7 +345,7 @@ regulator-boot-on; regulator-max-microvolt = <850000>; regulator-min-microvolt = <800000>; - regulator-name = "+VDD_SOC"; + regulator-name = "On-module +VDD_SOC (BUCK1)"; regulator-ramp-delay = <3125>; }; @@ -356,7 +356,7 @@ regulator-boot-on; regulator-max-microvolt = <950000>; regulator-min-microvolt = <850000>; - regulator-name = "+VDD_ARM"; + regulator-name = "On-module +VDD_ARM (BUCK2)"; regulator-ramp-delay = <3125>; }; @@ -365,7 +365,7 @@ regulator-boot-on; regulator-max-microvolt = <950000>; regulator-min-microvolt = <850000>; - regulator-name = "+VDD_GPU_VPU_DDR"; + regulator-name = "On-module +VDD_GPU_VPU_DDR (BUCK3)"; }; reg_vdd_3v3: BUCK4 { @@ -373,7 +373,7 @@ regulator-boot-on; regulator-max-microvolt = <3300000>; regulator-min-microvolt = <3300000>; - regulator-name = "+V3.3"; + regulator-name = "On-module +V3.3 (BUCK4)"; }; reg_vdd_1v8: BUCK5 { @@ -381,7 +381,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "PWR_1V8_MOCI"; + regulator-name = "PWR_1V8_MOCI (BUCK5)"; }; reg_nvcc_dram: BUCK6 { @@ -389,7 +389,7 @@ regulator-boot-on; regulator-max-microvolt = <1100000>; regulator-min-microvolt = <1100000>; - regulator-name = "+VDD_DDR"; + regulator-name = "On-module +VDD_DDR (BUCK6)"; }; reg_nvcc_snvs: LDO1 { @@ -397,7 +397,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8_SNVS"; + regulator-name = "On-module +V1.8_SNVS (LDO1)"; }; reg_vdd_snvs: LDO2 { @@ -405,7 +405,7 @@ regulator-boot-on; regulator-max-microvolt = <900000>; regulator-min-microvolt = <800000>; - regulator-name = "+V0.8_SNVS"; + regulator-name = "On-module +V0.8_SNVS (LDO2)"; }; reg_vdda: LDO3 { @@ -413,7 +413,7 @@ regulator-boot-on; regulator-max-microvolt = <1800000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V1.8A"; + regulator-name = "On-module +V1.8A (LDO3)"; }; reg_vdd_phy: LDO4 { @@ -421,13 +421,13 @@ regulator-boot-on; regulator-max-microvolt = <900000>; regulator-min-microvolt = <900000>; - regulator-name = "+V0.9_MIPI"; + regulator-name = "On-module +V0.9_MIPI (LDO4)"; }; reg_nvcc_sd: LDO5 { regulator-max-microvolt = <3300000>; regulator-min-microvolt = <1800000>; - regulator-name = "+V3.3_1.8_SD"; + regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; }; }; }; -- cgit v1.2.3 From 98e4f1930ef1561042a1be3b3b4fef7c3c271729 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:41 +0100 Subject: arm64: dts: imx8mm-verdin: multi-line comment style Fix multi-line comment style. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index f70782d2a23d..de811be435d0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -580,8 +580,10 @@ atmel_mxt_ts: touch@4a { compatible = "atmel,maxtouch"; - /* Verdin GPIO_9_DSI */ - /* (TOUCH_INT#, SODIMM 17, also routed to SN65dsi83 IRQ albeit currently unused) */ + /* + * Verdin GPIO_9_DSI + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + */ interrupt-parent = <&gpio3>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; @@ -695,8 +697,8 @@ uart-has-rtscts; }; -/* Verdin UART_4 */ /* + * Verdin UART_4 * Resource allocated to M4 by default, must not be accessed from Cortex-A35 or you get an OOPS */ &uart4 { @@ -1205,8 +1207,10 @@ ; }; - /* On-module Wi-Fi/BT or type specific SDHC interface */ - /* (e.g. on X52 extension slot of Verdin Development Board) */ + /* + * On-module Wi-Fi/BT or type specific SDHC interface + * (e.g. on X52 extension slot of Verdin Development Board) + */ pinctrl_usdhc3: usdhc3grp { fsl,pins = , -- cgit v1.2.3 From 344acf05d89ff9a5d3e3d047d36d328efc799fee Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:42 +0100 Subject: arm64: dts: imx8mm-verdin: alphabetically re-order nodes Alphabetically re-order nodes. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-verdin-wifi.dtsi | 26 +++++++++++----------- 1 file changed, 13 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi index 3e06a6ce3406..017db9eab256 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -17,19 +17,6 @@ }; }; -/* On-module Wi-Fi */ -&usdhc3 { - bus-width = <4>; - keep-power-in-suspend; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; - pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; - pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; - vmmc-supply = <®_wifi_en>; - status = "okay"; -}; - &gpio3 { gpio-line-names = "SODIMM_52", "SODIMM_54", @@ -92,3 +79,16 @@ "SODIMM_135", "SODIMM_129"; }; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; -- cgit v1.2.3 From 9847725e3a775832376646907159ce644d90bb18 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:43 +0100 Subject: arm64: dts: imx8mm-verdin: only dashes in node names Make sure we only have dashes rather than underscores in node names by renaming ctrl_sleep_moci-hog to ctrl-sleep-moci-hog. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index de811be435d0..599b620ae04d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -306,7 +306,7 @@ "SODIMM_151", "SODIMM_153"; - ctrl_sleep_moci-hog { + ctrl-sleep-moci-hog { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ gpios = <1 GPIO_ACTIVE_HIGH>; -- cgit v1.2.3 From 79c1c8509cbc3ce586fa7903cb1f9905b9f8326d Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:44 +0100 Subject: arm64: dts: imx8mm-verdin: comment about i2c level shifter Add a note about the bootloader being expected to switch on the I2C level shifter for the TLA2024 ADC behind this PMIC. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 599b620ae04d..4542c99ce906 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -337,6 +337,11 @@ reg = <0x25>; sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + /* + * The bootloader is expected to switch on the I2C level shifter for the TLA2024 ADC + * behind this PMIC. + */ + regulators { reg_vdd_soc: BUCK1 { nxp,dvs-run-voltage = <850000>; -- cgit v1.2.3 From 60f01b5b5c7df32360329aea9b455d13b76d2a5f Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:45 +0100 Subject: arm64: dts: imx8mm-verdin: update iomux configuration Update IOMUX configuration as required by the hardware design team. Signed-off-by: Andrejs Cainikovs Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 304 +++++++++++------------ 1 file changed, 152 insertions(+), 152 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 4542c99ce906..7976d055f17b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -781,34 +781,34 @@ pinctrl_can1_int: can1intgrp { fsl,pins = - ; /* CAN_1_SPI_INT#_1.8V */ + ; /* CAN_1_SPI_INT#_1.8V */ }; pinctrl_can2_int: can2intgrp { fsl,pins = - ; /* CAN_2_SPI_INT#_1.8V */ + ; /* CAN_2_SPI_INT#_1.8V, unused */ }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = - ; /* SODIMM 256 */ + ; /* SODIMM 256 */ }; pinctrl_ecspi2: ecspi2grp { fsl,pins = - , /* SODIMM 196 */ - , /* SODIMM 200 */ - , /* SODIMM 198 */ - ; /* SODIMM 202 */ + , /* SODIMM 196 */ + , /* SODIMM 200 */ + , /* SODIMM 198 */ + ; /* SODIMM 202 */ }; pinctrl_ecspi3: ecspi3grp { fsl,pins = - , /* CAN_SPI_SCK_1.8V */ - , /* CAN_SPI_MOSI_1.8V */ - , /* CAN_SPI_MISO_1.8V */ - , /* CAN_1_SPI_CS_1.8V# */ - ; /* CAN_2_SPI_CS#_1.8V */ + , /* CAN_SPI_SCK_1.8V */ + , /* CAN_SPI_MOSI_1.8V */ + , /* CAN_SPI_MISO_1.8V */ + , /* CAN_1_SPI_CS_1.8V# */ + ; /* CAN_2_SPI_CS#_1.8V */ }; pinctrl_fec1: fec1grp { @@ -827,7 +827,7 @@ , , , - ; + ; }; pinctrl_fec1_sleep: fec1-sleepgrp { @@ -846,170 +846,170 @@ , , , - ; + ; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = - , /* SODIMM 52 */ - , /* SODIMM 54 */ - , /* SODIMM 64 */ - , /* SODIMM 66 */ - , /* SODIMM 56 */ - , /* SODIMM 58 */ - , /* SODIMM 60 */ - ; /* SODIMM 62 */ + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 64 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + ; /* SODIMM 62 */ }; pinctrl_gpio1: gpio1grp { fsl,pins = - ; /* SODIMM 206 */ + ; /* SODIMM 206 */ }; pinctrl_gpio2: gpio2grp { fsl,pins = - ; /* SODIMM 208 */ + ; /* SODIMM 208 */ }; pinctrl_gpio3: gpio3grp { fsl,pins = - ; /* SODIMM 210 */ + ; /* SODIMM 210 */ }; pinctrl_gpio4: gpio4grp { fsl,pins = - ; /* SODIMM 212 */ + ; /* SODIMM 212 */ }; pinctrl_gpio5: gpio5grp { fsl,pins = - ; /* SODIMM 216 */ + ; /* SODIMM 216 */ }; pinctrl_gpio6: gpio6grp { fsl,pins = - ; /* SODIMM 218 */ + ; /* SODIMM 218 */ }; pinctrl_gpio7: gpio7grp { fsl,pins = - ; /* SODIMM 220 */ + ; /* SODIMM 220 */ }; pinctrl_gpio8: gpio8grp { fsl,pins = - ; /* SODIMM 222 */ + ; /* SODIMM 222 */ }; /* Verdin GPIO_9_DSI (pulled-up as active-low) */ pinctrl_gpio_9_dsi: gpio9dsigrp { fsl,pins = - ; /* SODIMM 17 */ + ; /* SODIMM 17 */ }; - /* Verdin GPIO_10_DSI */ + /* Verdin GPIO_10_DSI (pulled-up as active-low) */ pinctrl_gpio_10_dsi: gpio10dsigrp { fsl,pins = - ; /* SODIMM 21 */ + ; /* SODIMM 21 */ }; pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = - , /* SODIMM 88 */ - , /* SODIMM 90 */ - , /* SODIMM 92 */ - , /* SODIMM 94 */ - , /* SODIMM 96 */ - , /* SODIMM 100 */ - , /* SODIMM 102 */ - , /* SODIMM 104 */ - , /* SODIMM 106 */ - , /* SODIMM 108 */ - , /* SODIMM 112 */ - , /* SODIMM 114 */ - , /* SODIMM 116 */ - , /* SODIMM 118 */ - ; /* SODIMM 120 */ + , /* SODIMM 88 */ + , /* SODIMM 90 */ + , /* SODIMM 92 */ + , /* SODIMM 94 */ + , /* SODIMM 96 */ + , /* SODIMM 100 */ + , /* SODIMM 102 */ + , /* SODIMM 104 */ + , /* SODIMM 106 */ + , /* SODIMM 108 */ + , /* SODIMM 112 */ + , /* SODIMM 114 */ + , /* SODIMM 116 */ + , /* SODIMM 118 */ + ; /* SODIMM 120 */ }; pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = - ; /* SODIMM 91 */ + ; /* SODIMM 91 */ }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = - , /* SODIMM 157 */ - ; /* SODIMM 187 */ + , /* SODIMM 157 */ + ; /* SODIMM 187 */ }; pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = - ; /* SODIMM 252 */ + ; /* SODIMM 252 */ }; /* On-module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = - , /* PMIC_I2C_SCL */ - ; /* PMIC_I2C_SDA */ + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = - , /* SODIMM 55 */ - ; /* SODIMM 53 */ + , /* SODIMM 55 */ + ; /* SODIMM 53 */ }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = - , /* SODIMM 95 */ - ; /* SODIMM 93 */ + , /* SODIMM 95 */ + ; /* SODIMM 93 */ }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; pinctrl_i2c4_gpio: i2c4gpiogrp { fsl,pins = - , /* SODIMM 14 */ - ; /* SODIMM 12 */ + , /* SODIMM 14 */ + ; /* SODIMM 12 */ }; /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = - ; /* SODIMM 42 */ + ; /* SODIMM 42 */ }; /* Verdin I2S_2_D_OUT shared with SAI5 */ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { fsl,pins = - ; /* SODIMM 46 */ + ; /* SODIMM 46 */ }; pinctrl_pcie0: pcie0grp { @@ -1021,7 +1021,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = - ; /* PMIC_INT# */ + ; /* PMIC_INT# */ }; /* Verdin PWM_3_DSI shared with GPIO1_IO1 */ @@ -1043,82 +1043,82 @@ /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { fsl,pins = - ; /* SODIMM 19 */ + ; /* SODIMM 19 */ }; pinctrl_reg_eth: regethgrp { fsl,pins = - ; /* PMIC_EN_ETH */ + ; /* PMIC_EN_ETH */ }; pinctrl_reg_usb1_en: regusb1engrp { fsl,pins = - ; /* SODIMM 155 */ + ; /* SODIMM 155 */ }; pinctrl_reg_usb2_en: regusb2engrp { fsl,pins = - ; /* SODIMM 185 */ + ; /* SODIMM 185 */ }; pinctrl_sai2: sai2grp { fsl,pins = - , /* SODIMM 32 */ - , /* SODIMM 30 */ - , /* SODIMM 38 */ - , /* SODIMM 36 */ - ; /* SODIMM 34 */ + , /* SODIMM 32 */ + , /* SODIMM 30 */ + , /* SODIMM 38 */ + , /* SODIMM 36 */ + ; /* SODIMM 34 */ }; pinctrl_sai5: sai5grp { fsl,pins = - , /* SODIMM 48 */ - , /* SODIMM 44 */ - , /* SODIMM 42 */ - ; /* SODIMM 46 */ + , /* SODIMM 48 */ + , /* SODIMM 44 */ + , /* SODIMM 42 */ + ; /* SODIMM 46 */ }; /* control signal for optional ATTPM20P or SE050 */ pinctrl_pmic_tpm_ena: pmictpmenagrp { fsl,pins = - ; /* PMIC_TPM_ENA */ + ; /* PMIC_TPM_ENA */ }; pinctrl_tsp: tspgrp { fsl,pins = - , /* SODIMM 148 */ - , /* SODIMM 152 */ - , /* SODIMM 154 */ - , /* SODIMM 174 */ - ; /* SODIMM 150 */ + , /* SODIMM 148 */ + , /* SODIMM 152 */ + , /* SODIMM 154 */ + , /* SODIMM 174 */ + ; /* SODIMM 150 */ }; pinctrl_uart1: uart1grp { fsl,pins = - , /* SODIMM 149 */ - ; /* SODIMM 147 */ + , /* SODIMM 149 */ + ; /* SODIMM 147 */ }; pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 129 */ - , /* SODIMM 131 */ - , /* SODIMM 133 */ - ; /* SODIMM 135 */ + , /* SODIMM 129 */ + , /* SODIMM 131 */ + , /* SODIMM 133 */ + ; /* SODIMM 135 */ }; pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 137 */ - , /* SODIMM 139 */ - , /* SODIMM 141 */ - ; /* SODIMM 143 */ + , /* SODIMM 137 */ + , /* SODIMM 139 */ + , /* SODIMM 141 */ + ; /* SODIMM 143 */ }; pinctrl_uart4: uart4grp { fsl,pins = - , /* SODIMM 151 */ - ; /* SODIMM 153 */ + , /* SODIMM 151 */ + ; /* SODIMM 153 */ }; pinctrl_usdhc1: usdhc1grp { @@ -1171,45 +1171,45 @@ pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = - ; /* SODIMM 84 */ + ; /* SODIMM 84 */ }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = - ; /* SODIMM 76 */ + ; /* SODIMM 76 */ }; pinctrl_usdhc2: usdhc2grp { fsl,pins = - , /* SODIMM 78 */ - , /* SODIMM 74 */ - , /* SODIMM 80 */ - , /* SODIMM 82 */ - , /* SODIMM 70 */ - , /* SODIMM 72 */ - ; + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + , /* SODIMM 72 */ + ; }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = - , - , - , - , - , - , - ; + , + , + , + , + , + , + ; }; /* @@ -1218,56 +1218,56 @@ */ pinctrl_usdhc3: usdhc3grp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = - , - , - , - , - , - ; + , + , + , + , + , + ; }; pinctrl_wdog: wdoggrp { fsl,pins = - ; /* PMIC_WDI */ + ; /* PMIC_WDI */ }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = - , /* WIFI_WKUP_BT */ - , /* WIFI_W_WKUP_HOST */ - ; /* WIFI_WKUP_WLAN */ + , /* WIFI_WKUP_BT */ + , /* WIFI_W_WKUP_HOST */ + ; /* WIFI_WKUP_WLAN */ }; pinctrl_wifi_i2s: bti2sgrp { fsl,pins = - , /* WIFI_TX_BCLK */ - , /* WIFI_TX_DATA0 */ - , /* WIFI_TX_SYNC */ - ; /* WIFI_RX_DATA0 */ + , /* WIFI_TX_BCLK */ + , /* WIFI_TX_DATA0 */ + , /* WIFI_TX_SYNC */ + ; /* WIFI_RX_DATA0 */ }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = - ; /* PMIC_EN_WIFI */ + ; /* PMIC_EN_WIFI */ }; }; -- cgit v1.2.3 From 593c535b0ddcc48325c1199549afcae74ccbfb96 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:46 +0100 Subject: arm64: dts: imx8mm-verdin: re-order pinctrl groups Alphabetically re-order pinctrl groups. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 92 ++++++++++++------------ 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 7976d055f17b..f188ac187c37 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -796,36 +796,36 @@ pinctrl_ecspi2: ecspi2grp { fsl,pins = - , /* SODIMM 196 */ - , /* SODIMM 200 */ , /* SODIMM 198 */ + , /* SODIMM 200 */ + , /* SODIMM 196 */ ; /* SODIMM 202 */ }; pinctrl_ecspi3: ecspi3grp { fsl,pins = + , /* CAN_2_SPI_CS#_1.8V */ , /* CAN_SPI_SCK_1.8V */ , /* CAN_SPI_MOSI_1.8V */ , /* CAN_SPI_MISO_1.8V */ - , /* CAN_1_SPI_CS_1.8V# */ - ; /* CAN_2_SPI_CS#_1.8V */ + ; /* CAN_1_SPI_CS_1.8V# */ }; pinctrl_fec1: fec1grp { fsl,pins = , , - , - , - , - , - , - , - , , - , + , + , + , , , + , + , + , + , + , , ; }; @@ -834,17 +834,17 @@ fsl,pins = , , - , - , - , - , - , - , - , , - , + , + , + , , , + , + , + , + , + , , ; }; @@ -854,11 +854,11 @@ , /* SODIMM 52 */ , /* SODIMM 54 */ , /* SODIMM 64 */ - , /* SODIMM 66 */ , /* SODIMM 56 */ , /* SODIMM 58 */ , /* SODIMM 60 */ - ; /* SODIMM 62 */ + , /* SODIMM 62 */ + ; /* SODIMM 66 */ }; pinctrl_gpio1: gpio1grp { @@ -1063,9 +1063,9 @@ pinctrl_sai2: sai2grp { fsl,pins = - , /* SODIMM 32 */ - , /* SODIMM 30 */ , /* SODIMM 38 */ + , /* SODIMM 30 */ + , /* SODIMM 32 */ , /* SODIMM 36 */ ; /* SODIMM 34 */ }; @@ -1095,23 +1095,23 @@ pinctrl_uart1: uart1grp { fsl,pins = - , /* SODIMM 149 */ - ; /* SODIMM 147 */ + , /* SODIMM 147 */ + ; /* SODIMM 149 */ }; pinctrl_uart2: uart2grp { fsl,pins = - , /* SODIMM 129 */ - , /* SODIMM 131 */ , /* SODIMM 133 */ - ; /* SODIMM 135 */ + , /* SODIMM 135 */ + , /* SODIMM 131 */ + ; /* SODIMM 129 */ }; pinctrl_uart3: uart3grp { fsl,pins = - , /* SODIMM 137 */ - , /* SODIMM 139 */ , /* SODIMM 141 */ + , /* SODIMM 139 */ + , /* SODIMM 137 */ ; /* SODIMM 143 */ }; @@ -1181,35 +1181,35 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = + , , /* SODIMM 78 */ , /* SODIMM 74 */ , /* SODIMM 80 */ , /* SODIMM 82 */ , /* SODIMM 70 */ - , /* SODIMM 72 */ - ; + ; /* SODIMM 72 */ }; pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { fsl,pins = + , , , , , , - , - ; + ; }; pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { fsl,pins = + , , , , , , - , - ; + ; }; /* @@ -1218,32 +1218,32 @@ */ pinctrl_usdhc3: usdhc3grp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { fsl,pins = - , - , , , , - ; + , + , + ; }; pinctrl_wdog: wdoggrp { -- cgit v1.2.3 From 473b34b8ce38f02b7b0c0272b90e30c99d8d4fdd Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:47 +0100 Subject: arm64: dts: imx8mm-verdin: capitalisation of verdin comments Fix capitalisation of Verdin in comments. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index aca5ae0d307d..c2a5c2f7b204 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -114,7 +114,7 @@ status = "okay"; }; -/* VERDIN I2S_1 */ +/* Verdin I2S_1 */ &sai2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index f188ac187c37..6e1c762fd2e7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -668,7 +668,7 @@ #pwm-cells = <3>; }; -/* VERDIN I2S_1 */ +/* Verdin I2S_1 */ &sai2 { #sound-dai-cells = <0>; assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; -- cgit v1.2.3 From f84ccff6d8f34b7b1513411bcb172e8c903fc14e Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:48 +0100 Subject: arm64: dts: imx8mm-verdin: note about disabled sd1 pull-ups MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a note about us using discrete external on-module resistors pulling-up to the on-module +V3.3_1.8_SD (LDO5) rail and explicitly disabling the internal pull-ups due to ERR050080 [1]: IO: Degradation of internal IO pullup/pulldown current capability for IO’s continuously driven in a 3.3V operating mode [1] https://www.nxp.com/webapp/Download?colCode=IMX8MM_0N87W Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 6e1c762fd2e7..97dd7a00d63b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -1179,6 +1179,10 @@ ; /* SODIMM 76 */ }; + /* + * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the + * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. + */ pinctrl_usdhc2: usdhc2grp { fsl,pins = , -- cgit v1.2.3 From 4f6b5de98560d27638dea2b43d9a97fa88b79e4b Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Thu, 24 Mar 2022 16:56:49 +0100 Subject: arm64: dts: imx8mm-verdin: add sd1 sleep pinctrl Add SD1 sleep pinctrl to avoid backfeeding during sleep. Signed-off-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index 97dd7a00d63b..eafa88d980b3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -757,10 +757,11 @@ bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; }; @@ -1174,6 +1175,11 @@ ; /* SODIMM 84 */ }; + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = ; /* SODIMM 76 */ @@ -1216,6 +1222,18 @@ ; }; + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + /* * On-module Wi-Fi/BT or type specific SDHC interface * (e.g. on X52 extension slot of Verdin Development Board) -- cgit v1.2.3 From be0b178c50c37a666d54f435da71cf9f008362a0 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 30 Mar 2022 13:33:29 +0200 Subject: arm64: dts: ls1028a: sl28: use ocelot-8021q tagging by default Enable the ocelot-8021q tagger by default which supports ethernet flow control. The new default is set in the common board dtsi. The actual switch node is enabled on a per board variant basis. Because of this we set the new tagger default for both internal ports and a particular variant is free to choose among the two port. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index c03f4e183389..0825c090ca95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -311,6 +311,14 @@ status = "okay"; }; +&mscc_felix_port4 { + dsa-tag-protocol = "ocelot-8021q"; +}; + +&mscc_felix_port5 { + dsa-tag-protocol = "ocelot-8021q"; +}; + &usb0 { status = "okay"; }; -- cgit v1.2.3 From 73d901d6dc6158e3a7474b184f319260a2ebc921 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 30 Mar 2022 13:34:42 +0200 Subject: arm64: dts: ls1028a: default to OTG mode for USB At the moment, the dtsi will force the dr_mode to host. This is problematic because it will always turn on the Vbus voltage regardless if the port is host or device. This might lead to a "shortcut" between the two USB endpoints because both might have their Vbus supplies enabled. Therefore, the default should be "otg" for any ports which aren't host only (from a SoC point of view) and have a user of the dtsi file overwrite that explicitly. Move the 'dr_mode = "host";' into the board dts. Now that the dtsi doesn't set the dr_mode anymore, we can also drop the 'dr_mode = "otg";' in the board dts because that is the default value if dr_mode is not set. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 1 + arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 ++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 -- 4 files changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 0825c090ca95..4ab17b984b03 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -324,5 +324,6 @@ }; &usb1 { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index 19d3952dbffe..5baf060acf93 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -382,9 +382,11 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { + dr_mode = "host"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index 68c31cb8eead..e0cd1516d05b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -299,10 +299,10 @@ }; &usb0 { + dr_mode = "host"; status = "okay"; }; &usb1 { - dr_mode = "otg"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 088271d49139..92465f777603 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -599,7 +599,6 @@ compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3100000 0x0 0x10000>; interrupts = ; - dr_mode = "host"; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; @@ -610,7 +609,6 @@ compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; reg = <0x0 0x3110000 0x0 0x10000>; interrupts = ; - dr_mode = "host"; snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -- cgit v1.2.3 From 7cbeeb0553615d4c8beaab36170f26b138f718ee Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 3 Apr 2022 00:38:55 +0530 Subject: arm64: dts: lx2160a: Update can node property fsl,clk-source property is of type uint8 and need to be defined as "/bits/ 8 <0>". Simply setting value to 0 raise warning: can@2180000: fsl,clk-source:0: [0, 0, 0, 0] is too long Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index c5daa15b020d..82bd8c0f318b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -909,7 +909,7 @@ QORIQ_CLK_PLL_DIV(8)>, <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg", "per"; - fsl,clk-source = <0>; + fsl,clk-source = /bits/ 8 <0>; status = "disabled"; }; @@ -921,7 +921,7 @@ QORIQ_CLK_PLL_DIV(8)>, <&clockgen QORIQ_CLK_SYSCLK 0>; clock-names = "ipg", "per"; - fsl,clk-source = <0>; + fsl,clk-source = /bits/ 8 <0>; status = "disabled"; }; -- cgit v1.2.3 From aba3a3fb8ebc8672288f287176286d39abcd7515 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:55 +0200 Subject: arm64: dts: freescale: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 10 +++++----- arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +- 4 files changed, 8 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi index 10d2fe091965..6fab73d484b6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi @@ -104,21 +104,21 @@ &dspi { status = "okay"; - dflash0: n25q128a@0 { + dflash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <3000000>; reg = <0>; }; - dflash1: sst25wf040b@1 { + dflash1: flash@1 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; spi-max-frequency = <3000000>; reg = <1>; }; - dflash2: en25s64@2 { + dflash2: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; @@ -129,7 +129,7 @@ &qspi { status = "okay"; - flash0: s25fl256s1@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; @@ -138,7 +138,7 @@ spi-tx-bus-width = <4>; reg = <0>; }; - flash2: s25fl256s1@2 { + flash2: flash@2 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi index 4b71c4fcb35f..f8135c5c252d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi @@ -100,7 +100,7 @@ &dspi { status = "okay"; - dflash0: n25q512a@0 { + dflash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "st,m25p80"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi index 7c4af71baab9..0dbdc9ec3fe5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon.dtsi @@ -98,7 +98,7 @@ pinctrl-1 = <&pinctrl_flexspi1>; status = "okay"; - flash0: spi-flash@0 { + flash0: flash@0 { reg = <0>; #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 22a5ef771d4e..8f90eb02550d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -66,7 +66,7 @@ cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency = <80000000>; reg = <0>; -- cgit v1.2.3 From a00f1fa615803cfe5eeb834fc411ab6c560b1952 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:23 +0200 Subject: arm64: dts: imx8mp: add uart2 dma Add DMA properties to uart2 node. Signed-off-by: Marcel Ziswiler Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 2c207bc27d70..c42d25bd16ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -693,6 +693,8 @@ clocks = <&clk IMX8MP_CLK_UART2_ROOT>, <&clk IMX8MP_CLK_UART2_ROOT>; clock-names = "ipg", "per"; + dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; + dma-names = "rx", "tx"; status = "disabled"; }; -- cgit v1.2.3 From a39ed23bdf6ec7eb0f093b6ef0391e1f3d152f71 Mon Sep 17 00:00:00 2001 From: Marcel Ziswiler Date: Fri, 8 Apr 2022 16:57:25 +0200 Subject: arm64: dts: freescale: add initial support for verdin imx8m plus This patch adds the device tree to support Toradex Verdin iMX8M Plus [1] a computer on module which can be used on different carrier boards. The module consists of an NXP i.MX 8M Plus family SoC (either i.MX 8M Plus Quad or 8M Plus QuadLite), a PCA9450C PMIC, a Gigabit Ethernet PHY, 1, 2, 4 or 8 GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC, an I2C EEPROM, an RX8130 RTC, an optional I2C temperature sensor plus an optional Bluetooth/Wi-Fi module. Anything that is not self-contained on the module is disabled by default. The device tree for the Dahlia includes the module's device tree and enables the supported peripherals of the carrier board. The device tree for the Verdin Development Board includes the module's device tree as well as the Dahlia one as it is a superset and supports almost all peripherals available. So far there is no display functionality supported at all but basic console UART, USB host, eMMC and Ethernet functionality work fine. [1] https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus Signed-off-by: Marcel Ziswiler Reviewed-by: Laurent Pinchart Tested-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 4 + .../boot/dts/freescale/imx8mp-verdin-dahlia.dtsi | 129 ++ .../boot/dts/freescale/imx8mp-verdin-dev.dtsi | 46 + .../dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts | 18 + .../dts/freescale/imx8mp-verdin-nonwifi-dev.dts | 18 + .../boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi | 54 + .../dts/freescale/imx8mp-verdin-wifi-dahlia.dts | 18 + .../boot/dts/freescale/imx8mp-verdin-wifi-dev.dts | 18 + .../boot/dts/freescale/imx8mp-verdin-wifi.dtsi | 82 ++ arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1380 ++++++++++++++++++++ 10 files changed, 1767 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 52ce0f798657..85c2c9ba5110 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -79,6 +79,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-kontron-pitx-imx8m.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi new file mode 100644 index 000000000000..4b8f86f63081 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/* TODO: Audio Codec */ + +&backlight { + power-supply = <®_3p3v>; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + status = "okay"; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin Development board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + status = "okay"; +}; + +/* Current measurement into module VCC */ +&hwmon { + status = "okay"; +}; + +&hwmon_temp { + vs-supply = <®_1p8v>; + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; + + /* TODO: Audio Codec */ +}; + +/* TODO: Verdin PCIE_1 */ + +/* Verdin PWM_1 */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + status = "okay"; +}; + +®_usdhc2_vmmc { + vin-supply = <®_3p3v>; +}; + +/* TODO: Verdin I2S_1 */ + +/* Verdin UART_1 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi new file mode 100644 index 000000000000..cefabe65b252 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + /* TODO: Audio Codec */ + + reg_eth2phy: regulator-eth2phy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio_expander_21 4 GPIO_ACTIVE_HIGH>; /* ETH_PWR_EN */ + off-on-delay = <500000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_ETH"; + startup-delay-us = <200000>; + vin-supply = <®_3p3v>; + }; +}; + +&fec { + phy-supply = <®_eth2phy>; + status = "okay"; +}; + +&gpio_expander_21 { + status = "okay"; + vcc-supply = <®_1p8v>; +}; + +/* TODO: Verdin I2C_1 with Audio Codec */ + +/* Verdin UART_1, connector X50 through RS485 transceiver */ +&uart1 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +}; + +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts new file mode 100644 index 000000000000..68147b0c1b35 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Dahlia Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-dahlia", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts new file mode 100644 index 000000000000..879ff687cf2b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Verdin Development Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-dev", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi new file mode 100644 index 000000000000..91d597391b7c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "SODIMM_164", + "SODIMM_152", + "SODIMM_116", + "SODIMM_128", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_hdmi_hog>; +}; + +/* + * Verdin UART_4 + * Often used by the M7 and then should not be enabled here. + */ +&uart4 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts new file mode 100644 index 000000000000..804567f6ccee --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dahlia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-dahlia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Dahlia Board"; + compatible = "toradex,verdin-imx8mp-wifi-dahlia", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts new file mode 100644 index 000000000000..c1713c28cdce --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-dev.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-dev.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Verdin Development Board"; + compatible = "toradex,verdin-imx8mp-wifi-dev", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi new file mode 100644 index 000000000000..34d9bc48c899 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "PDn_AW-CM276NF"; + startup-delay-us = <2000>; + }; +}; + +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "", + "", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, + <&pinctrl_hdmi_hog>; +}; + +/* On-module Bluetooth */ +&uart4 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + status = "okay"; +}; + +/* On-module Wi-Fi */ +&usdhc1 { + bus-width = <4>; + keep-power-in-suspend; + max-frequency = <100000000>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi new file mode 100644 index 000000000000..aa6442be130e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -0,0 +1,1380 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "imx8mp.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; + + aliases { + /* Ethernet aliases to ensure correct MAC addresses */ + ethernet0 = &eqos; + ethernet1 = &fec; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */ + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>; + power-supply = <®_3p3v>; + /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */ + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + backlight_mezzanine: backlight-mezzanine { + compatible = "pwm-backlight"; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + /* Verdin GPIO 4 (SODIMM 212) */ + enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + /* Verdin PWM_2 (SODIMM 16) */ + pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + debounce-interval = <10>; + /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */ + gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; + label = "Wake-Up"; + linux,code = ; + wakeup-source; + }; + }; + + /* Carrier Board Supplies */ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + reg_5p0v: regulator-5p0v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "+V5_SW"; + }; + + /* Non PMIC On-module Supplies */ + reg_module_eth1phy: regulator-module-eth1phy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */ + off-on-delay = <500000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3_ETH"; + startup-delay-us = <200000>; + vin-supply = <®_vdd_3v3>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_1_EN (SODIMM 155) */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB_2_EN (SODIMM 185) */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_vbus>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "USB_2_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin SD_1_PWR_EN (SODIMM 76) */ + gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>; + off-on-delay = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SD"; + startup-delay-us = <2000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* Use the kernel configuration settings instead */ + /delete-node/ linux,cma; + }; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; +}; + +/* Verdin ETH_1 (On-module PHY) */ +&eqos { + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + phy-supply = <®_module_eth1phy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + snps,force_thresh_dma_mode; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-100tx; + eee-broken-1000t; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <5>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + snps,map-to-dma-channel = <0>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + snps,map-to-dma-channel = <1>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + snps,map-to-dma-channel = <2>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + snps,map-to-dma-channel = <3>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + snps,map-to-dma-channel = <4>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <5>; + snps,tx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue2 { + snps,dcb-algorithm; + snps,priority = <0x4>; + }; + + queue3 { + snps,dcb-algorithm; + snps,priority = <0x8>; + }; + + queue4 { + snps,dcb-algorithm; + snps,priority = <0xf0>; + }; + }; +}; + +/* Verdin ETH_2_RGMII */ +&fec { + fsl,magic-packet; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec>; + pinctrl-1 = <&pinctrl_fec_sleep>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio4>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + + +/* Verdin CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; +}; + +&gpio1 { + gpio-line-names = "SODIMM_206", + "SODIMM_208", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_216", + "SODIMM_218", + "", + "", + "SODIMM_16", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_91"; +}; + +&gpio2 { + gpio-line-names = "", + "", + "", + "", + "", + "", + "SODIMM_143", + "SODIMM_141", + "", + "", + "SODIMM_161", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; + + ctrl-sleep-moci-hog { + gpio-hog; + /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ + gpios = <29 GPIO_ACTIVE_HIGH>; + line-name = "CTRL_SLEEP_MOCI#"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; + }; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "", + "", + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "", + "SODIMM_64", + "", + "", + "SODIMM_34", + "SODIMM_19", + "", + "SODIMM_32", + "", + "", + "SODIMM_30", + "SODIMM_59", + "SODIMM_57", + "SODIMM_63", + "SODIMM_61"; +}; + +&gpio4 { + gpio-line-names = "SODIMM_252", + "SODIMM_222", + "SODIMM_36", + "SODIMM_220", + "SODIMM_193", + "SODIMM_191", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_199", + "SODIMM_197", + "SODIMM_221", + "SODIMM_219", + "SODIMM_217", + "SODIMM_215", + "SODIMM_211", + "SODIMM_213", + "SODIMM_189", + "SODIMM_244", + "SODIMM_38", + "", + "SODIMM_76", + "SODIMM_135", + "SODIMM_133", + "SODIMM_17", + "SODIMM_24", + "SODIMM_26", + "SODIMM_21", + "SODIMM_256", + "SODIMM_48", + "SODIMM_44"; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + interrupt-parent = <&gpio1>; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + /* + * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the + * I2C level shifter for the TLA2024 ADC behind this PMIC. + */ + + regulators { + BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <720000>; + regulator-name = "On-module +VDD_SOC (BUCK1)"; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "On-module +VDD_ARM (BUCK2)"; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3 (BUCK4)"; + }; + + reg_vdd_1v8: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PWR_1V8_MOCI (BUCK5)"; + }; + + BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "On-module +VDD_DDR (BUCK6)"; + }; + + LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "On-module +V1.8_SNVS (LDO1)"; + }; + + LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <800000>; + regulator-name = "On-module +V0.8_SNVS (LDO2)"; + }; + + LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8A (LDO3)"; + }; + + LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "On-module +V3.3_ADC (LDO4)"; + }; + + LDO5 { + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V3.3_1.8_SD (LDO5)"; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + /* On-module temperature sensor */ + hwmon_temp_module: sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + vs-supply = <®_vdd_1v8>; + }; + + adc@49 { + compatible = "ti,ads1015"; + reg = <0x49>; + #address-cells = <1>; + #size-cells = <0>; + + /* Verdin I2C_1 (ADC_4 - ADC_3) */ + channel@0 { + reg = <0>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_4 - ADC_1) */ + channel@1 { + reg = <1>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_3 - ADC_1) */ + channel@2 { + reg = <2>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 (ADC_2 - ADC_1) */ + channel@3 { + reg = <3>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_4 */ + channel@4 { + reg = <4>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_3 */ + channel@5 { + reg = <5>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_2 */ + channel@6 { + reg = <6>; + ti,datarate = <4>; + ti,gain = <2>; + }; + + /* Verdin I2C_1 ADC_1 */ + channel@7 { + reg = <7>; + ti,datarate = <4>; + ti,gain = <2>; + }; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ + clock-frequency = <10000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + atmel_mxt_ts_mezzanine: touch-mezzanine@4a { + compatible = "atmel,maxtouch"; + /* Verdin GPIO_3 (SODIMM 210) */ + interrupt-parent = <&gpio1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reg = <0x4a>; + /* Verdin GPIO_2 (SODIMM 208) */ + reset-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +/* TODO: Verdin I2C_3_HDMI */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + vcc-supply = <®_3p3v>; + status = "disabled"; + }; + + lvds_ti_sn65dsi83: bridge@2c { + compatible = "ti,sn65dsi83"; + /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>; + reg = <0x2c>; + status = "disabled"; + }; + + /* Current measurement into module VCC */ + hwmon: hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "disabled"; + }; + + hdmi_lontium_lt8912: hdmi@48 { + compatible = "lontium,lt8912b"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>; + reg = <0x48>; + /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */ + /* Verdin GPIO_10_DSI (SODIMM 21) */ + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + atmel_mxt_ts: touch@4a { + compatible = "atmel,maxtouch"; + /* + * Verdin GPIO_9_DSI + * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused) + */ + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>; + reg = <0x4a>; + /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */ + reset-gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + /* Temperature sensor on carrier board */ + hwmon_temp: sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + status = "disabled"; + }; + + /* EEPROM on display adapter (MIPI DSI Display Adapter) */ + eeprom_display_adapter: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + status = "disabled"; + }; + + /* EEPROM on carrier board */ + eeprom_carrier_board: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + status = "disabled"; + }; +}; + +/* TODO: Verdin PCIE_1 */ + +/* Verdin PWM_1 */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_2 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; +}; + +/* TODO: Verdin I2S_1 */ + +/* TODO: Verdin I2S_2 */ + +&snvs_pwrkey { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_2 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; +}; + +/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; +}; + +/* Verdin USB_1 */ +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; +}; + +&usb_dwc3_0 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + maximum-speed = "high-speed"; + over-current-active-low; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + srp-disable; +}; + +/* Verdin USB_2 */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; +}; + +&usb_dwc3_1 { + disable-over-current; + dr_mode = "host"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; + assigned-clock-rates = <400000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; + vmmc-supply = <®_usdhc2_vmmc>; +}; + +/* On-module eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl_bt_uart: btuartgrp { + fsl,pins = + , + , + , + ; + }; + + pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { + fsl,pins = + ; /* SODIMM 256 */ + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = + , /* SODIMM 198 */ + , /* SODIMM 200 */ + , /* SODIMM 196 */ + ; /* SODIMM 202 */ + }; + + /* Connection On Board PHY */ + pinctrl_eqos: eqosgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + /* ETH_INT# shared with TPM_INT# (usually N/A) */ + pinctrl_eth_tpm_int: ethtpmintgrp { + fsl,pins = + ; + }; + + /* Connection Carrier Board PHY ETH_2 */ + pinctrl_fec: fecgrp { + fsl,pins = + , /* SODIMM 193 */ + , /* SODIMM 191 */ + , /* SODIMM 201 */ + , /* SODIMM 203 */ + , /* SODIMM 205 */ + , /* SODIMM 207 */ + , /* SODIMM 197 */ + , /* SODIMM 199 */ + , /* SODIMM 221 */ + , /* SODIMM 219 */ + , /* SODIMM 217 */ + , /* SODIMM 215 */ + , /* SODIMM 211 */ + , /* SODIMM 213 */ + ; /* SODIMM 189 */ + }; + + pinctrl_fec_sleep: fecsleepgrp { + fsl,pins = + , /* SODIMM 193 */ + , /* SODIMM 191 */ + , /* SODIMM 201 */ + , /* SODIMM 203 */ + , /* SODIMM 205 */ + , /* SODIMM 207 */ + , /* SODIMM 197 */ + , /* SODIMM 199 */ + , /* SODIMM 221 */ + , /* SODIMM 219 */ + , /* SODIMM 217 */ + , /* SODIMM 215 */ + , /* SODIMM 211 */ + , /* SODIMM 213 */ + ; /* SODIMM 189 */ + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = + , /* SODIMM 22 */ + ; /* SODIMM 20 */ + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = + , /* SODIMM 26 */ + ; /* SODIMM 24 */ + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = + , /* SODIMM 52 */ + , /* SODIMM 54 */ + , /* SODIMM 66 */ + , /* SODIMM 56 */ + , /* SODIMM 58 */ + , /* SODIMM 60 */ + , /* SODIMM 62 */ + ; /* SODIMM 64 */ + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = + ; /* SODIMM 206 */ + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = + ; /* SODIMM 208 */ + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = + ; /* SODIMM 210 */ + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = + ; /* SODIMM 212 */ + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = + ; /* SODIMM 216 */ + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = + ; /* SODIMM 218 */ + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = + ; /* SODIMM 220 */ + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = + ; /* SODIMM 222 */ + }; + + /* Verdin GPIO_9_DSI (pulled-up as active-low) */ + pinctrl_gpio_9_dsi: gpio9dsigrp { + fsl,pins = + ; /* SODIMM 17 */ + }; + + /* Verdin GPIO_10_DSI */ + pinctrl_gpio_10_dsi: gpio10dsigrp { + fsl,pins = + ; /* SODIMM 21 */ + }; + + /* Non-wifi MSP usage only */ + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = + , /* SODIMM 116 */ + , /* SODIMM 152 */ + , /* SODIMM 164 */ + ; /* SODIMM 128 */ + }; + + /* USB_2_OC# */ + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = + ; /* SODIMM 187 */ + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = + , /* SODIMM 157 */ + /* CSI_1_MCLK */ + ; /* SODIMM 91 */ + }; + + /* Wifi usage only */ + pinctrl_gpio_hog4: gpiohog4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = + ; /* SODIMM 252 */ + }; + + pinctrl_hdmi_hog: hdmihoggrp { + fsl,pins = + , /* SODIMM 63 */ + , /* SODIMM 59 */ + , /* SODIMM 57 */ + ; /* SODIMM 61 */ + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = + , /* PMIC_I2C_SCL */ + ; /* PMIC_I2C_SDA */ + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = + , /* SODIMM 55 */ + ; /* SODIMM 53 */ + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = + , /* SODIMM 95 */ + ; /* SODIMM 93 */ + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = + , /* SODIMM 14 */ + ; /* SODIMM 12 */ + }; + + /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ + pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { + fsl,pins = + ; /* SODIMM 42 */ + }; + + /* Verdin I2S_2_D_OUT shared with SAI3 */ + pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { + fsl,pins = + ; /* SODIMM 46 */ + }; + + pinctrl_pcie: pciegrp { + fsl,pins = + , /* SODIMM 244 */ + ; /* PMIC_EN_PCIe_CLK, unused */ + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = + ; /* PMIC_INT# */ + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = + ; /* SODIMM 15 */ + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = + ; /* SODIMM 16 */ + }; + + /* Verdin PWM_3_DSI shared with GPIO3_IO20 */ + pinctrl_pwm_3: pwm3grp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */ + pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp { + fsl,pins = + ; /* SODIMM 19 */ + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = + ; /* PMIC_EN_ETH */ + }; + + pinctrl_sai1: sai1grp { + fsl,pins = + , /* SODIMM 38 */ + , /* SODIMM 36 */ + , /* SODIMM 30 */ + , /* SODIMM 32 */ + ; /* SODIMM 34 */ + }; + + pinctrl_sai3: sai3grp { + fsl,pins = + , /* SODIMM 48 */ + , /* SODIMM 42 */ + , /* SODIMM 46 */ + ; /* SODIMM 44 */ + }; + + pinctrl_uart1: uart1grp { + fsl,pins = + , /* SODIMM 135 */ + , /* SODIMM 133 */ + , /* SODIMM 129 */ + ; /* SODIMM 131 */ + }; + + pinctrl_uart2: uart2grp { + fsl,pins = + , /* SODIMM 143 */ + , /* SODIMM 141 */ + , /* SODIMM 137 */ + ; /* SODIMM 139 */ + }; + + pinctrl_uart3: uart3grp { + fsl,pins = + , /* SODIMM 147 */ + ; /* SODIMM 149 */ + }; + + /* Non-wifi usage only */ + pinctrl_uart4: uart4grp { + fsl,pins = + , /* SODIMM 151 */ + ; /* SODIMM 153 */ + }; + + pinctrl_usb1_vbus: usb1vbusgrp { + fsl,pins = + ; /* SODIMM 155 */ + }; + + /* USB_1_ID */ + pinctrl_usb_1_id: usb1idgrp { + fsl,pins = + ; /* SODIMM 161 */ + }; + + pinctrl_usb2_vbus: usb2vbusgrp { + fsl,pins = + ; /* SODIMM 185 */ + }; + + /* On-module Wi-Fi */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = + ; /* SODIMM 84 */ + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = + ; /* SODIMM 76 */ + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = + , /* PMIC_USDHC_VSELECT */ + , /* SODIMM 78 */ + , /* SODIMM 74 */ + , /* SODIMM 80 */ + , /* SODIMM 82 */ + , /* SODIMM 70 */ + ; /* SODIMM 72 */ + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = + , + , + , + , + , + , + , + , + , + , + , + ; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = + ; /* PMIC_WDI */ + }; + + pinctrl_bluetooth_ctrl: bluetoothctrlgrp { + fsl,pins = + ; /* WIFI_WKUP_BT */ + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = + ; /* WIFI_WKUP_WLAN */ + }; + + pinctrl_wifi_i2s: wifii2sgrp { + fsl,pins = + , /* WIFI_TX_SYNC */ + , /* WIFI_RX_DATA0 */ + , /* WIFI_TX_BCLK */ + ; /* WIFI_TX_DATA0 */ + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = + ; /* PMIC_EN_WIFI */ + }; +}; -- cgit v1.2.3 From bd04437341962d4bff32a8410d69c4ab974c86d1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:47 +0100 Subject: arm64: dts: renesas: r8a779f0: Add I2C nodes Add device nodes for the I2C Bus Interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e1c7fb17801bc82a74aa5364212d02ba51535dd2.1643898884.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 102 ++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index f4e549867371..ab0856b7a2bd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -96,6 +96,108 @@ #power-domain-cells = <1>; }; + i2c0: i2c@e6500000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 518>; + dmas = <&dmac0 0x91>, <&dmac0 0x90>, + <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 519>; + dmas = <&dmac0 0x93>, <&dmac0 0x92>, + <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 520>; + dmas = <&dmac0 0x95>, <&dmac0 0x94>, + <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 521>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 521>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>, + <&dmac1 0x97>, <&dmac1 0x96>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 522>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>, + <&dmac1 0x99>, <&dmac1 0x98>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + compatible = "renesas,i2c-r8a779f0", + "renesas,rcar-gen4-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 523>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, + <&dmac1 0x9b>, <&dmac1 0x9a>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779f0", "renesas,rcar-gen4-scif", "renesas,scif"; -- cgit v1.2.3 From b74d5d65afce4332b2c781c4b252ff9af4885b1f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:48 +0100 Subject: arm64: dts: renesas: spider-cpu: Add I2C4 and EEPROMs Enable the I2C4 bus on the Falcon CPU board, and describe the I2C EEPROMs present on the Spider CPU and BreakOut boards. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/6d8917e49f83b6a932970ca169100eb086d11f16.1643898884.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 20 ++++++++++++++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 9 +++++++++ 2 files changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 6e07c54148e7..41aa8591b3b1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -31,10 +31,30 @@ clock-frequency = <32768>; }; +&i2c4 { + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; + i2c4_pins: i2c4 { + groups = "i2c4"; + function = "i2c4"; + }; + scif3_pins: scif3 { groups = "scif3_data", "scif3_ctrl"; function = "scif3"; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index f286254b41d8..78c4730538fd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -20,3 +20,12 @@ stdout-path = "serial0:115200n8"; }; }; + +&i2c4 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; -- cgit v1.2.3 From 599fdfddc8fcdde92b41444613549ff99cff7adb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 3 Feb 2022 16:26:49 +0100 Subject: arm64: dts: renesas: spider: Add Ethernet sub-board Add a DTS file for the Spider Ether TSN sub-board (RTP8A779F0ASKB0ST0S), and include it from the main r8a779f0-spider.dts. For now its contents are limited to the Board ID EEPROM. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/5aa58816182b34d9e5795bc1e22784f4e4879d13.1643898884.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 1 + 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi new file mode 100644 index 000000000000..15e8d1ebf575 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Spider Ethernet sub-board + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +&i2c4 { + eeprom@52 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "ethernet-sub-board"; + reg = <0x52>; + pagesize = <8>; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts index 78c4730538fd..2e3b719cc749 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r8a779f0-spider-cpu.dtsi" +#include "r8a779f0-spider-ethernet.dtsi" / { model = "Renesas Spider CPU and Breakout boards based on r8a779f0"; -- cgit v1.2.3 From 456733feb0da2dbb1288b9e8f5765df163620c2c Mon Sep 17 00:00:00 2001 From: Christian Hewitt Date: Sat, 9 Apr 2022 06:42:57 +0000 Subject: arm64: dts: meson: alpa sort the board Makefile Let's alpha-sort the board Makefile to keep things organised. Signed-off-by: Christian Hewitt Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20220409064257.24453-1-christianshewitt@gmail.com --- arch/arm64/boot/dts/amlogic/Makefile | 38 ++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 0eec18678311..8773211df50e 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -1,17 +1,18 @@ # SPDX-License-Identifier: GPL-2.0 -dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb dtb-$(CONFIG_ARCH_MESON) += meson-axg-jethome-jethub-j100.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-radxa-zero.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-sei510.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12a-x96-max.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gsking-x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking-pro.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-a311d-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-gtking.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2-plus.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-odroid-n2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-g12b-s922x-khadas-vim3.dtb dtb-$(CONFIG_ARCH_MESON) += meson-g12b-ugoos-am6.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb @@ -19,29 +20,29 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p200.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-p201.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-meta.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-hub.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-wetek-play2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-libretech-ac.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-mecool-kii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-phicomm-n1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-sml5442tw.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-vero4k-plus.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-libretech-pc.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-jethome-jethub-j80.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-hwacom-amazetv.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-khadas-vim.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc-v2.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-libretech-cc.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-nexbox-a95x.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-mecool-kiii-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-minix-neo-u9h.dtb @@ -52,15 +53,14 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxm-rbox-pro.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-libretech-pc.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-vega-s96.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-wetek-core2.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air-gbit.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-a95xf3-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-bananapi-m5.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-h96-max.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-khadas-vim3l.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-c4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-odroid-hc4.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-sei610.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air-gbit.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-a1-ad401.dtb -dtb-$(CONFIG_ARCH_MESON) += meson-s4-s805x2-aq222.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-sm1-x96-air.dtb -- cgit v1.2.3 From f31c834d3976652753f39eb319170c8c4ac3ce55 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 24 Mar 2022 15:33:31 -0700 Subject: arm64: dts: qcom: sc7280: Fix sar1_irq_odl node name This node should be named sar1-irq-odl, not sar0-irq-odl. Otherwise we'll overwrite the settings for sar0 with what is intended for sar1, leading to probe failures for sar1 that are quite confusing. Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Cc: Douglas Anderson Cc: Matthias Kaehlcke Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Tested-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220324223331.876199-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index dc17f2079695..7b8fe20afcea 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -741,7 +741,7 @@ ap_ec_spi: &spi10 { bias-pull-up; }; - sar1_irq_odl: sar0-irq-odl { + sar1_irq_odl: sar1-irq-odl { pins = "gpio140"; function = "gpio"; bias-pull-up; -- cgit v1.2.3 From 70137d1d8a63d5bbb1ad8bf8181299dbc3aab3e7 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 29 Mar 2022 10:59:33 -0700 Subject: arm64: dts: qcom: sc7280: Add SAR sensors for herobrine Add nodes for the two SX9324 SAR proximity sensors. Not all herobrine boards have these sensors, so leave them disabled by default. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220329105854.v3.1.Icedb2e3cd5e21f3a4ec535ddf756fa44d053b6ed@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 37 ++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 7b8fe20afcea..5f00fa2abaf6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -341,6 +341,43 @@ vreg_edp_3p3: &pp3300_left_in_mlb {}; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ +ap_sar_sensor_i2c: &i2c1 { + clock-frequency = <400000>; + status = "disabled"; + + ap_sar_sensor0: proximity@28 { + compatible = "semtech,sx9324"; + reg = <0x28>; + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sar0_irq_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <141 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&pp1800_prox>; + + label = "proximity-wifi-lte0"; + status = "disabled"; + }; + + ap_sar_sensor1: proximity@2c { + compatible = "semtech,sx9324"; + reg = <0x2c>; + #io-channel-cells = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sar1_irq_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <140 IRQ_TYPE_LEVEL_LOW>; + + vdd-supply = <&pp1800_prox>; + + label = "proximity-wifi-lte1"; + status = "disabled"; + }; +}; + ap_i2c_tpm: &i2c14 { status = "okay"; clock-frequency = <400000>; -- cgit v1.2.3 From ee2a621160156000da338280c0b8e45bcfb5db8f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Tue, 29 Mar 2022 10:59:34 -0700 Subject: arm64: dts: qcom: sc7280: Add device tree for herobrine villager Add a basic device tree for the herobrine villager board. Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220329105854.v3.2.Iebdb5af0db7d3d6364cb229a27cd7c668f1063ae@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../boot/dts/qcom/sc7280-herobrine-villager-r0.dts | 296 +++++++++++++++++++++ 2 files changed, 297 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f9e6343acd03..f1b597512352 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts new file mode 100644 index 000000000000..6c2b9a14535a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -0,0 +1,296 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Villager board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Google Villager (rev0+)"; + compatible = "google,villager", "qcom,sc7280"; +}; + +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@2c { + compatible = "hid-over-i2c"; + reg = <0x2c>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + hid-descr-addr = <0x20>; + vcc-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to herobrine board and is named it gets that name. + * - If a pin goes to herobrine board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "SSD_RST_L", + "PE_WAKE_ODL", + "AP_SAR_SDA", + "AP_SAR_SCL", + "PRB_SC_GPIO_6", + "TP_INT_ODL", + "HP_I2C_SDA", + "HP_I2C_SCL", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "SPI_AP_MOSI", + "SPI_AP_MISO", + "SPI_AP_CLK", + "SPI_AP_CS0_L", + /* + * AP_FLASH_WP is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_OD. + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_L", + "", + + "UF_CAM_RST_L", /* 20 */ + "WF_CAM_RST_L", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "PRB_SC_GPIO_32", + "HUB_RST_L", + "", + "", + "AP_SPI_FP_MISO", + "AP_SPI_FP_MOSI", + "AP_SPI_FP_CLK", + "AP_SPI_FP_CS_L", + + "AP_EC_SPI_MISO", /* 40 */ + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "LCM_RST_L", + "EARLY_EUD_N", + "", + "DP_HOT_PLUG_DET", + "IO_BRD_MLB_ID0", + "IO_BRD_MLB_ID1", + + "IO_BRD_MLB_ID2", /* 50 */ + "SSD_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "PRB_SC_GPIO_58", + "PRB_SC_GPIO_59", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "FP_TO_AP_IRQ_L", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "WF_CAM_MCLK", + "PRB_SC_GPIO_67", + "FPMCU_BOOT0", + "UF_CAM_SDA", + + "UF_CAM_SCL", /* 70 */ + "", + "", + "WF_CAM_SDA", + "WF_CAM_SCL", + "", + "", + "EN_FP_RAILS", + "FP_RST_L", + "PCIE1_CLKREQ_ODL", + + "EN_PP3300_DX_EDP", /* 80 */ + "SC_GPIO_81", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CD_ODL", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "HP_MCLK", + "HP_BCLK", + "HP_DOUT", + "HP_DIN", + + "HP_LRCLK", /* 100 */ + "HP_IRQ", + "", + "", + "GSC_AP_INT_ODL", + "EN_PP3300_CODEC", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "PRB_SC_GPIO_112", + "UIM0_DATA", + "UIM0_CLK", + "UIM0_RST", + "UIM0_PRESENT_ODL", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "WF_CAM_EN", + + "FASTBOOT_SEL_0", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "PRB_SC_GPIO_129", + + "LCM_ID0", /* 130 */ + "LCM_ID1", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "PRB_SC_GPIO_139", + + "SAR1_IRQ_ODL", /* 140 */ + "SAR0_IRQ_ODL", + "PRB_SC_GPIO_142", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_ODL", + "HUB_EN", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; -- cgit v1.2.3 From 476dce6e50bb21ec0752d54b6754306e30b3f868 Mon Sep 17 00:00:00 2001 From: Rakesh Pillai Date: Mon, 28 Mar 2022 12:37:01 +0530 Subject: arm64: dts: qcom: sc7280: Add WPSS remoteproc node Add the WPSS remoteproc node in dts for PIL loading. Reviewed-by: Stephen Boyd Signed-off-by: Rakesh Pillai Signed-off-by: Manikanta Pubbisetty Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220328070701.28551-1-quic_mpubbise@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 51 ++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index ecbf2b89d896..069ffbc37bc4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -547,3 +547,7 @@ }; }; +&remoteproc_wpss { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f0b64be63c21..b757e8ad1199 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2842,6 +2842,57 @@ status = "disabled"; }; + remoteproc_wpss: remoteproc@8a00000 { + compatible = "qcom,sc7280-wpss-pil"; + reg = <0 0x08a00000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>, + <&gcc GCC_WPSS_AHB_CLK>, + <&gcc GCC_WPSS_RSCP_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ahb_bdg", "ahb", + "rscp", "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MX>; + power-domain-names = "cx", "mx"; + + memory-region = <&wpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&wpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + resets = <&aoss_reset AOSS_CC_WCSS_RESTART>, + <&pdc_reset PDC_WPSS_SYNC_RESET>; + reset-names = "restart", "pdc_sync"; + + qcom,halt-regs = <&tcsr_mutex 0x37000>; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_WPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + label = "wpss"; + qcom,remote-pid = <13>; + }; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; -- cgit v1.2.3 From 33495eb77ee4ed1850aa70801afd2a24e8d738bd Mon Sep 17 00:00:00 2001 From: Ivy Jian Date: Tue, 22 Mar 2022 09:25:26 +0800 Subject: arm64: dts: qcom: switch panel compatible to "edp-panel" for limozeen some panel can't light up with new board with ps8640, switch compatible panel define to make it workable. Signed-off-by: Pan Sheng-Liang Signed-off-by: Ivy Jian Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220322092524.1.Ied05fc4b996737e3481861c6ab130a706f288412@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index 4e35aec6a1e5..c44ed54af690 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -20,7 +20,7 @@ /delete-node/&ap_ts; &panel { - compatible = "innolux,n116bca-ea1", "innolux,n116bge"; + compatible = "edp-panel"; }; &sdhc_2 { -- cgit v1.2.3 From 737f9ea6cee76fb0004c116479a9db34a67fb814 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:17 -0700 Subject: arm64: dts: qcom: sc7280: Rename crd to crd-r3 There are multiple revisions of CRD boards. The current sc7280-crd.dts describes revision 3 and 4 (aka CRD 1.0 and 2.0). Support for a newer version will be added by another patch. Add the revision number to distinguish it from the versionn. Also add the revision numbers to the compatible string. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.1.I2deda8f2cd6adfbb525a97d8fee008a8477b7b0e@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 +- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 105 +++++++++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-crd.dts | 105 ----------------------------- 3 files changed, 106 insertions(+), 106 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-crd.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index f1b597512352..d91fdae81487 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -88,7 +88,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts new file mode 100644 index 000000000000..7a028b9248c3 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * sc7280 CRD board device tree source + * + * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "sc7280-idp.dtsi" +#include "sc7280-idp-ec-h1.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; + compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; + + aliases { + serial0 = &uart5; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&vreg_l18b_1p8>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&vreg_l19b_1p8>; + }; +}; + +&nvme_3v3_regulator { + gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; +}; + +&nvme_pwren { + pins = "gpio51"; +}; + +&tlmm { + tp_int_odl: tp-int-odl { + pins = "gpio7"; + function = "gpio"; + bias-disable; + }; + + ts_int_l: ts-int-l { + pins = "gpio55"; + function = "gpio"; + bias-pull-up; + }; + + ts_reset_l: ts-reset-l { + pins = "gpio54"; + function = "gpio"; + bias-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-crd.dts deleted file mode 100644 index e2efbdde53a3..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-crd.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * sc7280 CRD board device tree source - * - * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved. - */ - -/dts-v1/; - -#include "sc7280-idp.dtsi" -#include "sc7280-idp-ec-h1.dtsi" - -/ { - model = "Qualcomm Technologies, Inc. sc7280 CRD platform"; - compatible = "qcom,sc7280-crd", "google,hoglin", "qcom,sc7280"; - - aliases { - serial0 = &uart5; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; -}; - -&apps_rsc { - pmg1110-regulators { - compatible = "qcom,pmg1110-rpmh-regulators"; - qcom,pmic-id = "k"; - - vreg_s1k_1p0: smps1 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; - }; -}; - -ap_tp_i2c: &i2c0 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@15 { - compatible = "hid-over-i2c"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <7 IRQ_TYPE_EDGE_FALLING>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - vdd-supply = <&vreg_l18b_1p8>; - - wakeup-source; - }; -}; - -ap_ts_pen_1v8: &i2c13 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@5c { - compatible = "hid-over-i2c"; - reg = <0x5c>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <55 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <500>; - hid-descr-addr = <0x0000>; - - vdd-supply = <&vreg_l19b_1p8>; - }; -}; - -&nvme_3v3_regulator { - gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; -}; - -&nvme_pwren { - pins = "gpio51"; -}; - -&tlmm { - tp_int_odl: tp-int-odl { - pins = "gpio7"; - function = "gpio"; - bias-disable; - }; - - ts_int_l: ts-int-l { - pins = "gpio55"; - function = "gpio"; - bias-pull-up; - }; - - ts_reset_l: ts-reset-l { - pins = "gpio54"; - function = "gpio"; - bias-disable; - }; -}; -- cgit v1.2.3 From f226c660533416c308fcde62d1b785527528974d Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:18 -0700 Subject: arm64: dts: qcom: sc7280: Add 'piglin' to the crd-r3 compatible strings With newer bootloader versions the crd-r3 (aka CRD 1.0 and 2.0) is identified as a 'piglin' board (like the IDP2 board), instead of 'hoglin' Add the compatible strings 'google,piglin-rev{3,4}'. The hoglin entries are kept to make sure the board keeps booting with older bootloader versions. The compatible string 'google,piglin' (without revision information) is still used by the IDP2 board, which is not expected to evolve further. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.2.Ib0fbb7e5218201c81a2d064ff13c9bc1b0863212@changeid --- arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts index 7a028b9248c3..344338ad8a01 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts @@ -12,7 +12,10 @@ / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev3 - 4)"; - compatible = "qcom,sc7280-crd", "google,hoglin-rev3", "google,hoglin-rev4", "qcom,sc7280"; + compatible = "qcom,sc7280-crd", + "google,hoglin-rev3", "google,hoglin-rev4", + "google,piglin-rev3", "google,piglin-rev4", + "qcom,sc7280"; aliases { serial0 = &uart5; -- cgit v1.2.3 From 533ca1c3c1996ea49a1b31a83ba978f2f96fea9b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:19 -0700 Subject: arm64: dts: qcom: sc7280: herobrine: disable some regulators by default Not all herobrine boards have a world facing camera or a fingerprint sensor, disable the regulators that feed these devices by default and only enable them for the boards that use them. Similarly the audio configuration can vary between boards, not all boards have the regulator pp3300_codec, disable it by default. Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.3.Iad21bd53f3ac14956b8dbbf3825fc7ab29abdf97@changeid --- .../dts/qcom/sc7280-herobrine-herobrine-r1.dts | 30 ++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 6 +++++ 2 files changed, 36 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index f95273052da0..29c4ca095294 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -14,6 +14,36 @@ compatible = "google,herobrine", "qcom,sc7280"; }; +/* + * ADDITIONS TO FIXED REGULATORS DEFINED IN PARENT DEVICE TREE FILES + * + * Sort order matches the order in the parent files (parents before children). + */ + +&pp3300_codec { + status = "okay"; +}; + +&pp3300_fp_mcu { + status = "okay"; +}; + +&pp2850_vcm_wf_cam { + status = "okay"; +}; + +&pp2850_wf_cam { + status = "okay"; +}; + +&pp1800_wf_cam { + status = "okay"; +}; + +&pp1200_wf_cam { + status = "okay"; +}; + /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ &ap_spi_fp { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 5f00fa2abaf6..d57ea4881fa1 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -92,6 +92,7 @@ pinctrl-0 = <&en_pp3300_codec>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_left_in_mlb: pp3300-left-in-mlb-regulator { @@ -132,6 +133,7 @@ pinctrl-0 = <&en_fp_rails>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp3300_hub: pp3300-hub-regulator { @@ -194,6 +196,7 @@ pinctrl-0 = <&wf_cam_en>; vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp2850_wf_cam: pp2850-wf-cam-regulator { @@ -214,6 +217,7 @@ */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; pp1800_fp: pp1800-fp-regulator { @@ -258,6 +262,7 @@ */ vin-supply = <&vreg_l19b_s0>; + status = "disabled"; }; pp1200_wf_cam: pp1200-wf-cam-regulator { @@ -278,6 +283,7 @@ */ vin-supply = <&pp3300_z1>; + status = "disabled"; }; /* BOARD-SPECIFIC TOP LEVEL NODES */ -- cgit v1.2.3 From 6675ac9d0046201af945c7abfe5dd794df22230b Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Wed, 16 Mar 2022 17:28:20 -0700 Subject: arm64: dts: qcom: sc7280: Add CRD rev5 Add support for Qualcomm's SC7280 CRD rev5 (aka CRD 3.0/3.1). Signed-off-by: Matthias Kaehlcke Reviewed-by: Rajendra Nayak Reviewed-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220316172814.v1.4.I37bdb77fdd06fb4143056366d7ec35b929528002@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 313 ++++++++++++++++++++++ 2 files changed, 314 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d91fdae81487..512084804439 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts new file mode 100644 index 000000000000..fd6eadc8581a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -0,0 +1,313 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sc7280 CRD 3+ board device tree source + * + * Copyright 2022 Google LLC. + */ + +/dts-v1/; + +#include "sc7280-herobrine.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; + compatible = "google,hoglin", "qcom,sc7280"; +}; + +/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ + +&apps_rsc { + pmg1110-regulators { + compatible = "qcom,pmg1110-rpmh-regulators"; + qcom,pmic-id = "k"; + + vreg_s1k_1p0: smps1 { + regulator-min-microvolt = <1010000>; + regulator-max-microvolt = <1170000>; + }; + }; +}; + +ap_tp_i2c: &i2c0 { + status = "okay"; + clock-frequency = <400000>; + + trackpad: trackpad@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + pinctrl-names = "default"; + pinctrl-0 = <&tp_int_odl>; + + interrupt-parent = <&tlmm>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + + post-power-on-delay-ms = <20>; + hid-descr-addr = <0x0001>; + vdd-supply = <&pp3300_z1>; + + wakeup-source; + }; +}; + +ap_ts_pen_1v8: &i2c13 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@5c { + compatible = "hid-over-i2c"; + reg = <0x5c>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>; + + interrupt-parent = <&tlmm>; + interrupts = <55 IRQ_TYPE_LEVEL_LOW>; + + post-power-on-delay-ms = <500>; + hid-descr-addr = <0x0000>; + + vdd-supply = <&pp3300_left_in_mlb>; + }; +}; + +/* For nvme */ +&pcie1 { + status = "okay"; +}; + +/* For nvme */ +&pcie1_phy { + status = "okay"; +}; + +/* For eMMC */ +&sdhc_1 { + status = "okay"; +}; + +/* For SD Card */ +&sdhc_2 { + status = "okay"; +}; + +/* PINCTRL - BOARD-SPECIFIC */ + +/* + * Methodology for gpio-line-names: + * - If a pin goes to CRD board and is named it gets that name. + * - If a pin goes to CRD board and is not named, it gets no name. + * - If a pin is totally internal to Qcard then it gets Qcard name. + * - If a pin is not hooked up on Qcard, it gets no name. + */ + +&pm8350c_gpios { + gpio-line-names = "FLASH_STROBE_1", /* 1 */ + "AP_SUSPEND", + "PM8008_1_RST_N", + "", + "", + "EDP_BL_REG_EN", + "PMIC_EDP_BL_EN", + "PMIC_EDP_BL_PWM", + ""; +}; + +&tlmm { + gpio-line-names = "AP_TP_I2C_SDA", /* 0 */ + "AP_TP_I2C_SCL", + "PCIE1_RESET_N", + "PCIE1_WAKE_N", + "APPS_I2C_SDA", + "APPS_I2C_SCL", + "", + "TPAD_INT_N", + "", + "", + + "GNSS_L1_EN", /* 10 */ + "GNSS_L5_EN", + "QSPI_DATA_0", + "QSPI_DATA_1", + "QSPI_CLK", + "QSPI_CS_N_1", + /* + * AP_FLASH_WP is crossystem ABI. Schematics call it + * BIOS_FLASH_WP_L (the '_L' suffix is misleading, the + * signal is active high). + */ + "AP_FLASH_WP", + "", + "AP_EC_INT_N", + "", + + "CAM0_RST_N", /* 20 */ + "CAM1_RST_N", + "SM_DBG_UART_TX", + "SM_DBG_UART_RX", + "", + "PM8008_IRQ_1", + "HOST2WLAN_SOL", + "WLAN2HOST_SOL", + "MOS_BT_UART_CTS", + "MOS_BT_UART_RFR", + + "MOS_BT_UART_TX", /* 30 */ + "MOS_BT_UART_RX", + "", + "HUB_RST", + "", + "", + "", + "", + "", + "", + + "EC_SPI_MISO_GPIO40", /* 40 */ + "EC_SPI_MOSI_GPIO41", + "EC_SPI_CLK_GPIO42", + "EC_SPI_CS_GPIO43", + "", + "EARLY_EUD_EN", + "", + "DP_HOT_PLUG_DETECT", + "AP_BRD_ID_0", + "AP_BRD_ID_1", + + "AP_BRD_ID_2", /* 50 */ + "NVME_PWR_REG_EN", + "TS_I2C_SDA_CONN", + "TS_I2C_CLK_CONN", + "TS_RST_CONN", + "TS_INT_CONN", + "AP_I2C_TPM_SDA", + "AP_I2C_TPM_SCL", + "", + "", + + "EDP_HOT_PLUG_DET_N", /* 60 */ + "", + "", + "AMP_EN", + "CAM0_MCLK_GPIO_64", + "CAM1_MCLK_GPIO_65", + "", + "", + "", + "CCI_I2C_SDA0", + + "CCI_I2C_SCL0", /* 70 */ + "", + "", + "", + "", + "", + "", + "", + "", + "PCIE1_CLK_REQ_N", + + "EN_PP3300_DX_EDP", /* 80 */ + "US_EURO_HS_SEL", + "FORCED_USB_BOOT", + "WCD_RESET_N", + "MOS_WLAN_EN", + "MOS_BT_EN", + "MOS_SW_CTRL", + "MOS_PCIE0_RST", + "MOS_PCIE0_CLKREQ_N", + "MOS_PCIE0_WAKE_N", + + "MOS_LAA_AS_EN", /* 90 */ + "SD_CARD_DET_CONN", + "", + "", + "MOS_BT_WLAN_SLIMBUS_CLK", + "MOS_BT_WLAN_SLIMBUS_DAT0", + "", + "", + "", + "", + + "", /* 100 */ + "", + "", + "", + "H1_AP_INT_N", + "", + "AMP_BCLK", + "AMP_DIN", + "AMP_LRCLK", + "UIM1_DATA_GPIO_109", + + "UIM1_CLK_GPIO_110", /* 110 */ + "UIM1_RESET_GPIO_111", + "", + "UIM1_DATA", + "UIM1_CLK", + "UIM1_RESET", + "UIM1_PRESENT", + "SDM_RFFE0_CLK", + "SDM_RFFE0_DATA", + "", + + "SDM_RFFE1_DATA", /* 120 */ + "SC_GPIO_121", + "FASTBOOT_SEL_1", + "SC_GPIO_123", + "FASTBOOT_SEL_2", + "SM_RFFE4_CLK_GRFC_8", + "SM_RFFE4_DATA_GRFC_9", + "WLAN_COEX_UART1_RX", + "WLAN_COEX_UART1_TX", + "", + + "", /* 130 */ + "", + "", + "SDR_QLINK_REQ", + "SDR_QLINK_EN", + "QLINK0_WMSS_RESET_N", + "SMR526_QLINK1_REQ", + "SMR526_QLINK1_EN", + "SMR526_QLINK1_WMSS_RESET_N", + "", + + "SAR1_INT_N", /* 140 */ + "SAR0_INT_N", + "", + "", + "WCD_SWR_TX_CLK", + "WCD_SWR_TX_DATA0", + "WCD_SWR_TX_DATA1", + "WCD_SWR_RX_CLK", + "WCD_SWR_RX_DATA0", + "WCD_SWR_RX_DATA1", + + "DMIC01_CLK", /* 150 */ + "DMIC01_DATA", + "DMIC23_CLK", + "DMIC23_DATA", + "", + "", + "EC_IN_RW_N", + "EN_PP3300_HUB", + "WCD_SWR_TX_DATA2", + "", + + "", /* 160 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + + "", /* 170 */ + "MOS_BLE_UART_TX", + "MOS_BLE_UART_RX", + "", + "", + ""; +}; -- cgit v1.2.3 From 0d40497d054194768b3ddbf3a676d481b38b96eb Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 10 Mar 2022 13:04:34 -0800 Subject: arm64: dts: qcom: sc7280-herobrine: Fix PCIe regulator glitch at bootup While scoping signals, we found that the PCIe signals weren't compliant at bootup. Specifically, the bootloader was setting up PCIe and leaving it configured, then jumping to the kernel. The kernel was turning off the regulator while leaving the PCIe clock running, which was a violation. In the regulator bindings (and the Linux kernel driver that uses them), there's currently no way to specify that a GPIO-controlled regulator should keep its state at bootup. You've got to pick either "on" or "off". Let's switch it so that the PCIe regulator defaults to "on" instead of "off". This should be a much safer way to go and avoids the timing violation. The regulator will still be turned off later if there are no users. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220310130429.1.Id41fda1d7f5d9230bc45c1b85b06b0fb0ddd29af@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d57ea4881fa1..3d9b870d440b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -180,6 +180,13 @@ pinctrl-names = "default"; pinctrl-0 = <&ssd_en>; + /* + * The bootloaer may have left PCIe configured. Powering this + * off while the PCIe clocks are still running isn't great, + * so it's better to default to this regulator being on. + */ + regulator-boot-on; + vin-supply = <&pp3300_z1>; }; -- cgit v1.2.3 From 9464b00e6a118b2712092d453b07ec835deb327f Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 8 Mar 2022 12:52:35 -0800 Subject: arm64: dts: qcom: sc7280: Delete herobrine-r0 As talked about in commit 61a6262f95e0 ("arm64: dts: qcom: sc7280: Move herobrine-r0 to its own dts"), herobrine evolved pretty significantly after -r0 and newer revisions are pretty different. Nobody needs the old boards to keep working, so let's delete to avoid the maintenance burden. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220308125044.1.I3e4a1a9c102d194698b68661e69efebafec8af1c@changeid --- arch/arm64/boot/dts/qcom/Makefile | 1 - .../dts/qcom/sc7280-herobrine-herobrine-r0.dts | 1352 -------------------- 2 files changed, 1353 deletions(-) delete mode 100644 arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 512084804439..2f8aec2cc6db 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -84,7 +84,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-crd.dtb -dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-villager-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts deleted file mode 100644 index 1779d96c30f6..000000000000 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts +++ /dev/null @@ -1,1352 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Google Herobrine board device tree source - * - * Copyright 2021 Google LLC. - */ - -/dts-v1/; - -#include -#include -#include -#include -#include -#include - -#include "sc7280.dtsi" - -/* PMICs depend on spmi_bus label and so must come after SoC */ -#include "pm7325.dtsi" -#include "pm8350c.dtsi" -#include "pmk8350.dtsi" - -#include "sc7280-chrome-common.dtsi" - -/ { - model = "Google Herobrine (rev0)"; - compatible = "google,herobrine-rev0", "qcom,sc7280"; -}; - -/ { - aliases { - serial0 = &uart5; - serial1 = &uart7; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - /* FIXED REGULATORS - parents above children */ - - /* This is the top level supply and variable voltage */ - ppvar_sys: ppvar-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "ppvar_sys"; - regulator-always-on; - regulator-boot-on; - }; - - /* This divides ppvar_sys by 2, so voltage is variable */ - src_vph_pwr: src-vph-pwr-regulator { - compatible = "regulator-fixed"; - regulator-name = "src_vph_pwr"; - - /* EC turns on with switchcap_on; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&ppvar_sys>; - }; - - pp5000_s3: pp5000-s3-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp5000_s3"; - - /* EC turns on with en_pp5000_s3; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_z1: pp3300-z1-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_z1"; - - /* EC turns on with en_pp3300_z1; always on for AP */ - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - vin-supply = <&ppvar_sys>; - }; - - pp3300_audio: - pp3300_codec: pp3300-codec-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_codec"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_codec>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_cam: - pp3300_edp: - pp3300_ts: pp3300-edp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_edp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_dx_edp>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_fp: - pp3300_fp_ls: - pp3300_mcu: pp3300-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_fp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_hub: pp3300-hub-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_hub"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - regulator-boot-on; - regulator-always-on; - - gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&en_pp3300_hub>; - - vin-supply = <&pp3300_z1>; - }; - - pp3300_tp: pp3300-tp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp3300_tp"; - - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - /* AP turns on with PP1800_L18B_S0; always on for AP */ - regulator-always-on; - regulator-boot-on; - - vin-supply = <&pp3300_z1>; - }; - - pp2850_uf_cam: pp2850-uf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_uf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&uf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_vcm_wf_cam: pp2850-vcm-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_vcm_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&wf_cam_en>; - - vin-supply = <&pp3300_cam>; - }; - - pp2850_wf_cam: pp2850-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp2850_wf_cam"; - - regulator-min-microvolt = <2850000>; - regulator-max-microvolt = <2850000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp3300_cam>; - }; - - pp1800_fp: pp1800-fp-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_fp"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - regulator-boot-on; - regulator-always-on; - - /* - * WARNING: it is intentional that GPIO 42 isn't listed here. - * The userspace script for updating the fingerprint firmware - * needs to control the FP regulators during a FW update, - * hence the signal can't be owned by the kernel regulator. - */ - - pinctrl-names = "default"; - pinctrl-0 = <&en_fp_rails>; - - vin-supply = <&pp1800_l18b_s0>; - status = "disabled"; - }; - - pp1800_uf_cam: pp1800-uf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_uf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&uf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1800_wf_cam: pp1800-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1800_wf_cam"; - - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1800_l19b>; - }; - - pp1200_wf_cam: pp1200-wf-cam-regulator { - compatible = "regulator-fixed"; - regulator-name = "pp1200_wf_cam"; - - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - - gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - /* - * The pinconf can only be referenced once so we put it on the - * first regulator and comment it out here. - * - * pinctrl-names = "default"; - * pinctrl-0 = <&wf_cam_en>; - */ - - vin-supply = <&pp1200_l6b>; - }; - - /* BOARD-SPECIFIC TOP LEVEL NODES */ - - gpio_keys: gpio-keys { - compatible = "gpio-keys"; - status = "disabled"; - pinctrl-names = "default"; - pinctrl-0 = <&pen_pdct_l>; - - pen_insert: pen-insert { - label = "Pen Insert"; - - /* Insert = low, eject = high */ - gpios = <&tlmm 39 GPIO_ACTIVE_LOW>; - linux,code = ; - linux,input-type = ; - wakeup-event-action = ; - wakeup-source; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - status = "disabled"; - keyboard_backlight: keyboard-backlight { - status = "disabled"; - label = "cros_ec::kbd_backlight"; - pwms = <&cros_ec_pwm 0>; - max-brightness = <1023>; - }; - }; -}; - -&apps_rsc { - pm7325-regulators { - compatible = "qcom,pm7325-rpmh-regulators"; - qcom,pmic-id = "b"; - - vdd19_pmu_pcie_i: - vdd19_pmu_rfa_i: - vreg_s1b_wlan: - vreg_s1b: smps1 { - regulator-min-microvolt = <1856000>; - regulator-max-microvolt = <2040000>; - }; - - vdd_pmu_aon_i: - vreg_s7b_wlan: - vreg_s7b: smps7 { - regulator-min-microvolt = <535000>; - regulator-max-microvolt = <1120000>; - }; - - vdd13_pmu_pcie_i: - vdd13_pmu_rfa_i: - vreg_s8b_wlan: - vreg_s8b: smps8 { - regulator-min-microvolt = <1256000>; - regulator-max-microvolt = <1500000>; - }; - - vdda_usb_ss_dp_core: - vreg_l1b: ldo1 { - regulator-min-microvolt = <825000>; - regulator-max-microvolt = <925000>; - regulator-initial-mode = ; - }; - - vdda_usb_hs0_3p1: - vreg_l2b: ldo2 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1200_l6b: - vdd_ufs_1p2: - vdd_vref: - vdda_csi01_1p2: - vdda_csi23_1p2: - vdda_csi4_1p2: - vdda_dsi0_1p2: - vdda_pcie0_1p2: - vdda_pcie1_1p2: - vdda_usb_ss_dp_1p2: - vdda_qlink0_1p2_ck: - vdda_qlink1_1p2_ck: - vreg_l6b_1p2: - vreg_l6b: ldo6 { - regulator-min-microvolt = <1120000>; - regulator-max-microvolt = <1408000>; - regulator-initial-mode = ; - }; - - pp2950_l7b: - vreg_l7b: ldo7 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - codec_vcc: - pp1800_l18b_s0: - pp1800_ts: - vdd1: - vddpx_0: - vddpx_3: - vddpx_7: - vreg_l18b: ldo18 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp1800_l19b: - vddpx_ts: - vddpx_wl4otp: - vreg_l19b: ldo19 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-initial-mode = ; - }; - }; - - pm8350c-regulators { - compatible = "qcom,pm8350c-rpmh-regulators"; - qcom,pmic-id = "c"; - - vreg_s1c: smps1 { - regulator-min-microvolt = <2190000>; - regulator-max-microvolt = <2210000>; - }; - - vddpx_1: - vreg_s9c: smps9 { - regulator-min-microvolt = <1010000>; - regulator-max-microvolt = <1170000>; - }; - - pp1800_l1c: - pp1800_pen: - vdd_a_gfx_cs_1p1: - vdd_a_cxo_1p8: - vdd_qfprom: - vdda_apc_cs_1p8: - vdda_qrefs_1p8: - vdda_turing_q6_cs_1p8: - vdda_usb_hs0_1p8: - vreg_l1c: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - dmic_vdd: - pp1800_alc5682: - pp1800_l2c: - pp1800_vreg_alc5682: - vreg_l2c: ldo2 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <1980000>; - regulator-initial-mode = ; - }; - - pp3300_sar: - pp3300_sensor: - vreg_l3c: ldo3 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3540000>; - regulator-initial-mode = ; - }; - - ppvar_uim1: - vddpx_5: - vreg_l4c: ldo4 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - pp2950_l5c: - uim_vcc: - vddpx_6: - vreg_l5c: ldo5 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <3300000>; - regulator-initial-mode = ; - }; - - ppvar_l6c: - vddpx_2: - vreg_l6c: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <2950000>; - regulator-initial-mode = ; - }; - - vreg_l7c: ldo7 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_prox: - pp1800_sar: - vreg_l8c: ldo8 { - regulator-min-microvolt = <1620000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp2950_l9c: - vreg_l9c: ldo9 { - regulator-min-microvolt = <2960000>; - regulator-max-microvolt = <2960000>; - regulator-initial-mode = ; - }; - - vdd_a_gnss_0p9: - vdd_ufs_core: - vdd_usb_hs0_core: - vdd_vref_0p9: - vdda_csi01_0p9: - vdda_csi23_0p9: - vdda_csi4_0p9: - vdda_dsi0_pll_0p9: - vdda_dsi0_0p9: - vdda_pcie0_core: - vdda_pcie1_core: - vdda_qlink0_0p9: - vdda_qlink1_0p9: - vdda_qlink0_0p9_ck: - vdda_qlink1_0p9_ck: - vdda_qrefs_0p875: - vreg_l10c_0p8: - vreg_l10c: ldo10 { - regulator-min-microvolt = <720000>; - regulator-max-microvolt = <1050000>; - regulator-initial-mode = ; - }; - - pp2800_l11c: - vreg_l11c: ldo11 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - pp1800_l12c: - vreg_l12c: ldo12 { - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <2000000>; - regulator-initial-mode = ; - }; - - pp3300_l13c: - vreg_l13c: ldo13 { - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - regulator-initial-mode = ; - }; - - vreg_bob: bob { - regulator-min-microvolt = <3008000>; - regulator-max-microvolt = <3960000>; - regulator-initial-mode = ; - }; - }; -}; - -ap_tp_i2c: &i2c1 { - status = "okay"; - clock-frequency = <400000>; - - trackpad: trackpad@15 { - compatible = "elan,ekth3000"; - reg = <0x15>; - pinctrl-names = "default"; - pinctrl-0 = <&tp_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <102 IRQ_TYPE_EDGE_FALLING>; - - vcc-supply = <&pp3300_z1>; - - wakeup-source; - }; -}; - -ap_h1_i2c: &i2c12 { - status = "okay"; - clock-frequency = <400000>; - - tpm@50 { - compatible = "google,cr50"; - reg = <0x50>; - - pinctrl-names = "default"; - pinctrl-0 = <&h1_ap_int_odl>; - - interrupt-parent = <&tlmm>; - interrupts = <54 IRQ_TYPE_EDGE_RISING>; - }; -}; - -ap_ts_pen: &i2c13 { - status = "okay"; - clock-frequency = <400000>; - - ap_ts: touchscreen@10 { - compatible = "hid-over-i2c"; - reg = <0x10>; - pinctrl-names = "default"; - pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; - - interrupt-parent = <&tlmm>; - interrupts = <81 IRQ_TYPE_LEVEL_LOW>; - - post-power-on-delay-ms = <20>; - hid-descr-addr = <0x0001>; - - vdd-supply = <&pp3300_ts>; - }; -}; - -&pm7325_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_gpios { - status = "disabled"; /* No GPIOs are connected */ -}; - -&pmk8350_rtc { - status = "disabled"; -}; - -&pmk8350_vadc { - pmk8350_die_temp { - reg = ; - label = "pmk8350_die_temp"; - qcom,pre-scaling = <1 1>; - }; - - pmr735a_die_temp { - reg = ; - label = "pmr735a_die_temp"; - qcom,pre-scaling = <1 1>; - }; -}; - -&qfprom { - vcc-supply = <&vdd_qfprom>; -}; - -&qupv3_id_0 { - status = "okay"; -}; - -&qupv3_id_1 { - status = "okay"; -}; - -&sdhc_1 { - status = "okay"; - - vmmc-supply = <&pp2950_l7b>; - vqmmc-supply = <&pp1800_l19b>; -}; - -&sdhc_2 { - status = "okay"; - - pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>; - pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>; - vmmc-supply = <&pp2950_l9c>; - vqmmc-supply = <&ppvar_l6c>; - - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; -}; - -ap_ec_spi: &spi8 { - status = "okay"; - - pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs_gpio_init_high>, <&qup_spi8_cs_gpio>; - cs-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; - - cros_ec: ec@0 { - compatible = "google,cros-ec-spi"; - reg = <0>; - interrupt-parent = <&tlmm>; - interrupts = <142 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&ap_ec_int_l>; - spi-max-frequency = <3000000>; - - cros_ec_pwm: pwm { - compatible = "google,cros-ec-pwm"; - #pwm-cells = <1>; - }; - - i2c_tunnel: i2c-tunnel { - compatible = "google,cros-ec-i2c-tunnel"; - google,remote-bus = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - typec { - compatible = "google,cros-ec-typec"; - #address-cells = <1>; - #size-cells = <0>; - - usb_c0: connector@0 { - compatible = "usb-c-connector"; - reg = <0>; - label = "left"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - - usb_c1: connector@1 { - compatible = "usb-c-connector"; - reg = <1>; - label = "right"; - power-role = "dual"; - data-role = "host"; - try-power-role = "source"; - }; - }; - }; -}; - -#include -#include - -&keyboard_controller { - function-row-physmap = < - MATRIX_KEY(0x00, 0x02, 0) /* T1 */ - MATRIX_KEY(0x03, 0x02, 0) /* T2 */ - MATRIX_KEY(0x02, 0x02, 0) /* T3 */ - MATRIX_KEY(0x01, 0x02, 0) /* T4 */ - MATRIX_KEY(0x03, 0x04, 0) /* T5 */ - MATRIX_KEY(0x02, 0x04, 0) /* T6 */ - MATRIX_KEY(0x01, 0x04, 0) /* T7 */ - MATRIX_KEY(0x02, 0x09, 0) /* T8 */ - MATRIX_KEY(0x01, 0x09, 0) /* T9 */ - MATRIX_KEY(0x00, 0x04, 0) /* T10 */ - >; - linux,keymap = < - MATRIX_KEY(0x00, 0x02, KEY_BACK) - MATRIX_KEY(0x03, 0x02, KEY_REFRESH) - MATRIX_KEY(0x02, 0x02, KEY_ZOOM) - MATRIX_KEY(0x01, 0x02, KEY_SCALE) - MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) - MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) - MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) - MATRIX_KEY(0x02, 0x09, KEY_MUTE) - MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) - MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) - - CROS_STD_MAIN_KEYMAP - >; -}; - -&uart5 { - compatible = "qcom,geni-debug-uart"; - status = "okay"; -}; - -&uart7 { - status = "okay"; -}; - -&usb_1 { - status = "okay"; -}; - -&usb_1_dwc3 { - dr_mode = "host"; -}; - -&usb_1_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -&usb_1_qmpphy { - status = "okay"; - - vdda-phy-supply = <&vdda_usb_ss_dp_1p2>; - vdda-pll-supply = <&vdda_usb_ss_dp_core>; -}; - -&usb_2 { - status = "okay"; -}; - -&usb_2_dwc3 { - dr_mode = "host"; -}; - -&usb_2_hsphy { - status = "okay"; - - vdda-pll-supply = <&vdd_usb_hs0_core>; - vdda33-supply = <&vdda_usb_hs0_3p1>; - vdda18-supply = <&vdda_usb_hs0_1p8>; -}; - -/* PINCTRL - additions to nodes defined in sc7280.dtsi */ - -&dp_hot_plug_det { - bias-disable; -}; - -&pcie1_clkreq_n { - bias-pull-up; - drive-strength = <2>; -}; - -&qspi_cs0 { - bias-disable; -}; - -&qspi_clk { - bias-disable; -}; - -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; -}; - -&qup_uart5_rx { - drive-strength = <2>; - bias-pull-up; -}; - -&qup_uart5_tx { - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_cts { - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; -}; - -&qup_uart7_rts { - /* We'll drive RTS, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_tx { - /* We'll drive TX, so no pull */ - drive-strength = <2>; - bias-disable; -}; - -&qup_uart7_rx { - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module is - * in tri-state (module powered off or not driving the - * signal yet). - */ - bias-pull-up; -}; - -&sdc1_clk { - bias-disable; - drive-strength = <16>; -}; - -&sdc1_cmd { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc1_data { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc1_rclk { - bias-pull-down; -}; - -&sdc2_clk { - bias-disable; - drive-strength = <16>; -}; - -&sdc2_cmd { - bias-pull-up; - drive-strength = <10>; -}; - -&sdc2_data { - bias-pull-up; - drive-strength = <10>; -}; - -/* PINCTRL - board-specific pinctrl */ - -&pm8350c_gpios { - gpio-line-names = "AP_SUSPEND", - "", - "", - "AP_BL_EN", - "", - "SD_CD_ODL", - "", - "", - "AP_BL_PWM"; - - ap_bl_en: ap-bl-en { - pins = "gpio4"; - function = "normal"; - qcom,drive-strength = ; - bias-disable; - - /* Force backlight to be disabled to match state at boot. */ - output-low; - }; -}; - -&tlmm { - gpio-line-names = "HP_I2C_SDA", /* 0 */ - "HP_I2C_SCL", - "SSD_RST_L", - "PE_WAKE_ODL", - "AP_TP_I2C_SDA", - "AP_TP_I2C_SCL", - "UF_CAM_EN", - "WF_CAM_EN", - "AP_SAR_SENSOR_SDA", - "AP_SAR_SENSOR_SCL", - - "", /* 10 */ - "", - "AP_SPI_MOSI", - "AP_SPI_MISO", - "AP_SPI_CLK", - "AP_SPI_CS0_L", - "", - "", - "EDP_HPD", - "", - - "UF_CAM_RST_L", /* 20 */ - "WF_CAM_RST_L", - "UART_AP_TX_DBG_RX", - "UART_DBG_TX_AP_RX", - "EN_PP3300_HUB", - "", - "HOST2WLAN_SOL", - "WLAN2HOST_SOL", - "BT_UART_CTS", - "BT_UART_RTS", - - "BT_UART_TXD", /* 30 */ - "BT_UART_RXD", - "AP_EC_SPI_MISO", - "AP_EC_SPI_MOSI", - "AP_EC_SPI_CLK", - "AP_EC_SPI_CS_L", - "", - "", - "", - "PEN_PDCT_L", - - "IO_BRD_ID0", /* 40 */ - "IO_BRD_ID1", - "EN_FP_RAILS", - "PEN_IRQ_L", - "AP_SPI_FP_MISO", - "AP_SPI_FP_MOSI", - "AP_SPI_FP_CLK", - "AP_SPI_FP_CS_L", - "AP_H1_SPI_MISO", - "AP_H1_SPI_MOSI", - - "AP_H1_SPI_CLK", /* 50 */ - "AP_H1_SPI_CS_L", - "AP_TS_PEN_I2C_SDA", - "AP_TS_PEN_I2C_SCL", - "H1_AP_INT_ODL", - "", - "LCM_RST_1V8_L", - "AMP_EN", - "", - "DP_HOT_PLUG_DET", - - "HUB_RST_L", /* 60 */ - "FP_TO_AP_IRQ_L", - "", - "", - "UF_CAM_MCLK", - "WF_CAM_MCLK", - "IO_BRD_ID2", - "EN_PP3300_CODEC", - "EC_IN_RW_ODL", - "UF_CAM_SDA", - - "UF_CAM_SCL", /* 70 */ - "WF_CAM_SDA", - "WF_CAM_SCL", - "AP_BRD_ID0", - "AP_BRD_ID1", - "AP_BRD_ID2", - "", - "FPMCU_BOOT0", - "FP_RST_L", - "PE_CLKREQ_ODL", - - "EN_EDP_PP3300", /* 80 */ - "TS_INT_L", - "FORCE_USB_BOOT", - "WCD_RST_L", - "WLAN_EN", - "BT_EN", - "WLAN_SW_CTRL", - "PCIE0_RESET_L", - "PCIE0_CLK_REQ_L", - "PCIE0_WAKE_L", - - "AS_EN", /* 90 */ - "SD_CD_ODL", - "", - /* - * AP_FLASH_WP_L is crossystem ABI. Schematics - * call it BIOS_FLASH_WP_L. - */ - "AP_FLASH_WP_L", - "BT_WLAN_SB_CLK", - "BT_WLAN_SB_DATA", - "HP_MCLK", - "HP_BCLK", - "HP_DOUT", - "HP_DIN", - - "HP_LRCLK", /* 100 */ - "HP_IRQ", - "TP_INT_ODL", - "", - "IO_SKU_ID2", - "TS_RESET_L", - "AMP_BCLK", - "AMP_DIN", - "AMP_LRCLK", - "UIM2_DATA", - - "UIM2_CLK", /* 110 */ - "UIM2_RST", - "UIM2_PRESENT", - "UIM1_DATA", - "UIM1_CLK", - "UIM1_RST", - "", - "RFFE0_CLK", - "RFFE0_DATA/BOOT_CONFIG_0", - "RFFE1_CLK", - - "RFFE1_DATA/BOOT_CONFIG_1", /* 120 */ - "RFFE2_CLK", - "RFFE2_DATA/BOOT_CONFIG_2", - "RFFE3_CLK", - "RFFE3_DATA/BOOT_CONFIG_3", - "RFFE4_CLK", - "RFFE4_DATA", - "WCI2_LTE_COEX_RXD", - "WCI2_LTE_COEX_TXD", - "IO_SKU_ID0", - - "IO_SKU_ID1", /* 130 */ - "", - "", - "QLINK0_REQ", - "QLINK0_EN", - "QLINK0_WMSS_RESET_L", - "QLINK1_REQ", - "QLINK1_EN", - "QLINK1_WMSS_RESET_L", - "FORCED_USB_BOOT_POL", - - "", /* 140 */ - "P_SENSOR_INT_L", - "AP_EC_INT_L", - "", - "WCD_SWR_TX_CLK", - "WCD_SWR_TX_DATA_0", - "WCD_SWR_TX_DATA_1", - "WCD_SWR_RX_CLK", - "WCD_SWR_RX_DATA_0", - "WCD_SWR_RX_DATA_1", - - "", /* 150 */ - "", - "", - "", - "", - "", - "", - "", - "WCD_SWR_TX_DATA_2", - "", - - "", /* 160 */ - "", - "", - "", - "", - "", - "", - "", - "", - "", - - "", /* 170 */ - "SENS_UART_TXD", - "SENS_UART_RXD", - "", - "", - ""; - - /* - * pinctrl settings for pins that have no real owners. - */ - pinctrl-names = "default"; - pinctrl-0 = <&bios_flash_wp_l>; - - amp_en: amp-en { - pins = "gpio57"; - function = "gpio"; - bias-pull-down; - }; - - ap_ec_int_l: ap-ec-int-l { - pins = "gpio142"; - input-enable; - bias-pull-up; - }; - - bios_flash_wp_l: bios-flash-wp-l { - pins = "gpio93"; - function = "gpio"; - input-enable; - bias-disable; - }; - - bt_en: bt-en { - pins = "gpio85"; - function = "gpio"; - drive-strength = <2>; - output-low; - bias-pull-down; - }; - - en_fp_rails: en-fp-rails { - pins = "gpio42"; - drive-strength = <2>; - output-high; - bias-disable; - }; - - en_pp3300_codec: en-pp3300-codec { - pins = "gpio67"; - drive-strength = <2>; - bias-disable; - }; - - en_pp3300_dx_edp: en-pp3300-dx-edp { - pins = "gpio80"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - en_pp3300_hub: en-pp3300-hub { - pins = "gpio24"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - fp_to_ap_irq_l: fp-to-ap-irq-l { - pins = "gpio61"; - function = "gpio"; - input-enable; - /* Has external pullup */ - bias-disable; - }; - - h1_ap_int_odl: h1-ap-int-odl { - pins = "gpio54"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - hp_irq: hp-irq { - pins = "gpio101"; - function = "gpio"; - bias-pull-up; - }; - - p_sensor_int_l: p-sensor-int-l { - pins = "gpio141"; - function = "gpio"; - input-enable; - bias-pull-up; - }; - - pen_irq_l: pen-irq-l { - pins = "gpio43"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - pen_pdct_l: pen-pdct-l { - pins = "gpio39"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - qup_spi8_cs_gpio_init_high: qup-spi8-cs-gpio-init-high { - pins = "gpio35"; - output-high; - }; - - qup_spi11_cs_gpio_init_high: qup-spi11-cs-gpio-init-high { - pins = "gpio47"; - output-high; - }; - - qup_spi12_cs_gpio_init_high: qup-spi12-cs-gpio-init-high { - pins = "gpio51"; - output-high; - }; - - qup_uart7_sleep_cts: qup-uart7-sleep-cts { - pins = "gpio28"; - function = "gpio"; - /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. - */ - bias-pull-down; - }; - - qup_uart7_sleep_rts: qup-uart7-sleep-rts { - pins = "gpio29"; - function = "gpio"; - /* - * Configure pull-down on RTS. As RTS is active low - * signal, pull it low to indicate the BT SoC that it - * can wakeup the system anytime from suspend state by - * pulling RX low (by sending wakeup bytes). - */ - bias-pull-down; - }; - - qup_uart7_sleep_rx: qup-uart7-sleep-rx { - pins = "gpio31"; - function = "gpio"; - /* - * Configure a pull-up on RX. This is needed to avoid - * garbage data when the TX pin of the Bluetooth module - * is floating which may cause spurious wakeups. - */ - bias-pull-up; - }; - - qup_uart7_sleep_tx: qup-uart7-sleep-tx { - pins = "gpio30"; - function = "gpio"; - /* - * Configure pull-up on TX when it isn't actively driven - * to prevent BT SoC from receiving garbage during sleep. - */ - bias-pull-up; - }; - - sd_cd: sd-cd { - pins = "gpio91"; - function = "gpio"; - bias-pull-up; - }; - - tp_int_odl: tp-int-odl { - pins = "gpio102"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - }; - - ts_int_l: ts-int-l { - pins = "gpio81"; - function = "gpio"; - /* Has external pullup */ - bias-pull-up; - }; - - ts_reset_l: ts-reset-l { - pins = "gpio105"; - function = "gpio"; - /* Has external pullup */ - bias-disable; - drive-strength = <2>; - }; - - uf_cam_en: uf-cam-en { - pins = "gpio6"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; - - wf_cam_en: wf-cam-en { - pins = "gpio7"; - function = "gpio"; - drive-strength = <2>; - /* Has external pulldown */ - bias-disable; - }; -}; -- cgit v1.2.3 From dbcbeed94f3b6f7f24349a7f335cc603a682e7a7 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 16 Mar 2022 18:06:39 -0700 Subject: arm64: dts: qcom: sc7280-herobrine: Drop outputs on fpmcu pins Having these pins with outputs is good on a fresh boot because it puts the boot and reset pins in a known "good" state. Unfortunately, that conflicts with the fingerprint firmware flashing code. The firmware flashing process binds and unbinds the cros-ec and spidev drivers and that reapplies the pin output values after the flashing code has overridden the gpio values. This causes a problem because we try to put the device into bootloader mode, bind the spidev driver and that inadvertently puts it right back into normal boot mode, breaking the flashing process. Fix this by removing the outputs. We'll introduce a binding for fingerprint cros-ec specifically to set the gpios properly via gpio APIs during cros-ec driver probe instead. Cc: Douglas Anderson Cc: Matthias Kaehlcke Cc: Alexandru M Stan Fixes: 116f7cc43d28 ("arm64: dts: qcom: sc7280: Add herobrine-r1") Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220317010640.2498502-2-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 3d9b870d440b..10de5e104b4f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -727,7 +727,6 @@ ap_ec_spi: &spi10 { function = "gpio"; bias-disable; drive-strength = <2>; - output-high; }; fp_to_ap_irq_l: fp-to-ap-irq-l { @@ -741,7 +740,6 @@ ap_ec_spi: &spi10 { pins = "gpio68"; function = "gpio"; bias-disable; - output-low; }; gsc_ap_int_odl: gsc-ap-int-odl { -- cgit v1.2.3 From 516ca27b6033a07d7654e7838520f2c00b1ec606 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 25 Mar 2022 14:16:40 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Simplify SAR sensor enabling The SAR node, ap_sar_sensor, needs to be enabled in addition to the i2c bus it resides on. Let's simplify this by leaving the sensor node enabled by default while leaving the i2c bus disabled by default. On boards that use the sensor, we already enable the i2c bus so we can simply remove the extra bit that enables the sar sensor node. This saves some lines but is otherwise a non-functional change. Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325211640.54228-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 4 files changed, 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts index e16ba7b01f25..eb20157f6af9 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dts @@ -13,10 +13,6 @@ compatible = "google,lazor-rev1-sku0", "google,lazor-rev2-sku0", "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index c5c9feff41b8..8913592b2d82 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -20,10 +20,6 @@ "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index 344b57c035d0..8107f3d932eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -17,10 +17,6 @@ compatible = "google,lazor-sku0", "qcom,sc7180"; }; -&ap_sar_sensor { - status = "okay"; -}; - &ap_sar_sensor_i2c { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 732e1181af48..b0efb354458c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -722,7 +722,6 @@ ap_sar_sensor_i2c: &i2c5 { vdd-supply = <&pp3300_a>; svdd-supply = <&pp1800_prox>; - status = "disabled"; label = "proximity-wifi"; }; }; -- cgit v1.2.3 From e7773dbc87674aec210432185d9624ed346a46f1 Mon Sep 17 00:00:00 2001 From: Petr Vorel Date: Wed, 23 Mar 2022 21:48:40 +0100 Subject: arm64: dts: qcom: msm8994-huawei-angler: Add sdhc1 definition Angler does not have SD card, thus sdhc2 kept disabled. Signed-off-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220323204840.22832-1-petr.vorel@gmail.com --- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 0e3dd48f0dbf..6e43e4339f55 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright (c) 2015, Huawei Inc. All rights reserved. * Copyright (c) 2016, The Linux Foundation. All rights reserved. - * Copyright (c) 2021, Petr Vorel + * Copyright (c) 2021-2022, Petr Vorel */ /dts-v1/; @@ -41,3 +41,8 @@ &tlmm { gpio-reserved-ranges = <85 4>; }; + +&sdhc1 { + status = "okay"; + mmc-hs400-1_8v; +}; -- cgit v1.2.3 From 9e5c45a5aac0ccb0d3433c8ea6b577c0473351ef Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:42:04 +0200 Subject: arm64: dts: qcom: sm6350: Fix naming of uart9 The uart9 was previously mistakenly called uart2. Fix this. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408114205.234635-1-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d7c9edff19f7..ef43af39569c 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -529,13 +529,13 @@ ranges; status = "disabled"; - uart2: serial@98c000 { + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart2_default>; + pinctrl-0 = <&qup_uart9_default>; interrupts = ; status = "disabled"; }; @@ -974,7 +974,7 @@ #interrupt-cells = <2>; gpio-ranges = <&tlmm 0 0 157>; - qup_uart2_default: qup-uart2-default { + qup_uart9_default: qup-uart9-default { pins = "gpio25", "gpio26"; function = "qup13_f2"; drive-strength = <2>; diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index adb6ca2be2a5..67d14bda3797 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -23,7 +23,7 @@ qcom,board-id = <8 32>; aliases { - serial0 = &uart2; + serial0 = &uart9; }; chosen { @@ -332,7 +332,7 @@ gpio-reserved-ranges = <13 4>, <56 2>; }; -&uart2 { +&uart9 { status = "okay"; }; -- cgit v1.2.3 From 7be9f3ae250e97859e28c26daf457b1be3f58d17 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:42:05 +0200 Subject: arm64: dts: qcom: sm6350: Add I2C busses Add nodes for the I2C busses on sm6350. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408114205.234635-2-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 134 +++++++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index ef43af39569c..81db25952cf1 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -517,6 +517,45 @@ }; }; + qupv3_id_0: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x8c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + #address-cells = <2>; + #size-cells = <2>; + iommus = <&apps_smmu 0x43 0x0>; + ranges; + status = "disabled"; + + i2c0: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + qupv3_id_1: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x9c0000 0x0 0x2000>; @@ -529,6 +568,45 @@ ranges; status = "disabled"; + i2c6: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart9: serial@98c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x98c000 0 0x4000>; @@ -539,6 +617,20 @@ interrupts = ; status = "disabled"; }; + + i2c10: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; tcsr_mutex: hwlock@1f40000 { @@ -980,6 +1072,48 @@ drive-strength = <2>; bias-disable; }; + + qup_i2c0_default: qup-i2c0-default { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_default: qup-i2c6-default { + pins = "gpio13", "gpio14"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_default: qup-i2c7-default { + pins = "gpio27", "gpio28"; + function = "qup11"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default { + pins = "gpio19", "gpio20"; + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default { + pins = "gpio4", "gpio5"; + function = "qup14"; + drive-strength = <2>; + bias-pull-up; + }; }; apps_smmu: iommu@15000000 { -- cgit v1.2.3 From 413821b7777d062b57f8dc66ab088ed390cbc3ec Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 8 Apr 2022 13:53:10 +0200 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Add AW8695 haptics Add a node for the haptics driver found on the phone. Signed-off-by: Luca Weiss Reported-by: kernel test robot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220408115311.237039-3-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 29 +++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 67d14bda3797..4691a5e5c8e5 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -296,6 +296,35 @@ firmware-name = "qcom/sm7225/fairphone4/cdsp.mdt"; }; +&i2c10 { + status = "okay"; + clock-frequency = <400000>; + + haptics@5a { + compatible = "awinic,aw8695"; + reg = <0x5a>; + interrupts-extended = <&tlmm 85 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 90 GPIO_ACTIVE_HIGH>; + + awinic,f0-preset = <2350>; + awinic,f0-coefficient = <260>; + awinic,f0-calibration-percent = <7>; + awinic,drive-level = <125>; + + awinic,f0-detection-play-time = <5>; + awinic,f0-detection-wait-time = <3>; + awinic,f0-detection-repeat = <2>; + awinic,f0-detection-trace = <15>; + + awinic,boost-debug = /bits/ 8 <0x30 0xeb 0xd4>; + awinic,tset = /bits/ 8 <0x12>; + awinic,r-spare = /bits/ 8 <0x68>; + + awinic,bemf-upper-threshold = <4104>; + awinic,bemf-lower-threshold = <1016>; + }; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm7225/fairphone4/modem.mdt"; -- cgit v1.2.3 From aff4d695b4eb3b279bfff53d2f06f464e363ee4a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 7 Apr 2022 17:52:54 -0500 Subject: arm64: dts: qcom: sdm845: shift6mq: Fix boolean properties with values Boolean properties in DT are present or not present and don't take a value. A property such as 'foo = <0>;' evaluated to true. IOW, the value doesn't matter. It may have been intended that 0 values are false, but there is no change in behavior with this patch. Cc: Andy Gross Cc: Bjorn Andersson Cc: Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Rob Herring [bjorn: Updated subject prefix] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407225254.2178644-1-robh@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts index 8553c8bf79bd..103cc40816fd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts @@ -563,7 +563,7 @@ config { pins = "gpio6", "gpio11"; drive-strength = <8>; - bias-disable = <0>; + bias-disable; }; }; -- cgit v1.2.3 From 2b6d37f6b7fe2f98197b77adcce81d4198aeb305 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:31:12 +0200 Subject: arm64: dts: qcom: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407143112.294930-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 2 +- arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 2 +- arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index 5aec18308712..821cb7c0c183 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -39,7 +39,7 @@ cs-select = <0>; status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; reg = <0>; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index b5e1eaa367bf..de20cb98acd3 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -35,7 +35,7 @@ &blsp1_spi1 { status = "okay"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi index 07e670829676..ce86d9b10d69 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi @@ -29,7 +29,7 @@ &blsp1_spi1 { status = "ok"; - m25p80@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; -- cgit v1.2.3 From b32846a38fc2a68f6a9c1149b495fa4ca2552f20 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:23 +0200 Subject: arm64: dts: qcom: msm8996: drop unsupported UFS vddp-ref-clk-max-microamp The property vddp-ref-clk-max-microamp (for VDDP ref clk supply which is l25 regulator) is not documented in MSM8996 UFS PHY bindings (qcom,msm8996-qmp-ufs-phy). It is mentioned in the other UFS PHY bindings for qcom,msm8996-ufs-phy-qmp-14nm. The MSM8996-based Xiaomi devices configure l25 regulator in a conflicting way: 1. with maximum 100 uAmp for VDDP ref clk supply of UFS PHY, 2. with maximum 450 mAmp for VCCQ supply of UFS. Since the vddp-ref-clk-max-microamp property is basically not documented for that UFS PHY and has a conflicting values, drop it entirely as it looks like not tested and not used ever. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 7a9fcbe9bb31..3ade756e1cd9 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -341,7 +341,6 @@ vdda-pll-max-microamp = <9440>; vddp-ref-clk-supply = <&vreg_l25a_1p2>; - vddp-ref-clk-max-microamp = <100>; vddp-ref-clk-always-on; }; -- cgit v1.2.3 From 64ff698424433dc5d2e827de2a4cc927300d7fe2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:24 +0200 Subject: arm64: dts: qcom: msm8996: correct UFS compatible The Qualcomm UFS bindings require to use specific (qcom,msm8996-ufshc) and generic (jedec,ufs-2.0) compatibles. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index f0f81c23c16f..fa491f2271ff 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1730,7 +1730,8 @@ }; ufshc: ufshc@624000 { - compatible = "qcom,ufshc"; + compatible = "qcom,msm8996-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; reg = <0x00624000 0x2500>; interrupts = ; -- cgit v1.2.3 From 7ba57d11e5bb57095e6d312b518ae9ceb7efcbf1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 11:27:25 +0200 Subject: arm64: dts: qcom: sm8350: drop duplicated ref_clk in UFS ref_clk clock in UFS node is already there with a <0 0> frequency, which matches other DTSI files. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220407092725.232463-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 3 --- 1 file changed, 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 20f850b94158..e70687d6c2da 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1916,7 +1916,6 @@ iommus = <&apps_smmu 0xe0 0x0>; clock-names = - "ref_clk", "core_clk", "bus_aggr_clk", "iface_clk", @@ -1926,7 +1925,6 @@ "rx_lane0_sync_clk", "rx_lane1_sync_clk"; clocks = - <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_UFS_PHY_AHB_CLK>, @@ -1936,7 +1934,6 @@ <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; freq-table-hz = - <75000000 300000000>, <75000000 300000000>, <0 0>, <0 0>, -- cgit v1.2.3 From cdbfb815d63a792fb565ab15c8f565833bb86c8b Mon Sep 17 00:00:00 2001 From: Manikanta Pubbisetty Date: Wed, 6 Apr 2022 16:43:03 +0530 Subject: arm64: dts: qcom: sc7280: Add WCN6750 WiFi node Add DTS node for WCN6750 WiFi chipset. Signed-off-by: Manikanta Pubbisetty Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220406111303.27670-1-quic_mpubbise@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 6 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 069ffbc37bc4..015a3474d401 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -551,3 +551,9 @@ status = "okay"; }; +&wifi { + status = "okay"; + wifi-firmware { + iommus = <&apps_smmu 0x1c02 0x1>; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index b757e8ad1199..26f66f46a950 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -85,6 +85,11 @@ #size-cells = <2>; ranges; + wlan_ce_mem: memory@4cd000 { + no-map; + reg = <0x0 0x004cd000 0x0 0x1000>; + }; + hyp_mem: memory@80000000 { reg = <0x0 0x80000000 0x0 0x600000>; no-map; @@ -1808,6 +1813,47 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + wifi: wifi@17a10040 { + compatible = "qcom,wcn6750-wifi"; + reg = <0 0x17a10040 0 0x0>; + iommus = <&apps_smmu 0x1c00 0x1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,rproc = <&remoteproc_wpss>; + memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; + status = "disabled"; + }; + pcie1: pci@1c08000 { compatible = "qcom,pcie-sc7280"; reg = <0 0x01c08000 0 0x3000>, -- cgit v1.2.3 From 0fa44edd0f8fe2bd829827adcc5659304c8ab7fa Mon Sep 17 00:00:00 2001 From: Souradeep Chowdhury Date: Wed, 6 Apr 2022 15:03:48 +0530 Subject: arm64: dts: qcom: sc7280: Set the default dr_mode for usb2 Set the default dr_mode for usb2 node to "otg" to enable role-switch for EUD(Embedded USB Debugger) connector node. Signed-off-by: Souradeep Chowdhury Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/451392a942f90aa9805b00afad7dff894604d189.1649235218.git.quic_schowdhu@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index a7be133a782f..6d3ff80582ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -90,7 +90,7 @@ }; &usb_2_dwc3 { - dr_mode = "host"; + dr_mode = "otg"; }; &usb_2_hsphy { -- cgit v1.2.3 From dcd0a663544fe978d658520709dfeaeb95ee855a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:57:51 +0200 Subject: arm64: dts: qcom: msm8916: rename WCNSS child name to bluetooth The "bluetooth" is more popular and more descriptive than "bt", for a Bluetooth device. The WCNSS DT schema will expect such naming. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405065752.27389-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e34963505e07..4209fbd52359 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1788,7 +1788,7 @@ qcom,mmio = <&pronto>; - bt { + bluetooth { compatible = "qcom,wcnss-bt"; }; -- cgit v1.2.3 From 0e1b27f4f69e86b8b62ba5bedb78936341433247 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:43 +0200 Subject: arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema The DT schema expects dma channels in tx-rx order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 ++++---- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 ++++++++++++++++---------------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++++---------- 4 files changed, 38 insertions(+), 38 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index aac56575e30d..87c28ffa44d3 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -322,8 +322,8 @@ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -337,8 +337,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d80b1cefab10..2072638006a4 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -471,8 +471,8 @@ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-0 = <&i2c_0_pins>; pinctrl-names = "default"; status = "disabled"; @@ -488,8 +488,8 @@ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 17>, <&blsp_dma 16>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 16>, <&blsp_dma 17>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,8 +503,8 @@ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <400000>; - dmas = <&blsp_dma 21>, <&blsp_dma 20>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 20>, <&blsp_dma 21>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -518,8 +518,8 @@ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; clock-names = "iface", "core"; clock-frequency = <100000>; - dmas = <&blsp_dma 23>, <&blsp_dma 22>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 22>, <&blsp_dma 23>; + dma-names = "tx", "rx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 4209fbd52359..e90e9eb22810 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1485,8 +1485,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 1>, <&blsp_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 0>, <&blsp_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart1_default>; pinctrl-1 = <&blsp1_uart1_sleep>; @@ -1499,8 +1499,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 3>, <&blsp_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 2>, <&blsp_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_uart2_default>; pinctrl-1 = <&blsp1_uart2_sleep>; @@ -1529,8 +1529,8 @@ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 5>, <&blsp_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 4>, <&blsp_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi1_default>; pinctrl-1 = <&spi1_sleep>; @@ -1561,8 +1561,8 @@ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 7>, <&blsp_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 6>, <&blsp_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi2_default>; pinctrl-1 = <&spi2_sleep>; @@ -1593,8 +1593,8 @@ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 9>, <&blsp_dma 8>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 8>, <&blsp_dma 9>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi3_default>; pinctrl-1 = <&spi3_sleep>; @@ -1625,8 +1625,8 @@ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 11>, <&blsp_dma 10>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 10>, <&blsp_dma 11>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi4_default>; pinctrl-1 = <&spi4_sleep>; @@ -1657,8 +1657,8 @@ clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 13>, <&blsp_dma 12>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 12>, <&blsp_dma 13>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi5_default>; pinctrl-1 = <&spi5_sleep>; @@ -1689,8 +1689,8 @@ clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp_dma 15>, <&blsp_dma 14>; - dma-names = "rx", "tx"; + dmas = <&blsp_dma 14>, <&blsp_dma 15>; + dma-names = "tx", "rx"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&spi6_default>; pinctrl-1 = <&spi6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 3f06f7cd3cf2..6b3a8e1006d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -823,8 +823,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 1>, <&blsp1_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart0_default>; status = "disabled"; @@ -836,8 +836,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 3>, <&blsp1_dma 2>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart1_default>; status = "disabled"; @@ -849,8 +849,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 5>, <&blsp1_dma 4>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart2_default>; status = "okay"; @@ -903,8 +903,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp1_dma 7>, <&blsp1_dma 6>; - dma-names = "rx", "tx"; + dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_uart3_default>; status = "disabled"; @@ -1067,8 +1067,8 @@ interrupts = ; clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; clock-names = "core", "iface"; - dmas = <&blsp2_dma 1>, <&blsp2_dma 0>; - dma-names = "rx", "tx"; + dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_uart0_default>; status = "disabled"; -- cgit v1.2.3 From 2374b99e19ac7f2beca2d4e62ebb96803db0e66b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 5 Apr 2022 08:34:44 +0200 Subject: arm64: dts: qcom: align clocks in I2C/SPI with DT schema The DT schema expects clocks core-iface order. No functional change. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220405063451.12011-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 +++--- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++++------ arch/arm64/boot/dts/qcom/msm8916.dtsi | 36 +++++++++--------- arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++++------------ arch/arm64/boot/dts/qcom/msm8994.dtsi | 42 ++++++++++---------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 36 +++++++++--------- arch/arm64/boot/dts/qcom/qcs404.dtsi | 72 +++++++++++++++++------------------ 7 files changed, 135 insertions(+), 135 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 87c28ffa44d3..8032d7933c66 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -318,9 +318,9 @@ #size-cells = <0>; reg = <0x0 0x078b6000 0x0 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -333,9 +333,9 @@ #size-cells = <0>; reg = <0x0 0x078b7000 0x0 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2072638006a4..8e41c910b8f9 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -467,9 +467,9 @@ #size-cells = <0>; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 14>, <&blsp_dma 15>; dma-names = "tx", "rx"; @@ -484,9 +484,9 @@ #size-cells = <0>; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <100000>; dmas = <&blsp_dma 16>, <&blsp_dma 17>; dma-names = "tx", "rx"; @@ -499,9 +499,9 @@ #size-cells = <0>; reg = <0x78b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp_dma 20>, <&blsp_dma 21>; dma-names = "tx", "rx"; @@ -514,9 +514,9 @@ #size-cells = <0>; reg = <0x078ba000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <100000>; dmas = <&blsp_dma 22>, <&blsp_dma 23>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index e90e9eb22810..c2713d307833 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1511,9 +1511,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b5000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_default>; pinctrl-1 = <&i2c1_sleep>; @@ -1543,9 +1543,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c2_default>; pinctrl-1 = <&i2c2_sleep>; @@ -1575,9 +1575,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b7000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c3_default>; pinctrl-1 = <&i2c3_sleep>; @@ -1607,9 +1607,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c4_default>; pinctrl-1 = <&i2c4_sleep>; @@ -1639,9 +1639,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b9000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c5_default>; pinctrl-1 = <&i2c5_sleep>; @@ -1671,9 +1671,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078ba000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c6_default>; pinctrl-1 = <&i2c6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 431228faacdd..2a70263a701d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -923,9 +923,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b5000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_1_default>; @@ -941,9 +941,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b6000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_2_default>; @@ -959,9 +959,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b7000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_3_default>; pinctrl-1 = <&i2c_3_sleep>; @@ -976,9 +976,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x78b8000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_4_default>; pinctrl-1 = <&i2c_4_sleep>; @@ -993,9 +993,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af5000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_5_default>; pinctrl-1 = <&i2c_5_sleep>; @@ -1010,9 +1010,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af6000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_6_default>; pinctrl-1 = <&i2c_6_sleep>; @@ -1027,9 +1027,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af7000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_7_default>; pinctrl-1 = <&i2c_7_sleep>; @@ -1044,9 +1044,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x7af8000 0x600>; interrupts = ; - clock-names = "iface", "core"; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>; + clock-names = "core", "iface"; + clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c_8_default>; pinctrl-1 = <&i2c_8_sleep>; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 8c1dc5155b71..209f9ef030e5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -519,9 +519,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9923000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; dma-names = "tx", "rx"; @@ -555,9 +555,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9924000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; dma-names = "tx", "rx"; @@ -575,9 +575,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9926000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; dma-names = "tx", "rx"; @@ -593,9 +593,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9927000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; @@ -611,9 +611,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9928000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; dma-names = "tx", "rx"; @@ -657,9 +657,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9963000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; dma-names = "tx", "rx"; @@ -693,9 +693,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0xf9967000 0x500>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <355000>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; dma-names = "tx", "rx"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index fa491f2271ff..db3eb160d1bb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2787,9 +2787,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07577000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp1_i2c3_default>; pinctrl-1 = <&blsp1_i2c3_sleep>; @@ -2835,9 +2835,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b5000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c1_default>; pinctrl-1 = <&blsp2_i2c1_sleep>; @@ -2852,9 +2852,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b6000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c2_default>; pinctrl-1 = <&blsp2_i2c2_sleep>; @@ -2869,9 +2869,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x075b7000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; clock-frequency = <400000>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c3_default>; @@ -2887,9 +2887,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75b9000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c5_default>; dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; @@ -2903,9 +2903,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75ba000 0x1000>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&blsp2_i2c6_default>; pinctrl-1 = <&blsp2_i2c6_sleep>; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 6b3a8e1006d0..acf120f91b42 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -914,9 +914,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c0_default>; #address-cells = <1>; @@ -928,9 +928,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi0_default>; #address-cells = <1>; @@ -942,9 +942,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c1_default>; #address-cells = <1>; @@ -956,9 +956,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b6000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi1_default>; #address-cells = <1>; @@ -970,9 +970,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c2_default>; #address-cells = <1>; @@ -984,9 +984,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b7000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi2_default>; #address-cells = <1>; @@ -998,9 +998,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c3_default>; #address-cells = <1>; @@ -1012,9 +1012,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b8000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi3_default>; #address-cells = <1>; @@ -1026,9 +1026,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_i2c4_default>; #address-cells = <1>; @@ -1040,9 +1040,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x078b9000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP1_AHB_CLK>, - <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, + <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp1_spi4_default>; #address-cells = <1>; @@ -1078,9 +1078,9 @@ compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_i2c0_default>; #address-cells = <1>; @@ -1092,9 +1092,9 @@ compatible = "qcom,spi-qup-v2.2.1"; reg = <0x07af5000 0x600>; interrupts = ; - clocks = <&gcc GCC_BLSP2_AHB_CLK>, - <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>; - clock-names = "iface", "core"; + clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, + <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; pinctrl-names = "default"; pinctrl-0 = <&blsp2_spi0_default>; #address-cells = <1>; -- cgit v1.2.3 From 6b834df8391b5f1ee710b4750d2ed39a6d0c693d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 3 Apr 2022 13:57:11 +0300 Subject: arm64: dts: qcom: sdm845-db845c: add wifi variant property Dragonboard845c doesn't have board-specific board-id programmed, it uses generic 0xff. Thus add the property with the 'variant' of the calibration data. Note: the driver will check for the calibration data for the following IDs, so older board-2.bin files that were distributed as a part of Linaro releases will continue to work. - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=30214,variant=Thundercomm_DB845C' - 'bus=snoc,qmi-board-id=ff,qmi-chip-id=30214' - 'bus=snoc,qmi-board-id=ff' For the reference, the board is identified by the driver in the following way: ath10k_snoc 18800000.wifi: qmi chip_id 0x30214 chip_family 0x4001 board_id 0xff soc_id 0x40030001 ath10k_snoc 18800000.wifi: qmi fw_version 0x2009856b fw_build_timestamp 2018-07-19 12:28 fw_build_id QC_IMAGE_VERSION_STRING=WLAN.HL.2.0-01387-QCAHLSWMTPLZ-1 Fixes: 3f72e2d3e682 ("arm64: dts: qcom: Add Dragonboard 845c") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403105711.1173161-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 28fe45c5d516..9206efa9d6d2 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1051,6 +1051,7 @@ vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; qcom,snoc-host-cap-8bit-quirk; + qcom,ath10k-calibration-variant = "Thundercomm_DB845C"; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ -- cgit v1.2.3 From 876644c7603440279545fab4988edd424aea6d9f Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 3 Apr 2022 20:11:50 +0530 Subject: arm64: dts: qcom: sm8150: Add support for SDC2 Add support for SDC2 which can be used to interface uSD card. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403144151.92572-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 45 ++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 13547c15f321..c0128c960950 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3515,6 +3515,51 @@ }; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm8150-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd 0>; + operating-points-v2 = <&sdhc2_opp_table>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + dc_noc: interconnect@9160000 { compatible = "qcom,sm8150-dc-noc"; reg = <0 0x09160000 0 0x3200>; -- cgit v1.2.3 From 0deb2624e2d09aa158495ead66906fb437a67148 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 3 Apr 2022 20:11:51 +0530 Subject: arm64: dts: qcom: sa8155p-adp: Add support for uSD card Add support for uSD card on SA8155p-ADP board using the SDHC2 interface. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403144151.92572-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 68 ++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 676e4fe3f848..8e781125e8d0 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -317,6 +317,20 @@ firmware-name = "qcom/sa8155p/cdsp.mdt"; }; +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + vqmmc-supply = <&vreg_l13c_2p96>; /* IO line power */ + vmmc-supply = <&vreg_l17a_2p96>; /* Card power line */ + bus-width = <4>; + no-sdio; + no-emmc; +}; + &uart2 { status = "okay"; }; @@ -405,6 +419,60 @@ &tlmm { gpio-reserved-ranges = <0 4>; + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; /* No pull */ + drive-strength = <16>; /* 16 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <16>; /* 16 MA */ + }; + + sd-cd { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; /* No pull */ + drive-strength = <2>; /* 2 MA */ + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + data { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + + sd-cd { + pins = "gpio96"; + function = "gpio"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + usb2phy_ac_en1_default: usb2phy_ac_en1_default { mux { pins = "gpio113"; -- cgit v1.2.3 From 902d97a44211b17bae49442b770ac5311b7c0b32 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:16 +0000 Subject: arm64: dts: qcom: msm8996: Revamp reserved memory Fix a total overlap between zap_shader_region and slpi_region, and rename all regions to match the naming convention in other Qualcomm SoC device trees. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-2-y.oudjana@protonmail.com --- .../boot/dts/qcom/msm8996-sony-xperia-tone.dtsi | 18 ++++--- .../arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 18 +++---- arch/arm64/boot/dts/qcom/msm8996.dtsi | 63 ++++++++++++---------- 3 files changed, 55 insertions(+), 44 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi index 3bb50cecd62d..ca3c633f5a45 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-sony-xperia-tone.dtsi @@ -13,9 +13,10 @@ #include #include -/delete-node/ &slpi_region; -/delete-node/ &venus_region; -/delete-node/ &zap_shader_region; +/delete-node/ &adsp_mem; +/delete-node/ &slpi_mem; +/delete-node/ &venus_mem; +/delete-node/ &gpu_mem; / { qcom,msm-id = <246 0x30001>; /* MSM8996 V3.1 (Final) */ @@ -46,18 +47,23 @@ no-map; }; - zap_shader_region: gpu@90400000 { + adsp_mem: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1a00000>; + no-map; + }; + + gpu_mem: gpu@90400000 { compatible = "shared-dma-pool"; reg = <0x0 0x90400000 0x0 0x2000>; no-map; }; - slpi_region: memory@90500000 { + slpi_mem: memory@90500000 { reg = <0 0x90500000 0 0xa00000>; no-map; }; - venus_region: memory@90f00000 { + venus_mem: memory@90f00000 { reg = <0 0x90f00000 0 0x500000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index 3ade756e1cd9..d3ac943a00fb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -66,32 +66,32 @@ /* This platform has all PIL regions offset by 0x1400000 */ /delete-node/ mpss@88800000; - mpss_region: mpss@89c00000 { + mpss_mem: mpss@89c00000 { reg = <0x0 0x89c00000 0x0 0x6200000>; no-map; }; /delete-node/ adsp@8ea00000; - adsp_region: adsp@8ea00000 { + adsp_mem: adsp@8fe00000 { reg = <0x0 0x8fe00000 0x0 0x1b00000>; no-map; }; - /delete-node/ slpi@90b00000; - slpi_region: slpi@91900000 { + /delete-node/ slpi@90500000; + slpi_mem: slpi@91900000 { reg = <0x0 0x91900000 0x0 0xa00000>; no-map; }; - /delete-node/ gpu@8f200000; - zap_shader_region: gpu@92300000 { + /delete-node/ gpu@90f00000; + gpu_mem: gpu@92300000 { compatible = "shared-dma-pool"; reg = <0x0 0x92300000 0x0 0x2000>; no-map; }; /delete-node/ venus@91000000; - venus_region: venus@90400000 { + venus_mem: venus@92400000 { reg = <0x0 0x92400000 0x0 0x500000>; no-map; }; @@ -107,7 +107,7 @@ pmsg-size = <0x40000>; }; - /delete-node/ rmtfs@86700000; + /delete-node/ rmtfs; rmtfs@f6c00000 { compatible = "qcom,rmtfs-mem"; reg = <0 0xf6c00000 0 0x200000>; @@ -118,7 +118,7 @@ }; /delete-node/ mba@91500000; - mba_region: mba@f6f00000 { + mba_mem: mba@f6f00000 { reg = <0x0 0xf6f00000 0x0 0x100000>; no-map; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index db3eb160d1bb..dd4b2b370264 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -384,60 +384,65 @@ #size-cells = <2>; ranges; - mba_region: mba@91500000 { - reg = <0x0 0x91500000 0x0 0x200000>; + hyp_mem: memory@85800000 { + reg = <0x0 0x85800000 0x0 0x600000>; no-map; }; - slpi_region: slpi@90b00000 { - reg = <0x0 0x90b00000 0x0 0xa00000>; + xbl_mem: memory@85e00000 { + reg = <0x0 0x85e00000 0x0 0x200000>; no-map; }; - venus_region: venus@90400000 { - reg = <0x0 0x90400000 0x0 0x700000>; + smem_mem: smem-mem@86000000 { + reg = <0x0 0x86000000 0x0 0x200000>; no-map; }; - adsp_region: adsp@8ea00000 { - reg = <0x0 0x8ea00000 0x0 0x1a00000>; + tz_mem: memory@86200000 { + reg = <0x0 0x86200000 0x0 0x2600000>; no-map; }; - mpss_region: mpss@88800000 { - reg = <0x0 0x88800000 0x0 0x6200000>; + rmtfs_mem: rmtfs { + compatible = "qcom,rmtfs-mem"; + + size = <0x0 0x200000>; + alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; }; - smem_mem: smem-mem@86000000 { - reg = <0x0 0x86000000 0x0 0x200000>; + mpss_mem: mpss@88800000 { + reg = <0x0 0x88800000 0x0 0x6200000>; no-map; }; - memory@85800000 { - reg = <0x0 0x85800000 0x0 0x800000>; + adsp_mem: adsp@8ea00000 { + reg = <0x0 0x8ea00000 0x0 0x1b00000>; no-map; }; - memory@86200000 { - reg = <0x0 0x86200000 0x0 0x2600000>; + slpi_mem: slpi@90500000 { + reg = <0x0 0x90500000 0x0 0xa00000>; no-map; }; - rmtfs@86700000 { - compatible = "qcom,rmtfs-mem"; - - size = <0x0 0x200000>; - alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; + gpu_mem: gpu@90f00000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x90f00000 0x0 0x100000>; no-map; + }; - qcom,client-id = <1>; - qcom,vmid = <15>; + venus_mem: venus@91000000 { + reg = <0x0 0x91000000 0x0 0x500000>; + no-map; }; - zap_shader_region: gpu@8f200000 { - compatible = "shared-dma-pool"; - reg = <0x0 0x90b00000 0x0 0xa00000>; + mba_mem: mba@91500000 { + reg = <0x0 0x91500000 0x0 0x200000>; no-map; }; }; @@ -1033,7 +1038,7 @@ }; zap-shader { - memory-region = <&zap_shader_region>; + memory-region = <&gpu_mem>; }; }; @@ -2027,7 +2032,7 @@ <&venus_smmu 0x2c>, <&venus_smmu 0x2d>, <&venus_smmu 0x31>; - memory-region = <&venus_region>; + memory-region = <&venus_mem>; status = "disabled"; video-decoder { @@ -3034,7 +3039,7 @@ clocks = <&rpmcc RPM_SMD_BB_CLK1>; clock-names = "xo"; - memory-region = <&adsp_region>; + memory-region = <&adsp_mem>; qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; -- cgit v1.2.3 From 6d338feb553a32efee3ca50f503ab36e01455924 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:28 +0000 Subject: arm64: dts: qcom: msm8996: Unify smp2p naming Rename smp2p-modem to smp2p-mpss, and make the subnode labels of smp2p_adsp and smp2p_slpi follow the _smp2p_ layout. Also move smp2p_slpi_out above smp2p_slpi_in to make it match mpss and adsp where master-kernel is the first subnode. This patch brings no functional change. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-4-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index dd4b2b370264..b7b5b17f9dd7 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -518,12 +518,12 @@ qcom,local-pid = <0>; qcom,remote-pid = <2>; - smp2p_adsp_out: master-kernel { + adsp_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; - smp2p_adsp_in: slave-kernel { + adsp_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; @@ -531,7 +531,7 @@ }; }; - smp2p-modem { + smp2p-mpss { compatible = "qcom,smp2p"; qcom,smem = <435>, <428>; @@ -542,12 +542,12 @@ qcom,local-pid = <0>; qcom,remote-pid = <1>; - modem_smp2p_out: master-kernel { + mpss_smp2p_out: master-kernel { qcom,entry-name = "master-kernel"; #qcom,smem-state-cells = <1>; }; - modem_smp2p_in: slave-kernel { + mpss_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; interrupt-controller; @@ -566,16 +566,17 @@ qcom,local-pid = <0>; qcom,remote-pid = <3>; - smp2p_slpi_in: slave-kernel { + slpi_smp2p_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + slpi_smp2p_in: slave-kernel { qcom,entry-name = "slave-kernel"; + interrupt-controller; #interrupt-cells = <2>; }; - - smp2p_slpi_out: master-kernel { - qcom,entry-name = "master-kernel"; - #qcom,smem-state-cells = <1>; - }; }; soc: soc { @@ -3029,10 +3030,10 @@ reg = <0x09300000 0x80000>; interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, - <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; @@ -3041,7 +3042,7 @@ memory-region = <&adsp_mem>; - qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; power-domains = <&rpmpd MSM8996_VDDCX>; -- cgit v1.2.3 From 127dd2f08d274d9be9a6b1172035ebf7b7d51bc7 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:35 +0000 Subject: arm64: dts: qcom: msm8996: Add MSS and SLPI Add nodes for the MSS and SLPI remoteprocs. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-5-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 99 +++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b7b5b17f9dd7..e918038e8bd3 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2129,6 +2129,105 @@ clock-names = "iface", "bus"; }; + slpi_pil: remoteproc@1c00000 { + compatible = "qcom,msm8996-slpi-pil"; + reg = <0x01c00000 0x4000>; + + interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&xo_board>, + <&rpmcc RPM_SMD_AGGR2_NOC_CLK>; + clock-names = "xo", "aggre2"; + + memory-region = <&slpi_mem>; + + qcom,smem-states = <&slpi_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + power-domains = <&rpmpd MSM8996_VDDSSCX>; + power-domain-names = "ssc_cx"; + + status = "disabled"; + + smd-edge { + interrupts = ; + + label = "dsps"; + mboxes = <&apcs_glb 25>; + qcom,smd-edge = <3>; + qcom,remote-pid = <3>; + }; + }; + + mss_pil: remoteproc@2080000 { + compatible = "qcom,msm8996-mss-pil"; + reg = <0x2080000 0x100>, + <0x2180000 0x020>; + reg-names = "qdsp6", "rmb"; + + interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&mpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", + "shutdown-ack"; + + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, + <&gcc GCC_BOOT_ROM_AHB_CLK>, + <&xo_board>, + <&gcc GCC_MSS_GPLL0_DIV_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, + <&rpmcc RPM_SMD_PCNOC_CLK>, + <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "iface", "bus", "mem", "xo", "gpll0_mss", + "snoc_axi", "mnoc_axi", "pnoc", "qdss"; + + resets = <&gcc GCC_MSS_RESTART>; + reset-names = "mss_restart"; + + power-domains = <&rpmpd MSM8996_VDDCX>, + <&rpmpd MSM8996_VDDMX>; + power-domain-names = "cx", "mx"; + + qcom,smem-states = <&mpss_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; + + status = "disabled"; + + mba { + memory-region = <&mba_mem>; + }; + + mpss { + memory-region = <&mpss_mem>; + }; + + smd-edge { + interrupts = ; + + label = "mpss"; + mboxes = <&apcs_glb 12>; + qcom,smd-edge = <0>; + qcom,remote-pid = <1>; + }; + }; + stm@3002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0x3002000 0x1000>, -- cgit v1.2.3 From 73f7731b6831876fb61c32be1e75c4ad6ac25dbf Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Sun, 26 Sep 2021 19:06:45 +0000 Subject: arm64: dts: qcom: msm8996-xiaomi-*: Enable MSS and SLPI Enable mss_pil and slpi_pil and set their firmware paths. Signed-off-by: Yassine Oudjana Tested-by: Dmitry Baryshkov #db820c Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926190555.278589-6-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 9 +++++++++ arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 9 +++++++++ 3 files changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index d3ac943a00fb..fdb70227c0fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -267,6 +267,12 @@ vdd-gfx-supply = <&vdd_gfx>; }; +&mss_pil { + status = "okay"; + + pll-supply = <&vreg_l12a_1p8>; +}; + &pcie0 { status = "okay"; @@ -291,6 +297,12 @@ linux,code = ; }; +&slpi_pil { + status = "okay"; + + px-supply = <&vreg_lvs2a_1p8>; +}; + &usb3 { status = "okay"; extcon = <&typec>; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts index 34f82e06ef53..22978d06f85b 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -130,6 +130,11 @@ status = "okay"; }; +&mss_pil { + firmware-name = "qcom/msm8996/gemini/mba.mbn", + "qcom/msm8996/gemini/modem.mbn"; +}; + &q6asmdai { dai@0 { reg = <0>; @@ -144,6 +149,10 @@ }; }; +&slpi_pil { + firmware-name = "qcom/msm8996/gemini/slpi.mbn"; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "gemini"; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts index 27a45ddbb5bd..1e2dd6763ad1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -111,6 +111,11 @@ status = "disabled"; }; +&mss_pil { + firmware-name = "qcom/msm8996/scorpio/mba.mbn", + "qcom/msm8996/scorpio/modem.mbn"; +}; + &q6asmdai { dai@0 { reg = <0>; @@ -125,6 +130,10 @@ }; }; +&slpi_pil { + firmware-name = "qcom/msm8996/scorpio/slpi.mbn"; +}; + &sound { compatible = "qcom,apq8096-sndcard"; model = "scorpio"; -- cgit v1.2.3 From 61fd9113f0c743153c76f6bc72938800bbb57ccc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 3 Apr 2022 22:39:11 +0300 Subject: arm64: dts: qcom: apq8096-db820c: enable MSS node APQ8096 provides a 'modem' with reduced functionality, mainly targeting location services. Enable corresponding device tree node. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220403193911.1393920-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts index f623db8451f1..56e54ce4d10e 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts @@ -258,6 +258,12 @@ vdd-gfx-supply = <&vdd_gfx>; }; +&mss_pil { + status = "okay"; + pll-supply = <&vreg_l12a_1p8>; + firmware-name = "qcom/apq8096/mba.mbn", "qcom/apq8096/modem.mbn"; +}; + &pm8994_resin { status = "okay"; linux,code = ; -- cgit v1.2.3 From b4f3996c756ad9e13a6c5ce06c56c2f1dd05768d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 14:58:07 +0300 Subject: arm64: dts: qcom: sdm845: remove snps,dw-pcie compatibles On SDM845 PCI controller bindings are not compatible with snps,dw-pcie binding. The platform doesn't provide second (global) IRQ, it requires additional glue code. To prevent it from probing against the dw-pcie driver, remove corresponding compatible. Fixes: 5c538e09cb19 ("arm64: dts: qcom: sdm845: Add first PCIe controller and PHY") Fixes: 42ad231338c1 ("arm64: dts: qcom: sdm845: Add second PCIe PHY and controller") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411115808.1976500-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index b31bf62e8680..85dfa0842003 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2027,7 +2027,7 @@ }; pcie0: pci@1c00000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c00000 0 0x2000>, <0 0x60000000 0 0xf1d>, <0 0x60000f20 0 0xa8>, @@ -2132,7 +2132,7 @@ }; pcie1: pci@1c08000 { - compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; + compatible = "qcom,pcie-sdm845"; reg = <0 0x01c08000 0 0x2000>, <0 0x40000000 0 0xf1d>, <0 0x40000f20 0 0xa8>, -- cgit v1.2.3 From 66d7cadb7a4362b317764b7bb859ef76bddfe43a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Mon, 11 Apr 2022 14:58:08 +0300 Subject: arm64: dts: qcom: msm8996: remove snps,dw-pcie compatibles On MSM8996 PCI controller bindings are not compatible with snps,dw-pcie binding. The platform doesn't provide second (global) IRQ, it requires additional glue code. To prevent it from probing against the dw-pcie driver, remove corresponding compatible. Fixes: ed965ef89227 ("arm64: dts: qcom: msm8996: add support to pcie") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411115808.1976500-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index e918038e8bd3..1a1539399a87 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1580,7 +1580,7 @@ ranges; pcie0: pcie@600000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; status = "disabled"; power-domains = <&gcc PCIE0_GDSC>; bus-range = <0x00 0xff>; @@ -1632,7 +1632,7 @@ }; pcie1: pcie@608000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE1_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; @@ -1685,7 +1685,7 @@ }; pcie2: pcie@610000 { - compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; + compatible = "qcom,pcie-msm8996"; power-domains = <&gcc PCIE2_GDSC>; bus-range = <0x00 0xff>; num-lanes = <1>; -- cgit v1.2.3 From b36e493cecae89038ccafc59fb45ded3ae8a9bf4 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Apr 2022 23:59:00 +0300 Subject: arm64: dts: qcom: sm8450-hdk: Enable remoteproc instances Enable the audio, compute, sensor and modem remoteproc and specify firmware path for these on the Qualcomm SM8450 HDK. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410205901.1672089-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index f0fcb1428449..34e37991c0c9 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,26 @@ }; }; +&remoteproc_adsp { + status = "okay"; + firmware-name = "qcom/sm8450/adsp.mbn"; +}; + +&remoteproc_cdsp { + status = "okay"; + firmware-name = "qcom/sm8450/cdsp.mbn"; +}; + +&remoteproc_mpss { + status = "okay"; + firmware-name = "qcom/sm8450/modem.mbn"; +}; + +&remoteproc_slpi { + status = "okay"; + firmware-name = "qcom/sm8450/slpi.mbn"; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From 91d70eb70867f3fa4f0380c68253cda9e77e8bfc Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sun, 10 Apr 2022 23:59:01 +0300 Subject: arm64: dts: qcom: sm8450: add fastrpc nodes Add fastrpc device tree nodes for aDSP, cDSP and SLPI. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410205901.1672089-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 119 +++++++++++++++++++++++++++++++++++ 1 file changed, 119 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 934e29b9e153..385892330017 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -887,6 +887,33 @@ label = "slpi"; qcom,remote-pid = <3>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "sdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x0541 0x0>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x0542 0x0>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x0543 0x0>; + /* note: shared-cb = <4> in downstream */ + }; + }; }; }; @@ -927,6 +954,32 @@ label = "lpass"; qcom,remote-pid = <2>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "adsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x1803 0x0>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x1804 0x0>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x1805 0x0>; + }; + }; }; }; @@ -967,6 +1020,72 @@ label = "cdsp"; qcom,remote-pid = <5>; + + fastrpc { + compatible = "qcom,fastrpc"; + qcom,glink-channels = "fastrpcglink-apps-dsp"; + label = "cdsp"; + #address-cells = <1>; + #size-cells = <0>; + + compute-cb@1 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <1>; + iommus = <&apps_smmu 0x2161 0x0400>, + <&apps_smmu 0x1021 0x1420>; + }; + + compute-cb@2 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <2>; + iommus = <&apps_smmu 0x2162 0x0400>, + <&apps_smmu 0x1022 0x1420>; + }; + + compute-cb@3 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <3>; + iommus = <&apps_smmu 0x2163 0x0400>, + <&apps_smmu 0x1023 0x1420>; + }; + + compute-cb@4 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <4>; + iommus = <&apps_smmu 0x2164 0x0400>, + <&apps_smmu 0x1024 0x1420>; + }; + + compute-cb@5 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <5>; + iommus = <&apps_smmu 0x2165 0x0400>, + <&apps_smmu 0x1025 0x1420>; + }; + + compute-cb@6 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <6>; + iommus = <&apps_smmu 0x2166 0x0400>, + <&apps_smmu 0x1026 0x1420>; + }; + + compute-cb@7 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <7>; + iommus = <&apps_smmu 0x2167 0x0400>, + <&apps_smmu 0x1027 0x1420>; + }; + + compute-cb@8 { + compatible = "qcom,fastrpc-compute-cb"; + reg = <8>; + iommus = <&apps_smmu 0x2168 0x0400>, + <&apps_smmu 0x1028 0x1420>; + }; + + /* note: secure cb9 in downstream */ + }; }; }; -- cgit v1.2.3 From 6127d8e4cd096c4f5c8590617e22a2fdc80aee30 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 27 Feb 2022 00:10:28 +0530 Subject: arm64: dts: qcom: sm8150: Add PDC as the interrupt parent for tlmm Several wakeup gpios supported by the Top Level Mode Multiplexer (TLMM) block on sm8150 can be used as interrupt sources and these interrupts are routed to the PDC interrupt controller. So, specify PDC as the interrupt parent for the TLMM block. Cc: Bjorn Andersson Cc: Vinod Koul Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226184028.111566-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index c0128c960950..068cf3e3e89f 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -2247,6 +2247,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; qup_i2c0_default: qup-i2c0-default { mux { -- cgit v1.2.3 From 0e0a8e35d72533b3eef3365e900baacd7cede8e2 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 15 Mar 2022 17:11:04 +0300 Subject: arm64: dts: qcom: sdm845: correct dynamic power coefficients MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Following sm8150/sm8250 update sdm845 capacity-dmips-mhz and dynamic-power-coefficient based on the measurements [1], [2]. The energy model dynamic-power-coefficient values were calculated with DPC = µW / MHz / V^2 for each OPP, and averaged across all OPPs within each cluster for the final coefficient. Voltages were obtained from the qcom-cpufreq-hw driver that reads voltages from the OSM LUT programmed into the SoC. Normalized DMIPS/MHz capacity scale values for each CPU were calculated from CoreMarks/MHz (CoreMark iterations per second per MHz), which serves the same purpose. For each CPU, the final capacity-dmips-mhz value is the C/MHz value of its maximum frequency normalized to SCHED_CAPACITY_SCALE (1024) for the fastest CPU in the system. For more details on measurement process see the commit message for the commit 6aabed5526ee ("arm64: dts: qcom: sm8250: Add CPU capacities and energy model"). [1] https://github.com/kdrag0n/freqbench [2] https://github.com/kdrag0n/freqbench/tree/master/results/sdm845/main Cc: Danny Lin Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220315141104.730235-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 85dfa0842003..a49376d8ecbf 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -200,8 +200,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -225,8 +225,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -247,8 +247,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -269,8 +269,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <607>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <611>; + dynamic-power-coefficient = <290>; qcom,freq-domain = <&cpufreq_hw 0>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -292,7 +292,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -314,7 +314,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -336,7 +336,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, @@ -358,7 +358,7 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - dynamic-power-coefficient = <396>; + dynamic-power-coefficient = <442>; qcom,freq-domain = <&cpufreq_hw 1>; operating-points-v2 = <&cpu4_opp_table>; interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, -- cgit v1.2.3 From 5a814af5fc229b2649c814921a39ae1f652e366d Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 21 Mar 2022 14:33:17 +0100 Subject: arm64: dts: qcom: sm6350: Add UFS nodes Add the necessary nodes for UFS and its PHY. Signed-off-by: Luca Weiss Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220321133318.99406-6-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 81db25952cf1..f6fb97d5ca92 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -633,6 +633,83 @@ }; + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm6350-ufshc", "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>, + <0 0x01d90000 0 0x8000>; + reg-names = "std", "ice"; + interrupts = ; + phys = <&ufs_mem_phy_lanes>; + phy-names = "ufsphy"; + lanes-per-direction = <2>; + #reset-cells = <1>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + power-domains = <&gcc UFS_PHY_GDSC>; + + iommus = <&apps_smmu 0x80 0x0>; + + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk", + "ice_core_clk"; + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_QLINK_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + status = "disabled"; + }; + + ufs_mem_phy: phy@1d87000 { + compatible = "qcom,sm6350-qmp-ufs-phy"; + reg = <0 0x01d87000 0 0x18c>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clock-names = "ref", + "ref_aux"; + clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + status = "disabled"; + + ufs_mem_phy_lanes: phy@1d87400 { + reg = <0 0x01d87400 0 0x128>, + <0 0x01d87600 0 0x1fc>, + <0 0x01d87c00 0 0x1dc>, + <0 0x01d87800 0 0x128>, + <0 0x01d87a00 0 0x1fc>; + #phy-cells = <0>; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- cgit v1.2.3 From 606efee95767b54e8da4cce0429f1587ff1a3cb0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Mon, 21 Mar 2022 14:33:18 +0100 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Enable UFS Configure and enable the nodes for UFS that are used for internal storage on FP4. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220321133318.99406-7-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index 4691a5e5c8e5..f70174a342c6 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -365,6 +365,24 @@ status = "okay"; }; +&ufs_mem_hc { + status = "okay"; + + reset-gpios = <&tlmm 156 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l7e>; + vcc-max-microamp = <800000>; + vccq2-supply = <&vreg_l12a>; + vccq2-max-microamp = <800000>; +}; + +&ufs_mem_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l18a>; + vdda-pll-supply = <&vreg_l22a>; +}; + &usb_1 { status = "okay"; }; -- cgit v1.2.3 From 05f333b746d48c985f6df3c4e7cc8e63a0f30840 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Mar 2022 22:05:36 +0530 Subject: arm64: dts: qcom: sm8150: add ethernet node SM8150 SoC supports ethqos ethernet controller so add the node for it Cc: Bjorn Andersson Signed-off-by: Vinod Koul [bhsharma: Correct ethernet interrupt numbers and add power-domain] Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325163537.1579969-2-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 068cf3e3e89f..f0c550155d03 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -915,6 +915,33 @@ status = "disabled"; }; + ethernet: ethernet@20000 { + compatible = "qcom,sm8150-ethqos"; + reg = <0x0 0x00020000 0x0 0x10000>, + <0x0 0x00036000 0x0 0x100>; + reg-names = "stmmaceth", "rgmii"; + clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; + clocks = <&gcc GCC_EMAC_AXI_CLK>, + <&gcc GCC_EMAC_SLV_AHB_CLK>, + <&gcc GCC_EMAC_PTP_CLK>, + <&gcc GCC_EMAC_RGMII_CLK>; + interrupts = , + ; + interrupt-names = "macirq", "eth_lpi"; + + power-domains = <&gcc EMAC_GDSC>; + resets = <&gcc GCC_EMAC_BCR>; + + iommus = <&apps_smmu 0x3C0 0x0>; + + snps,tso; + rx-fifo-depth = <4096>; + tx-fifo-depth = <4096>; + + status = "disabled"; + }; + + qupv3_id_0: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; -- cgit v1.2.3 From c5cb42cc8411c8313b0265777b90715e6d032ba1 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Fri, 25 Mar 2022 22:05:37 +0530 Subject: arm64: dts: qcom: sa8155p-adp: Enable ethernet node Enable the ethernet node, add the phy node and pinctrl for ethernet. [bhsharma: Correct ethernet/rgmii related pinmuxs, specify multi-queues and plug in the PHY interrupt for WOL] Cc: Bjorn Andersson Signed-off-by: Vinod Koul Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325163537.1579969-3-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 146 +++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8e781125e8d0..8034d0d31bd0 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -47,6 +47,65 @@ vin-supply = <&vreg_3p3>; }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <4>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + + queue1 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x1>; + snps,route-ptp; + }; + + queue2 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x2>; + snps,route-avcp; + }; + + queue3 { + snps,avb-algorithm; + snps,map-to-dma-channel = <0x3>; + snps,priority = <0xC>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <4>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + + queue1 { + snps,weight = <0x11>; + snps,dcb-algorithm; + snps,priority = <0x1>; + }; + + queue2 { + snps,weight = <0x12>; + snps,dcb-algorithm; + snps,priority = <0x2>; + }; + + queue3 { + snps,weight = <0x13>; + snps,dcb-algorithm; + snps,priority = <0x3>; + }; + }; }; &apps_rsc { @@ -303,6 +362,44 @@ }; }; +ðernet { + status = "okay"; + + snps,reset-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 70000>; + + snps,ptp-ref-clk-rate = <250000000>; + snps,ptp-req-clk-rate = <96000000>; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + pinctrl-names = "default"; + pinctrl-0 = <ðernet_defaults>; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii"; + max-speed = <1000>; + + mdio { + #address-cells = <0x1>; + #size-cells = <0x0>; + + compatible = "snps,dwmac-mdio"; + + /* Micrel KSZ9031RNZ PHY */ + rgmii_phy: phy@7 { + reg = <0x7>; + + interrupt-parent = <&tlmm>; + interrupts-extended = <&tlmm 124 IRQ_TYPE_EDGE_FALLING>; /* phy intr */ + device_type = "ethernet-phy"; + compatible = "ethernet-phy-ieee802.3-c22"; + }; + }; +}; + &qupv3_id_1 { status = "okay"; }; @@ -490,4 +587,53 @@ drive-strength = <2>; }; }; + + ethernet_defaults: ethernet-defaults { + mdc { + pins = "gpio7"; + function = "rgmii"; + bias-pull-up; + }; + + mdio { + pins = "gpio59"; + function = "rgmii"; + bias-pull-up; + }; + + rgmii-rx { + pins = "gpio117", "gpio118", "gpio119", "gpio120", "gpio115", "gpio116"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx { + pins = "gpio122", "gpio4", "gpio5", "gpio6", "gpio114", "gpio121"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + + phy-intr { + pins = "gpio124"; + function = "emac_phy"; + bias-disable; + drive-strength = <8>; + }; + + pps { + pins = "gpio81"; + function = "emac_pps"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset { + pins = "gpio79"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + }; }; -- cgit v1.2.3 From e036b77be77d232f41a1f6dd91e4f1f238cbb680 Mon Sep 17 00:00:00 2001 From: Sankeerth Billakanti Date: Wed, 16 Mar 2022 23:05:46 +0530 Subject: arm64: dts: qcom: sc7280: rename edp_out label to mdss_edp_out Rename the edp_out label in the sc7280 platform to mdss_edp_out so that the nodes related to mdss are all grouped together in the board specific files. Signed-off-by: Sankeerth Billakanti Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1647452154-16361-2-git-send-email-quic_sbillaka@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 26f66f46a950..0cb126a7a8d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3393,7 +3393,7 @@ port@1 { reg = <1>; - edp_out: endpoint { }; + mdss_edp_out: endpoint { }; }; }; -- cgit v1.2.3 From 726111e687192575e47de9e286ad0e45e2ce1466 Mon Sep 17 00:00:00 2001 From: Jami Kettunen Date: Fri, 25 Feb 2022 23:56:42 +0200 Subject: arm64: dts: qcom: msm8998-oneplus-common: Add NFC The OnePlus 5/5T both have an NXP PN553 which is supported by the nxp-nci-i2c driver in mainline. It detects/reads NFC tags using "nfctool" and with the NearD test scripts data can also be written to be received by another device. Signed-off-by: Jami Kettunen Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220225215642.3916-1-jami.kettunen@somainline.org --- .../boot/dts/qcom/msm8998-oneplus-common.dtsi | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi index 9823d48a91b1..dbaea360bffc 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-oneplus-common.dtsi @@ -188,6 +188,23 @@ }; }; +&blsp1_i2c6 { + status = "okay"; + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + interrupt-parent = <&tlmm>; + interrupts = <92 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 116 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_int_active &nfc_enable_active>; + }; +}; + &blsp1_uart3 { status = "okay"; @@ -462,6 +479,20 @@ drive-strength = <8>; bias-pull-up; }; + + nfc_int_active: nfc-int-active { + pins = "gpio92"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; + + nfc_enable_active: nfc-enable-active { + pins = "gpio12", "gpio116"; + function = "gpio"; + drive-strength = <6>; + bias-pull-up; + }; }; &ufshc { -- cgit v1.2.3 From a2d2c809cfeeb35b9e0a17940fcee90ff195b592 Mon Sep 17 00:00:00 2001 From: Baruch Siach Date: Mon, 28 Feb 2022 08:58:44 +0200 Subject: arm64: dts: qcom: ipq6018: Add mdio bus description The IPQ60xx has the same MDIO bug block as IPQ4019. Add IO range and clock resources description. Reviewed-by: Bryan O'Donoghue Signed-off-by: Baruch Siach Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/ef01a79ccc6ef86dc3a10d0fa3331794d49e9859.1646031524.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 8032d7933c66..bbe58b92079a 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -630,6 +630,16 @@ }; }; + mdio: mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; + reg = <0x0 0x90000 0x0 0x64>; + clocks = <&gcc GCC_MDIO_AHB_CLK>; + clock-names = "gcc_mdio_ahb_clk"; + status = "disabled"; + }; + qusb_phy_1: qusb@59000 { compatible = "qcom,ipq6018-qusb2-phy"; reg = <0x0 0x059000 0x0 0x180>; -- cgit v1.2.3 From 7a79b95f4288c67b72a1c90c90a4fb6ad6fc0c6d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:29 +0300 Subject: arm64: dts: qcom: pm8350: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 308f9ca7c744..b10f33afa5e3 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pm8350_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350_temp_alarm>; + + trips { + pm8350_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8350: pmic@1 { compatible = "qcom,pm8350", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8350_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x1 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350_gpios: gpio@8800 { compatible = "qcom,pm8350-gpio"; reg = <0x8800>; -- cgit v1.2.3 From 5c1399299d9d82cb378bd22049da0ae08c4efa54 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:30 +0300 Subject: arm64: dts: qcom: pm8350b: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350b.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index b23bb1d49a4d..f1d1d4c8edf8 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pm8350b_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350b_temp_alarm>; + + trips { + pm8350b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pm8350b_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pm8350b: pmic@3 { compatible = "qcom,pm8350b", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pm8350b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x3 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pm8350b_gpios: gpio@8800 { compatible = "qcom,pm8350b-gpio"; reg = <0x8800>; -- cgit v1.2.3 From 6f3426b3dea42abbe8d797560966056303d7cbd6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:31 +0300 Subject: arm64: dts: qcom: pmr735b: add temp sensor and thermal zone config Add temp-alarm device tree node and a default configuration for the corresponding thermal zone for this PMIC. Temperatures are based on downstream values. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pmr735b.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index 1144086280f5..604324188603 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -6,6 +6,30 @@ #include #include +/ { + thermal-zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735b_temp_alarm>; + + trips { + pmr735b_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + pmr735b_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + &spmi_bus { pmr735b: pmic@5 { compatible = "qcom,pmr735b", "qcom,spmi-pmic"; @@ -13,6 +37,13 @@ #address-cells = <1>; #size-cells = <0>; + pmr735b_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + pmr735b_gpios: gpio@8800 { compatible = "qcom,pmr735b-gpio"; reg = <0x8800>; -- cgit v1.2.3 From d67ddd17dedd1b7f1c287a9f32f5db084a7c85eb Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:32 +0300 Subject: arm64: dts: qcom: pm8350c: stop depending on thermal_zones label Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 3795fe7d497b ("arm64: dts: qcom: pm8350c: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index e1b75ae0a823..9bc6464477bd 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -32,23 +32,25 @@ }; }; -&thermal_zones { - pm8350c_thermal: pm8350c-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pm8350c_temp_alarm>; +/ { + thermal-zones { + pm8350c_thermal: pm8350c-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pm8350c_temp_alarm>; - trips { - pm8350c_trip0: trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; + trips { + pm8350c_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; - pm8350c_crit: pm8350c-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; + pm8350c_crit: pm8350c-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3 From 7dc11169a0990f7efcd9515e012f9257aa6035b6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:33 +0300 Subject: arm64: dts: qcom: pmr735a: stop depending on thermal_zones label Most of SoC device trees do not provide the thermal_zones label. Thus stop depending on it and use the full path to the thermal zones nodes. Fixes: 7a3544e5d4e8 ("arm64: dts: qcom: pmr735a: Add temp-alarm support") Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pmr735a.dtsi | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pmr735a.dtsi b/arch/arm64/boot/dts/qcom/pmr735a.dtsi index b4b6ba24f845..febda50779f9 100644 --- a/arch/arm64/boot/dts/qcom/pmr735a.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735a.dtsi @@ -32,23 +32,25 @@ }; }; -&thermal_zones { - pmr735a_thermal: pmr735a-thermal { - polling-delay-passive = <100>; - polling-delay = <0>; - thermal-sensors = <&pmr735a_temp_alarm>; +/ { + thermal-zones { + pmr735a_thermal: pmr735a-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + thermal-sensors = <&pmr735a_temp_alarm>; - trips { - pmr735a_trip0: trip0 { - temperature = <95000>; - hysteresis = <0>; - type = "passive"; - }; + trips { + pmr735a_trip0: trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; - pmr735a_crit: pmr735a-crit { - temperature = <115000>; - hysteresis = <0>; - type = "critical"; + pmr735a_crit: pmr735a-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; }; }; }; -- cgit v1.2.3 From 64d3cb73b317a60d162f08533533aa5f1d9cfe72 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Sat, 26 Feb 2022 23:50:35 +0300 Subject: arm64: dts: qcom: add pm8450 support Add PM8450 PMIC device tree include file. It is going to be used by SM8450-based devices. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226205035.1826360-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8450.dtsi | 59 ++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pm8450.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8450.dtsi b/arch/arm64/boot/dts/qcom/pm8450.dtsi new file mode 100644 index 000000000000..ae5bce3cf46e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pm8450.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include + +/ { + thermal-zones { + pm8450-thermal { + polling-delay-passive = <100>; + polling-delay = <0>; + + thermal-sensors = <&pm8450_temp_alarm>; + + trips { + trip0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <115000>; + hysteresis = <0>; + type = "hot"; + }; + }; + }; + }; +}; + + +&spmi_bus { + pm8450: pmic@7 { + compatible = "qcom,pm8450", "qcom,spmi-pmic"; + reg = <0x7 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pm8450_temp_alarm: temp-alarm@a00 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0xa00>; + interrupts = <0x7 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + #thermal-sensor-cells = <0>; + }; + + pm8450_gpios: gpio@8800 { + compatible = "qcom,pm8450-gpio", "qcom,spmi-gpio"; + reg = <0x8800>; + gpio-controller; + gpio-ranges = <&pm8450_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; -- cgit v1.2.3 From c38406aa46da8f417ee30e6ba1fad71f891ec8be Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 28 Feb 2022 23:54:00 +0100 Subject: arm64: dts: qcom: msm8916: Add BAM-DMUX for WWAN network interfaces The BAM Data Multiplexer provides access to the network data channels of modems integrated into many older Qualcomm SoCs, including MSM8916. Add the nodes for the BAM DMA engine and BAM-DMUX to enable using WWAN on smartphones/tablets based on MSM8916. This should work out of the box with open-source WWAN userspace such as ModemManager. The nodes are disabled by default to avoid loading unnecessary drivers on devices that cannot use BAM-DMUX (e.g. DragonBoard 410c). However, strictly speaking the nodes could be enabled by default since both the bam_dma and bam_dmux driver will simply do nothing if the modem does not announce any BAM-DMUX channels. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228225400.146555-3-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index c2713d307833..0f72349d4067 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1314,6 +1314,20 @@ #interrupt-cells = <4>; }; + bam_dmux_dma: dma-controller@4044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x04044000 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + + status = "disabled"; + }; + mpss: remoteproc@4080000 { compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil"; reg = <0x04080000 0x100>, @@ -1357,6 +1371,22 @@ memory-region = <&mpss_mem>; }; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupt-parent = <&hexagon_smsm>; + interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + + status = "disabled"; + }; + smd-edge { interrupts = ; -- cgit v1.2.3 From cde8b4d070bd98587f5e13a5a5e63e88cfe31322 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:14 +0530 Subject: arm64: dts: qcom: msm8996-xiaomi: Drop max-microamp and vddp-ref-clk properties from QMP PHY The following properties are not supported and causing dtbs_check warnings. - vdda-phy-max-microamp - vdda-pll-max-microamp - vddp-ref-clk-max-microamp - vddp-ref-clk-always-on arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dt.yaml: phy@627000: 'vdda-phy-max-microamp', 'vddp-ref-clk-always-on', 'vddp-ref-clk-max-microamp' do not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Drop them from QMP PHY nodes for 'msm8996-xiaomi' dts. Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-4-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi index fdb70227c0fa..be4f643b1fd1 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -348,12 +348,7 @@ vdda-phy-supply = <&vreg_l28a_0p925>; vdda-pll-supply = <&vreg_l12a_1p8>; - - vdda-phy-max-microamp = <18380>; - vdda-pll-max-microamp = <9440>; - vddp-ref-clk-supply = <&vreg_l25a_1p2>; - vddp-ref-clk-always-on; }; &venus { -- cgit v1.2.3 From 56205c56ea2a050ee6a237ba686cea0b38860c84 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:15 +0530 Subject: arm64: dts: qcom: sc7280: Fix qmp phy node (use phy@ instead of lanes@) Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sc7280-idp.dt.yaml: phy@1c0e000: 'lanes@1c0e200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 0cb126a7a8d0..ebbf4a41a63d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1949,7 +1949,7 @@ status = "disabled"; - pcie1_lane: lanes@1c0e200 { + pcie1_lane: phy@1c0e200 { reg = <0 0x01c0e200 0 0x170>, <0 0x01c0e400 0 0x200>, <0 0x01c0ea00 0 0x1f0>, -- cgit v1.2.3 From c769a3521dd5b8605b35ed246b7a0cb4567cdec4 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:16 +0530 Subject: arm64: dts: qcom: sm8450: Fix qmp ufs phy node (use phy@ instead of lanes@) Fix the 'make dtbs_check' warning: arch/arm64/boot/dts/qcom/sm8450-qrd.dt.yaml: phy@1d87000: 'lanes@1d87400' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-6-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 385892330017..b576d34ca40e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1544,7 +1544,7 @@ reset-names = "ufsphy"; status = "disabled"; - ufs_mem_phy_lanes: lanes@1d87400 { + ufs_mem_phy_lanes: phy@1d87400 { reg = <0 0x01d87400 0 0x108>, <0 0x01d87600 0 0x1e0>, <0 0x01d87c00 0 0x1dc>, -- cgit v1.2.3 From 7011db96f69316e8055961b366ac92b6c28403dd Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Mon, 28 Feb 2022 18:00:17 +0530 Subject: arm64: dts: qcom: ipq6018: Fix qmp usb3 phy node Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@ and by moving '#clock-cells' to sub-node: arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml: ssphy@78000: 'lane@78200' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Reviewed-by: Shawn Guo [bjorn: s/clock-names/clock-cells/ per Shawn's feedback] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220228123019.382037-7-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index bbe58b92079a..a4d363c187fc 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -693,7 +693,6 @@ reg = <0x0 0x78000 0x0 0x1C4>; #address-cells = <2>; #size-cells = <2>; - #clock-cells = <1>; ranges; clocks = <&gcc GCC_USB0_AUX_CLK>, @@ -705,12 +704,13 @@ reset-names = "phy","common"; status = "disabled"; - usb0_ssphy: lane@78200 { + usb0_ssphy: phy@78200 { reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ <0x0 0x00078400 0x0 0x200>, /* Rx */ <0x0 0x00078800 0x0 0x1F8>, /* PCS */ <0x0 0x00078600 0x0 0x044>; /* PCS misc */ #phy-cells = <0>; + #clock-cells = <1>; clocks = <&gcc GCC_USB0_PIPE_CLK>; clock-names = "pipe0"; clock-output-names = "gcc_usb0_pipe_clk_src"; -- cgit v1.2.3 From 5a026558d2a994a5e58ca6fcab34008b95fea7e1 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 11 Apr 2022 14:13:39 -0700 Subject: arm64: dts: qcom: sc7280-herobrine: Audio codec wants 1.8V, not 1.62V The L2C rail on herobrine boards is intended to go to the audio codec. Let's override the 1.62V specified in the qcard.dtsi file to be 1.8V. Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411141332.v2.1.I9f06fec63b978699fe62591fec9e5ac31bb3a69d@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index 10de5e104b4f..d58045dd7334 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -308,7 +308,10 @@ }; /* - * BOARD-LOCAL NAMES FOR REGULATORS THAT CONNECT TO QCARD + * ADJUSTMENTS TO QCARD REGULATORS + * + * Mostly this is just board-local names for regulators that come from + * Qcard, but this also has some minor regulator overrides. * * Names are only listed here if regulators go somewhere other than a * testpoint. @@ -352,6 +355,16 @@ vreg_edp_bl: &ppvar_sys {}; ts_avdd: &pp3300_left_in_mlb {}; vreg_edp_3p3: &pp3300_left_in_mlb {}; +/* Regulator overrides from Qcard */ + +/* + * Herobrine boards only use l2c to power an external audio codec (like + * alc5682) and we want that to be at 1.8V, not at some slightly lower voltage. + */ +&vreg_l2c_1p8 { + regulator-min-microvolt = <1800000>; +}; + /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ ap_sar_sensor_i2c: &i2c1 { -- cgit v1.2.3 From 959cb513074386954629cbdc914612d6ff755b8c Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Tue, 12 Apr 2022 16:02:08 +0530 Subject: arm64: dts: qcom: sc7280: Add reset entries for SDCC controllers Add gcc hardware reset entries for eMMC and SD card. Signed-off-by: Shaik Sajida Bhanu Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649759528-15125-3-git-send-email-quic_c_sbhanu@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ebbf4a41a63d..ce766a86e146 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -886,6 +886,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + resets = <&gcc GCC_SDCC1_BCR>; + sdhc1_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2732,6 +2734,8 @@ qcom,dll-config = <0x0007642c>; + resets = <&gcc GCC_SDCC2_BCR>; + sdhc2_opp_table: opp-table { compatible = "operating-points-v2"; -- cgit v1.2.3 From 551b614e235389063341b47f3b5bade763353589 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 22 Feb 2022 02:48:05 +0100 Subject: arm64: dts: qcom: sm8250-edo: Add dual CS35L41 amps Add nodes for dual Cirrus Logic CS35L41 audio amps connected via I2C. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220222014806.22446-1-konrad.dybcio@somainline.org --- .../boot/dts/qcom/sm8250-sony-xperia-edo.dtsi | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi index d63f7a9bc4e9..e819b5b77363 100644 --- a/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250-sony-xperia-edo.dtsi @@ -441,7 +441,35 @@ status = "okay"; clock-frequency = <1000000>; - /* Dual Cirrus Logic CS35L41 amps @ 40, 41 */ + cs35l41_l: cs35l41@40 { + compatible = "cirrus,cs35l41"; + reg = <0x40>; + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; + + cs35l41_r: cs35l41@41 { + compatible = "cirrus,cs35l41"; + reg = <0x41>; + interrupt-parent = <&tlmm>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>; + cirrus,boost-peak-milliamp = <4000>; + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-cap-microfarad = <15>; + cirrus,asp-sdout-hiz = <3>; + cirrus,gpio2-src-select = <2>; + cirrus,gpio2-output-enable; + #sound-dai-cells = <1>; + }; }; &i2c5 { -- cgit v1.2.3 From d317344d6e5ecc8cfa90463e801f9ec60bb4ef50 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 10 Apr 2022 21:51:12 +0200 Subject: arm64: dts: qcom: msm8916-huawei-g7: Clarify installation instructions The comment with installation instructions in the huawei-g7 device tree is a bit misleading and does not describe the recommended installation steps very well. The bootloader is actually not patched; to avoid all trouble with the vendor bootloader it is easier to bypass it completely by jumping to a custom bootloader (e.g. based on the open-source LK released by Qualcomm). To avoid confusion, simplify the comment to state only the problem and then refer to the wiki article which contains detailed suggested installation instructions. This will also make it easier to keep it up to date with new developments in the future. Fixes: 55056b229189 ("arm64: dts: qcom: msm8916: Add device tree for Huawei Ascend G7") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410195113.13646-2-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 42d93d3fba36..8ad9eb436a0c 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -11,15 +11,10 @@ /* * Note: The original firmware from Huawei can only boot 32-bit kernels. - * To boot arm64 kernels it is necessary to flash 64-bit TZ/HYP firmware - * with EDL, e.g. taken from the DragonBoard 410c. This works because Huawei - * forgot to set up (firmware) secure boot for some reason. - * - * Also note that Huawei no longer provides bootloader unlock codes. - * This can be bypassed by patching the bootloader from a custom HYP firmware, - * making it think the bootloader is unlocked. - * - * See: https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + * To boot this device tree using arm64 it is necessary to flash 64-bit TZ/HYP + * firmware (e.g. taken from the DragonBoard 410c). + * See https://wiki.postmarketos.org/wiki/Huawei_Ascend_G7_(huawei-g7) + * for suggested installation instructions. */ / { -- cgit v1.2.3 From 372c1c3dd709700bdec6c0d377363783fc7c1618 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Sun, 10 Apr 2022 21:51:13 +0200 Subject: arm64: dts: qcom: msm8916-huawei-g7: Add sound card The huawei-g7 uses the msm8916-wcd-digital/analog audio codecs similar to apq8016-sbc, so we can mostly copy paste it from there to make audio work correctly. The main difference is the hphl-jack-type-normally-open property, which is needed to avoid inverted audio jack detection. Note that at least on my device the jack detection is not fully reliable: sometimes headphones are detected as headsets (with microphone). However, this is not a big problem for typical usage. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410195113.13646-3-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts index 8ad9eb436a0c..00488afb413d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts @@ -8,6 +8,7 @@ #include #include #include +#include /* * Note: The original firmware from Huawei can only boot 32-bit kernels. @@ -211,6 +212,10 @@ status = "okay"; }; +&lpass { + status = "okay"; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -255,6 +260,40 @@ cd-gpios = <&msmgpio 56 GPIO_ACTIVE_LOW>; }; +&sound { + status = "okay"; + + model = "msm8916"; + audio-routing = + "AMIC1", "MIC BIAS External1", + "AMIC2", "MIC BIAS External2", + "AMIC3", "MIC BIAS External1"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cdc_pdm_lines_act>; + pinctrl-1 = <&cdc_pdm_lines_sus>; + + primary-dai-link { + link-name = "WCD"; + cpu { + sound-dai = <&lpass MI2S_PRIMARY>; + }; + codec { + sound-dai = <&lpass_codec 0>, <&wcd_codec 0>; + }; + }; + + tertiary-dai-link { + link-name = "WCD-Capture"; + cpu { + sound-dai = <&lpass MI2S_TERTIARY>; + }; + codec { + sound-dai = <&lpass_codec 1>, <&wcd_codec 1>; + }; + }; +}; + &usb { status = "okay"; extcon = <&usb_id>, <&usb_id>; @@ -264,6 +303,13 @@ extcon = <&usb_id>; }; +&wcd_codec { + qcom,micbias-lvl = <2800>; + qcom,mbhc-vthreshold-low = <75 150 237 450 500>; + qcom,mbhc-vthreshold-high = <75 150 237 450 500>; + qcom,hphl-jack-type-normally-open; +}; + &smd_rpm_regulators { vdd_l1_l2_l3-supply = <&pm8916_s3>; vdd_l4_l5_l6-supply = <&pm8916_s4>; -- cgit v1.2.3 From 095a7137ba3630bcca11e6017bfd4ab48b7fc12e Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Sun, 10 Apr 2022 23:20:53 +0530 Subject: arm64: dts: qcom: msm8996: User generic node name for DMA Qcom BAM DT spec expects generic DMA controller node name as "dma-controller" to enable validations. Signed-off-by: Kuldeep Singh Reviewed-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410175056.79330-4-singh.kuldeep87k@gmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1a1539399a87..b7eaab8b325a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -713,7 +713,7 @@ #thermal-sensor-cells = <1>; }; - cryptobam: dma@644000 { + cryptobam: dma-controller@644000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00644000 0x24000>; interrupts = ; -- cgit v1.2.3 From 9499240d15f29760d2271371eea963ca6f761463 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 2 Feb 2022 11:02:07 +0530 Subject: arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers Add the low pass audio clock controller device nodes. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220202053207.14256-1-tdas@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 43 ++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ce766a86e146..e6571de5d293 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -8,6 +8,8 @@ #include #include #include +#include +#include #include #include #include @@ -2028,6 +2030,47 @@ #clock-cells = <1>; }; + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc7280-lpassaudiocc"; + reg = <0 0x03300000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; + clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; + power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_aon: clock-controller@3380000 { + compatible = "qcom,sc7280-lpassaoncc"; + reg = <0 0x03380000 0 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&lpasscore LPASS_CORE_CC_CORE_CLK>; + clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpasscore: clock-controller@3900000 { + compatible = "qcom,sc7280-lpasscorecc"; + reg = <0 0x03900000 0 0x50000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + + lpass_hm: clock-controller@3c00000 { + compatible = "qcom,sc7280-lpasshm"; + reg = <0 0x3c00000 0 0x28>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #power-domain-cells = <1>; + }; + lpass_ag_noc: interconnect@3c40000 { reg = <0 0x03c40000 0 0xf080>; compatible = "qcom,sc7280-lpass-ag-noc"; -- cgit v1.2.3 From d41a72c24ce3fdbbc75d13e90700d6878cbad49c Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:54 +0300 Subject: arm64: dts: qcom: sm8450: add PCIe0 PHY node Add device tree node for the first PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index b576d34ca40e..cd881156a666 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -683,8 +683,12 @@ #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - clock-names = "bi_tcxo", "sleep_clk"; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&pcie0_lane>, + <&sleep_clk>; + clock-names = "bi_tcxo", + "pcie_0_pipe_clk", + "sleep_clk"; }; qupv3_id_0: geniqup@9c0000 { @@ -750,6 +754,40 @@ }; }; + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; + reg = <0 0x01c06000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie0_lane: lanes@1c06200 { + reg = <0 0x1c06e00 0 0x200>, /* tx */ + <0 0x1c07000 0 0x200>, /* rx */ + <0 0x1c06200 0 0x200>, /* pcs */ + <0 0x1c06600 0 0x200>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_0_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; -- cgit v1.2.3 From 7b09b1b47335b7a6d869df6b77a55cdc2b75e14e Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:55 +0300 Subject: arm64: dts: qcom: sm8450: add PCIe0 RC device Add device tree node for the first PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Acked-by: Manivannan Sadhasivam Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 98 ++++++++++++++++++++++++++++++++++++ 1 file changed, 98 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index cd881156a666..d79ad52f4338 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -754,6 +754,81 @@ }; }; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-sm8450-pcie0"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, + <&pcie0_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre0", + "aggre1"; + + iommus = <&apps_smmu 0x1c00 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, + <0x100 &apps_smmu 0x1c01 0x1>; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_0_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie0_lane>; + phy-names = "pciephy"; + + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_default_state>; + + status = "disabled"; + }; + pcie0_phy: phy@1c06000 { compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; reg = <0 0x01c06000 0 0x200>; @@ -1208,6 +1283,29 @@ gpio-ranges = <&tlmm 0 0 211>; wakeup-parent = <&pdc>; + pcie0_default_state: pcie0-default-state { + perst { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio95"; + function = "pcie0_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; -- cgit v1.2.3 From 334d91d2410d76b9045d3821bc02ae92a9e0b23b Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:56 +0300 Subject: arm64: dts: qcom: sm8450: add PCIe1 PHY node Add device tree node for the second PCIe PHY device found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 38 ++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d79ad52f4338..4a40045fa480 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -685,9 +685,11 @@ #power-domain-cells = <1>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie0_lane>, + <&pcie1_lane>, <&sleep_clk>; clock-names = "bi_tcxo", "pcie_0_pipe_clk", + "pcie_1_pipe_clk", "sleep_clk"; }; @@ -863,6 +865,42 @@ }; }; + pcie1_phy: phy@1c0f000 { + compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; + reg = <0 0x01c0f000 0 0x200>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + clock-names = "aux", "cfg_ahb", "ref", "refgen"; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + status = "disabled"; + + pcie1_lane: lanes@1c0e000 { + reg = <0 0x1c0e000 0 0x200>, /* tx */ + <0 0x1c0e200 0 0x300>, /* rx */ + <0 0x1c0f200 0 0x200>, /* pcs */ + <0 0x1c0e800 0 0x200>, /* tx */ + <0 0x1c0ea00 0 0x300>, /* rx */ + <0 0x1c0f400 0 0xc00>; /* pcs_pcie */ + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "pipe0"; + + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "pcie_1_pipe_clk"; + }; + }; + config_noc: interconnect@1500000 { compatible = "qcom,sm8450-config-noc"; reg = <0 0x01500000 0 0x1c000>; -- cgit v1.2.3 From bc6588bc25fb30b25125660d39222d3ca4a44eb6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:57 +0300 Subject: arm64: dts: qcom: sm8450: add PCIe1 root device Add device tree node for the second PCIe host found on the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 96 ++++++++++++++++++++++++++++++++++++ 1 file changed, 96 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 4a40045fa480..2cfc67b75259 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -865,6 +865,79 @@ }; }; + pcie1: pci@1c08000 { + compatible = "qcom,pcie-sm8450-pcie1"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + device_type = "pci"; + linux,pci-domain = <1>; + bus-range = <0x00 0xff>; + num-lanes = <2>; + + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x01000000 0x0 0x40200000 0 0x40200000 0x0 0x100000>, + <0x02000000 0x0 0x40300000 0 0x40300000 0x0 0x1fd00000>; + + interrupts = ; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie1_lane>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; + clock-names = "pipe", + "pipe_mux", + "phy_pipe", + "ref", + "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "aggre1"; + + iommus = <&apps_smmu 0x1c80 0x7f>; + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, + <0x100 &apps_smmu 0x1c81 0x1>; + + resets = <&gcc GCC_PCIE_1_BCR>; + reset-names = "pci"; + + power-domains = <&gcc PCIE_1_GDSC>; + power-domain-names = "gdsc"; + + phys = <&pcie1_lane>; + phy-names = "pciephy"; + + perst-gpio = <&tlmm 97 GPIO_ACTIVE_LOW>; + enable-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_default_state>; + + status = "disabled"; + }; + pcie1_phy: phy@1c0f000 { compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; reg = <0 0x01c0f000 0 0x200>; @@ -1344,6 +1417,29 @@ }; }; + pcie1_default_state: pcie1-default-state { + perst { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq { + pins = "gpio98"; + function = "pcie1_clkreqn"; + drive-strength = <2>; + bias-pull-up; + }; + + wake { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; -- cgit v1.2.3 From 3795221250b60b1a3a9f60a22fd447f2f9e17b57 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:58 +0300 Subject: arm64: dts: qcom: sm8450-qrd: enable PCIe0 PHY device Enable PCIe0 PHY on the SM8450 QRD device. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-6-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 9526632d4029..7b6324969a4e 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -342,6 +342,12 @@ }; }; +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit v1.2.3 From bce9887e0f4e4ef4ffc5a5af4d7b6769fa18c949 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:14:59 +0300 Subject: arm64: dts: qcom: sm8450-qrd: enable PCIe0 host Enable PCIe0 host on SM8450 QRD device. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-7-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index 7b6324969a4e..d33e86a375c0 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -342,6 +342,10 @@ }; }; +&pcie0 { + status = "okay"; +}; + &pcie0_phy { status = "okay"; vdda-phy-supply = <&vreg_l5b_0p88>; -- cgit v1.2.3 From 37ebe34fc04e62a019006912d49e0b5fb0731986 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Tue, 1 Mar 2022 09:15:00 +0300 Subject: arm64: dts: qcom: sm8450-hdk: add pcie nodes Add device tree nodes for PCIe0/PCIe1 controllers and corresponding PHYs. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220301061500.2110569-8-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index 34e37991c0c9..4e51a9d6af98 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -349,6 +349,27 @@ }; }; +&pcie0 { + status = "okay"; + max-link-speed = <2>; +}; + +&pcie0_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l5b_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + +&pcie1 { + status = "okay"; +}; + +&pcie1_phy { + status = "okay"; + vdda-phy-supply = <&vreg_l2h_0p91>; + vdda-pll-supply = <&vreg_l6b_1p2>; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; -- cgit v1.2.3 From 7b36ab2673b359d1daf4da9e42597edc5ef866fa Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:06 +0300 Subject: arm64: dts: qcom: msm8996: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 12d540375736 ("arm64: dts: qcom: msm8996: Add DSI0 nodes") Fixes: 3a4547c1fc2f ("arm64: qcom: msm8996.dtsi: Add Display nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index b7eaab8b325a..67d2253e2c35 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -794,7 +794,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; clocks = <&mmcc MDSS_AHB_CLK>, <&mmcc MDSS_AXI_CLK>, @@ -840,7 +840,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_BYTE0_CLK>, @@ -910,7 +910,7 @@ "hdcp_physical"; interrupt-parent = <&mdss>; - interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <8>; clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_AHB_CLK>, -- cgit v1.2.3 From 2a11b3bfc51ac4d5dcb17a22dd98741f26350e5f Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:07 +0300 Subject: arm64: dts: qcom: sdm630: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: b52555d590d1 ("arm64: dts: qcom: sdm630: Add MDSS nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm630.dtsi b/arch/arm64/boot/dts/qcom/sdm630.dtsi index 240293592ef9..7f875bf9390a 100644 --- a/arch/arm64/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630.dtsi @@ -1453,7 +1453,7 @@ reg-names = "mdp_phys"; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; assigned-clocks = <&mmcc MDSS_MDP_CLK>, <&mmcc MDSS_VSYNC_CLK>; @@ -1530,7 +1530,7 @@ power-domains = <&rpmpd SDM660_VDDCX>; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>; -- cgit v1.2.3 From 63ddd8a54d4be02976e63ff06bb1cc98226c6981 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:08 +0300 Subject: arm64: dts: qcom: sdm660: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: ab290284398d ("arm64: dts: qcom: sdm660: Add required nodes for DSI1") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm660.dtsi b/arch/arm64/boot/dts/qcom/sdm660.dtsi index eccf6fde16b4..1d748c5305f4 100644 --- a/arch/arm64/boot/dts/qcom/sdm660.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm660.dtsi @@ -163,7 +163,7 @@ power-domains = <&rpmpd SDM660_VDDCX>; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; -- cgit v1.2.3 From 0316da6bbcb7d78017f8f177399bff5ff889456a Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:09 +0300 Subject: arm64: dts: qcom: sdm845: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 08c2a076d18f ("arm64: dts: qcom: sdm845: Add dpu to sdm845 dts file") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-4-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index a49376d8ecbf..692cf4be4eef 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4283,7 +4283,7 @@ power-domains = <&rpmhpd SDM845_CX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -4335,7 +4335,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -4407,7 +4407,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, -- cgit v1.2.3 From be633329928a3b33d91b3cd2b41e9b7f522d1416 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 3 Mar 2022 01:54:10 +0300 Subject: arm64: dts: qcom: sm8250: Drop flags for mdss irqs The number of interrupt cells for the mdss interrupt controller is 1, meaning there should only be one cell for the interrupt number, not two. Drop the second cell containing (unused) irq flags. Reviewed-by: Stephen Boyd Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes") Signed-off-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Abhinav Kumar Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220302225411.2456001-5-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index af8f22636436..33ea5ed4c0f5 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3202,7 +3202,7 @@ power-domains = <&rpmhpd SM8250_MMCX>; interrupt-parent = <&mdss>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <0>; ports { #address-cells = <1>; @@ -3254,7 +3254,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <4>; clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, @@ -3327,7 +3327,7 @@ reg-names = "dsi_ctrl"; interrupt-parent = <&mdss>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <5>; clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, -- cgit v1.2.3 From f607dd767f5d6800ffbdce5b99ba81763b023781 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Fri, 11 Feb 2022 17:44:15 +0530 Subject: arm64: dts: qcom: ipq8074: fix the sleep clock frequency Sleep clock frequency should be 32768Hz. Lets fix it. Cc: stable@vger.kernel.org Fixes: 41dac73e243d ("arm64: dts: Add ipq8074 SoC and HK01 board support") Link: https://lore.kernel.org/all/e2a447f8-6024-0369-f698-2027b6edcf9e@codeaurora.org/ Signed-off-by: Kathiravan T Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1644581655-11568-1-git-send-email-quic_kathirav@quicinc.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 8e41c910b8f9..943243d5515b 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -13,7 +13,7 @@ clocks { sleep_clk: sleep_clk { compatible = "fixed-clock"; - clock-frequency = <32000>; + clock-frequency = <32768>; #clock-cells = <0>; }; -- cgit v1.2.3 From 3bfef00d767124838b4b285de8da66fdf395da0d Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Sat, 26 Feb 2022 00:51:32 +0530 Subject: arm64: dts: qcom: sc7280: Support gpu speedbin Add speedbin fuse and additional OPPs for gpu to support sc7280 SKUs. Signed-off-by: Akhil P Oommen Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220226005021.v2.5.I4c2cb95f06f0c37038c80cc1ad20563fdf0618e2@changeid --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 46 ++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e6571de5d293..9ece35736515 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -849,6 +849,11 @@ power-domains = <&rpmhpd SC7280_MX>; #address-cells = <1>; #size-cells = <1>; + + gpu_speed_bin: gpu_speed_bin@1e9 { + reg = <0x1e9 0x2>; + bits = <5 8>; + }; }; sdhc_1: sdhci@7c4000 { @@ -2094,6 +2099,9 @@ interconnect-names = "gfx-mem"; #cooling-cells = <2>; + nvmem-cells = <&gpu_speed_bin>; + nvmem-cell-names = "speed_bin"; + gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2101,18 +2109,56 @@ opp-hz = /bits/ 64 <315000000>; opp-level = ; opp-peak-kBps = <1804000>; + opp-supported-hw = <0x03>; }; opp-450000000 { opp-hz = /bits/ 64 <450000000>; opp-level = ; opp-peak-kBps = <4068000>; + opp-supported-hw = <0x03>; }; opp-550000000 { opp-hz = /bits/ 64 <550000000>; opp-level = ; opp-peak-kBps = <6832000>; + opp-supported-hw = <0x03>; + }; + + opp-608000000 { + opp-hz = /bits/ 64 <608000000>; + opp-level = ; + opp-peak-kBps = <8368000>; + opp-supported-hw = <0x02>; + }; + + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-812000000 { + opp-hz = /bits/ 64 <812000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-840000000 { + opp-hz = /bits/ 64 <840000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; + }; + + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-level = ; + opp-peak-kBps = <8532000>; + opp-supported-hw = <0x02>; }; }; }; -- cgit v1.2.3 From 5827e28304673444f8e1cf426c2b08cc16382290 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:31 +0100 Subject: arm64: dts: qcom: msm8994: Fix sleep clock name The sleep clock name expected by GCC is actually "sleep" and not "sleep_clk". Fix the clock-names value for it to make sure it is provided. Fixes: 9204da57cd65 ("arm64: dts: qcom: msm8994: Provide missing "xo_board" and "sleep_clk" to GCC") Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-2-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 209f9ef030e5..499f169ae773 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -714,7 +714,7 @@ #power-domain-cells = <1>; reg = <0xfc400000 0x2000>; - clock-names = "xo", "sleep_clk"; + clock-names = "xo", "sleep"; clocks = <&xo_board>, <&sleep_clk>; }; -- cgit v1.2.3 From 13cff03303676148bc8f0bbe73a6d40d5fdd020e Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:32 +0100 Subject: arm64: dts: qcom: msm8992-libra: Add CPU regulators Specify CPU regulator voltages for both VDD_APC rails. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-3-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 84558ab5fe86..6371719aacc5 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -126,6 +126,23 @@ no-map; }; +&pm8994_spmi_regulators { + VDD_APC0: s8 { + regulator-min-microvolt = <680000>; + regulator-max-microvolt = <1180000>; + regulator-always-on; + regulator-boot-on; + }; + + /* APC1 is 3-phase, but quoting downstream, s11 is "the gang leader" */ + VDD_APC1: s11 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; +}; + &rpm_requests { pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; -- cgit v1.2.3 From ed288ae94af0875fba3934893ae3490387d4adc1 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:33 +0100 Subject: arm64: dts: qcom: msm8992-libra: Temporarily restrict CPU count to 1 The phone seems to randomly crash when more than 1 CPU is enabled, which is probably related to lack of some driver. Restrict the device to only use a single core until this is solved. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-4-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 6371719aacc5..7a6ed8b017d1 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -23,7 +23,7 @@ /* This enables graphical output via bootloader-enabled display */ chosen { - bootargs = "earlycon=tty0 console=tty0"; + bootargs = "earlycon=tty0 console=tty0 maxcpus=1"; #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 2d0f45f760fe8ff5c9b7b58640bd4d665aac80f7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:34 +0100 Subject: arm64: dts: qcom: msm8992-libra: Remove superfluous status = "okay" The framebuffer is already enabled by default. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-5-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index 7a6ed8b017d1..e638fc489539 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -30,7 +30,6 @@ ranges; framebuffer0: framebuffer@3404000 { - status= "okay"; compatible = "simple-framebuffer"; reg = <0 0x3404000 0 (1080 * 1920 * 3)>; width = <1080>; -- cgit v1.2.3 From e9b0eb542027195382c27158ffc83ef77cfb5ba6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:35 +0100 Subject: arm64: dts: qcom: msm8994: Add MMCC node Describe the Multimedia Clock Controller block in the DT. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-6-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 499f169ae773..096bde7bb4f1 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -4,6 +4,8 @@ #include #include +#include +#include #include / { @@ -1012,6 +1014,44 @@ drive-strength = <2>; }; }; + + mmcc: clock-controller@fd8c0000 { + compatible = "qcom,mmcc-msm8994"; + reg = <0xfd8c0000 0x5200>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + clock-names = "xo", + "gpll0", + "mmssnoc_ahb", + "oxili_gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll"; + clocks = <&xo_board>, + <&gcc GPLL0_OUT_MMSSCC>, + <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <0>, + <0>, + <0>, + <0>, + <0>; + + assigned-clocks = <&mmcc MMPLL0_PLL>, + <&mmcc MMPLL1_PLL>, + <&mmcc MMPLL3_PLL>, + <&mmcc MMPLL4_PLL>, + <&mmcc MMPLL5_PLL>; + assigned-clock-rates = <800000000>, + <1167000000>, + <1020000000>, + <960000000>, + <600000000>; + }; }; timer: timer { -- cgit v1.2.3 From 355ea704c887303aa1a4b3c8e228cb7ccc2d54c0 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:36 +0100 Subject: arm64: dts: qcom: msm8992: Use the correct GCC compatible Now that proper msm8992 support is in the driver, switch to the new compatible. Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-7-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 58fe58cc7703..1b175b7f1514 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -10,6 +10,10 @@ /delete-node/ &cpu6_map; /delete-node/ &cpu7_map; +&gcc { + compatible = "qcom,gcc-msm8992"; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; -- cgit v1.2.3 From b0b5687a2ce5b27dc76acda2b48415c69b5a5a95 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:37 +0100 Subject: arm64: dts: qcom: msm8992: Use the correct MMCC compatible Now that proper msm8992 support is in the driver, switch to the new compatible. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-8-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 1b175b7f1514..1de1d9c4643d 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -14,6 +14,16 @@ compatible = "qcom,gcc-msm8992"; }; +&mmcc { + compatible = "qcom,mmcc-msm8992"; + + assigned-clock-rates = <800000000>, + <808000000>, + <1020000000>, + <960000000>, + <800000000>; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; -- cgit v1.2.3 From 049c46f31a726bf8d202ff1681661513447fac84 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:38 +0100 Subject: arm64: dts: qcom: msm8994: Fix the cont_splash_mem address The default memory map places cont_splash_mem at 3401000, which was overlooked.. Fix it! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-9-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 096bde7bb4f1..18cf05535229 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -185,8 +185,8 @@ no-map; }; - cont_splash_mem: memory@3800000 { - reg = <0 0x03800000 0 0x2400000>; + cont_splash_mem: memory@3401000 { + reg = <0 0x03401000 0 0x2200000>; no-map; }; -- cgit v1.2.3 From 9e398b4c4ed8f926fcbd9d7d8013d6620d9833ea Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:39 +0100 Subject: arm64: dts: qcom: msm8992-libra: Fix up the framebuffer Make sure the necessary clocks are kept on after clk_cleanup (until MDSS is properly handled by its own driver) and touch up the fb address to prevent some weird shifting. It's still not perfect, but at least the kernel log doesn't start a third deep into your screen.. Signed-off-by: Konrad Dybcio [bjorn: Folded in change of framebuffer base address, from Konrad] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-10-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts index e638fc489539..7748b745a5df 100644 --- a/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts +++ b/arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts @@ -29,13 +29,25 @@ #size-cells = <2>; ranges; - framebuffer0: framebuffer@3404000 { + framebuffer0: framebuffer@3400000 { compatible = "simple-framebuffer"; - reg = <0 0x3404000 0 (1080 * 1920 * 3)>; + reg = <0 0x3400000 0 (1080 * 1920 * 3)>; width = <1080>; height = <1920>; stride = <(1080 * 3)>; format = "r8g8b8"; + /* + * That's a lot of clocks, but it's necessary due + * to unused clk cleanup & no panel driver yet.. + */ + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>; + power-domains = <&mmcc MDSS_GDSC>; }; }; -- cgit v1.2.3 From 7d9379bf1ecfbf0a7b30a773137006b04a713dd4 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:40 +0100 Subject: arm64: dts: qcom: msm8994-kitakami: Disable a mistakengly enabled I2C host I2C4 turns out not to be used on Kitakami after all and it only blocks a GPIO used by camera hardware. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-11-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index dde7ed159c4d..5e93ab0a649b 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -108,13 +108,6 @@ /* NXP PN547 NFC */ }; -&blsp1_i2c4 { - status = "okay"; - clock-frequency = <355000>; - - /* Empty but active */ -}; - &blsp1_i2c6 { status = "okay"; clock-frequency = <355000>; -- cgit v1.2.3 From 410e1619d51720ee5efa7ef59e4784128ee9801a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:41 +0100 Subject: arm64: dts: qcom: msm8994-kitakami: Update regulator configuration Remove regulator-always-on property where not necessary and mark regulators that are not supposed to be voted active on boot with regulator-boot-on. While at it, reorder the load properties to make it look more decent. Reorder PMICs to fix a probe defer caused by messy dependencies and Linux's inability to handle them (at least for now). Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-12-konrad.dybcio@somainline.org --- .../dts/qcom/msm8994-sony-xperia-kitakami.dtsi | 82 ++++++++++++---------- 1 file changed, 44 insertions(+), 38 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi index 5e93ab0a649b..e5a45af0bd12 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi @@ -187,26 +187,38 @@ }; &rpm_requests { + /* PMI8994 should probe first, because pmi8994_bby supplies some of PM8994's regulators */ + pmi8994_regulators: pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + pmi8994_s1: s1 { + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + /* S2 & S3 - VDD_GFX */ + + pmi8994_bby: boost-bypass { + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + }; + }; + pm8994_regulators: pm8994-regulators { compatible = "qcom,rpm-pm8994-regulators"; - vdd_s1-supply = <&vph_pwr>; - vdd_s2-supply = <&vph_pwr>; vdd_s3-supply = <&vph_pwr>; vdd_s4-supply = <&vph_pwr>; vdd_s5-supply = <&vph_pwr>; vdd_s6-supply = <&vph_pwr>; vdd_s7-supply = <&vph_pwr>; - vdd_s8-supply = <&vph_pwr>; - vdd_s9-supply = <&vph_pwr>; - vdd_s10-supply = <&vph_pwr>; - vdd_s11-supply = <&vph_pwr>; - vdd_s12-supply = <&vph_pwr>; vdd_l1-supply = <&pmi8994_s1>; vdd_l2_l26_l28-supply = <&pm8994_s3>; vdd_l3_l11-supply = <&pm8994_s3>; vdd_l4_l27_l31-supply = <&pm8994_s3>; - vdd_l5_l7-supply = <&pm8994_s5>; vdd_l6_l12_l32-supply = <&pm8994_s5>; vdd_l8_l16_l30-supply = <&vph_pwr>; vdd_l9_l10_l18_l22-supply = <&pmi8994_bby>; @@ -227,9 +239,9 @@ pm8994_s4: s4 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-system-load = <325000>; regulator-allow-set-load; regulator-always-on; - regulator-system-load = <325000>; }; pm8994_s5: s5 { @@ -255,13 +267,14 @@ pm8994_l2: l2 { regulator-min-microvolt = <1250000>; regulator-max-microvolt = <1250000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l3: l3 { regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; + regulator-boot-on; }; pm8994_l4: l4 { @@ -301,8 +314,8 @@ pm8994_l12: l12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l13: l13 { @@ -313,8 +326,9 @@ pm8994_l14: l14 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; + regulator-boot-on; }; pm8994_l15: l15 { @@ -330,44 +344,47 @@ pm8994_l17: l17 { regulator-min-microvolt = <2200000>; regulator-max-microvolt = <2200000>; + regulator-boot-on; }; pm8994_l18: l18 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; regulator-always-on; + regulator-boot-on; }; pm8994_l19: l19 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; + regulator-boot-on; }; pm8994_l20: l20 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-boot-on; - regulator-allow-set-load; regulator-system-load = <570000>; + regulator-allow-set-load; }; pm8994_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; - regulator-always-on; - regulator-allow-set-load; regulator-system-load = <800000>; + regulator-allow-set-load; }; pm8994_l22: l22 { regulator-min-microvolt = <3000000>; regulator-max-microvolt = <3000000>; + regulator-boot-on; }; pm8994_l23: l23 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; }; pm8994_l24: l24 { @@ -378,6 +395,7 @@ pm8994_l25: l25 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; + regulator-boot-on; }; pm8994_l26: l26 { @@ -388,30 +406,33 @@ pm8994_l27: l27 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; + regulator-boot-on; }; pm8994_l28: l28 { regulator-min-microvolt = <1000000>; regulator-max-microvolt = <1000000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l29: l29 { regulator-min-microvolt = <2700000>; regulator-max-microvolt = <2700000>; + regulator-boot-on; }; pm8994_l30: l30 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-boot-on; }; pm8994_l31: l31 { regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; - regulator-allow-set-load; regulator-system-load = <10000>; + regulator-allow-set-load; }; pm8994_l32: l32 { @@ -419,26 +440,11 @@ regulator-max-microvolt = <1800000>; }; - pm8994_lvs1: lvs1 {}; - pm8994_lvs2: lvs2 {}; - }; - - pmi8994_regulators: pmi8994-regulators { - compatible = "qcom,rpm-pmi8994-regulators"; - - vdd_s1-supply = <&vph_pwr>; - vdd_bst_byp-supply = <&vph_pwr>; - - pmi8994_s1: s1 { - regulator-min-microvolt = <1025000>; - regulator-max-microvolt = <1025000>; + pm8994_lvs1: lvs1 { + regulator-boot-on; }; - - /* S2 & S3 - VDD_GFX */ - - pmi8994_bby: boost-bypass { - regulator-min-microvolt = <3150000>; - regulator-max-microvolt = <3600000>; + pm8994_lvs2: lvs2 { + regulator-boot-on; }; }; }; -- cgit v1.2.3 From 9d511d0a7926c86e259e5084ae1b25fd61a428f3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:42 +0100 Subject: arm64: dts: qcom: msm8994: Add OCMEM node Add OCMEM node to allow for GPU SRAM access. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-13-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8992.dtsi | 8 ++++++++ arch/arm64/boot/dts/qcom/msm8994.dtsi | 17 +++++++++++++++++ 2 files changed, 25 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 1de1d9c4643d..92c1f87d6bba 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -24,6 +24,14 @@ <800000000>; }; +&ocmem { + reg = <0xfdd00000 0x2000>, <0xfec00000 0x100000>; + + gmu-sram@0 { + reg = <0x0 0x80000>; + }; +}; + &rpmcc { compatible = "qcom,rpmcc-msm8992"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 18cf05535229..e4b212630509 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -1052,6 +1052,23 @@ <960000000>, <600000000>; }; + + ocmem: ocmem@fdd00000 { + compatible = "qcom,msm8974-ocmem"; + reg = <0xfdd00000 0x2000>, + <0xfec00000 0x200000>; + reg-names = "ctrl", "mem"; + clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, + <&mmcc OCMEMCX_OCMEMNOC_CLK>; + clock-names = "core", "iface"; + + #address-cells = <1>; + #size-cells = <1>; + + gmu_sram: gmu-sram@0 { + reg = <0x0 0x180000>; + }; + }; }; timer: timer { -- cgit v1.2.3 From 1ae438d26b620979ed004d559c304d31c42173ae Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:43 +0100 Subject: arm64: dts: qcom: msm8994: Fix BLSP[12]_DMA channels count MSM8994 actually features 24 DMA channels for each BLSP, fix it! Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-14-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e4b212630509..e9920b4c9399 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -500,7 +500,7 @@ #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; - num-channels = <18>; + num-channels = <24>; qcom,num-ees = <4>; }; @@ -636,7 +636,7 @@ #dma-cells = <1>; qcom,ee = <0>; qcom,controlled-remotely; - num-channels = <18>; + num-channels = <24>; qcom,num-ees = <4>; }; -- cgit v1.2.3 From e0be93fb3818b1eb7fc04ebd6c03bb8ba2d67814 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:44 +0100 Subject: arm64: dts: qcom: msm8994: Add watchdog timer node Add and configure the watchdog node. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-15-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e9920b4c9399..068dfe49ed82 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -356,6 +356,15 @@ #mbox-cells = <1>; }; + watchdog@f9017000 { + compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; + reg = <0xf9017000 0x1000>; + interrupts = , + ; + clocks = <&sleep_clk>; + timeout-sec = <10>; + }; + timer@f9020000 { #address-cells = <1>; #size-cells = <1>; -- cgit v1.2.3 From d8023f3a8e55907f5b463d571b9797feae59ead9 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 19 Mar 2022 18:46:45 +0100 Subject: arm64: dts: qcom: msm8994: Add mmc aliases Set the aliases for both SDHCI controllers. Signed-off-by: Konrad Dybcio Reviewed-by: Petr Vorel Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220319174645.340379-16-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 068dfe49ed82..e2a95d52d8f3 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -14,6 +14,11 @@ #address-cells = <2>; #size-cells = <2>; + aliases { + mmc1 = &sdhc1; + mmc2 = &sdhc2; + }; + chosen { }; clocks { -- cgit v1.2.3 From 48cc9bb1d38d8bca1e1fcd98812c965ed13abc3e Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Mar 2022 11:18:40 +0100 Subject: arm64: dts: qcom: sm6350: Add wifi node Add a node describing the wifi hardware found on sm6350. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325101841.172304-1-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index f6fb97d5ca92..6c6112427ef9 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1356,6 +1356,28 @@ }; }; + wifi: wifi@18800000 { + compatible = "qcom,wcn3990-wifi"; + reg = <0 0x18800000 0 0x800000>; + reg-names = "membase"; + memory-region = <&wlan_fw_mem>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + iommus = <&apps_smmu 0x20 0x1>; + qcom,msa-fixed-perm; + status = "disabled"; + }; + apps_rsc: rsc@18200000 { compatible = "qcom,rpmh-rsc"; label = "apps_rsc"; -- cgit v1.2.3 From 22437c436c3be0bb92cd44bd2aead00747394ce0 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Fri, 25 Mar 2022 11:18:41 +0100 Subject: arm64: dts: qcom: sm7225-fairphone-fp4: Enable wifi Configure regulators used by the wifi hardware and enable it. Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220325101841.172304-2-luca.weiss@fairphone.com --- arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts index f70174a342c6..61925216f5e3 100644 --- a/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts +++ b/arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts @@ -406,3 +406,13 @@ vdda-phy-supply = <&vreg_l22a>; vdda-pll-supply = <&vreg_l16a>; }; + +&wifi { + status = "okay"; + + vdd-0.8-cx-mx-supply = <&vreg_l4a>; + vdd-1.8-xo-supply = <&vreg_l7a>; + vdd-1.3-rfa-supply = <&vreg_l2e>; + vdd-3.3-ch0-supply = <&vreg_l10e>; + vdd-3.3-ch1-supply = <&vreg_l11e>; +}; -- cgit v1.2.3 From b3d26821d9394be7d17435168448db01bd8bc494 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:26 +0200 Subject: arm64: dts: qcom: msm8953: do not use underscore in node name Align RPM requests node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 2a70263a701d..006a561f5a9d 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -321,7 +321,7 @@ qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - rpm_requests: rpm_requests { + rpm_requests: rpm-requests { compatible = "qcom,rpm-msm8953"; qcom,smd-channels = "rpm_requests"; -- cgit v1.2.3 From 0e324e9f49220055a9a81b027443740d3fc5ca07 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:27 +0200 Subject: arm64: dts: qcom: msm8994: remove SMD qcom,local-pid property The Qualcomm SMD does not use qcom,local-pid property. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index e2a95d52d8f3..7317feb128fa 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -240,7 +240,6 @@ interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; - qcom,local-pid = <0>; qcom,remote-pid = <6>; rpm_requests: rpm-requests { -- cgit v1.2.3 From 812b0b61ee6a281047f433b143b4e9127f1ad97c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 1 Apr 2022 22:10:28 +0200 Subject: arm64: dts: qcom: add RPM clock controller fallback compatible The bindings require a fallback compatible to RPM clock controller. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220401201035.189106-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8953.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8992.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8994.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 2 +- arch/arm64/boot/dts/qcom/qcs404.dtsi | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0f72349d4067..05472510e29d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -299,7 +299,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-msm8916"; + compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi index 006a561f5a9d..49903a6e9dfd 100644 --- a/arch/arm64/boot/dts/qcom/msm8953.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi @@ -326,7 +326,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8953"; + compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; clocks = <&xo_board>; clock-names = "xo"; #clock-cells = <1>; diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi index 92c1f87d6bba..750643763a76 100644 --- a/arch/arm64/boot/dts/qcom/msm8992.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8992.dtsi @@ -33,7 +33,7 @@ }; &rpmcc { - compatible = "qcom,rpmcc-msm8992"; + compatible = "qcom,rpmcc-msm8992", "qcom,rpmcc"; }; &tcsr_mutex { diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi index 7317feb128fa..367ed913902c 100644 --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi @@ -247,7 +247,7 @@ qcom,smd-channels = "rpm_requests"; rpmcc: rpmcc { - compatible = "qcom,rpmcc-msm8994"; + compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 67d2253e2c35..9d993f25046a 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -461,7 +461,7 @@ qcom,glink-channels = "rpm_requests"; rpmcc: qcom,rpmcc { - compatible = "qcom,rpmcc-msm8996"; + compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc"; #clock-cells = <1>; }; diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index acf120f91b42..bc446c6002d0 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -226,7 +226,7 @@ qcom,glink-channels = "rpm_requests"; rpmcc: clock-controller { - compatible = "qcom,rpmcc-qcs404"; + compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; #clock-cells = <1>; }; -- cgit v1.2.3 From 2bc0aa18ee9f34613876f6ac7bf944ad65d63e17 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:10 +0100 Subject: arm64: dts: renesas: rcar-gen3: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + 8 files changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 4e87e8776a2b..742834fa7097 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -369,6 +369,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 6f79da8cc8c0..0f2635af7b58 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -334,6 +334,7 @@ compatible = "renesas,r8a7796-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7d522ea5fca2..d4fe1d7f3c62 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -323,6 +323,7 @@ compatible = "renesas,r8a77961-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 9f858af8b762..bba07944228b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -205,6 +205,7 @@ compatible = "renesas,r8a77965-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 517892cf6294..79718234d85f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -108,6 +108,7 @@ compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 347c068ff2c5..148983130adf 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -138,6 +138,7 @@ compatible = "renesas,r8a77980-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 7e0f1aab2135..af61c67b093d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -171,6 +171,7 @@ compatible = "renesas,r8a77990-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index cac1f9467ffa..00254cf0aa92 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -94,6 +94,7 @@ compatible = "renesas,r8a77995-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; resets = <&cpg 402>; -- cgit v1.2.3 From 7ac8afba2257f08e95ef7d0e3ed2ac47cad9195b Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:11 +0100 Subject: arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + 3 files changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 12846125a4c9..faf5bbbb3710 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -283,6 +283,7 @@ compatible = "renesas,r8a774a1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index a4b406a346f9..be998bc40412 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -156,6 +156,7 @@ compatible = "renesas,r8a774b1-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 402>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index e123c8d1bab9..4f69f90d88cb 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -145,6 +145,7 @@ compatible = "renesas,r8a774c0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 402>; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 402>; -- cgit v1.2.3 From ccc0dd722e66daac9d31d7c584f6c2ceabf6c493 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 22 Mar 2022 10:55:12 +0100 Subject: arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodes Driver doesn't use it yet, but let's describe the HW properly. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220322095512.4707-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 1 + 2 files changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index c80f4584035e..57d49d27cdca 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -88,6 +88,7 @@ compatible = "renesas,r8a779a0-wdt", "renesas,rcar-gen3-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 907>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index ab0856b7a2bd..eaea28cc5ffb 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -63,6 +63,7 @@ compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; + interrupts = ; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; resets = <&cpg 907>; -- cgit v1.2.3 From f191fba76916dc18c41cf6183d71dbf9a1d821c8 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:01 +0200 Subject: arm64: dts: renesas: rcar-gen3: Add RPC device nodes Add device nodes for the SPI Multi I/O Bus Controllers (RPC-IF) on the various R-Car Gen3 SoCs that do not have support for them yet in their device trees (R-Car H3, M3-W, M3-W+, M3-N, E3, and D3). Based on patches in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/3231749c7b63df1a2134daabe66446a3e0e5515b.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77960.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77961.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77965.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/renesas/r8a77995.dtsi | 16 ++++++++++++++++ 6 files changed, 96 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 742834fa7097..884210544ba0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -2732,6 +2732,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7795-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a7795", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0f2635af7b58..0d96b5bb9584 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2532,6 +2532,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a7796-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index d4fe1d7f3c62..58e161e5dae0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2401,6 +2401,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77961-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index bba07944228b..ecca9582edf6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2379,6 +2379,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77965-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sata: sata@ee300000 { compatible = "renesas,sata-r8a77965", "renesas,rcar-gen3-sata"; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index af61c67b093d..5d41e46d06f5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1838,6 +1838,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77990-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 00254cf0aa92..0eccf81db374 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1238,6 +1238,22 @@ status = "disabled"; }; + rpc: spi@ee200000 { + compatible = "renesas,r8a77995-rpc-if", + "renesas,rcar-gen3-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 917>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3 From a1de91f0ac71cfd3ff3dd630ab560238db05bef6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:02 +0200 Subject: arm64: dts: renesas: draak: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Draak board DTS file. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/0f3d3018ecfcdce1bce67708708a6d3a98368b10.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/draak.dtsi | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index eb0327c0df48..2a784ee6da49 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -541,6 +541,12 @@ function = "pwm1"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data"; function = "scif2"; @@ -630,6 +636,58 @@ }; }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; -- cgit v1.2.3 From 5f300a7f3953aea5b2ce996a0bdec31ffd108999 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:03 +0200 Subject: arm64: dts: renesas: ebisu: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Ebisu board DTS file. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/b14c769f62211b67d90dbd2f127357756e6cb4fa.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 67231c8576c5..ae688707f8c6 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -600,6 +600,12 @@ function = "pwm5"; }; + rpc_pins: rpc { + groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", + "rpc_int"; + function = "rpc"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -711,6 +717,58 @@ }; +&rpc { + pinctrl-0 = <&rpc_pins>; + pinctrl-names = "default"; + + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; -- cgit v1.2.3 From 1ee6674bbe1cd6bd38216be3b7693ef1e5e2eabf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:04 +0200 Subject: arm64: dts: renesas: salvator-common: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common Salvator-X(S) board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/cfc6af8a4c42febcc405b7356c38448eec8e29b0.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 6092dc4531ad..7ad72f377a35 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -866,6 +866,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; -- cgit v1.2.3 From 79e903fbf43b734badb33723525a84d2ffeb9c8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 29 Mar 2022 14:20:05 +0200 Subject: arm64: dts: renesas: ulcb: Add RPC HyperFlash device node Add the RPC HyperFlash device node along with its partitions to the common ULCB board DTS file. Based on a patch in the BSP by Valentine Barshak. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/61a63e819d4296760ca7ae83ef5226a2c4d7bd93.1648548339.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/ulcb.dtsi | 49 +++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index b4bdb2d7e4ba..90a4c0629d24 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -426,6 +426,55 @@ }; }; +&rpc { + /* Left disabled. To be enabled by firmware when unlocked. */ + + flash@0 { + compatible = "cypress,hyperflash", "cfi-flash"; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + bl2@40000 { + reg = <0x00040000 0x140000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x040000>; + read-only; + }; + tee@200000 { + reg = <0x00200000 0x440000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x100000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + &rwdt { timeout-sec = <60>; status = "okay"; -- cgit v1.2.3 From 061ba41c7449a9cf4bbf2b6930eb0ded69e5eead Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Apr 2022 15:57:02 +0100 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board RSPI1 (SPI1) interface is available on PMOD0 connector (J1) on the carrier board. This patch adds pinmux and spi1 nodes to the carrier board dtsi file and drops deleting pinctl* properties from DTS file. RSPI1 interface is tested by setting the macro SW_RSPI_CAN to 0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220401145702.17954-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 8 ++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 74a2f2bade10..fc34058002e2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -13,9 +13,3 @@ model = "Renesas SMARC EVK based on r9a07g044c2"; compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044"; }; - -&spi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi index d275a55333e3..a78a8def363e 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi @@ -106,6 +106,13 @@ input-enable; }; + spi1_pins: spi1 { + pinmux = , /* CK */ + , /* MOSI */ + , /* MISO */ + ; /* SSL */ + }; + ssi0_pins: ssi0 { pinmux = , /* BCK */ , /* RCK */ diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index f73b4acb8f9e..856c949796ff 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -90,3 +90,11 @@ status = "okay"; }; #endif + +#if (SW_RSPI_CAN) +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif -- cgit v1.2.3 From f40846e7c9f50bfbba96d566c63cbdb57b817249 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 1 Apr 2022 18:54:27 +0100 Subject: arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi On RZ/G2{L,LC} SoM module, gpio for power selection is connected to P39_1 whereas on RZ/G2UL it is connected to P6_1. So move gpios property of vccq_sdhi1 regulator from common dtsi to soc specific dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220401175427.19078-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 1 - arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 4 ++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 8dd1c69a6749..0e61b85efb43 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -74,7 +74,6 @@ regulator-name = "SDHI1 VccQ"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; gpios-states = <1>; states = <3300000 1>, <1800000 0>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index c934cd3633a4..aadc41515093 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -48,3 +48,7 @@ status = "okay"; }; #endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 856c949796ff..74a844ea7537 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -98,3 +98,7 @@ status = "disabled"; }; #endif + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From cf40c9689e5109bf5e4c29038c9f450223aaad2b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:13 +0100 Subject: arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC Add initial DTSI for RZ/G2UL SoC. Both RZ/G2L and RZ/G2UL uses the same SMARC EVK. Therefore they share the common dtsi (rz-smarc.dtsi) file. Place holders are added in device nodes to avoid compilation errors for the devices which have not been enabled yet on RZ/G2UL SoC. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 413 +++++++++++++++++++++++++++++ 1 file changed, 413 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..aed9ab4f9ba4 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,413 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + audio_clk1: audio-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + audio_clk2: audio-clk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by boards that provide it */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x40000>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssi0: ssi@10049c00 { + reg = <0 0x10049c00 0 0x400>; + #sound-dai-cells = <0>; + /* place holder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif1: serial@1004bc00 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004bc00 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif2: serial@1004c000 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c000 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif3: serial@1004c400 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c400 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; + status = "disabled"; + }; + + scif4: serial@1004c800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004c800 0 0x400>; + interrupts = , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; + status = "disabled"; + }; + + sci0: serial@1004d000 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI0_RST>; + status = "disabled"; + }; + + sci1: serial@1004d400 { + compatible = "renesas,r9a07g043-sci", "renesas,sci"; + reg = <0 0x1004d400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCI1_RST>; + status = "disabled"; + }; + + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + /* place holder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + /* place holder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + /* place holder */ + }; + + i2c3: i2c@10058c00 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058c00 0 0x400>; + /* place holder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + /* place holder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + /* place holder */ + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + interrupts = , + , + , + ; + interrupt-names = "lpm_int", "ca55stbydone_int", + "cm33stbyr_int", "ca55_deny"; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + /* place holder */ + }; + + dmac: dma-controller@11820000 { + compatible = "renesas,r9a07g043-dmac", + "renesas,rz-dmac"; + reg = <0 0x11820000 0 0x10000>, + <0 0x11830000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, + <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_DMAC_ARESETN>, + <&cpg R9A07G043_DMAC_RST_ASYNC>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + gic: interrupt-controller@11900000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x11900000 0 0x40000>, + <0x0 0x11940000 0 0x60000>; + interrupts = ; + }; + + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + /* place holder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + /* place holder */ + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + /* place holder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + /* place holder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + /* place holder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + /* place holder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + /* place holder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + /* place holder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + /* place holder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + /* place holder */ + }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + /* place holder */ + }; + + wdt2: watchdog@12800400 { + reg = <0 0x12800400 0 0x400>; + /* place holder */ + }; + + ostm0: timer@12801000 { + reg = <0x0 0x12801000 0x0 0x400>; + /* place holder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + /* place holder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + /* place holder */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit v1.2.3 From 895199bc4e5261b67b688a915c592dd4c3af113c Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 12 Apr 2022 17:13:14 +0100 Subject: arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK Add basic support for RZ/G2UL SMARC EVK (based on R9A07G043U11): - memory - External input clock - CPG - DMA - SCIF It shares the same carrier board with RZ/G2L, but the pin mapping is different. Disable the device nodes which are not tested and delete the corresponding pinctrl definitions. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 111 +++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 25 +++++ 3 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index d000f6b131dc..fa9811251fd7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -75,6 +75,8 @@ dtb-$(CONFIG_ARCH_R8A77961) += r8a779m3-ulcb-kf.dtb dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs.dtb +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb + dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts new file mode 100644 index 000000000000..aaa29f83e84c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a07g043.dtsi" +#include "rzg2ul-smarc-som.dtsi" +#include "rz-smarc-common.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043u11"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; +}; + +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ehci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&hsusb { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&i2c1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; + + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + +&ohci0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ohci1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&phyrst { + status = "disabled"; +}; + +&scif0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +&sdhi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-1; + /delete-property/ pinctrl-names; + /delete-property/ vmmc-supply; + status = "disabled"; +}; + +&spi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&ssi0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy0 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; + +&usb2_phy1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi new file mode 100644 index 000000000000..3bbb8fcd604c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC SOM common parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + chosen { + bootargs = "ignore_loglevel"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; -- cgit v1.2.3 From 2d10555298576a95b637a5087751d0aad570964d Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:22 +0100 Subject: arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node Fillup the pinctrl(GPIO) stub node in RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index aed9ab4f9ba4..f24756d89bc2 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -275,10 +275,16 @@ }; pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; - /* place holder */ + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; }; dmac: dma-controller@11820000 { -- cgit v1.2.3 From 4e44055440e1fef93e830bd06111bbbb0a89fa44 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:23 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins Add scif0 and audio clk pins to soc pinctrl dtsi and drop deleting the pinctrl-0 and pinctrl-names properties for scif0 node so that we now actually make use of these properties for scif0. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 6 +----- .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 24 ++++++++++++++++++++++ 2 files changed, 25 insertions(+), 5 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index aaa29f83e84c..64370faf8f6d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "r9a07g043.dtsi" #include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" / { @@ -73,11 +74,6 @@ status = "disabled"; }; -&scif0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; -}; - &sdhi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-1; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi new file mode 100644 index 000000000000..2db9c92cf01f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL SMARC pincontrol parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +&pinctrl { + pinctrl-0 = <&sound_clk_pins>; + pinctrl-names = "default"; + + scif0_pins: scif0 { + pinmux = , /* TxD */ + ; /* RxD */ + }; + + sound_clk_pins: sound_clk { + pins = "AUDIO_CLK1", "AUDIO_CLK2"; + input-enable; + }; +}; -- cgit v1.2.3 From 20e63d3948985672b9e8efa98ff3643d91378e84 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:24 +0100 Subject: arm64: dts: renesas: r9a07g043: Add SDHI nodes Add SDHI{0, 1} nodes to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index f24756d89bc2..c013d4fbe9f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -334,13 +334,35 @@ }; sdhi0: mmc@11c00000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c00000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI0_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; sdhi1: mmc@11c10000 { + compatible = "renesas,sdhi-r9a07g043", + "renesas,rcar-gen3-sdhi"; reg = <0x0 0x11c10000 0 0x10000>; - /* place holder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, + <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, + <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, + <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg R9A07G043_SDHI1_IXRST>; + power-domains = <&cpg>; + status = "disabled"; }; phyrst: usbphy-ctrl@11c40000 { -- cgit v1.2.3 From 13ea8b3584c09f0ab94d5447ff2965d255329a88 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:25 +0100 Subject: arm64: dts: renesas: r9a07g043: Add GbEthernet nodes Add Gigabit Ethernet{0,1} nodes to SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c013d4fbe9f7..c8aadbe55278 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -365,6 +365,46 @@ status = "disabled"; }; + eth0: ethernet@11c20000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c20000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH0_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + eth1: ethernet@11c30000 { + compatible = "renesas,r9a07g043-gbeth", + "renesas,rzg2l-gbeth"; + reg = <0 0x11c30000 0 0x10000>; + interrupts = , + , + ; + interrupt-names = "mux", "fil", "arp_ns"; + phy-mode = "rgmii"; + clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, + <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, + <&cpg CPG_CORE R9A07G043_CLK_HP>; + clock-names = "axi", "chi", "refclk"; + resets = <&cpg R9A07G043_ETH1_RST_HW_N>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + phyrst: usbphy-ctrl@11c40000 { reg = <0 0x11c40000 0 0x10000>; /* place holder */ -- cgit v1.2.3 From a74a0bf3f329415008c1a374118d27023a3d4735 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:26 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform Enable the microSD card slot connected to SDHI1 on the RZ/G2UL SMARC platform by removing the sdhi1 override which disabled it, and by adding the necessary pinmux required for SDHI1. This patch also adds gpios property to vccq_sdhi1 regulator. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 12 +------ .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 39 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 9 +++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 14 ++++++++ 4 files changed, 63 insertions(+), 11 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 64370faf8f6d..08a0404c6f0b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -7,9 +7,7 @@ /dts-v1/; #include "r9a07g043.dtsi" -#include "rzg2ul-smarc-som.dtsi" -#include "rzg2ul-smarc-pinfunction.dtsi" -#include "rz-smarc-common.dtsi" +#include "rzg2ul-smarc.dtsi" / { model = "Renesas SMARC EVK based on r9a07g043u11"; @@ -74,14 +72,6 @@ status = "disabled"; }; -&sdhi1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-1; - /delete-property/ pinctrl-names; - /delete-property/ vmmc-supply; - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 2db9c92cf01f..b515748e6a9a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -17,6 +17,45 @@ ; /* RxD */ }; + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_data { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <3300>; + }; + + sd1_ctrl { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <3300>; + }; + + sd1_mux { + pinmux = ; /* SD1_CD */ + }; + }; + + sdhi1_pins_uhs: sd1_uhs { + sd1_data_uhs { + pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; + power-source = <1800>; + }; + + sd1_ctrl_uhs { + pins = "SD1_CLK", "SD1_CMD"; + power-source = <1800>; + }; + + sd1_mux_uhs { + pinmux = ; /* SD1_CD */ + }; + }; + sound_clk_pins: sound_clk { pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 3bbb8fcd604c..8ecc650099a7 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -18,6 +18,15 @@ /* first 128MB is reserved for secure area. */ reg = <0x0 0x48000000 0x0 0x38000000>; }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi new file mode 100644 index 000000000000..f47b4e2e0feb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "rzg2ul-smarc-som.dtsi" +#include "rzg2ul-smarc-pinfunction.dtsi" +#include "rz-smarc-common.dtsi" + +&vccq_sdhi1 { + gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; +}; -- cgit v1.2.3 From ed8efe50b76e751791a9aa4ce1f95fe3d9d794ac Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:27 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform RZ/G2UL SoM has both 64GB eMMC and microSD connected to SDHI0. Both these interfaces are mutually exclusive and the SD0 device selection is based on SW1[2] on SoM module. Set SW1[2] to position OFF for selecting eMMC Set SW1[2] to position ON for selecting microSD This patch enables eMMC on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 104 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 ++ 2 files changed, 112 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 8ecc650099a7..0d6fc0d84783 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -19,6 +19,15 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + reg_3p3v: regulator1 { compatible = "regulator-fixed"; regulator-name = "fixed-3.3V"; @@ -27,8 +36,103 @@ regulator-boot-on; regulator-always-on; }; + +#if !(SW_SW0_DEV_SEL) + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +#endif }; &extal_clk { clock-frequency = <24000000>; }; + +&pinctrl { + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +#if (SW_SW0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#else +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f47b4e2e0feb..f8c90ff676fe 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -5,6 +5,14 @@ * Copyright (C) 2022 Renesas Electronics Corp. */ +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * Please change below macros according to SW1 setting + */ +#define SW_SW0_DEV_SEL 1 + #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" -- cgit v1.2.3 From 6494e4f90503cb4027632dfcedcb7a683d829db0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sat, 2 Apr 2022 09:13:28 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform Enable Ethernet{0,1} interfaces on RZ/G2UL SMARC EVK. Ethernet0 pins are muxed with CAN0, CAN1, SSI1 and RSPI1 pins and Ethernet0 device selection is based on the SW1[3] switch position. Set SW1[3] to position OFF for selecting CAN0, CAN1, SSI1 and RSPI1. Set SW1[3] to position ON for selecting Ethernet0. This patch disables Ethernet0 on RZ/G2UL SMARC platform by default. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220402081328.26292-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 97 ++++++++++++++++++++++- arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 2 + 2 files changed, 98 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 0d6fc0d84783..b0822679a55b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -9,8 +9,13 @@ #include / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + chosen { - bootargs = "ignore_loglevel"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; }; memory@48000000 { @@ -52,11 +57,101 @@ #endif }; +#if (!SW_ET0_EN_N) +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; +#endif + +ð1 { + pinctrl-0 = <ð1_pins>; + pinctrl-names = "default"; + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy1: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txdv-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + &extal_clk { clock-frequency = <24000000>; }; &pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + eth1_pins: eth1 { + pinmux = , /* ET1_LINKSTA */ + , /* ET1_MDC */ + , /* ET1_MDIO */ + , /* ET1_TXC */ + , /* ET1_TX_CTL */ + , /* ET1_TXD0 */ + , /* ET1_TXD1 */ + , /* ET1_TXD2 */ + , /* ET1_TXD3 */ + , /* ET1_RXC */ + , /* ET1_RX_CTL */ + , /* ET1_RXD0 */ + , /* ET1_RXD1 */ + , /* ET1_RXD2 */ + ; /* ET1_RXD3 */ + }; + sdhi0_emmc_pins: sd0emmc { sd0_emmc_data { pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index f8c90ff676fe..056a77369c8d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -9,9 +9,11 @@ * DIP-Switch SW1 setting * 1 : High; 0: Low * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) * Please change below macros according to SW1 setting */ #define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 #include "rzg2ul-smarc-som.dtsi" #include "rzg2ul-smarc-pinfunction.dtsi" -- cgit v1.2.3 From 8dd3cdeaf3032728e30a7ec5e79ca780fc86cf7a Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Wed, 13 Apr 2022 10:35:47 +0100 Subject: arm64: dts: juno: Fix SCMI power domain IDs for ETF and CS funnel The SCMI power domain ID for all the coresight components is 8 while the previous/older SCPI domain was 0. When adding SCMI variant, couple of instances retained SCPI domain ID by mistake. Fix the same by using the correct SCMI power domain ID of 8. Link: https://lore.kernel.org/r/20220413093547.1699535-1-sudeep.holla@arm.com Fixes: 96bb0954860a ("arm64: dts: juno: Add separate SCMI variants") Cc: Robin Murphy Reported-by: Mike Leach Acked-by: Robin Murphy Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 ++-- arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index 190a0fba4ad6..fd1f0d26d751 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -7,11 +7,11 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index dbf13770084f..35e6d4762c46 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -7,11 +7,11 @@ }; etf@20140000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; funnel@20150000 { - power-domains = <&scmi_devpd 0>; + power-domains = <&scmi_devpd 8>; }; }; -- cgit v1.2.3 From e7676a00bc52b994960f89b118b0d548e4542372 Mon Sep 17 00:00:00 2001 From: Mike Leach Date: Wed, 13 Apr 2022 22:49:25 +0100 Subject: arm64: dts: juno: add CTI entries to device tree Add Coresight Cross Trigger Interface(CTI) entries to the device tree for all the Juno variants. Link: https://lore.kernel.org/r/20220413214925.30359-1-mike.leach@linaro.org Reviewed-by: Mathieu Poirier Signed-off-by: Mike Leach Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 162 +++++++++++++++++++++++++++++- arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 37 ++++++- arch/arm64/boot/dts/arm/juno-r1-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r1.dts | 25 +++++ arch/arm64/boot/dts/arm/juno-r2-scmi.dts | 4 + arch/arm64/boot/dts/arm/juno-r2.dts | 25 +++++ arch/arm64/boot/dts/arm/juno-scmi.dtsi | 25 +++++ arch/arm64/boot/dts/arm/juno.dts | 25 +++++ 8 files changed, 302 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 446c8f476eec..4f40a5c8f565 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -117,7 +117,7 @@ * The actual size is just 4K though 64K is reserved. Access to the * unmapped reserved region results in a DECERR response. */ - etf@20010000 { /* etf0 */ + etf_sys0: etf@20010000 { /* etf0 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20010000 0 0x1000>; @@ -141,7 +141,7 @@ }; }; - tpiu@20030000 { + tpiu_sys: tpiu@20030000 { compatible = "arm,coresight-tpiu", "arm,primecell"; reg = <0 0x20030000 0 0x1000>; @@ -194,7 +194,7 @@ }; }; - etr@20070000 { + etr_sys: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20070000 0 0x1000>; iommus = <&smmu_etr 0>; @@ -212,7 +212,7 @@ }; }; - stm@20100000 { + stm_sys: stm@20100000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x20100000 0 0x1000>, <0 0x28000000 0 0x1000000>; @@ -289,6 +289,18 @@ }; }; + cti0: cti@22020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm0>; + }; + funnel@220c0000 { /* cluster0 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x220c0000 0 0x1000>; @@ -349,6 +361,18 @@ }; }; + cti1: cti@22120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x22120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm1>; + }; + cpu_debug2: cpu-debug@23010000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23010000 0x0 0x1000>; @@ -374,6 +398,18 @@ }; }; + cti2: cti@23020000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm2>; + }; + funnel@230c0000 { /* cluster1 funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x230c0000 0 0x1000>; @@ -446,6 +482,18 @@ }; }; + cti3: cti@23120000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23120000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm3>; + }; + cpu_debug4: cpu-debug@23210000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23210000 0x0 0x1000>; @@ -471,6 +519,18 @@ }; }; + cti4: cti@23220000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23220000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm4>; + }; + cpu_debug5: cpu-debug@23310000 { compatible = "arm,coresight-cpu-debug", "arm,primecell"; reg = <0x0 0x23310000 0x0 0x1000>; @@ -496,6 +556,100 @@ }; }; + cti5: cti@23320000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0 0x23320000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + arm,cs-dev-assoc = <&etm5>; + }; + + cti_sys0: cti@20020000 { /* sys_cti_0 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20020000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<2 3>; + arm,trig-in-types=; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etr_sys>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=; + arm,trig-out-sigs=<7 6>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etf_sys0>; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<4 5 6 7>; + arm,trig-in-types=; + arm,trig-out-sigs=<4 5>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&stm_sys>; + }; + + trig-conns@3 { + reg = <3>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&tpiu_sys>; + }; + }; + + cti_sys1: cti@20110000 { /* sys_cti_1 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20110000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=; + arm,trig-out-sigs=<0>; + arm,trig-out-types=; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-out-sigs=<1 6>; + arm,trig-out-types=; + arm,trig-conn-name = "g_counter"; + }; + }; + gpu: gpu@2d000000 { compatible = "arm,juno-mali", "arm,mali-t624"; reg = <0 0x2d000000 0 0x10000>; diff --git a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi index eda3d9e18af6..2e43f4531308 100644 --- a/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi +++ b/arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi @@ -23,7 +23,7 @@ }; }; - etf@20140000 { /* etf1 */ + etf_sys1: etf@20140000 { /* etf1 */ compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0 0x20140000 0 0x1000>; @@ -82,4 +82,39 @@ }; }; + + cti_sys2: cti@20160000 { /* sys_cti_2 */ + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0 0x20160000 0 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + power-domains = <&scpi_devpd 0>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0 1>; + arm,trig-in-types=; + arm,trig-out-sigs=<0 1>; + arm,trig-out-types=; + arm,cs-dev-assoc = <&etf_sys1>; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-in-sigs=<2 3 4>; + arm,trig-in-types=; + arm,trig-conn-name = "ela_clus_0"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<5 6 7>; + arm,trig-in-types=; + arm,trig-conn-name = "ela_clus_1"; + }; + }; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts index fd1f0d26d751..dd9ea69f086f 100644 --- a/arch/arm64/boot/dts/arm/juno-r1-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r1-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A57_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts index 0e24e29eb9b1..f099fb611d4e 100644 --- a/arch/arm64/boot/dts/arm/juno-r1.dts +++ b/arch/arm64/boot/dts/arm/juno-r1.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -313,3 +314,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts index 35e6d4762c46..de2cbac1d1c3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2-scmi.dts +++ b/arch/arm64/boot/dts/arm/juno-r2-scmi.dts @@ -15,6 +15,10 @@ }; }; +&cti_sys2 { + power-domains = <&scmi_devpd 8>; +}; + &A72_0 { clocks = <&scmi_dvfs 0>; }; diff --git a/arch/arm64/boot/dts/arm/juno-r2.dts b/arch/arm64/boot/dts/arm/juno-r2.dts index e609420ce3e4..709389582ae3 100644 --- a/arch/arm64/boot/dts/arm/juno-r2.dts +++ b/arch/arm64/boot/dts/arm/juno-r2.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" #include "juno-cs-r1r2.dtsi" @@ -319,3 +320,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A72_0>; +}; + +&cti1 { + cpu = <&A72_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; diff --git a/arch/arm64/boot/dts/arm/juno-scmi.dtsi b/arch/arm64/boot/dts/arm/juno-scmi.dtsi index d72dcff9bf06..4135d62e44a2 100644 --- a/arch/arm64/boot/dts/arm/juno-scmi.dtsi +++ b/arch/arm64/boot/dts/arm/juno-scmi.dtsi @@ -154,6 +154,31 @@ power-domains = <&scmi_devpd 8>; }; +&cti0 { + power-domains = <&scmi_devpd 8>; +}; +&cti1 { + power-domains = <&scmi_devpd 8>; +}; +&cti2 { + power-domains = <&scmi_devpd 8>; +}; +&cti3 { + power-domains = <&scmi_devpd 8>; +}; +&cti4 { + power-domains = <&scmi_devpd 8>; +}; +&cti5 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys0 { + power-domains = <&scmi_devpd 8>; +}; +&cti_sys1 { + power-domains = <&scmi_devpd 8>; +}; + &gpu { clocks = <&scmi_dvfs 2>; power-domains = <&scmi_devpd 9>; diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts index f00cffbd032c..dbc22e70b62c 100644 --- a/arch/arm64/boot/dts/arm/juno.dts +++ b/arch/arm64/boot/dts/arm/juno.dts @@ -9,6 +9,7 @@ /dts-v1/; #include +#include #include "juno-base.dtsi" / { @@ -295,3 +296,27 @@ &cpu_debug5 { cpu = <&A53_3>; }; + +&cti0 { + cpu = <&A57_0>; +}; + +&cti1 { + cpu = <&A57_1>; +}; + +&cti2 { + cpu = <&A53_0>; +}; + +&cti3 { + cpu = <&A53_1>; +}; + +&cti4 { + cpu = <&A53_2>; +}; + +&cti5 { + cpu = <&A53_3>; +}; -- cgit v1.2.3 From 472f20b4f2534236fb90cdf93b42a071eb77bc5e Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Apr 2022 14:35:42 -0500 Subject: arm64: dts: imx8mn: Enable HS400-ES The SDHC controller in the imx8mn has the same controller as the imx8mm which supports HS400-ES. Change the compatible fallback to imx8mm to enable it, but keep the imx7d-usdhc to prevent breaking backwards compatibility. Signed-off-by: Adam Ford Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 99f0f5026674..13c51363cc06 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -933,7 +933,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -947,7 +947,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, @@ -961,7 +961,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; clocks = <&clk IMX8MN_CLK_IPG_ROOT>, -- cgit v1.2.3 From 746a72411cddb87d3c09dc42f901e6e69467744f Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Sun, 10 Apr 2022 14:35:43 -0500 Subject: arm64: dts: imx8mp: Enable HS400-ES The SDHC controller in the imx8mp has the same controller as the imx8mm which supports HS400-ES. Change the compatible fallback to imx8mm to enable it, but keep the imx7d-usdhc to prevent breaking backwards compatibility. Signed-off-by: Adam Ford Acked-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index c42d25bd16ed..7ad824e6b820 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -847,7 +847,7 @@ }; usdhc1: mmc@30b40000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b40000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, @@ -861,7 +861,7 @@ }; usdhc2: mmc@30b50000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b50000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, @@ -875,7 +875,7 @@ }; usdhc3: mmc@30b60000 { - compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc"; + compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; reg = <0x30b60000 0x10000>; interrupts = ; clocks = <&clk IMX8MP_CLK_DUMMY>, -- cgit v1.2.3 From 0d9968d98467d75cfdcb903f6c202884f2299521 Mon Sep 17 00:00:00 2001 From: Ming Qian Date: Mon, 11 Apr 2022 14:50:49 +0800 Subject: arm64: dts: freescale: imx8q: add imx vpu codec entries Add the Video Processing Unit node for IMX8Q SoC. Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi | 74 ++++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 25 +++++++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 24 +++++++++ 3 files changed, 123 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi new file mode 100644 index 000000000000..c6540768bdb9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-vpu.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + * Dong Aisheng + */ + +vpu: vpu@2c000000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x2c000000 0x0 0x2c000000 0x2000000>; + reg = <0 0x2c000000 0 0x1000000>; + power-domains = <&pd IMX_SC_R_VPU>; + status = "disabled"; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + status = "disabled"; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + status = "disabled"; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = ; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + status = "disabled"; + }; + + vpu_core0: vpu-core@2d080000 { + reg = <0x2d080000 0x10000>; + compatible = "nxp,imx8q-vpu-decoder"; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0>, + <&mu_m0 0 1>, + <&mu_m0 1 0>; + status = "disabled"; + }; + + vpu_core1: vpu-core@2d090000 { + reg = <0x2d090000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0>, + <&mu1_m0 0 1>, + <&mu1_m0 1 0>; + status = "disabled"; + }; + + vpu_core2: vpu-core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0>, + <&mu2_m0 0 1>, + <&mu2_m0 1 0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 863232a47004..07d8dd8160f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -135,6 +135,14 @@ status = "okay"; }; +&mu_m0 { + status = "okay"; +}; + +&mu1_m0 { + status = "okay"; +}; + &scu_key { status = "okay"; }; @@ -196,6 +204,23 @@ status = "okay"; }; +&vpu { + compatible = "nxp,imx8qxp-vpu"; + status = "okay"; +}; + +&vpu_core0 { + reg = <0x2d040000 0x10000>; + memory-region = <&decoder_boot>, <&decoder_rpc>; + status = "okay"; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; + memory-region = <&encoder_boot>, <&encoder_rpc>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index dbec7c106e0b..a79ae33cbad2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -46,6 +46,9 @@ serial1 = &lpuart1; serial2 = &lpuart2; serial3 = &lpuart3; + vpu_core0 = &vpu_core0; + vpu_core1 = &vpu_core1; + vpu_core2 = &vpu_core2; }; cpus { @@ -162,10 +165,30 @@ #size-cells = <2>; ranges; + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@92000000 { + reg = <0 0x92000000 0 0x100000>; + no-map; + }; + dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; }; + + encoder_rpc: encoder-rpc@94400000 { + reg = <0 0x94400000 0 0x700000>; + no-map; + }; }; pmu { @@ -287,6 +310,7 @@ /* sorted in register address */ #include "imx8-ss-img.dtsi" + #include "imx8-ss-vpu.dtsi" #include "imx8-ss-adma.dtsi" #include "imx8-ss-conn.dtsi" #include "imx8-ss-ddr.dtsi" -- cgit v1.2.3 From d9a9a7cf32c93c4c66b437438857f9fb7eb54d91 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Mon, 11 Apr 2022 12:46:38 -0700 Subject: arm64: dts: imx8m{m,n}-venice-*: add missing uart-has-rtscts property to UARTs Add the missing 'uart-has-rtscts' property to UART's that have hardware flow control capability. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 3 +++ arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 1 + 4 files changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 426483ec1f88..7a5d45e80982 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -221,6 +221,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 7e7231046215..70b2ae55e906 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -716,6 +716,7 @@ dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -731,6 +732,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -739,6 +741,7 @@ pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>; cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index edf0c7aaaef0..1b03aa154688 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -644,6 +644,7 @@ pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; @@ -660,6 +661,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { @@ -677,6 +679,7 @@ dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>; dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>; dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 3c0e63d2e82d..2c1f591335ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -625,6 +625,7 @@ pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>; rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; + uart-has-rtscts; status = "okay"; bluetooth { -- cgit v1.2.3 From e7fc48e6c7a8c3b37855703925d9320680041675 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 12 Apr 2022 16:32:38 +0200 Subject: arm64: dts: imx8mn: add 8MNANOD3L-EVK device tree Add a device tree for the 8MNANOD3L-EVK eval board which features an IMX8MN SoC. It is similar to the 8MNANODLPD4-EVK eval board except it has an IMX8MN UltraLite SoC and DDR3L memory. It esp. differs in the PMIC configuration because the SoC has a smaller package and thus the ARM core voltage is combined with the SoC voltage and the DDR voltage is 1.35V for the DDR3L memory. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts | 114 +++++++++++++++++++++ 2 files changed, 115 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 85c2c9ba5110..bdb76e67ccfe 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -73,6 +73,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts new file mode 100644 index 000000000000..000e2c0596df --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr3l-evk.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "imx8mn.dtsi" +#include "imx8mn-evk.dtsi" +#include + +/ { + model = "NXP i.MX8MNano DDR3L EVK board"; + compatible = "fsl,imx8mn-ddr3l-evk", "fsl,imx8mn"; +}; + +&A53_0 { + cpu-supply = <&buck1>; +}; + +&A53_1 { + cpu-supply = <&buck1>; +}; + +&A53_2 { + cpu-supply = <&buck1>; +}; + +&A53_3 { + cpu-supply = <&buck1>; +}; + +&i2c1 { + pmic: pmic@25 { + compatible = "nxp,pca9450b"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + regulators { + buck1: BUCK1 { + regulator-name = "VDD_SOC_0V9"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + buck5: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + buck6: BUCK6 { + regulator-name = "NVCC_DRAM_1V35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1: LDO1 { + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2: LDO2 { + regulator-name = "VDD_SNVS_0V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3: LDO3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo4: LDO4 { + regulator-name = "VDD_PHY_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; -- cgit v1.2.3 From b5f955c099cd9bccbf44681e8ee14c3d786ea25a Mon Sep 17 00:00:00 2001 From: Tommaso Merciai Date: Wed, 13 Apr 2022 23:33:11 +0200 Subject: arm64: dts: imx8mm-evk: add pwm1/backlight support Add pwm1/backlight support nodes for imx8mm_evk board. Align with u-boot dts References: - https://patchwork.ozlabs.org/project/uboot/patch/20220326111911.13720-9-tommaso.merciai@amarulasolutions.com/ Signed-off-by: Tommaso Merciai Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6d67df7692f1..6a209395452a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -59,6 +59,14 @@ enable-active-high; }; + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 255>; + num-interpolated-steps = <255>; + default-brightness-level = <250>; + }; + ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; @@ -395,6 +403,12 @@ status = "okay"; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_backlight>; + status = "okay"; +}; + &iomuxc { pinctrl_fec1: fec1grp { fsl,pins = < @@ -549,4 +563,10 @@ MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 >; }; + + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06 + >; + }; }; -- cgit v1.2.3 From 7899eb6cb15d54a907adc73efacb4a373c697598 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Thu, 14 Apr 2022 09:15:05 -0700 Subject: arm64: dts: imx: Add i.MX8M Plus Gateworks gw7400 dts support The Gateworks GW7400 is an ARM based single board computer (SBC) featuring: - i.MX8M Plus SoC - LPDDR4 DRAM - eMMC FLASH - Gateworks System Controller (GSC) - QOS GbE - Microchip GbE Switch - Multiple multi-protocol RS232/RS485/RS422 Serial ports - USB 3.0 Front panel connector - onboard 802.11ac WiFi / BT - 3x miniPCIe socket with PCIe and USB 2.0 - 1x M.2 B/A-E socket with PCIe, USB 3.0 and dual nano-SIM sockets - off-board connectors for: MIPI DSI, MIPI CSI, SPI, GPIO, I2C - Wide range DC power input - Passive PoE - 802.3at PoE Signed-off-by: Tim Harvey Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../boot/dts/freescale/imx8mp-venice-gw74xx.dts | 896 +++++++++++++++++++++ 2 files changed, 897 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index bdb76e67ccfe..851e6faf8c05 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts new file mode 100644 index 000000000000..101d31147603 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -0,0 +1,896 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 Gateworks Corporation + */ + +/dts-v1/; + +#include +#include +#include + +#include "imx8mp.dtsi" + +/ { + model = "Gateworks Venice GW74xx i.MX8MP board"; + compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp"; + + aliases { + ethernet0 = &eqos; + ethernet1 = &fec; + ethernet2 = &lan1; + ethernet3 = &lan2; + ethernet4 = &lan3; + ethernet5 = &lan4; + ethernet6 = &lan5; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x0 0x40000000 0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + key-0 { + label = "user_pb"; + gpios = <&gpio 2 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-1 { + label = "user_pb1x"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <0>; + }; + + key-2 { + label = "key_erased"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <1>; + }; + + key-3 { + label = "eeprom_wp"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <2>; + }; + + key-4 { + label = "tamper"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <5>; + }; + + key-5 { + label = "switch_hold"; + linux,code = ; + interrupt-parent = <&gsc>; + interrupts = <7>; + }; + }; + + led-controller { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_HEARTBEAT; + color = ; + gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + pps { + compatible = "pps-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + reg_usb2_vbus: regulator-usb2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2>; + compatible = "regulator-fixed"; + regulator-name = "usb_usb2_vbus"; + gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_can>; + regulator-name = "can2_stby"; + gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_wifi_en: regulator-wifi-en { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_wifi>; + compatible = "regulator-fixed"; + regulator-name = "wl"; + gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +/* off-board header */ +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + local-mac-address = [00 00 00 00 00 00]; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "dio0", "", "dio1", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "m2_gdis#", "", "", "", "", "", "", "m2_rst#", + "", "", "", "", "", "", "", "", + "m2_off#", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "m2_wdis#", "", "", "", + "", "", "", "", "", "", "", "uart_rs485"; +}; + +&gpio5 { + gpio-line-names = + "uart_half", "uart_term", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + gsc: gsc@20 { + compatible = "gw,gsc"; + reg = <0x20>; + pinctrl-0 = <&pinctrl_gsc>; + interrupt-parent = <&gpio4>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <1>; + + adc { + compatible = "gw,gsc-adc"; + #address-cells = <1>; + #size-cells = <0>; + + channel@6 { + gw,mode = <0>; + reg = <0x06>; + label = "temp"; + }; + + channel@8 { + gw,mode = <1>; + reg = <0x08>; + label = "vdd_bat"; + }; + + channel@82 { + gw,mode = <2>; + reg = <0x82>; + label = "vdd_adc1"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@84 { + gw,mode = <2>; + reg = <0x84>; + label = "vdd_adc2"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@86 { + gw,mode = <2>; + reg = <0x86>; + label = "vdd_vin"; + gw,voltage-divider-ohms = <22100 1000>; + }; + + channel@88 { + gw,mode = <2>; + reg = <0x88>; + label = "vdd_3p3"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@8c { + gw,mode = <2>; + reg = <0x8c>; + label = "vdd_2p5"; + gw,voltage-divider-ohms = <10000 10000>; + }; + + channel@90 { + gw,mode = <2>; + reg = <0x90>; + label = "vdd_soc"; + }; + + channel@92 { + gw,mode = <2>; + reg = <0x92>; + label = "vdd_arm"; + }; + + channel@98 { + gw,mode = <2>; + reg = <0x98>; + label = "vdd_1p8"; + }; + + channel@9a { + gw,mode = <2>; + reg = <0x9a>; + label = "vdd_1p2"; + }; + + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_dram"; + }; + + channel@a2 { + gw,mode = <2>; + reg = <0xa2>; + label = "vdd_gsc"; + gw,voltage-divider-ohms = <10000 10000>; + }; + }; + }; + + gpio: gpio@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gsc>; + interrupts = <4>; + }; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio3>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + regulators { + BUCK1 { + regulator-name = "BUCK1"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + BUCK2 { + regulator-name = "BUCK2"; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1025000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + BUCK4 { + regulator-name = "BUCK4"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK5 { + regulator-name = "BUCK5"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + BUCK6 { + regulator-name = "BUCK6"; + regulator-min-microvolt = <1045000>; + regulator-max-microvolt = <1155000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <1710000>; + regulator-max-microvolt = <1890000>; + regulator-boot-on; + regulator-always-on; + }; + + LDO5 { + regulator-name = "LDO5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + rtc@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + accelerometer@19 { + compatible = "st,lis2de12"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + reg = <0x19>; + st,drdy-int-pin = <1>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT1"; + }; + + switch: switch@5f { + compatible = "microchip,ksz9897"; + reg = <0x5f>; + pinctrl-0 = <&pinctrl_ksz>; + interrupt-parent = <&gpio4>; + interrupts = <29 IRQ_TYPE_EDGE_FALLING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + label = "lan1"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan2: port@1 { + reg = <1>; + label = "lan2"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan3: port@2 { + reg = <2>; + label = "lan3"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan4: port@3 { + reg = <3>; + label = "lan4"; + local-mac-address = [00 00 00 00 00 00]; + }; + + lan5: port@4 { + reg = <4>; + label = "lan5"; + local-mac-address = [00 00 00 00 00 00]; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&fec>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +/* off-board header */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +/* off-board header */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +/* GPS / off-board header */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* RS232 console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +/* USB1 - Type C front panel */ +&usb3_phy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + status = "okay"; +}; + +&usb3_0 { + fsl,over-current-active-low; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 - USB3.0 Hub */ +&usb3_phy1 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ + MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ + MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ + MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ + MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ + MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ + >; + }; + + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 + MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 + MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 + MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 + MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 + MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f + MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f + MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f + MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f + MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f + MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 + MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + >; + }; + + pinctrl_gsc: gscgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_ksz: kszgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ + >; + }; + + pinctrl_gpio_leds: ledgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 + MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 + >; + }; + + pinctrl_reg_can: regcangrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154 + >; + }; + + pinctrl_reg_usb2: regusb2grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 + >; + }; + + pinctrl_reg_wifi: regwifigrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK + MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK + >; + }; + + pinctrl_spi2: spi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 + MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140 + >; + }; + + pinctrl_uart3_gpio: uart3gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 + >; + }; + + pinctrl_usb1: usb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 + MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 + MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 + MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 + MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 + MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 + MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166 + >; + }; +}; -- cgit v1.2.3 From 8ba8560d4ff1b1b2000aaed5500c56bfd3dfd69c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 4 Apr 2022 17:35:32 +0200 Subject: arm64: dts: renesas: r8a779f0: Add GPIO nodes Add device nodes for the General Purpose Input/Output (GPIO) blocks on the Renesas R-Car S4-8 (R8A779F0) SoC. Note that GPIO blocks 4-7 are not added, as they can only be accessed from the Control Domain. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/7fb68561026fa8bb5d9baf0596560c5c719a38cc.1649086225.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 60 +++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index eaea28cc5ffb..df46fb87cffc 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -76,6 +76,66 @@ <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; }; + gpio0: gpio@e6050180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 21>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@e6050980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6050980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 32 25>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@e6051180 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051180 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 64 17>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@e6051980 { + compatible = "renesas,gpio-r8a779f0", + "renesas,rcar-gen4-gpio"; + reg = <0 0xe6051980 0 0x54>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 915>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 96 19>; + interrupt-controller; + #interrupt-cells = <2>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; -- cgit v1.2.3 From 65b96377bf9130617ced41f317f3ec387d3e0dc3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:03:57 +0200 Subject: arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 4 ++-- arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 8bd6d7e8a474..6b3057a09251 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1045,8 +1045,8 @@ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi index 636c8817df7e..3125c3869c69 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi @@ -671,8 +671,8 @@ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>, <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>; clock-names = "ref_clk", "phy_clk"; - freq-table-hz = <0 0 - 0 0>; + freq-table-hz = <0 0>, + <0 0>; /* offset: 0x84; bit: 12 */ resets = <&crg_rst 0x84 12>; reset-names = "rst"; -- cgit v1.2.3 From 1ed29355df221407370933522a94dc8a0f47eb35 Mon Sep 17 00:00:00 2001 From: Michael Srba Date: Mon, 11 Apr 2022 09:21:56 +0200 Subject: arm64: dts: qcom: msm8998: reserve potentially inaccessible clocks With the gcc driver now being more complete and describing clocks which might not always be write-accessible to the OS, conservatively specify all such clocks as protected in the SoC dts. The board dts - or even user-supplied dts - can override this property to reflect the actual configuration. Signed-off-by: Michael Srba Reviewed-by: Jeffrey Hugo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411072156.24451-6-michael.srba@seznam.cz --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 2fda21e810c9..4a84de6cee1e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -815,6 +815,21 @@ clock-names = "xo", "sleep_clk"; clocks = <&xo>, <&sleep_clk>; + + /* + * The hypervisor typically configures the memory region where these clocks + * reside as read-only for the HLOS. If the HLOS tried to enable or disable + * these clocks on a device with such configuration (e.g. because they are + * enabled but unused during boot-up), the device will most likely decide + * to reboot. + * In light of that, we are conservative here and we list all such clocks + * as protected. The board dts (or a user-supplied dts) can override the + * list of protected clocks if it differs from the norm, and it is in fact + * desired for the HLOS to manage these clocks + */ + protected-clocks = , + , + ; }; rpm_msg_ram: sram@778000 { -- cgit v1.2.3 From 48995e863307bf08a51362a0aafb10e70bdafb4e Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 11 Apr 2022 02:44:56 +0300 Subject: arm64: dts: qcom: sm8450: Add thermal sensor controllers The change adds description of two thermal sensor controllers found on SM8450. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410234458.1739279-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 2cfc67b75259..f498951a25f8 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1364,6 +1364,28 @@ interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + #qcom,sensors = <16>; + interrupts = , + ; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + aoss_qmp: power-controller@c300000 { compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; reg = <0 0x0c300000 0 0x400>; -- cgit v1.2.3 From fccf8e31ac3d7c3f874ae5d78de495edaf1ead58 Mon Sep 17 00:00:00 2001 From: Vladimir Zapolskiy Date: Mon, 11 Apr 2022 02:44:57 +0300 Subject: arm64: dts: qcom: sm8450: Add thermal zones Add thermal zones handled by tsens sensors. The definitions and the trip points were taken from the downstream dts. For the CPU core thermal sensors, the trip points were changed to follow the example of other Qualcomm platforms. Signed-off-by: Vladimir Zapolskiy Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220410234458.1739279-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 843 +++++++++++++++++++++++++++++++++++ 1 file changed, 843 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index f498951a25f8..82083b16e4c1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -11,6 +11,7 @@ #include #include #include +#include / { interrupt-parent = <&intc>; @@ -47,6 +48,7 @@ power-domains = <&CPU_PD0>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -65,6 +67,7 @@ power-domains = <&CPU_PD1>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -80,6 +83,7 @@ power-domains = <&CPU_PD2>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -95,6 +99,7 @@ power-domains = <&CPU_PD3>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; + #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -110,6 +115,7 @@ power-domains = <&CPU_PD4>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -125,6 +131,7 @@ power-domains = <&CPU_PD5>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -141,6 +148,7 @@ power-domains = <&CPU_PD6>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; + #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -156,6 +164,7 @@ power-domains = <&CPU_PD7>; power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; + #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -1906,6 +1915,840 @@ }; }; + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpuss4-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + cpu4_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + cpu4_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + cpu5_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + cpu5_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + cpu6_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + cpu6_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + cpu7_top_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_top_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + cpu7_middle_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_middle_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + cpu7_bottom_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7_bottom_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + gpu-top-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + gpu-bottom-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens0 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + cpu0_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + cpu1_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + cpu2_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + cpu3_alert0: trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_alert1: trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3_crit: cpu_crit { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cdsp0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_0_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 6>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_1_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + cdsp2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 7>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + thermal-hal-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + + cdsp_2_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 8>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + mem-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 9>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + ddr_config0: ddr0-config { + temperature = <90000>; + hysteresis = <5000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 10>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss0_config0: mdmss0-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss0_config1: mdmss0-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 11>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss1_config0: mdmss1-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss1_config1: mdmss1-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss2_config0: mdmss2-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss2_config1: mdmss2-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + mdmss3_config0: mdmss3-config0 { + temperature = <102000>; + hysteresis = <3000>; + type = "passive"; + }; + + mdmss3_config1: mdmss3-config1 { + temperature = <105000>; + hysteresis = <3000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + thermal-engine-config { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + + reset-mon-cfg { + temperature = <115000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , -- cgit v1.2.3 From fc0e7dd6d2e2c9f8b2c6497a190ee29d8f3aef3a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 11 Apr 2022 10:59:34 +0200 Subject: arm64: dts: qcom: do not use underscore in BCM node name Align BCM voter node with DT schema by using hyphen instead of underscore. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220411085935.130072-3-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +- arch/arm64/boot/dts/qcom/sm8350.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index e1c46b80f14a..86175d257b1e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3522,7 +3522,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 6c6112427ef9..fb1a0f662575 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1450,7 +1450,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index f0c550155d03..2700a8145cb9 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -4072,7 +4072,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 33ea5ed4c0f5..13f57c8e2f1c 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4654,7 +4654,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e70687d6c2da..abdbfd456d2f 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -1881,7 +1881,7 @@ }; }; - apps_bcm_voter: bcm_voter { + apps_bcm_voter: bcm-voter { compatible = "qcom,bcm-voter"; }; }; -- cgit v1.2.3 From efbd3599154cb3d947564a9dce419a6754d233ef Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:02 +0530 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: change firmware path and use mbn format The "qcom/sdm845/" path conflicts with db845c's firmware that are present in the linux-firmware package. Xiaomi uses their own signed firmware for Poco F1 and can't use the db845c's firmware. So let's use "qcom/sdm845/beryllium/" to distinguish Poco F1's firmware files. For easier handling and packaging, the mdt+bXX files are squashed using Bjorn Andersson's pil-squasher tool from this link: https://github.com/andersson/pil-squasher Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB700966DEE6F6044EBEB5B892D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 367389526b41..27ba9ad1ad02 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -121,7 +121,7 @@ &adsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/adsp.mdt"; + firmware-name = "qcom/sdm845/beryllium/adsp.mbn"; }; &apps_rsc { @@ -208,7 +208,7 @@ &cdsp_pas { status = "okay"; - firmware-name = "qcom/sdm845/cdsp.mdt"; + firmware-name = "qcom/sdm845/beryllium/cdsp.mbn"; }; &dsi0 { @@ -262,7 +262,7 @@ zap-shader { memory-region = <&gpu_mem>; - firmware-name = "qcom/sdm845/a630_zap.mbn"; + firmware-name = "qcom/sdm845/beryllium/a630_zap.mbn"; }; }; @@ -289,7 +289,7 @@ &mss_pil { status = "okay"; - firmware-name = "qcom/sdm845/mba.mbn", "qcom/sdm845/modem.mdt"; + firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; }; &pm8998_gpio { -- cgit v1.2.3 From 84b6c2420415767079baa24ffd70d048cd35bdd8 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:03 +0530 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom ipa driver Enable Qualcomm IP Accelerator (IPA) driver for mobile data functionality which works by using ModemManager. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009405D7C06C0B480974063D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 27ba9ad1ad02..801b8c5984a3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -292,6 +292,12 @@ firmware-name = "qcom/sdm845/beryllium/mba.mbn", "qcom/sdm845/beryllium/modem.mbn"; }; +&ipa { + status = "okay"; + memory-region = <&ipa_fw_mem>; + firmware-name = "qcom/sdm845/beryllium/ipa_fws.mbn"; +}; + &pm8998_gpio { vol_up_pin_a: vol-up-active { pins = "gpio6"; -- cgit v1.2.3 From 1f1c494082a1f10d03ce4ee1485ee96d212e22ff Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:04 +0530 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: fix typo in panel's vddio-supply property vddio is misspelled with a "0" instead of "o". Fix it. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009901651E6A8D5ACB0425ED91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 801b8c5984a3..f97900e7797b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -218,7 +218,7 @@ panel@0 { compatible = "tianma,fhd-video"; reg = <0>; - vddi0-supply = <&vreg_l14a_1p8>; + vddio-supply = <&vreg_l14a_1p8>; vddpos-supply = <&lab>; vddneg-supply = <&ibb>; -- cgit v1.2.3 From 3213b3741a147db59ed6f1ebc5f569854725b91f Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Wed, 30 Mar 2022 12:15:05 +0530 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: enable second wifi channel Like the c630, the Poco F1 is also capable of using both antenna channels for 2.4 and 5ghz wifi, however unlike the c630 only the first channel is used for bluetooth. Similar to Oneplus 6. Signed-off-by: Joel Selvaraj Reviewed-by: Caleb Connolly Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB7009E2566F9000F338432761D91F9@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index f97900e7797b..798fc72578a7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -185,6 +185,12 @@ regulator-initial-mode = ; }; + vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + vreg_l24a_3p075: ldo24 { regulator-min-microvolt = <3088000>; regulator-max-microvolt = <3088000>; @@ -547,6 +553,7 @@ vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; }; /* PINCTRL - additions to nodes defined in sdm845.dtsi */ -- cgit v1.2.3 From 89561886191c0dcb6ce1491f14552eac16e14a80 Mon Sep 17 00:00:00 2001 From: Joel Selvaraj Date: Fri, 1 Apr 2022 05:48:10 +0530 Subject: arm64: dts: qcom: sdm845-xiaomi-beryllium: enable qcom wled backlight and link to panel Xiaomi Poco F1 uses the QCOM WLED driver for backlight control. Enable and link it to the panel to use it. Signed-off-by: Joel Selvaraj Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/BY5PR02MB70092607CD7CDD8CF8BCD464D9E09@BY5PR02MB7009.namprd02.prod.outlook.com --- arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts index 798fc72578a7..d88dc07205f7 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-xiaomi-beryllium.dts @@ -231,6 +231,7 @@ #address-cells = <1>; #size-cells = <0>; + backlight = <&pmi8998_wled>; reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; port { @@ -314,6 +315,17 @@ }; }; +&pmi8998_wled { + status = "okay"; + qcom,current-boost-limit = <970>; + qcom,ovp-millivolt = <29600>; + qcom,current-limit-microamp = <20000>; + qcom,num-strings = <2>; + qcom,switching-freq = <600>; + qcom,external-pfet; + qcom,cabc; +}; + &pm8998_pon { resin { compatible = "qcom,pm8941-resin"; -- cgit v1.2.3 From c46e3c4bdfaca1595b898bb58b112fd683fe0c11 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 2 Apr 2022 21:28:58 +0200 Subject: arm64: dts: qcom: msm8994: override nodes by label Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220402192859.154977-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts index 6e43e4339f55..dbfbb77e9ff5 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts @@ -27,15 +27,13 @@ chosen { stdout-path = "serial0:115200n8"; }; +}; - soc { - serial@f991e000 { - status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; - }; - }; +&blsp1_uart2 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; }; &tlmm { -- cgit v1.2.3 From 2a80a66f68e37ce19dee7fdb3d3e946859712b53 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 2 Apr 2022 21:28:59 +0200 Subject: arm64: dts: qcom: msm8996: override nodes by label Using node paths to extend or override a device tree node is error prone. If there was a typo error, a new node will be created instead of extending the existing node. This will lead to run-time errors that could be hard to detect. A mistyped label on the other hand, will cause a dtc compile error (during build time). This also reduces the indentation making the code easier to read. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220402192859.154977-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/qcom/msm8996-mtp.dts | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts index 6a1699a96c99..596ad4c896f5 100644 --- a/arch/arm64/boot/dts/qcom/msm8996-mtp.dts +++ b/arch/arm64/boot/dts/qcom/msm8996-mtp.dts @@ -18,12 +18,10 @@ chosen { stdout-path = "serial0"; }; +}; - soc { - serial@75b0000 { - status = "okay"; - }; - }; +&blsp2_uart2 { + status = "okay"; }; &hdmi { -- cgit v1.2.3 From 97276cbfb4fbe33c3ab8b5f5277a73c0b5f3732b Mon Sep 17 00:00:00 2001 From: Sandeep Maheswaram Date: Tue, 12 Apr 2022 00:46:54 +0530 Subject: arm64: dts: qcom: sc7280: Add wakeup-source property for USB node Adding wakeup-source property for USB controller in SC7280. This property is added to inform that the USB controller is wake up capable and to conditionally power down the phy during system suspend. Signed-off-by: Sandeep Maheswaram Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1649704614-31518-7-git-send-email-quic_c_sanm@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 9ece35736515..00bacc4ae4f7 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3106,6 +3106,7 @@ phys = <&usb_1_hsphy>, <&usb_1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; maximum-speed = "super-speed"; + wakeup-source; }; }; -- cgit v1.2.3 From bc08fbf49bc87e7613717e41674303905a9934fc Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:35 -0700 Subject: arm64: dts: qcom: sm8350: Define GPI DMA engines The Qualcomm SM8350 has three GPI DMA engines, add definitions for these. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-1-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index abdbfd456d2f..f60e35d7fe08 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -675,6 +676,28 @@ }; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x5f6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x008c0000 0x0 0x6000>; @@ -840,12 +863,37 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x09800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x5b6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x6000>; @@ -1078,12 +1126,37 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0xff>; + iommus = <&apps_smmu 0x56 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; -- cgit v1.2.3 From ddc97e7d1765cb2bf6089e211dae8e0b63cb3892 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:36 -0700 Subject: arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-2-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index f60e35d7fe08..c0137bdcf94b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -718,6 +718,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = ; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -731,6 +734,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -744,6 +750,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = ; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -757,6 +766,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -770,6 +782,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = ; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -783,6 +798,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -796,6 +814,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = ; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -809,6 +830,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -824,6 +848,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -850,6 +877,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = ; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -914,6 +944,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = ; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -927,6 +960,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -940,6 +976,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = ; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -953,6 +992,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -966,6 +1008,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = ; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -979,6 +1024,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1009,6 +1057,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1022,6 +1073,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = ; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1035,6 +1089,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1048,6 +1105,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = ; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1061,6 +1121,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1074,6 +1137,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = ; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1087,6 +1153,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1113,6 +1182,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = ; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1177,6 +1249,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1190,6 +1265,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1203,6 +1281,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1216,6 +1297,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1229,6 +1313,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = ; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1242,6 +1329,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1255,6 +1345,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1268,6 +1361,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1281,6 +1377,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = ; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1294,6 +1393,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1307,6 +1409,9 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = ; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1320,6 +1425,9 @@ interrupts = ; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit v1.2.3 From 83b8347a858d06f7d070663cc3898215d3d299a0 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 12 Apr 2022 14:51:37 -0700 Subject: arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Some versions of the firmware for the SM8350 Hardware Development Kit (HDK) has FIFO mode disabled for i2c13 and must thus use GPI DMA. Enable &gpi_dma1 to allow this. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Link: https://lore.kernel.org/r/20220412215137.2385831-3-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 1e5e9405d8b1..0fcf5bd88fc7 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -213,6 +213,10 @@ firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&gpi_dma1 { + status = "okay"; +}; + &mpss { status = "okay"; firmware-name = "qcom/sm8350/modem.mbn"; -- cgit v1.2.3 From b9c8433083097327cad19fbf633fb0735a008315 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:24 +0530 Subject: arm64: dts: qcom: sm8450: Add gpi_dma nodes GPI DMA can be used for DMA operations for QUP devices, so add the three gpi_dma insances found in this SoC Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 67 ++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 82083b16e4c1..8f1d07ab6163 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -702,6 +703,50 @@ "sleep_clk"; }; + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x800000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x496 0x0>; + status = "disabled"; + }; + + gpi_dma0: dma-controller@900000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0x900000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x5b6 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x009c0000 0x0 0x2000>; @@ -727,6 +772,28 @@ }; }; + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8450-gpi-dma"; + #dma-cells = <3>; + reg = <0 0xa00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7e>; + iommus = <&apps_smmu 0x56 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; -- cgit v1.2.3 From 488922c1a372579bf2caf40933e7459e3c86276f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:25 +0530 Subject: arm64: dts: qcom: sm8450: Fix missing iommus for qup qupv3_id_0 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. While at it also add interconnect nodes for qup Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 8f1d07ab6163..7b079afffe8f 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -753,6 +753,9 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x5a3 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; -- cgit v1.2.3 From a84e88e9a00334f1468a9f69a77091dbe80b7a3b Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:26 +0530 Subject: arm64: dts: qcom: sm8450: Add qup nodes for qup0 qup0 has 7 SEs, with SE7 as uart and already added, so add the remaining 6 SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-4-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 412 +++++++++++++++++++++++++++++++++++ 1 file changed, 412 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 7b079afffe8f..1b11c16b241c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -343,6 +343,25 @@ }; }; + qup_opp_table_100mhz: qup-100mhz-opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -761,6 +780,292 @@ ranges; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00980000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00984000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00988000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x0098c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00990000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + power-domains = <&rpmhpd SM8450_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00994000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x998000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + uart7: serial@99c000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x0099c000 0 0x4000>; @@ -1541,6 +1846,41 @@ }; }; + qup_i2c0_data_clk: qup-i2c0-data-clk { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk { + pins = "gpio8", "gpio9"; + function = "qup2"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk { + pins = "gpio12", "gpio13"; + function = "qup3"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk { + pins = "gpio16", "gpio17"; + function = "qup4"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk { + pins = "gpio206", "gpio207"; + function = "qup5"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk { + pins = "gpio20", "gpio21"; + function = "qup6"; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; @@ -1555,6 +1895,78 @@ bias-pull-up; }; + qup_spi0_cs: qup-spi0-cs { + pins = "gpio3"; + function = "qup0"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup0"; + }; + + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup1"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup1"; + }; + + qup_spi2_cs: qup-spi2-cs { + pins = "gpio11"; + function = "qup2"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup2"; + }; + + qup_spi3_cs: qup-spi3-cs { + pins = "gpio15"; + function = "qup3"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { + pins = "gpio12", "gpio13", "gpio14"; + function = "qup3"; + }; + + qup_spi4_cs: qup-spi4-cs { + pins = "gpio19"; + function = "qup4"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { + pins = "gpio16", "gpio17", "gpio18"; + function = "qup4"; + }; + + qup_spi5_cs: qup-spi5-cs { + pins = "gpio85"; + function = "qup5"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { + pins = "gpio206", "gpio207", "gpio84"; + function = "qup5"; + }; + + qup_spi6_cs: qup-spi6-cs { + pins = "gpio23"; + function = "qup6"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { + pins = "gpio20", "gpio21", "gpio22"; + function = "qup6"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; -- cgit v1.2.3 From 1a380216fd6fcf7135b2b413bb9431fc98e2fa23 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:27 +0530 Subject: arm64: dts: qcom: sm8450: Add qup nodes for qup1 qup1 has 7 SEs, I2C13 and I2C14 were already added so added the remaining SEs (i2c and spi) along with pinconf for these SEs Also add interconnect properties for I2C13 and I2C14 Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-5-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 359 +++++++++++++++++++++++++++++++++++ 1 file changed, 359 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1b11c16b241c..a39949f5329d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1113,6 +1113,206 @@ ranges; status = "disabled"; + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c13: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0 0x00a94000 0 0x4000>; @@ -1121,6 +1321,33 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_data_clk>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a94000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1134,6 +1361,33 @@ pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_data_clk>; interrupts = ; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00a98000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1881,6 +2135,31 @@ function = "qup6"; }; + qup_i2c8_data_clk: qup-i2c8-data-clk { + pins = "gpio28", "gpio29"; + function = "qup8"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk { + pins = "gpio32", "gpio33"; + function = "qup9"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk { + pins = "gpio36", "gpio37"; + function = "qup10"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk { + pins = "gpio40", "gpio41"; + function = "qup11"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk { + pins = "gpio44", "gpio45"; + function = "qup12"; + }; + qup_i2c13_data_clk: qup-i2c13-data-clk { pins = "gpio48", "gpio49"; function = "qup13"; @@ -1967,6 +2246,86 @@ function = "qup6"; }; + qup_spi8_cs: qup-spi8-cs { + pins = "gpio31"; + function = "qup8"; + }; + + qup_spi8_data_clk: qup-spi8-data-clk { + pins = "gpio28", "gpio29", "gpio30"; + function = "qup8"; + }; + + qup_spi9_cs: qup-spi9-cs { + pins = "gpio35"; + function = "qup9"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { + pins = "gpio32", "gpio33", "gpio34"; + function = "qup9"; + }; + + qup_spi10_cs: qup-spi10-cs { + pins = "gpio39"; + function = "qup10"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { + pins = "gpio36", "gpio37", "gpio38"; + function = "qup10"; + }; + + qup_spi11_cs: qup-spi11-cs { + pins = "gpio43"; + function = "qup11"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { + pins = "gpio40", "gpio41", "gpio42"; + function = "qup11"; + }; + + qup_spi12_cs: qup-spi12-cs { + pins = "gpio47"; + function = "qup12"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup12"; + }; + + qup_spi13_cs: qup-spi13-cs { + pins = "gpio51"; + function = "qup13"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { + pins = "gpio48", "gpio49", "gpio50"; + function = "qup13"; + }; + + qup_spi14_cs: qup-spi14-cs { + pins = "gpio55"; + function = "qup14"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { + pins = "gpio52", "gpio53", "gpio54"; + function = "qup14"; + }; + + qup_spi15_cs: qup-spi15-cs { + pins = "gpio59"; + function = "qup15"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { + pins = "gpio56", "gpio57", "gpio58"; + function = "qup15"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; -- cgit v1.2.3 From ba640cd31342b45dcf2f95f6ca7dcbc46629919f Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:28 +0530 Subject: arm64: dts: qcom: sm8450: Add qup nodes for qup2 qup2 has 7 SEs, so add the SEs (i2c and spi) along with pinconf for these SEs Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-6-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 396 +++++++++++++++++++++++++++++++++++ 1 file changed, 396 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index a39949f5329d..e2d55c3b12d2 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -744,6 +744,299 @@ status = "disabled"; }; + qupv3_id_2: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x008c0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + iommus = <&apps_smmu 0x483 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c15: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi15: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00880000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c16: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c16_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi16: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00884000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c17: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c17_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi17: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x00888000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c18: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x0088c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c18_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi18: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c19: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00890000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c19_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi19: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c20: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00894000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c20_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi20: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c21: i2c@898000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x00898000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c21_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, + <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, + <&gpi_dma2 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi21: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00898000 0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; + spi-max-frequency = <50000000>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, + <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; + interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, + <&gpi_dma2 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + gpi_dma0: dma-controller@900000 { compatible = "qcom,sm8450-gpi-dma"; #dma-cells = <3>; @@ -2174,6 +2467,41 @@ bias-pull-up; }; + qup_i2c15_data_clk: qup-i2c15-data-clk { + pins = "gpio56", "gpio57"; + function = "qup15"; + }; + + qup_i2c16_data_clk: qup-i2c16-data-clk { + pins = "gpio60", "gpio61"; + function = "qup16"; + }; + + qup_i2c17_data_clk: qup-i2c17-data-clk { + pins = "gpio64", "gpio65"; + function = "qup17"; + }; + + qup_i2c18_data_clk: qup-i2c18-data-clk { + pins = "gpio68", "gpio69"; + function = "qup18"; + }; + + qup_i2c19_data_clk: qup-i2c19-data-clk { + pins = "gpio72", "gpio73"; + function = "qup19"; + }; + + qup_i2c20_data_clk: qup-i2c20-data-clk { + pins = "gpio76", "gpio77"; + function = "qup20"; + }; + + qup_i2c21_data_clk: qup-i2c21-data-clk { + pins = "gpio80", "gpio81"; + function = "qup21"; + }; + qup_spi0_cs: qup-spi0-cs { pins = "gpio3"; function = "qup0"; @@ -2326,6 +2654,74 @@ function = "qup15"; }; + qup_spi16_cs: qup-spi16-cs { + pins = "gpio63"; + function = "qup16"; + }; + + qup_spi16_data_clk: qup-spi16-data-clk { + pins = "gpio60", "gpio61", "gpio62"; + function = "qup16"; + }; + + qup_spi17_cs: qup-spi17-cs { + pins = "gpio67"; + function = "qup17"; + }; + + qup_spi17_data_clk: qup-spi17-data-clk { + pins = "gpio64", "gpio65", "gpio66"; + function = "qup17"; + }; + + qup_spi18_cs: qup-spi18-cs { + pins = "gpio71"; + function = "qup18"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi18_data_clk: qup-spi18-data-clk { + pins = "gpio68", "gpio69", "gpio70"; + function = "qup18"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_cs: qup-spi19-cs { + pins = "gpio75"; + function = "qup19"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi19_data_clk: qup-spi19-data-clk { + pins = "gpio72", "gpio73", "gpio74"; + function = "qup19"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi20_cs: qup-spi20-cs { + pins = "gpio79"; + function = "qup20"; + }; + + qup_spi20_data_clk: qup-spi20-data-clk { + pins = "gpio76", "gpio77", "gpio78"; + function = "qup20"; + }; + + qup_spi21_cs: qup-spi21-cs { + pins = "gpio83"; + function = "qup21"; + }; + + qup_spi21_data_clk: qup-spi21-data-clk { + pins = "gpio80", "gpio81", "gpio82"; + function = "qup21"; + }; + qup_uart7_rx: qup-uart7-rx { pins = "gpio26"; function = "qup7"; -- cgit v1.2.3 From 67ebdc6dd1e2049fd9620f0572bc81a809afbe24 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:29 +0530 Subject: arm64: dts: qcom: sm8450: Fix missing iommus for qup1 qupv3_id_1 was missing iommus property which cause any dma transaction to fail and board crash. So add the missing iommus. Fixes: 5188049c9b36 ("arm64: dts: qcom: Add base SM8450 DTSI") Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-7-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index e2d55c3b12d2..764e4be756db 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1401,6 +1401,9 @@ clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; + interconnect-names = "qup-core"; #address-cells = <2>; #size-cells = <2>; ranges; -- cgit v1.2.3 From d953239726e971ecaee45d86b4bcd605be839b2a Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 14 Apr 2022 15:46:30 +0530 Subject: arm64: dts: qcom: sm8450-qrd: Enable spi and i2c nodes Enable the i2c5, spi4, spi18 and spi19 nodes which were tested on qrd board along with related qup nodes and gpi_dma0 Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220414101630.1189052-8-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sm8450-qrd.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts index d33e86a375c0..236e53974fdd 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-qrd.dts @@ -352,10 +352,22 @@ vdda-pll-supply = <&vreg_l6b_1p2>; }; +&gpi_dma0 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; +&qupv3_id_2 { + status = "okay"; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; @@ -376,6 +388,18 @@ firmware-name = "qcom/sm8450/slpi.mbn"; }; +&spi4 { + status = "okay"; +}; + +&spi18 { + status = "okay"; +}; + +&spi19 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <28 4>, <36 4>; }; -- cgit v1.2.3 From ca79a997f2c0826ccf7d313068de3d04d5e8c82b Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:53 +0100 Subject: arm64: dts: qcom: sm8250: Add camcc DT node Add the camcc DT node for the Camera Clock Controller on sm8250. Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-2-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 13f57c8e2f1c..ab75d0f0aa7f 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -18,6 +18,7 @@ #include #include #include +#include #include / { @@ -3149,6 +3150,21 @@ #power-domain-cells = <1>; }; + camcc: clock-controller@ad00000 { + compatible = "qcom,sm8250-camcc"; + reg = <0 0x0ad00000 0 0x10000>; + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + power-domains = <&rpmhpd SM8250_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + mdss: mdss@ae00000 { compatible = "qcom,sm8250-mdss"; reg = <0 0x0ae00000 0 0x1000>; -- cgit v1.2.3 From 30325603b910e4ca61d56d20e2f5b9076d371e83 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:54 +0100 Subject: arm64: dts: qcom: sm8250: camss: Add CAMSS block definition Adds a CAMSS definition block. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-3-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 153 +++++++++++++++++++++++++++++++++++ 1 file changed, 153 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index ab75d0f0aa7f..061455bab53a 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,159 @@ #power-domain-cells = <1>; }; + camss: camss@ac6a000 { + compatible = "qcom,sm8250-camss"; + status = "disabled"; + + reg = <0 0xac6a000 0 0x2000>, + <0 0xac6c000 0 0x2000>, + <0 0xac6e000 0 0x1000>, + <0 0xac70000 0 0x1000>, + <0 0xac72000 0 0x1000>, + <0 0xac74000 0 0x1000>, + <0 0xacb4000 0 0xd000>, + <0 0xacc3000 0 0xd000>, + <0 0xacd9000 0 0x2200>, + <0 0xacdb200 0 0x2200>; + reg-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "csiphy5", + "csid0", + "csid1", + "csid2", + "csid3", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1"; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc TITAN_TOP_GDSC>; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY5_CLK>, + <&camcc CAM_CC_CSI5PHYTIMER_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_IFE_0_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_0_AREG_CLK>, + <&camcc CAM_CC_IFE_1_AHB_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_1_AREG_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_AXI_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + + clock-names = "cam_ahb_clk", + "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "csiphy5", + "csiphy5_timer", + "slow_ahb_src", + "vfe0_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe0_areg", + "vfe1_ahb", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe1_areg", + "vfe_lite_ahb", + "vfe_lite_axi", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + iommus = <&apps_smmu 0x800 0x400>, + <&apps_smmu 0x801 0x400>, + <&apps_smmu 0x840 0x400>, + <&apps_smmu 0x841 0x400>, + <&apps_smmu 0xc00 0x400>, + <&apps_smmu 0xc01 0x400>, + <&apps_smmu 0xc40 0x400>, + <&apps_smmu 0xc41 0x400>; + + interconnects = <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_CAMERA_CFG>, + <&mmss_noc MASTER_CAMNOC_HF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_SF &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_CAMNOC_ICP &mc_virt SLAVE_EBI_CH0>; + interconnect-names = "cam_ahb", + "cam_hf_0_mnoc", + "cam_sf_0_mnoc", + "cam_sf_icp_mnoc"; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sm8250-camcc"; reg = <0 0x0ad00000 0 0x10000>; -- cgit v1.2.3 From e7173009e139bc13bf7833ea4185dda4779b95f3 Mon Sep 17 00:00:00 2001 From: Bryan O'Donoghue Date: Fri, 15 Apr 2022 17:46:55 +0100 Subject: arm64: dts: qcom: sm8250: camss: Add CCI definitions sm8250 has two CCI busses with two I2C busses apiece. Co-developed-by: Julian Grahsl Signed-off-by: Julian Grahsl Reviewed-by: Vladimir Zapolskiy Signed-off-by: Bryan O'Donoghue Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415164655.1679628-4-bryan.odonoghue@linaro.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 162 +++++++++++++++++++++++++++++++++++ 1 file changed, 162 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 061455bab53a..26afaa4f98fe 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3150,6 +3150,88 @@ #power-domain-cells = <1>; }; + cci0: cci@ac4f000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac4f000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_0_CLK>, + <&camcc CAM_CC_CCI_0_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci0_default>; + pinctrl-1 = <&cci0_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci0_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci0_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cci1: cci@ac50000 { + compatible = "qcom,sm8250-cci"; + #address-cells = <1>; + #size-cells = <0>; + + reg = <0 0x0ac50000 0 0x1000>; + interrupts = ; + power-domains = <&camcc TITAN_TOP_GDSC>; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CCI_1_CLK>, + <&camcc CAM_CC_CCI_1_CLK_SRC>; + clock-names = "camnoc_axi", + "slow_ahb_src", + "cpas_ahb", + "cci", + "cci_src"; + + pinctrl-0 = <&cci1_default>; + pinctrl-1 = <&cci1_sleep>; + pinctrl-names = "default", "sleep"; + + status = "disabled"; + + cci1_i2c0: i2c-bus@0 { + reg = <0>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + cci1_i2c1: i2c-bus@1 { + reg = <1>; + clock-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + camss: camss@ac6a000 { compatible = "qcom,sm8250-camss"; status = "disabled"; @@ -3688,6 +3770,86 @@ gpio-ranges = <&tlmm 0 0 181>; wakeup-parent = <&pdc>; + cci0_default: cci0-default { + cci0_i2c0_default: cci0-i2c0-default { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci0_i2c1_default: cci0-i2c1-default { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci0_sleep: cci0-sleep { + cci0_i2c0_sleep: cci0-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio101", "gpio102"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + + cci0_i2c1_sleep: cci0-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio103", "gpio104"; + function = "cci_i2c"; + + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + }; + }; + + cci1_default: cci1-default { + cci1_i2c0_default: cci1-i2c0-default { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_default: cci1-i2c1-default { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-up; + drive-strength = <2>; /* 2 mA */ + }; + }; + + cci1_sleep: cci1-sleep { + cci1_i2c0_sleep: cci1-i2c0-sleep { + /* SDA, SCL */ + pins = "gpio105","gpio106"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + + cci1_i2c1_sleep: cci1-i2c1-sleep { + /* SDA, SCL */ + pins = "gpio107","gpio108"; + function = "cci_i2c"; + + bias-pull-down; + drive-strength = <2>; /* 2 mA */ + }; + }; + pri_mi2s_active: pri-mi2s-active { sclk { pins = "gpio138"; -- cgit v1.2.3 From 5d04419045e7ad28155e2f7403599b2fdbd1548f Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 15 Apr 2022 17:22:41 -0700 Subject: arm64: dts: qcom: sc7280: Add SAR sensors to herobrine crd Enable the two SAR sensors of the CRD based on herobrine. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415172238.1.I671bdf40fdfce7a35f6349fca0dc56145d4210ee@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index fd6eadc8581a..b06f61e9b90b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -49,6 +49,18 @@ ap_tp_i2c: &i2c0 { }; }; +&ap_sar_sensor_i2c { + status = "okay"; +}; + +&ap_sar_sensor0 { + status = "okay"; +}; + +&ap_sar_sensor1 { + status = "okay"; +}; + ap_ts_pen_1v8: &i2c13 { status = "okay"; clock-frequency = <400000>; -- cgit v1.2.3 From 1eae95fb1d696968ca72be3ac8e0d62bb4d8da42 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 13:05:02 +0530 Subject: arm64: dts: qcom: qrb5165-rb5: Fix can-clock node name Per DT spec node names should not have underscores (_) in them, so change can_clock to can-clock. Fixes: 5c44c564e449 ("arm64: dts: qcom: qrb5165-rb5: Add support for MCP2518FD") Signed-off-by: Vinod Koul Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421073502.1824089-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 845eb7a6bf92..0e63f707b911 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -29,7 +29,7 @@ }; /* Fixed crystal oscillator dedicated to MCP2518FD */ - clk40M: can_clock { + clk40M: can-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <40000000>; -- cgit v1.2.3 From cb29e7106d4ee7bc3860fc65d28b6d7d0b71c0f8 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 13:04:38 +0530 Subject: arm64: dts: qcom: db845c: Add support for MCP2517FD Add support for onboard MCP2517FD SPI CAN transceiver attached to SPI0 of RB3. Signed-off-by: Vinod Koul Reviewed-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421073438.1824061-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 32 ++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 9206efa9d6d2..194ebeb3259c 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -28,6 +28,13 @@ stdout-path = "serial0:115200n8"; }; + /* Fixed crystal oscillator dedicated to MCP2517FD */ + clk40M: can-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + dc12v: dc12v-regulator { compatible = "regulator-fixed"; regulator-name = "DC12V"; @@ -746,6 +753,23 @@ }; }; +&spi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + cs-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; + + can@0 { + compatible = "microchip,mcp2517fd"; + reg = <0>; + clocks = <&clk40M>; + interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdc_5v>; + xceiver-supply = <&vdc_5v>; + }; +}; + &spi2 { /* On Low speed expansion */ label = "LS-SPI0"; @@ -1220,3 +1244,11 @@ }; }; }; + +/* PINCTRL - additions to nodes defined in sdm845.dtsi */ +&qup_spi0_default { + config { + drive-strength = <6>; + bias-disable; + }; +}; -- cgit v1.2.3 From 2a31f958f8326c263f2af2511cd6d8256d81e810 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 19 Apr 2022 02:25:09 +0530 Subject: arm64: dts: qcom: sm8450: Fix qmp phy node (use phy@ instead of lanes@) Fix the following 'make dtbs_check' warning(s) by using phy@ instead of lanes@: arch/arm64/boot/dts/qcom/sm8450-hdk.dtb: phy@1c0f000: 'lanes@1c0e000' does not match any of the regexes: '^phy@[0-9a-f]+$', 'pinctrl-[0-9]+' Cc: Bjorn Andersson Cc: Rob Herring Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220418205509.1102109-5-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 764e4be756db..7f52c3cfdfb7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -1785,7 +1785,7 @@ status = "disabled"; - pcie0_lane: lanes@1c06200 { + pcie0_lane: phy@1c06200 { reg = <0 0x1c06e00 0 0x200>, /* tx */ <0 0x1c07000 0 0x200>, /* rx */ <0 0x1c06200 0 0x200>, /* pcs */ @@ -1892,7 +1892,7 @@ status = "disabled"; - pcie1_lane: lanes@1c0e000 { + pcie1_lane: phy@1c0e000 { reg = <0 0x1c0e000 0 0x200>, /* tx */ <0 0x1c0e200 0 0x300>, /* rx */ <0 0x1c0f200 0 0x200>, /* pcs */ -- cgit v1.2.3 From c11e239f6aee32e20718dc3cf5349894d0e994ec Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:24 +0530 Subject: arm64: dts: qcom: sc7280: Add GPI DMAengines The Qualcomm SC7280 has two GPI DMAengines, add definitions for these. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-1-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 00bacc4ae4f7..43641db0e7de 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -915,6 +915,28 @@ }; + gpi_dma0: dma-controller@900000 { + #dma-cells = <3>; + compatible = "qcom,sc7280-gpi-dma"; + reg = <0 0x00900000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x7f>; + iommus = <&apps_smmu 0x0136 0x0>; + status = "disabled"; + }; + qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>; @@ -1344,6 +1366,28 @@ }; }; + gpi_dma1: dma-controller@a00000 { + #dma-cells = <3>; + compatible = "qcom,sc7280-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + dma-channels = <12>; + dma-channel-mask = <0x1e>; + iommus = <&apps_smmu 0x56 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x00ac0000 0 0x2000>; -- cgit v1.2.3 From 18bec7f725c5184f7c5b2a404602dd95f630d4d7 Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:25 +0530 Subject: arm64: dts: qcom: sc7280: Add GENI I2C/SPI DMA channels The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-2-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 43641db0e7de..f72451f7f539 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -964,6 +965,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -982,6 +986,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1016,6 +1023,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1034,6 +1044,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1068,6 +1081,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1086,6 +1102,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1120,6 +1139,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, + <&gpi_dma0 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1138,6 +1160,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1172,6 +1197,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1190,6 +1218,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1224,6 +1255,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1242,6 +1276,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1276,6 +1313,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1294,6 +1334,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1328,6 +1371,9 @@ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1346,6 +1392,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, + <&gpi_dma0 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1415,6 +1464,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1433,6 +1485,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1467,6 +1522,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1485,6 +1543,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1519,6 +1580,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1537,6 +1601,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1571,6 +1638,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1589,6 +1659,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1623,6 +1696,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1641,6 +1717,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1675,6 +1754,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1693,6 +1775,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1727,6 +1812,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1745,6 +1833,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1779,6 +1870,9 @@ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "qup-core", "qup-config", "qup-memory"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -1797,6 +1891,9 @@ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; interconnect-names = "qup-core", "qup-config"; + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit v1.2.3 From f238ff81e8946540e1a7c1496aa92fa2386893dc Mon Sep 17 00:00:00 2001 From: Vinod Koul Date: Thu, 21 Apr 2022 17:25:26 +0530 Subject: arm64: dts: qcom: sc7280-idp: Enable GPI DMAs Some versions of the firmware for the sc7280-idp board FIFO mode disabled and must thus use GPI DMA. Enable gpi_dma0 and gpi_dma1 to allow this. Co-developed-by: Vijaya Krishna Nivarthi Signed-off-by: Vijaya Krishna Nivarthi Signed-off-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220421115526.1828659-3-vkoul@kernel.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 015a3474d401..6a14259b93c4 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -233,6 +233,14 @@ }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + &ipa { status = "okay"; modem-init; -- cgit v1.2.3 From 510c527b4ff574bda5c20429eb563eda63c41198 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 18 Apr 2022 15:24:57 +0200 Subject: arm64: dts: imx8mm: Add i.MX8M Mini Toradex Verdin based Menlo board Add new board based on the Toradex Verdin iMX8M Mini SoM, the MX8Menlo. The board is a compatible replacement for i.MX53 M53Menlo and features USB, multiple UARTs, ethernet, LEDs, SD and eMMC. Reviewed-by: Fabio Estevam Reviewed-by: Francesco Dolcini Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Francesco Dolcini Cc: Marcel Ziswiler Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts | 321 ++++++++++++++++++++++ 2 files changed, 322 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 851e6faf8c05..cdf9dfcbe020 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-n801x-s.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts new file mode 100644 index 000000000000..c20db0c550da --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -0,0 +1,321 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2021-2022 Marek Vasut + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" + +/ { + model = "MENLO MX8MM EMBEDDED DEVICE"; + compatible = "menlo,mx8menlo", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; + + /delete-node/ gpio-keys; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + beeper { + compatible = "gpio-beeper"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_beeper>; + gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; + }; + + /* Fixed clock dedicated to SPI CAN on carrier board */ + clk_xtal20: clk-xtal20 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; +}; + +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + /* CAN controller on the baseboard */ + canfd: can@0 { + compatible = "microchip,mcp2518fd"; + clocks = <&clk_xtal20>; + interrupt-parent = <&gpio1>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + +}; + +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>; + status = "disabled"; +}; + +ðphy0 { + max-speed = <100>; +}; + +&fec1 { + status = "okay"; +}; + +&flexspi { + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio3 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "DISP_reset", "KBD_intI", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + /* + * CPLD_D[n] is ARM_CPLD[n] in schematic + * CPLD_int is SA_INTERRUPT in schematic + * CPLD_reset is RESET_SOFT in schematic + */ + gpio-line-names = + "CPLD_D[1]", "CPLD_int", "CPLD_reset", "", + "", "CPLD_D[0]", "", "", + "", "", "", "CPLD_D[2]", + "CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]", + "CPLD_D[7]", "", "", "", + "", "", "", "", + "", "", "", "KBD_intK", + "", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio_expander_21 { + status = "okay"; +}; + +&hwmon { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + /* None of this is present on the SoM. */ + /delete-node/ bridge@2c; + /delete-node/ hdmi@48; + /delete-node/ touch@4a; + /delete-node/ sensor@4f; + /delete-node/ eeprom@50; + /delete-node/ eeprom@57; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; + + pinctrl_beeper: beepergrp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 + >; + }; + + pinctrl_uart4_rts: uart4rtsgrp { + fsl,pins = < + /* SODIMM 222 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 + >; + }; +}; + +&pinctrl_gpio1 { + fsl,pins = < + /* SODIMM 206 */ + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4 + >; +}; + +&pinctrl_gpio_hog1 { + fsl,pins = < + /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 + /* CPLD_int */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 + /* CPLD_reset */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 + /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 + /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 + /* CPLD_D[7] */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 + /* CPLD_D[6] */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 + /* CPLD_D[5] */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 + /* CPLD_D[4] */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 + /* CPLD_D[3] */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 + /* CPLD_D[2] */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 + /* CPLD_D[1] */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 + /* CPLD_D[0] */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 + /* KBD_intK */ + MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4 + /* DISP_reset */ + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4 + /* KBD_intI */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4 + /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4 + >; +}; + +&pinctrl_uart1 { + fsl,pins = < + /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4 + /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4 + /* SODIMM 210 */ + MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4 + /* SODIMM 212 */ + MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4 + >; +}; + +®_usb_otg1_vbus { + /delete-property/ enable-active-high; + gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; +}; + +®_usb_otg2_vbus { + /delete-property/ enable-active-high; + gpio = <&gpio1 14 GPIO_ACTIVE_LOW>; +}; + +&sai2 { + status = "disabled"; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + status = "okay"; +}; -- cgit v1.2.3 From cc545760170590b5e6733ebfef8398f97d7dee05 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 18 Apr 2022 15:36:17 -0300 Subject: arm64: dts: imx8mn-evk: Add UART3 support UART3 pins are available in the J1003 connector. Add support for it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index dc75d6d13bb3..d1f6cccfa00d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -212,6 +212,15 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clk IMX8MN_CLK_UART3>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; + status = "okay"; +}; + &usbotg1 { dr_mode = "otg"; hnp-disable; @@ -374,6 +383,15 @@ >; }; + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140 + MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140 + >; + }; + pinctrl_usdhc2_gpio: usdhc2gpiogrp { fsl,pins = < MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 -- cgit v1.2.3 From a69d277460888c2bd99a6fa849f474a7197a3e16 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Fri, 8 Apr 2022 14:19:22 +0100 Subject: arm64: dts: Add Arm corstone1000 platform support Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. These device trees contains the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and the FPGA MPS3 board Cortex-A35 implementation at Cortex-A35 host side of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Link: https://lore.kernel.org/r/20220408131922.3864348-3-rui.silva@linaro.org Reviewed-by: Rob Herring Signed-off-by: Rui Miguel Silva Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/corstone1000-fvp.dts | 51 ++++++++ arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 32 +++++ arch/arm64/boot/dts/arm/corstone1000.dtsi | 164 ++++++++++++++++++++++++++ 4 files changed, 248 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/corstone1000-fvp.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000-mps3.dts create mode 100644 arch/arm64/boot/dts/arm/corstone1000.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 4382b73baef5..d908e96d7ddc 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -6,3 +6,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb juno-scmi.dtb ju dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts new file mode 100644 index 000000000000..26b0f1b3cea6 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FVP (Fixed Virtual Platform)"; + compatible = "arm,corstone1000-fvp"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan91c111"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + }; + + vmmc_v3_3d: fixed_v3_3d { + compatible = "regulator-fixed"; + regulator-name = "vmmc_supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + sdmmc0: mmc@40300000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x40300000 0x1000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; + + sdmmc1: mmc@50000000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x50000000 0x10000>; + interrupts = ; + max-frequency = <12000000>; + vmmc-supply = <&vmmc_v3_3d>; + clocks = <&smbclk>, <&refclk100mhz>; + clock-names = "smclk", "apb_pclk"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts new file mode 100644 index 000000000000..e3146747c2d9 --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +/dts-v1/; + +#include "corstone1000.dtsi" + +/ { + model = "ARM Corstone1000 FPGA MPS3 board"; + compatible = "arm,corstone1000-mps3"; + + smsc: ethernet@4010000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x40100000 0x10000>; + phy-mode = "mii"; + interrupts = ; + reg-io-width = <2>; + smsc,irq-push-pull; + }; + + usb_host: usb@40200000 { + compatible = "nxp,usb-isp1763"; + reg = <0x40200000 0x100000>; + interrupts = ; + bus-width = <16>; + dr_mode = "host"; + }; +}; diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi new file mode 100644 index 000000000000..4e46826f883a --- /dev/null +++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: GPL-2.0 or MIT +/* + * Copyright (c) 2022, Arm Limited. All rights reserved. + * Copyright (c) 2022, Linaro Limited. All rights reserved. + * + */ + +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0>; + next-level-cache = <&L2_0>; + }; + }; + + memory@88200000 { + device_type = "memory"; + reg = <0x88200000 0x77e00000>; + }; + + gic: interrupt-controller@1c000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x1c010000 0x1000>, + <0x1c02f000 0x2000>, + <0x1c04f000 0x1000>, + <0x1c06f000 0x2000>; + interrupts = ; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-sets = <1024>; + }; + + refclk100mhz: refclk100mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "apb_pclk"; + }; + + smbclk: refclk24mhzx2 { + /* Reference 24MHz clock x 2 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + clock-output-names = "smclk"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + uartclk: uartclk { + /* UART clock - 50MHz */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + clock-output-names = "uartclk"; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + timer@1a220000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x1a220000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + clock-frequency = <50000000>; + ranges; + + frame@1a230000 { + frame-number = <0>; + interrupts = ; + reg = <0x1a230000 0x1000>; + }; + }; + + uart0: serial@1a510000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a510000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@1a520000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1a520000 0x1000>; + interrupts = ; + clocks = <&uartclk>, <&refclk100mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + mhu_hse1: mailbox@1b820000 { + compatible = "arm,mhuv2-tx", "arm,primecell"; + reg = <0x1b820000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + + mhu_seh1: mailbox@1b830000 { + compatible = "arm,mhuv2-rx", "arm,primecell"; + reg = <0x1b830000 0x1000>; + clocks = <&refclk100mhz>; + clock-names = "apb_pclk"; + interrupts = ; + #mbox-cells = <2>; + arm,mhuv2-protocols = <0 0>; + secure-status = "okay"; /* secure-world-only */ + status = "disabled"; + }; + }; +}; -- cgit v1.2.3 From 5393158f009bdc5e9b55559ce4ad2b0700c46e73 Mon Sep 17 00:00:00 2001 From: Diego Sueiro Date: Thu, 21 Apr 2022 15:35:21 +0100 Subject: arm64: dts: fvp: Add virtio-rng support The virtio-rng is available from FVP_Base_RevC-2xAEMvA version 11.17, so add the devicetree node to support it. It is disabled by default to avoid any issues with models that doesn't support it. Link: https://lore.kernel.org/r/ac3be672c636091ee1e079cadce776b1fb7e0b2e.1650543392.git.diego.sueiro@arm.com Signed-off-by: Diego Sueiro Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/fvp-base-revc.dts | 3 ++- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 7 +++++++ arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 3 files changed, 10 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/fvp-base-revc.dts b/arch/arm64/boot/dts/arm/fvp-base-revc.dts index 269b649934b5..a496e39e6204 100644 --- a/arch/arm64/boot/dts/arm/fvp-base-revc.dts +++ b/arch/arm64/boot/dts/arm/fvp-base-revc.dts @@ -241,6 +241,7 @@ <0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, <0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, <0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, - <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + <0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <0 0 46 &gic 0 0 GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 33182d9e5826..1b6326514c97 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -21,6 +21,13 @@ reg = <0x150000 0x200>; interrupts = <44>; }; + + virtio-rng@200000 { + compatible = "virtio,mmio"; + reg = <0x200000 0x200>; + interrupts = <46>; + status = "disabled"; + }; }; }; }; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index 5f6cab668aa0..a999e7f52d8b 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -110,7 +110,7 @@ compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; - ranges = <0 3 0 0x200000>; + ranges = <0 3 0 0x210000>; v2m_sysreg: sysreg@10000 { compatible = "arm,vexpress-sysreg"; -- cgit v1.2.3 From d7030edf32ad5196af61a8d88e557ed2951b94cd Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Mon, 25 Apr 2022 14:55:24 +0100 Subject: arm64: dts: fvp: Align virtio device node names with dtschema Align the virtio mmio device tree node names with the schema to avoid any schema warnings. Link: https://lore.kernel.org/r/20220425135524.1077986-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/foundation-v8.dtsi | 2 +- arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi | 6 +++--- arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi index fbf13f7c2baf..83e3e7e3984f 100644 --- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi +++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi @@ -220,7 +220,7 @@ clock-names = "uartclk", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi index 1b6326514c97..ec2d5280a30b 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard-rs2.dtsi @@ -10,19 +10,19 @@ arm,v2m-memory-map = "rs2"; iofpga-bus@300000000 { - virtio-p9@140000 { + virtio@140000 { compatible = "virtio,mmio"; reg = <0x140000 0x200>; interrupts = <43>; }; - virtio-net@150000 { + virtio@150000 { compatible = "virtio,mmio"; reg = <0x150000 0x200>; interrupts = <44>; }; - virtio-rng@200000 { + virtio@200000 { compatible = "virtio,mmio"; reg = <0x200000 0x200>; interrupts = <46>; diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi index a999e7f52d8b..ba8beef3fe99 100644 --- a/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi +++ b/arch/arm64/boot/dts/arm/rtsm_ve-motherboard.dtsi @@ -222,7 +222,7 @@ clock-names = "timclken1", "timclken2", "apb_pclk"; }; - virtio-block@130000 { + virtio@130000 { compatible = "virtio,mmio"; reg = <0x130000 0x200>; interrupts = <42>; -- cgit v1.2.3 From 962c400d48e604438cfb3732016ad1b74bfc298c Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 5 Apr 2022 18:31:19 +0530 Subject: arm64: tegra: Add node for Tegra234 CCPLEX cluster Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses some of the CRAB (Control Register Access Bus) registers for CPU frequency requests. These registers are memory mapped to the CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB registers is required only for CPU frequency info. Signed-off-by: Sumit Gupta Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 448512af7dea..8767dbe2d066 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -1286,6 +1286,13 @@ }; }; + ccplex@e000000 { + compatible = "nvidia,tegra234-ccplex-cluster"; + reg = <0x0 0x0e000000 0x0 0x5ffff>; + nvidia,bpmp = <&bpmp>; + status = "okay"; + }; + sram@40000000 { compatible = "nvidia,tegra234-sysram", "mmio-sram"; reg = <0x0 0x40000000 0x0 0x80000>; -- cgit v1.2.3 From 6d9d19af3e34121a816757b4fae341a4d749e1a7 Mon Sep 17 00:00:00 2001 From: Jon Hunter Date: Wed, 6 Apr 2022 16:26:55 +0100 Subject: arm64: tegra: Update PWM fan node name According to the device-tree binding document for PWM fans [0], the PWM fan node name should be 'pwm-fan'. Update the PWM fan node name to align with this. [0] Documentation/devicetree/bindings/hwmon/pwm-fan.txt Signed-off-by: Jon Hunter Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 2 +- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index 4631504c3c7a..7e9aad9ff177 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -349,7 +349,7 @@ status = "okay"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 2478ece9e67c..27d28626bf5b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -1989,7 +1989,7 @@ "p2u-5", "p2u-6", "p2u-7"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm4 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 32ce7904f44f..8033be098f34 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -1993,7 +1993,7 @@ "p2u-5", "p2u-6", "p2u-7"; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm6 0 45334>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 72c2dc3c14ea..746bd52ea3f7 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1657,7 +1657,7 @@ }; }; - fan: fan { + fan: pwm-fan { compatible = "pwm-fan"; pwms = <&pwm 3 45334>; -- cgit v1.2.3 From 74a46891867bf18535250fa8771c10f0153856f3 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:02:55 +0200 Subject: arm64: dts: mediatek: mt8183: align Google CROS EC PWM node name with dtschema dtschema expects PWM node name to be a generic "pwm". This also matches Devicetree specification requirements about generic node names. Signed-off-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220214081916.162014-3-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 8f7bf33f607d..2d7a193272ae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -92,7 +92,7 @@ }; &cros_ec { - cros_ec_pwm: ec-pwm { + cros_ec_pwm: pwm { compatible = "google,cros-ec-pwm"; #pwm-cells = <1>; status = "disabled"; -- cgit v1.2.3 From 6f117db4123931d3fbde9cfaf360b02fe550c8d6 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:05:30 +0200 Subject: arm64: dts: mediatek: align operating-points table name with dtschema Align the name of operating-points node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: opp_table0: $nodename:0: 'opp_table0' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210820081616.83674-1-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++-- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi index 86579330a8bd..623eb3beabf2 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi @@ -19,7 +19,7 @@ #address-cells = <2>; #size-cells = <2>; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp00 { @@ -36,7 +36,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp00 { diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 042feaedda4a..785c98cf786b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -57,7 +57,7 @@ serial3 = &uart3; }; - cluster0_opp: opp_table0 { + cluster0_opp: opp-table-0 { compatible = "operating-points-v2"; opp-shared; opp-507000000 { @@ -94,7 +94,7 @@ }; }; - cluster1_opp: opp_table1 { + cluster1_opp: opp-table-1 { compatible = "operating-points-v2"; opp-shared; opp-507000000 { diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5d4a1dd55adc..05106d2a6b1d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -197,7 +197,7 @@ }; }; - gpu_opp_table: opp_table0 { + gpu_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; -- cgit v1.2.3 From 624f1806a7c3f8061641a1f3e7c0dfa73e82fb10 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 19 Apr 2022 12:05:20 +0200 Subject: arm64: dts: mediatek: align thermal zone node names with dtschema Align the name of thermal zone node to dtschema to fix warnings like: arch/arm64/boot/dts/mediatek/mt8173-elm.dt.yaml: thermal-zones: 'cpu_thermal' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20210820081616.83674-2-krzysztof.kozlowski@canonical.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 +- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 785c98cf786b..848e3f39c8ef 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -273,7 +273,7 @@ }; thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; /* milliseconds */ polling-delay = <1000>; /* milliseconds */ diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 05106d2a6b1d..d1448a0b86cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -823,7 +823,7 @@ }; thermal_zones: thermal-zones { - cpu_thermal: cpu_thermal { + cpu_thermal: cpu-thermal { polling-delay-passive = <100>; polling-delay = <500>; thermal-sensors = <&thermal 0>; -- cgit v1.2.3 From d3ee03d81615a889824eca49d24d5c51d0481bd1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:21:43 +0200 Subject: arm64: dts: mt8183-kukui: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407142143.293740-1-krzysztof.kozlowski@linaro.org Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 0f9480f91261..8d5bf73a9099 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -849,7 +849,7 @@ mediatek,pad-select = <0>; status = "okay"; - w25q64dw: spi-flash@0 { + w25q64dw: flash@0 { compatible = "winbond,w25q64dw", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <25000000>; -- cgit v1.2.3 From bf01df06ddb1452c7b4d7d2b4f51ecfad6cc5b71 Mon Sep 17 00:00:00 2001 From: Yong Wu Date: Thu, 21 Apr 2022 11:51:09 +0800 Subject: arm64: dts: mediatek: Get rid of mediatek, larb for MM nodes After adding device_link between the IOMMU consumer and smi, the mediatek,larb is unnecessary now. CC: Matthias Brugger Signed-off-by: Yong Wu Signed-off-by: Allen-KH Cheng Reviewed-by: Evan Green Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220421035111.7267-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 16 ---------------- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 6 ------ 2 files changed, 22 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 848e3f39c8ef..10291b2690ab 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1010,7 +1010,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,vpu = <&vpu>; }; @@ -1021,7 +1020,6 @@ <&mmsys CLK_MM_MUTEX_32K>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_RDMA1>; - mediatek,larb = <&larb4>; }; mdp_rsz0: rsz@14003000 { @@ -1051,7 +1049,6 @@ clocks = <&mmsys CLK_MM_MDP_WDMA>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WDMA>; - mediatek,larb = <&larb0>; }; mdp_wrot0: wrot@14007000 { @@ -1060,7 +1057,6 @@ clocks = <&mmsys CLK_MM_MDP_WROT0>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT0>; - mediatek,larb = <&larb0>; }; mdp_wrot1: wrot@14008000 { @@ -1069,7 +1065,6 @@ clocks = <&mmsys CLK_MM_MDP_WROT1>; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; iommus = <&iommu M4U_PORT_MDP_WROT1>; - mediatek,larb = <&larb4>; }; ovl0: ovl@1400c000 { @@ -1079,7 +1074,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1090,7 +1084,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_OVL1>; iommus = <&iommu M4U_PORT_DISP_OVL1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; }; @@ -1101,7 +1094,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; }; @@ -1112,7 +1104,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; }; @@ -1123,7 +1114,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_RDMA2>; iommus = <&iommu M4U_PORT_DISP_RDMA2>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; }; @@ -1134,7 +1124,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA0>; iommus = <&iommu M4U_PORT_DISP_WDMA0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; }; @@ -1145,7 +1134,6 @@ power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_WDMA1>; iommus = <&iommu M4U_PORT_DISP_WDMA1>; - mediatek,larb = <&larb4>; mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; }; @@ -1399,7 +1387,6 @@ <0 0x16027800 0 0x800>, /* VDEC_HWB */ <0 0x16028400 0 0x400>; /* VDEC_HWG */ interrupts = ; - mediatek,larb = <&larb1>; iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, <&iommu M4U_PORT_HW_VDEC_PP_EXT>, <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, @@ -1467,7 +1454,6 @@ compatible = "mediatek,mt8173-vcodec-enc"; reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ interrupts = ; - mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_VENC_RCPU>, <&iommu M4U_PORT_VENC_REC>, <&iommu M4U_PORT_VENC_BSDMA>, @@ -1495,7 +1481,6 @@ clock-names = "jpgdec-smi", "jpgdec"; power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; - mediatek,larb = <&larb3>; iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, <&iommu M4U_PORT_JPGDEC_BSDMA>; }; @@ -1529,7 +1514,6 @@ <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; - mediatek,larb = <&larb5>; mediatek,vpu = <&vpu>; clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; clock-names = "venc_lt_sel"; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index d1448a0b86cb..be9728526ed3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1396,7 +1396,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0>; iommus = <&iommu M4U_PORT_DISP_OVL0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; }; @@ -1407,7 +1406,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; }; @@ -1418,7 +1416,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; - mediatek,larb = <&larb0>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; }; @@ -1429,7 +1426,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA0>; iommus = <&iommu M4U_PORT_DISP_RDMA0>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <5120>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; }; @@ -1441,7 +1437,6 @@ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; clocks = <&mmsys CLK_MM_DISP_RDMA1>; iommus = <&iommu M4U_PORT_DISP_RDMA1>; - mediatek,larb = <&larb0>; mediatek,rdma-fifo-size = <2048>; mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; }; @@ -1598,7 +1593,6 @@ compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; reg = <0 0x17030000 0 0x1000>; interrupts = ; - mediatek,larb = <&larb4>; iommus = <&iommu M4U_PORT_JPGENC_RDMA>, <&iommu M4U_PORT_JPGENC_BSDMA>; power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; -- cgit v1.2.3 From dab2782be22c359dd1a14a118e9b1592a7f91db3 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 21 Apr 2022 11:51:10 +0800 Subject: arm64: dts: mediatek: mt8173: Add power domain to encoder nodes The power of encoder is not control by mediatek,larb, so we add power domain to encoder nodes for mt8173 SoC. Signed-off-by: Irui Wang Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220421035111.7267-4-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 10291b2690ab..eebc2d074254 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1470,6 +1470,7 @@ clock-names = "venc_sel"; assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC>; }; jpegdec: jpegdec@18004000 { @@ -1520,6 +1521,7 @@ assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; + power-domains = <&scpsys MT8173_POWER_DOMAIN_VENC_LT>; }; }; }; -- cgit v1.2.3 From 3b7d143be4b7cf09cf19b04e78669ce0c970cc76 Mon Sep 17 00:00:00 2001 From: Hui Liu Date: Thu, 21 Apr 2022 09:26:23 +0800 Subject: arm64: dts: mt6359: add PMIC MT6359 related nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT6359 is the primary PMIC for MT8192. Add PMIC MT6359 related node which is used for MT8192 platform. Signed-off-by: Hui Liu Reviewed-by: Nícolas F. R. A. Prado Tested-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220421012623.3446-2-hui.liu@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 298 ++++++++++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8192-evb.dts | 1 + 2 files changed, 299 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt6359.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi new file mode 100644 index 000000000000..df3e822232d3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ + +&pwrap { + pmic: pmic { + compatible = "mediatek,mt6359"; + interrupt-controller; + #interrupt-cells = <2>; + + mt6359codec: mt6359codec { + }; + + regulators { + mt6359_vs1_buck_reg: buck_vs1 { + regulator-name = "vs1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <2200000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vgpu11_buck_reg: buck_vgpu11 { + regulator-name = "vgpu11"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vmodem_buck_reg: buck_vmodem { + regulator-name = "vmodem"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1100000>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <200>; + }; + mt6359_vpu_buck_reg: buck_vpu { + regulator-name = "vpu"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_buck_reg: buck_vcore { + regulator-name = "vcore"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1300000>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vs2_buck_reg: buck_vs2 { + regulator-name = "vs2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1600000>; + regulator-enable-ramp-delay = <0>; + regulator-always-on; + }; + mt6359_vpa_buck_reg: buck_vpa { + regulator-name = "vpa"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3650000>; + regulator-enable-ramp-delay = <300>; + }; + mt6359_vproc2_buck_reg: buck_vproc2 { + regulator-name = "vproc2"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vproc1_buck_reg: buck_vproc1 { + regulator-name = "vproc1"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <200>; + regulator-allowed-modes = <0 1 2>; + }; + mt6359_vcore_sshub_buck_reg: buck_vcore_sshub { + regulator-name = "vcore_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vgpu11_sshub_buck_reg: buck_vgpu11_sshub { + regulator-name = "vgpu11_sshub"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1193750>; + }; + mt6359_vaud18_ldo_reg: ldo_vaud18 { + regulator-name = "vaud18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vsim1_ldo_reg: ldo_vsim1 { + regulator-name = "vsim1"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vibr_ldo_reg: ldo_vibr { + regulator-name = "vibr"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vrf12_ldo_reg: ldo_vrf12 { + regulator-name = "vrf12"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vusb_ldo_reg: ldo_vusb { + regulator-name = "vusb"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vsram_proc2_ldo_reg: ldo_vsram_proc2 { + regulator-name = "vsram_proc2"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vio18_ldo_reg: ldo_vio18 { + regulator-name = "vio18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-enable-ramp-delay = <960>; + regulator-always-on; + }; + mt6359_vcamio_ldo_reg: ldo_vcamio { + regulator-name = "vcamio"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vcn18_ldo_reg: ldo_vcn18 { + regulator-name = "vcn18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vfe28_ldo_reg: ldo_vfe28 { + regulator-name = "vfe28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <120>; + }; + mt6359_vcn13_ldo_reg: ldo_vcn13 { + regulator-name = "vcn13"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1300000>; + }; + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { + regulator-name = "vcn33_1_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { + regulator-name = "vcn33_1_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vaux18_ldo_reg: ldo_vaux18 { + regulator-name = "vaux18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsram_others_ldo_reg: ldo_vsram_others { + regulator-name = "vsram_others"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <5000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vefuse_ldo_reg: ldo_vefuse { + regulator-name = "vefuse"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <2000000>; + }; + mt6359_vxo22_ldo_reg: ldo_vxo22 { + regulator-name = "vxo22"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + regulator-always-on; + }; + mt6359_vrfck_ldo_reg: ldo_vrfck { + regulator-name = "vrfck"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1700000>; + }; + mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { + regulator-name = "vrfck"; + regulator-min-microvolt = <1240000>; + regulator-max-microvolt = <1600000>; + }; + mt6359_vbif28_ldo_reg: ldo_vbif28 { + regulator-name = "vbif28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vio28_ldo_reg: ldo_vio28 { + regulator-name = "vio28"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + mt6359_vemc_ldo_reg: ldo_vemc { + regulator-name = "vemc"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vemc_1_ldo_reg: ldo_vemc_1 { + regulator-name = "vemc"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3300000>; + }; + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { + regulator-name = "vcn33_2_bt"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { + regulator-name = "vcn33_2_wifi"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3500000>; + }; + mt6359_va12_ldo_reg: ldo_va12 { + regulator-name = "va12"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + mt6359_va09_ldo_reg: ldo_va09 { + regulator-name = "va09"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vrf18_ldo_reg: ldo_vrf18 { + regulator-name = "vrf18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1810000>; + }; + mt6359_vsram_md_ldo_reg: ldo_vsram_md { + regulator-name = "vsram_md"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <10760>; + regulator-enable-ramp-delay = <240>; + }; + mt6359_vufs_ldo_reg: ldo_vufs { + regulator-name = "vufs"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + mt6359_vm18_ldo_reg: ldo_vm18 { + regulator-name = "vm18"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-always-on; + }; + mt6359_vbbck_ldo_reg: ldo_vbbck { + regulator-name = "vbbck"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1200000>; + }; + mt6359_vsram_proc1_ldo_reg: ldo_vsram_proc1 { + regulator-name = "vsram_proc1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + regulator-ramp-delay = <7500>; + regulator-enable-ramp-delay = <240>; + regulator-always-on; + }; + mt6359_vsim2_ldo_reg: ldo_vsim2 { + regulator-name = "vsim2"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3100000>; + }; + mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { + regulator-name = "vsram_others_sshub"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1293750>; + }; + }; + + mt6359rtc: mt6359rtc { + compatible = "mediatek,mt6358-rtc"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts index 0205837fa698..808be492e970 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-evb.dts @@ -5,6 +5,7 @@ */ /dts-v1/; #include "mt8192.dtsi" +#include "mt6359.dtsi" / { model = "MediaTek MT8192 evaluation board"; -- cgit v1.2.3 From a8bbcf703cf3c5cb63dd8516abc87262ad86b635 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 14:32:26 +0800 Subject: arm64: dts: mt8192: Add spmi node Add spmi node for mt8192 SoC. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419063226.15958-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index a6da7b04b9d4..164fae36a3d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -537,6 +537,21 @@ assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; }; + spmi: spmi@10027000 { + compatible = "mediatek,mt6873-spmi"; + reg = <0 0x10027000 0 0x000e00>, + <0 0x10029000 0 0x000100>; + reg-names = "pmif", "spmimst"; + clocks = <&infracfg CLK_INFRA_PMIC_AP>, + <&infracfg CLK_INFRA_PMIC_TMR>, + <&topckgen CLK_TOP_SPMI_MST_SEL>; + clock-names = "pmif_sys_ck", + "pmif_tmr_ck", + "spmimst_clk_mux"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>; + }; + scp_adsp: clock-controller@10720000 { compatible = "mediatek,mt8192-scp_adsp"; reg = <0 0x10720000 0 0x1000>; -- cgit v1.2.3 From 1afd9b62f95f51d68d38a006100a392b7761c53f Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Tue, 19 Apr 2022 10:55:57 +0800 Subject: arm64: dts: mt8192: Add audio-related nodes Add audio-related nodes in audsys for mt8192 SoC. - Move audsys node in ascending order. - Increase the address range's length from 0x1000 to 0x2000. Signed-off-by: Allen-KH Cheng Link: https://lore.kernel.org/r/20220419025557.22262-3-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 135 +++++++++++++++++++++++++++++-- 1 file changed, 129 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 164fae36a3d8..9a8310f907b3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -731,6 +731,135 @@ status = "disabled"; }; + audsys: syscon@11210000 { + compatible = "mediatek,mt8192-audsys", "syscon"; + reg = <0 0x11210000 0 0x2000>; + #clock-cells = <1>; + + afe: mt8192-afe-pcm { + compatible = "mediatek,mt8192-audio"; + interrupts = ; + resets = <&watchdog 17>; + reset-names = "audiosys"; + mediatek,apmixedsys = <&apmixedsys>; + mediatek,infracfg = <&infracfg>; + mediatek,topckgen = <&topckgen>; + power-domains = <&spm MT8192_POWER_DOMAIN_AUDIO>; + clocks = <&audsys CLK_AUD_AFE>, + <&audsys CLK_AUD_DAC>, + <&audsys CLK_AUD_DAC_PREDIS>, + <&audsys CLK_AUD_ADC>, + <&audsys CLK_AUD_ADDA6_ADC>, + <&audsys CLK_AUD_22M>, + <&audsys CLK_AUD_24M>, + <&audsys CLK_AUD_APLL_TUNER>, + <&audsys CLK_AUD_APLL2_TUNER>, + <&audsys CLK_AUD_TDM>, + <&audsys CLK_AUD_TML>, + <&audsys CLK_AUD_NLE>, + <&audsys CLK_AUD_DAC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES>, + <&audsys CLK_AUD_ADC_HIRES_TML>, + <&audsys CLK_AUD_ADDA6_ADC_HIRES>, + <&audsys CLK_AUD_3RD_DAC>, + <&audsys CLK_AUD_3RD_DAC_PREDIS>, + <&audsys CLK_AUD_3RD_DAC_TML>, + <&audsys CLK_AUD_3RD_DAC_HIRES>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_B>, + <&topckgen CLK_TOP_AUDIO_SEL>, + <&topckgen CLK_TOP_AUD_INTBUS_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4_D4>, + <&topckgen CLK_TOP_AUD_1_SEL>, + <&topckgen CLK_TOP_APLL1>, + <&topckgen CLK_TOP_AUD_2_SEL>, + <&topckgen CLK_TOP_APLL2>, + <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, + <&topckgen CLK_TOP_APLL1_D4>, + <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, + <&topckgen CLK_TOP_APLL2_D4>, + <&topckgen CLK_TOP_APLL_I2S0_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S1_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S2_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S3_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S4_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S5_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S6_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S7_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S8_M_SEL>, + <&topckgen CLK_TOP_APLL_I2S9_M_SEL>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&topckgen CLK_TOP_APLL12_DIV5>, + <&topckgen CLK_TOP_APLL12_DIV6>, + <&topckgen CLK_TOP_APLL12_DIV7>, + <&topckgen CLK_TOP_APLL12_DIV8>, + <&topckgen CLK_TOP_APLL12_DIV9>, + <&topckgen CLK_TOP_AUDIO_H_SEL>, + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adda6_adc_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_tdm_clk", + "aud_tml_clk", + "aud_nle", + "aud_dac_hires_clk", + "aud_adc_hires_clk", + "aud_adc_hires_tml", + "aud_adda6_adc_hires_clk", + "aud_3rd_dac_clk", + "aud_3rd_dac_predis_clk", + "aud_3rd_dac_tml", + "aud_3rd_dac_hires_clk", + "aud_infra_clk", + "aud_infra_26m_clk", + "top_mux_audio", + "top_mux_audio_int", + "top_mainpll_d4_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d4", + "top_mux_aud_eng2", + "top_apll2_d4", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_i2s6_m_sel", + "top_i2s7_m_sel", + "top_i2s8_m_sel", + "top_i2s9_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_apll12_div5", + "top_apll12_div6", + "top_apll12_div7", + "top_apll12_div8", + "top_apll12_div9", + "top_mux_audio_h", + "top_clk26m_clk"; + }; + }; + pcie: pcie@11230000 { compatible = "mediatek,mt8192-pcie"; device_type = "pci"; @@ -781,12 +910,6 @@ status = "disabled"; }; - audsys: clock-controller@11210000 { - compatible = "mediatek,mt8192-audsys", "syscon"; - reg = <0 0x11210000 0 0x1000>; - #clock-cells = <1>; - }; - efuse: efuse@11c10000 { compatible = "mediatek,efuse"; reg = <0 0x11c10000 0 0x1000>; -- cgit v1.2.3 From 71b946e9505510bdf2f84241205635c2f2da3e66 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 11 Apr 2022 11:58:42 +0800 Subject: arm64: dts: mt8183: Update disp_aal node compatible The driver data of MT8183 and MT8173 are different. The value of has_gamma for MT8173 is true while the value of MT8183 is false. Therefore, the compatible of disp_aal for MT8183 is not suitable for the compatible for MT8173. Signed-off-by: Rex-BC Chen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220411035843.19847-3-rex-bc.chen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index be9728526ed3..01e650251928 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1461,8 +1461,7 @@ }; aal0: aal@14010000 { - compatible = "mediatek,mt8183-disp-aal", - "mediatek,mt8173-disp-aal"; + compatible = "mediatek,mt8183-disp-aal"; reg = <0 0x14010000 0 0x1000>; interrupts = ; power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; -- cgit v1.2.3 From db61337e49a8324d3e7cae3450db22cf2bf87369 Mon Sep 17 00:00:00 2001 From: Allen-KH Cheng Date: Thu, 7 Apr 2022 19:37:03 +0800 Subject: arm64: dts: mt8192: Add mmc device nodes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In mt8192 SoC, mmc driver dose not use the MSDC module to control clock. It will read/write register to enable/disable clock. Also there is no other device of mt8192 using MSDC controller. We add mmc nodes for mt8192 SoC and remove the clock-controller in dts for avoid a duplicate unit-address(11f60000) warning. Signed-off-by: Allen-KH Cheng Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/r/20220407113703.26423-2-allen-kh.cheng@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 34 ++++++++++++++++++++++++++++---- 1 file changed, 30 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 9a8310f907b3..26dbe9ecc528 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -1123,10 +1123,36 @@ #clock-cells = <1>; }; - msdc: clock-controller@11f60000 { - compatible = "mediatek,mt8192-msdc"; - reg = <0 0x11f60000 0 0x1000>; - #clock-cells = <1>; + mmc0: mmc@11f60000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f60000 0 0x1000>, <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_0P>, + <&msdc_top CLK_MSDC_TOP_SRC_0P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC0>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; + }; + + mmc1: mmc@11f70000 { + compatible = "mediatek,mt8192-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11f70000 0 0x1000>, <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&msdc_top CLK_MSDC_TOP_H_MST_1P>, + <&msdc_top CLK_MSDC_TOP_SRC_1P>, + <&msdc_top CLK_MSDC_TOP_P_CFG>, + <&msdc_top CLK_MSDC_TOP_P_MSDC1>, + <&msdc_top CLK_MSDC_TOP_AXI>, + <&msdc_top CLK_MSDC_TOP_AHB2AXI_BRG_AXI>; + clock-names = "source", "hclk", "source_cg", "sys_cg", + "pclk_cg", "axi_cg", "ahb_cg"; + status = "disabled"; }; mfgcfg: clock-controller@13fbf000 { -- cgit v1.2.3 From 37f2582883be7218dc69f9af135959a8e93de223 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Mon, 11 Apr 2022 10:27:24 +0800 Subject: arm64: dts: Add mediatek SoC mt8195 and evaluation board Add basic chip support for mediatek mt8195. Signed-off-by: Seiya Wang Signed-off-by: Tinghan Shen Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220411022724.11005-3-tinghan.shen@mediatek.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 181 +++++ arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++++++++++ 3 files changed, 1227 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 8c1e18032f9f..5da29e7223e4 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts new file mode 100644 index 000000000000..db25a515e420 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -0,0 +1,181 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Seiya Wang + */ +/dts-v1/; +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 evaluation board"; + compatible = "mediatek,mt8195-evb", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; +}; + +&auxadc { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pin>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pin>; + clock-frequency = <400000>; + status = "okay"; +}; + +&nor_flash { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&pio { + i2c0_pin: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c1_pin: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <0>; + drive-strength = <6>; + }; + }; + + i2c4_pin: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + mediatek,drive-strength-adv = <7>; + }; + }; + + i2c6_pin: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; + }; + + i2c7_pin: i2c7-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + }; + }; + + nor_pins_default: nor-pins { + pins0 { + pinmux = , + , + ; + bias-pull-down; + }; + + pins1 { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + uart0_pin: uart0-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&u3phy0 { + status="okay"; +}; + +&u3phy1 { + status="okay"; +}; + +&u3phy2 { + status="okay"; +}; + +&u3phy3 { + status="okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pin>; + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci1 { + status = "okay"; +}; + +&xhci2 { + status = "okay"; +}; + +&xhci3 { + /* This controller is connected with a BT device. + * Disable usb2 lpm to prevent known issues. + */ + usb2-lpm-disable; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi new file mode 100644 index 000000000000..b57e620c2c72 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -0,0 +1,1045 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Seiya Wang + */ + +/dts-v1/; +#include +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x000>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x100>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x200>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a55"; + reg = <0x300>; + enable-method = "psci"; + clock-frequency = <1701000000>; + capacity-dmips-mhz = <578>; + cpu-idle-states = <&cpu_off_l &cluster_off_l>; + next-level-cache = <&l2_0>; + #cooling-cells = <2>; + }; + + cpu4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x400>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x500>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x600>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-a78"; + reg = <0x700>; + enable-method = "psci"; + clock-frequency = <2171000000>; + capacity-dmips-mhz = <1024>; + cpu-idle-states = <&cpu_off_b &cluster_off_b>; + next-level-cache = <&l2_1>; + #cooling-cells = <2>; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + + core1 { + cpu = <&cpu5>; + }; + + core2 { + cpu = <&cpu6>; + }; + + core3 { + cpu = <&cpu7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + cpu_off_l: cpu-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <95>; + min-residency-us = <580>; + }; + + cpu_off_b: cpu-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x00010001>; + local-timer-stop; + entry-latency-us = <45>; + exit-latency-us = <140>; + min-residency-us = <740>; + }; + + cluster_off_l: cluster-off-l { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <55>; + exit-latency-us = <155>; + min-residency-us = <840>; + }; + + cluster_off_b: cluster-off-b { + compatible = "arm,idle-state"; + arm,psci-suspend-param = <0x01010002>; + local-timer-stop; + entry-latency-us = <50>; + exit-latency-us = <200>; + min-residency-us = <1000>; + }; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + next-level-cache = <&l3_0>; + }; + + l3_0: l3-cache { + compatible = "cache"; + }; + }; + + dsu-pmu { + compatible = "arm,dsu-pmu"; + interrupts = ; + cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, + <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; + }; + + clk26m: oscillator-26m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + clk32k: oscillator-32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "clk32k"; + }; + + pmu-a55 { + compatible = "arm,cortex-a55-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + pmu-a78 { + compatible = "arm,cortex-a78-pmu"; + interrupt-parent = <&gic>; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer: timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + #redistributor-regions = <1>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, + <0 0x0c040000 0 0x200000>; + interrupts = ; + + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg_ao: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + + infracfg_rst: reset-controller { + compatible = "ti,syscon-reset"; + #reset-cells = <1>; + ti,reset-bits = < + 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ + 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ + 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ + 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ + >; + }; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8195-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@10005000 { + compatible = "mediatek,mt8195-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11d30000 0 0x1000>, + <0 0x11d40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11eb0000 0 0x1000>, + <0 0x11f40000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", + "iocfg_br", "iocfg_lm", "iocfg_rb", + "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 144>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + systimer: timer@10017000 { + compatible = "mediatek,mt8195-timer", + "mediatek,mt6765-timer"; + reg = <0 0x10017000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_CLK26M_D2>; + }; + + pwrap: pwrap@10024000 { + compatible = "mediatek,mt8195-pwrap", "syscon"; + reg = <0 0x10024000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, + <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; + clock-names = "spi", "wrap"; + assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; + assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; + }; + + scp_adsp: clock-controller@10720000 { + compatible = "mediatek,mt8195-scp_adsp"; + reg = <0 0x10720000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001100 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart1: serial@11001200 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001200 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart2: serial@11001300 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001300 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart3: serial@11001400 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001400 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart4: serial@11001500 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001500 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + uart5: serial@11001600 { + compatible = "mediatek,mt8195-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11001600 0 0x100>; + interrupts = ; + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + auxadc: auxadc@11002000 { + compatible = "mediatek,mt8195-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11002000 0 0x1000>; + clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + pericfg_ao: syscon@11003000 { + compatible = "mediatek,mt8195-pericfg_ao", "syscon"; + reg = <0 0x11003000 0 0x1000>; + #clock-cells = <1>; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x1100a000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi1: spi@11010000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11010000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI1>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi2: spi@11012000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11012000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI2>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi3: spi@11013000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11013000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI3>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi4: spi@11018000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11018000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI4>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spi5: spi@11019000 { + compatible = "mediatek,mt8195-spi", + "mediatek,mt6765-spi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x11019000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, + <&topckgen CLK_TOP_SPI>, + <&infracfg_ao CLK_INFRA_AO_SPI5>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + spis0: spi@1101d000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101d000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + spis1: spi@1101e000 { + compatible = "mediatek,mt8195-spi-slave"; + reg = <0 0x1101e000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; + clock-names = "spi"; + assigned-clocks = <&topckgen CLK_TOP_SPIS>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; + status = "disabled"; + }; + + xhci0: usb@11200000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, + <&topckgen CLK_TOP_SSUSB_XHCI>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, + <&topckgen CLK_TOP_SSUSB_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x10000>, + <0 0x11f50000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0>, + <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c70000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1>, + <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + mmc2: mmc@11250000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11250000 0 0x1000>, + <0 0x11e60000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_2>, + <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, + <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; + clock-names = "source", "hclk", "source_cg"; + assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; + assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; + status = "disabled"; + }; + + xhci1: usb@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port1 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, + <&topckgen CLK_TOP_SSUSB_XHCI_1P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, + <&topckgen CLK_TOP_SSUSB_P1_REF>, + <&apmixedsys CLK_APMIXED_USB1PLL>, + <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck"; + status = "disabled"; + }; + + xhci2: usb@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port2 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>, + <&topckgen CLK_TOP_SSUSB_XHCI_2P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, + <&topckgen CLK_TOP_SSUSB_P2_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; + status = "disabled"; + }; + + xhci3: usb@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port3 PHY_TYPE_USB2>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>, + <&topckgen CLK_TOP_SSUSB_XHCI_3P>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, + <&topckgen CLK_TOP_SSUSB_P3_REF>, + <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; + clock-names = "sys_ck", "ref_ck", "xhci_ck"; + status = "disabled"; + }; + + nor_flash: spi@1132c000 { + compatible = "mediatek,mt8195-nor", + "mediatek,mt8173-nor"; + reg = <0 0x1132c000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SPINOR>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, + <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; + clock-names = "spi", "sf", "axi"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + u3phy2: t-phy@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + u3phy3: t-phy@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "disabled"; + + u2port3: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + i2c5: i2c@11d00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x10220580 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@11d01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d01000 0 0x1000>, + <0 0x10220600 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@11d02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11d02000 0 0x1000>, + <0 0x10220680 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_s: clock-controller@11d03000 { + compatible = "mediatek,mt8195-imp_iic_wrap_s"; + reg = <0 0x11d03000 0 0x1000>; + #clock-cells = <1>; + }; + + i2c0: i2c@11e00000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e00000 0 0x1000>, + <0 0x10220080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + }; + + i2c1: i2c@11e01000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e01000 0 0x1000>, + <0 0x10220200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11e02000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e02000 0 0x1000>, + <0 0x10220380 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@11e03000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e03000 0 0x1000>, + <0 0x10220480 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@11e04000 { + compatible = "mediatek,mt8195-i2c", + "mediatek,mt8192-i2c"; + reg = <0 0x11e04000 0 0x1000>, + <0 0x10220500 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, + <&infracfg_ao CLK_INFRA_AO_APDMA_B>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + imp_iic_wrap_w: clock-controller@11e05000 { + compatible = "mediatek,mt8195-imp_iic_wrap_w"; + reg = <0 0x11e05000 0 0x1000>; + #clock-cells = <1>; + }; + + u3phy1: t-phy@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + u3phy0: t-phy@11e40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, + <&clk26m>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, + <&topckgen CLK_TOP_SSUSB_PHY_REF>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + ufsphy: ufs-phy@11fa0000 { + compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; + reg = <0 0x11fa0000 0 0xc000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "unipro", "mp"; + #phy-cells = <0>; + status = "disabled"; + }; + + mfgcfg: clock-controller@13fbf000 { + compatible = "mediatek,mt8195-mfgcfg"; + reg = <0 0x13fbf000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys: clock-controller@14e00000 { + compatible = "mediatek,mt8195-wpesys"; + reg = <0 0x14e00000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp0: clock-controller@14e02000 { + compatible = "mediatek,mt8195-wpesys_vpp0"; + reg = <0 0x14e02000 0 0x1000>; + #clock-cells = <1>; + }; + + wpesys_vpp1: clock-controller@14e03000 { + compatible = "mediatek,mt8195-wpesys_vpp1"; + reg = <0 0x14e03000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys: clock-controller@15000000 { + compatible = "mediatek,mt8195-imgsys"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_top: clock-controller@15110000 { + compatible = "mediatek,mt8195-imgsys1_dip_top"; + reg = <0 0x15110000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_dip_nr: clock-controller@15130000 { + compatible = "mediatek,mt8195-imgsys1_dip_nr"; + reg = <0 0x15130000 0 0x1000>; + #clock-cells = <1>; + }; + + imgsys1_wpe: clock-controller@15220000 { + compatible = "mediatek,mt8195-imgsys1_wpe"; + reg = <0 0x15220000 0 0x1000>; + #clock-cells = <1>; + }; + + ipesys: clock-controller@15330000 { + compatible = "mediatek,mt8195-ipesys"; + reg = <0 0x15330000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: clock-controller@16000000 { + compatible = "mediatek,mt8195-camsys"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawa: clock-controller@1604f000 { + compatible = "mediatek,mt8195-camsys_rawa"; + reg = <0 0x1604f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuva: clock-controller@1606f000 { + compatible = "mediatek,mt8195-camsys_yuva"; + reg = <0 0x1606f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_rawb: clock-controller@1608f000 { + compatible = "mediatek,mt8195-camsys_rawb"; + reg = <0 0x1608f000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_yuvb: clock-controller@160af000 { + compatible = "mediatek,mt8195-camsys_yuvb"; + reg = <0 0x160af000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys_mraw: clock-controller@16140000 { + compatible = "mediatek,mt8195-camsys_mraw"; + reg = <0 0x16140000 0 0x1000>; + #clock-cells = <1>; + }; + + ccusys: clock-controller@17200000 { + compatible = "mediatek,mt8195-ccusys"; + reg = <0 0x17200000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_soc: clock-controller@1800f000 { + compatible = "mediatek,mt8195-vdecsys_soc"; + reg = <0 0x1800f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: clock-controller@1802f000 { + compatible = "mediatek,mt8195-vdecsys"; + reg = <0 0x1802f000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys_core1: clock-controller@1803f000 { + compatible = "mediatek,mt8195-vdecsys_core1"; + reg = <0 0x1803f000 0 0x1000>; + #clock-cells = <1>; + }; + + apusys_pll: clock-controller@190f3000 { + compatible = "mediatek,mt8195-apusys_pll"; + reg = <0 0x190f3000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: clock-controller@1a000000 { + compatible = "mediatek,mt8195-vencsys"; + reg = <0 0x1a000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys_core1: clock-controller@1b000000 { + compatible = "mediatek,mt8195-vencsys_core1"; + reg = <0 0x1b000000 0 0x1000>; + #clock-cells = <1>; + }; + }; +}; -- cgit v1.2.3 From 6147314aeedc24ecf70ea5656884b03cba836782 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Fri, 15 Apr 2022 17:00:01 +0200 Subject: arm64: dts: mediatek: Add device-tree for MT8195 Demo board Add basic device-tree for the MT8195 Demo board. The Demo board is made by MediaTek and has a MT8195 SoC, associated with the MT6359 and MT6360 PMICs, and the MT7921 connectivity chip. The IOs available on that board are: * 1 USB Type-C connector with DP aux mode support * 1 USB Type-A connector * 1 full size HDMI RX and 1 full size HDMI TX connector * 1 uSD slot * 40 pins header * SPI interface header * 1 M.2 slot * 1 audio jack * 1 micro-USB port for serial debug * 2 connectors for DSI displays * 3 connectors for CSI cameras * 1 connector for a eDP panel * 1 MMC storage This commit adds basic support in order to be able to boot. Signed-off-by: Fabien Parent Tested-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220415150003.1793063-3-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 445 +++++++++++++++++++++++++++ 2 files changed, 446 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-demo.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5da29e7223e4..c7d4636a2cb7 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -38,5 +38,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts new file mode 100644 index 000000000000..def3fc26cb99 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 BayLibre, SAS. + * Author: Fabien Parent + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include +#include +#include +#include + +/ { + model = "MediaTek MT8195 demo board"; + compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x30000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + + charger { + compatible = "mediatek,mt6360-chg"; + richtek,vinovp-microvolt = <14500000>; + + otg_vbus_regulator: usb-otg-vbus-regulator { + regulator-compatible = "usb-otg-vbus"; + regulator-name = "usb-otg-vbus"; + regulator-min-microvolt = <4425000>; + regulator-max-microvolt = <5825000>; + }; + }; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN3-supply = <&mt6360_buck2>; + + mt6360_buck1: buck1 { + regulator-compatible = "BUCK1"; + regulator-name = "mt6360,buck1"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: buck2 { + regulator-compatible = "BUCK2"; + regulator-name = "mt6360,buck2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: ldo1 { + regulator-compatible = "LDO1"; + regulator-name = "mt6360,ldo1"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo2: ldo2 { + regulator-compatible = "LDO2"; + regulator-name = "mt6360,ldo2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: ldo3 { + regulator-compatible = "LDO3"; + regulator-name = "mt6360,ldo3"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: ldo5 { + regulator-compatible = "LDO5"; + regulator-name = "mt6360,ldo5"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo6: ldo6 { + regulator-compatible = "LDO6"; + regulator-name = "mt6360,ldo6"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: ldo7 { + regulator-compatible = "LDO7"; + regulator-name = "mt6360,ldo7"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x14c11>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&pio { + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; +}; + + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&u3phy3 { + status = "okay"; +}; + +&xhci0 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&otg_vbus_regulator>; + status = "okay"; +}; + +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&xhci3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; -- cgit v1.2.3 From caaff77ffb3f186c2f2df61fa91fb409ea2d929b Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 28 Feb 2022 12:03:29 +0100 Subject: arm64: dts: mediatek: mt8173: Add gce-client-reg handle to disp-mutex Add a gce client reg handle to the disp mutex to enable MT8173 platforms to use MediaTek's CMDQ for extra performance. Signed-off-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20220228110329.245366-1-angelogioacchino.delregno@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index eebc2d074254..40d7b47fc52e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1278,6 +1278,7 @@ interrupts = ; power-domains = <&spm MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_MUTEX_32K>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; mediatek,gce-events = , ; }; -- cgit v1.2.3 From 402eb8ec54b36f8fc0649768c01abb57062d6f8b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:23 +0200 Subject: arm64: dts: microchip: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20220407143223.295344-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/microchip/sparx5_nand.dtsi | 2 +- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 4 ++-- arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi | 4 ++-- arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi | 4 ++-- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi index 03f107e427d7..ce0747fd6444 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_nand.dtsi @@ -19,7 +19,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <14>; /* CS14 */ - spi-flash@6 { + flash@6 { compatible = "spi-nand"; pinctrl-0 = <&cs14_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 9baa085d7861..dbf8c1d48a02 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -47,7 +47,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ @@ -59,7 +59,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <1>; /* CS1 */ - spi-flash@9 { + flash@9 { compatible = "spi-nand"; pinctrl-0 = <&cs1_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 33faf1f3264f..699256f1b9d8 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -274,7 +274,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -289,7 +289,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index ef96e6d8c6b3..d10a9172b529 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -89,7 +89,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0>; @@ -104,7 +104,7 @@ #address-cells = <1>; #size-cells = <0>; reg = <0>; /* CS0 */ - spi-flash@9 { + flash@9 { compatible = "jedec,spi-nor"; spi-max-frequency = <8000000>; reg = <0x9>; /* SPI */ -- cgit v1.2.3 From 2f00bb4a69c770b7957b9b4621323c2f84fc6538 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Apr 2022 16:32:34 +0200 Subject: arm64: dts: marvell: align SPI NOR node name with dtschema The node names should be generic and SPI NOR dtschema expects "flash". Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220407143234.295426-2-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/marvell/armada-3720-db.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts | 2 +- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 2 +- arch/arm64/boot/dts/marvell/armada-7040-db.dts | 4 ++-- arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts | 2 +- arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts | 2 +- arch/arm64/boot/dts/marvell/armada-8040-db.dts | 4 ++-- arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts | 2 +- arch/arm64/boot/dts/marvell/cn9130-crb.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9130-db.dtsi | 2 +- arch/arm64/boot/dts/marvell/cn9131-db.dtsi | 2 +- 12 files changed, 14 insertions(+), 14 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index 3e5789f37206..bd4e61d5448e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -164,7 +164,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <108000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index 1cee26479bfe..d665f742a7d5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -211,7 +211,7 @@ assigned-clock-parents = <&tbg 1>; assigned-clock-rates = <20000000>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index 95d46e8d081c..a4de8d00cf46 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts index cd326fe224ce..5e5baf6beea4 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts @@ -83,7 +83,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -186,7 +186,7 @@ &cp0_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts index f3b0d57a24a3..39a8e5e99d79 100644 --- a/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts +++ b/arch/arm64/boot/dts/marvell/armada-7040-mochabin.dts @@ -155,7 +155,7 @@ pinctrl-names = "default"; pinctrl-0 = <&cp0_spi1_pins>; - spi-flash@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts index 8729c6467303..871f84b4a6ed 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts @@ -589,7 +589,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts index f2e8e0df8865..92897bd7e6cf 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts @@ -72,7 +72,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <10000000>; @@ -238,7 +238,7 @@ &cp1_spi1 { status = "okay"; - spi-flash@0 { + flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; spi-max-frequency = <20000000>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index adbfecc678b5..779cf167c33e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -360,7 +360,7 @@ pinctrl-0 = <&cp1_spi1_pins>; status = "okay"; - spi-flash@0 { + flash@0 { compatible = "st,w25q32"; spi-max-frequency = <50000000>; reg = <0>; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts index dac85fa748de..74bed79e4f5e 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-puzzle-m801.dts @@ -185,7 +185,7 @@ &spi0 { status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi index d9f9f2c19740..1acd746284dc 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-crb.dtsi @@ -175,7 +175,7 @@ <0x2000000 0x1000000>; /* CS0 */ status = "okay"; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi index c00b69b88bd2..7e20987253a3 100644 --- a/arch/arm64/boot/dts/marvell/cn9130-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9130-db.dtsi @@ -310,7 +310,7 @@ pinctrl-0 = <&cp0_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi index f995b1bcda01..b7fc241a228c 100644 --- a/arch/arm64/boot/dts/marvell/cn9131-db.dtsi +++ b/arch/arm64/boot/dts/marvell/cn9131-db.dtsi @@ -137,7 +137,7 @@ pinctrl-0 = <&cp1_spi0_pins>; reg = <0x700680 0x50>; - spi-flash@0 { + flash@0 { #address-cells = <0x1>; #size-cells = <0x1>; compatible = "jedec,spi-nor"; -- cgit v1.2.3 From 47a08153f32dc7d38953c84e3f2c07059411ce66 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 31 Mar 2022 19:33:31 +0530 Subject: arm64: tegra: Add ASRC device on Tegra186 and later Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is present on Tegra186 and later generations of Tegra SoC. Add this device on the relevant SoC DTSI files. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 7 +++++++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 8 ++++++++ arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++ 3 files changed, 23 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index e9b40f5d79ec..2e7faa1e0b9c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -516,6 +516,13 @@ sound-name-prefix = "MIXER1"; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 1d6be5774fac..f9d343b24597 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -569,6 +569,14 @@ sound-name-prefix = "MIXER1"; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra194-asrc", + "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 8767dbe2d066..71c21d7d0551 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -378,6 +378,14 @@ iommus = <&smmu_niso0 TEGRA234_SID_APE>; status = "disabled"; }; + + tegra_asrc: asrc@2910000 { + compatible = "nvidia,tegra234-asrc", + "nvidia,tegra186-asrc"; + reg = <0x2910000 0x2000>; + sound-name-prefix = "ASRC1"; + status = "disabled"; + }; }; adma: dma-controller@2930000 { -- cgit v1.2.3 From 261a46a977c6babde207d5e979fe5cf779b067b9 Mon Sep 17 00:00:00 2001 From: Sameer Pujar Date: Thu, 31 Mar 2022 19:33:32 +0530 Subject: arm64: tegra: Enable ASRC on various platforms Enable ASRC module usage on various Jetson Platforms. This can be plugged into an audio path using ALSA mixer controls. Signed-off-by: Sameer Pujar Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 223 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 223 +++++++++++++++++++++ .../arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi | 223 +++++++++++++++++++++ .../dts/nvidia/tegra234-p3737-0000+p3701-0000.dts | 223 +++++++++++++++++++++ 4 files changed, 892 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts index c4dee05f330c..70737a09a9b8 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts @@ -811,6 +811,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1935,6 +2039,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2331,6 +2548,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2348,6 +2569,8 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* I/O */ <&i2s1_port>, <&i2s2_port>, <&i2s3_port>, <&i2s4_port>, <&i2s5_port>, <&i2s6_port>, <&dmic1_port>, <&dmic2_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 27d28626bf5b..bce518ace6a0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -764,6 +764,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1734,6 +1838,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2052,6 +2269,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2068,6 +2289,8 @@ <&adx4_out3_port>, <&adx4_out4_port>, <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 8033be098f34..7acc32dd290a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -774,6 +774,110 @@ remote-endpoint = <&mixer_out5_ep>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; admaif@290f000 { @@ -1794,6 +1898,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; }; @@ -2102,6 +2319,10 @@ <&xbar_mixer_in5_port>, <&xbar_mixer_in6_port>, <&xbar_mixer_in7_port>, <&xbar_mixer_in8_port>, <&xbar_mixer_in9_port>, <&xbar_mixer_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -2119,6 +2340,8 @@ <&mixer_out1_port>, <&mixer_out2_port>, <&mixer_out3_port>, <&mixer_out4_port>, <&mixer_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s3_port>, <&i2s5_port>, <&dmic1_port>, <&dmic2_port>, <&dmic4_port>, diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts index 34d6a01ee1c6..eaf1994abb04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701-0000.dts @@ -763,6 +763,110 @@ remote-endpoint = <&mix_out5>; }; }; + + xbar_asrc_in1_port: port@63 { + reg = <0x63>; + + xbar_asrc_in1_ep: endpoint { + remote-endpoint = <&asrc_in1_ep>; + }; + }; + + port@64 { + reg = <0x64>; + + xbar_asrc_out1_ep: endpoint { + remote-endpoint = <&asrc_out1_ep>; + }; + }; + + xbar_asrc_in2_port: port@65 { + reg = <0x65>; + + xbar_asrc_in2_ep: endpoint { + remote-endpoint = <&asrc_in2_ep>; + }; + }; + + port@66 { + reg = <0x66>; + + xbar_asrc_out2_ep: endpoint { + remote-endpoint = <&asrc_out2_ep>; + }; + }; + + xbar_asrc_in3_port: port@67 { + reg = <0x67>; + + xbar_asrc_in3_ep: endpoint { + remote-endpoint = <&asrc_in3_ep>; + }; + }; + + port@68 { + reg = <0x68>; + + xbar_asrc_out3_ep: endpoint { + remote-endpoint = <&asrc_out3_ep>; + }; + }; + + xbar_asrc_in4_port: port@69 { + reg = <0x69>; + + xbar_asrc_in4_ep: endpoint { + remote-endpoint = <&asrc_in4_ep>; + }; + }; + + port@6a { + reg = <0x6a>; + + xbar_asrc_out4_ep: endpoint { + remote-endpoint = <&asrc_out4_ep>; + }; + }; + + xbar_asrc_in5_port: port@6b { + reg = <0x6b>; + + xbar_asrc_in5_ep: endpoint { + remote-endpoint = <&asrc_in5_ep>; + }; + }; + + port@6c { + reg = <0x6c>; + + xbar_asrc_out5_ep: endpoint { + remote-endpoint = <&asrc_out5_ep>; + }; + }; + + xbar_asrc_in6_port: port@6d { + reg = <0x6d>; + + xbar_asrc_in6_ep: endpoint { + remote-endpoint = <&asrc_in6_ep>; + }; + }; + + port@6e { + reg = <0x6e>; + + xbar_asrc_out6_ep: endpoint { + remote-endpoint = <&asrc_out6_ep>; + }; + }; + + xbar_asrc_in7_port: port@6f { + reg = <0x6f>; + + xbar_asrc_in7_ep: endpoint { + remote-endpoint = <&asrc_in7_ep>; + }; + }; }; i2s@2901000 { @@ -1733,6 +1837,119 @@ }; }; }; + + asrc@2910000 { + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0x0>; + + asrc_in1_ep: endpoint { + remote-endpoint = <&xbar_asrc_in1_ep>; + }; + }; + + port@1 { + reg = <0x1>; + + asrc_in2_ep: endpoint { + remote-endpoint = <&xbar_asrc_in2_ep>; + }; + }; + + port@2 { + reg = <0x2>; + + asrc_in3_ep: endpoint { + remote-endpoint = <&xbar_asrc_in3_ep>; + }; + }; + + port@3 { + reg = <0x3>; + + asrc_in4_ep: endpoint { + remote-endpoint = <&xbar_asrc_in4_ep>; + }; + }; + + port@4 { + reg = <0x4>; + + asrc_in5_ep: endpoint { + remote-endpoint = <&xbar_asrc_in5_ep>; + }; + }; + + port@5 { + reg = <0x5>; + + asrc_in6_ep: endpoint { + remote-endpoint = <&xbar_asrc_in6_ep>; + }; + }; + + port@6 { + reg = <0x6>; + + asrc_in7_ep: endpoint { + remote-endpoint = <&xbar_asrc_in7_ep>; + }; + }; + + asrc_out1_port: port@7 { + reg = <0x7>; + + asrc_out1_ep: endpoint { + remote-endpoint = <&xbar_asrc_out1_ep>; + }; + }; + + asrc_out2_port: port@8 { + reg = <0x8>; + + asrc_out2_ep: endpoint { + remote-endpoint = <&xbar_asrc_out2_ep>; + }; + }; + + asrc_out3_port: port@9 { + reg = <0x9>; + + asrc_out3_ep: endpoint { + remote-endpoint = <&xbar_asrc_out3_ep>; + }; + }; + + asrc_out4_port: port@a { + reg = <0xa>; + + asrc_out4_ep: endpoint { + remote-endpoint = <&xbar_asrc_out4_ep>; + }; + }; + + asrc_out5_port: port@b { + reg = <0xb>; + + asrc_out5_ep: endpoint { + remote-endpoint = <&xbar_asrc_out5_ep>; + }; + }; + + asrc_out6_port: port@c { + reg = <0xc>; + + asrc_out6_ep: endpoint { + remote-endpoint = <&xbar_asrc_out6_ep>; + }; + }; + }; + }; }; dma-controller@2930000 { @@ -1823,6 +2040,10 @@ <&xbar_mix_in5_port>, <&xbar_mix_in6_port>, <&xbar_mix_in7_port>, <&xbar_mix_in8_port>, <&xbar_mix_in9_port>, <&xbar_mix_in10_port>, + <&xbar_asrc_in1_port>, <&xbar_asrc_in2_port>, + <&xbar_asrc_in3_port>, <&xbar_asrc_in4_port>, + <&xbar_asrc_in5_port>, <&xbar_asrc_in6_port>, + <&xbar_asrc_in7_port>, /* HW accelerators */ <&sfc1_out_port>, <&sfc2_out_port>, <&sfc3_out_port>, <&sfc4_out_port>, @@ -1839,6 +2060,8 @@ <&adx4_out3_port>, <&adx4_out4_port>, <&mix_out1_port>, <&mix_out2_port>, <&mix_out3_port>, <&mix_out4_port>, <&mix_out5_port>, + <&asrc_out1_port>, <&asrc_out2_port>, <&asrc_out3_port>, + <&asrc_out4_port>, <&asrc_out5_port>, <&asrc_out6_port>, /* BE I/O Ports */ <&i2s1_port>, <&i2s2_port>, <&i2s4_port>, <&i2s6_port>, <&dmic3_port>; -- cgit v1.2.3 From 439677d416b17dd39964d5f7d64b742a2e51da5b Mon Sep 17 00:00:00 2001 From: Matthias Schiffer Date: Tue, 19 Apr 2022 09:51:57 +0200 Subject: arm64: dts: ti: k3-am64-mcu: remove incorrect UART base clock rates We found that (at least some versions of) the sci-fw set the base clock rate for UARTs in the MCU domain to 96 MHz instead of the expected 48 MHz, leading to incorrect baud rates when used from Linux. As the 8250_omap driver will query the actual clock rate from the clk driver when clock-frequency is unset, removing the incorrect property is sufficient to fix the baud rate. Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Signed-off-by: Matthias Schiffer Signed-off-by: Vignesh Raghavendra Reviewed-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20220419075157.189347-1-matthias.schiffer@ew.tq-group.com --- arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi index 2bb5c9ff172c..02d4285acbb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-mcu.dtsi @@ -10,7 +10,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a00000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 149 0>; @@ -21,7 +20,6 @@ compatible = "ti,am64-uart", "ti,am654-uart"; reg = <0x00 0x04a10000 0x00 0x100>; interrupts = ; - clock-frequency = <48000000>; current-speed = <115200>; power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 160 0>; -- cgit v1.2.3 From 065d62612e264e228c153afe9aa31d85aeea3d17 Mon Sep 17 00:00:00 2001 From: Kishon Vijay Abraham I Date: Thu, 14 Apr 2022 19:06:12 +0530 Subject: arm64: dts: ti: k3-am642-sk: Enable WLAN connected to SDHCI0 WL1837 module is connected to SDHCI0 in AM642 SK. Enable it here. This will enable the WiFi functionaliy on the board. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Vignesh Raghavendra Signed-off-by: Nikhil Devshatwar Signed-off-by: Aparna M Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220414133612.13365-1-a-m1@ti.com --- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 62 ++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts index 1d7db8bf3a5c..59f506cbd275 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -125,6 +125,31 @@ vin-supply = <&vcc_3v3_sys>; gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; }; + + com8_ls_en: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "com8_ls_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + pinctrl-0 = <&main_com8_ls_en_pins_default>; + pinctrl-names = "default"; + gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; + }; + + wlan_en: regulator-2 { + /* output of SN74AVC4T245RSVR */ + compatible = "regulator-fixed"; + regulator-name = "wlan_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + pinctrl-0 = <&main_wlan_en_pins_default>; + pinctrl-names = "default"; + vin-supply = <&com8_ls_en>; + gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; + }; }; &main_pmx0 { @@ -216,6 +241,23 @@ AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ >; }; + main_wlan_en_pins_default: main-wlan-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ + >; + }; + + main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ + >; + }; + + main_wlan_pins_default: main-wlan-pins-default { + pinctrl-single,pins = < + AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ + >; + }; }; &mcu_uart0 { @@ -293,6 +335,26 @@ status = "reserved"; }; +&sdhci0 { + vmmc-supply = <&wlan_en>; + bus-width = <4>; + non-removable; + cap-power-off-card; + keep-power-in-suspend; + ti,driver-strength-ohm = <50>; + + #address-cells = <1>; + #size-cells = <0>; + wlcore: wlcore@2 { + compatible = "ti,wl1837"; + reg = <2>; + pinctrl-0 = <&main_wlan_pins_default>; + pinctrl-names = "default"; + interrupt-parent = <&main_gpio0>; + interrupts = <46 IRQ_TYPE_EDGE_FALLING>; + }; +}; + &sdhci1 { /* SD/MMC */ vmmc-supply = <&vdd_mmc1>; -- cgit v1.2.3 From c37c58fdeb8a9ddaff2ae512bf738ac7a5d3cd2e Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 27 Apr 2022 12:59:53 +0530 Subject: arm64: dts: ti: k3-am62: Add more peripheral nodes Add nodes for McSPI, OSPI, DMA, CPSW, MMC and On Chip SRAM nodes. Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220427072954.8821-2-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 266 +++++++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 20 +++ 2 files changed, 286 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index c68472c692f4..eec8dae65e7c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -6,6 +6,14 @@ */ &cbass_main { + oc_sram: sram@70000000 { + compatible = "mmio-sram"; + reg = <0x00 0x70000000 0x00 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x70000000 0x10000>; + }; + gic500: interrupt-controller@1800000 { compatible = "arm,gic-v3"; #address-cells = <2>; @@ -40,6 +48,12 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0x00 0x00100000 0x20000>; + + phy_gmii_sel: phy@4044 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4044 0x8>; + #phy-cells = <1>; + }; }; dmss: bus@48000000 { @@ -61,6 +75,69 @@ interrupt-names = "rx_012"; interrupts = ; }; + + inta_main_dmss: interrupt-controller@48000000 { + compatible = "ti,sci-inta"; + reg = <0x00 0x48000000 0x00 0x100000>; + #interrupt-cells = <0>; + interrupt-controller; + interrupt-parent = <&gic500>; + msi-controller; + ti,sci = <&dmsc>; + ti,sci-dev-id = <28>; + ti,interrupt-ranges = <4 68 36>; + ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; + }; + + main_bcdma: dma-controller@485c0100 { + compatible = "ti,am64-dmss-bcdma"; + reg = <0x00 0x485c0100 0x00 0x100>, + <0x00 0x4c000000 0x00 0x20000>, + <0x00 0x4a820000 0x00 0x20000>, + <0x00 0x4aa40000 0x00 0x20000>, + <0x00 0x4bc00000 0x00 0x100000>; + reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <3>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <26>; + ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ + ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ + ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ + }; + + main_pktdma: dma-controller@485c0000 { + compatible = "ti,am64-dmss-pktdma"; + reg = <0x00 0x485c0000 0x00 0x100>, + <0x00 0x4a800000 0x00 0x20000>, + <0x00 0x4aa00000 0x00 0x40000>, + <0x00 0x4b800000 0x00 0x400000>; + reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; + msi-parent = <&inta_main_dmss>; + #dma-cells = <2>; + + ti,sci = <&dmsc>; + ti,sci-dev-id = <30>; + ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ + <0x24>, /* CPSW_TX_CHAN */ + <0x25>, /* SAUL_TX_0_CHAN */ + <0x26>; /* SAUL_TX_1_CHAN */ + ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ + <0x11>, /* RING_CPSW_TX_CHAN */ + <0x12>, /* RING_SAUL_TX_0_CHAN */ + <0x13>; /* RING_SAUL_TX_1_CHAN */ + ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ + <0x2b>, /* CPSW_RX_CHAN */ + <0x2d>, /* SAUL_RX_0_CHAN */ + <0x2f>, /* SAUL_RX_1_CHAN */ + <0x31>, /* SAUL_RX_2_CHAN */ + <0x33>; /* SAUL_RX_3_CHAN */ + ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ + <0x2c>, /* FLOW_CPSW_RX_CHAN */ + <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ + <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ + }; }; dmsc: system-controller@44043000 { @@ -203,6 +280,36 @@ clock-names = "fck"; }; + main_spi0: spi@20100000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x20100000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 172 0>; + }; + + main_spi1: spi@20110000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20110000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 173 0>; + }; + + main_spi2: spi@20120000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x20120000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 174 0>; + }; + main_gpio_intr: interrupt-controller@a00000 { compatible = "ti,sci-intr"; reg = <0x00 0x00a00000 0x00 0x800>; @@ -249,6 +356,165 @@ clock-names = "gpio"; }; + sdhci0: mmc@fa10000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 57 5>, <&k3_clks 57 6>; + clock-names = "clk_ahb", "clk_xin"; + assigned-clocks = <&k3_clks 57 6>; + assigned-clock-parents = <&k3_clks 57 8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + ti,trm-icp = <0x2>; + bus-width = <8>; + ti,clkbuf-sel = <0x7>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-ddr52 = <0x9>; + ti,otap-del-sel-hs200 = <0x6>; + }; + + sdhci1: mmc@fa00000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + bus-width = <4>; + }; + + sdhci2: mmc@fa20000 { + compatible = "ti,am62-sdhci"; + reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; + interrupts = ; + power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; + clock-names = "clk_ahb", "clk_xin"; + ti,trm-icp = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-sdr104 = <0x6>; + ti,otap-del-sel-ddr50 = <0x9>; + ti,itap-del-sel-legacy = <0x0>; + ti,itap-del-sel-sd-hs = <0x0>; + ti,itap-del-sel-sdr12 = <0x0>; + ti,itap-del-sel-sdr25 = <0x0>; + ti,clkbuf-sel = <0x7>; + }; + + fss: bus@fc00000 { + compatible = "simple-bus"; + reg = <0x00 0x0fc00000 0x00 0x70000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ospi0: spi@fc40000 { + compatible = "ti,am654-ospi", "cdns,qspi-nor"; + reg = <0x00 0x0fc40000 0x00 0x100>, + <0x05 0x00000000 0x01 0x00000000>; + interrupts = ; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + clocks = <&k3_clks 75 7>; + assigned-clocks = <&k3_clks 75 7>; + assigned-clock-parents = <&k3_clks 75 8>; + assigned-clock-rates = <166666666>; + power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + cpsw3g: ethernet@8000000 { + compatible = "ti,am642-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0x08000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; + clocks = <&k3_clks 13 0>; + assigned-clocks = <&k3_clks 13 3>; + assigned-clock-parents = <&k3_clks 13 11>; + clock-names = "fck"; + power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_pktdma 0xc600 15>, + <&main_pktdma 0xc601 15>, + <&main_pktdma 0xc602 15>, + <&main_pktdma 0xc603 15>, + <&main_pktdma 0xc604 15>, + <&main_pktdma 0xc605 15>, + <&main_pktdma 0xc606 15>, + <&main_pktdma 0xc607 15>, + <&main_pktdma 0x4600 15>; + dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", + "tx7", "rx"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + cpsw_port1: port@1 { + reg = <1>; + ti,mac-only; + label = "port1"; + phys = <&phy_gmii_sel 1>; + mac-address = [00 00 00 00 00 00]; + ti,syscon-efuse = <&wkup_conf 0x200>; + }; + + cpsw_port2: port@2 { + reg = <2>; + ti,mac-only; + label = "port2"; + phys = <&phy_gmii_sel 2>; + mac-address = [00 00 00 00 00 00]; + }; + }; + + cpsw3g_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 13 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,j721e-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 13 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + hwspinlock: spinlock@2a000000 { compatible = "ti,am64-hwspinlock"; reg = <0x00 0x2a000000 0x00 0x1000>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index 9d210d55fc71..d103824c963f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -33,4 +33,24 @@ clocks = <&k3_clks 106 2>; clock-names = "fck"; }; + + mcu_spi0: spi@4b00000 { + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; + reg = <0x00 0x04b00000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 147 0>; + }; + + mcu_spi1: spi@4b10000 { + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; + reg = <0x00 0x04b10000 0x00 0x400>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 148 0>; + }; }; -- cgit v1.2.3 From d19a66ae488afe23398090b5dbe5483b26863e13 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Wed, 27 Apr 2022 12:59:54 +0530 Subject: arm64: dts: ti: k3-am625-sk: Enable on board peripherals Add nodes for I2C IO expander, OSPI Flash, Eth PHYs, SD and eMMC that are present on AM625 SK board. Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220427072954.8821-3-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 273 +++++++++++++++++++++++++++++++++ 1 file changed, 273 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 0de4113ccd5d..5c38ee5ff9b2 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -9,6 +9,7 @@ #include #include +#include #include "k3-am625.dtsi" / { @@ -17,6 +18,12 @@ aliases { serial2 = &main_uart0; + mmc0 = &sdhci0; + mmc1 = &sdhci1; + mmc2 = &sdhci2; + spi0 = &ospi0; + ethernet0 = &cpsw_port1; + ethernet1 = &cpsw_port2; }; chosen { @@ -87,6 +94,33 @@ regulator-boot-on; }; + vdd_mmc1: regulator-3 { + /* TPS22918DBVR */ + compatible = "regulator-fixed"; + regulator-name = "vdd_mmc1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + enable-active-high; + vin-supply = <&vcc_3v3_sys>; + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; + }; + + vdd_sd_dv: regulator-4 { + /* Output of TLV71033 */ + compatible = "regulator-gpio"; + regulator-name = "tlv71033"; + pinctrl-names = "default"; + pinctrl-0 = <&vdd_sd_dv_pins_default>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + vin-supply = <&vcc_5v0>; + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; + states = <1800000 0x0>, + <3300000 0x1>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -124,11 +158,114 @@ >; }; + main_i2c2_pins_default: main-i2c2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_mmc0_pins_default: main-mmc0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ + >; + }; + + main_mmc1_pins_default: main-mmc1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ + >; + }; + usr_led_pins_default: usr-led-pins-default { pinctrl-single,pins = < AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ >; }; + + main_mdio1_pins_default: main-mdio1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ + >; + }; + + main_rgmii1_pins_default: main-rgmii1-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ + >; + }; + + main_rgmii2_pins_default: main-rgmii2-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ + AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ + AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ + AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ + AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ + AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ + AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ + AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ + AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ + AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ + AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ + AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ + >; + }; + + ospi0_pins_default: ospi0-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ + AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ + AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ + AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ + AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ + AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ + AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ + AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ + AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ + AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ + AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ + >; + }; + + vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ + >; + }; + + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { + pinctrl-single,pins = < + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ + >; + }; }; &wkup_uart0 { @@ -188,6 +325,33 @@ pinctrl-names = "default"; pinctrl-0 = <&main_i2c1_pins_default>; clock-frequency = <400000>; + + exp1: gpio@22 { + compatible = "ti,tca6424"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", + "PRU_DETECT", "MMC1_SD_EN", + "VPP_LDO_EN", "EXP_PS_3V3_En", + "EXP_PS_5V0_En", "EXP_HAT_DETECT", + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", + "UART1_FET_BUF_EN", "WL_LT_EN", + "GPIO_HDMI_RSTn", "CSI_GPIO1", + "CSI_GPIO2", "PRU_3V3_EN", + "HDMI_INTn", "TEST_GPIO2", + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", + "MCASP1_FET_SEL", "UART1_FET_SEL", + "TSINT#", "IO_EXP_TEST_LED"; + + interrupt-parent = <&main_gpio1>; + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; + }; }; &main_i2c2 { @@ -198,9 +362,118 @@ status = "disabled"; }; +&sdhci0 { + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc0_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&sdhci1 { + /* SD/MMC */ + vmmc-supply = <&vdd_mmc1>; + vqmmc-supply = <&vdd_sd_dv>; + pinctrl-names = "default"; + pinctrl-0 = <&main_mmc1_pins_default>; + ti,driver-strength-ohm = <50>; + disable-wp; +}; + +&cpsw3g { + pinctrl-names = "default"; + pinctrl-0 = <&main_mdio1_pins_default + &main_rgmii1_pins_default + &main_rgmii2_pins_default>; +}; + +&cpsw_port1 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy0>; +}; + +&cpsw_port2 { + phy-mode = "rgmii-rxid"; + phy-handle = <&cpsw3g_phy1>; +}; + +&cpsw3g_mdio { + cpsw3g_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; + + cpsw3g_phy1: ethernet-phy@1 { + reg = <1>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + &mailbox0_cluster0 { mbox_m4_0: mbox-m4-0 { ti,mbox-rx = <0 0 0>; ti,mbox-tx = <1 0 0>; }; }; + +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&ospi0_pins_default>; + + flash@0{ + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; -- cgit v1.2.3 From bd67e1be98ddb884ff3f3df95c2382e6e70930b6 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Tue, 19 Apr 2022 11:59:02 +0530 Subject: arm64: dts: ti: k3-am625-sk: Add ECAP APWM nodes AM62 has 3 ECAP instances with 1 APWM each. Add DT nodes for the same. Keep them disabled in am625-sk dts as these pins can be repurposed in user exp connector. Signed-off-by: Vignesh Raghavendra Reviewed-by: Aswath Govindraju Link: https://lore.kernel.org/r/20220419062902.196526-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 27 +++++++++++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 12 ++++++++++++ 2 files changed, 39 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index eec8dae65e7c..9f32b6dad8a9 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -530,4 +530,31 @@ ti,mbox-num-users = <4>; ti,mbox-num-fifos = <16>; }; + + ecap0: pwm@23100000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23100000 0x00 0x100>; + power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 51 0>; + clock-names = "fck"; + }; + + ecap1: pwm@23110000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23110000 0x00 0x100>; + power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 52 0>; + clock-names = "fck"; + }; + + ecap2: pwm@23120000 { + compatible = "ti,am3352-ecap"; + #pwm-cells = <3>; + reg = <0x00 0x23120000 0x00 0x100>; + power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 53 0>; + clock-names = "fck"; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 5c38ee5ff9b2..3b6a20e342ed 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -477,3 +477,15 @@ }; }; }; + +&ecap0 { + status = "disabled"; +}; + +&ecap1 { + status = "disabled"; +}; + +&ecap2 { + status = "disabled"; +}; -- cgit v1.2.3 From d196d2a98d62c505ab71caf2630575e448dc417c Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 21 Apr 2022 11:49:38 +0530 Subject: arm64: dts: ti: k3-am62-mcu: Enable MCU GPIO module AM62 has x1 GPIO module and associated interrupt router in MCU Domain. Add DT nodes for the same. Signed-off-by: Vignesh Raghavendra Reviewed-by: Aswath Govindraju Link: https://lore.kernel.org/r/20220421061938.122317-1-vigneshr@ti.com --- arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi index d103824c963f..f56c803560f2 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi @@ -53,4 +53,32 @@ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 148 0>; }; + + mcu_gpio_intr: interrupt-controller@4210000 { + compatible = "ti,sci-intr"; + reg = <0x00 0x04210000 0x00 0x200>; + ti,intr-trigger-type = <1>; + interrupt-controller; + interrupt-parent = <&gic500>; + #interrupt-cells = <1>; + ti,sci = <&dmsc>; + ti,sci-dev-id = <5>; + ti,interrupt-ranges = <0 104 4>; + }; + + mcu_gpio0: gpio@4201000 { + compatible = "ti,am64-gpio", "ti,keystone-gpio"; + reg = <0x00 0x4201000 0x00 0x100>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&mcu_gpio_intr>; + interrupts = <30>, <31>; + interrupt-controller; + #interrupt-cells = <2>; + ti,ngpio = <24>; + ti,davinci-gpio-unbanked = <0>; + power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 79 0>; + clock-names = "gpio"; + }; }; -- cgit v1.2.3 From 2492a974022081935fbcb0f1bf8a80fc39812806 Mon Sep 17 00:00:00 2001 From: Aswath Govindraju Date: Mon, 18 Apr 2022 17:28:01 +0530 Subject: arm64: dts: ti: k3-am62: Add support for MCAN AM62 SoC has one instance of MCAN in main domain. However, its corresponding CAN signals are not brought out through a transceiver, on the SK board. Therefore, add the device tree node in the main dt file and set the status to disabled in the SK board dts file. Signed-off-by: Aswath Govindraju Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220418115802.5672-1-a-govindraju@ti.com --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 14 ++++++++++++++ arch/arm64/boot/dts/ti/k3-am625-sk.dts | 4 ++++ 2 files changed, 18 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi index 9f32b6dad8a9..d08abad0bcf4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -557,4 +557,18 @@ clocks = <&k3_clks 53 0>; clock-names = "fck"; }; + + main_mcan0: can@20701000 { + compatible = "bosch,m_can"; + reg = <0x00 0x20701000 0x00 0x200>, + <0x00 0x20708000 0x00 0x8000>; + reg-names = "m_can", "message_ram"; + power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; + clock-names = "hclk", "cclk"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; + }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/ti/k3-am625-sk.dts index 3b6a20e342ed..39fb1d763037 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -489,3 +489,7 @@ &ecap2 { status = "disabled"; }; + +&main_mcan0 { + status = "disabled"; +}; -- cgit v1.2.3 From bc9e1dbb175706242a7160675b4f52d0380ae4ea Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:18 +0100 Subject: arm64: dts: renesas: r9a07g043: Add I2C2 node and fillup the I2C{0,1,3} stub nodes Add I2C2 node and fillup the I2C{0,1,3} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 73 ++++++++++++++++++++++++++++-- 1 file changed, 70 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index c8aadbe55278..2025224d71ab 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -220,22 +220,89 @@ i2c0: i2c@10058000 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058000 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C0_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c1: i2c@10058400 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058400 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C1_MRST>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@10058800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; + reg = <0 0x10058800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C2_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; i2c3: i2c@10058c00 { #address-cells = <1>; #size-cells = <0>; + compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; reg = <0 0x10058c00 0 0x400>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A07G043_I2C3_MRST>; + power-domains = <&cpg>; + status = "disabled"; }; adc: adc@10059000 { -- cgit v1.2.3 From 559f2b0708c70c49ae3143d481ee10351089e590 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:19 +0100 Subject: arm64: dts: renesas: r9a07g043: Add SSI{1,2,3} nodes and fillup the SSI0 stub node Add SSI{1,2,3} nodes and fillup the SSI0 stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 80 +++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 2025224d71ab..ef8550a2de09 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -75,9 +75,87 @@ ranges; ssi0: ssi@10049c00 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; reg = <0 0x10049c00 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; + dmas = <&dmac 0x2655>, <&dmac 0x2656>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; #sound-dai-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + ssi1: ssi@1004a000 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a000 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; + dmas = <&dmac 0x2659>, <&dmac 0x265a>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi2: ssi@1004a400 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a400 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; + dmas = <&dmac 0x265f>; + dma-names = "rt"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + ssi3: ssi@1004a800 { + compatible = "renesas,r9a07g043-ssi", + "renesas,rz-ssi"; + reg = <0 0x1004a800 0 0x400>; + interrupts = , + , + , + ; + interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; + clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, + <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, + <&audio_clk1>, <&audio_clk2>; + clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; + resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; + dmas = <&dmac 0x2661>, <&dmac 0x2662>; + dma-names = "tx", "rx"; + power-domains = <&cpg>; + #sound-dai-cells = <0>; + status = "disabled"; }; spi1: spi@1004b000 { -- cgit v1.2.3 From f52e14095e56ab6470d959f08e40aa2e45cb85cd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:20 +0100 Subject: arm64: dts: renesas: r9a07g043: Add USB2.0 support Add USB2.0 host and device support by filling usb phy control, phy, device and host stub nodes in RZ/G2UL SoC dtsi. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 90 +++++++++++++++++++++++++++--- 1 file changed, 82 insertions(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index ef8550a2de09..8bcda969d130 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -551,43 +551,117 @@ }; phyrst: usbphy-ctrl@11c40000 { + compatible = "renesas,r9a07g043-usbphy-ctrl", + "renesas,rzg2l-usbphy-ctrl"; reg = <0 0x11c40000 0 0x10000>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; + resets = <&cpg R9A07G043_USB_PRESETN>; + power-domains = <&cpg>; + #reset-cells = <1>; + status = "disabled"; }; ohci0: usb@11c50000 { + compatible = "generic-ohci"; reg = <0 0x11c50000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ohci1: usb@11c70000 { + compatible = "generic-ohci"; reg = <0 0x11c70000 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; ehci0: usb@11c50100 { + compatible = "generic-ehci"; reg = <0 0x11c50100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2H0_HRESETN>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&cpg>; + status = "disabled"; }; ehci1: usb@11c70100 { + compatible = "generic-ehci"; reg = <0 0x11c70100 0 0x100>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>, + <&cpg R9A07G043_USB_U2H1_HRESETN>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy0: usb-phy@11c50200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c50200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; + resets = <&phyrst 0>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; usb2_phy1: usb-phy@11c70200 { + compatible = "renesas,usb2-phy-r9a07g043", + "renesas,rzg2l-usb2-phy"; reg = <0 0x11c70200 0 0x700>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; + resets = <&phyrst 1>; + #phy-cells = <1>; + power-domains = <&cpg>; + status = "disabled"; }; hsusb: usb@11c60000 { + compatible = "renesas,usbhs-r9a07g043", + "renesas,rza2-usbhs"; reg = <0 0x11c60000 0 0x10000>; - /* place holder */ + interrupts = , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, + <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; + resets = <&phyrst 0>, + <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; + renesas,buswait = <7>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&cpg>; + status = "disabled"; }; wdt0: watchdog@12800800 { -- cgit v1.2.3 From 1de1b44833e394e63119fcff37e458a94c244799 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:21 +0100 Subject: arm64: dts: renesas: r9a07g043: Fillup the CANFD stub node Fillup the CANFD stub node in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 31 +++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 8bcda969d130..60db9b02e0a7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -291,8 +291,37 @@ }; canfd: can@10050000 { + compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; reg = <0 0x10050000 0 0x8000>; - /* place holder */ + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "g_err", "g_recc", + "ch0_err", "ch0_rec", "ch0_trx", + "ch1_err", "ch1_rec", "ch1_trx"; + clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, + <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; + assigned-clock-rates = <50000000>; + resets = <&cpg R9A07G043_CANFD_RSTP_N>, + <&cpg R9A07G043_CANFD_RSTC_N>; + reset-names = "rstp_n", "rstc_n"; + power-domains = <&cpg>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + channel1 { + status = "disabled"; + }; }; i2c0: i2c@10058000 { -- cgit v1.2.3 From e42faad1ef822e186c20e60576b198e1ac9866c4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:22 +0100 Subject: arm64: dts: renesas: r9a07g043: Fillup the OSTM{0,1,2} stub nodes Fillup the OSTM{0,1,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 60db9b02e0a7..d161600495aa 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -704,18 +704,36 @@ }; ostm0: timer@12801000 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801000 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; + resets = <&cpg R9A07G043_OSTM0_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm1: timer@12801400 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801400 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; + resets = <&cpg R9A07G043_OSTM1_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; ostm2: timer@12801800 { + compatible = "renesas,r9a07g043-ostm", + "renesas,ostm"; reg = <0x0 0x12801800 0x0 0x400>; - /* place holder */ + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; + resets = <&cpg R9A07G043_OSTM2_PRESETZ>; + power-domains = <&cpg>; + status = "disabled"; }; }; -- cgit v1.2.3 From a8352a5158ed032fa6c0d433fefc63285fdac8b0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:23 +0100 Subject: arm64: dts: renesas: r9a07g043: Fillup the WDT{0,2} stub nodes Fillup the WDT{0,2} stub nodes in RZ/G2UL (R9A07G043) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-7-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index d161600495aa..15335e9ca06b 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -694,13 +694,33 @@ }; wdt0: watchdog@12800800 { + compatible = "renesas,r9a07g043-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800800 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, + <&cpg CPG_MOD R9A07G043_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G043_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; wdt2: watchdog@12800400 { + compatible = "renesas,r9a07g043-wdt", + "renesas,rzg2l-wdt"; reg = <0 0x12800400 0 0x400>; - /* place holder */ + clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, + <&cpg CPG_MOD R9A07G043_WDT2_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A07G043_WDT2_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; }; ostm0: timer@12801000 { -- cgit v1.2.3 From c024c46fe13bb9e9a70d044fd2d63dbee82bbb59 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Tue, 12 Apr 2022 13:20:08 +0530 Subject: arm64: dts: ti: k3-am62: Add SA3UL ranges in cbass_main Add the address space for SA3UL to the ranges property of the cbass_main node. Signed-off-by: Jayesh Choudhary Signed-off-by: Vignesh Raghavendra Reviewed-by: Bryan Brattlof Link: https://lore.kernel.org/r/20220412075008.10553-1-j-choudhary@ti.com --- arch/arm64/boot/dts/ti/k3-am62.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi index bc2997b18556..37fcbe7a3c33 100644 --- a/arch/arm64/boot/dts/ti/k3-am62.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi @@ -66,6 +66,7 @@ <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ + <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ -- cgit v1.2.3 From b0fa698b834f0f8b4a0c9c5c086d88787f1124a0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:24 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Enable i2c{0,1} and wm8978 Enable i2c{0,1} on RZ/G2UL SMARC EVK by deleting respective entries from board dts and adding pincontrol entries to the soc-pinctrl dtsi. Also enable wm8978 audio codec. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-8-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 18 ------------------ .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 10 ++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 ++++++++ 3 files changed, 18 insertions(+), 18 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 08a0404c6f0b..2bf4a3b62438 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -38,24 +38,6 @@ status = "disabled"; }; -&i2c0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&i2c1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; - - wm8978: codec@1a { - compatible = "wlf,wm8978"; - #sound-dai-cells = <0>; - reg = <0x1a>; - }; -}; - &ohci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index b515748e6a9a..94106095c66a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -12,6 +12,16 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; + i2c0_pins: i2c0 { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + i2c1_pins: i2c1 { + pins = "RIIC1_SDA", "RIIC1_SCL"; + input-enable; + }; + scif0_pins: scif0 { pinmux = , /* TxD */ ; /* RxD */ diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index 056a77369c8d..a580b04987ec 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -19,6 +19,14 @@ #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" +&i2c1 { + wm8978: codec@1a { + compatible = "wlf,wm8978"; + #sound-dai-cells = <0>; + reg = <0x1a>; + }; +}; + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; }; -- cgit v1.2.3 From 820e976909c2b286d1ef259ea524979540475ba6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:28 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Enable CANFD Enable CANFD on RZ/G2UL SMARC platform. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-12-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 6 ----- .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 28 ++++++++++++++++++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 8 +++++++ 3 files changed, 36 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 2bf4a3b62438..df27b63f0465 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -14,12 +14,6 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; -&canfd { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &ehci0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 94106095c66a..17527184ff2a 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -12,6 +12,34 @@ pinctrl-0 = <&sound_clk_pins>; pinctrl-names = "default"; + can0_pins: can0 { + pinmux = , /* TX */ + ; /* RX */ + }; + +#if (SW_ET0_EN_N) + can0-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can0_stb"; + }; +#endif + + can1_pins: can1 { + pinmux = , /* TX */ + ; /* RX */ + }; + +#if (SW_ET0_EN_N) + can1-stb-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "can1_stb"; + }; +#endif + i2c0_pins: i2c0 { pins = "RIIC0_SDA", "RIIC0_SCL"; input-enable; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index a580b04987ec..d75ad79ba804 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -19,6 +19,14 @@ #include "rzg2ul-smarc-pinfunction.dtsi" #include "rz-smarc-common.dtsi" +#if (!SW_ET0_EN_N) +&canfd { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978"; -- cgit v1.2.3 From 0b3e18dbcdf6ec80d22d76d4c8099968704f7cf9 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:29 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc-som: Enable OSTM Enable OSTM{1, 2} interfaces on RZ/G2UL SMARC EVK. OSTM0 is reserved for TF-A. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-13-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index b0822679a55b..4c4cd7f2f17b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -115,6 +115,14 @@ clock-frequency = <24000000>; }; +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + &pinctrl { eth0_pins: eth0 { pinmux = , /* ET0_LINKSTA */ -- cgit v1.2.3 From 3f67af66e65baf88da482b6327c53c742b949d15 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 25 Apr 2022 18:05:30 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc-som: Enable watchdog Enable watchdog{0,2} interfaces on RZ/G2UL SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220425170530.200921-14-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi index 4c4cd7f2f17b..a663115f5aae 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi @@ -239,3 +239,13 @@ status = "okay"; }; #endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; -- cgit v1.2.3 From 000b99e5ed1c9e33c14f3582474ae55cd739ae8d Mon Sep 17 00:00:00 2001 From: Ashish Mhetre Date: Tue, 26 Apr 2022 13:08:27 +0530 Subject: arm64: tegra: Add memory controller channels From tegra186 onwards, memory controller support multiple channels. During the error interrupts from memory controller, corresponding channels need to be accessed for logging error info and clearing the interrupt. So add address and size of these channels in device tree node of tegra186, tegra194 and tegra234 memory controller. Also add reg-names for each of these reg items which are used by driver for mapping. Signed-off-by: Ashish Mhetre Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 8 +++++++- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 24 +++++++++++++++++++++--- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 24 +++++++++++++++++++++--- 3 files changed, 49 insertions(+), 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 2e7faa1e0b9c..0e9afc3e2f26 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -528,7 +528,13 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; - reg = <0x0 0x02c00000 0x0 0xb0000>; + reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */ + <0x0 0x02c10000 0x0 0x10000>, /* Broadcast channel */ + <0x0 0x02c20000 0x0 0x10000>, /* MC0 */ + <0x0 0x02c30000 0x0 0x10000>, /* MC1 */ + <0x0 0x02c40000 0x0 0x10000>, /* MC2 */ + <0x0 0x02c50000 0x0 0x10000>; /* MC3 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3"; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index f9d343b24597..d1f8248c00f4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -612,9 +612,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra194-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "disabled"; diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 71c21d7d0551..cb3af539e477 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -515,9 +515,27 @@ mc: memory-controller@2c00000 { compatible = "nvidia,tegra234-mc"; - reg = <0x02c00000 0x100000>, - <0x02b80000 0x040000>, - <0x01700000 0x100000>; + reg = <0x02c00000 0x10000>, /* MC-SID */ + <0x02c10000 0x10000>, /* MC Broadcast*/ + <0x02c20000 0x10000>, /* MC0 */ + <0x02c30000 0x10000>, /* MC1 */ + <0x02c40000 0x10000>, /* MC2 */ + <0x02c50000 0x10000>, /* MC3 */ + <0x02b80000 0x10000>, /* MC4 */ + <0x02b90000 0x10000>, /* MC5 */ + <0x02ba0000 0x10000>, /* MC6 */ + <0x02bb0000 0x10000>, /* MC7 */ + <0x01700000 0x10000>, /* MC8 */ + <0x01710000 0x10000>, /* MC9 */ + <0x01720000 0x10000>, /* MC10 */ + <0x01730000 0x10000>, /* MC11 */ + <0x01740000 0x10000>, /* MC12 */ + <0x01750000 0x10000>, /* MC13 */ + <0x01760000 0x10000>, /* MC14 */ + <0x01770000 0x10000>; /* MC15 */ + reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", + "ch11", "ch12", "ch13", "ch14", "ch15"; interrupts = ; #interconnect-cells = <1>; status = "okay"; -- cgit v1.2.3 From a2fe0f97fd4a5e482123fc207a48bde844b161a1 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Mon, 25 Apr 2022 19:45:09 +0100 Subject: arm64: dts: rockchip: Rename vdec_mmu node for RK3328 All other rockchip devices which have vdec nodes do not have an rk prefix. Remove the prefix from the (currently unused) rkvdec_mmu node for consistency with other devices. Signed-off-by: Christopher Obbard Reviewed-by: Ezequiel Garcia Link: https://lore.kernel.org/r/20220425184510.1138446-3-chris.obbard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b822533dc7f1..f8ef149fedad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -660,7 +660,7 @@ power-domains = <&power RK3328_PD_VPU>; }; - rkvdec_mmu: iommu@ff360480 { + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; interrupts = ; -- cgit v1.2.3 From 17408c9b119de4edef9ea57ade7e97d4a1b8b632 Mon Sep 17 00:00:00 2001 From: Christopher Obbard Date: Mon, 25 Apr 2022 19:45:10 +0100 Subject: arm64: dts: rockchip: Add vdec support for RK3328 The RK3328 has an vdec device with dedicated iommu. Describe the vdec device, the required power-domains and enable the iommu in the devicetree. Signed-off-by: Christopher Obbard Link: https://lore.kernel.org/r/20220425184510.1138446-4-chris.obbard@collabora.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3328.dtsi | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index f8ef149fedad..49ae15708a0b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -306,6 +306,10 @@ }; power-domain@RK3328_PD_VIDEO { reg = ; + clocks = <&cru ACLK_RKVDEC>, + <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; #power-domain-cells = <0>; }; power-domain@RK3328_PD_VPU { @@ -660,6 +664,20 @@ power-domains = <&power RK3328_PD_VPU>; }; + vdec: video-codec@ff360000 { + compatible = "rockchip,rk3328-vdec", "rockchip,rk3399-vdec"; + reg = <0x0 0xff360000 0x0 0x400>; + interrupts = ; + clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, + <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; + clock-names = "axi", "ahb", "cabac", "core"; + assigned-clocks = <&cru ACLK_RKVDEC>, <&cru SCLK_VDEC_CABAC>, + <&cru SCLK_VDEC_CORE>; + assigned-clock-rates = <400000000>, <400000000>, <300000000>; + iommus = <&vdec_mmu>; + power-domains = <&power RK3328_PD_VIDEO>; + }; + vdec_mmu: iommu@ff360480 { compatible = "rockchip,iommu"; reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>; @@ -667,7 +685,7 @@ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; clock-names = "aclk", "iface"; #iommu-cells = <0>; - status = "disabled"; + power-domains = <&power RK3328_PD_VIDEO>; }; vop: vop@ff370000 { -- cgit v1.2.3 From ec48c3e82ca36a66ae37ba8b1fdb9a7561dcab14 Mon Sep 17 00:00:00 2001 From: Caleb Connolly Date: Mon, 28 Mar 2022 01:50:05 +0100 Subject: arm64: dts: rockchip: add an input enable pinconf to rk3399 Add a pinconf to configure pins as input-enable. Signed-off-by: Caleb Connolly Link: https://lore.kernel.org/r/20220328005005.72492-5-kc@postmarketos.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index a90beec50f6a..8db8b2dba12d 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -2211,6 +2211,22 @@ output-low; }; + pcfg_input_enable: pcfg-input-enable { + input-enable; + }; + + pcfg_input_pull_up: pcfg-input-pull-up { + input-enable; + bias-pull-up; + drive-strength = <2>; + }; + + pcfg_input_pull_down: pcfg-input-pull-down { + input-enable; + bias-pull-down; + drive-strength = <2>; + }; + clock { clk_32k: clk-32k { rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; -- cgit v1.2.3 From 8d411bebd4538a9750db175c030d6083d5210d7c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Apr 2022 22:56:13 -0500 Subject: arm64: dts: rockchip: Add accelerometer to rk3566-pinenote PineNote has an SC7A20 accelerometer connected via I2C. Enable it. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220413035614.31045-2-samuel@sholland.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index fea748adfa90..adc0e7d39fb3 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -468,6 +468,22 @@ }; }; +&i2c5 { + status = "okay"; + + accelerometer@18 { + compatible = "silan,sc7a20"; + reg = <0x18>; + interrupt-parent = <&gpio3>; + interrupts = ; + pinctrl-0 = <&accelerometer_int_l>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + vdd-supply = <&vcc_3v3>; + vddio-supply = <&vcc_3v3>; + }; +}; + &i2s1_8ch { pinctrl-0 = <&i2s1m0_lrcktx>, <&i2s1m0_sclktx>, <&i2s1m0_sdi0>, <&i2s1m0_sdo0>; rockchip,trcm-sync-tx-only; @@ -482,6 +498,12 @@ }; &pinctrl { + accelerometer { + accelerometer_int_l: accelerometer-int-l { + rockchip,pins = <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + audio-amplifier { spk_amp_enable_h: spk-amp-enable-h { rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; -- cgit v1.2.3 From 87a267b4af09477721e9d2bad63555f0dc49d08a Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Apr 2022 22:56:14 -0500 Subject: arm64: dts: rockchip: Add USB and TCPC to rk3566-pinenote PineNote has a USB Type-C port connected to the first USB 2.0 OTG PHY and XHCI controller via a Willsemi WUSB3801 Type-C port controller. Add support for it. Signed-off-by: Samuel Holland Link: https://lore.kernel.org/r/20220413035614.31045-3-samuel@sholland.org Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi index adc0e7d39fb3..e01668e6e5f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi @@ -466,6 +466,39 @@ default-brightness = <0>; }; }; + + wusb3801: tcpc@60 { + compatible = "willsemi,wusb3801"; + reg = <0x60>; + interrupt-parent = <&gpio0>; + interrupts = ; + pinctrl-0 = <&tcpc_int_l>; + pinctrl-names = "default"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + vbus-supply = <&otg_switch>; + power-role = "dual"; + try-power-role = "sink"; + data-role = "dual"; + typec-power-opmode = "default"; + pd-disable; + + ports { + #address-cells = <0x1>; + #size-cells = <0x0>; + + port@0 { + reg = <0x0>; + + typec_hs_usb2phy0: endpoint { + remote-endpoint = <&usb2phy0_typec_hs>; + }; + }; + }; + }; + }; }; &i2c5 { @@ -572,6 +605,12 @@ }; }; + tcpc { + tcpc_int_l: tcpc-int-l { + rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + vcc-wl { vcc_wl_pin: vcc-wl-pin { rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; @@ -659,3 +698,22 @@ &uart2 { status = "okay"; }; + +&usb_host0_xhci { + dr_mode = "otg"; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + status = "okay"; + + port { + usb2phy0_typec_hs: endpoint { + remote-endpoint = <&typec_hs_usb2phy0>; + }; + }; +}; -- cgit v1.2.3 From 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:49 -0400 Subject: arm64: dts: rockchip: add rk356x sfc support Add the sfc node to the rk356x device tree. This enables spi flash support for this soc. Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-5-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 55e6dcb948cc..3f0e11af738d 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -778,6 +778,17 @@ status = "disabled"; }; + sfc: spi@fe300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0xfe300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; + clock-names = "clk_sfc", "hclk_sfc"; + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + status = "disabled"; + }; + sdhci: mmc@fe310000 { compatible = "rockchip,rk3568-dwcmshc"; reg = <0x0 0xfe310000 0x0 0x10000>; -- cgit v1.2.3 From 254a1f6a29e7a273adb1a1d032305ec58ef83a69 Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:01 +0200 Subject: arm64: dts: rockchip: add usb3 support to the radxa rock3 model a The Radxa ROCK3 Model A features one USB 3.0 host port and one USB 3.0 OTG/DRD port. Enable them in the device tree. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-2-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 46 +++++++++++++++++++++++++ 1 file changed, 46 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 53cf444ecb04..4169f8a85ecd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -96,6 +96,26 @@ regulator-max-microvolt = <5000000>; vin-supply = <&vcc5v0_usb>; }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en>; + regulator-name = "vcc5v0_usb_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_usb>; + }; +}; + +&combphy0 { + status = "okay"; +}; + +&combphy1 { + status = "okay"; }; &cpu0 { @@ -416,6 +436,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; }; }; @@ -479,6 +502,11 @@ status = "okay"; }; +&usb_host0_xhci { + extcon = <&usb2phy0>; + status = "okay"; +}; + &usb_host1_ehci { status = "okay"; }; @@ -487,6 +515,24 @@ status = "okay"; }; +&usb_host1_xhci { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb_host>; + status = "okay"; +}; + +&usb2phy0_otg { + vbus-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + &usb2phy1 { status = "okay"; }; -- cgit v1.2.3 From 160f126b89e10bd58491e10067a44c7e3f85fa2c Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:02 +0200 Subject: arm64: dts: rockchip: enable usb hub on the radxa rock3 model a One USB 2.0 host port on the Radxa ROCK3 Model A is connected to the SoC via a hub. Introduce a voltage regulator to enable this USB hub. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-3-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts index 4169f8a85ecd..0813c0c5abde 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts @@ -97,6 +97,17 @@ vin-supply = <&vcc5v0_usb>; }; + vcc5v0_usb_hub: vcc5v0-usb-hub-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_hub_en>; + regulator-name = "vcc5v0_usb_hub"; + regulator-always-on; + vin-supply = <&vcc5v0_usb>; + }; + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -436,6 +447,9 @@ vcc5v0_usb_host_en: vcc5v0_usb_host_en { rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; }; + vcc5v0_usb_hub_en: vcc5v0_usb_hub_en { + rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; + }; vcc5v0_usb_otg_en: vcc5v0_usb_otg_en { rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; }; -- cgit v1.2.3 From b30ae5638dac6c5e640c47f59707d5b1e2c493e2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:57 +0200 Subject: arm64: dts: juno: Drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Another reason is that the number of requests also does not seem right (should be 8). Link: https://lore.kernel.org/r/20220430121902.59895-5-krzysztof.kozlowski@linaro.org Reported-by: Rob Herring Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sudeep Holla --- arch/arm64/boot/dts/arm/juno-base.dtsi | 2 -- 1 file changed, 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index 4f40a5c8f565..065381c1cbf5 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -829,8 +829,6 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0x0 0x7ff00000 0 0x1000>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; interrupts = , , , -- cgit v1.2.3 From dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20 Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:50 -0400 Subject: arm64: dts: rockchip: add Pine64 Quartz64-B device tree Add a device tree for the Pine64 Quartz64 Model B single board computer. This board ouputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 x2 (one port otg capable) USB3 PCIe/SATA M2 HDMI DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI Flash PI-40 compatible pin header Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-6-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts | 615 +++++++++++++++++++++ 2 files changed, 616 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 99941e9dbba1..1093146d33ee 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts new file mode 100644 index 000000000000..7bdcecc0dfe4 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts @@ -0,0 +1,615 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 Quartz64-B Board"; + compatible = "pine64,quartz64-b", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <100>; + power-off-delay-us = <5000000>; + }; + + vcc5v0_in: vcc5v0-in-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_in"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_in>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m1_miim + &gmac1m1_tx_bus2 + &gmac1m1_rx_bus2 + &gmac1m1_rgmii_clk + &gmac1m1_clkinout + &gmac1m1_rgmii_bus>; + snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc_3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + }; + }; + }; +}; + +/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "okay"; +}; + +/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +/* + * i2c4_m0 is exposed on PI40, pulled up to vcc_3v3 + * pin 27 - i2c4_sda_m0 + * pin 28 - i2c4_scl_m0 + */ +&i2c4 { + status = "okay"; +}; + +/* + * i2c5_m0 is exposed on PI40 + * pin 29 - i2c5_scl_m0 + * pin 31 - i2c5_sda_m0 + */ +&i2c5 { + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcca1v8_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcca1v8_pmu>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; +}; + +&saradc { + vref-supply = <&vcca_1v8>; + status = "okay"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + status = "okay"; +}; + +&sfc { + pinctrl-0 = <&fspi_pins>; + pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <24000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <1>; + }; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4345c5"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2_m0 is exposed on PI40 + * pin 8 - uart2_tx_m0 + * pin 10 - uart2_rx_m0 + */ +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3 From 5859b5a9c3ac92d831bed164374cb837519524ad Mon Sep 17 00:00:00 2001 From: Peter Geis Date: Fri, 29 Apr 2022 07:52:51 -0400 Subject: arm64: dts: rockchip: add SoQuartz CM4IO dts This is the initial SoQuartz SoM device tree on a CM4IO carrier board. This board outputs debug on uart2 and supports the following components: Gigabit Ethernet USB2 (OTG/Host shared) PCIe 2.0 x1 HDMI (HDMI Port 0) eDP (HDMI Port 1) DSI (RPi compatible pinout) CSI (RPi compatible pinout) A/B/G/N WiFi Bluetooth SDMMC eMMC SPI NOR Flash (Not placed) PI-40 compatible pin header Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-7-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 177 ++++++ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 616 +++++++++++++++++++++ 3 files changed, 794 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 1093146d33ee..107fab18cacd 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts new file mode 100644 index 000000000000..e00568a6be5c --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include "rk3566-soquartz.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board"; + compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566"; + + /* labeled +12v in schematic */ + vcc12v_dcin: vcc12v-dcin-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + /* labeled +5v in schematic */ + vcc_5v: vcc-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; +}; + +&gmac1 { + status = "okay"; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "okay"; + + /* + * the rtc interrupt is tied to PMIC_PWRON, + * it will force reset the board if triggered. + */ + pcf85063: rtc@51 { + compatible = "nxp,pcf85063"; + reg = <0x51>; + }; +}; + +/* + * i2c2 is exposed on CM1 / Module1A - to PI40 + * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A - to PI40 + * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B - to PI40 + * pin 45 - GPIO24 - i2c4_scl_m1 + * pin 47 - GPIO23 - i2c4_sda_m1 + */ +&i2c4 { + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A - to PI40 + * pin 24 - GPIO26 - i2s1_sdi1_m1 + * pin 25 - GPIO21 - i2s1_sdo0_m1 + * pin 26 - GPIO19 - i2s1_lrck_tx_m1 + * pin 27 - GPIO20 - i2s1_sdi0_m1 + * pin 29 - GPIO16 - i2s1_sdi3_m1 + * pin 30 - GPIO6 - i2s1_sdi2_m1 + * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - GPIO25 - i2s1_sdo2_m1 + * pin 49 - GPIO18 - i2s1_sclk_tx_m1 + * pin 50 - GPIO17 - i2s1_mclk_m1 + * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + status = "disabled"; +}; + +&led_diy { + status = "okay"; +}; + +&led_work { + status = "okay"; +}; + +&rgmii_phy1 { + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A - to J2 + * pin 94 - AIN1 - saradc_vin3 + * pin 96 - AIN0 - saradc_vin2 + */ +&saradc { + status = "disabled"; +}; + +&sdmmc0 { + vmmc-supply = <&sdmmc_pwr>; + status = "okay"; +}; + +&sdmmc_pwr { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A - to PI40 + * pin 37 - GPIO7 - spi3_cs1_m0 + * pin 38 - GPIO11 - spi3_clk_m0 + * pin 39 - GPIO8 - spi3_cs0_m0 + * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - GPIO10 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +/* + * uart2 is exposed on CM1 / Module1A - to PI40 + * pin 51 - GPIO15 - uart2_rx_m0 + * pin 55 - GPIO14 - uart2_tx_m0 + */ +&uart2 { + status = "okay"; +}; + +/* + * uart7 is exposed on CM1 / Module1A - to PI40 + * pin 46 - GPIO22 - uart7_tx_m2 + * pin 47 - GPIO23 - uart7_rx_m2 + */ +&uart7 { + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc_5v>; + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&vbus { + vin-supply = <&vcc_5v>; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi new file mode 100644 index 000000000000..5bcd4be32964 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi @@ -0,0 +1,616 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Pine64 RK3566 SoQuartz SOM"; + compatible = "pine64,soquartz", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led_diy: led-diy { + label = "diy-led"; + default-state = "on"; + gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&diy_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + + led_work: led-work { + label = "work-led"; + default-state = "off"; + gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&work_led_enable_h>; + retain-state-suspended; + status = "disabled"; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>; + }; + + vbus: vbus-regulator { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* sourced from vbus, vbus is provided by the carrier board */ + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vbus>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + sdmmc_pwr: sdmmc-pwr-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_pwr_h>; + regulator-name = "sdmmc_pwr"; + status = "disabled"; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_3v3>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f, also works well here */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x30>; + rx_delay = <0x10>; + phy-handle = <&rgmii_phy1>; + status = "disabled"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-name = "vcc_ddr"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-initial-mode = <0x2>; + regulator-name = "vdd_npu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_image"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda_0v9"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdda0v9_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_acodec"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc3v3_pmu"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca_1v8"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_pmu"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcca1v8_image"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-name = "vcc_3v3"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + status = "disabled"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + }; + }; +}; + +/* + * i2c1 is exposed on CM1 / Module1A + * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu + * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu + */ +&i2c1 { + status = "disabled"; +}; + +/* + * i2c2 is exposed on CM1 / Module1A + * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch + * pin 58 - i2c2_sda_m1, pullup to vcc_3v3 + */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2m1_xfer>; + status = "disabled"; +}; + +/* + * i2c3 is exposed on CM1 / Module1A + * pin 35 - i2c3_scl_m0, pullup to vcc_3v3 + * pin 36 - i2c3_sda_m0, pullup to vcc_3v3 + */ +&i2c3 { + status = "disabled"; +}; + +/* + * i2c4 is exposed on CM2 / Module1B + * pin 45 - i2c4_scl_m1 + * pin 47 - i2c4_sda_m1 + */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4m1_xfer>; + status = "disabled"; +}; + +/* + * i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 + * pin 25 - i2s1_sdo0_m1 + * pin 26 - i2s1_lrck_tx_m1 + * pin 27 - i2s1_sdi0_m1 + * pin 29 - i2s1_sdi3_m1 + * pin 30 - i2s1_sdi2_m1 + * pin 40 - i2s1_sdo1_m1, shared with spi3 + * pin 41 - i2s1_sdo2_m1 + * pin 49 - i2s1_sclk_tx_m1 + * pin 50 - i2s1_mclk_m1 + * pin 56 - i2s1_sdo3_m1, shared with i2c2 + */ +&i2s1_8ch { + pinctrl-names = "default"; + pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx + &i2s1m1_lrcktx &i2s1m1_lrckrx + &i2s1m1_sdi0 &i2s1m1_sdi1 + &i2s1m1_sdi2 &i2s1m1_sdi3 + &i2s1m1_sdo0 &i2s1m1_sdo1 + &i2s1m1_sdo2 &i2s1m1_sdo3>; + status = "disabled"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + status = "disabled"; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + work_led_enable_h: work-led-enable-h { + rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + diy_led_enable_h: diy-led-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + sdmmc-pwr { + sdmmc_pwr_h: sdmmc-pwr-h { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vcc_3v3>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; + status = "okay"; +}; + +/* + * saradc is exposed on CM1 / Module1A + * pin 94 - saradc_vin3 + * pin 96 - saradc_vin2 + */ +&saradc { + vref-supply = <&vcca_1v8>; + status = "disabled"; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + broken-cd; + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + vqmmc-supply = <&vccio_sd>; + status = "disabled"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +/* + * spi3 is exposed on CM1 / Module1A + * pin 37 - spi3_cs1_m0 + * pin 38 - spi3_clk_m0 + * pin 39 - spi3_cs0_m0 + * pin 40 - spi3_miso_m0, shared with i2s1_8ch + * pin 44 - spi3_mosi_m0 + */ +&spi3 { + status = "disabled"; +}; + +&tsadc { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +/* + * uart2 is exposed on CM1 / Module1A + * pin 51 - uart2_rx_m0 + * pin 55 - uart2_tx_m0 + */ +&uart2 { + status = "disabled"; +}; + +/* + * uart7 is exposed on CM1 / Module1A + * pin 46 - uart7_tx_m2 + * pin 47 - uart7_rx_m2 + */ +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7m2_xfer>; + status = "disabled"; +}; + +/* dwc3_otg is the only usb port available */ +&usb2phy0 { + status = "disabled"; +}; + +&usb2phy0_otg { + status = "disabled"; +}; + +&usb_host0_xhci { + status = "disabled"; +}; -- cgit v1.2.3 From 30ac9b4e25d8cece00d32c7419f9d919f55421fe Mon Sep 17 00:00:00 2001 From: Furkan Kardame Date: Fri, 29 Apr 2022 07:52:52 -0400 Subject: arm64: dts: rockchip: add dts for Firefly Station M2 rk3566 Add dts for Firefly Station M2. Working IO: * UART * LED * LAN * Wifi * SD Card * eMMC * USB2 Signed-off-by: Furkan Kardame Signed-off-by: Peter Geis Link: https://lore.kernel.org/r/20220429115252.2360496-8-pgwipeout@gmail.com Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/Makefile | 1 + arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 579 +++++++++++++++++++++++++ 2 files changed, 580 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index 107fab18cacd..18d00eae3072 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts new file mode 100644 index 000000000000..57759b66d44d --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/dts-v1/; + +#include +#include +#include "rk3566.dtsi" + +/ { + model = "Firefly Station M2"; + compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566"; + + aliases { + mmc0 = &sdmmc0; + mmc1 = &sdhci; + mmc2 = &sdmmc1; + }; + + chosen: chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac1_clkin: external-gmac1-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac1_clkin"; + #clock-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + label = "user-led"; + default-state = "on"; + gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&user_led_enable_h>; + retain-state-suspended; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + status = "okay"; + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; + }; + + usb_5v: usb-5v-regulator { + compatible = "regulator-fixed"; + regulator-name = "usb_5v"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&usb_5v>; + }; + + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb30_host: vcc5v0-usb30-host-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb30_host"; + enable-active-high; + gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb30_host_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_usb_otg"; + enable-active-high; + gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_usb_otg_en_h>; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&combphy1 { + status = "okay"; +}; + +&cpu0 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu1 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu2 { + cpu-supply = <&vdd_cpu>; +}; + +&cpu3 { + cpu-supply = <&vdd_cpu>; +}; + +&gmac1 { + assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>; + assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>; + clock_in_out = "input"; + phy-mode = "rgmii-id"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&gmac1m0_miim + &gmac1m0_tx_bus2 + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk + &gmac1m0_clkinout + &gmac1m0_rgmii_bus>; + snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + /* Reset time is 20ms, 100ms for rtl8211f */ + snps,reset-delays-us = <0 20000 100000>; + tx_delay = <0x4f>; + rx_delay = <0x24>; + phy-handle = <&rgmii_phy1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + vdd_cpu: regulator@1c { + compatible = "tcs,tcs4525"; + reg = <0x1c>; + fcs,suspend-voltage-selector = <1>; + regulator-name = "vdd_cpu"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1150000>; + regulator-ramp-delay = <2300>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc5v0_sys>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; + vcc4-supply = <&vcc3v3_sys>; + vcc5-supply = <&vcc3v3_sys>; + vcc6-supply = <&vcc3v3_sys>; + vcc7-supply = <&vcc3v3_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc3v3_sys>; + + regulators { + vdd_log: DCDC_REG1 { + regulator-name = "vdd_log"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdd_gpu: DCDC_REG2 { + regulator-name = "vdd_gpu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-init-microvolt = <900000>; + regulator-ramp-delay = <6001>; + + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_npu: DCDC_REG4 { + regulator-name = "vdd_npu"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8: DCDC_REG5 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdda0v9_image: LDO_REG1 { + regulator-name = "vdda0v9_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda_0v9: LDO_REG2 { + regulator-name = "vdda_0v9"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vdda0v9_pmu: LDO_REG3 { + regulator-name = "vdda0v9_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <900000>; + }; + }; + + vccio_acodec: LDO_REG4 { + regulator-name = "vccio_acodec"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + + }; + }; + + vccio_sd: LDO_REG5 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc3v3_pmu: LDO_REG6 { + regulator-name = "vcc3v3_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcca_1v8: LDO_REG7 { + regulator-name = "vcca_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_pmu: LDO_REG8 { + regulator-name = "vcca1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcca1v8_image: LDO_REG9 { + regulator-name = "vcca1v8_image"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_3v3: SWITCH_REG1 { + regulator-boot-on; + regulator-name = "vcc3v3"; + }; + + vcc3v3_sd: SWITCH_REG2 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m1_xfer>; + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&mdio1 { + rgmii_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + }; +}; + +&pinctrl { + bt { + bt_enable_h: bt-enable-h { + rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + bt_host_wake_l: bt-host-wake-l { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + bt_wake_l: bt-wake-l { + rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + leds { + user_led_enable_h: user-led-enable-h { + rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int: pmic_int { + rockchip,pins = + <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + sdio-pwrseq { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h { + rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; + vccio2-supply = <&vcc_1v8>; + vccio3-supply = <&vccio_sd>; + vccio4-supply = <&vcc_1v8>; + vccio5-supply = <&vcc_3v3>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_3v3>; +}; + +&sdhci { + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + cap-sd-highspeed; + cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sd>; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + mmc-pwrseq = <&sdio_pwrseq>; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcca1v8_pmu>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; + status = "okay"; +}; + +&tsadc { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; + status = "okay"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm43438-bt"; + clocks = <&rk809 1>; + clock-names = "lpo"; + device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>; + vbat-supply = <&vcc3v3_sys>; + vddio-supply = <&vcca1v8_pmu>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb2phy0_host { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0_otg { + phy-supply = <&vcc5v0_usb_otg>; + status = "okay"; +}; + +&usb2phy1_otg { + phy-supply = <&vcc5v0_usb30_host>; + status = "okay"; +}; + +&usb2phy0 { + status = "okay"; +}; + +&usb2phy1 { + status = "okay"; +}; + +&usb_host0_xhci { + status = "okay"; +}; + +&usb_host1_xhci { + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; -- cgit v1.2.3 From bd820bc5e77087a71a42c36f2660b8a35d2c01a5 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Fri, 22 Apr 2022 09:28:23 +0200 Subject: arm64: dts: rockchip: rename HDMI ref clock to 'ref' on rk3399 The reference clock for the HDMI controller has been renamed to 'ref', the previous 'vpll' name is only left for compatibility in the driver. Rename the clock to the new name. Signed-off-by: Sascha Hauer Tested-by: Michael Riesch Link: https://lore.kernel.org/r/20220422072841.2206452-7-s.hauer@pengutronix.de Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 8db8b2dba12d..fbd0346624e6 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1907,7 +1907,7 @@ <&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>, <&cru PLL_VPLL>; - clock-names = "iahb", "isfr", "cec", "grf", "vpll"; + clock-names = "iahb", "isfr", "cec", "grf", "ref"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; -- cgit v1.2.3 From 50612cf9e05d111c21e84096e50a31d0c35d5825 Mon Sep 17 00:00:00 2001 From: Harald Geyer Date: Sat, 30 Apr 2022 19:10:09 +0000 Subject: arm64: dts: allwinner: teres-i: Add GPIO port regulators Allwinner A64 SoC has separate supplies for PC, PD, PE, PG and PL. Signed-off-by: Harald Geyer Reviewed-by: Samuel Holland Signed-off-by: Jernej Skrabec Link: https://lore.kernel.org/r/20220430191009.73946-1-harald@ccbib.org --- arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts index aff0660b899c..1128030e4c25 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts @@ -197,6 +197,14 @@ status = "okay"; }; +&pio { + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dldo2>; + vcc-pe-supply = <®_aldo1>; + vcc-pf-supply = <®_dcdc1>; /* No dedicated supply-pin for this */ + vcc-pg-supply = <®_aldo2>; +}; + &pwm { status = "okay"; }; -- cgit v1.2.3 From 067bc653b85e466048914c48e46659a50a907fa6 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Thu, 14 Apr 2022 17:58:26 -0700 Subject: arm64: dts: qcom: sc7180: Remove ipa interconnect node This device node is unused now that we've removed the driver that consumed it in the kernel. Drop the unused node to save some space. Cc: Alex Elder Cc: Taniya Das Cc: Mike Tipton Cc: Georgi Djakov Signed-off-by: Stephen Boyd Acked-by: Georgi Djakov Reviewed-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220415005828.1980055-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 86175d257b1e..82fa009e540f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1421,13 +1421,6 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - ipa_virt: interconnect@1e00000 { - compatible = "qcom,sc7180-ipa-virt"; - reg = <0 0x01e00000 0 0x1000>; - #interconnect-cells = <2>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - ipa: ipa@1e40000 { compatible = "qcom,sc7180-ipa"; -- cgit v1.2.3 From 497b272759986af1aa5a25b5e903d082c67bd8f6 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Thu, 21 Apr 2022 21:26:06 +0530 Subject: arm64: dts: qcom: sc7280-idp: Configure CTS pin to bias-bus-hold for bluetooth WLAN rail was leaking power during RBSC/sleep even after turning BT off. Change active and sleep pinctrl configurations to handle same. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1650556567-4995-2-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 6a14259b93c4..5eb668991e24 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -408,10 +408,13 @@ &qup_uart7_cts { /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; &qup_uart7_rts { @@ -503,10 +506,13 @@ pins = "gpio28"; function = "gpio"; /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; qup_uart7_sleep_rts: qup-uart7-sleep-rts { -- cgit v1.2.3 From 3d0e375bae55c2dfa6dd0762f45ad71f0b192f71 Mon Sep 17 00:00:00 2001 From: Vijaya Krishna Nivarthi Date: Thu, 21 Apr 2022 21:26:07 +0530 Subject: arm64: dts: qcom: sc7280-qcard: Configure CTS pin to bias-bus-hold for bluetooth WLAN rail was leaking power during RBSC/sleep even after turning BT off. Change active and sleep pinctrl configurations to handle same. Signed-off-by: Vijaya Krishna Nivarthi Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1650556567-4995-3-git-send-email-quic_vnivarth@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index b833ba1e8f4a..98b5cd70bca5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -398,8 +398,14 @@ mos_bt_uart: &uart7 { /* For mos_bt_uart */ &qup_uart7_cts { - /* Configure a pull-down on CTS to match the pull of the Bluetooth module. */ - bias-pull-down; + /* + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. + */ + bias-bus-hold; }; /* For mos_bt_uart */ @@ -490,10 +496,13 @@ mos_bt_uart: &uart7 { pins = "gpio28"; function = "gpio"; /* - * Configure a pull-down on CTS to match the pull of - * the Bluetooth module. + * Configure a bias-bus-hold on CTS to lower power + * usage when Bluetooth is turned off. Bus hold will + * maintain a low power state regardless of whether + * the Bluetooth module drives the pin in either + * direction or leaves the pin fully unpowered. */ - bias-pull-down; + bias-bus-hold; }; /* For mos_bt_uart */ -- cgit v1.2.3 From f223095c6e1d20aac831e75016b58ca8adbbf122 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 3 May 2022 11:26:31 +0200 Subject: arm64: dts: exynos: move XTCXO clock frequency to board in Exynos Auto v9 The external oscillator - XTCXO - is an input to the SoC. It is defined in the Exynos Auto v9 SoC DTSI, because all boards will provide it and clock controller bindings expect it, however the actual frequency of the clock should be determined by the board. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Chanho Park Link: https://lore.kernel.org/r/20220503092631.174713-1-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts | 4 ++++ arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 1 - 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts index 57518cb5e8c4..17e568853eb6 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts +++ b/arch/arm64/boot/dts/exynos/exynosautov9-sadk.dts @@ -58,3 +58,7 @@ &usi_0 { status = "okay"; }; + +&xtcxo { + clock-frequency = <26000000>; +}; diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 807d500d6022..68d087ed0459 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -153,7 +153,6 @@ xtcxo: clock { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <26000000>; clock-output-names = "oscclk"; }; -- cgit v1.2.3 From 03e1d34d27a5e8065c5ef691648ee8a519e3c1b0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:19:01 +0200 Subject: arm64: dts: exynos: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-9-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 6 ------ arch/arm64/boot/dts/exynos/exynos7.dtsi | 4 ---- 2 files changed, 10 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 017ccc2f4650..75b548e495a0 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -1866,8 +1866,6 @@ clocks = <&cmu_fsys CLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@15600000 { @@ -1877,8 +1875,6 @@ clocks = <&cmu_fsys CLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; audio-subsystem@11400000 { @@ -1898,8 +1894,6 @@ clocks = <&cmu_aud CLK_ACLK_DMAC>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; power-domains = <&pd_aud>; }; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index e38bb02a2152..1cd771c90b47 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -149,8 +149,6 @@ clocks = <&clock_fsys0 ACLK_PDMA0>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; pdma1: dma-controller@10eb0000 { @@ -160,8 +158,6 @@ clocks = <&clock_fsys0 ACLK_PDMA1>; clock-names = "apb_pclk"; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; }; clock_topc: clock-controller@10570000 { -- cgit v1.2.3 From 6745dbc73112819529d776275b4e76dae5c12680 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:19:02 +0200 Subject: arm64: dts: fsd: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-10-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/tesla/fsd.dtsi | 8 -------- 1 file changed, 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 10c217a57a7d..af39655331de 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -432,8 +432,6 @@ reg = <0x0 0x10100000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_imem 0x800 0x0>; @@ -444,8 +442,6 @@ reg = <0x0 0x10110000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_imem 0x801 0x0>; @@ -456,8 +452,6 @@ reg = <0x0 0x14280000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_peric 0x2 0x0>; @@ -468,8 +462,6 @@ reg = <0x0 0x14290000 0x0 0x1000>; interrupts = ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; clock-names = "apb_pclk"; iommus = <&smmu_peric 0x1 0x0>; -- cgit v1.2.3 From a93fbb002310ef04fce504dbf1510f6eb8265188 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:56 +0200 Subject: arm64: dts: stratix10/agilex: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-4-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 -- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 884bda106399..aa2bba75265f 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -346,8 +346,6 @@ <0 88 4>, <0 89 4>; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index c78371703e76..caccb0334ada 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -350,8 +350,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; reset-names = "dma", "dma-ocp"; clocks = <&clkmgr AGILEX_L4_MAIN_CLK>; -- cgit v1.2.3 From 8dba791a7280542bc125b68b3547bfa2680bc1af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Apr 2022 14:18:58 +0200 Subject: arm64: dts: broadcom: drop useless 'dma-channels/requests' properties The pl330 DMA controller provides number of DMA channels and requests through its registers, so duplicating this information (with a chance of mistakes) in DTS is pointless. Additionally the DTS used always wrong property names which causes DT schema check failures - the bindings documented 'dma-channels' and 'dma-requests' properties without leading hash sign. Reported-by: Rob Herring Suggested-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220430121902.59895-6-krzysztof.kozlowski@linaro.org --- arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 2 -- arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 2 -- 2 files changed, 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index f59fa3979a04..fda97c47f4e9 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -289,8 +289,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&iprocslow>; clock-names = "apb_pclk"; }; diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi index 7f1b8efd0883..09d4aa8ae1d6 100644 --- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi +++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi @@ -556,8 +556,6 @@ , ; #dma-cells = <1>; - #dma-channels = <8>; - #dma-requests = <32>; clocks = <&hsls_div2_clk>; clock-names = "apb_pclk"; iommus = <&smmu 0x6000 0x0000>; -- cgit v1.2.3 From 0017f2c856e21bb900be88469e15dac4f41f4065 Mon Sep 17 00:00:00 2001 From: Diogo Ivo Date: Fri, 29 Apr 2022 13:58:43 +0100 Subject: arm64: tegra: Add missing DFLL reset on Tegra210 Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. In order to be able to fix this, add the corresponding reset to the DT. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 218a2b32200f..4f0e51f1a343 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1366,8 +1366,9 @@ <&tegra_car TEGRA210_CLK_DFLL_REF>, <&tegra_car TEGRA210_CLK_I2C5>; clock-names = "soc", "ref", "i2c"; - resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; - reset-names = "dvco"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, + <&tegra_car 155>; + reset-names = "dvco", "dfll"; #clock-cells = <0>; clock-output-names = "dfllCPU_out"; status = "disabled"; -- cgit v1.2.3 From 5be66d2dc8873edcf215804067b1c076b00c6887 Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Tue, 22 Feb 2022 11:25:08 +0530 Subject: arm64: dts: qcom: pm8350c: Add pwm support Add pwm support for PM8350C pmic. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645509309-16142-4-git-send-email-quic_c_skakit@quicinc.com --- arch/arm64/boot/dts/qcom/pm8350c.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/pm8350c.dtsi b/arch/arm64/boot/dts/qcom/pm8350c.dtsi index 9bc6464477bd..e0bbb67717fe 100644 --- a/arch/arm64/boot/dts/qcom/pm8350c.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350c.dtsi @@ -29,6 +29,13 @@ interrupt-controller; #interrupt-cells = <2>; }; + + pm8350c_pwm: pwm@e800 { + compatible = "qcom,pm8350c-pwm"; + reg = <0xe800>; + #pwm-cells = <2>; + status = "disabled"; + }; }; }; -- cgit v1.2.3 From 82096cc644098ab610e6df5238341907ea662164 Mon Sep 17 00:00:00 2001 From: Satya Priya Date: Tue, 22 Feb 2022 11:25:09 +0530 Subject: arm64: dts: qcom: Enable pm8350c pwm for sc7280-idp2 Enable pm8350c pmic pwm support for backlight on sc7280-idp2. Signed-off-by: Satya Priya Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1645509309-16142-5-git-send-email-quic_c_skakit@quicinc.com --- arch/arm64/boot/dts/qcom/sc7280-idp2.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts index 73b9911dd802..d4f7cab17078 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp2.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp2.dts @@ -34,3 +34,7 @@ &nvme_3v3_regulator { gpio = <&tlmm 51 GPIO_ACTIVE_HIGH>; }; + +&pm8350c_pwm { + status = "okay"; +}; -- cgit v1.2.3 From aadc48f7c4ecd11b4fba7ba7d5ed1788ce32bb78 Mon Sep 17 00:00:00 2001 From: Katherine Perez Date: Tue, 7 Dec 2021 15:17:36 -0800 Subject: arm64: dts: qcom: sm8350-duo2: enable battery charger Enable the relevant qup and I2C nodes to enable the battery charger. Signed-off-by: Katherine Perez Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211207231736.1762503-2-kaperez@linux.microsoft.com --- arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts index 9cb1d8455fd0..9a6faa9393dc 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-microsoft-surface-duo2.dts @@ -281,6 +281,14 @@ firmware-name = "qcom/sm8350/microsoft/cdsp.mbn"; }; +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; +}; + &ipa { status = "okay"; @@ -296,6 +304,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &slpi { status = "okay"; firmware-name = "qcom/sm8350/microsoft/slpi.mbn"; -- cgit v1.2.3 From fefbc0021940a1da023eeff7634341841a048acf Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:14 -0500 Subject: arm64: dts: remove "simple-bus" compatible from ifc node The binding of ifc device has been updated. Update dts to match accordingly. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 35d1939e690b..e0dc64452569 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -390,7 +390,7 @@ }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <0 43 0x4>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 4e7bd04d9798..6a51f33b382b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -281,7 +281,7 @@ }; ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 18e529118476..5578078c64d2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -397,7 +397,7 @@ }; ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; little-endian; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 1282b61da8a5..eb63117b44fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1037,7 +1037,7 @@ }; ifc: ifc@2240000 { - compatible = "fsl,ifc", "simple-bus"; + compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 0x4>; /* Level high type */ little-endian; -- cgit v1.2.3 From e55264f3d7581e8a352ef734109edede7e7befbb Mon Sep 17 00:00:00 2001 From: Li Yang Date: Mon, 21 Mar 2022 21:28:17 -0500 Subject: arm64: dts: freescale: update ifc node name to be memory-controller Update the node name to be align with updated DT binding. But be noted that u-boot for ls1088a used the ifc node name to disable ifc-nor node when the SoC is configured to use QSPI. The u-boot has been updated to use the latest name but the change could break compatibility with older u-boot for ls1088a. Signed-off-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index e0dc64452569..0c9c9edeb9ff 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -389,7 +389,7 @@ big-endian; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <0 43 0x4>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 6a51f33b382b..9d53730b956b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -280,7 +280,7 @@ big-endian; }; - ifc: ifc@1530000 { + ifc: memory-controller@1530000 { compatible = "fsl,ifc"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = ; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 5578078c64d2..80bf1e672e5c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -396,7 +396,7 @@ #interrupt-cells = <2>; }; - ifc: ifc@2240000 { + ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index eb63117b44fb..202650a4a91c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -1036,7 +1036,7 @@ QORIQ_CLK_PLL_DIV(4)>; }; - ifc: ifc@2240000 { + ifc: memory-controller@2240000 { compatible = "fsl,ifc"; reg = <0x0 0x2240000 0x0 0x20000>; interrupts = <0 21 0x4>; /* Level high type */ -- cgit v1.2.3 From eefe06b295087caa24340888b9465d7dc61df856 Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:23 +0530 Subject: arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. General features: - NXP i.MX8M Plus - Up to 4GB LDDR4 - 8 eMMC - Gigabit Ethernet - USB 3.0, 2.0 Host/OTG - PCIe 3.0 interface - I2S - LVDS - rest of i.MX8M Plus features i.Core MX8M Plus needs to mount on top of Engicam baseboards for creating complete platform solutions. Add support for it. Signed-off-by: Manoj Sai Signed-off-by: Matteo Lisi Reviewed-by: Jagan Teki Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 186 +++++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi new file mode 100644 index 000000000000..5116079cce22 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi @@ -0,0 +1,186 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/ { + compatible = "engicam,icore-mx8mp", "fsl,imx8mp"; +}; + +&A53_0 { + cpu-supply = <&buck2>; +}; + +&A53_1 { + cpu-supply = <&buck2>; +}; + +&A53_2 { + cpu-supply = <&buck2>; +}; + +&A53_3 { + cpu-supply = <&buck2>; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450c"; + interrupt-parent = <&gpio3>; + interrupts = <1 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x25>; + + regulators { + buck1: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1000000>; + regulator-name = "BUCK1"; + regulator-ramp-delay = <3125>; + }; + + buck2: BUCK2 { + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1025000>; + regulator-min-microvolt = <720000>; + regulator-name = "BUCK2"; + regulator-ramp-delay = <3125>; + }; + + buck4: BUCK4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3600000>; + regulator-min-microvolt = <3000000>; + regulator-name = "BUCK4"; + }; + + buck5: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "BUCK5"; + }; + + buck6: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1155000>; + regulator-min-microvolt = <1045000>; + regulator-name = "BUCK6"; + }; + + ldo1: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1950000>; + regulator-min-microvolt = <1650000>; + regulator-name = "LDO1"; + }; + + ldo3: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1890000>; + regulator-min-microvolt = <1710000>; + regulator-name = "LDO3"; + }; + + ldo5: LDO5 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "LDO5"; + }; + }; + }; +}; + +/* EMMC */ +&usdhc3 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; +}; -- cgit v1.2.3 From aec8ad34f7f248381288919f4fc1315e8abad90d Mon Sep 17 00:00:00 2001 From: Manoj Sai Date: Mon, 25 Apr 2022 19:12:24 +0530 Subject: arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit Genaral features: - LCD 7" C.Touch - microSD slot - Ethernet 1Gb - Wifi/BT - 2x LVDS Full HD interfaces - 3x USB 2.0 - 1x USB 3.0 - HDMI Out - Plus PCIe - MIPI CSI - 2x CAN - Audio Out i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Manoj Sai Signed-off-by: Matteo Lisi Reviewed-by: Jagan Teki Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts | 175 +++++++++++++++++++++ 2 files changed, 176 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index cdf9dfcbe020..238a83e5b8c6 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -80,6 +80,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts new file mode 100644 index 000000000000..70a701a624a6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 NXP + * Copyright (c) 2019 Engicam srl + * Copyright (c) 2020 Amarula Solutons(India) + */ + +/dts-v1/; + +#include "imx8mp.dtsi" +#include "imx8mp-icore-mx8mp.dtsi" +#include + +/ { + model = "Engicam i.Core MX8M Plus EDIMM2.2 Starter Kit"; + compatible = "engicam,icore-mx8mp-edimm2.2", "engicam,icore-mx8mp", + "fsl,imx8mp"; + + chosen { + stdout-path = &uart2; + }; + + reg_usb1_vbus: regulator-usb1 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +/* Ethernet */ +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-handle = <ðphy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* console */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* SDCARD */ +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + pinctrl-names = "default" ; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 + MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 + MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 + MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x140 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + >; + }; + + pinctrl_reg_usb1: regusb1grp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 + >; + }; +}; -- cgit v1.2.3 From 2ae42e0c0b67d155cdac1f801f59ac3290650442 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Apr 2022 17:33:59 +0200 Subject: arm64: dts: imx8mp: add HSIO power-domains This adds the GPC and HSIO blk-ctrl nodes providing power control for the high-speed (USB and PCIe) IOs. Signed-off-by: Lucas Stach Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 57 +++++++++++++++++++++++++++---- 1 file changed, 51 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 7ad824e6b820..3a59ce27e312 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -523,6 +523,21 @@ #address-cells = <1>; #size-cells = <0>; + pgc_pcie_phy: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb1_phy: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_usb2_phy: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_gpu2d: power-domain@6 { #power-domain-cells = <0>; reg = ; @@ -549,6 +564,16 @@ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; power-domains = <&pgc_gpumix>; }; + + pgc_hsiomix: power-domains@17 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_HSIO_AXI>, + <&clk IMX8MP_CLK_HSIO_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + }; }; }; }; @@ -970,6 +995,28 @@ }; }; + aips4: bus@32c00000 { + compatible = "fsl,aips-bus", "simple-bus"; + reg = <0x32c00000 0x400000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + hsio_blk_ctrl: blk-ctrl@32f10000 { + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; + reg = <0x32f10000 0x24>; + clocks = <&clk IMX8MP_CLK_USB_ROOT>, + <&clk IMX8MP_CLK_PCIE_ROOT>; + clock-names = "usb", "pcie"; + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, + <&pgc_usb1_phy>, <&pgc_usb2_phy>, + <&pgc_hsiomix>, <&pgc_pcie_phy>; + power-domain-names = "bus", "usb", "usb-phy1", + "usb-phy2", "pcie", "pcie-phy"; + #power-domain-cells = <1>; + }; + }; + gpu3d: gpu@38000000 { compatible = "vivante,gc"; reg = <0x38000000 0x8000>; @@ -1030,6 +1077,7 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; #phy-cells = <0>; status = "disabled"; }; @@ -1042,6 +1090,7 @@ <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -1055,9 +1104,6 @@ <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; @@ -1073,6 +1119,7 @@ clock-names = "phy"; assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; #phy-cells = <0>; status = "disabled"; }; @@ -1085,6 +1132,7 @@ <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "hsio", "suspend"; interrupts = ; + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; #address-cells = <1>; #size-cells = <1>; dma-ranges = <0x40000000 0x40000000 0xc0000000>; @@ -1098,9 +1146,6 @@ <&clk IMX8MP_CLK_USB_CORE_REF>, <&clk IMX8MP_CLK_USB_ROOT>; clock-names = "bus_early", "ref", "suspend"; - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; - assigned-clock-rates = <500000000>; interrupts = ; phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; -- cgit v1.2.3 From 9d89189d5227507a05a6029818e1a2e2b074522a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Wed, 6 Apr 2022 17:34:00 +0200 Subject: arm64: dts: imx8mp: Add MEDIAMIX power domains Add the power domains related to the MEDIAMIX to the GPC. Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 3a59ce27e312..a0b4957f7a16 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -523,6 +523,11 @@ #address-cells = <1>; #size-cells = <0>; + pgc_mipi_phy1: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = ; @@ -565,6 +570,18 @@ power-domains = <&pgc_gpumix>; }; + pgc_mediamix: power-domain@10 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + }; + + pgc_mipi_phy2: power-domain@16 { + #power-domain-cells = <0>; + reg = ; + }; + pgc_hsiomix: power-domains@17 { #power-domain-cells = <0>; reg = ; @@ -574,6 +591,12 @@ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; assigned-clock-rates = <500000000>; }; + + pgc_ispdwp: power-domain@18 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; + }; }; }; }; -- cgit v1.2.3 From 29f440a7bda8df98c595f6ac29cd196fa1df394a Mon Sep 17 00:00:00 2001 From: Paul Elder Date: Wed, 6 Apr 2022 17:34:01 +0200 Subject: arm64: dts: imx8mp: Add MEDIA_BLK_CTRL Add a DT node for the MEDIA_BLK_CTRL, which provides power domains for the camera and display devices. Signed-off-by: Paul Elder Signed-off-by: Laurent Pinchart Reviewed-by: Marek Vasut Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index a0b4957f7a16..ed75bd30d9af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1025,6 +1025,44 @@ #size-cells = <1>; ranges; + media_blk_ctrl: blk-ctrl@32ec0000 { + compatible = "fsl,imx8mp-media-blk-ctrl", + "syscon"; + reg = <0x32ec0000 0x10000>; + power-domains = <&pgc_mediamix>, + <&pgc_mipi_phy1>, + <&pgc_mipi_phy1>, + <&pgc_mediamix>, + <&pgc_mediamix>, + <&pgc_mipi_phy2>, + <&pgc_mediamix>, + <&pgc_ispdwp>, + <&pgc_ispdwp>, + <&pgc_mipi_phy2>; + power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", + "lcdif1", "isi", "mipi-csi2", + "lcdif2", "isp", "dwe", + "mipi-dsi2"; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, + <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, + <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, + <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; + clock-names = "apb", "axi", "cam1", "cam2", + "disp1", "disp2", "isp", "phy"; + + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, + <&clk IMX8MP_CLK_MEDIA_APB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + + #power-domain-cells = <1>; + }; + hsio_blk_ctrl: blk-ctrl@32f10000 { compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; reg = <0x32f10000 0x24>; -- cgit v1.2.3 From 83b41ad1dca61ede1c261aa788fe643b746fb546 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:19:16 -0300 Subject: arm64: dts: imx8mp-verdin: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Marcel Ziswiler Signed-off-by: Fabio Estevam Acked-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi index 34d9bc48c899..36289c175e6e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -61,7 +61,7 @@ /* On-module Bluetooth */ &uart4 { - fsl,uart-has-rtscts; + uart-has-rtscts; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_bt_uart>; status = "okay"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index aa6442be130e..fb17e329cd37 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -760,14 +760,14 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - fsl,uart-has-rtscts; + uart-has-rtscts; }; /* Verdin UART_2 */ &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; - fsl,uart-has-rtscts; + uart-has-rtscts; }; /* Verdin UART_3, used as the Linux Console */ -- cgit v1.2.3 From dab98061d71891a506c3ae2766fd23c07b65f6d3 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 21 Apr 2022 22:19:17 -0300 Subject: arm64: dts: imx8mq-kontron-pitx-imx8m: Use the standard 'uart-has-rtscts' The usage of the 'fsl,uart-has-rtscts' property is deprecated. Use the standard 'uart-has-rtscts' instead. Cc: Heiko Thiery Signed-off-by: Fabio Estevam Acked-By: Heiko Thiery Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index 564746d5000d..a91c136797f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -311,7 +311,7 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; - fsl,uart-has-rtscts; + uart-has-rtscts; assigned-clocks = <&clk IMX8MQ_CLK_UART3>; assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; status = "okay"; -- cgit v1.2.3 From 13e4e43a1934d22e27a4553cb219133ef9583954 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 21:59:01 +0200 Subject: arm64: dts: imx8mm: Add CPLD on MX8Menlo board The CPLD on MX8Menlo board is used to operate custom hardware, the CPLD content is compatible with previous M53Menlo CPLD, add the bindings. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Marcel Ziswiler Cc: Peng Fan Cc: Rob Herring Cc: Shawn Guo Cc: NXP Linux Team Cc: devicetree@vger.kernel.org To: linux-arm-kernel@lists.infradead.org Reviewed-by: Marcel Ziswiler Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts index c20db0c550da..92eaf4ef4563 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-mx8menlo.dts @@ -71,7 +71,20 @@ &ecspi2 { pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>; cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>; - status = "disabled"; + status = "okay"; + + spidev@0 { + compatible = "menlo,m53cpld"; + reg = <0>; + spi-max-frequency = <25000000>; + }; + + spidev@1 { + compatible = "menlo,m53cpld"; + reg = <1>; + spi-max-frequency = <25000000>; + }; + }; ðphy0 { -- cgit v1.2.3 From 13305aa53692700a7d2ed2a7ad47965650d8be7b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 22:02:47 +0200 Subject: arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC The USB2 port has USB Hub permanently connected to it, disable OC to avoid getting false OC indication. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 154116d01c94..b2d90b79f500 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -962,6 +962,7 @@ }; &usbotg2 { + disable-over-current; dr_mode = "host"; status = "okay"; }; -- cgit v1.2.3 From 42c1a6f62e5c46269ed37238f6a5331b30c32c75 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 26 Apr 2022 22:03:29 +0200 Subject: arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz to guarantee this I2C device can work correctly. Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC") Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Peng Fan Cc: Shawn Guo Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index b2d90b79f500..8c9dd09dbc74 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -392,7 +392,7 @@ &i2c2 { /* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */ - clock-frequency = <320000>; + clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; pinctrl-1 = <&pinctrl_i2c2_gpio>; -- cgit v1.2.3 From 4ce01ce36d77137cf60776b320babed89de6bd4c Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 26 Apr 2022 15:51:43 -0500 Subject: arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3 There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index ec3f2c177035..f338a886d811 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -278,6 +278,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MM_CLK_UART3>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -386,6 +387,8 @@ fsl,pins = < MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; -- cgit v1.2.3 From 5446ff1a67160ad92d9aae9530846aa54750be36 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 26 Apr 2022 15:51:44 -0500 Subject: arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3 There is a header for a DB9 serial port, but any attempts to use hardware handshaking fail. Enable RTS and CTS pin muxing and enable handshaking in the uart node. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi | 3 +++ 1 file changed, 3 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 0f40b43ac091..02f37dcda7ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -175,6 +175,7 @@ pinctrl-0 = <&pinctrl_uart3>; assigned-clocks = <&clk IMX8MN_CLK_UART3>; assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>; + uart-has-rtscts; status = "okay"; }; @@ -258,6 +259,8 @@ fsl,pins = < MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40 + MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40 + MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40 >; }; -- cgit v1.2.3 From 339c8beae89b0435610b363df378abe10a486542 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 27 Apr 2022 09:53:36 +0200 Subject: arm64: dts: freescale: reduce the interrup-map-mask Reduce the interrupt-map-mask of the external interrupt controller to 0xf to align with the devicetree schema. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 2 +- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 0c9c9edeb9ff..21200cbf7161 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -335,7 +335,7 @@ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 9d53730b956b..0085e83adf65 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -341,7 +341,7 @@ <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 80bf1e672e5c..f476b7d8b056 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -265,7 +265,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 202650a4a91c..4ba1e0499dfd 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -305,7 +305,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index 82bd8c0f318b..47ea854720ce 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -698,7 +698,7 @@ <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-map-mask = <0xffffffff 0x0>; + interrupt-map-mask = <0xf 0x0>; }; }; -- cgit v1.2.3 From bf198e2e919ed551794d6eec3fe52e2d1693f0eb Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:13:47 -0700 Subject: arm64: dts: imx8mm-venice-gw7902: fix pcie bindings Update the pcie bindings to the correct dt bindings: pcie_phy: - use pcie0_refclk - add required clock-names pcie: - remove pcie_phy clock as it comes from phy driver Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 1b03aa154688..f0eccc5b810d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -595,7 +595,8 @@ &pcie_phy { fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; - clocks = <&clk IMX8MM_CLK_DUMMY>; + clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; @@ -604,8 +605,8 @@ pinctrl-0 = <&pinctrl_pcie0>; reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, - <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>; - clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + <&pcie0_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_bus"; assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-rates = <10000000>, <250000000>; -- cgit v1.2.3 From 5394461a31c9d1c6a0452a0312f941e0b4d08d74 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:52 +0900 Subject: arm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9 Add cmu_top, cmu_busmc, cmu_core, cmu_fsys and peric0/c1/s clock nodes. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-11-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 84 ++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 68d087ed0459..499b9ce3bee1 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -6,6 +6,7 @@ * */ +#include #include #include @@ -189,6 +190,89 @@ reg = <0x10000000 0x24>; }; + cmu_peris: clock-controller@10020000 { + compatible = "samsung,exynosautov9-cmu-peris"; + reg = <0x10020000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIS_BUS>; + clock-names = "oscclk", + "dout_clkcmu_peris_bus"; + }; + + cmu_peric0: clock-controller@10200000 { + compatible = "samsung,exynosautov9-cmu-peric0"; + reg = <0x10200000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC0_BUS>, + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; + clock-names = "oscclk", + "dout_clkcmu_peric0_bus", + "dout_clkcmu_peric0_ip"; + }; + + cmu_peric1: clock-controller@10800000 { + compatible = "samsung,exynosautov9-cmu-peric1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_PERIC1_BUS>, + <&cmu_top DOUT_CLKCMU_PERIC1_IP>; + clock-names = "oscclk", + "dout_clkcmu_peric1_bus", + "dout_clkcmu_peric1_ip"; + }; + + cmu_fsys2: clock-controller@17c00000 { + compatible = "samsung,exynosautov9-cmu-fsys2"; + reg = <0x17c00000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_FSYS2_BUS>, + <&cmu_top DOUT_CLKCMU_FSYS2_UFS_EMBD>, + <&cmu_top DOUT_CLKCMU_FSYS2_ETHERNET>; + clock-names = "oscclk", + "dout_clkcmu_fsys2_bus", + "dout_fsys2_clkcmu_ufs_embd", + "dout_fsys2_clkcmu_ethernet"; + }; + + cmu_core: clock-controller@1b030000 { + compatible = "samsung,exynosautov9-cmu-core"; + reg = <0x1b030000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_CORE_BUS>; + clock-names = "oscclk", + "dout_clkcmu_core_bus"; + }; + + cmu_busmc: clock-controller@1b200000 { + compatible = "samsung,exynosautov9-cmu-busmc"; + reg = <0x1b200000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>, + <&cmu_top DOUT_CLKCMU_BUSMC_BUS>; + clock-names = "oscclk", + "dout_clkcmu_busmc_bus"; + }; + + cmu_top: clock-controller@1b240000 { + compatible = "samsung,exynosautov9-cmu-top"; + reg = <0x1b240000 0x8000>; + #clock-cells = <1>; + + clocks = <&xtcxo>; + clock-names = "oscclk"; + }; + gic: interrupt-controller@10101000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit v1.2.3 From 4c882968d434c9968f53fbefa3ba6e64ff33d6a0 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:53 +0900 Subject: arm64: dts: exynos: switch USI clocks in ExynosAutov9 Use CMU clock nodes instead of dummy fixed-rate-clock. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-12-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index 499b9ce3bee1..bb1c7f43b5db 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -157,17 +157,6 @@ clock-output-names = "oscclk"; }; - /* - * Keep the stub clock for serial driver, until proper clock - * driver is implemented. - */ - uart_clock: uart-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <133250000>; - clock-output-names = "uart"; - }; - /* * Keep the stub clock for ufs driver, until proper clock * driver is implemented. @@ -354,7 +343,8 @@ #address-cells = <1>; #size-cells = <1>; ranges; - clocks = <&uart_clock>, <&uart_clock>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "pclk", "ipclk"; status = "disabled"; @@ -365,7 +355,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart0_bus_dual>; - clocks = <&uart_clock>, <&uart_clock>; + clocks = <&cmu_peric0 CLK_GOUT_PERIC0_PCLK_0>, + <&cmu_peric0 CLK_GOUT_PERIC0_IPCLK_0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; -- cgit v1.2.3 From 9882948322874b1ffdd559e6887397de4c903440 Mon Sep 17 00:00:00 2001 From: Chanho Park Date: Wed, 4 May 2022 16:51:54 +0900 Subject: arm64: dts: exynos: switch UFS clock node in ExynosAutov9 Use cmu_fsys's clock node instead of dummy UFS clock node. Signed-off-by: Chanho Park Reviewed-by: Chanwoo Choi Link: https://lore.kernel.org/r/20220504075154.58819-13-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi index bb1c7f43b5db..0ce46ec5cdc3 100644 --- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi +++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi @@ -156,16 +156,6 @@ #clock-cells = <0>; clock-output-names = "oscclk"; }; - - /* - * Keep the stub clock for ufs driver, until proper clock - * driver is implemented. - */ - ufs_core_clock: ufs-core-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <166562500>; - }; }; soc: soc@0 { @@ -382,8 +372,8 @@ <0x17dc0000 0x2200>; /* 3: UFS protector */ reg-names = "hci", "vs_hci", "unipro", "ufsp"; interrupts = ; - clocks = <&ufs_core_clock>, - <&ufs_core_clock>; + clocks = <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_ACLK>, + <&cmu_fsys2 CLK_GOUT_FSYS2_UFS_EMBD0_UNIPRO>; clock-names = "core_clk", "sclk_unipro_main"; freq-table-hz = <0 0>, <0 0>; pinctrl-names = "default"; -- cgit v1.2.3 From 450cec4f7d78fb2e04e3f7f5360e62f4837a4b68 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:16:29 -0700 Subject: arm64: dts: imx8m*venice: add missing clock-names to pcie_phy Define the missing clock-names property for the pcie_phy required by the fsl,imx8-pcie-phy dt bindings. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 1 + arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts | 1 + 5 files changed, 5 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 73addc0b8e57..337f2600a276 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -112,6 +112,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 1e7badb2a82e..8b0ef3fa543f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -134,6 +134,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 7a5d45e80982..2561b8b3fb11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -154,6 +154,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 70b2ae55e906..157ade01626e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -678,6 +678,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 1deb2ea8fcc9..a7dae9bd4c11 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -540,6 +540,7 @@ fsl,refclk-pad-mode = ; fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; + clock-names = "ref"; status = "okay"; }; -- cgit v1.2.3 From dd6fa8604301248935b0cf15b8ff6352dc5f7637 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:19:44 -0700 Subject: arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel Add missing vdd_5p0 ADC channel for the GW7902 boards. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 7 +++++++ arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 7 +++++++ 2 files changed, 14 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index f0eccc5b810d..407ab4592b4c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -394,6 +394,13 @@ gw,voltage-divider-ohms = <10000 10000>; }; + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 2c1f591335ad..367a232675aa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -393,6 +393,13 @@ gw,voltage-divider-ohms = <10000 10000>; }; + channel@9c { + gw,mode = <2>; + reg = <0x9c>; + label = "vdd_5p0"; + gw,voltage-divider-ohms = <10000 10000>; + }; + channel@a2 { gw,mode = <2>; reg = <0xa2>; -- cgit v1.2.3 From 22463f7cd0e17c4b60a0d8ad6c10f62c76840344 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 29 Apr 2022 09:20:30 -0700 Subject: arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override Remove the unnecessary cpu_alert0 and cpu_crit0 TMU node overrides as these are added dynamically by boot firmware based on CPU temperature grade. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index 157ade01626e..24737e89038a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -1091,15 +1091,3 @@ >; }; }; - -&cpu_alert0 { - temperature = <95000>; - hysteresis = <2000>; - type = "passive"; -}; - -&cpu_crit0 { - temperature = <105000>; - hysteresis = <2000>; - type = "critical"; -}; -- cgit v1.2.3 From 15ca3f00a1e3a56811371a63bf0c067603226eae Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:48:58 +0200 Subject: arm64: dt: imx8mq: support pwm polarity inversion The i.MX8MQ has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts index 622f3787a186..b86f188a440d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts @@ -18,7 +18,7 @@ backlight_dsi: backlight-dsi { compatible = "pwm-backlight"; /* 200 Hz for the PAM2841 */ - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 100>; num-interpolated-steps = <100>; /* Default brightness level (index into the array defined by */ diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 94a13cb500e6..8956a46788fa 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -18,7 +18,7 @@ compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_backlight>; - pwms = <&pwm2 0 10000>; + pwms = <&pwm2 0 10000 0>; power-supply = <®_main_usb>; enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; brightness-levels = <0 32 64 128 160 200 255>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 1eca2b431467..49eadb081b19 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -798,7 +798,7 @@ clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, <&clk IMX8MQ_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -809,7 +809,7 @@ clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, <&clk IMX8MQ_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -820,7 +820,7 @@ clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, <&clk IMX8MQ_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -831,7 +831,7 @@ clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, <&clk IMX8MQ_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; -- cgit v1.2.3 From 957aef026c462f27419082c61cd170f6e2d5c833 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:48:59 +0200 Subject: arm64: dt: imx8mm: support pwm polarity inversion The i.MX8M Mini has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells and correct board device trees. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts | 2 +- arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++---- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts index 8c9dd09dbc74..778bdbe228d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-data-modul-edm-sbc.dts @@ -35,7 +35,7 @@ brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>; default-brightness-level = <7>; enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; /* Disabled by default, unless display board plugged in. */ status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index 6a209395452a..c42b966f7a64 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -61,7 +61,7 @@ backlight: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; + pwms = <&pwm1 0 5000000 0>; brightness-levels = <0 255>; num-interpolated-steps = <255>; default-brightness-level = <250>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 1ee05677c2dd..1bf070473829 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -758,7 +758,7 @@ clocks = <&clk IMX8MM_CLK_PWM1_ROOT>, <&clk IMX8MM_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -769,7 +769,7 @@ clocks = <&clk IMX8MM_CLK_PWM2_ROOT>, <&clk IMX8MM_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -780,7 +780,7 @@ clocks = <&clk IMX8MM_CLK_PWM3_ROOT>, <&clk IMX8MM_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -791,7 +791,7 @@ clocks = <&clk IMX8MM_CLK_PWM4_ROOT>, <&clk IMX8MM_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; -- cgit v1.2.3 From 6bc1e58055c1ea3ff31335637f62a1b77da5633d Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:49:00 +0200 Subject: arm64: dt: imx8mn: support pwm polarity inversion The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mn.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index 13c51363cc06..176abe8fe659 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -705,7 +705,7 @@ clocks = <&clk IMX8MN_CLK_PWM1_ROOT>, <&clk IMX8MN_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -716,7 +716,7 @@ clocks = <&clk IMX8MN_CLK_PWM2_ROOT>, <&clk IMX8MN_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -727,7 +727,7 @@ clocks = <&clk IMX8MN_CLK_PWM3_ROOT>, <&clk IMX8MN_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -738,7 +738,7 @@ clocks = <&clk IMX8MN_CLK_PWM4_ROOT>, <&clk IMX8MN_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; -- cgit v1.2.3 From d80b9c8422fa8e02b9a92b90fbb328e3e069c649 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 2 May 2022 11:49:01 +0200 Subject: arm64: dt: imx8mp: support pwm polarity inversion The i.MX8M Plus has the same PWM IP as i.MX6 / i.MX7. This IP and the driver supporting pwm polarity inversion. Switch CPU device tree fragment to use 3 pwm-cells. Tested on MBa8MPxL mainboard. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index ed75bd30d9af..d9542dfff83f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -615,7 +615,7 @@ clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, <&clk IMX8MP_CLK_PWM1_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -626,7 +626,7 @@ clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, <&clk IMX8MP_CLK_PWM2_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -637,7 +637,7 @@ clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, <&clk IMX8MP_CLK_PWM3_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; @@ -648,7 +648,7 @@ clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, <&clk IMX8MP_CLK_PWM4_ROOT>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; status = "disabled"; }; -- cgit v1.2.3 From 92c996f4ceabd5780bb7678138267db0a1e1a00e Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 29 Apr 2022 16:56:38 +0530 Subject: arm64: dts: ti: k3-j721e-*: add DP & DP PHY Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. Also add the required phy link nodes in the board dts files. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220429112639.13004-2-r-ravikumar@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 16 +++++ arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 75 +++++++++++++++++++++- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 16 +++++ 3 files changed, 105 insertions(+), 2 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index f5ca8e26ed99..2f119e94e783 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -793,6 +793,22 @@ }; }; +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; +}; + &pcie0_rc { reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index db0669985e42..43b6cf5791ee 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -5,6 +5,7 @@ * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ */ #include +#include #include #include @@ -789,6 +790,47 @@ #size-cells = <2>; }; + serdes_wiz4: wiz@5050000 { + compatible = "ti,am64-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 297 9>; + assigned-clock-parents = <&k3_clks 297 10>; + assigned-clock-rates = <19200000>; + num-lanes = <4>; + #reset-cells = <1>; + #clock-cells = <1>; + ranges = <0x05050000 0x00 0x05050000 0x010000>, + <0x0a030a00 0x00 0x0a030a00 0x40>; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x05050000 0x010000>, + <0x0a030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy", "dptx_phy"; + + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>; + clock-names = "refclk"; + assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>, + <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>, + <&serdes_wiz4 TI_WIZ_REFCLK_DIG>; + assigned-clock-parents = <&k3_clks 297 9>, + <&k3_clks 297 9>, + <&k3_clks 297 9>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -1267,6 +1309,37 @@ }; }; + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 151 36>; + + interrupt-parent = <&gic500>; + interrupts = ; + + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = @@ -1317,8 +1390,6 @@ "common_s2"; dss_ports: ports { - #address-cells = <1>; - #size-cells = <0>; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index f25d85169e0d..98177a20b45f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -624,6 +624,22 @@ }; }; +&serdes4 { + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = ; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; +}; + +&mhdp { + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; +}; + &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; -- cgit v1.2.3 From 8f984f60f2f1fa109f9ae8c9194b6989f6675c1d Mon Sep 17 00:00:00 2001 From: Tomi Valkeinen Date: Fri, 29 Apr 2022 16:56:39 +0530 Subject: arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required pinmux nodes for hotplug. Signed-off-by: Tomi Valkeinen Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220429112639.13004-3-r-ravikumar@ti.com --- .../boot/dts/ti/k3-j721e-common-proc-board.dts | 61 ++++++++++++++++++++-- 1 file changed, 57 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2f119e94e783..2bc26a296496 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -148,6 +148,28 @@ pinctrl-0 = <&main_mcan2_gpio_pins_default>; standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; }; + + dp_pwr_3v3: regulator-dp-pwr { + compatible = "regulator-fixed"; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -190,6 +212,12 @@ >; }; + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ + >; + }; + main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ @@ -658,6 +686,33 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + &mcasp0 { status = "disabled"; }; @@ -807,6 +862,8 @@ &mhdp { phys = <&torrent_phy_dp>; phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; }; &pcie0_rc { @@ -859,10 +916,6 @@ status = "disabled"; }; -&dss { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- cgit v1.2.3 From d4f3c8a169ab82b91ba1e10a495e900477a75cf5 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Thu, 5 May 2022 14:37:08 +0530 Subject: arm64: dts: ti: k3-j721e-sk: Enable DisplayPort Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220505090709.9252-2-r-ravikumar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 45 +++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 98177a20b45f..07b1e40fbc47 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -213,6 +213,18 @@ enable-active-high; }; + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -638,6 +650,8 @@ &mhdp { phys = <&torrent_phy_dp>; phy-names = "dpphy"; + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; }; &usbss0 { @@ -718,6 +732,33 @@ <&k3_clks 152 18>; /* DPI1_EXT_CLKSEL_OUT0 */ }; +&dss_ports { + port { + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + &mcasp0 { /* Unused */ status = "disabled"; @@ -852,10 +893,6 @@ status = "disabled"; }; -&dss { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- cgit v1.2.3 From 7d4686fc3c2ad9bfd1eaf3c54515d6469e542578 Mon Sep 17 00:00:00 2001 From: Rahul T R Date: Thu, 5 May 2022 14:37:09 +0530 Subject: arm64: dts: ti: k3-j721e-sk: Enable HDMI Add node for dvi bridge and the endpoint nodes to describe connection from DSS => TI TFP410 DPI-to-DVI Bridge => HDMI connector. Also add the required pinmux for HDMI hotplug and powerdown Signed-off-by: Rahul T R Signed-off-by: Vignesh Raghavendra Reviewed-by: Aradhya Bhatia Link: https://lore.kernel.org/r/20220505090709.9252-3-r-ravikumar@ti.com --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 80 +++++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 07b1e40fbc47..80358cba6954 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -225,6 +225,59 @@ }; }; }; + + hdmi-connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_pins_default>; + + ddc-i2c-bus = <&main_i2c1>; + + /* HDMI_HPD */ + hpd-gpios = <&main_gpio1 0 GPIO_ACTIVE_HIGH>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + dvi-bridge { + compatible = "ti,tfp410"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_pdn_pins_default>; + + powerdown-gpios = <&main_gpio0 127 GPIO_ACTIVE_LOW>; + ti,deskew = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint { + remote-endpoint = <&dpi1_out>; + pclk-sample = <1>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint { + remote-endpoint = + <&hdmi_connector_in>; + }; + }; + }; + }; }; &main_pmx0 { @@ -329,6 +382,18 @@ >; }; + hdmi_hpd_pins_default: hdmi-hpd-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x204, PIN_INPUT, 7) /* (AD5) UART1_RTSn.GPIO1_0 */ + >; + }; + + hdmi_pdn_pins_default: hdmi-pdn-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ + >; + }; + /* Reset for M.2 E Key slot on PCIe0 */ ekey_reset_pins_default: ekey-reset-pns-pins-default { pinctrl-single,pins = < @@ -733,11 +798,24 @@ }; &dss_ports { - port { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpi0_out: endpoint { remote-endpoint = <&dp0_in>; }; }; + + port@1 { + reg = <1>; + + dpi1_out: endpoint { + remote-endpoint = <&tfp410_in>; + }; + }; }; &dp0_ports { -- cgit v1.2.3 From 9583009097c8933a30110097d373a09624cb8c37 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sat, 23 Apr 2022 02:36:11 +0530 Subject: arm64: dts: qcom: sm8150: Fix iommu sid value for SDC2 controller Fix the IOMMU sid value for SDC2 controller, to ensure that no ADMA error is observed when the microSD card is detected on the SA8155p-ADP board. Fixes: 876644c76034 ("arm64: dts: qcom: sm8150: Add support for SDC2") Cc: Bjorn Andersson Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220422210611.173842-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 2700a8145cb9..f70ae4c56762 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -3555,7 +3555,7 @@ <&gcc GCC_SDCC2_APPS_CLK>, <&rpmhcc RPMH_CXO_CLK>; clock-names = "iface", "core", "xo"; - iommus = <&apps_smmu 0x4a0 0x0>; + iommus = <&apps_smmu 0x6a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; power-domains = <&rpmhpd 0>; -- cgit v1.2.3 From 11a3f3dc2cf8d6127aae6183a69dcf3dde026305 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Sun, 24 Apr 2022 01:20:03 +0530 Subject: arm64: dts: qcom: sa8155p-adp: Disable multiple Tx and Rx queues for ethernet IP Fix the issues seen with ethernet traffic getting stalled on SA8155p-ADP board with default (or larger) mtu size of 1500 bytes, by disabling multiple Tx and Rx queues for the stmmac IP block. With the single queue setup, the ethernet traffic is stable, wget / curl can work well on the board and no ethernet stall is observed even when longer netperf / iperf3 test are run. Also a performance of ~940 Mbits/sec is observed on the 1G link, so there is no observable degradation in performance as well. Fixes: c5cb42cc8411 ("arm64: dts: qcom: sa8155p-adp: Enable ethernet node") Cc: Bjorn Andersson Cc: Vinod Koul Signed-off-by: Bhupesh Sharma Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220423195003.353150-1-bhupesh.sharma@linaro.org --- arch/arm64/boot/dts/qcom/sa8155p-adp.dts | 40 ++------------------------------ 1 file changed, 2 insertions(+), 38 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts index 8034d0d31bd0..ba547ca9fc6b 100644 --- a/arch/arm64/boot/dts/qcom/sa8155p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8155p-adp.dts @@ -49,7 +49,7 @@ }; mtl_rx_setup: rx-queues-config { - snps,rx-queues-to-use = <4>; + snps,rx-queues-to-use = <1>; snps,rx-sched-sp; queue0 { @@ -58,28 +58,10 @@ snps,route-up; snps,priority = <0x1>; }; - - queue1 { - snps,dcb-algorithm; - snps,map-to-dma-channel = <0x1>; - snps,route-ptp; - }; - - queue2 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x2>; - snps,route-avcp; - }; - - queue3 { - snps,avb-algorithm; - snps,map-to-dma-channel = <0x3>; - snps,priority = <0xC>; - }; }; mtl_tx_setup: tx-queues-config { - snps,tx-queues-to-use = <4>; + snps,tx-queues-to-use = <1>; snps,tx-sched-wrr; queue0 { @@ -87,24 +69,6 @@ snps,dcb-algorithm; snps,priority = <0x0>; }; - - queue1 { - snps,weight = <0x11>; - snps,dcb-algorithm; - snps,priority = <0x1>; - }; - - queue2 { - snps,weight = <0x12>; - snps,dcb-algorithm; - snps,priority = <0x2>; - }; - - queue3 { - snps,weight = <0x13>; - snps,dcb-algorithm; - snps,priority = <0x3>; - }; }; }; -- cgit v1.2.3 From 366a0a194b3b3e3e52bc7b7b1ac35b40a1187902 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Tue, 26 Apr 2022 12:41:03 -0700 Subject: arm64: dts: qcom: sc7280: eDP for herobrine boards Add eDP support to herobrine boards, splitting up amongst the different files as makes sense. Rationale for the current split of things: * The eDP connector itself is on qcard. However, not all devices with a qcard will use an eDP panel. Some might use MIPI and, presumably, someone could build a device with qcard that had no display at all. * The qcard provides a PWM for backlight that goes to the eDP connector. This PWM is also provided to the board and it's expected that it would be used as the backlight PWM even for herobrine devices with MIPI displays. * It's currently assumed that all herobrine boards will have some sort of display, either MIPI or eDP (but not both). * We will assume herobrine-rev1 has eDP. The schematics allow for a MIPI panel to be hooked up but, aside from some testing, nobody is doing this and most boards don't have all the parts stuffed for it. The two panels would also share a PWM for backlight, which is weird. * herobrine-villager and herobrine-hoglin (crd) also have eDP. * herobrine-hoglin (crd) has slightly different regulator setup for the backlight. It's expected that this is unique to this board. See comments in the dts file. * There are some regulators that are defined in the qcard schematic but provided by the board like "vreg_edp_bl" and "vreg_edp_3p3". While we could put references to these regulators straight in the qcard.dtsi file, this would force someone using qcard that didn't provide those regulators to provide a dummy or do an ugly /delete-node/. Instead, we'll add references in herobrine.dtsi. Signed-off-by: Douglas Anderson Reviewed-by: Abhinav Kumar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220426124053.v2.1.Iedd71976a78d53c301ce0134832de95a989c9195@changeid --- arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts | 40 ++++++++++++++++ .../dts/qcom/sc7280-herobrine-herobrine-r1.dts | 8 ++++ .../boot/dts/qcom/sc7280-herobrine-villager-r0.dts | 8 ++++ arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 24 ++++++++++ arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi | 54 ++++++++++++++++++++++ 5 files changed, 134 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts index b06f61e9b90b..a4ac33c4fd59 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts @@ -12,6 +12,27 @@ / { model = "Qualcomm Technologies, Inc. sc7280 CRD platform (rev5+)"; compatible = "google,hoglin", "qcom,sc7280"; + + /* FIXED REGULATORS */ + + /* + * On most herobrine boards PPVAR_SYS directly provides VREG_EDP_BL. + * However, on CRD there's an extra regulator in the way. Since this + * is expected to be uncommon, we'll leave the "vreg_edp_bl" label + * in the baseboard herobrine.dtsi point at "ppvar_sys" and then + * make a "_crd" specific version here. + */ + vreg_edp_bl_crd: vreg-edp-bl-crd-regulator { + compatible = "regulator-fixed"; + regulator-name = "vreg_edp_bl_crd"; + + gpio = <&pm8350c_gpios 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&edp_bl_reg_en>; + + vin-supply = <&ppvar_sys>; + }; }; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ @@ -81,6 +102,14 @@ ap_ts_pen_1v8: &i2c13 { }; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; @@ -91,6 +120,10 @@ ap_ts_pen_1v8: &i2c13 { status = "okay"; }; +&pm8350c_pwm_backlight { + power-supply = <&vreg_edp_bl_crd>; +}; + /* For eMMC */ &sdhc_1 { status = "okay"; @@ -121,6 +154,13 @@ ap_ts_pen_1v8: &i2c13 { "PMIC_EDP_BL_EN", "PMIC_EDP_BL_PWM", ""; + + edp_bl_reg_en: edp-bl-reg-en { + pins = "gpio6"; + function = "normal"; + bias-disable; + qcom,drive-strength = ; + }; }; &tlmm { diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts index 29c4ca095294..b69ca09d9bfb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts @@ -100,6 +100,14 @@ ts_i2c: &i2c13 { }; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts index 6c2b9a14535a..d3d6ffad4eff 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine-villager-r0.dts @@ -58,6 +58,14 @@ ap_tp_i2c: &i2c0 { status = "okay"; }; +&mdss_edp { + status = "okay"; +}; + +&mdss_edp_phy { + status = "okay"; +}; + /* For nvme */ &pcie1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index d58045dd7334..9cb1bc8ed6b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -367,6 +367,11 @@ vreg_edp_3p3: &pp3300_left_in_mlb {}; /* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */ +&edp_panel { + /* Our board provides power to the qcard for the eDP panel. */ + power-supply = <&vreg_edp_3p3>; +}; + ap_sar_sensor_i2c: &i2c1 { clock-frequency = <400000>; status = "disabled"; @@ -420,6 +425,14 @@ ap_i2c_tpm: &i2c14 { }; }; +&mdss { + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + /* NVMe drive, enabled on a per-board basis */ &pcie1 { pinctrl-names = "default"; @@ -429,6 +442,17 @@ ap_i2c_tpm: &i2c14 { vddpe-3v3-supply = <&pp3300_ssd>; }; +&pm8350c_pwm { + status = "okay"; +}; + +&pm8350c_pwm_backlight { + status = "okay"; + + /* Our board provides power to the qcard for the backlight */ + power-supply = <&vreg_edp_bl>; +}; + &pmk8350_rtc { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi index 98b5cd70bca5..d59002d4492e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi @@ -29,6 +29,16 @@ serial0 = &uart5; serial1 = &uart7; }; + + pm8350c_pwm_backlight: backlight { + compatible = "pwm-backlight"; + status = "disabled"; + + enable-gpios = <&pm8350c_gpios 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_edp_bl_en>; + pwms = <&pm8350c_pwm 3 65535>; + }; }; &apps_rsc { @@ -293,11 +303,50 @@ modem-init; }; +/* NOTE: Not all Qcards have eDP connector stuffed */ +&mdss_edp { + vdda-0p9-supply = <&vdd_a_edp_0_0p9>; + vdda-1p2-supply = <&vdd_a_edp_0_1p2>; + + aux-bus { + edp_panel: panel { + compatible = "edp-panel"; + + backlight = <&pm8350c_pwm_backlight>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + edp_panel_in: endpoint { + remote-endpoint = <&mdss_edp_out>; + }; + }; + }; + }; + }; +}; + +&mdss_edp_out { + remote-endpoint = <&edp_panel_in>; +}; + +&mdss_edp_phy { + vdda-pll-supply = <&vdd_a_edp_0_0p9>; + vdda-phy-supply = <&vdd_a_edp_0_1p2>; +}; + &pcie1_phy { vdda-phy-supply = <&vreg_l10c_0p88>; vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pm8350c_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_edp_bl_pwm>; +}; + &pmk8350_vadc { pmk8350-die-temp@3 { reg = ; @@ -383,6 +432,11 @@ mos_bt_uart: &uart7 { * baseboard or board device tree, not here. */ +/* No external pull for eDP HPD, so set the internal one. */ +&edp_hot_plug_det { + bias-pull-down; +}; + /* * For ts_i2c * -- cgit v1.2.3 From 51d30402be7506db007af6d29c6bc7c1cefcc82f Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:37 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Simplify trackpad enabling Trogdor boards with a detachable keyboard don't have a trackpad over i2c. Instead the trackpad is on the detachable keyboard base. Let's move the enabling of the trackpad i2c bus out of the base sc7180-trogdor.dtsi file so that each trogdor board that is detachable, of which there are many, doesn't have to disable the trackpad bus. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-2-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 4 ++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 1 - 6 files changed, 12 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index c81805ef2250..8da61a52f150 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -111,10 +111,6 @@ ap_ts_pen_1v8: &i2c4 { }; }; -&i2c7 { - status = "disabled"; -}; - &i2c9 { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index bff2b556cc75..532c7dcc3f73 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -88,10 +88,6 @@ ap_h1_spi: &spi0 {}; }; }; -&ap_tp_i2c { - status = "disabled"; -}; - ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 69666f92176a..75df5d1633b2 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -19,6 +19,10 @@ ap_h1_spi: &spi0 {}; semtech,avg-pos-strength = <64>; }; +&ap_tp_i2c { + status = "okay"; +}; + /* * Lazor is stuffed with a 47k NTC as charger thermistor which currently is * not supported by the PM6150 ADC driver. Disable the charger thermal zone diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index e90f99ef5323..410ca2a76d81 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -36,6 +36,10 @@ ap_h1_spi: &spi0 {}; realtek,dmic-clk-driving-high = "true"; }; +&ap_tp_i2c { + status = "okay"; +}; + &cpu6_alert0 { temperature = <60000>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 457c25499863..311c42a535ff 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -20,6 +20,10 @@ ap_h1_spi: &spi0 {}; compatible = "google,trogdor", "qcom,sc7180"; }; +&ap_tp_i2c { + status = "okay"; +}; + ap_ts_pen_1v8: &i2c4 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index b0efb354458c..7648be83f7e4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -727,7 +727,6 @@ ap_sar_sensor_i2c: &i2c5 { }; ap_tp_i2c: &i2c7 { - status = "okay"; clock-frequency = <400000>; trackpad: trackpad@15 { -- cgit v1.2.3 From d277cab7afc7b54ea91808c0895d78c2021af534 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:38 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Simplify spi0/spi6 labeling We had to do this spi0/spi6 flip-flop on trogdor-r0 because the spi buses got swizzled between r0 and r1. The swizzle stopped after r1, but we kept this around to support either hardware possibility and to keep trogdor-r0 working. trogdor-r0 isn't supported upstream, so this swizzle is not doing anything besides making a pattern that others tryt to copy for the EC and H1 nodes. Let's remove it and simplify the dts files. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-3-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 6 +----- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 3 --- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 4 ---- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 6 files changed, 3 insertions(+), 21 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index 8da61a52f150..ac2279142a95 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -6,14 +6,10 @@ */ #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" -/* Deleted nodes from trogdor.dtsi */ +/* Deleted nodes from sc7180-trogdor.dtsi */ /delete-node/ &alc5682; /delete-node/ &pp3300_codec; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index 532c7dcc3f73..9b3e3d13c165 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -5,9 +5,6 @@ * Copyright 2021 Google LLC. */ -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 75df5d1633b2..fe2369c29aad 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -5,9 +5,6 @@ * Copyright 2020 Google LLC. */ -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" &ap_sar_sensor { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 410ca2a76d81..3bca7545ffe5 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -6,10 +6,6 @@ */ #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 311c42a535ff..6c822c84112a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -8,10 +8,6 @@ /dts-v1/; #include "sc7180.dtsi" - -ap_ec_spi: &spi6 {}; -ap_h1_spi: &spi0 {}; - #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 7648be83f7e4..ea5bedc3d1cb 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -626,7 +626,7 @@ }; }; -&ap_ec_spi { +ap_ec_spi: &spi6 { status = "okay"; cros_ec: ec@0 { compatible = "google,cros-ec-spi"; @@ -675,7 +675,7 @@ }; }; -&ap_h1_spi { +ap_h1_spi: &spi0 { status = "okay"; cr50: tpm@0 { compatible = "google,cr50"; -- cgit v1.2.3 From 19794489fa2474a55c00848e00ca3d15ea01d36c Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Tue, 26 Apr 2022 19:03:39 -0700 Subject: arm64: dts: qcom: Only include sc7180.dtsi in sc7180-trogdor.dtsi The SoC is always present on sc7180-trogdor.dtsi and thus we should include it in the "generic" dtsi file for trogdor. Previously we had removed it from there because we had to do the spi6/spi0 swizzle, so each trogdor variant board had to include sc7180.dtsi and then sc7180-trogdor.dtsi so that the latter dtsi file could modify the right spi bus for EC and H1 properties that are common to all trogdor boards. Now that we're done with that we can replace sc7180.dtsi includes with sc7180-trogdor.dtsi and include sc7180.dtsi in sc7180-trogdor.dtsi as was originally intended. We still need to include sc7180-trogdor.dtsi before the bridge dtsi files though because those rely on the panel label. Cc: "Joseph S. Barrera III" Cc: Douglas Anderson Signed-off-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220427020339.360855-4-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts | 2 +- arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts | 1 - arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 3 ++- 19 files changed, 17 insertions(+), 19 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index ac2279142a95..8ac1f1e61006 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts index 70032983fb65..d9e905ed4e62 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts index e92e2e9e48ed..242c178fdc52 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts index 0de0c97f5728..66dd87016201 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r4.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-homestar.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts index f360ff27226e..235cda2bba5e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts index c44ed54af690..913b5fc3ba76 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts index 42b4bbcc76f4..d42dcd421146 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r4.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts index dc47842bc662..15d77dc5f956 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts index b142006478ea..bfbf26fd2cd4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts index 59740799fa3a..d45a59afd7fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts index 18ef9da71998..6ff81c1f7c44 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts index 8913592b2d82..e58e36e35950 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts index 7adcedbf080d..76c83f88cb41 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts index 7f5c015e1ecb..960f7b7ce094 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-kb.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts index 8107f3d932eb..38027f13b9d0 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9-lte.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-trogdor-lte-sku.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts index 83f6a4eb5ae5..56dd222650d3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r9.dts @@ -7,7 +7,7 @@ /dts-v1/; -#include "sc7180.dtsi" +#include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-parade-ps8640.dtsi" #include "sc7180-trogdor-lazor.dtsi" #include "sc7180-lite.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index 3bca7545ffe5..4841d42c8c62 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -5,7 +5,6 @@ * Copyright 2020 Google LLC. */ -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts index 6c822c84112a..352827e5740a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dts @@ -7,7 +7,6 @@ /dts-v1/; -#include "sc7180.dtsi" #include "sc7180-trogdor.dtsi" #include "sc7180-trogdor-ti-sn65dsi86.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index ea5bedc3d1cb..e55dbaa6dc12 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -11,7 +11,8 @@ #include #include -/* PMICs depend on spmi_bus label and so must come after SoC */ +#include "sc7180.dtsi" +/* PMICs depend on spmi_bus label and so must come after sc7180.dtsi */ #include "pm6150.dtsi" #include "pm6150l.dtsi" -- cgit v1.2.3 From 987da486d84a5643fb0e027fe4fc4dfcb54206a0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 28 Apr 2022 22:50:57 +0900 Subject: arm64: dts: renesas: Add Renesas R8A779G0 SoC support Add initial support for the Renesas R8A779G0 (R-Car V4H) SoC. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220428135058.597586-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 122 ++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi new file mode 100644 index 000000000000..7cbb0de060dd --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G0) SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779g0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779G0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu_a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779g0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779g0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779g0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779g0", + "renesas,rcar-gen4-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779G0_CLK_S0D3_PER>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit v1.2.3 From e4d755cfec44197f605e1a2e9ff17434c6c9d513 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 28 Apr 2022 22:50:58 +0900 Subject: arm64: dts: renesas: Add Renesas White Hawk boards support Initial support for the Renesas White Hawk CPU and BreakOut boards. Signed-off-by: Yoshihiro Shimoda Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220428135058.597586-4-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 45 ++++++++++++++++++++++ .../arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 22 +++++++++++ 3 files changed, 69 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fa9811251fd7..15309309a2e1 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_R8A779A0) += r8a779a0-falcon.dtb dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb.dtb dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-ulcb-kf.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi new file mode 100644 index 000000000000..ea4ae4b893ab --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "r8a779g0.dtsi" + +/ { + model = "Renesas White Hawk CPU board"; + compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts new file mode 100644 index 000000000000..bc0ac109b17c --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the White Hawk CPU and BreakOut boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" + +/ { + model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; + compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; + + aliases { + serial0 = &hscif0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; +}; -- cgit v1.2.3 From c62af12c700dc435b82df207e49dac3f91ece6c6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:23:58 +0100 Subject: arm64: dts: renesas: rzg2l-smarc: Move ssi0 and cpu sound_dai nodes from common dtsi On RZ/G2{L,LC} SoM module, the wm8978 audio codec is connected to ssi0, whereas on RZ/G2UL it is connected to ssi1. So move ssi0 and cpu sound_dai nodes from common dtsi to board specific dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 6 ------ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 8 -------- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 11 +++++++++++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 11 +++++++++++ 4 files changed, 22 insertions(+), 14 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index df27b63f0465..52ee1640c3c1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -54,12 +54,6 @@ status = "disabled"; }; -&ssi0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - &usb2_phy0 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index 0e61b85efb43..3962d47b3e59 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -52,7 +52,6 @@ "Mic Bias", "Microphone Jack"; cpu_dai: simple-audio-card,cpu { - sound-dai = <&ssi0>; }; codec_dai: simple-audio-card,codec { @@ -168,13 +167,6 @@ status = "okay"; }; -&ssi0 { - pinctrl-0 = <&ssi0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - &usb2_phy0 { pinctrl-0 = <&usb0_pins>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index aadc41515093..e180a955b6ac 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -18,6 +18,10 @@ }; }; +&cpu_dai { + sound-dai = <&ssi0>; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; @@ -49,6 +53,13 @@ }; #endif +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index 74a844ea7537..aa170492dd2b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -60,6 +60,10 @@ }; #endif +&cpu_dai { + sound-dai = <&ssi0>; +}; + &i2c2 { pinctrl-0 = <&i2c2_pins>; pinctrl-names = "default"; @@ -91,6 +95,13 @@ }; #endif +&ssi0 { + pinctrl-0 = <&ssi0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + #if (SW_RSPI_CAN) &spi1 { /delete-property/ pinctrl-0; -- cgit v1.2.3 From 1ed914e341392dbb7c29f0f62c105a81cce6b3e0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:23:59 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Enable Audio Enable Audio on RZ/G2UL SMARC EVK by adding ssi1 pincontrol entries to the soc-pinctrl dtsi and ssi1 and cpu sound_dai nodes to the board dtsi. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi | 23 ++++++++++++++++++++++ 2 files changed, 30 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 17527184ff2a..201b70150e01 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -98,4 +98,11 @@ pins = "AUDIO_CLK1", "AUDIO_CLK2"; input-enable; }; + + ssi1_pins: ssi1 { + pinmux = , /* BCK */ + , /* RCK */ + , /* TXD */ + ; /* RXD */ + }; }; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi index d75ad79ba804..0051634d7b1c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi @@ -27,6 +27,10 @@ }; #endif +&cpu_dai { + sound-dai = <&ssi1>; +}; + &i2c1 { wm8978: codec@1a { compatible = "wlf,wm8978"; @@ -35,6 +39,25 @@ }; }; +#if (SW_ET0_EN_N) +&ssi1 { + pinctrl-0 = <&ssi1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; +#else +&snd_rzg2l { + status = "disabled"; +}; + +&ssi1 { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; + status = "disabled"; +}; +#endif + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>; }; -- cgit v1.2.3 From 094ff3485a05cd29db083a6e2905e87b68f13538 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Apr 2022 08:24:00 +0100 Subject: arm64: dts: renesas: rzg2ul-smarc: Enable USB2.0 support Enable USB2.0 Host/Device support on RZ/G2UL SMARC EVK by adding usb{0,1} pincontrol entries to the soc-pinctrl dtsi and deleting the nodes which disabled it. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220429072400.23729-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts | 46 ---------------------- .../boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi | 11 ++++++ 2 files changed, 11 insertions(+), 46 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts index 52ee1640c3c1..2d740bd420ca 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts @@ -14,54 +14,8 @@ compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043"; }; -&ehci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ehci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&hsusb { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&ohci1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&phyrst { - status = "disabled"; -}; - &spi1 { /delete-property/ pinctrl-0; /delete-property/ pinctrl-names; status = "disabled"; }; - -&usb2_phy0 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; - -&usb2_phy1 { - /delete-property/ pinctrl-0; - /delete-property/ pinctrl-names; - status = "disabled"; -}; diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi index 201b70150e01..bd8bc858c28c 100644 --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi @@ -105,4 +105,15 @@ , /* TXD */ ; /* RXD */ }; + + usb0_pins: usb0 { + pinmux = , /* VBUS */ + , /* OVC */ + ; /* OTG_ID */ + }; + + usb1_pins: usb1 { + pinmux = , /* OVC */ + ; /* VBUS */ + }; }; -- cgit v1.2.3 From b7423e39432c00de8ba8ebefce3849aa502208d1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 24 Apr 2022 19:12:27 +0300 Subject: arm64: dts: renesas: Remove empty lvds endpoints Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty lvds endpoints from SoC dtsi files, they should be instead declared in the board dts or in overlays. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20220424161228.8147-1-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 4 ---- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 4 ---- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 4 ---- 12 files changed, 30 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index faf5bbbb3710..d99ed3d47427 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2776,8 +2776,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index be998bc40412..69ab6e66bb98 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2621,8 +2621,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 4f69f90d88cb..514a095ac3a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1914,8 +1914,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1941,8 +1939,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 989c1c00dcdc..aefed8e0037f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2895,8 +2895,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index 884210544ba0..d3cd275b20cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3395,8 +3395,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 0d96b5bb9584..da4904325c4a 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2992,8 +2992,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 58e161e5dae0..9a46bdeb8993 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2802,8 +2802,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index ecca9582edf6..0d6d8cb9a409 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2804,8 +2804,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 79718234d85f..6d9e69895cae 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1191,8 +1191,6 @@ }; port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 148983130adf..46d5567799b8 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1569,8 +1569,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 5d41e46d06f5..12440f12c83d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2091,8 +2091,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -2118,8 +2116,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 0eccf81db374..2c0441718d39 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1410,8 +1410,6 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - }; }; }; }; @@ -1437,8 +1435,6 @@ port@1 { reg = <1>; - lvds1_out: endpoint { - }; }; }; }; -- cgit v1.2.3 From 747bbcd3aacd95fe200cdda415dba02e872946b5 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sun, 24 Apr 2022 19:12:28 +0300 Subject: arm64: dts: renesas: Remove empty rgb output endpoints Endpoints node must have a remote-endpoint property, as endpoints only exist to model a link between ports. Drop the empty rgb output endpoints from SoC dtsi files, and declare them in the board dts instead. Signed-off-by: Laurent Pinchart Reviewed-by: Kieran Bingham Link: https://lore.kernel.org/r/20220424161228.8147-2-laurent.pinchart+renesas@ideasonboard.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi | 10 ++++++++-- arch/arm64/boot/dts/renesas/draak.dtsi | 2 +- arch/arm64/boot/dts/renesas/ebisu.dtsi | 2 +- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 2 +- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 2 -- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 2 -- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 +- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 10 ++++++++-- 18 files changed, 20 insertions(+), 32 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi index 5ad6cd1864c1..142e7ffbd2bd 100644 --- a/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi +++ b/arch/arm64/boot/dts/renesas/beacon-renesom-baseboard.dtsi @@ -272,8 +272,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&rgb_panel>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&rgb_panel>; + }; + }; + }; }; &ehci0 { diff --git a/arch/arm64/boot/dts/renesas/draak.dtsi b/arch/arm64/boot/dts/renesas/draak.dtsi index 2a784ee6da49..7231f820d601 100644 --- a/arch/arm64/boot/dts/renesas/draak.dtsi +++ b/arch/arm64/boot/dts/renesas/draak.dtsi @@ -285,7 +285,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index ae688707f8c6..72f359efa23e 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -356,7 +356,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index d99ed3d47427..bdf23c17f049 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2738,8 +2738,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 69ab6e66bb98..156ccc541358 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2583,8 +2583,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts index 4e72e4f2bab0..5a6ea08ffd2b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts +++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts @@ -172,7 +172,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&tda19988_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 514a095ac3a3..9da3e739a729 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1871,8 +1871,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index aefed8e0037f..e20e3e135229 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2857,8 +2857,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index d3cd275b20cd..b0063f58990f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -3351,8 +3351,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index da4904325c4a..ef1d86023155 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -2954,8 +2954,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 9a46bdeb8993..aa666b17b827 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -2764,8 +2764,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 0d6d8cb9a409..02b1cbb61b85 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -2766,8 +2766,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { reg = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 6d9e69895cae..1891b3bc8cc5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1157,8 +1157,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 46d5567799b8..b56120fffaf0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1534,8 +1534,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 12440f12c83d..44d6f6032de7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -2048,8 +2048,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 2c0441718d39..9c181e0cb6c0 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -1367,8 +1367,6 @@ port@0 { reg = <0>; - du_out_rgb: endpoint { - }; }; port@1 { diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index 7ad72f377a35..31837fcd7bf0 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -386,7 +386,7 @@ ports { port@0 { - endpoint { + du_out_rgb: endpoint { remote-endpoint = <&adv7123_in>; }; }; diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index ae532cd21708..5bcb84403ef6 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -97,8 +97,14 @@ status = "okay"; }; -&du_out_rgb { - remote-endpoint = <&adv7513_in>; +&du { + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; + }; }; &ehci0 { -- cgit v1.2.3 From 1404ca90f49be530551e26b8bc6dfe2142aba86e Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Apr 2022 14:31:55 +0100 Subject: arm64: dts: renesas: r9a07g044: Fix external clk node names Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220428133156.18080-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 19287cccb1f0..3652e511160f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,14 +28,14 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ -- cgit v1.2.3 From 975253505429bc60d1b400296728fffb416aa1ff Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Apr 2022 14:31:56 +0100 Subject: arm64: dts: renesas: r9a07g054: Fix external clk node names Add suffix '-clk' for can and extal clk node names and replace the clk node names audio_clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220428133156.18080-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index f35aa0311e9c..4d6b9d7684c9 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -13,14 +13,14 @@ #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio_clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio_clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ @@ -28,14 +28,14 @@ }; /* External CAN clock - to be overridden by boards that provide it */ - can_clk: can { + can_clk: can-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ - extal_clk: extal { + extal_clk: extal-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ -- cgit v1.2.3 From 22ec868997108e514fe380171c45578da630a0ec Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:22 +0100 Subject: arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 43 +++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 15335e9ca06b..82fe61991204 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -158,11 +158,52 @@ status = "disabled"; }; + spi0: spi@1004ac00 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004ac00 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; + resets = <&cpg R9A07G043_RSPI0_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + spi1: spi@1004b000 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; reg = <0 0x1004b000 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; + resets = <&cpg R9A07G043_RSPI1_RST>; + power-domains = <&cpg>; + num-cs = <1>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; + }; + + spi2: spi@1004b400 { + compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; + reg = <0 0x1004b400 0 0x400>; + interrupts = , + , + ; + interrupt-names = "error", "rx", "tx"; + clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; + resets = <&cpg R9A07G043_RSPI2_RST>; + power-domains = <&cpg>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; scif0: serial@1004b800 { -- cgit v1.2.3 From e6a9acc370c6cb9e6ff6225b034a7a4374df0134 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:23 +0100 Subject: arm64: dts: renesas: r9a07g043: Add OPP table Add OPP table for RZ/G2UL SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 82fe61991204..e2300d5c6a15 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -42,6 +42,33 @@ clock-frequency = <0>; }; + cluster0_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-125000000 { + opp-hz = /bits/ 64 <125000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-250000000 { + opp-hz = /bits/ 64 <250000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1100000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -53,6 +80,7 @@ next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + operating-points-v2 = <&cluster0_opp>; }; L3_CA55: cache-controller-0 { -- cgit v1.2.3 From 91e548da2cb1b180a1ab1059a1c89d7532135da7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:24 +0100 Subject: arm64: dts: renesas: r9a07g043: Add TSU node Add TSU node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-5-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index e2300d5c6a15..cd7d30797eee 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -486,6 +486,16 @@ /* place holder */ }; + tsu: thermal@10059400 { + compatible = "renesas,r9a07g043-tsu", + "renesas,rzg2l-tsu"; + reg = <0 0x10059400 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; + resets = <&cpg R9A07G043_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <1>; + }; + sbc: spi@10060000 { reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, @@ -826,6 +836,22 @@ }; }; + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu 0>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, -- cgit v1.2.3 From c2ff5c0282f94c1f1f81007e1fa7378fe95f46d3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Sun, 1 May 2022 12:29:25 +0100 Subject: arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Setup a thermal zone driven by SoC temperature sensor. Create passive trip points and bind them to CPUFreq cooling device that supports power extension. Based on the work done by Dien Pham and others for r8a77990 SoC. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220501112926.47024-6-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index cd7d30797eee..9048edb5e2b1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -77,6 +77,7 @@ compatible = "arm,cortex-a55"; reg = <0>; device_type = "cpu"; + #cooling-cells = <2>; next-level-cache = <&L3_CA55>; enable-method = "psci"; clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; @@ -841,6 +842,15 @@ polling-delay-passive = <250>; polling-delay = <1000>; thermal-sensors = <&tsu 0>; + sustainable-power = <717>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&cpu0 0 2>; + contribution = <1024>; + }; + }; trips { sensor_crit: sensor-crit { @@ -848,6 +858,12 @@ hysteresis = <1000>; type = "critical"; }; + + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; }; }; }; -- cgit v1.2.3 From 470218e29daf7f1de9f4d1af16c7ecf54344f6a1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 2 May 2022 20:01:55 +0100 Subject: arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220502190155.84496-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 9048edb5e2b1..b31fb713ae4d 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -498,12 +498,19 @@ }; sbc: spi@10060000 { + compatible = "renesas,r9a07g043-rpc-if", + "renesas,rzg2l-rpc-if"; reg = <0 0x10060000 0 0x10000>, <0 0x20000000 0 0x10000000>, <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, + <&cpg CPG_MOD R9A07G043_SPI_CLK>; + resets = <&cpg R9A07G043_SPI_RST>; + power-domains = <&cpg>; #address-cells = <1>; #size-cells = <0>; - /* place holder */ + status = "disabled"; }; cpg: clock-controller@11010000 { -- cgit v1.2.3 From 6af663af3c46300032fd7a783bdc3e585035438f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 19:33:52 +0200 Subject: arm64: dts: renesas: Add interrupt-names to CANFD nodes The Renesas R-Car CAN-FD Controller on R-Car Gen3 and RZ/G2 SoCs has two interrupts. Add interrupt-names properties to all CAN-FD device nodes to identify the individual interrupts, so we can make this property a required property in the DT bindings. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/10eef1e20372af4a156b06df8e5124666ec7c6b6.1651512451.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77951.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77960.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77961.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77990.dtsi | 1 + arch/arm64/boot/dts/renesas/r8a77995.dtsi | 1 + 12 files changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index bdf23c17f049..e7d17776624d 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -1179,6 +1179,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774A1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 156ccc541358..f62d95760e82 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -1052,6 +1052,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774B1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index 9da3e739a729..b6aeb22e8836 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1009,6 +1009,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774C0_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index e20e3e135229..8ec59094882b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1280,6 +1280,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A774E1_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index b0063f58990f..a297af22a195 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -1368,6 +1368,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7795_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index ef1d86023155..4159c23d3874 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -1240,6 +1240,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A7796_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index aa666b17b827..3c744b7d0dc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -1229,6 +1229,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77961_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 02b1cbb61b85..21a5e1cdd9f1 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -1103,6 +1103,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77965_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1891b3bc8cc5..2703ef3a38c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -557,6 +557,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77970_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index b56120fffaf0..8594be72f221 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -609,6 +609,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77980_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 44d6f6032de7..d33021202637 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1052,6 +1052,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77990_CLK_CANFD>, <&can_clk>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 9c181e0cb6c0..f040d03e0a87 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -557,6 +557,7 @@ reg = <0 0xe66c0000 0 0x8000>; interrupts = , ; + interrupt-names = "ch_int", "g_int"; clocks = <&cpg CPG_MOD 914>, <&cpg CPG_CORE R8A77995_CLK_CANFD>, <&can_clk>; -- cgit v1.2.3 From a1721bbbdb5c6687d157f8b8714bba837f6028ac Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 2 May 2022 15:35:17 +0200 Subject: arm64: dts: renesas: r8a779a0: Update to R-Car Gen4 compatible values Despite the name, R-Car V3U is the first member of the R-Car Gen4 family. Hence update the compatible properties in various device nodes to include family-specific compatible values for R-Car Gen4 instead of R-Car Gen3: - DMAC, - (H)SCIF, - I2C, - IPMMU, - WDT. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/73cea9d5e1a6639422c67e4df4285042e31c9fd5.1651497071.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 74 ++++++++++++++++++------------- 1 file changed, 44 insertions(+), 30 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 57d49d27cdca..b9731504b7cd 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -86,7 +86,7 @@ rwdt: watchdog@e6020000 { compatible = "renesas,r8a779a0-wdt", - "renesas,rcar-gen3-wdt"; + "renesas,rcar-gen4-wdt"; reg = <0 0xe6020000 0 0x0c>; interrupts = ; clocks = <&cpg CPG_MOD 907>; @@ -430,7 +430,7 @@ i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6500000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 518>; @@ -446,7 +446,7 @@ i2c1: i2c@e6508000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 519>; @@ -462,7 +462,7 @@ i2c2: i2c@e6510000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe6510000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 520>; @@ -478,7 +478,7 @@ i2c3: i2c@e66d0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 521>; @@ -494,7 +494,7 @@ i2c4: i2c@e66d8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66d8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 522>; @@ -510,7 +510,7 @@ i2c5: i2c@e66e0000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e0000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 523>; @@ -526,7 +526,7 @@ i2c6: i2c@e66e8000 { compatible = "renesas,i2c-r8a779a0", - "renesas,rcar-gen3-i2c"; + "renesas,rcar-gen4-i2c"; reg = <0 0xe66e8000 0 0x40>; interrupts = ; clocks = <&cpg CPG_MOD 524>; @@ -542,7 +542,7 @@ hscif0: serial@e6540000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6540000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 514>, @@ -558,7 +558,7 @@ hscif1: serial@e6550000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6550000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 515>, @@ -574,7 +574,7 @@ hscif2: serial@e6560000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe6560000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 516>, @@ -590,7 +590,7 @@ hscif3: serial@e66a0000 { compatible = "renesas,hscif-r8a779a0", - "renesas,rcar-gen3-hscif", "renesas,hscif"; + "renesas,rcar-gen4-hscif", "renesas,hscif"; reg = <0 0xe66a0000 0 0x60>; interrupts = ; clocks = <&cpg CPG_MOD 517>, @@ -943,7 +943,7 @@ scif0: serial@e6e60000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 702>, @@ -959,7 +959,7 @@ scif1: serial@e6e68000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 703>, @@ -975,7 +975,7 @@ scif3: serial@e6c50000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 704>, @@ -991,7 +991,7 @@ scif4: serial@e6c40000 { compatible = "renesas,scif-r8a779a0", - "renesas,rcar-gen3-scif", "renesas,scif"; + "renesas,rcar-gen4-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 705>, @@ -2003,7 +2003,8 @@ }; dmac1: dma-controller@e7350000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7350000 0 0x1000>, <0 0xe7300000 0 0x10000>; interrupts = , @@ -2037,7 +2038,8 @@ }; dmac2: dma-controller@e7351000 { - compatible = "renesas,dmac-r8a779a0"; + compatible = "renesas,dmac-r8a779a0", + "renesas,rcar-gen4-dmac"; reg = <0 0xe7351000 0 0x1000>, <0 0xe7310000 0 0x10000>; interrupts = , @@ -2092,7 +2094,8 @@ }; ipmmu_rt0: iommu@ee480000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee480000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 10>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2100,7 +2103,8 @@ }; ipmmu_rt1: iommu@ee4c0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xee4c0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 19>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2108,7 +2112,8 @@ }; ipmmu_ds0: iommu@eed00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 0>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2116,7 +2121,8 @@ }; ipmmu_ds1: iommu@eed40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 1>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2124,7 +2130,8 @@ }; ipmmu_ir: iommu@eed80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeed80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 3>; power-domains = <&sysc R8A779A0_PD_A3IR>; @@ -2132,7 +2139,8 @@ }; ipmmu_vc0: iommu@eedc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeedc0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 12>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2140,7 +2148,8 @@ }; ipmmu_vi0: iommu@eee80000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee80000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 14>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2148,7 +2157,8 @@ }; ipmmu_vi1: iommu@eeec0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeeec0000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 15>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2156,7 +2166,8 @@ }; ipmmu_3dg: iommu@eee00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeee00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 6>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2164,7 +2175,8 @@ }; ipmmu_vip0: iommu@eef00000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef00000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 5>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2172,7 +2184,8 @@ }; ipmmu_vip1: iommu@eef40000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeef40000 0 0x20000>; renesas,ipmmu-main = <&ipmmu_mm 11>; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -2180,7 +2193,8 @@ }; ipmmu_mm: iommu@eefc0000 { - compatible = "renesas,ipmmu-r8a779a0"; + compatible = "renesas,ipmmu-r8a779a0", + "renesas,rcar-gen4-ipmmu-vmsa"; reg = <0 0xeefc0000 0 0x20000>; interrupts = , ; -- cgit v1.2.3 From fb1929b98f2e1c012b4df596b7b2c9f6f28fbe54 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Wed, 4 May 2022 10:44:56 +0100 Subject: arm64: dts: renesas: Add initial DTSI for RZ/V2M SoC Details of the SoC can be found here: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220504094456.24386-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 93 ++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011.dtsi (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi new file mode 100644 index 000000000000..27810f4ad4cb --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g011"; + #address-cells = <2>; + #size-cells = <2>; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + }; + }; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0>; + device_type = "cpu"; + clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@82000000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0x82010000 0 0x1000>, + <0x0 0x82020000 0 0x20000>, + <0x0 0x82040000 0 0x20000>, + <0x0 0x82060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>; + clock-names = "clk"; + }; + + cpg: clock-controller@a3500000 { + compatible = "renesas,r9a09g011-cpg"; + reg = <0 0xa3500000 0 0x1000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + uart0: serial@a4040000 { + compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; + reg = <0 0xa4040000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>, + <&cpg CPG_MOD R9A09G011_URT_PCLK>; + clock-names = "sclk", "pclk"; + status = "disabled"; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- cgit v1.2.3 From ad1bd2bf658062c6edc5ff1ee1725565a4fc8930 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Tue, 3 May 2022 12:55:57 +0100 Subject: arm64: dts: renesas: Add initial device tree for RZ/V2M EVK Add basic support for RZ/V2M EVK (based on R9A09G011): - memory - External input clock - UART Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-13-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts | 44 +++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 15309309a2e1..e66d76d42e52 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -83,3 +83,5 @@ dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044c2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G044) += r9a07g044l2-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G054) += r9a07g054l2-smarc.dtb + +dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts new file mode 100644 index 000000000000..c207d8ce5523 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2M (r9a09g011) Evaluation Kit Board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r9a09g011.dtsi" + +/ { + model = "RZ/V2M Evaluation Kit 2.0"; + compatible = "renesas,rzv2mevk2", "renesas,r9a09g011"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@58000000 { + device_type = "memory"; + /* + * first 1.25GiB is reserved for ISP Firmware, + * next 128MiB is reserved for secure area. + */ + reg = <0x0 0x58000000 0x0 0x28000000>; + }; + + memory@180000000 { + device_type = "memory"; + reg = <0x1 0x80000000 0x0 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <48000000>; +}; + +&uart0 { + status = "okay"; +}; -- cgit v1.2.3 From 5e9b59bd37371ef1e627b24483c0388a2567cc1c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 22 Mar 2022 11:58:56 +0100 Subject: arm64: dts: uDPU: update partition table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Partition currently called "uboot" does not only contain U-boot, but rather it contains TF-A, U-boot and U-boot environment. So, to avoid accidentally deleting the U-boot environment which is located at 0x180000 split the partition. "uboot" is not the correct name as you can't boot these boards with U-boot only, TF-A must be present as well, so rename the "uboot" partition to "firmware". While we are here, describe the NOR node as "spi-flash@0" instead of "m25p80@0" which is the old SPI-NOR driver name. This won't break booting for existing devices as the SoC-s BootROM is not partition aware at all, it will simply try booting from 0x0 of the boot device that is set by bootstrap pins. This will however prevent accidental or automated flashing of just U-boot to the partition. Signed-off-by: Robert Marko Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index 95d46e8d081c..ac64949bb53e 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -99,7 +99,7 @@ pinctrl-names = "default"; pinctrl-0 = <&spi_quad_pins>; - m25p80@0 { + spi-flash@0 { compatible = "jedec,spi-nor"; reg = <0>; spi-max-frequency = <54000000>; @@ -108,10 +108,15 @@ compatible = "fixed-partitions"; #address-cells = <1>; #size-cells = <1>; - /* only bootloader is located on the SPI */ + partition@0 { - label = "uboot"; - reg = <0 0x400000>; + label = "firmware"; + reg = <0x0 0x180000>; + }; + + partition@180000 { + label = "u-boot-env"; + reg = <0x180000 0x10000>; }; }; }; -- cgit v1.2.3 From e4fde76fa54a6f13da7fd5fd6601474c16c54d8d Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 22 Mar 2022 11:58:57 +0100 Subject: arm64: dts: uDPU: correct temperature sensors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit uDPU has a pair of NCT375 temperature sensors, which are TMP75C compatible as far as the driver is concerned. The current LM75 compatible worked as all of the LM75 compatible sensors are backwards compatible with the original part, but it meant that lower resolution and incorrect sample rate was being used. The "lm75" compatible has been deprecated anyway and is meant as fallback in order to keep older DTS-es working. Signed-off-by: Robert Marko Reviewed-by: Pali Rohár Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts index ac64949bb53e..1f534c0c65f7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts @@ -153,15 +153,15 @@ scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - lm75@48 { + nct375@48 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x48>; }; - lm75@49 { + nct375@49 { status = "okay"; - compatible = "lm75"; + compatible = "ti,tmp75c"; reg = <0x49>; }; }; -- cgit v1.2.3 From 5202f4c3816b42e989f9cad49a73c7e88fba89f4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:17 +0200 Subject: arm64: dts: marvell: espressobin-ultra: fix SPI-NOR config SPI config for the SPI-NOR is incorrect and completely breaking reading/writing to the onboard SPI-NOR. SPI-NOR is connected in the single(x1) IO mode and not in the quad (x4) mode. Also, there is no need to override the max frequency from the DTSI as the mx25u3235f that is used supports 104Mhz. Fixes: 3404fe15a60f ("arm64: dts: marvell: add DT for ESPRESSObin-Ultra") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 4 ---- 1 file changed, 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index c5eb3604dd5b..610ff6f385c7 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -71,10 +71,6 @@ &spi0 { flash@0 { - spi-max-frequency = <108000000>; - spi-rx-bus-width = <4>; - spi-tx-bus-width = <4>; - partitions { compatible = "fixed-partitions"; #address-cells = <1>; -- cgit v1.2.3 From e836070f94619af5325fd69d3fb48bd1a9e569b4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:18 +0200 Subject: arm64: dts: marvell: espressobin-ultra: add PHY and switch reset pins Both the Topaz switch and 88E1512 PHY have their reset and interrupts connected to the SoC. So, define the Topaz and 88E1512 reset pins in the DTS. Defining the interrupt pins wont work as both the 88E1512 and the Topaz switch uses active LOW IRQ signals but the A37xx GPIO controller only supports edge triggers. 88E1512 would require special setup anyway as its INT pin is shared with the LED2 and you first need to configure it as INT. Signed-off-by: Robert Marko Reviewed-by: Andrew Lunn Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 610ff6f385c7..7c786d218f1b 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -114,12 +114,16 @@ &mdio { extphy: ethernet-phy@1 { reg = <1>; + + reset-gpios = <&gpionb 2 GPIO_ACTIVE_LOW>; }; }; &switch0 { reg = <3>; + reset-gpios = <&gpiosb 23 GPIO_ACTIVE_LOW>; + ports { switch0port1: port@1 { reg = <1>; -- cgit v1.2.3 From eacec7ebc16cf5d2f6a6c7cf5d57156da2c3e98f Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 28 Sep 2021 19:09:19 +0200 Subject: arm64: dts: marvell: espressobin-ultra: enable front USB3 port Espressobin Ultra has a front panel USB3.0 Type-A port which works just fine so enable it. I dont see a reason why it was disabled in the first place anyway. Fixes: 3404fe15a60f ("arm64: dts: marvell: add DT for ESPRESSObin-Ultra") Signed-off-by: Robert Marko Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts index 7c786d218f1b..070725b81be5 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin-ultra.dts @@ -108,7 +108,6 @@ &usb3 { usb-phy = <&usb3_phy>; - status = "disabled"; }; &mdio { -- cgit v1.2.3 From 239466bddfc02f9643f64be74ba9a1d80c286f4b Mon Sep 17 00:00:00 2001 From: Chris Packham Date: Wed, 30 Mar 2022 11:05:43 +1300 Subject: arm64: dts: marvell: Update sdhci node names to match schema Update the node names of the sdhci@ interfaces to be mmc@ to match the node name enforced by the mmc-controller.yaml schema. Signed-off-by: Chris Packham Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 4 ++-- arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 2 +- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 8c8bb97c9d30..df152c72276b 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -444,7 +444,7 @@ #mbox-cells = <1>; }; - sdhci1: sdhci@d0000 { + sdhci1: mmc@d0000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; reg = <0xd0000 0x300>, @@ -455,7 +455,7 @@ status = "disabled"; }; - sdhci0: sdhci@d8000 { + sdhci0: mmc@d8000 { compatible = "marvell,armada-3700-sdhci", "marvell,sdhci-xenon"; reg = <0xd8000 0x300>, diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi index 6614472100c2..a06a0a889c43 100644 --- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi @@ -250,7 +250,7 @@ interrupts = ; }; - ap_sdhci0: sdhci@6e0000 { + ap_sdhci0: mmc@6e0000 { compatible = "marvell,armada-ap806-sdhci"; reg = <0x6e0000 0x300>; interrupts = ; diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi index 3bd2182817fb..d6c0990a267d 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -493,7 +493,7 @@ status = "okay"; }; - CP11X_LABEL(sdhci0): sdhci@780000 { + CP11X_LABEL(sdhci0): mmc@780000 { compatible = "marvell,armada-cp110-sdhci"; reg = <0x780000 0x300>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH>; -- cgit v1.2.3 From 34f7c6e7d4396090692a09789db231e12cb4762b Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Tue, 20 Apr 2021 14:38:27 +0900 Subject: arm64: dts: visconti: Add clock controller support for TMPV7708 Adds node of clock controller support for Toshiba Visconti TMPV7708. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220421080143.2135566-1-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 01d7ee61ad25..1683113a3c43 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -7,6 +7,7 @@ * */ +#include #include #include @@ -182,6 +183,12 @@ #clock-cells = <0>; }; + osc2_clk: osc2-clk { + compatible = "fixed-clock"; + clock-frequency = <20000000>; + #clock-cells = <0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; @@ -216,6 +223,20 @@ interrupt-parent = <&gic>; }; + pipllct: clock-controller@24220000 { + compatible = "toshiba,tmpv7708-pipllct"; + reg = <0 0x24220000 0 0x820>; + #clock-cells = <1>; + clocks = <&osc2_clk>; + }; + + pismu: syscon@24200000 { + compatible = "toshiba,tmpv7708-pismu", "syscon"; + reg = <0 0x24200000 0 0x2140>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + uart0: serial@28200000 { compatible = "arm,pl011", "arm,primecell"; reg = <0 0x28200000 0 0x1000>; -- cgit v1.2.3 From 4374055674eaf52c185c24fcbeb6cf7d6359bfc4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: arm64: dts: visconti: Update the clock providers for UART Remove fixed clock and source common clock for UART. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-2-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 4 ---- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts | 4 ---- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 14 ++++++++------ 3 files changed, 8 insertions(+), 14 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 9375b0faeea2..9b0666df6593 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -32,14 +32,10 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &piether { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index d0817463706e..56701e0e1dab 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -32,14 +32,10 @@ &uart0 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &uart1 { status = "okay"; - clocks = <&uart_clk>; - clock-names = "apb_pclk"; }; &piether { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 1683113a3c43..3b51e875630c 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -129,12 +129,6 @@ ; }; - uart_clk: uart-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - clk25mhz: clk25mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -243,6 +237,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart0_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART0>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -252,6 +248,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -261,6 +259,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart2_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -270,6 +270,8 @@ interrupts = ; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; + clocks = <&pismu TMPV770X_CLK_PIUART2>; + clock-names = "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From 0e7cd4395be5f433b70bde8d902ed50484ee1bc1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: arm64: dts: visconti: Update the clock providers for I2C Replace I2C clock with common clock framework. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-3-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 1 - arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 9 +++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index f0a93db6dde6..03827ce06ee3 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -40,5 +40,4 @@ &i2c0 { status = "okay"; - clocks = <&clk150mhz>; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 3b51e875630c..048b5dc7ae18 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -284,6 +284,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C0>; status = "disabled"; }; @@ -296,6 +297,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C1>; status = "disabled"; }; @@ -308,6 +310,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C2>; status = "disabled"; }; @@ -320,6 +323,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C3>; status = "disabled"; }; @@ -332,6 +336,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C4>; status = "disabled"; }; @@ -344,6 +349,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C5>; status = "disabled"; }; @@ -356,6 +362,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C6>; status = "disabled"; }; @@ -368,6 +375,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C7>; status = "disabled"; }; @@ -380,6 +388,7 @@ clock-frequency = <400000>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PII2C8>; status = "disabled"; }; -- cgit v1.2.3 From 27b754902dab93d1c3bde94e97983ca0fe81f253 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: arm64: dts: visconti: Update the clock providers for watchdog timer Remove fixed clock and source common clock for watchdog timer. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-4-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 1 - arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 1 - arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 7 +------ 3 files changed, 1 insertion(+), 8 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 9b0666df6593..45ddf6f03175 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -58,7 +58,6 @@ &wdt { status = "okay"; - clocks = <&wdt_clk>; }; &gpio { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index 03827ce06ee3..adfe8406c24c 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -13,7 +13,6 @@ &wdt { status = "okay"; - clocks = <&wdt_clk>; }; &gpio { diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 048b5dc7ae18..6050796a1678 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -171,12 +171,6 @@ clock-output-names = "extclk100mhz"; }; - wdt_clk: wdt-clk { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - }; - osc2_clk: osc2-clk { compatible = "fixed-clock"; clock-frequency = <20000000>; @@ -490,6 +484,7 @@ wdt: wdt@28330000 { compatible = "toshiba,visconti-wdt"; reg = <0 0x28330000 0 0x1000>; + clocks = <&pismu TMPV770X_CLK_WDTCLK>; status = "disabled"; }; -- cgit v1.2.3 From 340657b179165410ec6ca30db6e6d7fc5c366ca1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 22 Apr 2022 11:39:44 +0900 Subject: arm64: dts: visconti: Update the clock providers for SPI Remove fixed clock and source common clock for SPI. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-5-nobuhiro1.iwamatsu@toshiba.co.jp/ --- .../boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 21 ++++++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi index adfe8406c24c..0c8321022a73 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrc.dtsi @@ -25,8 +25,6 @@ &spi0 { status = "okay"; - clocks = <&clk300mhz>, <&clk150mhz>; - clock-names = "sspclk", "apb_pclk"; mmc-slot@0 { compatible = "mmc-spi-slot"; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 6050796a1678..196cda7b5d90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -143,13 +143,6 @@ clock-output-names = "clk125mhz"; }; - clk150mhz: clk150mhz { - compatible = "fixed-clock"; - clock-frequency = <150000000>; - #clock-cells = <0>; - clock-output-names = "clk150mhz"; - }; - clk300mhz: clk300mhz { compatible = "fixed-clock"; clock-frequency = <300000000>; @@ -395,6 +388,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -407,6 +402,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI1>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -419,6 +416,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI2>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -431,6 +430,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI3>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -443,6 +444,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI4>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -455,6 +458,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI5>; + clock-names = "apb_pclk"; status = "disabled"; }; @@ -467,6 +472,8 @@ num-cs = <1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&pismu TMPV770X_CLK_PISPI6>; + clock-names = "apb_pclk"; status = "disabled"; }; -- cgit v1.2.3 From c8a93f913109e575f3b9ddc330f210aa3d3cf2e1 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Fri, 22 Apr 2022 23:12:54 +0900 Subject: arm64: dts: visconti: Update the clock providers for ethernet device Remove fixed clock and source common clock for ethernet device. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-6-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 16 ++-------------- 3 files changed, 2 insertions(+), 18 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 45ddf6f03175..527bb437dd90 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -42,8 +42,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - clocks = <&clk300mhz>, <&clk125mhz>; - clock-names = "stmmaceth", "phy_ref_clk"; mdio0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts index 56701e0e1dab..ed7aa7e457b1 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-visrobo-vrb.dts @@ -42,8 +42,6 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "rgmii-id"; - clocks = <&clk300mhz>, <&clk125mhz>; - clock-names = "stmmaceth", "phy_ref_clk"; mdio0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 196cda7b5d90..7c80a9434e10 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -136,20 +136,6 @@ clock-output-names = "clk25mhz"; }; - clk125mhz: clk125mhz { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - #clock-cells = <0>; - clock-output-names = "clk125mhz"; - }; - - clk300mhz: clk300mhz { - compatible = "fixed-clock"; - clock-frequency = <300000000>; - #clock-cells = <0>; - clock-output-names = "clk300mhz"; - }; - clk600mhz: clk600mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -485,6 +471,8 @@ snps,txpbl = <4>; snps,rxpbl = <4>; snps,tso; + clocks = <&pismu TMPV770X_CLK_PIETHER_BUS>, <&pismu TMPV770X_CLK_PIETHER_125M>; + clock-names = "stmmaceth", "phy_ref_clk"; status = "disabled"; }; -- cgit v1.2.3 From 5d3b6ede2c6c80304944cdb5bc653957390afcf4 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 21 Apr 2022 16:38:05 +0900 Subject: arm64: dts: visconti: Update the clock providers for PCIe host controller Remove fixed clock and source common clock for PCIe host controller. Signed-off-by: Nobuhiro Iwamatsu Link: https://lore.kernel.org/r/20220510015229.139818-7-nobuhiro1.iwamatsu@toshiba.co.jp/ --- arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts | 2 -- arch/arm64/boot/dts/toshiba/tmpv7708.dtsi | 16 ++-------------- 2 files changed, 2 insertions(+), 16 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts index 527bb437dd90..d209fdc98597 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts +++ b/arch/arm64/boot/dts/toshiba/tmpv7708-rm-mbrc.dts @@ -72,6 +72,4 @@ &pcie { status = "okay"; - clocks = <&extclk100mhz>, <&clk600mhz>, <&clk25mhz>; - clock-names = "ref", "core", "aux"; }; diff --git a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi index 7c80a9434e10..0fc32c036f30 100644 --- a/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi +++ b/arch/arm64/boot/dts/toshiba/tmpv7708.dtsi @@ -129,20 +129,6 @@ ; }; - clk25mhz: clk25mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "clk25mhz"; - }; - - clk600mhz: clk600mhz { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <600000000>; - clock-output-names = "clk600mhz"; - }; - extclk100mhz: extclk100mhz { compatible = "fixed-clock"; #clock-cells = <0>; @@ -520,6 +506,8 @@ 0 0 0 3 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &gic GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; max-link-speed = <2>; + clocks = <&extclk100mhz>, <&pismu TMPV770X_CLK_PCIE_MSTR>, <&pismu TMPV770X_CLK_PCIE_AUX>; + clock-names = "ref", "core", "aux"; status = "disabled"; }; }; -- cgit v1.2.3 From bc405bb3eeee4b711830ab569e7f3811b92196ab Mon Sep 17 00:00:00 2001 From: Michael Riesch Date: Mon, 25 Apr 2022 15:35:00 +0200 Subject: arm64: dts: rockchip: enable otg/drd operation of usb_host0_xhci in rk356x This USB 3.0 controller is capable of OTG/DRD operation. Enable it in the device tree. Signed-off-by: Michael Riesch Link: https://lore.kernel.org/r/20220425133502.405512-1-michael.riesch@wolfvision.net Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk356x.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi index 3f0e11af738d..1042e68602de 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi @@ -266,7 +266,7 @@ <&cru ACLK_USB3OTG0>; clock-names = "ref_clk", "suspend_clk", "bus_clk"; - dr_mode = "host"; + dr_mode = "otg"; phy_type = "utmi_wide"; power-domains = <&power RK3568_PD_PIPE>; resets = <&cru SRST_USB3OTG0>; -- cgit v1.2.3 From c88fd98110242ed56b24284dd975fe54f2f65756 Mon Sep 17 00:00:00 2001 From: Dang Huynh Date: Mon, 25 Apr 2022 13:48:51 +0700 Subject: arm64: dts: mediatek: pumpkin: Remove input-name property This property doesn't seem to exist in the documentation nor in source code, but for some reason it is defined in a bunch of device trees. Signed-off-by: Dang Huynh Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220425064850.246228-1-danct12@riseup.net Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi index fcddec14738d..7a717f926929 100644 --- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi +++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi @@ -25,7 +25,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_default>; -- cgit v1.2.3 From 7d029cc240a012f0259477c905e84f3975d7cf2f Mon Sep 17 00:00:00 2001 From: Rui Salvaterra Date: Fri, 29 Apr 2022 09:42:25 +0100 Subject: arm64: dts: mt7622: specify the number of DMA requests The MT7622 device tree never bothered to specify the number of virtual DMA channels for the HSDMA controller, always falling back to the default value of 3. Make this value explicit, in order to avoid the following dmesg notification: mtk_hsdma 1b007000.dma-controller: Using 3 as missing dma-requests property Signed-off-by: Rui Salvaterra Link: https://lore.kernel.org/r/20220429084225.298213-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + 1 file changed, 1 insertion(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 6f8cb3ad1e84..da1f88d06dcc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -917,6 +917,7 @@ clock-names = "hsdma"; power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; #dma-cells = <1>; + dma-requests = <3>; }; eth: ethernet@1b100000 { -- cgit v1.2.3 From 80dd27b6c68c7189b865b4b966aa12c77d1adc1e Mon Sep 17 00:00:00 2001 From: Rui Salvaterra Date: Thu, 28 Apr 2022 23:57:55 +0100 Subject: arm64: dts: mt7622: specify the L2 cache topology On an MT7622 system, the kernel complains of not being able to detect the cache hierarchy of CPU 0. Specify the shared L2 cache node in the device tree, in order to fix this. Signed-off-by: Rui Salvaterra Link: https://lore.kernel.org/r/20220428225755.785153-1-rsalvaterra@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index da1f88d06dcc..5551f004945b 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -80,6 +80,7 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -94,6 +95,12 @@ enable-method = "psci"; clock-frequency = <1300000000>; cci-control-port = <&cci_control2>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; }; }; -- cgit v1.2.3 From 41d2d562e89cb9b9558242653862a932fd877f9a Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 18:47:55 +0200 Subject: arm64: dts: mediatek: mt8183-pumpkin: fix bad thermistor node name Fix the following dtbs_check error by using the correct node name: /home/fabo/build/linux/mt8183-pumpkin/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dtb: ntc: $nodename:0: 'ntc' does not match '^thermistor(.*)?$' From schema: /home/fabo/devel/baylibre/linux-mainline/Documentation/devicetree/bindings/hwmon/ntc-thermistor.yaml Signed-off-by: Fabien Parent Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Mattijs Korpershoek Link: https://lore.kernel.org/r/20220426164755.435372-1-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index ee912825cfc6..afeb5cd37826 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -55,7 +55,7 @@ }; }; - ntc { + thermistor { compatible = "murata,ncp03wf104"; pullup-uv = <1800000>; pullup-ohm = <390000>; -- cgit v1.2.3 From 8a87419481f2d51a7bd03617d363faf5f2b0e1b3 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 15:41:04 +0200 Subject: arm64: dts: mediatek: mt8195-demo: Remove input-name property This property doesn't seem to exist in the documentation nor in source code, let's remove it from the device-tree. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20220426134106.242353-7-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index def3fc26cb99..6606c7fe8db3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -34,7 +34,6 @@ gpio-keys { compatible = "gpio-keys"; - input-name = "gpio-keys"; pinctrl-names = "default"; pinctrl-0 = <&gpio_keys_pins>; -- cgit v1.2.3 From 7640d4350ae89df0ef142144c93e0ae48d623b69 Mon Sep 17 00:00:00 2001 From: Fabien Parent Date: Tue, 26 Apr 2022 15:41:05 +0200 Subject: arm64: dts: mediatek: mt8195-demo: enable uart1 The UART1 is exposed on a header. Enable the uart1 node to be able to use it. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20220426134106.242353-8-fparent@baylibre.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index 6606c7fe8db3..4fbd99eb496a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -406,6 +406,12 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + &u3phy0 { status = "okay"; }; -- cgit v1.2.3 From 5ba090a03af2074841342bbe5fee45260ec62144 Mon Sep 17 00:00:00 2001 From: Chuanhong Guo Date: Sun, 24 Apr 2022 11:25:27 +0800 Subject: arm64: dts: mediatek: add mtk-snfi for mt7622 This patch adds a device-tree node for the MTK SPI-NAND Flash Interface for MT7622 device tree. Signed-off-by: Chuanhong Guo Link: https://lore.kernel.org/r/20220424032527.673605-6-gch981213@gmail.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index 5551f004945b..9768523fe4c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -552,6 +552,18 @@ status = "disabled"; }; + snfi: spi@1100d000 { + compatible = "mediatek,mt7622-snand"; + reg = <0 0x1100d000 0 0x1000>; + interrupts = ; + clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; + clock-names = "nfi_clk", "pad_clk"; + nand-ecc-engine = <&bch>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + bch: ecc@1100e000 { compatible = "mediatek,mt7622-ecc"; reg = <0 0x1100e000 0 0x1000>; -- cgit v1.2.3 From c75104762ddace5973deb4ea54d35bf2b64bba98 Mon Sep 17 00:00:00 2001 From: "Nícolas F. R. A. Prado" Date: Wed, 4 May 2022 17:45:16 -0400 Subject: arm64: dts: mt8192: Follow binding order for SCP registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dt-binding for SCP documents the reg-names order as sram, cfg, l1tcm. Update the SCP node on the mt8192 devicetree to follow that order, which gets rid of a dtbs_check warning. This doesn't change any behavior since the SCP driver accesses the memory regions through the names anyway. Fixes: c63556ec6bfe ("arm64: dts: mt8192: Add SCP node") Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20220504214516.2957504-1-nfraprado@collabora.com Signed-off-by: Matthias Brugger --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'arch/arm64') diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 26dbe9ecc528..733aec2e7f77 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -699,9 +699,9 @@ scp: scp@10500000 { compatible = "mediatek,mt8192-scp"; reg = <0 0x10500000 0 0x100000>, - <0 0x10700000 0 0x8000>, - <0 0x10720000 0 0xe0000>; - reg-names = "sram", "l1tcm", "cfg"; + <0 0x10720000 0 0xe0000>, + <0 0x10700000 0 0x8000>; + reg-names = "sram", "cfg", "l1tcm"; interrupts = ; clocks = <&infracfg CLK_INFRA_SCPSYS>; clock-names = "main"; -- cgit v1.2.3