From 0207a2efb43d81e29e23662b5d035945688a103f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Thu, 16 Apr 2009 14:40:56 +0900 Subject: sh: Add support for SH7724 (SH-Mobile R2R) CPU subtype. This implements initial support for the SH-Mobile R2R CPU. Based on Rev 0.11 of the initial SH7724 hardware manual. Signed-off-by: Kuninori Morimoto Signed-off-by: Paul Mundt --- arch/sh/kernel/setup.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch/sh/kernel/setup.c') diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 04a6004fccc4..0e6ed804546e 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -435,7 +435,8 @@ static const char *cpu_name[] = { [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", - [CPU_SH7366] = "SH7366", [CPU_SH_NONE] = "Unknown" + [CPU_SH7366] = "SH7366", [CPU_SH7724] = "SH7724", + [CPU_SH_NONE] = "Unknown" }; const char *get_cpu_subtype(struct sh_cpuinfo *c) -- cgit v1.2.3 From 87a00dc059e3af46303f1f56b0e8df41af988c7b Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Wed, 15 Apr 2009 10:50:21 +0000 Subject: sh: Add plat_early_device_setup() Add a plat_early_device_setup() function to allow processor-specific code to register Early Platform Data. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/include/asm/device.h | 2 ++ arch/sh/kernel/setup.c | 7 +++++++ 2 files changed, 9 insertions(+) (limited to 'arch/sh/kernel/setup.c') diff --git a/arch/sh/include/asm/device.h b/arch/sh/include/asm/device.h index efd511d0803a..8688a88303ee 100644 --- a/arch/sh/include/asm/device.h +++ b/arch/sh/include/asm/device.h @@ -10,3 +10,5 @@ struct platform_device; int platform_resource_setup_memory(struct platform_device *pdev, char *name, unsigned long memsize); +void plat_early_device_setup(void); + diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 04a6004fccc4..22b976d42014 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -328,6 +329,10 @@ static int __init parse_elfcorehdr(char *arg) early_param("elfcorehdr", parse_elfcorehdr); #endif +void __init __attribute__ ((weak)) plat_early_device_setup(void) +{ +} + void __init setup_arch(char **cmdline_p) { enable_mmu(); @@ -381,6 +386,8 @@ void __init setup_arch(char **cmdline_p) parse_early_param(); + plat_early_device_setup(); + sh_mv_setup(); /* -- cgit v1.2.3 From 7b551f9daa9bd9533ba4ce31622ed4be1dd97d3e Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Fri, 8 May 2009 22:14:01 +0900 Subject: sh: Kill off the GENERIC_CALIBRATE_DELAY ifndef. Now that everyone is using the clock framework directly and we unconditionally provide our own calibrate_delay() function, having it wrapped in an ifndef is no longer useful. So, kill it off. Signed-off-by: Paul Mundt --- arch/sh/kernel/setup.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'arch/sh/kernel/setup.c') diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 38515a795920..00086b234278 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -156,7 +156,7 @@ static void __init reserve_crashkernel(void) &crash_size, &crash_base); if (ret == 0 && crash_size) { if (crash_base <= 0) { - vp = alloc_bootmem_nopanic(crash_size); + vp = alloc_bootmem_nopanic(crash_size); if (!vp) { printk(KERN_INFO "crashkernel allocation " "failed\n"); @@ -185,7 +185,6 @@ static inline void __init reserve_crashkernel(void) {} #endif -#ifndef CONFIG_GENERIC_CALIBRATE_DELAY void __cpuinit calibrate_delay(void) { struct clk *clk = clk_get(NULL, "cpu_clk"); @@ -201,7 +200,6 @@ void __cpuinit calibrate_delay(void) (loops_per_jiffy/(5000/HZ)) % 100, loops_per_jiffy); } -#endif void __init __add_active_range(unsigned int nid, unsigned long start_pfn, unsigned long end_pfn) -- cgit v1.2.3 From eb9b9b56eed280e65a9e194aaeb50a5a75111859 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Thu, 28 May 2009 11:51:51 +0000 Subject: sh: boot word / mode pin support V2 Add mode pin support for the SuperH architecture V2. With this patch applied the board code can add their own function to export the cpu mode pin configuration. In most cases this will be a constant bitmap, but boards that allow reading this from a register can instead read out the pin state from hardware. The code warns if a pin is tested but no board specific mode pin function has been provided. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/include/asm/machvec.h | 1 + arch/sh/include/asm/processor.h | 4 ++++ arch/sh/kernel/machvec.c | 1 + arch/sh/kernel/setup.c | 12 ++++++++++++ 4 files changed, 18 insertions(+) (limited to 'arch/sh/kernel/setup.c') diff --git a/arch/sh/include/asm/machvec.h b/arch/sh/include/asm/machvec.h index 73d6d16fa06b..84dd37761f56 100644 --- a/arch/sh/include/asm/machvec.h +++ b/arch/sh/include/asm/machvec.h @@ -48,6 +48,7 @@ struct sh_machine_vector { void (*mv_ioport_unmap)(void __iomem *); int (*mv_clk_init)(void); + int (*mv_mode_pins)(void); }; extern struct sh_machine_vector sh_mv; diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index 005c962c8b1c..fb67482e47eb 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -94,6 +94,10 @@ extern struct pt_regs fake_swapper_regs; const char *get_cpu_subtype(struct sh_cpuinfo *c); extern const struct seq_operations cpuinfo_op; +/* processor boot mode configuration */ +int generic_mode_pins(void); +int test_mode_pin(int pin); + #ifdef CONFIG_VSYSCALL int vsyscall_init(void); #else diff --git a/arch/sh/kernel/machvec.c b/arch/sh/kernel/machvec.c index c1ea41e5812a..548f6607fd0f 100644 --- a/arch/sh/kernel/machvec.c +++ b/arch/sh/kernel/machvec.c @@ -129,6 +129,7 @@ void __init sh_mv_setup(void) mv_set(ioport_map); mv_set(ioport_unmap); mv_set(irq_demux); + mv_set(mode_pins); if (!sh_mv.mv_nr_irqs) sh_mv.mv_nr_irqs = NR_IRQS; diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 00086b234278..050131eec773 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -420,6 +420,18 @@ void __init setup_arch(char **cmdline_p) #endif } +/* processor boot mode configuration */ +int generic_mode_pins(void) +{ + pr_warning("generic_mode_pins(): missing mode pin configuration\n"); + return 0; +} + +int test_mode_pin(int pin) +{ + return sh_mv.mv_mode_pins() & (1 << pin); +} + static const char *cpu_name[] = { [CPU_SH7201] = "SH7201", [CPU_SH7203] = "SH7203", [CPU_SH7263] = "SH7263", -- cgit v1.2.3 From 0d4fdbb64f472ef31195714993f1263f77cf85ca Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 2 Jun 2009 09:22:02 +0000 Subject: sh: rework mode pin code This patch reworks the mode pin code to keep the pin definitions in one place. The mode pins values are now the value of the bit instead of bit number. With this patch in place the sh7785 header file contains mode pin comments. The sh7785 clock code and the sh7785lcr board code are updated to reflect the new shared mode pins. Signed-off-by: Magnus Damm Signed-off-by: Paul Mundt --- arch/sh/boards/board-sh7785lcr.c | 14 ++++++------ arch/sh/include/asm/processor.h | 17 +++++++++++++++ arch/sh/include/cpu-sh4/cpu/sh7785.h | 39 +++++++++++++++++----------------- arch/sh/kernel/cpu/sh4a/clock-sh7785.c | 2 +- arch/sh/kernel/setup.c | 2 +- 5 files changed, 46 insertions(+), 28 deletions(-) (limited to 'arch/sh/kernel/setup.c') diff --git a/arch/sh/boards/board-sh7785lcr.c b/arch/sh/boards/board-sh7785lcr.c index c2894c5b71ea..7be56fb06c1f 100644 --- a/arch/sh/boards/board-sh7785lcr.c +++ b/arch/sh/boards/board-sh7785lcr.c @@ -330,13 +330,13 @@ static int sh7785lcr_mode_pins(void) * If you change these dip switches then you will need to * adjust the values below as well. */ - value |= 1 << MODE_PIN_MODE4; /* Clock Mode 16 */ - value |= 1 << MODE_PIN_MODE5; /* 32-bit Area0 bus width */ - value |= 1 << MODE_PIN_MODE6; /* 32-bit Area0 bus width */ - value |= 1 << MODE_PIN_MODE7; /* Area 0 SRAM interface [fixed] */ - value |= 1 << MODE_PIN_MODE8; /* Little Endian */ - value |= 1 << MODE_PIN_MODE9; /* Master Mode */ - value |= 1 << MODE_PIN_MODE14; /* No PLL step-up */ + value |= MODE_PIN4; /* Clock Mode 16 */ + value |= MODE_PIN5; /* 32-bit Area0 bus width */ + value |= MODE_PIN6; /* 32-bit Area0 bus width */ + value |= MODE_PIN7; /* Area 0 SRAM interface [fixed] */ + value |= MODE_PIN8; /* Little Endian */ + value |= MODE_PIN9; /* Master Mode */ + value |= MODE_PIN14; /* No PLL step-up */ return value; } diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h index fb67482e47eb..ff7daaf9a620 100644 --- a/arch/sh/include/asm/processor.h +++ b/arch/sh/include/asm/processor.h @@ -95,6 +95,23 @@ const char *get_cpu_subtype(struct sh_cpuinfo *c); extern const struct seq_operations cpuinfo_op; /* processor boot mode configuration */ +#define MODE_PIN0 (1 << 0) +#define MODE_PIN1 (1 << 1) +#define MODE_PIN2 (1 << 2) +#define MODE_PIN3 (1 << 3) +#define MODE_PIN4 (1 << 4) +#define MODE_PIN5 (1 << 5) +#define MODE_PIN6 (1 << 6) +#define MODE_PIN7 (1 << 7) +#define MODE_PIN8 (1 << 8) +#define MODE_PIN9 (1 << 9) +#define MODE_PIN10 (1 << 10) +#define MODE_PIN11 (1 << 11) +#define MODE_PIN12 (1 << 12) +#define MODE_PIN13 (1 << 13) +#define MODE_PIN14 (1 << 14) +#define MODE_PIN15 (1 << 15) + int generic_mode_pins(void); int test_mode_pin(int pin); diff --git a/arch/sh/include/cpu-sh4/cpu/sh7785.h b/arch/sh/include/cpu-sh4/cpu/sh7785.h index 89afaa6dc2d8..9dc9d91e0a8e 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7785.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7785.h @@ -1,25 +1,26 @@ #ifndef __ASM_SH7785_H__ #define __ASM_SH7785_H__ -/* Boot Mode Pins, more information in sh7785 manual Rev.1.00, page 1628 */ -enum { - MODE_PIN_MODE0, /* CPG - Initial Pck/Bck Frequency [FRQMR1] */ - MODE_PIN_MODE1, /* CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] */ - MODE_PIN_MODE2, /* CPG - Reserved (L: Normal operation) */ - MODE_PIN_MODE3, /* CPG - Reserved (L: Normal operation) */ - MODE_PIN_MODE4, /* CPG - Initial PLL setting (72x/36x) */ - MODE_PIN_MODE5, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] */ - MODE_PIN_MODE6, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] */ - MODE_PIN_MODE7, /* LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] */ - MODE_PIN_MODE8, /* LBSC - Endian Mode (L: Big, H: Little) [BCR.31] */ - MODE_PIN_MODE9, /* LBSC - Master/Slave Mode (L: Slave) [BCR.30] */ - MODE_PIN_MODE10, /* CPG - Clock Input (L: Ext Clk, H: Crystal) */ - MODE_PIN_MODE11, /* PCI - Pin Mode (LL: PCI host, LH: PCI slave) */ - MODE_PIN_MODE12, /* PCI - Pin Mode (HL: Local bus, HH: DU) */ - MODE_PIN_MODE13, /* Boot Address Mode (L: 29-bit, H: 32-bit) */ - MODE_PIN_MODE14, /* Reserved (H: Normal operation) */ - MODE_PIN_MPMD, /* Emulation Mode (L: Emulation mode, H: LSI mode) */ -}; +/* Boot Mode Pins: + * + * MODE0: CPG - Initial Pck/Bck Frequency [FRQMR1] + * MODE1: CPG - Initial Uck/SHck/DDRck Frequency [FRQMR1] + * MODE2: CPG - Reserved (L: Normal operation) + * MODE3: CPG - Reserved (L: Normal operation) + * MODE4: CPG - Initial PLL setting (72x/36x) + * MODE5: LBSC - Area0 Memory Type / Bus Width [CS0BCR.8] + * MODE6: LBSC - Area0 Memory Type / Bus Width [CS0BCR.9] + * MODE7: LBSC - Area0 Memory Type / Bus Width [CS0BCR.3] + * MODE8: LBSC - Endian Mode (L: Big, H: Little) [BCR.31] + * MODE9: LBSC - Master/Slave Mode (L: Slave) [BCR.30] + * MODE10: CPG - Clock Input (L: Ext Clk, H: Crystal) + * MODE11: PCI - Pin Mode (LL: PCI host, LH: PCI slave) + * MODE12: PCI - Pin Mode (HL: Local bus, HH: DU) + * MODE13: Boot Address Mode (L: 29-bit, H: 32-bit) + * MODE14: Reserved (H: Normal operation) + * + * More information in sh7785 manual Rev.1.00, page 1628. + */ /* Pin Function Controller: * GPIO_FN_xx - GPIO used to select pin function diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c index dae20aca536d..73abfbf2f16d 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7785.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7785.c @@ -32,7 +32,7 @@ static unsigned long pll_recalc(struct clk *clk) { int multiplier; - multiplier = test_mode_pin(MODE_PIN_MODE4) ? 36 : 72; + multiplier = test_mode_pin(MODE_PIN4) ? 36 : 72; return clk->parent->rate * multiplier; } diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c index 050131eec773..dd38338553ef 100644 --- a/arch/sh/kernel/setup.c +++ b/arch/sh/kernel/setup.c @@ -429,7 +429,7 @@ int generic_mode_pins(void) int test_mode_pin(int pin) { - return sh_mv.mv_mode_pins() & (1 << pin); + return sh_mv.mv_mode_pins() & pin; } static const char *cpu_name[] = { -- cgit v1.2.3