From 3b70d3f84e6f7b23bda18499177c6aa6b8ce7169 Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Sat, 23 Oct 2010 16:48:58 +0000 Subject: omap3: IGEP v2: Remove onenand_setup no-op function Set onenand_setup to NULL instead of adding a no-op function. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 7 ------- 1 file changed, 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 5e035a58b809..20b199fa5a60 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -136,16 +136,9 @@ static struct mtd_partition igep2_onenand_partitions[] = { }, }; -static int igep2_onenand_setup(void __iomem *onenand_base, int freq) -{ - /* nothing is required to be setup for onenand as of now */ - return 0; -} - static struct omap_onenand_platform_data igep2_onenand_data = { .parts = igep2_onenand_partitions, .nr_parts = ARRAY_SIZE(igep2_onenand_partitions), - .onenand_setup = igep2_onenand_setup, .dma_channel = -1, /* disable DMA in OMAP OneNAND driver */ }; -- cgit v1.2.3 From ca561434345cb2b522542467b686716b91aac610 Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Sat, 23 Oct 2010 16:48:59 +0000 Subject: omap3: IGEP v2: Remove igep2_config array omap_board_config_size is implicitly initialized to 0 in plat-omap/common.c, get_config() won't dereference omap_board_config, so we can remove the empty igep2_config array. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 5 ----- 1 file changed, 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 20b199fa5a60..42dcbf4f1602 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -247,9 +247,6 @@ static inline void __init igep2_init_smsc911x(void) static inline void __init igep2_init_smsc911x(void) { } #endif -static struct omap_board_config_kernel igep2_config[] __initdata = { -}; - static struct regulator_consumer_supply igep2_vmmc1_supply = { .supply = "vmmc", }; @@ -486,8 +483,6 @@ static struct platform_device *igep2_devices[] __initdata = { static void __init igep2_init_irq(void) { - omap_board_config = igep2_config; - omap_board_config_size = ARRAY_SIZE(igep2_config); omap2_init_common_hw(m65kxxxxam_sdrc_params, m65kxxxxam_sdrc_params); omap_init_irq(); omap_gpio_init(); -- cgit v1.2.3 From 8e4fad99a3e4330198e44b7ca21c88facab42931 Mon Sep 17 00:00:00 2001 From: Enric Balletbò i Serra Date: Sat, 23 Oct 2010 16:49:00 +0000 Subject: omap3: IGEP v2: Improve igep2_flash_init() function The changes are: - Use 'for' loop instead 'while' loop. - No need to initialize ret to 0, we're assigning it right after. - No need to check for onenandcs < GPMC_CS_NUM here, it will always be true. Signed-off-by: Enric Balletbo i Serra Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-igep0020.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 42dcbf4f1602..fe76b59b13ed 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -152,35 +152,34 @@ static struct platform_device igep2_onenand_device = { static void __init igep2_flash_init(void) { - u8 cs = 0; - u8 onenandcs = GPMC_CS_NUM + 1; + u8 cs = 0; + u8 onenandcs = GPMC_CS_NUM + 1; - while (cs < GPMC_CS_NUM) { - u32 ret = 0; + for (cs = 0; cs < GPMC_CS_NUM; cs++) { + u32 ret; ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); /* Check if NAND/oneNAND is configured */ if ((ret & 0xC00) == 0x800) /* NAND found */ - pr_err("IGEP v2: Unsupported NAND found\n"); + pr_err("IGEP2: Unsupported NAND found\n"); else { ret = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); if ((ret & 0x3F) == (ONENAND_MAP >> 24)) /* ONENAND found */ onenandcs = cs; } - cs++; } + if (onenandcs > GPMC_CS_NUM) { - pr_err("IGEP v2: Unable to find configuration in GPMC\n"); + pr_err("IGEP2: Unable to find configuration in GPMC\n"); return; } - if (onenandcs < GPMC_CS_NUM) { - igep2_onenand_data.cs = onenandcs; - if (platform_device_register(&igep2_onenand_device) < 0) - pr_err("IGEP v2: Unable to register OneNAND device\n"); - } + igep2_onenand_data.cs = onenandcs; + + if (platform_device_register(&igep2_onenand_device) < 0) + pr_err("IGEP2: Unable to register OneNAND device\n"); } #else -- cgit v1.2.3 From 16dffaa1350631efbc6147e55374ca2a75868a88 Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 8 Nov 2010 06:56:14 +0000 Subject: arm: omap: combine zoom2 and zoom3 board-files They are extremely similar anyway, let's get rid of one file. While at that, also remove the empty zoom_config variable. Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Makefile | 4 +- arch/arm/mach-omap2/board-zoom.c | 151 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/board-zoom2.c | 117 ----------------------------- arch/arm/mach-omap2/board-zoom3.c | 133 --------------------------------- 4 files changed, 153 insertions(+), 252 deletions(-) create mode 100644 arch/arm/mach-omap2/board-zoom.c delete mode 100644 arch/arm/mach-omap2/board-zoom2.c delete mode 100644 arch/arm/mach-omap2/board-zoom3.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 60e51bcf53bd..b0810b9abbba 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -144,12 +144,12 @@ obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o \ board-rx51-peripherals.o \ board-rx51-video.o \ hsmmc.o -obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom2.o \ +obj-$(CONFIG_MACH_OMAP_ZOOM2) += board-zoom.o \ board-zoom-peripherals.o \ board-flash.o \ hsmmc.o \ board-zoom-debugboard.o -obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom3.o \ +obj-$(CONFIG_MACH_OMAP_ZOOM3) += board-zoom.o \ board-zoom-peripherals.o \ board-flash.o \ hsmmc.o \ diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c new file mode 100644 index 000000000000..f10766ba7b5e --- /dev/null +++ b/arch/arm/mach-omap2/board-zoom.c @@ -0,0 +1,151 @@ +/* + * Copyright (C) 2009-2010 Texas Instruments Inc. + * Mikkel Christensen + * Felipe Balbi + * + * Modified from mach-omap2/board-ldp.c + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include + +#include "board-flash.h" +#include "mux.h" +#include "sdram-micron-mt46h32m32lf-6.h" +#include "sdram-hynix-h8mbx00u0mer-0em.h" + +static void __init omap_zoom_init_irq(void) +{ + if (machine_is_omap_zoom2()) + omap2_init_common_hw(mt46h32m32lf6_sdrc_params, + mt46h32m32lf6_sdrc_params); + else if (machine_is_omap_zoom3()) + omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, + h8mbx00u0mer0em_sdrc_params); + + omap_init_irq(); + omap_gpio_init(); +} + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + /* WLAN IRQ - GPIO 162 */ + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), + /* WLAN POWER ENABLE - GPIO 101 */ + OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), + /* WLAN SDIO: MMC3 CMD */ + OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 CLK */ + OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + /* WLAN SDIO: MMC3 DAT[0-3] */ + OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static struct mtd_partition zoom_nand_partitions[] = { + /* All the partition sizes are listed in terms of NAND block size */ + { + .name = "X-Loader-NAND", + .offset = 0, + .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "U-Boot-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ + .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ + .mask_flags = MTD_WRITEABLE, /* force read-only */ + }, + { + .name = "Boot Env-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ + .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ + }, + { + .name = "Kernel-NAND", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ + .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ + }, + { + .name = "system", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ + .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ + }, + { + .name = "userdata", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, + { + .name = "cache", + .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ + .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ + }, +}; + +static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { + .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, + .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, + .phy_reset = true, + .reset_gpio_port[0] = -EINVAL, + .reset_gpio_port[1] = 64, + .reset_gpio_port[2] = -EINVAL, +}; + +static void __init omap_zoom_init(void) +{ + if (machine_is_omap_zoom2()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + } else if (machine_is_omap_zoom3()) { + omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); + omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); + usb_ehci_init(&ehci_pdata); + } + + board_nand_init(zoom_nand_partitions, + ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); + zoom_debugboard_init(); + zoom_peripherals_init(); +} + +MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = omap_zoom_init_irq, + .init_machine = omap_zoom_init, + .timer = &omap_timer, +MACHINE_END + +MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = omap_zoom_init_irq, + .init_machine = omap_zoom_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/mach-omap2/board-zoom2.c b/arch/arm/mach-omap2/board-zoom2.c deleted file mode 100644 index 2992a9f3a585..000000000000 --- a/arch/arm/mach-omap2/board-zoom2.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Inc. - * Mikkel Christensen - * - * Modified from mach-omap2/board-ldp.c - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include - -#include "board-flash.h" -#include "mux.h" -#include "sdram-micron-mt46h32m32lf-6.h" - -static void __init omap_zoom2_init_irq(void) -{ - omap2_init_common_hw(mt46h32m32lf6_sdrc_params, - mt46h32m32lf6_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* WLAN IRQ - GPIO 162 */ - OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - /* WLAN POWER ENABLE - GPIO 101 */ - OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* WLAN SDIO: MMC3 CMD */ - OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 CLK */ - OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 DAT[0-3] */ - OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static struct mtd_partition zoom_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { - .name = "X-Loader-NAND", - .offset = 0, - .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "Boot Env-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ - .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ - }, - { - .name = "Kernel-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ - .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ - }, - { - .name = "system", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ - .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ - }, - { - .name = "userdata", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, - { - .name = "cache", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, -}; - -static void __init omap_zoom2_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); - zoom_peripherals_init(); - board_nand_init(zoom_nand_partitions, - ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); - zoom_debugboard_init(); -} - -MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .reserve = omap_reserve, - .init_irq = omap_zoom2_init_irq, - .init_machine = omap_zoom2_init, - .timer = &omap_timer, -MACHINE_END diff --git a/arch/arm/mach-omap2/board-zoom3.c b/arch/arm/mach-omap2/board-zoom3.c deleted file mode 100644 index 5adde12c0395..000000000000 --- a/arch/arm/mach-omap2/board-zoom3.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (C) 2009 Texas Instruments Inc. - * - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include - -#include "board-flash.h" -#include "mux.h" -#include "sdram-hynix-h8mbx00u0mer-0em.h" - -static struct omap_board_config_kernel zoom_config[] __initdata = { -}; - -static struct mtd_partition zoom_nand_partitions[] = { - /* All the partition sizes are listed in terms of NAND block size */ - { - .name = "X-Loader-NAND", - .offset = 0, - .size = 4 * (64 * 2048), /* 512KB, 0x80000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "U-Boot-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ - .size = 10 * (64 * 2048), /* 1.25MB, 0x140000 */ - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - { - .name = "Boot Env-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */ - .size = 2 * (64 * 2048), /* 256KB, 0x40000 */ - }, - { - .name = "Kernel-NAND", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x0200000*/ - .size = 240 * (64 * 2048), /* 30M, 0x1E00000 */ - }, - { - .name = "system", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x2000000 */ - .size = 3328 * (64 * 2048), /* 416M, 0x1A000000 */ - }, - { - .name = "userdata", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1C000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, - { - .name = "cache", - .offset = MTDPART_OFS_APPEND, /* Offset = 0x1E000000*/ - .size = 256 * (64 * 2048), /* 32M, 0x2000000 */ - }, -}; - -static void __init omap_zoom_init_irq(void) -{ - omap_board_config = zoom_config; - omap_board_config_size = ARRAY_SIZE(zoom_config); - omap2_init_common_hw(h8mbx00u0mer0em_sdrc_params, - h8mbx00u0mer0em_sdrc_params); - omap_init_irq(); - omap_gpio_init(); -} - -#ifdef CONFIG_OMAP_MUX -static struct omap_board_mux board_mux[] __initdata = { - /* WLAN IRQ - GPIO 162 */ - OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), - /* WLAN POWER ENABLE - GPIO 101 */ - OMAP3_MUX(CAM_D2, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), - /* WLAN SDIO: MMC3 CMD */ - OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE3 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 CLK */ - OMAP3_MUX(ETK_CLK, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - /* WLAN SDIO: MMC3 DAT[0-3] */ - OMAP3_MUX(ETK_D3, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D4, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D5, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - OMAP3_MUX(ETK_D6, OMAP_MUX_MODE2 | OMAP_PIN_INPUT_PULLUP), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; -#else -#define board_mux NULL -#endif - -static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { - .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, - .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, - .phy_reset = true, - .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = 64, - .reset_gpio_port[2] = -EINVAL, -}; - -static void __init omap_zoom_init(void) -{ - omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - zoom_peripherals_init(); - board_nand_init(zoom_nand_partitions, - ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS); - zoom_debugboard_init(); - - omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); - usb_ehci_init(&ehci_pdata); -} - -MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") - .boot_params = 0x80000100, - .map_io = omap3_map_io, - .reserve = omap_reserve, - .init_irq = omap_zoom_init_irq, - .init_machine = omap_zoom_init, - .timer = &omap_timer, -MACHINE_END -- cgit v1.2.3 From 281f9be7e03054cc0b5d587249bdbc0156b47a9c Mon Sep 17 00:00:00 2001 From: Felipe Balbi Date: Mon, 8 Nov 2010 06:56:15 +0000 Subject: arm: omap: zoom: substitute gpio number with symbolic name It's easier to understand what that number means and also avoids problems if we ever have to change it. Signed-off-by: Felipe Balbi Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/board-zoom.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c index f10766ba7b5e..3da69e4102a4 100644 --- a/arch/arm/mach-omap2/board-zoom.c +++ b/arch/arm/mach-omap2/board-zoom.c @@ -31,6 +31,8 @@ #include "sdram-micron-mt46h32m32lf-6.h" #include "sdram-hynix-h8mbx00u0mer-0em.h" +#define ZOOM3_EHCI_RESET_GPIO 64 + static void __init omap_zoom_init_irq(void) { if (machine_is_omap_zoom2()) @@ -112,7 +114,7 @@ static const struct ehci_hcd_omap_platform_data ehci_pdata __initconst = { .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, .phy_reset = true, .reset_gpio_port[0] = -EINVAL, - .reset_gpio_port[1] = 64, + .reset_gpio_port[1] = ZOOM3_EHCI_RESET_GPIO, .reset_gpio_port[2] = -EINVAL, }; @@ -122,7 +124,7 @@ static void __init omap_zoom_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); } else if (machine_is_omap_zoom3()) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); - omap_mux_init_gpio(64, OMAP_PIN_OUTPUT); + omap_mux_init_gpio(ZOOM3_EHCI_RESET_GPIO, OMAP_PIN_OUTPUT); usb_ehci_init(&ehci_pdata); } -- cgit v1.2.3 From 2004290f55f03c52e22044a5843928cf0f6cc56a Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Thu, 30 Sep 2010 02:40:12 +0530 Subject: OMAP2xxx: hwmod: add I2C hwmods for OMAP2420, 2430 Add hwmod structures for I2C controllers on OMAP2420/2430. NOTE: I2C module on OMAP2420 has 16bit registers and causes imprecise aborts if 32bits are read/written to it. Use the HWMOD_16BIT_REG flag to notify the hmwod framework of this hard requirement so that __raw_writew/readw is used to read /write the mdoule registers. Signed-off-by: Paul Walmsley Signed-off-by: Rajendra Nayak Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/cm-regbits-24xx.h | 4 + arch/arm/mach-omap2/omap_hwmod_2420_data.c | 145 ++++++++++++++++++++++++++- arch/arm/mach-omap2/omap_hwmod_2430_data.c | 155 ++++++++++++++++++++++++++++- 3 files changed, 299 insertions(+), 5 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index da51cc3ed7eb..9a106c04c4a0 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -126,8 +126,12 @@ #define OMAP24XX_ST_HDQ_MASK (1 << 23) #define OMAP2420_ST_I2C2_SHIFT 20 #define OMAP2420_ST_I2C2_MASK (1 << 20) +#define OMAP2430_ST_I2CHS1_SHIFT 19 +#define OMAP2430_ST_I2CHS1_MASK (1 << 19) #define OMAP2420_ST_I2C1_SHIFT 19 #define OMAP2420_ST_I2C1_MASK (1 << 19) +#define OMAP2430_ST_I2CHS2_SHIFT 20 +#define OMAP2430_ST_I2CHS2_MASK (1 << 20) #define OMAP24XX_ST_MCBSP2_SHIFT 16 #define OMAP24XX_ST_MCBSP2_MASK (1 << 16) #define OMAP24XX_ST_MCBSP1_SHIFT 15 diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c index adf6e3632a2b..a1a3dd6303b4 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c @@ -16,11 +16,13 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" -#include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" +#include "prm-regbits-24xx.h" /* * OMAP2420 hardware module integration data @@ -77,6 +79,8 @@ static struct omap_hwmod omap2420_l4_wkup_hwmod; static struct omap_hwmod omap2420_uart1_hwmod; static struct omap_hwmod omap2420_uart2_hwmod; static struct omap_hwmod omap2420_uart3_hwmod; +static struct omap_hwmod omap2420_i2c1_hwmod; +static struct omap_hwmod omap2420_i2c2_hwmod; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { @@ -139,6 +143,45 @@ static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2420_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { + .master = &omap2420_l4_core_hwmod, + .slave = &omap2420_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2420_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap2420_l4_core_slaves[] = { &omap2420_l3_main__l4_core, @@ -150,6 +193,8 @@ static struct omap_hwmod_ocp_if *omap2420_l4_core_masters[] = { &omap2_l4_core__uart1, &omap2_l4_core__uart2, &omap2_l4_core__uart3, + &omap2420_l4_core__i2c1, + &omap2420_l4_core__i2c2 }; /* L4 CORE */ @@ -418,6 +463,100 @@ static struct omap_hwmod omap2420_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = SYSC_HAS_SOFTRESET, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr; + +/* I2C1 */ + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = { + &omap2420_l4_core__i2c1, +}; + +static struct omap_hwmod omap2420_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, + }, + }, + .slaves = omap2420_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_16BIT_REG, +}; + +/* I2C2 */ + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = { + &omap2420_l4_core__i2c2, +}; + +static struct omap_hwmod omap2420_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2420_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, + }, + }, + .slaves = omap2420_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2420_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420), + .flags = HWMOD_16BIT_REG, +}; + static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_l3_main_hwmod, &omap2420_l4_core_hwmod, @@ -428,6 +567,8 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = { &omap2420_uart1_hwmod, &omap2420_uart2_hwmod, &omap2420_uart3_hwmod, + &omap2420_i2c1_hwmod, + &omap2420_i2c2_hwmod, NULL, }; @@ -435,5 +576,3 @@ int __init omap2420_hwmod_init(void) { return omap_hwmod_init(omap2420_hwmods); } - - diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c index 12d939e456cf..7cf0d3ab2a4a 100644 --- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include "omap_hwmod_common_data.h" @@ -77,6 +79,47 @@ static struct omap_hwmod omap2430_l4_wkup_hwmod; static struct omap_hwmod omap2430_uart1_hwmod; static struct omap_hwmod omap2430_uart2_hwmod; static struct omap_hwmod omap2430_uart3_hwmod; +static struct omap_hwmod omap2430_i2c1_hwmod; +static struct omap_hwmod omap2430_i2c2_hwmod; + +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap2430_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { + .master = &omap2430_l4_core_hwmod, + .slave = &omap2430_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap2430_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; /* L4_CORE -> L4_WKUP interface */ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = { @@ -418,6 +461,114 @@ static struct omap_hwmod omap2430_uart3_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +static struct omap_i2c_dev_attr i2c_dev_attr; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = { + &omap2430_l4_core__i2c1, +}; + +static struct omap_hwmod omap2430_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2chs1_fck", + .prcm = { + .omap2 = { + /* + * NOTE: The CM_FCLKEN* and CM_ICLKEN* for + * I2CHS IP's do not follow the usual pattern. + * prcm_reg_id alone cannot be used to program + * the iclk and fclk. Needs to be handled using + * additonal flags when clk handling is moved + * to hwmod framework. + */ + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, + }, + }, + .slaves = omap2430_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = { + &omap2430_l4_core__i2c2, +}; + +static struct omap_hwmod omap2430_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2chs2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP2430_EN_I2CHS2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, + }, + }, + .slaves = omap2430_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap2430_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430), +}; + static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_l3_main_hwmod, &omap2430_l4_core_hwmod, @@ -428,6 +579,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = { &omap2430_uart1_hwmod, &omap2430_uart2_hwmod, &omap2430_uart3_hwmod, + &omap2430_i2c1_hwmod, + &omap2430_i2c2_hwmod, NULL, }; @@ -435,5 +588,3 @@ int __init omap2430_hwmod_init(void) { return omap_hwmod_init(omap2430_hwmods); } - - -- cgit v1.2.3 From 4fe20e97c8b1082d16b38e9f4c53feeed143ab98 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Tue, 21 Sep 2010 19:37:13 +0530 Subject: OMAP3: hwmod: add I2C hwmods for OMAP3430 Add hwmod structures for I2C controllers on OMAP3430. This patch was developed in collaboration with Paul Walmsley . OMAP3 fixes for correct IDLEST bit monitoring from G, Manjunath Kondaiah Signed-off-by: Rajendra Nayak Signed-off-by: Paul Walmsley Cc: G, Manjunath Kondaiah Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 233 +++++++++++++++++++++++++++++ arch/arm/mach-omap2/prm-regbits-34xx.h | 3 + arch/arm/plat-omap/include/plat/i2c.h | 13 ++ arch/arm/plat-omap/include/plat/l4_3xxx.h | 24 +++ 4 files changed, 273 insertions(+) create mode 100644 arch/arm/plat-omap/include/plat/l4_3xxx.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c index cb97ecf0a3f6..a8bed843079c 100644 --- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c @@ -18,6 +18,9 @@ #include #include #include +#include +#include +#include #include "omap_hwmod_common_data.h" @@ -39,6 +42,9 @@ static struct omap_hwmod omap3xxx_l3_main_hwmod; static struct omap_hwmod omap3xxx_l4_core_hwmod; static struct omap_hwmod omap3xxx_l4_per_hwmod; static struct omap_hwmod omap3xxx_wd_timer2_hwmod; +static struct omap_hwmod omap3xxx_i2c1_hwmod; +static struct omap_hwmod omap3xxx_i2c2_hwmod; +static struct omap_hwmod omap3xxx_i2c3_hwmod; /* L3 -> L4_CORE interface */ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = { @@ -169,6 +175,84 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* I2C IP block address space length (in bytes) */ +#define OMAP2_I2C_AS_LEN 128 + +/* L4 CORE -> I2C1 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c1_hwmod, + .clk = "i2c1_ick", + .addr = omap3xxx_i2c1_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C2 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c2_hwmod, + .clk = "i2c2_ick", + .addr = omap3xxx_i2c2_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* L4 CORE -> I2C3 interface */ +static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1, + .flags = ADDR_TYPE_RT, + }, +}; + +static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = { + .master = &omap3xxx_l4_core_hwmod, + .slave = &omap3xxx_i2c3_hwmod, + .clk = "i2c3_ick", + .addr = omap3xxx_i2c3_addr_space, + .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space), + .fw = { + .omap2 = { + .l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION, + .l4_prot_group = 7, + .flags = OMAP_FIREWALL_L4, + } + }, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* Slave interfaces on the L4_CORE interconnect */ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = { &omap3xxx_l3_main__l4_core, @@ -179,6 +263,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = { &omap3xxx_l4_core__l4_wkup, &omap3_l4_core__uart1, &omap3_l4_core__uart2, + &omap3_l4_core__i2c1, + &omap3_l4_core__i2c2, + &omap3_l4_core__i2c3, }; /* L4 CORE */ @@ -315,6 +402,18 @@ static struct omap_hwmod_class_sysconfig omap3xxx_wd_timer_sysc = { .sysc_fields = &omap_hwmod_sysc_type1, }; +/* I2C common */ +static struct omap_hwmod_class_sysconfig i2c_sysc = { + .rev_offs = 0x00, + .sysc_offs = 0x20, + .syss_offs = 0x10, + .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + static struct omap_hwmod_class omap3xxx_wd_timer_hwmod_class = { .name = "wd_timer", .sysc = &omap3xxx_wd_timer_sysc, @@ -509,6 +608,137 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1), }; +static struct omap_hwmod_class i2c_class = { + .name = "i2c", + .sysc = &i2c_sysc, +}; + +/* I2C1 */ + +static struct omap_i2c_dev_attr i2c1_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = { + { .irq = INT_24XX_I2C1_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = { + &omap3_l4_core__i2c1, +}; + +static struct omap_hwmod omap3xxx_i2c1_hwmod = { + .name = "i2c1", + .mpu_irqs = i2c1_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs), + .sdma_reqs = i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C1_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT, + }, + }, + .slaves = omap3xxx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c1_slaves), + .class = &i2c_class, + .dev_attr = &i2c1_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C2 */ + +static struct omap_i2c_dev_attr i2c2_dev_attr = { + .fifo_depth = 8, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = { + { .irq = INT_24XX_I2C2_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX }, + { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = { + &omap3_l4_core__i2c2, +}; + +static struct omap_hwmod omap3xxx_i2c2_hwmod = { + .name = "i2c2", + .mpu_irqs = i2c2_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs), + .sdma_reqs = i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C2_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT, + }, + }, + .slaves = omap3xxx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c2_slaves), + .class = &i2c_class, + .dev_attr = &i2c2_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + +/* I2C3 */ + +static struct omap_i2c_dev_attr i2c3_dev_attr = { + .fifo_depth = 64, /* bytes */ +}; + +static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = { + { .irq = INT_34XX_I2C3_IRQ, }, +}; + +static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX }, + { .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX }, +}; + +static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = { + &omap3_l4_core__i2c3, +}; + +static struct omap_hwmod omap3xxx_i2c3_hwmod = { + .name = "i2c3", + .mpu_irqs = i2c3_mpu_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs), + .sdma_reqs = i2c3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs), + .main_clk = "i2c3_fck", + .prcm = { + .omap2 = { + .module_offs = CORE_MOD, + .prcm_reg_id = 1, + .module_bit = OMAP3430_EN_I2C3_SHIFT, + .idlest_reg_id = 1, + .idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT, + }, + }, + .slaves = omap3xxx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap3xxx_i2c3_slaves), + .class = &i2c_class, + .dev_attr = &i2c3_dev_attr, + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), +}; + static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_l3_main_hwmod, &omap3xxx_l4_core_hwmod, @@ -521,6 +751,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = { &omap3xxx_uart2_hwmod, &omap3xxx_uart3_hwmod, &omap3xxx_uart4_hwmod, + &omap3xxx_i2c1_hwmod, + &omap3xxx_i2c2_hwmod, + &omap3xxx_i2c3_hwmod, NULL, }; diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 9e63cb743a97..ec1a710db9ce 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -101,8 +101,11 @@ #define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) #define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) #define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) +#define OMAP3430_GRPSEL_I2C3_SHIFT 17 #define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) +#define OMAP3430_GRPSEL_I2C2_SHIFT 16 #define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) +#define OMAP3430_GRPSEL_I2C1_SHIFT 15 #define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) #define OMAP3430_GRPSEL_UART2_MASK (1 << 14) #define OMAP3430_GRPSEL_UART1_MASK (1 << 13) diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h index 36a0befd6168..878d632c4092 100644 --- a/arch/arm/plat-omap/include/plat/i2c.h +++ b/arch/arm/plat-omap/include/plat/i2c.h @@ -36,6 +36,19 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate, } #endif +/** + * i2c_dev_attr - OMAP I2C controller device attributes for omap_hwmod + * @fifo_depth: total controller FIFO size (in bytes) + * @flags: differences in hardware support capability + * + * @fifo_depth represents what exists on the hardware, not what is + * actually configured at runtime by the device driver. + */ +struct omap_i2c_dev_attr { + u8 fifo_depth; + u8 flags; +}; + void __init omap1_i2c_mux_pins(int bus_id); void __init omap2_i2c_mux_pins(int bus_id); diff --git a/arch/arm/plat-omap/include/plat/l4_3xxx.h b/arch/arm/plat-omap/include/plat/l4_3xxx.h new file mode 100644 index 000000000000..5e1949375422 --- /dev/null +++ b/arch/arm/plat-omap/include/plat/l4_3xxx.h @@ -0,0 +1,24 @@ +/* + * arch/arm/plat-omap/include/mach/l4_3xxx.h - L4 firewall definitions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ +#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H +#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_L4_3XXX_H + +/* L4 CORE */ +#define OMAP3_L4_CORE_FW_I2C1_REGION 21 +#define OMAP3_L4_CORE_FW_I2C1_TA_REGION 22 +#define OMAP3_L4_CORE_FW_I2C2_REGION 23 +#define OMAP3_L4_CORE_FW_I2C2_TA_REGION 24 +#define OMAP3_L4_CORE_FW_I2C3_REGION 73 +#define OMAP3_L4_CORE_FW_I2C3_TA_REGION 74 + +#endif -- cgit v1.2.3 From f776471f620a07be234f40288a1fd9932d039e26 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 21 Sep 2010 19:37:14 +0530 Subject: OMAP4: hwmod: add I2C hwmods for OMAP4430 Add hwmod structures for I2C controllers on OMAP4430. Signed-off-by: Benoit Cousson Signed-off-by: Rajendra Nayak Signed-off-by: Kevin Hilman --- arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 237 +++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c index 7274db4de487..0d5c6eb7e4c1 100644 --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c @@ -382,6 +382,238 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = { .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), }; +/* + * 'i2c' class + * multimaster high-speed i2c controller + */ + +static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SOFTRESET | + SYSC_HAS_AUTOIDLE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { + .name = "i2c", + .sysc = &omap44xx_i2c_sysc, +}; + +/* i2c1 */ +static struct omap_hwmod omap44xx_i2c1_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { + { .irq = 56 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { + { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { + { + .pa_start = 0x48070000, + .pa_end = 0x480700ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c1 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c1_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c1_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c1 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = { + &omap44xx_l4_per__i2c1, +}; + +static struct omap_hwmod omap44xx_i2c1_hwmod = { + .name = "i2c1", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c1_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs), + .sdma_reqs = omap44xx_i2c1_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs), + .main_clk = "i2c1_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c1_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c2 */ +static struct omap_hwmod omap44xx_i2c2_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { + { .irq = 57 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { + { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { + { + .pa_start = 0x48072000, + .pa_end = 0x480720ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c2 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c2_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c2_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c2 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = { + &omap44xx_l4_per__i2c2, +}; + +static struct omap_hwmod omap44xx_i2c2_hwmod = { + .name = "i2c2", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c2_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs), + .sdma_reqs = omap44xx_i2c2_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs), + .main_clk = "i2c2_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c2_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c3 */ +static struct omap_hwmod omap44xx_i2c3_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { + { .irq = 61 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { + { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { + { + .pa_start = 0x48060000, + .pa_end = 0x480600ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c3 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c3_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c3_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c3 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = { + &omap44xx_l4_per__i2c3, +}; + +static struct omap_hwmod omap44xx_i2c3_hwmod = { + .name = "i2c3", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c3_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs), + .sdma_reqs = omap44xx_i2c3_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs), + .main_clk = "i2c3_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c3_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + +/* i2c4 */ +static struct omap_hwmod omap44xx_i2c4_hwmod; +static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { + { .irq = 62 + OMAP44XX_IRQ_GIC_START }, +}; + +static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { + { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, + { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, +}; + +static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { + { + .pa_start = 0x48350000, + .pa_end = 0x483500ff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l4_per -> i2c4 */ +static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { + .master = &omap44xx_l4_per_hwmod, + .slave = &omap44xx_i2c4_hwmod, + .clk = "l4_div_ck", + .addr = omap44xx_i2c4_addrs, + .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs), + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* i2c4 slave ports */ +static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = { + &omap44xx_l4_per__i2c4, +}; + +static struct omap_hwmod omap44xx_i2c4_hwmod = { + .name = "i2c4", + .class = &omap44xx_i2c_hwmod_class, + .flags = HWMOD_INIT_NO_RESET, + .mpu_irqs = omap44xx_i2c4_irqs, + .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs), + .sdma_reqs = omap44xx_i2c4_sdma_reqs, + .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs), + .main_clk = "i2c4_fck", + .prcm = { + .omap4 = { + .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL, + }, + }, + .slaves = omap44xx_i2c4_slaves, + .slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430), +}; + /* * 'mpu_bus' class * instance(s): mpu_private @@ -826,6 +1058,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = { &omap44xx_l4_cfg_hwmod, &omap44xx_l4_per_hwmod, &omap44xx_l4_wkup_hwmod, + /* i2c class */ + &omap44xx_i2c1_hwmod, + &omap44xx_i2c2_hwmod, + &omap44xx_i2c3_hwmod, + &omap44xx_i2c4_hwmod, /* mpu_bus class */ &omap44xx_mpu_private_hwmod, -- cgit v1.2.3 From 4d17aeb1c5b2375769446d13012a98e6d265ec13 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Sep 2010 19:37:15 +0530 Subject: OMAP: I2C: split device registration and convert OMAP2+ to omap_device Split the OMAP1 and OMAP2+ platform_device build and register code. Convert the OMAP2+ variant to use omap_device. This patch was developed in collaboration with Rajendra Nayak . Signed-off-by: Paul Walmsley Signed-off-by: Rajendra Nayak Cc: Kevin Hilman Signed-off-by: Kevin Hilman --- arch/arm/plat-omap/i2c.c | 124 +++++++++++++++++++---------------------------- include/linux/i2c-omap.h | 5 ++ 2 files changed, 54 insertions(+), 75 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/i2c.c b/arch/arm/plat-omap/i2c.c index a5ce4f0aad35..a5bff9ce7cbe 100644 --- a/arch/arm/plat-omap/i2c.c +++ b/arch/arm/plat-omap/i2c.c @@ -27,18 +27,18 @@ #include #include #include +#include +#include +#include #include #include #include #include +#include #define OMAP_I2C_SIZE 0x3f #define OMAP1_I2C_BASE 0xfffb3800 -#define OMAP2_I2C_BASE1 0x48070000 -#define OMAP2_I2C_BASE2 0x48072000 -#define OMAP2_I2C_BASE3 0x48060000 -#define OMAP4_I2C_BASE4 0x48350000 static const char name[] = "i2c_omap"; @@ -55,15 +55,6 @@ static const char name[] = "i2c_omap"; static struct resource i2c_resources[][2] = { { I2C_RESOURCE_BUILDER(0, 0) }, -#if defined(CONFIG_ARCH_OMAP2PLUS) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE2, 0) }, -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - { I2C_RESOURCE_BUILDER(OMAP2_I2C_BASE3, 0) }, -#endif -#if defined(CONFIG_ARCH_OMAP4) - { I2C_RESOURCE_BUILDER(OMAP4_I2C_BASE4, 0) }, -#endif }; #define I2C_DEV_BUILDER(bus_id, res, data) \ @@ -77,18 +68,11 @@ static struct resource i2c_resources[][2] = { }, \ } -static struct omap_i2c_bus_platform_data i2c_pdata[ARRAY_SIZE(i2c_resources)]; +#define MAX_OMAP_I2C_HWMOD_NAME_LEN 16 +#define OMAP_I2C_MAX_CONTROLLERS 4 +static struct omap_i2c_bus_platform_data i2c_pdata[OMAP_I2C_MAX_CONTROLLERS]; static struct platform_device omap_i2c_devices[] = { I2C_DEV_BUILDER(1, i2c_resources[0], &i2c_pdata[0]), -#if defined(CONFIG_ARCH_OMAP2PLUS) - I2C_DEV_BUILDER(2, i2c_resources[1], &i2c_pdata[1]), -#endif -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4) - I2C_DEV_BUILDER(3, i2c_resources[2], &i2c_pdata[2]), -#endif -#if defined(CONFIG_ARCH_OMAP4) - I2C_DEV_BUILDER(4, i2c_resources[3], &i2c_pdata[3]), -#endif }; #define OMAP_I2C_CMDLINE_SETUP (BIT(31)) @@ -109,35 +93,20 @@ static int __init omap_i2c_nr_ports(void) return ports; } -/* Shared between omap2 and 3 */ -static resource_size_t omap2_i2c_irq[3] __initdata = { - INT_24XX_I2C1_IRQ, - INT_24XX_I2C2_IRQ, - INT_34XX_I2C3_IRQ, -}; - -static resource_size_t omap4_i2c_irq[4] __initdata = { - OMAP44XX_IRQ_I2C1, - OMAP44XX_IRQ_I2C2, - OMAP44XX_IRQ_I2C3, - OMAP44XX_IRQ_I2C4, -}; - -static inline int omap1_i2c_add_bus(struct platform_device *pdev, int bus_id) +static inline int omap1_i2c_add_bus(int bus_id) { - struct omap_i2c_bus_platform_data *pd; - struct resource *res; - - pd = pdev->dev.platform_data; - res = pdev->resource; - res[0].start = OMAP1_I2C_BASE; - res[0].end = res[0].start + OMAP_I2C_SIZE; - res[1].start = INT_I2C; + struct platform_device *pdev; + struct omap_i2c_bus_platform_data *pdata; + omap1_i2c_mux_pins(bus_id); + pdev = &omap_i2c_devices[bus_id - 1]; + pdata = &i2c_pdata[bus_id - 1]; + return platform_device_register(pdev); } + /* * XXX This function is a temporary compatibility wrapper - only * needed until the I2C driver can be converted to call @@ -148,52 +117,57 @@ static void omap_pm_set_max_mpu_wakeup_lat_compat(struct device *dev, long t) omap_pm_set_max_mpu_wakeup_lat(dev, t); } -static inline int omap2_i2c_add_bus(struct platform_device *pdev, int bus_id) -{ - struct resource *res; - resource_size_t *irq; +static struct omap_device_pm_latency omap_i2c_latency[] = { + [0] = { + .deactivate_func = omap_device_idle_hwmods, + .activate_func = omap_device_enable_hwmods, + .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST, + }, +}; - res = pdev->resource; +static inline int omap2_i2c_add_bus(int bus_id) +{ + int l; + struct omap_hwmod *oh; + struct omap_device *od; + char oh_name[MAX_OMAP_I2C_HWMOD_NAME_LEN]; + struct omap_i2c_bus_platform_data *pdata; - if (!cpu_is_omap44xx()) - irq = omap2_i2c_irq; - else - irq = omap4_i2c_irq; + omap2_i2c_mux_pins(bus_id); - if (bus_id == 1) { - res[0].start = OMAP2_I2C_BASE1; - res[0].end = res[0].start + OMAP_I2C_SIZE; + l = snprintf(oh_name, MAX_OMAP_I2C_HWMOD_NAME_LEN, "i2c%d", bus_id); + WARN(l >= MAX_OMAP_I2C_HWMOD_NAME_LEN, + "String buffer overflow in I2C%d device setup\n", bus_id); + oh = omap_hwmod_lookup(oh_name); + if (!oh) { + pr_err("Could not look up %s\n", oh_name); + return -EEXIST; } - res[1].start = irq[bus_id - 1]; - omap2_i2c_mux_pins(bus_id); - + pdata = &i2c_pdata[bus_id - 1]; /* * When waiting for completion of a i2c transfer, we need to * set a wake up latency constraint for the MPU. This is to * ensure quick enough wakeup from idle, when transfer * completes. + * Only omap3 has support for constraints */ - if (cpu_is_omap34xx()) { - struct omap_i2c_bus_platform_data *pd; - - pd = pdev->dev.platform_data; - pd->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; - } - - return platform_device_register(pdev); + if (cpu_is_omap34xx()) + pdata->set_mpu_wkup_lat = omap_pm_set_max_mpu_wakeup_lat_compat; + od = omap_device_build(name, bus_id, oh, pdata, + sizeof(struct omap_i2c_bus_platform_data), + omap_i2c_latency, ARRAY_SIZE(omap_i2c_latency), 0); + WARN(IS_ERR(od), "Could not build omap_device for %s\n", name); + + return PTR_ERR(od); } static int __init omap_i2c_add_bus(int bus_id) { - struct platform_device *pdev; - - pdev = &omap_i2c_devices[bus_id - 1]; - if (cpu_class_is_omap1()) - return omap1_i2c_add_bus(pdev, bus_id); + return omap1_i2c_add_bus(bus_id); else - return omap2_i2c_add_bus(pdev, bus_id); + return omap2_i2c_add_bus(bus_id); } /** diff --git a/include/linux/i2c-omap.h b/include/linux/i2c-omap.h index 78ebf507ce56..7472449cbb74 100644 --- a/include/linux/i2c-omap.h +++ b/include/linux/i2c-omap.h @@ -1,9 +1,14 @@ #ifndef __I2C_OMAP_H__ #define __I2C_OMAP_H__ +#include + struct omap_i2c_bus_platform_data { u32 clkrate; void (*set_mpu_wkup_lat)(struct device *dev, long set); + int (*device_enable) (struct platform_device *pdev); + int (*device_shutdown) (struct platform_device *pdev); + int (*device_idle) (struct platform_device *pdev); }; #endif -- cgit v1.2.3 From 92964e03f68a85a675343c65d5d3e5a998f8a83b Mon Sep 17 00:00:00 2001 From: Evgeny Kuznetsov Date: Mon, 8 Nov 2010 08:38:36 +0000 Subject: omap: Ptr "isr_reg" tracked as NULL was dereferenced Value of "isr_reg" pointer is depend on configuration and GPIO method. Potentially it may have NULL value and it is dereferenced later in code. Warning and exit from function are added in this case. Signed-off-by: Evgeny Kuznetsov Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/gpio.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index c05c653d1674..e0e2fa725269 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -1318,6 +1318,10 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) if (bank->method == METHOD_GPIO_44XX) isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0; #endif + + if (WARN_ON(!isr_reg)) + goto exit; + while(1) { u32 isr_saved, level_mask = 0; u32 enabled; @@ -1377,6 +1381,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) configured, we must unmask the bank interrupt only after handler(s) are executed in order to avoid spurious bank interrupt */ +exit: if (!unmasked) desc->chip->unmask(irq); -- cgit v1.2.3 From 2095e9b966d4e86081b76119afc5bceef0060256 Mon Sep 17 00:00:00 2001 From: Jarkko Nikula Date: Wed, 3 Nov 2010 09:24:23 +0000 Subject: omap: McBSP: Fix potential memory leak in omap_mcbsp_remove Function omap_mcbsp_probe allocates struct omap_mcbsp *mcbsp but it is not freed in omap_mcbsp_remove. Fix this, remove unneeded structure cleanups and clk_disable calls since they are not needed here. This is not problem currently but becomes if the mcbsp driver is ever modularized. Signed-off-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/mcbsp.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index eac4b978e9fd..f79090cb823b 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -1836,17 +1836,11 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev) omap34xx_device_exit(mcbsp); - clk_disable(mcbsp->fclk); - clk_disable(mcbsp->iclk); clk_put(mcbsp->fclk); clk_put(mcbsp->iclk); iounmap(mcbsp->io_base); - - mcbsp->fclk = NULL; - mcbsp->iclk = NULL; - mcbsp->free = 0; - mcbsp->dev = NULL; + kfree(mcbsp); } return 0; -- cgit v1.2.3 From 8b4ccf0f8aaf3344b361de8c0bae97985335a13a Mon Sep 17 00:00:00 2001 From: Shubhrajyoti D Date: Wed, 3 Nov 2010 09:58:57 +0000 Subject: McBSP:Make the free variable update more readable Using true/false instead of 1/0 to update the free variable. Signed-off-by: Shubhrajyoti D Acked-by: Jarkko Nikula Signed-off-by: Tony Lindgren --- arch/arm/plat-omap/mcbsp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index f79090cb823b..fdecd339d4f8 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -755,7 +755,7 @@ int omap_mcbsp_request(unsigned int id) goto err_kfree; } - mcbsp->free = 0; + mcbsp->free = false; mcbsp->reg_cache = reg_cache; spin_unlock(&mcbsp->lock); @@ -815,7 +815,7 @@ err_clk_disable: clk_disable(mcbsp->iclk); spin_lock(&mcbsp->lock); - mcbsp->free = 1; + mcbsp->free = true; mcbsp->reg_cache = NULL; err_kfree: spin_unlock(&mcbsp->lock); @@ -858,7 +858,7 @@ void omap_mcbsp_free(unsigned int id) if (mcbsp->free) dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id); else - mcbsp->free = 1; + mcbsp->free = true; mcbsp->reg_cache = NULL; spin_unlock(&mcbsp->lock); @@ -1771,7 +1771,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev) spin_lock_init(&mcbsp->lock); mcbsp->id = id + 1; - mcbsp->free = 1; + mcbsp->free = true; mcbsp->dma_tx_lch = -1; mcbsp->dma_rx_lch = -1; -- cgit v1.2.3 From e245dc6dd5101de63ebce6929b477c4ee45db171 Mon Sep 17 00:00:00 2001 From: Janusz Krzysztofik Date: Tue, 16 Nov 2010 14:26:57 -0800 Subject: OMAP1: drop AMS_DELTA_FIQ config option This patches removes a config option that was used to select a FIQ handler to be build for Amstrad Delta, as required by the on-board serio interface driver. Not having any problem reports received since it was introduced in 2.6.35, the FIQ handler can now be built and initialized by default, thus reqiring no extra config option. Signed-off-by: Janusz Krzysztofik Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/Kconfig | 11 +---------- arch/arm/mach-omap1/Makefile | 4 ++-- arch/arm/mach-omap1/board-ams-delta.c | 2 -- drivers/input/serio/Kconfig | 1 - 4 files changed, 3 insertions(+), 15 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig index 5f6496375404..8d2f2daba0c0 100644 --- a/arch/arm/mach-omap1/Kconfig +++ b/arch/arm/mach-omap1/Kconfig @@ -152,20 +152,11 @@ config MACH_NOKIA770 config MACH_AMS_DELTA bool "Amstrad E3 (Delta)" depends on ARCH_OMAP1 && ARCH_OMAP15XX + select FIQ help Support for the Amstrad E3 (codename Delta) videophone. Say Y here if you have such a device. -config AMS_DELTA_FIQ - bool "Fast Interrupt Request (FIQ) support for the E3" - depends on MACH_AMS_DELTA - select FIQ - help - Provide a FIQ handler for the E3. - This allows for fast handling of interrupts generated - by the clock line of the E3 mailboard (or a PS/2 keyboard) - connected to the GPIO based external keyboard port. - config MACH_OMAP_GENERIC bool "Generic OMAP board" depends on ARCH_OMAP1 && (ARCH_OMAP15XX || ARCH_OMAP16XX) diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile index 9a304d854e33..de3cc130ab8e 100644 --- a/arch/arm/mach-omap1/Makefile +++ b/arch/arm/mach-omap1/Makefile @@ -39,8 +39,8 @@ obj-$(CONFIG_MACH_OMAP_PALMTE) += board-palmte.o obj-$(CONFIG_MACH_OMAP_PALMZ71) += board-palmz71.o obj-$(CONFIG_MACH_OMAP_PALMTT) += board-palmtt.o obj-$(CONFIG_MACH_NOKIA770) += board-nokia770.o -obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o -obj-$(CONFIG_AMS_DELTA_FIQ) += ams-delta-fiq.o ams-delta-fiq-handler.o +obj-$(CONFIG_MACH_AMS_DELTA) += board-ams-delta.o ams-delta-fiq.o \ + ams-delta-fiq-handler.o obj-$(CONFIG_MACH_SX1) += board-sx1.o board-sx1-mmc.o obj-$(CONFIG_MACH_HERALD) += board-htcherald.o diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 1d4163b9f0b7..eaa7081fef8f 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -307,9 +307,7 @@ static void __init ams_delta_init(void) #endif platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices)); -#ifdef CONFIG_AMS_DELTA_FIQ ams_delta_init_fiq(); -#endif omap_writew(omap_readw(ARM_RSTCT1) | 0x0004, ARM_RSTCT1); } diff --git a/drivers/input/serio/Kconfig b/drivers/input/serio/Kconfig index 6256233d2bfb..bcb1fdedb595 100644 --- a/drivers/input/serio/Kconfig +++ b/drivers/input/serio/Kconfig @@ -214,7 +214,6 @@ config SERIO_AMS_DELTA tristate "Amstrad Delta (E3) mailboard support" depends on MACH_AMS_DELTA default y - select AMS_DELTA_FIQ ---help--- Say Y here if you have an E3 and want to use its mailboard, or any standard AT keyboard connected to the mailboard port. -- cgit v1.2.3 From 31fbf81e34b9a2ecb02289997d2f0f6030fb7a0a Mon Sep 17 00:00:00 2001 From: Srinath Date: Tue, 16 Nov 2010 14:26:58 -0800 Subject: omap: AM3517/05: Add craneboard support Craneboard is a hardware development platform based on the Sitara AM3517 ARM Cortex - A8 microprocessor device. This is a low cost reference design. This patch adds basic board file. Detailed support will follow in subsequent patches. [1] http://www.ti.com/arm [2] http://www.mistralsolutions.com/products/craneboard.php Signed-off-by: Srinath Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/Kconfig | 5 ++ arch/arm/mach-omap2/Makefile | 2 + arch/arm/mach-omap2/board-am3517crane.c | 69 ++++++++++++++++++++++++++++ arch/arm/plat-omap/include/plat/uncompress.h | 1 + 4 files changed, 77 insertions(+) create mode 100644 arch/arm/mach-omap2/board-am3517crane.c (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ab784bfde908..368851522629 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -174,6 +174,11 @@ config MACH_OMAP3517EVM default y select OMAP_PACKAGE_CBB +config MACH_CRANEBOARD + bool "AM3517/05 CRANE board" + depends on ARCH_OMAP3 + select OMAP_PACKAGE_CBB + config MACH_OMAP3_PANDORA bool "OMAP3 Pandora" depends on ARCH_OMAP3 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index b0810b9abbba..d43bd33a19be 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -174,6 +174,8 @@ obj-$(CONFIG_MACH_OMAP4_PANDA) += board-omap4panda.o \ obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o +obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o + obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o \ hsmmc.o # Platform specific device init code diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c new file mode 100644 index 000000000000..13ead330e389 --- /dev/null +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -0,0 +1,69 @@ +/* + * Support for AM3517/05 Craneboard + * http://www.mistralsolutions.com/products/craneboard.php + * + * Copyright (C) 2010 Mistral Solutions Pvt Ltd. + * Author: R.Srinath + * + * Based on mach-omap2/board-am3517evm.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind, + * whether express or implied; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + */ + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include "mux.h" + +/* Board initialization */ +static struct omap_board_config_kernel am3517_crane_config[] __initdata = { +}; + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + +static void __init am3517_crane_init_irq(void) +{ + omap_board_config = am3517_crane_config; + omap_board_config_size = ARRAY_SIZE(am3517_crane_config); + + omap2_init_common_hw(NULL, NULL); + omap_init_irq(); + omap_gpio_init(); +} + +static void __init am3517_crane_init(void) +{ + omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); + omap_serial_init(); +} + +MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") + .boot_params = 0x80000100, + .map_io = omap3_map_io, + .reserve = omap_reserve, + .init_irq = am3517_crane_init_irq, + .init_machine = am3517_crane_init, + .timer = &omap_timer, +MACHINE_END diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h index 9036e374e0ac..229fbf2cbd26 100644 --- a/arch/arm/plat-omap/include/plat/uncompress.h +++ b/arch/arm/plat-omap/include/plat/uncompress.h @@ -145,6 +145,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id) /* omap3 based boards using UART3 */ DEBUG_LL_OMAP3(3, cm_t35); DEBUG_LL_OMAP3(3, cm_t3517); + DEBUG_LL_OMAP3(3, craneboard); DEBUG_LL_OMAP3(3, igep0020); DEBUG_LL_OMAP3(3, igep0030); DEBUG_LL_OMAP3(3, nokia_rx51); -- cgit v1.2.3 From 1cbb3a9a132969ed1ffeaecff2f910619d4470ae Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 10 Aug 2010 17:33:01 +0200 Subject: OMAP: mux: Replace printk with pr_xxx macros Replace all the printk(KERN_XXX... with pr_xxx macros. Signed-off-by: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/mux.c | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 074536ae401f..979e9d1c4659 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -102,13 +102,13 @@ int __init omap_mux_init_gpio(int gpio, int val) } if (found == 0) { - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + pr_err("mux: Could not set gpio%i\n", gpio); return -ENODEV; } if (found > 1) { - printk(KERN_INFO "mux: Multiple gpio paths (%d) for gpio%i\n", - found, gpio); + pr_info("mux: Multiple gpio paths (%d) for gpio%i\n", + found, gpio); return -EINVAL; } @@ -118,8 +118,8 @@ int __init omap_mux_init_gpio(int gpio, int val) mux_mode |= OMAP_MUX_MODE3; else mux_mode |= OMAP_MUX_MODE4; - printk(KERN_DEBUG "mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", - gpio_mux->muxnames[0], gpio, old_mode, mux_mode); + pr_debug("mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", + gpio_mux->muxnames[0], gpio, old_mode, mux_mode); omap_mux_write(mux_mode, gpio_mux->reg_offset); return 0; @@ -161,9 +161,9 @@ int __init omap_mux_init_signal(const char *muxname, int val) old_mode = omap_mux_read(m->reg_offset); mux_mode = val | i; - printk(KERN_DEBUG "mux: Setting signal " - "%s.%s 0x%04x -> 0x%04x\n", - m0_entry, muxname, old_mode, mux_mode); + pr_debug("mux: Setting signal " + "%s.%s 0x%04x -> 0x%04x\n", + m0_entry, muxname, old_mode, mux_mode); omap_mux_write(mux_mode, m->reg_offset); found++; } @@ -174,12 +174,12 @@ int __init omap_mux_init_signal(const char *muxname, int val) return 0; if (found > 1) { - printk(KERN_ERR "mux: Multiple signal paths (%i) for %s\n", - found, muxname); + pr_err("mux: Multiple signal paths (%i) for %s\n", + found, muxname); return -EINVAL; } - printk(KERN_ERR "mux: Could not set signal %s\n", muxname); + pr_err("mux: Could not set signal %s\n", muxname); return -ENODEV; } @@ -462,8 +462,8 @@ static void __init omap_mux_package_fixup(struct omap_mux *p, s++; } if (!found) - printk(KERN_ERR "mux: Unknown entry offset 0x%x\n", - p->reg_offset); + pr_err("mux: Unknown entry offset 0x%x\n", + p->reg_offset); p++; } } @@ -487,8 +487,8 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b, s++; } if (!found) - printk(KERN_ERR "mux: Unknown ball offset 0x%x\n", - b->reg_offset); + pr_err("mux: Unknown ball offset 0x%x\n", + b->reg_offset); b++; } } @@ -615,7 +615,7 @@ u16 omap_mux_get_gpio(int gpio) offset = omap_mux_get_by_gpio(gpio); if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not get gpio%i\n", gpio); + pr_err("mux: Could not get gpio%i\n", gpio); return offset; } @@ -629,7 +629,7 @@ void omap_mux_set_gpio(u16 val, int gpio) offset = omap_mux_get_by_gpio(gpio); if (offset == OMAP_MUX_TERMINATOR) { - printk(KERN_ERR "mux: Could not set gpio%i\n", gpio); + pr_err("mux: Could not set gpio%i\n", gpio); return; } @@ -687,7 +687,7 @@ static void __init omap_mux_init_list(struct omap_mux *superset) entry = omap_mux_list_add(superset); if (!entry) { - printk(KERN_ERR "mux: Could not add entry\n"); + pr_err("mux: Could not add entry\n"); return; } superset++; @@ -738,7 +738,7 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size, mux_phys = mux_pbase; mux_base = ioremap(mux_pbase, mux_size); if (!mux_base) { - printk(KERN_ERR "mux: Could not ioremap\n"); + pr_err("mux: Could not ioremap\n"); return -ENODEV; } -- cgit v1.2.3 From 112485e9c543b17fc08daea56c7a558b415d06af Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 16 Aug 2010 10:55:35 +0200 Subject: OMAP: mux: Add support for control module split in several partitions Starting on OMAP4, the pin mux configuration is located in two different partitions of the control module (CODE_PAD and WKUP_PAD). The first one is inside the core power domain whereas the second one is inside the wakeup. - Add the capability to add any number of partition during board init time depending of Soc partitioning. - Add some init flags as well in order to avoid explicit Soc version check inside the mux core code. - Add a comment with mux0 mode on top of omap_mux/board/ if the current mux mode is not the default one. Thanks to Tony Lindgren for the following improvements: - Add omap_mux_get for getting the partition data so platform level device code can use it. - Fix the rx51 board code to use the new API. - Do not store the partition for each mux entry. Look up the partition for debugfs instead. Thanks to Dan Murphy for testing on OMAP4 and reporting a couple of bugs. Thanks to Anand Gadiyar for testing on OMAP3 zoom and bug report. Signed-off-by: Benoit Cousson Signed-off-by: Tony Lindgren Tested-by: Murphy Dan Cc: Paul Walmsley Cc: Kevin Hilman Cc: Santosh Shilimkar Cc: Anand Gadiyar --- arch/arm/mach-omap2/board-rx51-peripherals.c | 12 +- arch/arm/mach-omap2/mux.c | 337 ++++++++++++++++++--------- arch/arm/mach-omap2/mux.h | 70 +++++- arch/arm/mach-omap2/mux2420.c | 7 +- arch/arm/mach-omap2/mux2430.c | 7 +- arch/arm/mach-omap2/mux34xx.c | 7 +- 6 files changed, 312 insertions(+), 128 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 3fec4d62a91a..3fda20d73233 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -293,6 +293,8 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; +static struct omap_mux_partition *partition; + /* * Current flows to eMMC when eMMC is off and the data lines are pulled up, * so pull them down. N.B. we pull 8 lines because we are using 8 lines. @@ -300,9 +302,9 @@ static struct omap_board_mux rx51_mmc2_off_mux[] = { static void rx51_mmc2_remux(struct device *dev, int slot, int power_on) { if (power_on) - omap_mux_write_array(rx51_mmc2_on_mux); + omap_mux_write_array(partition, rx51_mmc2_on_mux); else - omap_mux_write_array(rx51_mmc2_off_mux); + omap_mux_write_array(partition, rx51_mmc2_off_mux); } static struct omap2_hsmmc_info mmc[] __initdata = { @@ -922,7 +924,11 @@ void __init rx51_peripherals_init(void) rx51_init_wl1251(); spi_register_board_info(rx51_peripherals_spi_board_info, ARRAY_SIZE(rx51_peripherals_spi_board_info)); - omap2_hsmmc_init(mmc); + + partition = omap_mux_get("core"); + if (partition) + omap2_hsmmc_init(mmc); + platform_device_register(&rx51_charger_device); } diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 979e9d1c4659..92215703b671 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -1,9 +1,9 @@ /* * linux/arch/arm/mach-omap2/mux.c * - * OMAP2 and OMAP3 pin multiplexing configurations + * OMAP2, OMAP3 and OMAP4 pin multiplexing configurations * - * Copyright (C) 2004 - 2008 Texas Instruments Inc. + * Copyright (C) 2004 - 2010 Texas Instruments Inc. * Copyright (C) 2003 - 2008 Nokia Corporation * * Written by Tony Lindgren @@ -40,60 +40,72 @@ #define OMAP_MUX_BASE_OFFSET 0x30 /* Offset from CTRL_BASE */ #define OMAP_MUX_BASE_SZ 0x5ca -#define MUXABLE_GPIO_MODE3 BIT(0) struct omap_mux_entry { struct omap_mux mux; struct list_head node; }; -static unsigned long mux_phys; -static void __iomem *mux_base; -static u8 omap_mux_flags; +static LIST_HEAD(mux_partitions); +static DEFINE_MUTEX(muxmode_mutex); + +struct omap_mux_partition *omap_mux_get(const char *name) +{ + struct omap_mux_partition *partition; + + list_for_each_entry(partition, &mux_partitions, node) { + if (!strcmp(name, partition->name)) + return partition; + } -u16 omap_mux_read(u16 reg) + return NULL; +} + +u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg) { - if (cpu_is_omap24xx()) - return __raw_readb(mux_base + reg); + if (partition->flags & OMAP_MUX_REG_8BIT) + return __raw_readb(partition->base + reg); else - return __raw_readw(mux_base + reg); + return __raw_readw(partition->base + reg); } -void omap_mux_write(u16 val, u16 reg) +void omap_mux_write(struct omap_mux_partition *partition, u16 val, + u16 reg) { - if (cpu_is_omap24xx()) - __raw_writeb(val, mux_base + reg); + if (partition->flags & OMAP_MUX_REG_8BIT) + __raw_writeb(val, partition->base + reg); else - __raw_writew(val, mux_base + reg); + __raw_writew(val, partition->base + reg); } -void omap_mux_write_array(struct omap_board_mux *board_mux) +void omap_mux_write_array(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { - while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { - omap_mux_write(board_mux->value, board_mux->reg_offset); + while (board_mux->reg_offset != OMAP_MUX_TERMINATOR) { + omap_mux_write(partition, board_mux->value, + board_mux->reg_offset); board_mux++; } } -static LIST_HEAD(muxmodes); -static DEFINE_MUTEX(muxmode_mutex); - #ifdef CONFIG_OMAP_MUX static char *omap_mux_options; -int __init omap_mux_init_gpio(int gpio, int val) +static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, + int gpio, int val) { struct omap_mux_entry *e; struct omap_mux *gpio_mux = NULL; u16 old_mode; u16 mux_mode; int found = 0; + struct list_head *muxmodes = &partition->muxmodes; if (!gpio) return -EINVAL; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, muxmodes, node) { struct omap_mux *m = &e->mux; if (gpio == m->gpio) { gpio_mux = m; @@ -112,24 +124,40 @@ int __init omap_mux_init_gpio(int gpio, int val) return -EINVAL; } - old_mode = omap_mux_read(gpio_mux->reg_offset); + old_mode = omap_mux_read(partition, gpio_mux->reg_offset); mux_mode = val & ~(OMAP_MUX_NR_MODES - 1); - if (omap_mux_flags & MUXABLE_GPIO_MODE3) + if (partition->flags & OMAP_MUX_GPIO_IN_MODE3) mux_mode |= OMAP_MUX_MODE3; else mux_mode |= OMAP_MUX_MODE4; pr_debug("mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", gpio_mux->muxnames[0], gpio, old_mode, mux_mode); - omap_mux_write(mux_mode, gpio_mux->reg_offset); + omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); return 0; } -int __init omap_mux_init_signal(const char *muxname, int val) +int __init omap_mux_init_gpio(int gpio, int val) +{ + struct omap_mux_partition *partition; + int ret; + + list_for_each_entry(partition, &mux_partitions, node) { + ret = _omap_mux_init_gpio(partition, gpio, val); + if (!ret) + return ret; + } + + return -ENODEV; +} + +static int __init _omap_mux_init_signal(struct omap_mux_partition *partition, + const char *muxname, int val) { struct omap_mux_entry *e; const char *mode_name; int found = 0, mode0_len = 0; + struct list_head *muxmodes = &partition->muxmodes; mode_name = strchr(muxname, '.'); if (mode_name) { @@ -139,7 +167,7 @@ int __init omap_mux_init_signal(const char *muxname, int val) mode_name = muxname; } - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, muxmodes, node) { struct omap_mux *m = &e->mux; char *m0_entry = m->muxnames[0]; int i; @@ -159,12 +187,14 @@ int __init omap_mux_init_signal(const char *muxname, int val) u16 old_mode; u16 mux_mode; - old_mode = omap_mux_read(m->reg_offset); + old_mode = omap_mux_read(partition, + m->reg_offset); mux_mode = val | i; pr_debug("mux: Setting signal " "%s.%s 0x%04x -> 0x%04x\n", m0_entry, muxname, old_mode, mux_mode); - omap_mux_write(mux_mode, m->reg_offset); + omap_mux_write(partition, mux_mode, + m->reg_offset); found++; } } @@ -184,6 +214,21 @@ int __init omap_mux_init_signal(const char *muxname, int val) return -ENODEV; } +int __init omap_mux_init_signal(const char *muxname, int val) +{ + struct omap_mux_partition *partition; + int ret; + + list_for_each_entry(partition, &mux_partitions, node) { + ret = _omap_mux_init_signal(partition, muxname, val); + if (!ret) + return ret; + } + + return -ENODEV; + +} + #ifdef CONFIG_DEBUG_FS #define OMAP_MUX_MAX_NR_FLAGS 10 @@ -248,13 +293,15 @@ static inline void omap_mux_decode(struct seq_file *s, u16 val) } while (i-- > 0); } -#define OMAP_MUX_DEFNAME_LEN 16 +#define OMAP_MUX_DEFNAME_LEN 32 static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) { + struct omap_mux_partition *partition = s->private; struct omap_mux_entry *e; + u8 omap_gen = omap_rev() >> 28; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; char m0_def[OMAP_MUX_DEFNAME_LEN]; char *m0_name = m->muxnames[0]; @@ -272,11 +319,16 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) } m0_def[i] = toupper(m0_name[i]); } - val = omap_mux_read(m->reg_offset); + val = omap_mux_read(partition, m->reg_offset); mode = val & OMAP_MUX_MODE7; - - seq_printf(s, "OMAP%i_MUX(%s, ", - cpu_is_omap34xx() ? 3 : 0, m0_def); + if (mode != 0) + seq_printf(s, "/* %s */\n", m->muxnames[mode]); + + /* + * XXX: Might be revisited to support differences accross + * same OMAP generation. + */ + seq_printf(s, "OMAP%d_MUX(%s, ", omap_gen, m0_def); omap_mux_decode(s, val); seq_printf(s, "),\n"); } @@ -286,7 +338,7 @@ static int omap_mux_dbg_board_show(struct seq_file *s, void *unused) static int omap_mux_dbg_board_open(struct inode *inode, struct file *file) { - return single_open(file, omap_mux_dbg_board_show, &inode->i_private); + return single_open(file, omap_mux_dbg_board_show, inode->i_private); } static const struct file_operations omap_mux_dbg_board_fops = { @@ -296,19 +348,43 @@ static const struct file_operations omap_mux_dbg_board_fops = { .release = single_release, }; +static struct omap_mux_partition *omap_mux_get_partition(struct omap_mux *mux) +{ + struct omap_mux_partition *partition; + + list_for_each_entry(partition, &mux_partitions, node) { + struct list_head *muxmodes = &partition->muxmodes; + struct omap_mux_entry *e; + + list_for_each_entry(e, muxmodes, node) { + struct omap_mux *m = &e->mux; + + if (m == mux) + return partition; + } + } + + return NULL; +} + static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) { struct omap_mux *m = s->private; + struct omap_mux_partition *partition; const char *none = "NA"; u16 val; int mode; - val = omap_mux_read(m->reg_offset); + partition = omap_mux_get_partition(m); + if (!partition) + return 0; + + val = omap_mux_read(partition, m->reg_offset); mode = val & OMAP_MUX_MODE7; - seq_printf(s, "name: %s.%s (0x%08lx/0x%03x = 0x%04x), b %s, t %s\n", + seq_printf(s, "name: %s.%s (0x%08x/0x%03x = 0x%04x), b %s, t %s\n", m->muxnames[0], m->muxnames[mode], - mux_phys + m->reg_offset, m->reg_offset, val, + partition->phys + m->reg_offset, m->reg_offset, val, m->balls[0] ? m->balls[0] : none, m->balls[1] ? m->balls[1] : none); seq_printf(s, "mode: "); @@ -330,14 +406,15 @@ static int omap_mux_dbg_signal_show(struct seq_file *s, void *unused) #define OMAP_MUX_MAX_ARG_CHAR 7 static ssize_t omap_mux_dbg_signal_write(struct file *file, - const char __user *user_buf, - size_t count, loff_t *ppos) + const char __user *user_buf, + size_t count, loff_t *ppos) { char buf[OMAP_MUX_MAX_ARG_CHAR]; struct seq_file *seqf; struct omap_mux *m; unsigned long val; int buf_size, ret; + struct omap_mux_partition *partition; if (count > OMAP_MUX_MAX_ARG_CHAR) return -EINVAL; @@ -358,7 +435,11 @@ static ssize_t omap_mux_dbg_signal_write(struct file *file, seqf = file->private_data; m = seqf->private; - omap_mux_write((u16)val, m->reg_offset); + partition = omap_mux_get_partition(m); + if (!partition) + return -ENODEV; + + omap_mux_write(partition, (u16)val, m->reg_offset); *ppos += count; return count; @@ -379,22 +460,38 @@ static const struct file_operations omap_mux_dbg_signal_fops = { static struct dentry *mux_dbg_dir; -static void __init omap_mux_dbg_init(void) +static void __init omap_mux_dbg_create_entry( + struct omap_mux_partition *partition, + struct dentry *mux_dbg_dir) { struct omap_mux_entry *e; + list_for_each_entry(e, &partition->muxmodes, node) { + struct omap_mux *m = &e->mux; + + (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, + m, &omap_mux_dbg_signal_fops); + } +} + +static void __init omap_mux_dbg_init(void) +{ + struct omap_mux_partition *partition; + static struct dentry *mux_dbg_board_dir; + mux_dbg_dir = debugfs_create_dir("omap_mux", NULL); if (!mux_dbg_dir) return; - (void)debugfs_create_file("board", S_IRUGO, mux_dbg_dir, - NULL, &omap_mux_dbg_board_fops); - - list_for_each_entry(e, &muxmodes, node) { - struct omap_mux *m = &e->mux; + mux_dbg_board_dir = debugfs_create_dir("board", mux_dbg_dir); + if (!mux_dbg_board_dir) + return; - (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir, - m, &omap_mux_dbg_signal_fops); + list_for_each_entry(partition, &mux_partitions, node) { + omap_mux_dbg_create_entry(partition, mux_dbg_dir); + (void)debugfs_create_file(partition->name, S_IRUGO, + mux_dbg_board_dir, partition, + &omap_mux_dbg_board_fops); } } @@ -421,23 +518,25 @@ static void __init omap_mux_free_names(struct omap_mux *m) /* Free all data except for GPIO pins unless CONFIG_DEBUG_FS is set */ static int __init omap_mux_late_init(void) { - struct omap_mux_entry *e, *tmp; + struct omap_mux_partition *partition; - list_for_each_entry_safe(e, tmp, &muxmodes, node) { - struct omap_mux *m = &e->mux; - u16 mode = omap_mux_read(m->reg_offset); + list_for_each_entry(partition, &mux_partitions, node) { + struct omap_mux_entry *e, *tmp; + list_for_each_entry_safe(e, tmp, &partition->muxmodes, node) { + struct omap_mux *m = &e->mux; + u16 mode = omap_mux_read(partition, m->reg_offset); - if (OMAP_MODE_GPIO(mode)) - continue; + if (OMAP_MODE_GPIO(mode)) + continue; #ifndef CONFIG_DEBUG_FS - mutex_lock(&muxmode_mutex); - list_del(&e->node); - mutex_unlock(&muxmode_mutex); - omap_mux_free_names(m); - kfree(m); + mutex_lock(&muxmode_mutex); + list_del(&e->node); + mutex_unlock(&muxmode_mutex); + omap_mux_free_names(m); + kfree(m); #endif - + } } omap_mux_dbg_init(); @@ -554,7 +653,7 @@ static void __init omap_mux_set_cmdline_signals(void) } static int __init omap_mux_copy_names(struct omap_mux *src, - struct omap_mux *dst) + struct omap_mux *dst) { int i; @@ -592,51 +691,63 @@ free: #endif /* CONFIG_OMAP_MUX */ -static u16 omap_mux_get_by_gpio(int gpio) +static struct omap_mux *omap_mux_get_by_gpio( + struct omap_mux_partition *partition, + int gpio) { struct omap_mux_entry *e; - u16 offset = OMAP_MUX_TERMINATOR; + struct omap_mux *ret = NULL; - list_for_each_entry(e, &muxmodes, node) { + list_for_each_entry(e, &partition->muxmodes, node) { struct omap_mux *m = &e->mux; if (m->gpio == gpio) { - offset = m->reg_offset; + ret = m; break; } } - return offset; + return ret; } /* Needed for dynamic muxing of GPIO pins for off-idle */ u16 omap_mux_get_gpio(int gpio) { - u16 offset; + struct omap_mux_partition *partition; + struct omap_mux *m; - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - pr_err("mux: Could not get gpio%i\n", gpio); - return offset; + list_for_each_entry(partition, &mux_partitions, node) { + m = omap_mux_get_by_gpio(partition, gpio); + if (m) + return omap_mux_read(partition, m->reg_offset); } - return omap_mux_read(offset); + if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) + pr_err("mux: Could not get gpio%i\n", gpio); + + return OMAP_MUX_TERMINATOR; } /* Needed for dynamic muxing of GPIO pins for off-idle */ void omap_mux_set_gpio(u16 val, int gpio) { - u16 offset; + struct omap_mux_partition *partition; + struct omap_mux *m = NULL; - offset = omap_mux_get_by_gpio(gpio); - if (offset == OMAP_MUX_TERMINATOR) { - pr_err("mux: Could not set gpio%i\n", gpio); - return; + list_for_each_entry(partition, &mux_partitions, node) { + m = omap_mux_get_by_gpio(partition, gpio); + if (m) { + omap_mux_write(partition, val, m->reg_offset); + return; + } } - omap_mux_write(val, offset); + if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) + pr_err("mux: Could not set gpio%i\n", gpio); } -static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) +static struct omap_mux * __init omap_mux_list_add( + struct omap_mux_partition *partition, + struct omap_mux *src) { struct omap_mux_entry *entry; struct omap_mux *m; @@ -656,7 +767,7 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) #endif mutex_lock(&muxmode_mutex); - list_add_tail(&entry->node, &muxmodes); + list_add_tail(&entry->node, &partition->muxmodes); mutex_unlock(&muxmode_mutex); return m; @@ -667,7 +778,8 @@ static struct omap_mux * __init omap_mux_list_add(struct omap_mux *src) * the GPIO to mux offset mapping that is needed for dynamic muxing * of GPIO pins for off-idle. */ -static void __init omap_mux_init_list(struct omap_mux *superset) +static void __init omap_mux_init_list(struct omap_mux_partition *partition, + struct omap_mux *superset) { while (superset->reg_offset != OMAP_MUX_TERMINATOR) { struct omap_mux *entry; @@ -679,13 +791,14 @@ static void __init omap_mux_init_list(struct omap_mux *superset) } #else /* Skip pins that are not muxed as GPIO by bootloader */ - if (!OMAP_MODE_GPIO(omap_mux_read(superset->reg_offset))) { + if (!OMAP_MODE_GPIO(omap_mux_read(partition, + superset->reg_offset))) { superset++; continue; } #endif - entry = omap_mux_list_add(superset); + entry = omap_mux_list_add(partition, superset); if (!entry) { pr_err("mux: Could not add entry\n"); return; @@ -706,10 +819,11 @@ static void omap_mux_init_package(struct omap_mux *superset, omap_mux_package_init_balls(package_balls, superset); } -static void omap_mux_init_signals(struct omap_board_mux *board_mux) +static void omap_mux_init_signals(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { omap_mux_set_cmdline_signals(); - omap_mux_write_array(board_mux); + omap_mux_write_array(partition, board_mux); } #else @@ -720,34 +834,49 @@ static void omap_mux_init_package(struct omap_mux *superset, { } -static void omap_mux_init_signals(struct omap_board_mux *board_mux) +static void omap_mux_init_signals(struct omap_mux_partition *partition, + struct omap_board_mux *board_mux) { } #endif -int __init omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls) -{ - if (mux_base) - return -EBUSY; +static u32 mux_partitions_cnt; - mux_phys = mux_pbase; - mux_base = ioremap(mux_pbase, mux_size); - if (!mux_base) { - pr_err("mux: Could not ioremap\n"); +int __init omap_mux_init(const char *name, u32 flags, + u32 mux_pbase, u32 mux_size, + struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_board_mux *board_mux, + struct omap_ball *package_balls) +{ + struct omap_mux_partition *partition; + + partition = kzalloc(sizeof(struct omap_mux_partition), GFP_KERNEL); + if (!partition) + return -ENOMEM; + + partition->name = name; + partition->flags = flags; + partition->size = mux_size; + partition->phys = mux_pbase; + partition->base = ioremap(mux_pbase, mux_size); + if (!partition->base) { + pr_err("mux: Could not ioremap mux partition at 0x%08x\n", + partition->phys); return -ENODEV; } - if (cpu_is_omap24xx()) - omap_mux_flags = MUXABLE_GPIO_MODE3; + INIT_LIST_HEAD(&partition->muxmodes); + + list_add_tail(&partition->node, &mux_partitions); + mux_partitions_cnt++; + pr_info("MUX: Add partition: #%d: %s, flags: %x\n", + mux_partitions_cnt, partition->name, partition->flags); omap_mux_init_package(superset, package_subset, package_balls); - omap_mux_init_list(superset); - omap_mux_init_signals(board_mux); + omap_mux_init_list(partition, superset); + omap_mux_init_signals(partition, board_mux); return 0; } diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 350c04f27383..86549bedd526 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2009 Nokia - * Copyright (C) 2009 Texas Instruments + * Copyright (C) 2009-2010 Texas Instruments * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -56,7 +56,7 @@ #define OMAP_MODE_GPIO(x) (((x) & OMAP_MUX_MODE7) == OMAP_MUX_MODE4) -/* Flags for omap_mux_init */ +/* Flags for omapX_mux_init */ #define OMAP_PACKAGE_MASK 0xffff #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ @@ -66,14 +66,47 @@ #define OMAP_PACKAGE_ZAF 1 /* 2420 447-pin SIP */ -#define OMAP_MUX_NR_MODES 8 /* Available modes */ -#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ +#define OMAP_MUX_NR_MODES 8 /* Available modes */ +#define OMAP_MUX_NR_SIDES 2 /* Bottom & top */ + +/* + * omap_mux_init flags definition: + * + * OMAP_MUX_REG_8BIT: Ensure that access to padconf is done in 8 bits. + * The default value is 16 bits. + * OMAP_MUX_GPIO_IN_MODE3: The GPIO is selected in mode3. + * The default is mode4. + */ +#define OMAP_MUX_REG_8BIT (1 << 0) +#define OMAP_MUX_GPIO_IN_MODE3 (1 << 1) + +/** + * struct mux_partition - contain partition related information + * @name: name of the current partition + * @flags: flags specific to this partition + * @phys: physical address + * @size: partition size + * @base: virtual address after ioremap + * @muxmodes: list of nodes that belong to a partition + * @node: list node for the partitions linked list + */ +struct omap_mux_partition { + const char *name; + u32 flags; + u32 phys; + u32 size; + void __iomem *base; + struct list_head muxmodes; + struct list_head node; +}; /** * struct omap_mux - data for omap mux register offset and it's value * @reg_offset: mux register offset from the mux base * @gpio: GPIO number * @muxnames: available signal modes for a ball + * @balls: available balls on the package + * @partition: mux partition */ struct omap_mux { u16 reg_offset; @@ -150,29 +183,40 @@ u16 omap_mux_get_gpio(int gpio); */ void omap_mux_set_gpio(u16 val, int gpio); +/** + * omap_mux_get() - get a mux partition by name + * @name: Name of the mux partition + * + */ +struct omap_mux_partition *omap_mux_get(const char *name); + /** * omap_mux_read() - read mux register + * @partition: Mux partition * @mux_offset: Offset of the mux register * */ -u16 omap_mux_read(u16 mux_offset); +u16 omap_mux_read(struct omap_mux_partition *p, u16 mux_offset); /** * omap_mux_write() - write mux register + * @partition: Mux partition * @val: New mux register value * @mux_offset: Offset of the mux register * * This should be only needed for dynamic remuxing of non-gpio signals. */ -void omap_mux_write(u16 val, u16 mux_offset); +void omap_mux_write(struct omap_mux_partition *p, u16 val, u16 mux_offset); /** * omap_mux_write_array() - write an array of mux registers + * @partition: Mux partition * @board_mux: Array of mux registers terminated by MAP_MUX_TERMINATOR * * This should be only needed for dynamic remuxing of non-gpio signals. */ -void omap_mux_write_array(struct omap_board_mux *board_mux); +void omap_mux_write_array(struct omap_mux_partition *p, + struct omap_board_mux *board_mux); /** * omap2420_mux_init() - initialize mux system with board specific set @@ -198,8 +242,10 @@ int omap3_mux_init(struct omap_board_mux *board_mux, int flags); /** * omap_mux_init - private mux init function, do not call */ -int omap_mux_init(u32 mux_pbase, u32 mux_size, - struct omap_mux *superset, - struct omap_mux *package_subset, - struct omap_board_mux *board_mux, - struct omap_ball *package_balls); +int omap_mux_init(const char *name, u32 flags, + u32 mux_pbase, u32 mux_size, + struct omap_mux *superset, + struct omap_mux *package_subset, + struct omap_board_mux *board_mux, + struct omap_ball *package_balls); + diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index 414af5434456..8231f0ae4856 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c @@ -681,8 +681,9 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) pr_warning("mux: No ball data available for omap2420 package\n"); } - return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, + OMAP2420_CONTROL_PADCONF_MUX_PBASE, OMAP2420_CONTROL_PADCONF_MUX_SIZE, - omap2420_muxmodes, NULL, board_subset, - package_balls); + omap2420_muxmodes, NULL, board_subset, + package_balls); } diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index 84d2c5a7ecd7..cb6b40436e19 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c @@ -784,8 +784,9 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) pr_warning("mux: No ball data available for omap2420 package\n"); } - return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, + OMAP2430_CONTROL_PADCONF_MUX_PBASE, OMAP2430_CONTROL_PADCONF_MUX_SIZE, - omap2430_muxmodes, NULL, board_subset, - package_balls); + omap2430_muxmodes, NULL, board_subset, + package_balls); } diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 574e54ea3ab7..4113c93d3f27 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2053,8 +2053,9 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) return -EINVAL; } - return omap_mux_init(OMAP3_CONTROL_PADCONF_MUX_PBASE, + return omap_mux_init("core", 0, + OMAP3_CONTROL_PADCONF_MUX_PBASE, OMAP3_CONTROL_PADCONF_MUX_SIZE, - omap3_muxmodes, package_subset, board_subset, - package_balls); + omap3_muxmodes, package_subset, board_subset, + package_balls); } -- cgit v1.2.3 From a041a52c4d2b82e25de2267bce5f4dc3d2179b2a Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 10 Aug 2010 17:27:48 +0200 Subject: OMAP4: mux: Add CBL package data for OMAP4430 ES1 Add data for OMAP4430 generated from HW pinout & register database. The data set is split in two partitions for both core and wkup. Signed-off-by: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/Kconfig | 3 + arch/arm/mach-omap2/Makefile | 1 + arch/arm/mach-omap2/mux.h | 12 + arch/arm/mach-omap2/mux44xx.c | 900 ++++++++++++++++++++++++++++++++++++++++++ arch/arm/mach-omap2/mux44xx.h | 277 +++++++++++++ 5 files changed, 1193 insertions(+) create mode 100644 arch/arm/mach-omap2/mux44xx.c create mode 100644 arch/arm/mach-omap2/mux44xx.h (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index ab784bfde908..e14c73d81997 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -85,6 +85,9 @@ config OMAP_PACKAGE_CUS config OMAP_PACKAGE_CBP bool +config OMAP_PACKAGE_CBL + bool + comment "OMAP Board Type" depends on ARCH_OMAP2PLUS diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 60e51bcf53bd..d32d660abab1 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -42,6 +42,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a obj-$(CONFIG_ARCH_OMAP2420) += mux2420.o obj-$(CONFIG_ARCH_OMAP2430) += mux2430.o obj-$(CONFIG_ARCH_OMAP3) += mux34xx.o +obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o # SMS/SDRC obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 86549bedd526..7aca779b588c 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -10,6 +10,7 @@ #include "mux2420.h" #include "mux2430.h" #include "mux34xx.h" +#include "mux44xx.h" #define OMAP_MUX_TERMINATOR 0xffff @@ -37,6 +38,9 @@ #define OMAP_OFF_PULL_UP (1 << 13) #define OMAP_WAKEUP_EN (1 << 14) +/* 44xx specific mux bit defines */ +#define OMAP_WAKEUP_EVENT (1 << 15) + /* Active pin states */ #define OMAP_PIN_OUTPUT 0 #define OMAP_PIN_INPUT OMAP_INPUT_EN @@ -58,6 +62,7 @@ /* Flags for omapX_mux_init */ #define OMAP_PACKAGE_MASK 0xffff +#define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ #define OMAP_PACKAGE_CBB 4 /* 515-pin 0.40 0.50 */ @@ -239,6 +244,13 @@ int omap2430_mux_init(struct omap_board_mux *board_mux, int flags); */ int omap3_mux_init(struct omap_board_mux *board_mux, int flags); +/** + * omap4_mux_init() - initialize mux system with board specific set + * @board_mux: Board specific mux table + * @flags: OMAP package type used for the board + */ +int omap4_mux_init(struct omap_board_mux *board_mux, int flags); + /** * omap_mux_init - private mux init function, do not call */ diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c new file mode 100644 index 000000000000..5e9d60a18146 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.c @@ -0,0 +1,900 @@ +/* + * OMAP44xx ES1.0 pin mux definition + * + * Copyright (C) 2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * - Based on mux34xx.c done by Tony Lindgren + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include +#include + +#include "mux.h" + +#ifdef CONFIG_OMAP_MUX + +#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .gpio = (g), \ + .muxnames = { m0, m1, m2, m3, m4, m5, m6, m7 }, \ +} + +#else + +#define _OMAP4_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .gpio = (g), \ +} + +#endif + +#define _OMAP4_BALLENTRY(M0, bb, bt) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .balls = { bb, bt }, \ +} + +/* + * Superset of all mux modes for omap4 + */ +static struct omap_mux __initdata omap4_core_muxmodes[] = { + _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", + "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", + "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", + "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", + "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", + "gpio_32", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", + "gpio_33", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", + "gpio_34", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", + "gpio_35", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", + "gpio_36", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", + "gpio_37", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", + "gpio_38", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", + "gpio_39", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", + "gpio_40", "venc_656_data0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", + "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", + "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", + "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", + "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", + "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", + "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", + "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", NULL, "c2c_clkout0", + "gpio_48", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", + "gpio_49", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", + "sys_ndmareq0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", + "gpio_51", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", NULL, "c2c_dataout7", + "gpio_52", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", + "c2c_dataout4", "gpio_53", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", + "sys_ndmareq1", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", + "sys_ndmareq2", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, + "gpio_56", "sys_ndmareq3", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, + "gpio_59", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", + "gpio_60", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, + "gpio_61", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", + "gpio_62", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA11, 100, "c2c_data11", "usbc1_icusb_txen", + "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA12, 101, "c2c_data12", "dsi1_te0", + "c2c_clkin0", "gpio_101", "sys_ndmareq1", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA13, 102, "c2c_data13", "dsi1_te1", + "c2c_clkin1", "gpio_102", "sys_ndmareq2", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA14, 103, "c2c_data14", "dsi2_te0", + "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(C2C_DATA15, 104, "c2c_data15", "dsi2_te1", + "c2c_dataout1", "gpio_104", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, + "gpio_65", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, + "gpio_66", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, + "gpio_83", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", + "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", + NULL, "hw_dbg20", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", + "hsi1_cadata", "mcbsp4_clkr", "gpio_85", + "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", + "hsi1_caflag", "mcbsp4_fsr", "gpio_86", + "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", + "hsi1_acready", "mcbsp4_fsx", "gpio_87", + "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", + "hsi1_acwake", "mcbsp4_clkx", "gpio_88", + "usbb1_ulpiphy_dat0", "usbb1_mm_rxrcv", "hw_dbg24", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", + "hsi1_acdata", "mcbsp4_dx", "gpio_89", + "usbb1_ulpiphy_dat1", "usbb1_mm_txse0", "hw_dbg25", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", + "hsi1_acflag", "mcbsp4_dr", "gpio_90", + "usbb1_ulpiphy_dat2", "usbb1_mm_txdat", "hw_dbg26", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", + "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", + "usbb1_mm_txen", "hw_dbg27", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", + "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", + "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", + "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", + "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", + "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", + "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", + "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", + "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, + "gpio_96", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, + NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, + "gpio_98", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, + "gpio_99", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", + "gpio_100", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", + "gpio_101", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", + "gpio_102", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", + "gpio_103", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", + "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", + "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, + "gpio_106", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, + "gpio_107", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, + "gpio_108", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, + "gpio_109", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", + "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", + "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", + "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", + "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", + "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", + "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", + "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", + "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", + "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", + "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, + "gpio_119", "usbb2_mm_txse0", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, + "gpio_120", "usbb2_mm_txdat", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", + NULL, "gpio_121", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", + "abe_dmic_clk2", "gpio_122", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, + "gpio_123", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, + "gpio_124", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, + "gpio_125", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, + "gpio_126", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", + "gpio_127", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, + "gpio_128", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, + "gpio_129", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, + "gpio_135", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, + "gpio_136", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, + "gpio_138", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", + "slimbus2_clock", "gpio_139", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", + "slimbus2_data", "gpio_140", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", + NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, + "gpio_142", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", + "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", + "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", + "usbc1_icusb_dp", "gpio_145", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", + "usbc1_icusb_dm", "gpio_146", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", + "usbc1_icusb_rcv", "gpio_147", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, + "usbc1_icusb_txen", "gpio_148", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, + "gpio_149", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, + "gpio_150", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", NULL, + "gpio_151", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", NULL, + "gpio_152", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", NULL, + "gpio_153", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", NULL, + "gpio_154", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", NULL, + "gpio_155", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", NULL, + "gpio_156", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", + "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", + "hsi2_cawake", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", + "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", + "hsi2_cadata", "dispc2_data23", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", + "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", + "hsi2_caflag", "dispc2_data22", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", + "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", + "hsi2_acready", "dispc2_data21", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", + "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", + "hsi2_acwake", "dispc2_data20", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", + "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", + "hsi2_acdata", "dispc2_data19", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", + "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", + "hsi2_acflag", "dispc2_data18", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", + "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", + "hsi2_caready", "dispc2_data15", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", + "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", + "mcspi3_somi", "dispc2_data14", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", + "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", + "mcspi3_cs0", "dispc2_data13", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", + "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", + "mcspi3_simo", "dispc2_data12", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", + "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", + "mcspi3_clk", "dispc2_data11", NULL, "reserved"), + _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, + "gpio_169", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, + NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX0, 171, "unipro_tx0", "kpd_col0", NULL, + "gpio_171", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY0, 172, "unipro_ty0", "kpd_col1", NULL, + "gpio_172", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX1, 173, "unipro_tx1", "kpd_col2", NULL, + "gpio_173", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY1, 174, "unipro_ty1", "kpd_col3", NULL, + "gpio_174", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TX2, 0, "unipro_tx2", "kpd_col4", NULL, + "gpio_0", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_TY2, 1, "unipro_ty2", "kpd_col5", NULL, + "gpio_1", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX0, 0, "unipro_rx0", "kpd_row0", NULL, + "gpi_175", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY0, 0, "unipro_ry0", "kpd_row1", NULL, + "gpi_176", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX1, 0, "unipro_rx1", "kpd_row2", NULL, + "gpi_177", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY1, 0, "unipro_ry1", "kpd_row3", NULL, + "gpi_178", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RX2, 0, "unipro_rx2", "kpd_row4", NULL, + "gpi_2", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UNIPRO_RY2, 0, "unipro_ry2", "kpd_row5", NULL, + "gpi_3", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(USBA0_OTG_DP, 179, "usba0_otg_dp", "uart3_rx_irrx", + "uart2_rx", "gpio_179", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_DM, 180, "usba0_otg_dm", "uart3_tx_irtx", + "uart2_tx", "gpio_180", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, + "gpio_181", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, + "gpio_182", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, + NULL, "hw_dbg0", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, + NULL, "hw_dbg1", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, + "gpio_13", NULL, "dispc2_fid", "hw_dbg2", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, + "gpio_14", NULL, "dispc2_data10", "hw_dbg3", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, + "gpio_15", NULL, "dispc2_data9", "hw_dbg4", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, + "gpio_16", "rfbi_te_vsync0", "dispc2_data16", + "hw_dbg5", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", + "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", + "dispc2_data17", "hw_dbg6", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", + "uart3_rx_irrx", "gpio_18", "rfbi_cs0", + "dispc2_hsync", "hw_dbg7", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", + "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", + "hw_dbg8", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", + "uart3_cts_rctx", "gpio_20", "rfbi_we", + "dispc2_vsync", "hw_dbg9", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", + NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", + "reserved"), + _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", + NULL, "gpio_22", "rfbi_data8", "dispc2_data8", + "hw_dbg11", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", + NULL, "gpio_23", "rfbi_data7", "dispc2_data7", + "hw_dbg12", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", + NULL, "gpio_24", "rfbi_data6", "dispc2_data6", + "hw_dbg13", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", + "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", + "hw_dbg14", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", + NULL, "gpio_26", "rfbi_data4", "dispc2_data4", + "hw_dbg15", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", + "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", + "hw_dbg16", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", + "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", + "hw_dbg17", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", + "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", + "hw_dbg18", "reserved"), + _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", + "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", + "hw_dbg19", "reserved"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBL package + * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBL) +struct omap_ball __initdata omap4_core_cbl_ball[] = { + _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), + _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), + _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), + _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), + _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), + _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), + _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), + _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), + _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), + _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), + _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), + _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), + _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), + _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), + _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), + _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), + _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), + _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), + _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), + _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), + _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), + _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), + _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), + _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), + _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), + _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), + _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), + _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), + _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), + _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), + _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), + _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), + _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), + _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), + _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), + _OMAP4_BALLENTRY(C2C_DATA11, "d23", NULL), + _OMAP4_BALLENTRY(C2C_DATA12, "a24", NULL), + _OMAP4_BALLENTRY(C2C_DATA13, "b24", NULL), + _OMAP4_BALLENTRY(C2C_DATA14, "c24", NULL), + _OMAP4_BALLENTRY(C2C_DATA15, "d24", NULL), + _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), + _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), + _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), + _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), + _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), + _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), + _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), + _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), + _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), + _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), + _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), + _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), + _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), + _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), + _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), + _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), + _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), + _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), + _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), + _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), + _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), + _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), + _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), + _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), + _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), + _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), + _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), + _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), + _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), + _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), + _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), + _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), + _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), + _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), + _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), + _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), + _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), + _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), + _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), + _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), + _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), + _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), + _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), + _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), + _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), + _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), + _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), + _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX0, "g26", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY0, "g25", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX1, "h26", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY1, "h25", NULL), + _OMAP4_BALLENTRY(UNIPRO_TX2, "j27", NULL), + _OMAP4_BALLENTRY(UNIPRO_TY2, "h27", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX0, "j26", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY0, "j25", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX1, "k26", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY1, "k25", NULL), + _OMAP4_BALLENTRY(UNIPRO_RX2, "l27", NULL), + _OMAP4_BALLENTRY(UNIPRO_RY2, "k27", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), + _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), + _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), + _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), + _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), + _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), + _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), + _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), + _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), + _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), + _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), + _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), + _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), + _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), + _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), + _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), + _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), + _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), + _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), + _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), + _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), + _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), + _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), + _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), + _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), + _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_core_cbl_ball NULL +#endif + +/* + * Superset of all mux modes for omap4 + */ +static struct omap_mux __initdata omap4_wkup_muxmodes[] = { + _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, + "c2c_wakereqin", NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, + "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", + "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", + NULL, "gpio_wk7", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, + "gpio_wk8", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, + NULL, "gpio_wk29", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, + "gpio_wk9", "c2c_wakereqout", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, + "gpio_wk10", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBL package + * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBL) +struct omap_ball __initdata omap4_wkup_cbl_ball[] = { + _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), + _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), + _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), + _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), + _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), + _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), + _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), + _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), + _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), + _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), + _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), + _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), + _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), + _OMAP4_BALLENTRY(FREF_CLK4_REQ, "ac2", NULL), + _OMAP4_BALLENTRY(FREF_CLK4_OUT, "ac3", NULL), + _OMAP4_BALLENTRY(SYS_32K, "ag7", NULL), + _OMAP4_BALLENTRY(SYS_NRESPWRON, "ae7", NULL), + _OMAP4_BALLENTRY(SYS_NRESWARM, "af7", NULL), + _OMAP4_BALLENTRY(SYS_PWR_REQ, "ah7", NULL), + _OMAP4_BALLENTRY(SYS_PWRON_RESET_OUT, "ag6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT6, "af8", NULL), + _OMAP4_BALLENTRY(SYS_BOOT7, "ae8", NULL), + _OMAP4_BALLENTRY(JTAG_NTRST, "ah2", NULL), + _OMAP4_BALLENTRY(JTAG_TCK, "ag1", NULL), + _OMAP4_BALLENTRY(JTAG_RTCK, "ae3", NULL), + _OMAP4_BALLENTRY(JTAG_TMS_TMSC, "ah1", NULL), + _OMAP4_BALLENTRY(JTAG_TDI, "ae1", NULL), + _OMAP4_BALLENTRY(JTAG_TDO, "ae2", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_wkup_cbl_ball NULL +#endif + + +int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) +{ + struct omap_ball *package_balls_core, *package_balls_wkup; + int ret; + + switch (flags & OMAP_PACKAGE_MASK) { + case OMAP_PACKAGE_CBL: + package_balls_core = omap4_core_cbl_ball; + package_balls_wkup = omap4_wkup_cbl_ball; + break; + default: + pr_err("mux: Unknown omap package, mux disabled\n"); + return -EINVAL; + } + + ret = omap_mux_init("core", + OMAP_MUX_GPIO_IN_MODE3, + OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, + OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, + omap4_core_muxmodes, NULL, board_subset, + package_balls_core); + if (ret) + return ret; + + ret = omap_mux_init("wkup", + OMAP_MUX_GPIO_IN_MODE3, + OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE, + OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE, + omap4_wkup_muxmodes, NULL, board_subset, + package_balls_wkup); + + return ret; +} + diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h new file mode 100644 index 000000000000..ea8b235d1487 --- /dev/null +++ b/arch/arm/mach-omap2/mux44xx.h @@ -0,0 +1,277 @@ +/* + * OMAP44xx MUX registers and bitfields + * + * Copyright (C) 2009-2010 Texas Instruments, Inc. + * + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_MUX_44XX_H +#define __ARCH_ARM_MACH_OMAP2_MUX_44XX_H + +#define OMAP4_MUX(M0, mux_value) \ +{ \ + .reg_offset = (OMAP4_CTRL_MODULE_PAD_##M0##_OFFSET), \ + .value = (mux_value), \ +} + +/* ctrl_module_pad_core base address */ +#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE 0x4a100000 + +/* ctrl_module_pad_core registers offset */ +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET 0x0040 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD1_OFFSET 0x0042 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD2_OFFSET 0x0044 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD3_OFFSET 0x0046 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD4_OFFSET 0x0048 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD5_OFFSET 0x004a +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD6_OFFSET 0x004c +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD7_OFFSET 0x004e +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD8_OFFSET 0x0050 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD9_OFFSET 0x0052 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD10_OFFSET 0x0054 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD11_OFFSET 0x0056 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD12_OFFSET 0x0058 +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD13_OFFSET 0x005a +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD14_OFFSET 0x005c +#define OMAP4_CTRL_MODULE_PAD_GPMC_AD15_OFFSET 0x005e +#define OMAP4_CTRL_MODULE_PAD_GPMC_A16_OFFSET 0x0060 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A17_OFFSET 0x0062 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A18_OFFSET 0x0064 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A19_OFFSET 0x0066 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A20_OFFSET 0x0068 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A21_OFFSET 0x006a +#define OMAP4_CTRL_MODULE_PAD_GPMC_A22_OFFSET 0x006c +#define OMAP4_CTRL_MODULE_PAD_GPMC_A23_OFFSET 0x006e +#define OMAP4_CTRL_MODULE_PAD_GPMC_A24_OFFSET 0x0070 +#define OMAP4_CTRL_MODULE_PAD_GPMC_A25_OFFSET 0x0072 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS0_OFFSET 0x0074 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS1_OFFSET 0x0076 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS2_OFFSET 0x0078 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS3_OFFSET 0x007a +#define OMAP4_CTRL_MODULE_PAD_GPMC_NWP_OFFSET 0x007c +#define OMAP4_CTRL_MODULE_PAD_GPMC_CLK_OFFSET 0x007e +#define OMAP4_CTRL_MODULE_PAD_GPMC_NADV_ALE_OFFSET 0x0080 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NOE_OFFSET 0x0082 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NWE_OFFSET 0x0084 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE0_CLE_OFFSET 0x0086 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NBE1_OFFSET 0x0088 +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT0_OFFSET 0x008a +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT1_OFFSET 0x008c +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA11_OFFSET 0x008e +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA12_OFFSET 0x0090 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA13_OFFSET 0x0092 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA14_OFFSET 0x0094 +#define OMAP4_CTRL_MODULE_PAD_C2C_DATA15_OFFSET 0x0096 +#define OMAP4_CTRL_MODULE_PAD_HDMI_HPD_OFFSET 0x0098 +#define OMAP4_CTRL_MODULE_PAD_HDMI_CEC_OFFSET 0x009a +#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SCL_OFFSET 0x009c +#define OMAP4_CTRL_MODULE_PAD_HDMI_DDC_SDA_OFFSET 0x009e +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX0_OFFSET 0x00a0 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY0_OFFSET 0x00a2 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX1_OFFSET 0x00a4 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY1_OFFSET 0x00a6 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX2_OFFSET 0x00a8 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY2_OFFSET 0x00aa +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX3_OFFSET 0x00ac +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY3_OFFSET 0x00ae +#define OMAP4_CTRL_MODULE_PAD_CSI21_DX4_OFFSET 0x00b0 +#define OMAP4_CTRL_MODULE_PAD_CSI21_DY4_OFFSET 0x00b2 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DX0_OFFSET 0x00b4 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DY0_OFFSET 0x00b6 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DX1_OFFSET 0x00b8 +#define OMAP4_CTRL_MODULE_PAD_CSI22_DY1_OFFSET 0x00ba +#define OMAP4_CTRL_MODULE_PAD_CAM_SHUTTER_OFFSET 0x00bc +#define OMAP4_CTRL_MODULE_PAD_CAM_STROBE_OFFSET 0x00be +#define OMAP4_CTRL_MODULE_PAD_CAM_GLOBALRESET_OFFSET 0x00c0 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_CLK_OFFSET 0x00c2 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_STP_OFFSET 0x00c4 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DIR_OFFSET 0x00c6 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_NXT_OFFSET 0x00c8 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT0_OFFSET 0x00ca +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT1_OFFSET 0x00cc +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT2_OFFSET 0x00ce +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT3_OFFSET 0x00d0 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT4_OFFSET 0x00d2 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT5_OFFSET 0x00d4 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT6_OFFSET 0x00d6 +#define OMAP4_CTRL_MODULE_PAD_USBB1_ULPITLL_DAT7_OFFSET 0x00d8 +#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_DATA_OFFSET 0x00da +#define OMAP4_CTRL_MODULE_PAD_USBB1_HSIC_STROBE_OFFSET 0x00dc +#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DP_OFFSET 0x00de +#define OMAP4_CTRL_MODULE_PAD_USBC1_ICUSB_DM_OFFSET 0x00e0 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CLK_OFFSET 0x00e2 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_CMD_OFFSET 0x00e4 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT0_OFFSET 0x00e6 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT1_OFFSET 0x00e8 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT2_OFFSET 0x00ea +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT3_OFFSET 0x00ec +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT4_OFFSET 0x00ee +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT5_OFFSET 0x00f0 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT6_OFFSET 0x00f2 +#define OMAP4_CTRL_MODULE_PAD_SDMMC1_DAT7_OFFSET 0x00f4 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_CLKX_OFFSET 0x00f6 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DR_OFFSET 0x00f8 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_DX_OFFSET 0x00fa +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP2_FSX_OFFSET 0x00fc +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_CLKX_OFFSET 0x00fe +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DR_OFFSET 0x0100 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_DX_OFFSET 0x0102 +#define OMAP4_CTRL_MODULE_PAD_ABE_MCBSP1_FSX_OFFSET 0x0104 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_UL_DATA_OFFSET 0x0106 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_DL_DATA_OFFSET 0x0108 +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_FRAME_OFFSET 0x010a +#define OMAP4_CTRL_MODULE_PAD_ABE_PDM_LB_CLK_OFFSET 0x010c +#define OMAP4_CTRL_MODULE_PAD_ABE_CLKS_OFFSET 0x010e +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_CLK1_OFFSET 0x0110 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN1_OFFSET 0x0112 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN2_OFFSET 0x0114 +#define OMAP4_CTRL_MODULE_PAD_ABE_DMIC_DIN3_OFFSET 0x0116 +#define OMAP4_CTRL_MODULE_PAD_UART2_CTS_OFFSET 0x0118 +#define OMAP4_CTRL_MODULE_PAD_UART2_RTS_OFFSET 0x011a +#define OMAP4_CTRL_MODULE_PAD_UART2_RX_OFFSET 0x011c +#define OMAP4_CTRL_MODULE_PAD_UART2_TX_OFFSET 0x011e +#define OMAP4_CTRL_MODULE_PAD_HDQ_SIO_OFFSET 0x0120 +#define OMAP4_CTRL_MODULE_PAD_I2C1_SCL_OFFSET 0x0122 +#define OMAP4_CTRL_MODULE_PAD_I2C1_SDA_OFFSET 0x0124 +#define OMAP4_CTRL_MODULE_PAD_I2C2_SCL_OFFSET 0x0126 +#define OMAP4_CTRL_MODULE_PAD_I2C2_SDA_OFFSET 0x0128 +#define OMAP4_CTRL_MODULE_PAD_I2C3_SCL_OFFSET 0x012a +#define OMAP4_CTRL_MODULE_PAD_I2C3_SDA_OFFSET 0x012c +#define OMAP4_CTRL_MODULE_PAD_I2C4_SCL_OFFSET 0x012e +#define OMAP4_CTRL_MODULE_PAD_I2C4_SDA_OFFSET 0x0130 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CLK_OFFSET 0x0132 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SOMI_OFFSET 0x0134 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_SIMO_OFFSET 0x0136 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS0_OFFSET 0x0138 +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS1_OFFSET 0x013a +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS2_OFFSET 0x013c +#define OMAP4_CTRL_MODULE_PAD_MCSPI1_CS3_OFFSET 0x013e +#define OMAP4_CTRL_MODULE_PAD_UART3_CTS_RCTX_OFFSET 0x0140 +#define OMAP4_CTRL_MODULE_PAD_UART3_RTS_SD_OFFSET 0x0142 +#define OMAP4_CTRL_MODULE_PAD_UART3_RX_IRRX_OFFSET 0x0144 +#define OMAP4_CTRL_MODULE_PAD_UART3_TX_IRTX_OFFSET 0x0146 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CLK_OFFSET 0x0148 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_CMD_OFFSET 0x014a +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT0_OFFSET 0x014c +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT1_OFFSET 0x014e +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT2_OFFSET 0x0150 +#define OMAP4_CTRL_MODULE_PAD_SDMMC5_DAT3_OFFSET 0x0152 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CLK_OFFSET 0x0154 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SIMO_OFFSET 0x0156 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_SOMI_OFFSET 0x0158 +#define OMAP4_CTRL_MODULE_PAD_MCSPI4_CS0_OFFSET 0x015a +#define OMAP4_CTRL_MODULE_PAD_UART4_RX_OFFSET 0x015c +#define OMAP4_CTRL_MODULE_PAD_UART4_TX_OFFSET 0x015e +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_CLK_OFFSET 0x0160 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_STP_OFFSET 0x0162 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DIR_OFFSET 0x0164 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_NXT_OFFSET 0x0166 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT0_OFFSET 0x0168 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT1_OFFSET 0x016a +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT2_OFFSET 0x016c +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT3_OFFSET 0x016e +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT4_OFFSET 0x0170 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT5_OFFSET 0x0172 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT6_OFFSET 0x0174 +#define OMAP4_CTRL_MODULE_PAD_USBB2_ULPITLL_DAT7_OFFSET 0x0176 +#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_DATA_OFFSET 0x0178 +#define OMAP4_CTRL_MODULE_PAD_USBB2_HSIC_STROBE_OFFSET 0x017a +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX0_OFFSET 0x017c +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY0_OFFSET 0x017e +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX1_OFFSET 0x0180 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY1_OFFSET 0x0182 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TX2_OFFSET 0x0184 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_TY2_OFFSET 0x0186 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX0_OFFSET 0x0188 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY0_OFFSET 0x018a +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX1_OFFSET 0x018c +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY1_OFFSET 0x018e +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RX2_OFFSET 0x0190 +#define OMAP4_CTRL_MODULE_PAD_UNIPRO_RY2_OFFSET 0x0192 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_CE_OFFSET 0x0194 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DP_OFFSET 0x0196 +#define OMAP4_CTRL_MODULE_PAD_USBA0_OTG_DM_OFFSET 0x0198 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK1_OUT_OFFSET 0x019a +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK2_OUT_OFFSET 0x019c +#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ1_OFFSET 0x019e +#define OMAP4_CTRL_MODULE_PAD_SYS_NIRQ2_OFFSET 0x01a0 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT0_OFFSET 0x01a2 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT1_OFFSET 0x01a4 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT2_OFFSET 0x01a6 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT3_OFFSET 0x01a8 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT4_OFFSET 0x01aa +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT5_OFFSET 0x01ac +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU0_OFFSET 0x01ae +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU1_OFFSET 0x01b0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU2_OFFSET 0x01b2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU3_OFFSET 0x01b4 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU4_OFFSET 0x01b6 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU5_OFFSET 0x01b8 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU6_OFFSET 0x01ba +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU7_OFFSET 0x01bc +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU8_OFFSET 0x01be +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU9_OFFSET 0x01c0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU10_OFFSET 0x01c2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU11_OFFSET 0x01c4 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU12_OFFSET 0x01c6 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU13_OFFSET 0x01c8 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU14_OFFSET 0x01ca +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU15_OFFSET 0x01cc +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU16_OFFSET 0x01ce +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU17_OFFSET 0x01d0 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 +#define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 + +#define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ + (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ + - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) + +/* ctrl_module_pad_wkup base address */ +#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_PBASE 0x4a31e000 + +/* ctrl_module_pad_wkup registers offset */ +#define OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET 0x0040 +#define OMAP4_CTRL_MODULE_PAD_SIM_CLK_OFFSET 0x0042 +#define OMAP4_CTRL_MODULE_PAD_SIM_RESET_OFFSET 0x0044 +#define OMAP4_CTRL_MODULE_PAD_SIM_CD_OFFSET 0x0046 +#define OMAP4_CTRL_MODULE_PAD_SIM_PWRCTRL_OFFSET 0x0048 +#define OMAP4_CTRL_MODULE_PAD_SR_SCL_OFFSET 0x004a +#define OMAP4_CTRL_MODULE_PAD_SR_SDA_OFFSET 0x004c +#define OMAP4_CTRL_MODULE_PAD_FREF_XTAL_IN_OFFSET 0x004e +#define OMAP4_CTRL_MODULE_PAD_FREF_SLICER_IN_OFFSET 0x0050 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK_IOREQ_OFFSET 0x0052 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK0_OUT_OFFSET 0x0054 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_REQ_OFFSET 0x0056 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK3_OUT_OFFSET 0x0058 +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_REQ_OFFSET 0x005a +#define OMAP4_CTRL_MODULE_PAD_FREF_CLK4_OUT_OFFSET 0x005c +#define OMAP4_CTRL_MODULE_PAD_SYS_32K_OFFSET 0x005e +#define OMAP4_CTRL_MODULE_PAD_SYS_NRESPWRON_OFFSET 0x0060 +#define OMAP4_CTRL_MODULE_PAD_SYS_NRESWARM_OFFSET 0x0062 +#define OMAP4_CTRL_MODULE_PAD_SYS_PWR_REQ_OFFSET 0x0064 +#define OMAP4_CTRL_MODULE_PAD_SYS_PWRON_RESET_OUT_OFFSET 0x0066 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT6_OFFSET 0x0068 +#define OMAP4_CTRL_MODULE_PAD_SYS_BOOT7_OFFSET 0x006a +#define OMAP4_CTRL_MODULE_PAD_JTAG_NTRST_OFFSET 0x006c +#define OMAP4_CTRL_MODULE_PAD_JTAG_TCK_OFFSET 0x006e +#define OMAP4_CTRL_MODULE_PAD_JTAG_RTCK_OFFSET 0x0070 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TMS_TMSC_OFFSET 0x0072 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TDI_OFFSET 0x0074 +#define OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET 0x0076 + +#define OMAP4_CTRL_MODULE_PAD_WKUP_MUX_SIZE \ + (OMAP4_CTRL_MODULE_PAD_JTAG_TDO_OFFSET \ + - OMAP4_CTRL_MODULE_PAD_SIM_IO_OFFSET + 2) + +#endif -- cgit v1.2.3 From fb6bf6320e33af5bd6ac788f27245f9162bc5215 Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Tue, 10 Aug 2010 17:43:15 +0200 Subject: OMAP4: sdp4430: Select CBL package for ES1 and initialize mux Select the CBL package if SDP4430 is enabled during config. Initialize the mux framework during the board init. Signed-off-by: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Kevin Hilman --- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/board-4430sdp.c | 10 ++++++++++ 2 files changed, 11 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index e14c73d81997..7efb256819a0 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -280,6 +280,7 @@ config MACH_OMAP_4430SDP bool "OMAP 4430 SDP board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index df5a425a49d1..e4f1726e6669 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -35,6 +35,7 @@ #include #include +#include "mux.h" #include "hsmmc.h" #include "timer-gp.h" #include "control.h" @@ -505,10 +506,19 @@ static void __init omap_sfh7741prox_init(void) } } +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap_4430sdp_init(void) { int status; + omap4_mux_init(board_mux, OMAP_PACKAGE_CBL); omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); -- cgit v1.2.3 From a7722d8796c3431163943c30af7a90d87c43180a Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Fri, 24 Sep 2010 16:56:59 +0200 Subject: OMAP4: mux: Add CBS package data for OMAP4430 ES2 Please note that the full muxmodes are re-defined for ES2 instead of using the subset. There are 81 differences among 204 pins. The subset fixup will have to iterate over the whole list for each subset entry, which can lead to an important number of iteration. On the other hand, it will take much more memory at boot time. Signed-off-by: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Anand Gadiyar --- arch/arm/mach-omap2/Kconfig | 3 + arch/arm/mach-omap2/mux.h | 1 + arch/arm/mach-omap2/mux44xx.c | 889 ++++++++++++++++++++++++++++++++++++++---- arch/arm/mach-omap2/mux44xx.h | 21 + 4 files changed, 832 insertions(+), 82 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 7efb256819a0..92fea6395d58 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -88,6 +88,9 @@ config OMAP_PACKAGE_CBP config OMAP_PACKAGE_CBL bool +config OMAP_PACKAGE_CBS + bool + comment "OMAP Board Type" depends on ARCH_OMAP2PLUS diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h index 7aca779b588c..79076d61d399 100644 --- a/arch/arm/mach-omap2/mux.h +++ b/arch/arm/mach-omap2/mux.h @@ -62,6 +62,7 @@ /* Flags for omapX_mux_init */ #define OMAP_PACKAGE_MASK 0xffff +#define OMAP_PACKAGE_CBS 8 /* 547-pin 0.40 0.40 */ #define OMAP_PACKAGE_CBL 7 /* 547-pin 0.40 0.40 */ #define OMAP_PACKAGE_CBP 6 /* 515-pin 0.40 0.50 */ #define OMAP_PACKAGE_CUS 5 /* 423-pin 0.65 */ diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c index 5e9d60a18146..80335f395d28 100644 --- a/arch/arm/mach-omap2/mux44xx.c +++ b/arch/arm/mach-omap2/mux44xx.c @@ -48,7 +48,7 @@ } /* - * Superset of all mux modes for omap4 + * Superset of all mux modes for omap4 ES1.0 */ static struct omap_mux __initdata omap4_core_muxmodes[] = { _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, @@ -755,90 +755,808 @@ struct omap_ball __initdata omap4_core_cbl_ball[] = { #endif /* - * Superset of all mux modes for omap4 + * Superset of all mux modes for omap4 ES2.0 */ -static struct omap_mux __initdata omap4_wkup_muxmodes[] = { - _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, +static struct omap_mux __initdata omap4_es2_core_muxmodes[] = { + _OMAP4_MUXENTRY(GPMC_AD0, 0, "gpmc_ad0", "sdmmc2_dat0", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD1, 0, "gpmc_ad1", "sdmmc2_dat1", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD2, 0, "gpmc_ad2", "sdmmc2_dat2", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD3, 0, "gpmc_ad3", "sdmmc2_dat3", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD4, 0, "gpmc_ad4", "sdmmc2_dat4", + "sdmmc2_dir_dat0", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD5, 0, "gpmc_ad5", "sdmmc2_dat5", + "sdmmc2_dir_dat1", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD6, 0, "gpmc_ad6", "sdmmc2_dat6", + "sdmmc2_dir_cmd", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD7, 0, "gpmc_ad7", "sdmmc2_dat7", + "sdmmc2_clk_fdbk", NULL, NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD8, 32, "gpmc_ad8", "kpd_row0", "c2c_data15", + "gpio_32", NULL, "sdmmc1_dat0", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD9, 33, "gpmc_ad9", "kpd_row1", "c2c_data14", + "gpio_33", NULL, "sdmmc1_dat1", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD10, 34, "gpmc_ad10", "kpd_row2", "c2c_data13", + "gpio_34", NULL, "sdmmc1_dat2", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD11, 35, "gpmc_ad11", "kpd_row3", "c2c_data12", + "gpio_35", NULL, "sdmmc1_dat3", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD12, 36, "gpmc_ad12", "kpd_col0", "c2c_data11", + "gpio_36", NULL, "sdmmc1_dat4", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD13, 37, "gpmc_ad13", "kpd_col1", "c2c_data10", + "gpio_37", NULL, "sdmmc1_dat5", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD14, 38, "gpmc_ad14", "kpd_col2", "c2c_data9", + "gpio_38", NULL, "sdmmc1_dat6", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_AD15, 39, "gpmc_ad15", "kpd_col3", "c2c_data8", + "gpio_39", NULL, "sdmmc1_dat7", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_A16, 40, "gpmc_a16", "kpd_row4", "c2c_datain0", + "gpio_40", "venc_656_data0", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A17, 41, "gpmc_a17", "kpd_row5", "c2c_datain1", + "gpio_41", "venc_656_data1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A18, 42, "gpmc_a18", "kpd_row6", "c2c_datain2", + "gpio_42", "venc_656_data2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A19, 43, "gpmc_a19", "kpd_row7", "c2c_datain3", + "gpio_43", "venc_656_data3", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A20, 44, "gpmc_a20", "kpd_col4", "c2c_datain4", + "gpio_44", "venc_656_data4", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A21, 45, "gpmc_a21", "kpd_col5", "c2c_datain5", + "gpio_45", "venc_656_data5", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A22, 46, "gpmc_a22", "kpd_col6", "c2c_datain6", + "gpio_46", "venc_656_data6", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A23, 47, "gpmc_a23", "kpd_col7", "c2c_datain7", + "gpio_47", "venc_656_data7", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A24, 48, "gpmc_a24", "kpd_col8", "c2c_clkout0", + "gpio_48", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_A25, 49, "gpmc_a25", NULL, "c2c_clkout1", + "gpio_49", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS0, 50, "gpmc_ncs0", NULL, NULL, "gpio_50", + "sys_ndmareq0", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NCS1, 51, "gpmc_ncs1", NULL, "c2c_dataout6", + "gpio_51", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS2, 52, "gpmc_ncs2", "kpd_row8", + "c2c_dataout7", "gpio_52", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS3, 53, "gpmc_ncs3", "gpmc_dir", + "c2c_dataout4", "gpio_53", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NWP, 54, "gpmc_nwp", "dsi1_te0", NULL, "gpio_54", + "sys_ndmareq1", NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_CLK, 55, "gpmc_clk", NULL, NULL, "gpio_55", + "sys_ndmareq2", "sdmmc1_cmd", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NADV_ALE, 56, "gpmc_nadv_ale", "dsi1_te1", NULL, + "gpio_56", "sys_ndmareq3", "sdmmc1_clk", NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NOE, 0, "gpmc_noe", "sdmmc2_clk", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NWE, 0, "gpmc_nwe", "sdmmc2_cmd", NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE0_CLE, 59, "gpmc_nbe0_cle", "dsi2_te0", NULL, + "gpio_59", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_NBE1, 60, "gpmc_nbe1", NULL, "c2c_dataout5", + "gpio_60", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT0, 61, "gpmc_wait0", "dsi2_te1", NULL, + "gpio_61", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(GPMC_WAIT1, 62, "gpmc_wait1", NULL, "c2c_dataout2", + "gpio_62", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_WAIT2, 100, "gpmc_wait2", "usbc1_icusb_txen", + "c2c_dataout3", "gpio_100", "sys_ndmareq0", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS4, 101, "gpmc_ncs4", "dsi1_te0", "c2c_clkin0", + "gpio_101", "sys_ndmareq1", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS5, 102, "gpmc_ncs5", "dsi1_te1", "c2c_clkin1", + "gpio_102", "sys_ndmareq2", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS6, 103, "gpmc_ncs6", "dsi2_te0", + "c2c_dataout0", "gpio_103", "sys_ndmareq3", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(GPMC_NCS7, 104, "gpmc_ncs7", "dsi2_te1", + "c2c_dataout1", "gpio_104", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(HDMI_HPD, 63, "hdmi_hpd", NULL, NULL, "gpio_63", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, + _OMAP4_MUXENTRY(HDMI_CEC, 64, "hdmi_cec", NULL, NULL, "gpio_64", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, + _OMAP4_MUXENTRY(HDMI_DDC_SCL, 65, "hdmi_ddc_scl", NULL, NULL, + "gpio_65", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDMI_DDC_SDA, 66, "hdmi_ddc_sda", NULL, NULL, + "gpio_66", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX0, 0, "csi21_dx0", NULL, NULL, "gpi_67", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", + _OMAP4_MUXENTRY(CSI21_DY0, 0, "csi21_dy0", NULL, NULL, "gpi_68", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX1, 0, "csi21_dx1", NULL, NULL, "gpi_69", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY1, 0, "csi21_dy1", NULL, NULL, "gpi_70", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX2, 0, "csi21_dx2", NULL, NULL, "gpi_71", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY2, 0, "csi21_dy2", NULL, NULL, "gpi_72", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX3, 0, "csi21_dx3", NULL, NULL, "gpi_73", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY3, 0, "csi21_dy3", NULL, NULL, "gpi_74", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DX4, 0, "csi21_dx4", NULL, NULL, "gpi_75", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI21_DY4, 0, "csi21_dy4", NULL, NULL, "gpi_76", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX0, 0, "csi22_dx0", NULL, NULL, "gpi_77", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY0, 0, "csi22_dy0", NULL, NULL, "gpi_78", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DX1, 0, "csi22_dx1", NULL, NULL, "gpi_79", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CSI22_DY1, 0, "csi22_dy1", NULL, NULL, "gpi_80", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_SHUTTER, 81, "cam_shutter", NULL, NULL, "gpio_81", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, - "c2c_wakereqin", NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, - "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", - "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, + _OMAP4_MUXENTRY(CAM_STROBE, 82, "cam_strobe", NULL, NULL, "gpio_82", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(CAM_GLOBALRESET, 83, "cam_globalreset", NULL, NULL, + "gpio_83", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_CLK, 84, "usbb1_ulpitll_clk", + "hsi1_cawake", NULL, "gpio_84", "usbb1_ulpiphy_clk", + NULL, "hw_dbg20", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_STP, 85, "usbb1_ulpitll_stp", + "hsi1_cadata", "mcbsp4_clkr", "gpio_85", + "usbb1_ulpiphy_stp", "usbb1_mm_rxdp", "hw_dbg21", "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", - "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, - NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", - "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", - NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", - NULL, "gpio_wk7", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, - "gpio_wk8", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, - NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, - NULL, "gpio_wk29", NULL, NULL, NULL, NULL), - _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, - "gpio_wk9", "c2c_wakereqout", NULL, NULL, + _OMAP4_MUXENTRY(USBB1_ULPITLL_DIR, 86, "usbb1_ulpitll_dir", + "hsi1_caflag", "mcbsp4_fsr", "gpio_86", + "usbb1_ulpiphy_dir", NULL, "hw_dbg22", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_NXT, 87, "usbb1_ulpitll_nxt", + "hsi1_acready", "mcbsp4_fsx", "gpio_87", + "usbb1_ulpiphy_nxt", "usbb1_mm_rxdm", "hw_dbg23", "safe_mode"), - _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, - "gpio_wk10", NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT0, 88, "usbb1_ulpitll_dat0", + "hsi1_acwake", "mcbsp4_clkx", "gpio_88", + "usbb1_ulpiphy_dat0", "usbb1_mm_txen", "hw_dbg24", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT1, 89, "usbb1_ulpitll_dat1", + "hsi1_acdata", "mcbsp4_dx", "gpio_89", + "usbb1_ulpiphy_dat1", "usbb1_mm_txdat", "hw_dbg25", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT2, 90, "usbb1_ulpitll_dat2", + "hsi1_acflag", "mcbsp4_dr", "gpio_90", + "usbb1_ulpiphy_dat2", "usbb1_mm_txse0", "hw_dbg26", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT3, 91, "usbb1_ulpitll_dat3", + "hsi1_caready", NULL, "gpio_91", "usbb1_ulpiphy_dat3", + "usbb1_mm_rxrcv", "hw_dbg27", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT4, 92, "usbb1_ulpitll_dat4", + "dmtimer8_pwm_evt", "abe_mcbsp3_dr", "gpio_92", + "usbb1_ulpiphy_dat4", NULL, "hw_dbg28", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT5, 93, "usbb1_ulpitll_dat5", + "dmtimer9_pwm_evt", "abe_mcbsp3_dx", "gpio_93", + "usbb1_ulpiphy_dat5", NULL, "hw_dbg29", "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT6, 94, "usbb1_ulpitll_dat6", + "dmtimer10_pwm_evt", "abe_mcbsp3_clkx", "gpio_94", + "usbb1_ulpiphy_dat6", "abe_dmic_din3", "hw_dbg30", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_ULPITLL_DAT7, 95, "usbb1_ulpitll_dat7", + "dmtimer11_pwm_evt", "abe_mcbsp3_fsx", "gpio_95", + "usbb1_ulpiphy_dat7", "abe_dmic_clk3", "hw_dbg31", + "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_DATA, 96, "usbb1_hsic_data", NULL, NULL, + "gpio_96", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB1_HSIC_STROBE, 97, "usbb1_hsic_strobe", NULL, + NULL, "gpio_97", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DP, 98, "usbc1_icusb_dp", NULL, NULL, + "gpio_98", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBC1_ICUSB_DM, 99, "usbc1_icusb_dm", NULL, NULL, + "gpio_99", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CLK, 100, "sdmmc1_clk", NULL, "dpm_emu19", + "gpio_100", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_CMD, 101, "sdmmc1_cmd", NULL, "uart1_rx", + "gpio_101", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT0, 102, "sdmmc1_dat0", NULL, "dpm_emu18", + "gpio_102", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT1, 103, "sdmmc1_dat1", NULL, "dpm_emu17", + "gpio_103", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT2, 104, "sdmmc1_dat2", NULL, "dpm_emu16", + "gpio_104", "jtag_tms_tmsc", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT3, 105, "sdmmc1_dat3", NULL, "dpm_emu15", + "gpio_105", "jtag_tck", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT4, 106, "sdmmc1_dat4", NULL, NULL, + "gpio_106", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT5, 107, "sdmmc1_dat5", NULL, NULL, + "gpio_107", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT6, 108, "sdmmc1_dat6", NULL, NULL, + "gpio_108", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC1_DAT7, 109, "sdmmc1_dat7", NULL, NULL, + "gpio_109", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_CLKX, 110, "abe_mcbsp2_clkx", "mcspi2_clk", + "abe_mcasp_ahclkx", "gpio_110", "usbb2_mm_rxdm", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_DR, 111, "abe_mcbsp2_dr", "mcspi2_somi", + "abe_mcasp_axr", "gpio_111", "usbb2_mm_rxdp", NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, - NULL, NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, - NULL, NULL, NULL, "safe_mode"), - _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, - NULL, NULL), - { .reg_offset = OMAP_MUX_TERMINATOR }, -}; - -/* - * Balls for 44XX CBL package - * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), - * 0.40mm Ball Pitch (Bottom) - */ -#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ - && defined(CONFIG_OMAP_PACKAGE_CBL) -struct omap_ball __initdata omap4_wkup_cbl_ball[] = { - _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), - _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), - _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), - _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), - _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), - _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), - _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), - _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), - _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), - _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), + _OMAP4_MUXENTRY(ABE_MCBSP2_DX, 112, "abe_mcbsp2_dx", "mcspi2_simo", + "abe_mcasp_amute", "gpio_112", "usbb2_mm_rxrcv", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP2_FSX, 113, "abe_mcbsp2_fsx", "mcspi2_cs0", + "abe_mcasp_afsx", "gpio_113", "usbb2_mm_txen", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_CLKX, 114, "abe_mcbsp1_clkx", + "abe_slimbus1_clock", NULL, "gpio_114", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DR, 115, "abe_mcbsp1_dr", + "abe_slimbus1_data", NULL, "gpio_115", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_DX, 116, "abe_mcbsp1_dx", "sdmmc3_dat2", + "abe_mcasp_aclkx", "gpio_116", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_MCBSP1_FSX, 117, "abe_mcbsp1_fsx", "sdmmc3_dat3", + "abe_mcasp_amutein", "gpio_117", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_UL_DATA, 0, "abe_pdm_ul_data", + "abe_mcbsp3_dr", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_DL_DATA, 0, "abe_pdm_dl_data", + "abe_mcbsp3_dx", NULL, NULL, NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_FRAME, 0, "abe_pdm_frame", "abe_mcbsp3_clkx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_PDM_LB_CLK, 0, "abe_pdm_lb_clk", "abe_mcbsp3_fsx", + NULL, NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_CLKS, 118, "abe_clks", NULL, NULL, "gpio_118", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_CLK1, 119, "abe_dmic_clk1", NULL, NULL, + "gpio_119", "usbb2_mm_txse0", "uart4_cts", NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN1, 120, "abe_dmic_din1", NULL, NULL, + "gpio_120", "usbb2_mm_txdat", "uart4_rts", NULL, + "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN2, 121, "abe_dmic_din2", "slimbus2_clock", + "abe_mcasp_axr", "gpio_121", NULL, + "dmtimer11_pwm_evt", NULL, "safe_mode"), + _OMAP4_MUXENTRY(ABE_DMIC_DIN3, 122, "abe_dmic_din3", "slimbus2_data", + "abe_dmic_clk2", "gpio_122", NULL, "dmtimer9_pwm_evt", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_CTS, 123, "uart2_cts", "sdmmc3_clk", NULL, + "gpio_123", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RTS, 124, "uart2_rts", "sdmmc3_cmd", NULL, + "gpio_124", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_RX, 125, "uart2_rx", "sdmmc3_dat0", NULL, + "gpio_125", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART2_TX, 126, "uart2_tx", "sdmmc3_dat1", NULL, + "gpio_126", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(HDQ_SIO, 127, "hdq_sio", "i2c3_sccb", "i2c2_sccb", + "gpio_127", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C1_SCL, 0, "i2c1_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C1_SDA, 0, "i2c1_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(I2C2_SCL, 128, "i2c2_scl", "uart1_rx", NULL, + "gpio_128", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C2_SDA, 129, "i2c2_sda", "uart1_tx", NULL, + "gpio_129", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SCL, 130, "i2c3_scl", NULL, NULL, "gpio_130", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C3_SDA, 131, "i2c3_sda", NULL, NULL, "gpio_131", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SCL, 132, "i2c4_scl", NULL, NULL, "gpio_132", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(I2C4_SDA, 133, "i2c4_sda", NULL, NULL, "gpio_133", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CLK, 134, "mcspi1_clk", NULL, NULL, "gpio_134", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SOMI, 135, "mcspi1_somi", NULL, NULL, + "gpio_135", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_SIMO, 136, "mcspi1_simo", NULL, NULL, + "gpio_136", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS0, 137, "mcspi1_cs0", NULL, NULL, "gpio_137", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS1, 138, "mcspi1_cs1", "uart1_rx", NULL, + "gpio_138", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS2, 139, "mcspi1_cs2", "uart1_cts", + "slimbus2_clock", "gpio_139", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI1_CS3, 140, "mcspi1_cs3", "uart1_rts", + "slimbus2_data", "gpio_140", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART3_CTS_RCTX, 141, "uart3_cts_rctx", "uart1_tx", + NULL, "gpio_141", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RTS_SD, 142, "uart3_rts_sd", NULL, NULL, + "gpio_142", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_RX_IRRX, 143, "uart3_rx_irrx", + "dmtimer8_pwm_evt", NULL, "gpio_143", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART3_TX_IRTX, 144, "uart3_tx_irtx", + "dmtimer9_pwm_evt", NULL, "gpio_144", NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CLK, 145, "sdmmc5_clk", "mcspi2_clk", + "usbc1_icusb_dp", "gpio_145", NULL, "sdmmc2_clk", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_CMD, 146, "sdmmc5_cmd", "mcspi2_simo", + "usbc1_icusb_dm", "gpio_146", NULL, "sdmmc2_cmd", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT0, 147, "sdmmc5_dat0", "mcspi2_somi", + "usbc1_icusb_rcv", "gpio_147", NULL, "sdmmc2_dat0", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT1, 148, "sdmmc5_dat1", NULL, + "usbc1_icusb_txen", "gpio_148", NULL, "sdmmc2_dat1", + NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT2, 149, "sdmmc5_dat2", "mcspi2_cs1", NULL, + "gpio_149", NULL, "sdmmc2_dat2", NULL, "safe_mode"), + _OMAP4_MUXENTRY(SDMMC5_DAT3, 150, "sdmmc5_dat3", "mcspi2_cs0", NULL, + "gpio_150", NULL, "sdmmc2_dat3", NULL, "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CLK, 151, "mcspi4_clk", "sdmmc4_clk", + "kpd_col6", "gpio_151", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SIMO, 152, "mcspi4_simo", "sdmmc4_cmd", + "kpd_col7", "gpio_152", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_SOMI, 153, "mcspi4_somi", "sdmmc4_dat0", + "kpd_row6", "gpio_153", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(MCSPI4_CS0, 154, "mcspi4_cs0", "sdmmc4_dat3", + "kpd_row7", "gpio_154", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(UART4_RX, 155, "uart4_rx", "sdmmc4_dat2", "kpd_row8", + "gpio_155", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(UART4_TX, 156, "uart4_tx", "sdmmc4_dat1", "kpd_col8", + "gpio_156", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_CLK, 157, "usbb2_ulpitll_clk", + "usbb2_ulpiphy_clk", "sdmmc4_cmd", "gpio_157", + "hsi2_cawake", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_STP, 158, "usbb2_ulpitll_stp", + "usbb2_ulpiphy_stp", "sdmmc4_clk", "gpio_158", + "hsi2_cadata", "dispc2_data23", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DIR, 159, "usbb2_ulpitll_dir", + "usbb2_ulpiphy_dir", "sdmmc4_dat0", "gpio_159", + "hsi2_caflag", "dispc2_data22", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_NXT, 160, "usbb2_ulpitll_nxt", + "usbb2_ulpiphy_nxt", "sdmmc4_dat1", "gpio_160", + "hsi2_acready", "dispc2_data21", NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT0, 161, "usbb2_ulpitll_dat0", + "usbb2_ulpiphy_dat0", "sdmmc4_dat2", "gpio_161", + "hsi2_acwake", "dispc2_data20", "usbb2_mm_txen", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT1, 162, "usbb2_ulpitll_dat1", + "usbb2_ulpiphy_dat1", "sdmmc4_dat3", "gpio_162", + "hsi2_acdata", "dispc2_data19", "usbb2_mm_txdat", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT2, 163, "usbb2_ulpitll_dat2", + "usbb2_ulpiphy_dat2", "sdmmc3_dat2", "gpio_163", + "hsi2_acflag", "dispc2_data18", "usbb2_mm_txse0", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT3, 164, "usbb2_ulpitll_dat3", + "usbb2_ulpiphy_dat3", "sdmmc3_dat1", "gpio_164", + "hsi2_caready", "dispc2_data15", "rfbi_data15", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT4, 165, "usbb2_ulpitll_dat4", + "usbb2_ulpiphy_dat4", "sdmmc3_dat0", "gpio_165", + "mcspi3_somi", "dispc2_data14", "rfbi_data14", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT5, 166, "usbb2_ulpitll_dat5", + "usbb2_ulpiphy_dat5", "sdmmc3_dat3", "gpio_166", + "mcspi3_cs0", "dispc2_data13", "rfbi_data13", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT6, 167, "usbb2_ulpitll_dat6", + "usbb2_ulpiphy_dat6", "sdmmc3_cmd", "gpio_167", + "mcspi3_simo", "dispc2_data12", "rfbi_data12", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_ULPITLL_DAT7, 168, "usbb2_ulpitll_dat7", + "usbb2_ulpiphy_dat7", "sdmmc3_clk", "gpio_168", + "mcspi3_clk", "dispc2_data11", "rfbi_data11", + "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_DATA, 169, "usbb2_hsic_data", NULL, NULL, + "gpio_169", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBB2_HSIC_STROBE, 170, "usbb2_hsic_strobe", NULL, + NULL, "gpio_170", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL3, 171, "kpd_col3", "kpd_col0", NULL, + "gpio_171", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL4, 172, "kpd_col4", "kpd_col1", NULL, + "gpio_172", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL5, 173, "kpd_col5", "kpd_col2", NULL, + "gpio_173", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL0, 174, "kpd_col0", "kpd_col3", NULL, + "gpio_174", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL1, 0, "kpd_col1", "kpd_col4", NULL, "gpio_0", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_COL2, 1, "kpd_col2", "kpd_col5", NULL, "gpio_1", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW3, 175, "kpd_row3", "kpd_row0", NULL, + "gpio_175", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW4, 176, "kpd_row4", "kpd_row1", NULL, + "gpio_176", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW5, 177, "kpd_row5", "kpd_row2", NULL, + "gpio_177", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW0, 178, "kpd_row0", "kpd_row3", NULL, + "gpio_178", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW1, 2, "kpd_row1", "kpd_row4", NULL, "gpio_2", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(KPD_ROW2, 3, "kpd_row2", "kpd_row5", NULL, "gpio_3", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_CE, 0, "usba0_otg_ce", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(USBA0_OTG_DP, 0, "usba0_otg_dp", "uart3_rx_irrx", + "uart2_rx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(USBA0_OTG_DM, 0, "usba0_otg_dm", "uart3_tx_irtx", + "uart2_tx", NULL, NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK1_OUT, 181, "fref_clk1_out", NULL, NULL, + "gpio_181", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK2_OUT, 182, "fref_clk2_out", NULL, NULL, + "gpio_182", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ1, 0, "sys_nirq1", NULL, NULL, NULL, NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_NIRQ2, 183, "sys_nirq2", NULL, NULL, "gpio_183", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT0, 184, "sys_boot0", NULL, NULL, "gpio_184", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT1, 185, "sys_boot1", NULL, NULL, "gpio_185", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT2, 186, "sys_boot2", NULL, NULL, "gpio_186", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT3, 187, "sys_boot3", NULL, NULL, "gpio_187", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT4, 188, "sys_boot4", NULL, NULL, "gpio_188", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT5, 189, "sys_boot5", NULL, NULL, "gpio_189", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU0, 11, "dpm_emu0", NULL, NULL, "gpio_11", NULL, + NULL, "hw_dbg0", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU1, 12, "dpm_emu1", NULL, NULL, "gpio_12", NULL, + NULL, "hw_dbg1", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU2, 13, "dpm_emu2", "usba0_ulpiphy_clk", NULL, + "gpio_13", NULL, "dispc2_fid", "hw_dbg2", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU3, 14, "dpm_emu3", "usba0_ulpiphy_stp", NULL, + "gpio_14", "rfbi_data10", "dispc2_data10", "hw_dbg3", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU4, 15, "dpm_emu4", "usba0_ulpiphy_dir", NULL, + "gpio_15", "rfbi_data9", "dispc2_data9", "hw_dbg4", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU5, 16, "dpm_emu5", "usba0_ulpiphy_nxt", NULL, + "gpio_16", "rfbi_te_vsync0", "dispc2_data16", + "hw_dbg5", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU6, 17, "dpm_emu6", "usba0_ulpiphy_dat0", + "uart3_tx_irtx", "gpio_17", "rfbi_hsync0", + "dispc2_data17", "hw_dbg6", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU7, 18, "dpm_emu7", "usba0_ulpiphy_dat1", + "uart3_rx_irrx", "gpio_18", "rfbi_cs0", + "dispc2_hsync", "hw_dbg7", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU8, 19, "dpm_emu8", "usba0_ulpiphy_dat2", + "uart3_rts_sd", "gpio_19", "rfbi_re", "dispc2_pclk", + "hw_dbg8", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU9, 20, "dpm_emu9", "usba0_ulpiphy_dat3", + "uart3_cts_rctx", "gpio_20", "rfbi_we", + "dispc2_vsync", "hw_dbg9", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU10, 21, "dpm_emu10", "usba0_ulpiphy_dat4", + NULL, "gpio_21", "rfbi_a0", "dispc2_de", "hw_dbg10", + "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU11, 22, "dpm_emu11", "usba0_ulpiphy_dat5", + NULL, "gpio_22", "rfbi_data8", "dispc2_data8", + "hw_dbg11", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU12, 23, "dpm_emu12", "usba0_ulpiphy_dat6", + NULL, "gpio_23", "rfbi_data7", "dispc2_data7", + "hw_dbg12", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU13, 24, "dpm_emu13", "usba0_ulpiphy_dat7", + NULL, "gpio_24", "rfbi_data6", "dispc2_data6", + "hw_dbg13", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU14, 25, "dpm_emu14", "sys_drm_msecure", + "uart1_rx", "gpio_25", "rfbi_data5", "dispc2_data5", + "hw_dbg14", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU15, 26, "dpm_emu15", "sys_secure_indicator", + NULL, "gpio_26", "rfbi_data4", "dispc2_data4", + "hw_dbg15", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU16, 27, "dpm_emu16", "dmtimer8_pwm_evt", + "dsi1_te0", "gpio_27", "rfbi_data3", "dispc2_data3", + "hw_dbg16", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU17, 28, "dpm_emu17", "dmtimer9_pwm_evt", + "dsi1_te1", "gpio_28", "rfbi_data2", "dispc2_data2", + "hw_dbg17", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU18, 190, "dpm_emu18", "dmtimer10_pwm_evt", + "dsi2_te0", "gpio_190", "rfbi_data1", "dispc2_data1", + "hw_dbg18", "safe_mode"), + _OMAP4_MUXENTRY(DPM_EMU19, 191, "dpm_emu19", "dmtimer11_pwm_evt", + "dsi2_te1", "gpio_191", "rfbi_data0", "dispc2_data0", + "hw_dbg19", "safe_mode"), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBS package + * 547-pin CBL ES2.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBS) +struct omap_ball __initdata omap4_core_cbs_ball[] = { + _OMAP4_BALLENTRY(GPMC_AD0, "c12", NULL), + _OMAP4_BALLENTRY(GPMC_AD1, "d12", NULL), + _OMAP4_BALLENTRY(GPMC_AD2, "c13", NULL), + _OMAP4_BALLENTRY(GPMC_AD3, "d13", NULL), + _OMAP4_BALLENTRY(GPMC_AD4, "c15", NULL), + _OMAP4_BALLENTRY(GPMC_AD5, "d15", NULL), + _OMAP4_BALLENTRY(GPMC_AD6, "a16", NULL), + _OMAP4_BALLENTRY(GPMC_AD7, "b16", NULL), + _OMAP4_BALLENTRY(GPMC_AD8, "c16", NULL), + _OMAP4_BALLENTRY(GPMC_AD9, "d16", NULL), + _OMAP4_BALLENTRY(GPMC_AD10, "c17", NULL), + _OMAP4_BALLENTRY(GPMC_AD11, "d17", NULL), + _OMAP4_BALLENTRY(GPMC_AD12, "c18", NULL), + _OMAP4_BALLENTRY(GPMC_AD13, "d18", NULL), + _OMAP4_BALLENTRY(GPMC_AD14, "c19", NULL), + _OMAP4_BALLENTRY(GPMC_AD15, "d19", NULL), + _OMAP4_BALLENTRY(GPMC_A16, "b17", NULL), + _OMAP4_BALLENTRY(GPMC_A17, "a18", NULL), + _OMAP4_BALLENTRY(GPMC_A18, "b18", NULL), + _OMAP4_BALLENTRY(GPMC_A19, "a19", NULL), + _OMAP4_BALLENTRY(GPMC_A20, "b19", NULL), + _OMAP4_BALLENTRY(GPMC_A21, "b20", NULL), + _OMAP4_BALLENTRY(GPMC_A22, "a21", NULL), + _OMAP4_BALLENTRY(GPMC_A23, "b21", NULL), + _OMAP4_BALLENTRY(GPMC_A24, "c20", NULL), + _OMAP4_BALLENTRY(GPMC_A25, "d20", NULL), + _OMAP4_BALLENTRY(GPMC_NCS0, "b25", NULL), + _OMAP4_BALLENTRY(GPMC_NCS1, "c21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS2, "d21", NULL), + _OMAP4_BALLENTRY(GPMC_NCS3, "c22", NULL), + _OMAP4_BALLENTRY(GPMC_NWP, "c25", NULL), + _OMAP4_BALLENTRY(GPMC_CLK, "b22", NULL), + _OMAP4_BALLENTRY(GPMC_NADV_ALE, "d25", NULL), + _OMAP4_BALLENTRY(GPMC_NOE, "b11", NULL), + _OMAP4_BALLENTRY(GPMC_NWE, "b12", NULL), + _OMAP4_BALLENTRY(GPMC_NBE0_CLE, "c23", NULL), + _OMAP4_BALLENTRY(GPMC_NBE1, "d22", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT0, "b26", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT1, "b23", NULL), + _OMAP4_BALLENTRY(GPMC_WAIT2, "d23", NULL), + _OMAP4_BALLENTRY(GPMC_NCS4, "a24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS5, "b24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS6, "c24", NULL), + _OMAP4_BALLENTRY(GPMC_NCS7, "d24", NULL), + _OMAP4_BALLENTRY(HDMI_HPD, "b9", NULL), + _OMAP4_BALLENTRY(HDMI_CEC, "b10", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SCL, "a8", NULL), + _OMAP4_BALLENTRY(HDMI_DDC_SDA, "b8", NULL), + _OMAP4_BALLENTRY(CSI21_DX0, "r26", NULL), + _OMAP4_BALLENTRY(CSI21_DY0, "r25", NULL), + _OMAP4_BALLENTRY(CSI21_DX1, "t26", NULL), + _OMAP4_BALLENTRY(CSI21_DY1, "t25", NULL), + _OMAP4_BALLENTRY(CSI21_DX2, "u26", NULL), + _OMAP4_BALLENTRY(CSI21_DY2, "u25", NULL), + _OMAP4_BALLENTRY(CSI21_DX3, "v26", NULL), + _OMAP4_BALLENTRY(CSI21_DY3, "v25", NULL), + _OMAP4_BALLENTRY(CSI21_DX4, "w26", NULL), + _OMAP4_BALLENTRY(CSI21_DY4, "w25", NULL), + _OMAP4_BALLENTRY(CSI22_DX0, "m26", NULL), + _OMAP4_BALLENTRY(CSI22_DY0, "m25", NULL), + _OMAP4_BALLENTRY(CSI22_DX1, "n26", NULL), + _OMAP4_BALLENTRY(CSI22_DY1, "n25", NULL), + _OMAP4_BALLENTRY(CAM_SHUTTER, "t27", NULL), + _OMAP4_BALLENTRY(CAM_STROBE, "u27", NULL), + _OMAP4_BALLENTRY(CAM_GLOBALRESET, "v27", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_CLK, "ae18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_STP, "ag19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DIR, "af19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_NXT, "ae19", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT0, "af18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT1, "ag18", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT2, "ae17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT3, "af17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT4, "ah17", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT5, "ae16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT6, "af16", NULL), + _OMAP4_BALLENTRY(USBB1_ULPITLL_DAT7, "ag16", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_DATA, "af14", NULL), + _OMAP4_BALLENTRY(USBB1_HSIC_STROBE, "ae14", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DP, "h2", NULL), + _OMAP4_BALLENTRY(USBC1_ICUSB_DM, "h3", NULL), + _OMAP4_BALLENTRY(SDMMC1_CLK, "d2", NULL), + _OMAP4_BALLENTRY(SDMMC1_CMD, "e3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT0, "e4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT1, "e2", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT2, "e1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT3, "f4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT4, "f3", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT5, "f1", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT6, "g4", NULL), + _OMAP4_BALLENTRY(SDMMC1_DAT7, "g3", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_CLKX, "ad27", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DR, "ad26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_DX, "ad25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP2_FSX, "ac28", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_CLKX, "ac26", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DR, "ac25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_DX, "ab25", NULL), + _OMAP4_BALLENTRY(ABE_MCBSP1_FSX, "ac27", NULL), + _OMAP4_BALLENTRY(ABE_PDM_UL_DATA, "ag25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_DL_DATA, "af25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_FRAME, "ae25", NULL), + _OMAP4_BALLENTRY(ABE_PDM_LB_CLK, "af26", NULL), + _OMAP4_BALLENTRY(ABE_CLKS, "ah26", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_CLK1, "ae24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN1, "af24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN2, "ag24", NULL), + _OMAP4_BALLENTRY(ABE_DMIC_DIN3, "ah24", NULL), + _OMAP4_BALLENTRY(UART2_CTS, "ab26", NULL), + _OMAP4_BALLENTRY(UART2_RTS, "ab27", NULL), + _OMAP4_BALLENTRY(UART2_RX, "aa25", NULL), + _OMAP4_BALLENTRY(UART2_TX, "aa26", NULL), + _OMAP4_BALLENTRY(HDQ_SIO, "aa27", NULL), + _OMAP4_BALLENTRY(I2C1_SCL, "ae28", NULL), + _OMAP4_BALLENTRY(I2C1_SDA, "ae26", NULL), + _OMAP4_BALLENTRY(I2C2_SCL, "c26", NULL), + _OMAP4_BALLENTRY(I2C2_SDA, "d26", NULL), + _OMAP4_BALLENTRY(I2C3_SCL, "w27", NULL), + _OMAP4_BALLENTRY(I2C3_SDA, "y27", NULL), + _OMAP4_BALLENTRY(I2C4_SCL, "ag21", NULL), + _OMAP4_BALLENTRY(I2C4_SDA, "ah22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CLK, "af22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SOMI, "ae22", NULL), + _OMAP4_BALLENTRY(MCSPI1_SIMO, "ag22", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS0, "ae23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS1, "af23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS2, "ag23", NULL), + _OMAP4_BALLENTRY(MCSPI1_CS3, "ah23", NULL), + _OMAP4_BALLENTRY(UART3_CTS_RCTX, "f27", NULL), + _OMAP4_BALLENTRY(UART3_RTS_SD, "f28", NULL), + _OMAP4_BALLENTRY(UART3_RX_IRRX, "g27", NULL), + _OMAP4_BALLENTRY(UART3_TX_IRTX, "g28", NULL), + _OMAP4_BALLENTRY(SDMMC5_CLK, "ae5", NULL), + _OMAP4_BALLENTRY(SDMMC5_CMD, "af5", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT0, "ae4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT1, "af4", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT2, "ag3", NULL), + _OMAP4_BALLENTRY(SDMMC5_DAT3, "af3", NULL), + _OMAP4_BALLENTRY(MCSPI4_CLK, "ae21", NULL), + _OMAP4_BALLENTRY(MCSPI4_SIMO, "af20", NULL), + _OMAP4_BALLENTRY(MCSPI4_SOMI, "af21", NULL), + _OMAP4_BALLENTRY(MCSPI4_CS0, "ae20", NULL), + _OMAP4_BALLENTRY(UART4_RX, "ag20", NULL), + _OMAP4_BALLENTRY(UART4_TX, "ah19", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_CLK, "ag12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_STP, "af12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DIR, "ae12", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_NXT, "ag13", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT0, "ae11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT1, "af11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT2, "ag11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT3, "ah11", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT4, "ae10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT5, "af10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT6, "ag10", NULL), + _OMAP4_BALLENTRY(USBB2_ULPITLL_DAT7, "ae9", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_DATA, "af13", NULL), + _OMAP4_BALLENTRY(USBB2_HSIC_STROBE, "ae13", NULL), + _OMAP4_BALLENTRY(KPD_COL3, "g26", NULL), + _OMAP4_BALLENTRY(KPD_COL4, "g25", NULL), + _OMAP4_BALLENTRY(KPD_COL5, "h26", NULL), + _OMAP4_BALLENTRY(KPD_COL0, "h25", NULL), + _OMAP4_BALLENTRY(KPD_COL1, "j27", NULL), + _OMAP4_BALLENTRY(KPD_COL2, "h27", NULL), + _OMAP4_BALLENTRY(KPD_ROW3, "j26", NULL), + _OMAP4_BALLENTRY(KPD_ROW4, "j25", NULL), + _OMAP4_BALLENTRY(KPD_ROW5, "k26", NULL), + _OMAP4_BALLENTRY(KPD_ROW0, "k25", NULL), + _OMAP4_BALLENTRY(KPD_ROW1, "l27", NULL), + _OMAP4_BALLENTRY(KPD_ROW2, "k27", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_CE, "c3", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DP, "b5", NULL), + _OMAP4_BALLENTRY(USBA0_OTG_DM, "b4", NULL), + _OMAP4_BALLENTRY(FREF_CLK1_OUT, "aa28", NULL), + _OMAP4_BALLENTRY(FREF_CLK2_OUT, "y28", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ1, "ae6", NULL), + _OMAP4_BALLENTRY(SYS_NIRQ2, "af6", NULL), + _OMAP4_BALLENTRY(SYS_BOOT0, "f26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT1, "e27", NULL), + _OMAP4_BALLENTRY(SYS_BOOT2, "e26", NULL), + _OMAP4_BALLENTRY(SYS_BOOT3, "e25", NULL), + _OMAP4_BALLENTRY(SYS_BOOT4, "d28", NULL), + _OMAP4_BALLENTRY(SYS_BOOT5, "d27", NULL), + _OMAP4_BALLENTRY(DPM_EMU0, "m2", NULL), + _OMAP4_BALLENTRY(DPM_EMU1, "n2", NULL), + _OMAP4_BALLENTRY(DPM_EMU2, "p2", NULL), + _OMAP4_BALLENTRY(DPM_EMU3, "v1", NULL), + _OMAP4_BALLENTRY(DPM_EMU4, "v2", NULL), + _OMAP4_BALLENTRY(DPM_EMU5, "w1", NULL), + _OMAP4_BALLENTRY(DPM_EMU6, "w2", NULL), + _OMAP4_BALLENTRY(DPM_EMU7, "w3", NULL), + _OMAP4_BALLENTRY(DPM_EMU8, "w4", NULL), + _OMAP4_BALLENTRY(DPM_EMU9, "y2", NULL), + _OMAP4_BALLENTRY(DPM_EMU10, "y3", NULL), + _OMAP4_BALLENTRY(DPM_EMU11, "y4", NULL), + _OMAP4_BALLENTRY(DPM_EMU12, "aa1", NULL), + _OMAP4_BALLENTRY(DPM_EMU13, "aa2", NULL), + _OMAP4_BALLENTRY(DPM_EMU14, "aa3", NULL), + _OMAP4_BALLENTRY(DPM_EMU15, "aa4", NULL), + _OMAP4_BALLENTRY(DPM_EMU16, "ab2", NULL), + _OMAP4_BALLENTRY(DPM_EMU17, "ab3", NULL), + _OMAP4_BALLENTRY(DPM_EMU18, "ab4", NULL), + _OMAP4_BALLENTRY(DPM_EMU19, "ac4", NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define omap4_core_cbs_ball NULL +#endif + +/* + * Superset of all mux modes for omap4 + */ +static struct omap_mux __initdata omap4_wkup_muxmodes[] = { + _OMAP4_MUXENTRY(SIM_IO, 0, "sim_io", NULL, NULL, "gpio_wk0", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CLK, 1, "sim_clk", NULL, NULL, "gpio_wk1", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_RESET, 2, "sim_reset", NULL, NULL, "gpio_wk2", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_CD, 3, "sim_cd", NULL, NULL, "gpio_wk3", NULL, + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SIM_PWRCTRL, 4, "sim_pwrctrl", NULL, NULL, "gpio_wk4", + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(SR_SCL, 0, "sr_scl", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SR_SDA, 0, "sr_sda", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(FREF_XTAL_IN, 0, "fref_xtal_in", NULL, NULL, NULL, + "c2c_wakereqin", NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_SLICER_IN, 0, "fref_slicer_in", NULL, NULL, + "gpi_wk5", "c2c_wakereqin", NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK_IOREQ, 0, "fref_clk_ioreq", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK0_OUT, 6, "fref_clk0_out", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk6", NULL, NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_REQ, 30, "fref_clk3_req", "fref_clk1_req", + "sys_drm_msecure", "gpio_wk30", "c2c_wakereqin", NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK3_OUT, 31, "fref_clk3_out", "fref_clk2_req", + "sys_secure_indicator", "gpio_wk31", "c2c_wakereqout", + NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(FREF_CLK4_REQ, 7, "fref_clk4_req", "fref_clk5_out", + NULL, "gpio_wk7", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(FREF_CLK4_OUT, 8, "fref_clk4_out", NULL, NULL, + "gpio_wk8", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_32K, 0, "sys_32k", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESPWRON, 0, "sys_nrespwron", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_NRESWARM, 0, "sys_nreswarm", NULL, NULL, NULL, + NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWR_REQ, 0, "sys_pwr_req", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_PWRON_RESET_OUT, 29, "sys_pwron_reset_out", NULL, + NULL, "gpio_wk29", NULL, NULL, NULL, NULL), + _OMAP4_MUXENTRY(SYS_BOOT6, 9, "sys_boot6", "dpm_emu18", NULL, + "gpio_wk9", "c2c_wakereqout", NULL, NULL, + "safe_mode"), + _OMAP4_MUXENTRY(SYS_BOOT7, 10, "sys_boot7", "dpm_emu19", NULL, + "gpio_wk10", NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_NTRST, 0, "jtag_ntrst", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TCK, 0, "jtag_tck", NULL, NULL, NULL, NULL, NULL, + NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_RTCK, 0, "jtag_rtck", NULL, NULL, NULL, NULL, + NULL, NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TMS_TMSC, 0, "jtag_tms_tmsc", NULL, NULL, NULL, + NULL, NULL, NULL, "safe_mode"), + _OMAP4_MUXENTRY(JTAG_TDI, 0, "jtag_tdi", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + _OMAP4_MUXENTRY(JTAG_TDO, 0, "jtag_tdo", NULL, NULL, NULL, NULL, NULL, + NULL, NULL), + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; + +/* + * Balls for 44XX CBL & CBS package - wakeup partition + * 547-pin CBL ES1.0 S-FPGA-N547, 0.40mm Ball Pitch (Top), + * 0.40mm Ball Pitch (Bottom) + */ +#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_DEBUG_FS) \ + && defined(CONFIG_OMAP_PACKAGE_CBL) +struct omap_ball __initdata omap4_wkup_cbl_cbs_ball[] = { + _OMAP4_BALLENTRY(SIM_IO, "h4", NULL), + _OMAP4_BALLENTRY(SIM_CLK, "j2", NULL), + _OMAP4_BALLENTRY(SIM_RESET, "g2", NULL), + _OMAP4_BALLENTRY(SIM_CD, "j1", NULL), + _OMAP4_BALLENTRY(SIM_PWRCTRL, "k1", NULL), + _OMAP4_BALLENTRY(SR_SCL, "ag9", NULL), + _OMAP4_BALLENTRY(SR_SDA, "af9", NULL), + _OMAP4_BALLENTRY(FREF_XTAL_IN, "ah6", NULL), + _OMAP4_BALLENTRY(FREF_SLICER_IN, "ag8", NULL), + _OMAP4_BALLENTRY(FREF_CLK_IOREQ, "ad1", NULL), _OMAP4_BALLENTRY(FREF_CLK0_OUT, "ad2", NULL), _OMAP4_BALLENTRY(FREF_CLK3_REQ, "ad3", NULL), _OMAP4_BALLENTRY(FREF_CLK3_OUT, "ad4", NULL), @@ -860,19 +1578,26 @@ struct omap_ball __initdata omap4_wkup_cbl_ball[] = { { .reg_offset = OMAP_MUX_TERMINATOR }, }; #else -#define omap4_wkup_cbl_ball NULL +#define omap4_wkup_cbl_cbs_ball NULL #endif - int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) { - struct omap_ball *package_balls_core, *package_balls_wkup; + struct omap_ball *package_balls_core; + struct omap_ball *package_balls_wkup = omap4_wkup_cbl_cbs_ball; + struct omap_mux *core_muxmodes; int ret; switch (flags & OMAP_PACKAGE_MASK) { case OMAP_PACKAGE_CBL: + pr_debug("mux: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n"); package_balls_core = omap4_core_cbl_ball; - package_balls_wkup = omap4_wkup_cbl_ball; + core_muxmodes = omap4_core_muxmodes; + break; + case OMAP_PACKAGE_CBS: + pr_debug("mux: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n"); + package_balls_core = omap4_core_cbs_ball; + core_muxmodes = omap4_es2_core_muxmodes; break; default: pr_err("mux: Unknown omap package, mux disabled\n"); @@ -883,7 +1608,7 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) OMAP_MUX_GPIO_IN_MODE3, OMAP4_CTRL_MODULE_PAD_CORE_MUX_PBASE, OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE, - omap4_core_muxmodes, NULL, board_subset, + core_muxmodes, NULL, board_subset, package_balls_core); if (ret) return ret; diff --git a/arch/arm/mach-omap2/mux44xx.h b/arch/arm/mach-omap2/mux44xx.h index ea8b235d1487..c635026cd7e9 100644 --- a/arch/arm/mach-omap2/mux44xx.h +++ b/arch/arm/mach-omap2/mux44xx.h @@ -233,6 +233,27 @@ #define OMAP4_CTRL_MODULE_PAD_DPM_EMU18_OFFSET 0x01d2 #define OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET 0x01d4 +/* ES2.0 only */ +#define OMAP4_CTRL_MODULE_PAD_GPMC_WAIT2_OFFSET 0x008e +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS4_OFFSET 0x0090 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS5_OFFSET 0x0092 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS6_OFFSET 0x0094 +#define OMAP4_CTRL_MODULE_PAD_GPMC_NCS7_OFFSET 0x0096 + +#define OMAP4_CTRL_MODULE_PAD_KPD_COL3_OFFSET 0x017c +#define OMAP4_CTRL_MODULE_PAD_KPD_COL4_OFFSET 0x017e +#define OMAP4_CTRL_MODULE_PAD_KPD_COL5_OFFSET 0x0180 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL0_OFFSET 0x0182 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL1_OFFSET 0x0184 +#define OMAP4_CTRL_MODULE_PAD_KPD_COL2_OFFSET 0x0186 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW3_OFFSET 0x0188 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW4_OFFSET 0x018a +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW5_OFFSET 0x018c +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW0_OFFSET 0x018e +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW1_OFFSET 0x0190 +#define OMAP4_CTRL_MODULE_PAD_KPD_ROW2_OFFSET 0x0192 + + #define OMAP4_CTRL_MODULE_PAD_CORE_MUX_SIZE \ (OMAP4_CTRL_MODULE_PAD_DPM_EMU19_OFFSET \ - OMAP4_CTRL_MODULE_PAD_GPMC_AD0_OFFSET + 2) -- cgit v1.2.3 From 6fea7b0a7ad9b79aca09df4c42773927db6934ed Mon Sep 17 00:00:00 2001 From: Benoit Cousson Date: Mon, 27 Sep 2010 10:50:33 +0200 Subject: OMAP4: sdp4430: Select CBS package for ES2 Select the CBS package if SDP4430 is enabled during config. Use the proper package (CBL or CBS) based on chip revision. Signed-off-by: Benoit Cousson Cc: Tony Lindgren Cc: Paul Walmsley Cc: Santosh Shilimkar Cc: Anand Gadiyar --- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/board-4430sdp.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 92fea6395d58..39229cf72c4b 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -284,6 +284,7 @@ config MACH_OMAP_4430SDP default y depends on ARCH_OMAP4 select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c index e4f1726e6669..94d989bee8ad 100644 --- a/arch/arm/mach-omap2/board-4430sdp.c +++ b/arch/arm/mach-omap2/board-4430sdp.c @@ -517,8 +517,12 @@ static struct omap_board_mux board_mux[] __initdata = { static void __init omap_4430sdp_init(void) { int status; + int package = OMAP_PACKAGE_CBS; + + if (omap_rev() == OMAP4430_REV_ES1_0) + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); - omap4_mux_init(board_mux, OMAP_PACKAGE_CBL); omap4_i2c_init(); omap_sfh7741prox_init(); platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices)); -- cgit v1.2.3 From fc63de829bbfa3945ffd6327bd3dc88f4e643642 Mon Sep 17 00:00:00 2001 From: sricharan Date: Mon, 8 Nov 2010 19:26:11 +0530 Subject: OMAP4: pandaboard: Select CBL & CBS package and initialize mux The mux framework allows the change of pad configuration by drivers when needed. Prior to this the mux framework has to be initialised with all the mux parameters specific to the board. The mux init is already present in the board file for SDP. Adding the mux init for panda boards. Signed-off-by: sricharan Acked-by: Anand Gadiyar Signed-off-by: Benoit Cousson Cc: Santosh Shilimkar --- arch/arm/mach-omap2/Kconfig | 2 ++ arch/arm/mach-omap2/board-omap4panda.c | 16 ++++++++++++++++ 2 files changed, 18 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 39229cf72c4b..186d270344e8 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -290,6 +290,8 @@ config MACH_OMAP4_PANDA bool "OMAP4 Panda Board" default y depends on ARCH_OMAP4 + select OMAP_PACKAGE_CBL + select OMAP_PACKAGE_CBS config OMAP3_EMU bool "OMAP3 debugging peripherals" diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c index 1ecd0a6cefb7..801f8146b00c 100644 --- a/arch/arm/mach-omap2/board-omap4panda.c +++ b/arch/arm/mach-omap2/board-omap4panda.c @@ -40,6 +40,7 @@ #include "hsmmc.h" #include "control.h" +#include "mux.h" #define GPIO_HUB_POWER 1 #define GPIO_HUB_NRESET 62 @@ -368,8 +369,23 @@ static int __init omap4_panda_i2c_init(void) omap_register_i2c_bus(4, 400, NULL, 0); return 0; } + +#ifdef CONFIG_OMAP_MUX +static struct omap_board_mux board_mux[] __initdata = { + { .reg_offset = OMAP_MUX_TERMINATOR }, +}; +#else +#define board_mux NULL +#endif + static void __init omap4_panda_init(void) { + int package = OMAP_PACKAGE_CBS; + + if (omap_rev() == OMAP4430_REV_ES1_0) + package = OMAP_PACKAGE_CBL; + omap4_mux_init(board_mux, package); + omap4_panda_i2c_init(); platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices)); omap_serial_init(); -- cgit v1.2.3 From 032a6424aeea7333a8dafc8cc05dd10b09c62680 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Mon, 15 Nov 2010 09:50:50 -0600 Subject: OMAP: mux: Add __func__ macro to pr_xxx macros Removed mux: and added the __func__ macro to make debugging easier. Signed-off-by: Dan Murphy Signed-off-by: Benoit Cousson Cc: Tony Lindgren --- arch/arm/mach-omap2/mux.c | 30 +++++++++++++++--------------- arch/arm/mach-omap2/mux2420.c | 3 ++- arch/arm/mach-omap2/mux2430.c | 3 ++- arch/arm/mach-omap2/mux34xx.c | 2 +- arch/arm/mach-omap2/mux44xx.c | 6 +++--- 5 files changed, 23 insertions(+), 21 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c index 92215703b671..3d71d93caab2 100644 --- a/arch/arm/mach-omap2/mux.c +++ b/arch/arm/mach-omap2/mux.c @@ -114,12 +114,12 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, } if (found == 0) { - pr_err("mux: Could not set gpio%i\n", gpio); + pr_err("%s: Could not set gpio%i\n", __func__, gpio); return -ENODEV; } if (found > 1) { - pr_info("mux: Multiple gpio paths (%d) for gpio%i\n", + pr_info("%s: Multiple gpio paths (%d) for gpio%i\n", __func__, found, gpio); return -EINVAL; } @@ -130,7 +130,7 @@ static int __init _omap_mux_init_gpio(struct omap_mux_partition *partition, mux_mode |= OMAP_MUX_MODE3; else mux_mode |= OMAP_MUX_MODE4; - pr_debug("mux: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", + pr_debug("%s: Setting signal %s.gpio%i 0x%04x -> 0x%04x\n", __func__, gpio_mux->muxnames[0], gpio, old_mode, mux_mode); omap_mux_write(partition, mux_mode, gpio_mux->reg_offset); @@ -190,8 +190,8 @@ static int __init _omap_mux_init_signal(struct omap_mux_partition *partition, old_mode = omap_mux_read(partition, m->reg_offset); mux_mode = val | i; - pr_debug("mux: Setting signal " - "%s.%s 0x%04x -> 0x%04x\n", + pr_debug("%s: Setting signal " + "%s.%s 0x%04x -> 0x%04x\n", __func__, m0_entry, muxname, old_mode, mux_mode); omap_mux_write(partition, mux_mode, m->reg_offset); @@ -204,12 +204,12 @@ static int __init _omap_mux_init_signal(struct omap_mux_partition *partition, return 0; if (found > 1) { - pr_err("mux: Multiple signal paths (%i) for %s\n", + pr_err("%s: Multiple signal paths (%i) for %s\n", __func__, found, muxname); return -EINVAL; } - pr_err("mux: Could not set signal %s\n", muxname); + pr_err("%s: Could not set signal %s\n", __func__, muxname); return -ENODEV; } @@ -561,7 +561,7 @@ static void __init omap_mux_package_fixup(struct omap_mux *p, s++; } if (!found) - pr_err("mux: Unknown entry offset 0x%x\n", + pr_err("%s: Unknown entry offset 0x%x\n", __func__, p->reg_offset); p++; } @@ -586,7 +586,7 @@ static void __init omap_mux_package_init_balls(struct omap_ball *b, s++; } if (!found) - pr_err("mux: Unknown ball offset 0x%x\n", + pr_err("%s: Unknown ball offset 0x%x\n", __func__, b->reg_offset); b++; } @@ -722,7 +722,7 @@ u16 omap_mux_get_gpio(int gpio) } if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) - pr_err("mux: Could not get gpio%i\n", gpio); + pr_err("%s: Could not get gpio%i\n", __func__, gpio); return OMAP_MUX_TERMINATOR; } @@ -742,7 +742,7 @@ void omap_mux_set_gpio(u16 val, int gpio) } if (!m || m->reg_offset == OMAP_MUX_TERMINATOR) - pr_err("mux: Could not set gpio%i\n", gpio); + pr_err("%s: Could not set gpio%i\n", __func__, gpio); } static struct omap_mux * __init omap_mux_list_add( @@ -800,7 +800,7 @@ static void __init omap_mux_init_list(struct omap_mux_partition *partition, entry = omap_mux_list_add(partition, superset); if (!entry) { - pr_err("mux: Could not add entry\n"); + pr_err("%s: Could not add entry\n", __func__); return; } superset++; @@ -862,8 +862,8 @@ int __init omap_mux_init(const char *name, u32 flags, partition->phys = mux_pbase; partition->base = ioremap(mux_pbase, mux_size); if (!partition->base) { - pr_err("mux: Could not ioremap mux partition at 0x%08x\n", - partition->phys); + pr_err("%s: Could not ioremap mux partition at 0x%08x\n", + __func__, partition->phys); return -ENODEV; } @@ -871,7 +871,7 @@ int __init omap_mux_init(const char *name, u32 flags, list_add_tail(&partition->node, &mux_partitions); mux_partitions_cnt++; - pr_info("MUX: Add partition: #%d: %s, flags: %x\n", + pr_info("%s: Add partition: #%d: %s, flags: %x\n", __func__, mux_partitions_cnt, partition->name, partition->flags); omap_mux_init_package(superset, package_subset, package_balls); diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c index 8231f0ae4856..cf6de0971c6c 100644 --- a/arch/arm/mach-omap2/mux2420.c +++ b/arch/arm/mach-omap2/mux2420.c @@ -678,7 +678,8 @@ int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags) case OMAP_PACKAGE_ZAF: /* REVISIT: Please add data */ default: - pr_warning("mux: No ball data available for omap2420 package\n"); + pr_warning("%s: No ball data available for omap2420 package\n", + __func__); } return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c index cb6b40436e19..4185f92553db 100644 --- a/arch/arm/mach-omap2/mux2430.c +++ b/arch/arm/mach-omap2/mux2430.c @@ -781,7 +781,8 @@ int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags) package_balls = omap2430_pop_ball; break; default: - pr_warning("mux: No ball data available for omap2420 package\n"); + pr_warning("%s: No ball data available for omap2420 package\n", + __func__); } return omap_mux_init("core", OMAP_MUX_REG_8BIT | OMAP_MUX_GPIO_IN_MODE3, diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index 4113c93d3f27..440c98e9a510 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -2049,7 +2049,7 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags) package_balls = omap36xx_cbp_ball; break; default: - printk(KERN_ERR "mux: Unknown omap package, mux disabled\n"); + pr_err("%s Unknown omap package, mux disabled\n", __func__); return -EINVAL; } diff --git a/arch/arm/mach-omap2/mux44xx.c b/arch/arm/mach-omap2/mux44xx.c index 80335f395d28..980f11d45c79 100644 --- a/arch/arm/mach-omap2/mux44xx.c +++ b/arch/arm/mach-omap2/mux44xx.c @@ -1590,17 +1590,17 @@ int __init omap4_mux_init(struct omap_board_mux *board_subset, int flags) switch (flags & OMAP_PACKAGE_MASK) { case OMAP_PACKAGE_CBL: - pr_debug("mux: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n"); + pr_debug("%s: OMAP4430 ES1.0 -> OMAP_PACKAGE_CBL\n", __func__); package_balls_core = omap4_core_cbl_ball; core_muxmodes = omap4_core_muxmodes; break; case OMAP_PACKAGE_CBS: - pr_debug("mux: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n"); + pr_debug("%s: OMAP4430 ES2.X -> OMAP_PACKAGE_CBS\n", __func__); package_balls_core = omap4_core_cbs_ball; core_muxmodes = omap4_es2_core_muxmodes; break; default: - pr_err("mux: Unknown omap package, mux disabled\n"); + pr_err("%s: Unknown omap package, mux disabled\n", __func__); return -EINVAL; } -- cgit v1.2.3 From f910043ce00791c06afc3789278447c4e88670ea Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 24 Nov 2010 11:09:03 -0800 Subject: OMAP: UART: don't resume UARTs that are not enabled. Add additional check to omap_uart_resume_idle() so that only enabled (specifically, idle-enabled) UARTs are allowed to resume. This matches the existing check in prepare idle. Without this patch, the system will hang if a board is configured to register only some uarts instead of all of them and PM is enabled. Cc: Govindraj R. Signed-off-by: Kevin Hilman [tony@atomide.com: updated description] Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/serial.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index becf0e38ef7e..bc934dbe3bf0 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -406,7 +406,7 @@ void omap_uart_resume_idle(int num) struct omap_uart_state *uart; list_for_each_entry(uart, &uart_list, node) { - if (num == uart->num) { + if (num == uart->num && uart->can_sleep) { omap_uart_enable_clocks(uart); /* Check for IO pad wakeup */ -- cgit v1.2.3 From 0d8e2d0dad98a693bad88aea6876ac8b94ad95c6 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Wed, 24 Nov 2010 16:49:05 -0700 Subject: OMAP2+: PM/serial: hold console semaphore while OMAP UARTs are disabled The console semaphore must be held while the OMAP UART devices are disabled, lest a console write cause an ARM abort (and a kernel crash) when the underlying console device is inaccessible. These crashes only occur when the console is on one of the OMAP internal serial ports. While this problem has been latent in the PM idle loop for some time, the crash was not triggerable with an unmodified kernel until commit 6f251e9db1093c187addc309b5f2f7fe3efd2995 ("OMAP: UART: omap_device conversions, remove implicit 8520 assumptions"). After this patch, a console write often occurs after the console UART has been disabled in the idle loop, crashing the system. Several users have encountered this bug: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg38396.html http://www.mail-archive.com/linux-omap@vger.kernel.org/msg36602.html The same commit also introduced new code that disabled the UARTs during init, in omap_serial_init_port(). The kernel will also crash in this code when earlyconsole and extra debugging is enabled: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg36411.html The minimal fix for the -rc series is to hold the console semaphore while the OMAP UARTs are disabled. This is a somewhat overbroad fix, since the console may not be located on an OMAP UART, as is the case with the GPMC UART on Zoom3. While it is technically possible to determine which devices the console or earlyconsole is actually running on, it is not a trivial problem to solve, and the code to do so is not really appropriate for the -rc series. The right long-term fix is to ensure that no code outside of the OMAP serial driver can disable an OMAP UART. As I understand it, code to implement this is under development by TI. This patch is a collaboration between Paul Walmsley and Tony Lindgren . Thanks to Ming Lei and Pramod for their feedback on earlier versions of this patch. Signed-off-by: Paul Walmsley Signed-off-by: Tony Lindgren Acked-by: Kevin Hilman Cc: Ming Lei Cc: Pramod Cc: Thomas Petazzoni Cc: Jean Pihet Cc: Govindraj.R --- arch/arm/mach-omap2/pm24xx.c | 7 +++++++ arch/arm/mach-omap2/pm34xx.c | 10 ++++++++++ arch/arm/mach-omap2/serial.c | 5 +++++ 3 files changed, 22 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a40457d81927..c85923e56b85 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -30,6 +30,7 @@ #include #include #include +#include #include #include @@ -118,6 +119,10 @@ static void omap2_enter_full_retention(void) if (omap_irq_pending()) goto no_sleep; + /* Block console output in case it is on one of the OMAP UARTs */ + if (try_acquire_console_sem()) + goto no_sleep; + omap_uart_prepare_idle(0); omap_uart_prepare_idle(1); omap_uart_prepare_idle(2); @@ -131,6 +136,8 @@ static void omap2_enter_full_retention(void) omap_uart_resume_idle(1); omap_uart_resume_idle(0); + release_console_sem(); + no_sleep: if (omap2_pm_debug) { unsigned long long tmp; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 75c0cd13ad8e..0ec8a04b7473 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -385,6 +386,12 @@ void omap_sram_idle(void) omap3_enable_io_chain(); } + /* Block console output in case it is on one of the OMAP UARTs */ + if (per_next_state < PWRDM_POWER_ON || + core_next_state < PWRDM_POWER_ON) + if (try_acquire_console_sem()) + goto console_still_active; + /* PER */ if (per_next_state < PWRDM_POWER_ON) { omap_uart_prepare_idle(2); @@ -463,6 +470,9 @@ void omap_sram_idle(void) omap_uart_resume_idle(3); } + release_console_sem(); + +console_still_active: /* Disable IO-PAD and IO-CHAIN wakeup */ if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index bc934dbe3bf0..d17960a1be25 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -27,6 +27,7 @@ #include #include #include +#include #ifdef CONFIG_SERIAL_OMAP #include @@ -807,6 +808,8 @@ void __init omap_serial_init_port(int port) oh->dev_attr = uart; + acquire_console_sem(); /* in case the earlycon is on the UART */ + /* * Because of early UART probing, UART did not get idled * on init. Now that omap_device is ready, ensure full idle @@ -831,6 +834,8 @@ void __init omap_serial_init_port(int port) omap_uart_block_sleep(uart); uart->timeout = DEFAULT_TIMEOUT; + release_console_sem(); + if ((cpu_is_omap34xx() && uart->padconf) || (uart->wk_en && uart->wk_mask)) { device_init_wakeup(&od->pdev.dev, true); -- cgit v1.2.3 From 706afddaf53522b67c81a0b1b38bdccd4d4ff00c Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:46 +0200 Subject: arm: omap1: add missing includes Add missing includes to get rid of the following sparse warnings: arch/arm/mach-omap1/devices.c:225:13: warning: symbol 'omap1_camera_init' was not declared. Should it be static? arch/arm/mach-omap1/flash.c:15:6: warning: symbol 'omap1_set_vpp' was not declared. Should it be static? arch/arm/mach-omap1/serial.c:190:6: warning: symbol 'omap_serial_wake_trigger' was not declared. Should it be static? arch/arm/mach-omap1/time.c:252:18: warning: symbol 'omap_timer' was not declared. Should it be static? Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/devices.c | 1 + arch/arm/mach-omap1/flash.c | 1 + arch/arm/mach-omap1/serial.c | 2 ++ arch/arm/mach-omap1/time.c | 1 + 4 files changed, 5 insertions(+) (limited to 'arch') diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c index e7f9ee63dce5..86ad38a20c3e 100644 --- a/arch/arm/mach-omap1/devices.c +++ b/arch/arm/mach-omap1/devices.c @@ -17,6 +17,7 @@ #include #include +#include #include #include diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c index 0b07a78eeaa7..acd161666408 100644 --- a/arch/arm/mach-omap1/flash.c +++ b/arch/arm/mach-omap1/flash.c @@ -11,6 +11,7 @@ #include #include +#include void omap1_set_vpp(struct map_info *map, int enable) { diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index b78d0749f13d..0845fbbf155e 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -27,6 +27,8 @@ #include #include +#include "pm.h" + static struct clk * uart1_ck; static struct clk * uart2_ck; static struct clk * uart3_ck; diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c index 1be6a214d88d..7f75bc614ec0 100644 --- a/arch/arm/mach-omap1/time.c +++ b/arch/arm/mach-omap1/time.c @@ -52,6 +52,7 @@ #include #include +#include #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE #define OMAP_MPU_TIMER_OFFSET 0x100 -- cgit v1.2.3 From e6f168212243452eae7c0d0c20c2f6e213933fc8 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:47 +0200 Subject: arm: omap1: make some functions static Make some functions static to get rid of the following sparse warnings: arch/arm/mach-omap1/mcbsp.c:177:12: warning: symbol 'omap1_mcbsp_init' was not declared. Should it be static? arch/arm/mach-omap1/mux.c:346:22: warning: symbol 'omap1_cfg_reg' was not declared. Should it be static? arch/arm/plat-omap/dma.c:177:5: warning: symbol 'omap_dma_in_1510_mode' was not declared. Should it be static? arch/arm/plat-omap/sram.c:273:12: warning: symbol 'omap1_sram_init' was not declared. Should it be static? Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mcbsp.c | 2 +- arch/arm/mach-omap1/mux.c | 2 +- arch/arm/plat-omap/dma.c | 2 +- arch/arm/plat-omap/sram.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c index b3a796a6da03..372ea711faee 100644 --- a/arch/arm/mach-omap1/mcbsp.c +++ b/arch/arm/mach-omap1/mcbsp.c @@ -174,7 +174,7 @@ static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = { #define OMAP16XX_MCBSP_REG_NUM 0 #endif -int __init omap1_mcbsp_init(void) +static int __init omap1_mcbsp_init(void) { if (cpu_is_omap7xx()) { omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ; diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c index 7835add00344..5fdef7a34828 100644 --- a/arch/arm/mach-omap1/mux.c +++ b/arch/arm/mach-omap1/mux.c @@ -343,7 +343,7 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0) #define OMAP1XXX_PINS_SZ 0 #endif /* CONFIG_ARCH_OMAP15XX || CONFIG_ARCH_OMAP16XX */ -int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) +static int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) { static DEFINE_SPINLOCK(mux_spin_lock); unsigned long flags; diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c index 2c2826571d45..a863f5546a6b 100644 --- a/arch/arm/plat-omap/dma.c +++ b/arch/arm/plat-omap/dma.c @@ -174,7 +174,7 @@ static inline void omap_enable_channel_irq(int lch); #ifdef CONFIG_ARCH_OMAP15XX /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ -int omap_dma_in_1510_mode(void) +static int omap_dma_in_1510_mode(void) { return enable_1510_mode; } diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index e2c8eebe6b3a..93641df487a1 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -270,7 +270,7 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl) _omap_sram_reprogram_clock(dpllctl, ckctl); } -int __init omap1_sram_init(void) +static int __init omap1_sram_init(void) { _omap_sram_reprogram_clock = omap_sram_push(omap1_sram_reprogram_clock, -- cgit v1.2.3 From dba5e190fcbe2a76b1a867ec6cbe9d7009e43708 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:48 +0200 Subject: arm: omap1: mbox: make variables static Make some variables static to get rid of the following warnings: arch/arm/mach-omap1/mailbox.c:136:18: warning: symbol 'mbox_dsp_info' was not declared. Should it be static? arch/arm/mach-omap1/mailbox.c:142:18: warning: symbol 'omap1_mboxes' was not declared. Should it be static? Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mailbox.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 1a85a421007f..12d68801450f 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -133,13 +133,13 @@ static struct omap_mbox1_priv omap1_mbox_dsp_priv = { }, }; -struct omap_mbox mbox_dsp_info = { +static struct omap_mbox mbox_dsp_info = { .name = "dsp", .ops = &omap1_mbox_ops, .priv = &omap1_mbox_dsp_priv, }; -struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; +static struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL }; static int __devinit omap1_mbox_probe(struct platform_device *pdev) { -- cgit v1.2.3 From 87aedfe25a754a3ab49a7cfdb8f81bc882bc34fa Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:49 +0200 Subject: arm: omap1: mbox: delete unused variable Delete unused variable from probe(). Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/mailbox.c | 1 - 1 file changed, 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c index 12d68801450f..c0e1f48aa119 100644 --- a/arch/arm/mach-omap1/mailbox.c +++ b/arch/arm/mach-omap1/mailbox.c @@ -145,7 +145,6 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev) { struct resource *mem; int ret; - int i; struct omap_mbox **list; list = omap1_mboxes; -- cgit v1.2.3 From 7489ffcea62e0b990d3557746d19a47e83e07042 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:50 +0200 Subject: arm: omap1: board-ams-delta: fix cast Use IOMEM() macro to get rid of the following sparse warning: arch/arm/mach-omap1/board-ams-delta.c:319:36: warning: incorrect type in initializer (different address spaces) arch/arm/mach-omap1/board-ams-delta.c:319:36: expected void [noderef] *membase arch/arm/mach-omap1/board-ams-delta.c:319:36: got void * Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/board-ams-delta.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c index 1d4163b9f0b7..1948cd3ee500 100644 --- a/arch/arm/mach-omap1/board-ams-delta.c +++ b/arch/arm/mach-omap1/board-ams-delta.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -316,7 +317,7 @@ static void __init ams_delta_init(void) static struct plat_serial8250_port ams_delta_modem_ports[] = { { - .membase = (void *) AMS_DELTA_MODEM_VIRT, + .membase = IOMEM(AMS_DELTA_MODEM_VIRT), .mapbase = AMS_DELTA_MODEM_PHYS, .irq = -EINVAL, /* changed later */ .flags = UPF_BOOT_AUTOCONF, -- cgit v1.2.3 From 2862945bf5262d516583477ce420a2f122306f43 Mon Sep 17 00:00:00 2001 From: Aaro Koskinen Date: Thu, 18 Nov 2010 19:59:51 +0200 Subject: arm: omap2: timer-gp: delete unused variable Delete a redundant local variable. Signed-off-by: Aaro Koskinen Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/timer-gp.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c index e13c29eecf2b..f9052e1c6936 100644 --- a/arch/arm/mach-omap2/timer-gp.c +++ b/arch/arm/mach-omap2/timer-gp.c @@ -203,7 +203,7 @@ static struct clocksource clocksource_gpt = { static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; - u32 tick_rate, tick_period; + u32 tick_rate; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR @@ -216,7 +216,6 @@ static void __init omap2_gp_clocksource_init(void) omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); - tick_period = (tick_rate / HZ) - 1; omap_dm_timer_set_load_start(gpt, 1, 0); -- cgit v1.2.3 From 3f90c2f0d671a2bbde4b304d2b6b4347682499d2 Mon Sep 17 00:00:00 2001 From: Andrei Emeltchenko Date: Fri, 12 Nov 2010 15:29:17 +0200 Subject: OMAP: Serial: Define OMAP uart MDR1 reg and remove magic numbers Define MDR1 register serial definitions used in serial and bluetooth drivers. Change magic number to ones defined in serial_reg for omap1/2 serial driver. Remove redefined MDR1 register definitions in omap-serial driver. Signed-off-by: Andrei Emeltchenko Acked-by: G, Manjunath Kondaiah Acked-by: Govindraj.R Acked-by: Greg Kroah-Hartman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap1/serial.c | 6 ++++-- arch/arm/mach-omap2/serial.c | 15 +++++++++------ arch/arm/plat-omap/include/plat/omap-serial.h | 3 --- drivers/serial/omap-serial.c | 6 +++--- include/linux/serial_reg.h | 12 ++++++++++++ 5 files changed, 28 insertions(+), 14 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap1/serial.c b/arch/arm/mach-omap1/serial.c index b78d0749f13d..c73d1b77b364 100644 --- a/arch/arm/mach-omap1/serial.c +++ b/arch/arm/mach-omap1/serial.c @@ -52,9 +52,11 @@ static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset, */ static void __init omap_serial_reset(struct plat_serial8250_port *p) { - omap_serial_outp(p, UART_OMAP_MDR1, 0x07); /* disable UART */ + omap_serial_outp(p, UART_OMAP_MDR1, + UART_OMAP_MDR1_DISABLE); /* disable UART */ omap_serial_outp(p, UART_OMAP_SCR, 0x08); /* TX watermark */ - omap_serial_outp(p, UART_OMAP_MDR1, 0x00); /* enable UART */ + omap_serial_outp(p, UART_OMAP_MDR1, + UART_OMAP_MDR1_16X_MODE); /* enable UART */ if (!cpu_is_omap15xx()) { omap_serial_outp(p, UART_OMAP_SYSC, 0x01); diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index becf0e38ef7e..edd7c99de38d 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -168,9 +168,9 @@ static inline void serial_write_reg(struct omap_uart_state *uart, int offset, static inline void __init omap_uart_reset(struct omap_uart_state *uart) { - serial_write_reg(uart, UART_OMAP_MDR1, 0x07); + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); serial_write_reg(uart, UART_OMAP_SCR, 0x08); - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); } #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) @@ -246,9 +246,10 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) uart->context_valid = 0; if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, 0x07, 0xA0); + omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_DISABLE, 0xA0); else - serial_write_reg(uart, UART_OMAP_MDR1, 0x7); + serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); + serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ efr = serial_read_reg(uart, UART_EFR); serial_write_reg(uart, UART_EFR, UART_EFR_ECB); @@ -267,11 +268,13 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) serial_write_reg(uart, UART_OMAP_SCR, uart->scr); serial_write_reg(uart, UART_OMAP_WER, uart->wer); serial_write_reg(uart, UART_OMAP_SYSC, uart->sysc); + if (uart->errata & UART_ERRATA_i202_MDR1_ACCESS) - omap_uart_mdr1_errataset(uart, 0x00, 0xA1); + omap_uart_mdr1_errataset(uart, UART_OMAP_MDR1_16X_MODE, 0xA1); else /* UART 16x mode */ - serial_write_reg(uart, UART_OMAP_MDR1, 0x00); + serial_write_reg(uart, UART_OMAP_MDR1, + UART_OMAP_MDR1_16X_MODE); } #else static inline void omap_uart_save_context(struct omap_uart_state *uart) {} diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index c8dae02f0704..6a1788014611 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -31,9 +31,6 @@ */ #define OMAP_SERIAL_NAME "ttyO" -#define OMAP_MDR1_DISABLE 0x07 -#define OMAP_MDR1_MODE13X 0x03 -#define OMAP_MDR1_MODE16X 0x00 #define OMAP_MODE13X_SPEED 230400 /* diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c index 14365f72b664..03a96db67de4 100644 --- a/drivers/serial/omap-serial.c +++ b/drivers/serial/omap-serial.c @@ -753,7 +753,7 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, /* Protocol, Baud Rate, and Interrupt Settings */ - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_DISABLE); + serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); up->efr = serial_in(up, UART_EFR); @@ -774,9 +774,9 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, serial_out(up, UART_LCR, cval); if (baud > 230400 && baud != 3000000) - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE13X); + serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_13X_MODE); else - serial_out(up, UART_OMAP_MDR1, OMAP_MDR1_MODE16X); + serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); /* Hardware Flow Control Configuration */ diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index c7a0ce11cd47..6f3823474e6c 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -341,5 +341,17 @@ #define UART_OMAP_SYSS 0x16 /* System status register */ #define UART_OMAP_WER 0x17 /* Wake-up enable register */ +/* + * These are the definitions for the MDR1 register + */ +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ +#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ +#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ +#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ +#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ +#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ + #endif /* _LINUX_SERIAL_REG_H */ -- cgit v1.2.3 From f567e88d41330e5d7bfadb66f307a6065d112e70 Mon Sep 17 00:00:00 2001 From: Andrei Emeltchenko Date: Wed, 17 Nov 2010 08:31:52 +0000 Subject: omap: Serial: Define register access modes in LCR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Access to some registers depends on register access mode Three different modes are available for OMAP (at least) • Operational mode LCR_REG[7] = 0x0 • Configuration mode A LCR_REG[7] = 0x1 and LCR_REG[7:0]! = 0xBF • Configuration mode B LCR_REG[7] = 0x1 and LCR_REG[7:0] = 0xBF Define access modes and remove redefinitions and magic numbers in serial drivers (and later in bluetooth driver). Signed-off-by: Andrei Emeltchenko Acked-by: Govindraj.R Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/serial.c | 12 +++++----- arch/arm/plat-omap/include/plat/omap-serial.h | 9 ------- drivers/serial/8250.c | 26 ++++++++++---------- drivers/serial/omap-serial.c | 34 +++++++++++++-------------- include/linux/serial_reg.h | 7 ++++++ 5 files changed, 43 insertions(+), 45 deletions(-) (limited to 'arch') diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index edd7c99de38d..14c87157d707 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -218,7 +218,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) return; lcr = serial_read_reg(uart, UART_LCR); - serial_write_reg(uart, UART_LCR, 0xBF); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); uart->dll = serial_read_reg(uart, UART_DLL); uart->dlh = serial_read_reg(uart, UART_DLM); serial_write_reg(uart, UART_LCR, lcr); @@ -226,7 +226,7 @@ static void omap_uart_save_context(struct omap_uart_state *uart) uart->sysc = serial_read_reg(uart, UART_OMAP_SYSC); uart->scr = serial_read_reg(uart, UART_OMAP_SCR); uart->wer = serial_read_reg(uart, UART_OMAP_WER); - serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); uart->mcr = serial_read_reg(uart, UART_MCR); serial_write_reg(uart, UART_LCR, lcr); @@ -250,19 +250,19 @@ static void omap_uart_restore_context(struct omap_uart_state *uart) else serial_write_reg(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); efr = serial_read_reg(uart, UART_EFR); serial_write_reg(uart, UART_EFR, UART_EFR_ECB); serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(uart, UART_IER, 0x0); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); serial_write_reg(uart, UART_DLL, uart->dll); serial_write_reg(uart, UART_DLM, uart->dlh); serial_write_reg(uart, UART_LCR, 0x0); /* Operational mode */ serial_write_reg(uart, UART_IER, uart->ier); - serial_write_reg(uart, UART_LCR, 0x80); + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_A); serial_write_reg(uart, UART_MCR, uart->mcr); - serial_write_reg(uart, UART_LCR, 0xBF); /* Config B mode */ + serial_write_reg(uart, UART_LCR, UART_LCR_CONF_MODE_B); serial_write_reg(uart, UART_EFR, efr); serial_write_reg(uart, UART_LCR, UART_LCR_WLEN8); serial_write_reg(uart, UART_OMAP_SCR, uart->scr); diff --git a/arch/arm/plat-omap/include/plat/omap-serial.h b/arch/arm/plat-omap/include/plat/omap-serial.h index 6a1788014611..b3e0bad9b77e 100644 --- a/arch/arm/plat-omap/include/plat/omap-serial.h +++ b/arch/arm/plat-omap/include/plat/omap-serial.h @@ -33,15 +33,6 @@ #define OMAP_MODE13X_SPEED 230400 -/* - * LCR = 0XBF: Switch to Configuration Mode B. - * In configuration mode b allow access - * to EFR,DLL,DLH. - * Reference OMAP TRM Chapter 17 - * Section: 1.4.3 Mode Selection - */ -#define OMAP_UART_LCR_CONF_MDB 0XBF - /* WER = 0x7F * Enable module level wakeup in WER reg */ diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 4d8e14b7aa93..aaf9907e6014 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -653,13 +653,13 @@ static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) { if (p->capabilities & UART_CAP_SLEEP) { if (p->capabilities & UART_CAP_EFR) { - serial_outp(p, UART_LCR, 0xBF); + serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B); serial_outp(p, UART_EFR, UART_EFR_ECB); serial_outp(p, UART_LCR, 0); } serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); if (p->capabilities & UART_CAP_EFR) { - serial_outp(p, UART_LCR, 0xBF); + serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B); serial_outp(p, UART_EFR, 0); serial_outp(p, UART_LCR, 0); } @@ -752,7 +752,7 @@ static int size_fifo(struct uart_8250_port *up) serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); serial_outp(up, UART_MCR, UART_MCR_LOOP); - serial_outp(up, UART_LCR, UART_LCR_DLAB); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A); old_dl = serial_dl_read(up); serial_dl_write(up, 0x0001); serial_outp(up, UART_LCR, 0x03); @@ -764,7 +764,7 @@ static int size_fifo(struct uart_8250_port *up) serial_inp(up, UART_RX); serial_outp(up, UART_FCR, old_fcr); serial_outp(up, UART_MCR, old_mcr); - serial_outp(up, UART_LCR, UART_LCR_DLAB); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_dl_write(up, old_dl); serial_outp(up, UART_LCR, old_lcr); @@ -782,7 +782,7 @@ static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) unsigned int id; old_lcr = serial_inp(p, UART_LCR); - serial_outp(p, UART_LCR, UART_LCR_DLAB); + serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A); old_dll = serial_inp(p, UART_DLL); old_dlm = serial_inp(p, UART_DLM); @@ -836,7 +836,7 @@ static void autoconfig_has_efr(struct uart_8250_port *up) * recommended for new designs). */ up->acr = 0; - serial_out(up, UART_LCR, 0xBF); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, UART_EFR_ECB); serial_out(up, UART_LCR, 0x00); id1 = serial_icr_read(up, UART_ID1); @@ -945,7 +945,7 @@ static void autoconfig_16550a(struct uart_8250_port *up) * Check for presence of the EFR when DLAB is set. * Only ST16C650V1 UARTs pass this test. */ - serial_outp(up, UART_LCR, UART_LCR_DLAB); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A); if (serial_in(up, UART_EFR) == 0) { serial_outp(up, UART_EFR, 0xA8); if (serial_in(up, UART_EFR) != 0) { @@ -963,7 +963,7 @@ static void autoconfig_16550a(struct uart_8250_port *up) * Maybe it requires 0xbf to be written to the LCR. * (other ST16C650V2 UARTs, TI16C752A, etc) */ - serial_outp(up, UART_LCR, 0xBF); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B); if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { DEBUG_AUTOCONF("EFRv2 "); autoconfig_has_efr(up); @@ -1024,7 +1024,7 @@ static void autoconfig_16550a(struct uart_8250_port *up) serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); status1 = serial_in(up, UART_IIR) >> 5; serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); - serial_outp(up, UART_LCR, UART_LCR_DLAB); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); status2 = serial_in(up, UART_IIR) >> 5; serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO); @@ -1183,7 +1183,7 @@ static void autoconfig(struct uart_8250_port *up, unsigned int probeflags) * We also initialise the EFR (if any) to zero for later. The * EFR occupies the same register location as the FCR and IIR. */ - serial_outp(up, UART_LCR, 0xBF); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_outp(up, UART_EFR, 0); serial_outp(up, UART_LCR, 0); @@ -1952,7 +1952,7 @@ static int serial8250_startup(struct uart_port *port) if (up->port.type == PORT_16C950) { /* Wake up and initialize UART */ up->acr = 0; - serial_outp(up, UART_LCR, 0xBF); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_outp(up, UART_EFR, UART_EFR_ECB); serial_outp(up, UART_IER, 0); serial_outp(up, UART_LCR, 0); @@ -2002,7 +2002,7 @@ static int serial8250_startup(struct uart_port *port) if (up->port.type == PORT_16850) { unsigned char fctr; - serial_outp(up, UART_LCR, 0xbf); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B); fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX); @@ -2363,7 +2363,7 @@ serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_cflag & CRTSCTS) efr |= UART_EFR_CTS; - serial_outp(up, UART_LCR, 0xBF); + serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_outp(up, UART_EFR, efr); } diff --git a/drivers/serial/omap-serial.c b/drivers/serial/omap-serial.c index 03a96db67de4..1201eff1831e 100644 --- a/drivers/serial/omap-serial.c +++ b/drivers/serial/omap-serial.c @@ -570,7 +570,7 @@ serial_omap_configure_xonxoff unsigned char efr = 0; up->lcr = serial_in(up, UART_LCR); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); @@ -598,7 +598,7 @@ serial_omap_configure_xonxoff efr |= OMAP_UART_SW_RX; serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR); @@ -612,14 +612,14 @@ serial_omap_configure_xonxoff up->mcr |= UART_MCR_XONANY; serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); /* Enable special char function UARTi.EFR_REG[5] and * load the new software flow control mode IXON or IXOFF * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. */ serial_out(up, UART_EFR, efr | UART_EFR_SCD); - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); serial_out(up, UART_LCR, up->lcr); @@ -724,22 +724,22 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, * baud clock is not running * DLL_REG and DLH_REG set to 0. */ - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_DLL, 0); serial_out(up, UART_DLM, 0); serial_out(up, UART_LCR, 0); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR); serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); /* FIFO ENABLE, DMA MODE */ serial_out(up, UART_FCR, up->fcr); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); if (up->use_dma) { serial_out(up, UART_TI752_TLR, 0); @@ -748,27 +748,27 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, } serial_out(up, UART_EFR, up->efr); - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr); /* Protocol, Baud Rate, and Interrupt Settings */ serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, 0); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, up->ier); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, cval); @@ -782,18 +782,18 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, if (termios->c_cflag & CRTSCTS) { efr |= (UART_EFR_CTS | UART_EFR_RTS); - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR); serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ - serial_out(up, UART_LCR, UART_LCR_DLAB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); serial_out(up, UART_LCR, cval); } @@ -815,13 +815,13 @@ serial_omap_pm(struct uart_port *port, unsigned int state, unsigned char efr; dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, efr | UART_EFR_ECB); serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); - serial_out(up, UART_LCR, OMAP_UART_LCR_CONF_MDB); + serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, efr); serial_out(up, UART_LCR, 0); /* Enable module level wake up */ diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h index 6f3823474e6c..3ecb71a9e505 100644 --- a/include/linux/serial_reg.h +++ b/include/linux/serial_reg.h @@ -99,6 +99,13 @@ #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ +/* + * Access to some registers depends on register access / configuration + * mode. + */ +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ + #define UART_MCR 4 /* Out: Modem Control Register */ #define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ -- cgit v1.2.3