From d38e2e7bcb3e27d1d1433e5f7480f2a1ff6bcd98 Mon Sep 17 00:00:00 2001 From: Vincent Chen Date: Tue, 5 Sep 2023 15:09:45 +0800 Subject: clocksource: extend the max_delta_ns of timer-riscv and timer-clint to ULONG_MAX When registering the riscv-timer or clint-timer as a clock_event device, the driver needs to specify the value of max_delta_ticks. This value directly influences the max_delta_ns, which represents the maximum time interval for configuring subsequent clock events. Currently, both riscv-timer and clint-timer are set with a max_delta_ticks value of 0x7fff_ffff. When the timer operates at a high frequency, this values limists the system to sleep only for a short time. For the 1GHz case, the sleep cannot exceed two seconds. To address this limitation, refer to other timer implementations to extend it to 2^(bit-width of the timer) - 1. Because the bit-width of $mtimecmp is 64bit, this value becomes ULONG_MAX (0xffff_ffff_ffff_ffff). Signed-off-by: Vincent Chen Link: https://lore.kernel.org/r/20230905070945.404653-1-vincent.chen@sifive.com Signed-off-by: Palmer Dabbelt --- drivers/clocksource/timer-riscv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/clocksource/timer-riscv.c') diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..87a7ac0ce6ce 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -114,7 +114,7 @@ static int riscv_timer_starting_cpu(unsigned int cpu) ce->features |= CLOCK_EVT_FEAT_C3STOP; if (static_branch_likely(&riscv_sstc_available)) ce->rating = 450; - clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff); + clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX); enable_percpu_irq(riscv_clock_event_irq, irq_get_trigger_type(riscv_clock_event_irq)); -- cgit v1.2.3 From 8248ca30ef89f9cc74ace62ae1b9a22b5f16736c Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Thu, 7 Mar 2024 01:23:30 +0800 Subject: clocksource/drivers/timer-riscv: Clear timer interrupt on timer initialization In the RISC-V specification, the stimecmp register doesn't have a default value. To prevent the timer interrupt from being triggered during timer initialization, clear the timer interrupt by writing stimecmp with a maximum value. Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available") Cc: Signed-off-by: Ley Foon Tan Reviewed-by: Samuel Holland Tested-by: Samuel Holland Reviewed-by: Atish Patra Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20240306172330.255844-1-leyfoon.tan@starfivetech.com --- drivers/clocksource/timer-riscv.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/clocksource/timer-riscv.c') diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index e66dcbd66566..79bb9a98baa7 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -108,6 +108,9 @@ static int riscv_timer_starting_cpu(unsigned int cpu) { struct clock_event_device *ce = per_cpu_ptr(&riscv_clock_event, cpu); + /* Clear timer interrupt */ + riscv_clock_event_stop(); + ce->cpumask = cpumask_of(cpu); ce->irq = riscv_clock_event_irq; if (riscv_timer_cannot_wake_cpu) -- cgit v1.2.3