From 4562236b3bc0a28aeb6ee93b2d8a849a4c4e1c7c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 15:58:20 -0400 Subject: drm/amd/dc: Add dc display driver (v2) Supported DCE versions: 8.0, 10.0, 11.0, 11.2 v2: rebase against 4.11 Signed-off-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1564 +++++++++++++++++++++ 1 file changed, 1564 insertions(+) create mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c new file mode 100644 index 000000000000..ae4ba7777839 --- /dev/null +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -0,0 +1,1564 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#include "dm_services_types.h" +#include "dc.h" + +#include "vid.h" +#include "amdgpu.h" +#include "atom.h" +#include "amdgpu_dm.h" +#include "amdgpu_dm_types.h" + +#include "amd_shared.h" +#include "amdgpu_dm_irq.h" +#include "dm_helpers.h" + +#include "ivsrcid/ivsrcid_vislands30.h" + +#include +#include +#include + +#include +#include +#include + +#include "modules/inc/mod_freesync.h" + +/* Debug facilities */ +#define AMDGPU_DM_NOT_IMPL(fmt, ...) \ + DRM_INFO("DM_NOT_IMPL: " fmt, ##__VA_ARGS__) + +/* + * dm_vblank_get_counter + * + * @brief + * Get counter for number of vertical blanks + * + * @param + * struct amdgpu_device *adev - [in] desired amdgpu device + * int disp_idx - [in] which CRTC to get the counter from + * + * @return + * Counter for vertical blanks + */ +static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + if (crtc >= adev->mode_info.num_crtc) + return 0; + else { + struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; + + if (NULL == acrtc->target) { + DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + return 0; + } + + return dc_target_get_vblank_counter(acrtc->target); + } +} + +static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) + return -EINVAL; + else { + struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; + + if (NULL == acrtc->target) { + DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + return 0; + } + + return dc_target_get_scanoutpos(acrtc->target, vbl, position); + } + + return 0; +} + +static bool dm_is_idle(void *handle) +{ + /* XXX todo */ + return true; +} + +static int dm_wait_for_idle(void *handle) +{ + /* XXX todo */ + return 0; +} + +static bool dm_check_soft_reset(void *handle) +{ + return false; +} + +static int dm_soft_reset(void *handle) +{ + /* XXX todo */ + return 0; +} + +static struct amdgpu_crtc *get_crtc_by_otg_inst( + struct amdgpu_device *adev, + int otg_inst) +{ + struct drm_device *dev = adev->ddev; + struct drm_crtc *crtc; + struct amdgpu_crtc *amdgpu_crtc; + + /* + * following if is check inherited from both functions where this one is + * used now. Need to be checked why it could happen. + */ + if (otg_inst == -1) { + WARN_ON(1); + return adev->mode_info.crtcs[0]; + } + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + amdgpu_crtc = to_amdgpu_crtc(crtc); + + if (amdgpu_crtc->otg_inst == otg_inst) + return amdgpu_crtc; + } + + return NULL; +} + +static void dm_pflip_high_irq(void *interrupt_params) +{ + struct amdgpu_flip_work *works; + struct amdgpu_crtc *amdgpu_crtc; + struct common_irq_params *irq_params = interrupt_params; + struct amdgpu_device *adev = irq_params->adev; + unsigned long flags; + + amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP); + + /* IRQ could occur when in initial stage */ + /*TODO work and BO cleanup */ + if (amdgpu_crtc == NULL) { + DRM_DEBUG_DRIVER("CRTC is null, returning.\n"); + return; + } + + spin_lock_irqsave(&adev->ddev->event_lock, flags); + works = amdgpu_crtc->pflip_works; + + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ + DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", + amdgpu_crtc->pflip_status, + AMDGPU_FLIP_SUBMITTED, + amdgpu_crtc->crtc_id, + amdgpu_crtc); + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + return; + } + + /* page flip completed. clean up */ + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; + amdgpu_crtc->pflip_works = NULL; + + /* wakeup usersapce */ + if (works->event) + drm_crtc_send_vblank_event(&amdgpu_crtc->base, + works->event); + + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE, work: %p,\n", + __func__, amdgpu_crtc->crtc_id, amdgpu_crtc, works); + + drm_crtc_vblank_put(&amdgpu_crtc->base); + schedule_work(&works->unpin_work); +} + +static void dm_crtc_high_irq(void *interrupt_params) +{ + struct common_irq_params *irq_params = interrupt_params; + struct amdgpu_device *adev = irq_params->adev; + uint8_t crtc_index = 0; + struct amdgpu_crtc *acrtc; + + acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); + + if (acrtc) + crtc_index = acrtc->crtc_id; + + drm_handle_vblank(adev->ddev, crtc_index); +} + +static int dm_set_clockgating_state(void *handle, + enum amd_clockgating_state state) +{ + return 0; +} + +static int dm_set_powergating_state(void *handle, + enum amd_powergating_state state) +{ + return 0; +} + +/* Prototypes of private functions */ +static int dm_early_init(void* handle); + +static void hotplug_notify_work_func(struct work_struct *work) +{ + struct amdgpu_display_manager *dm = container_of(work, struct amdgpu_display_manager, mst_hotplug_work); + struct drm_device *dev = dm->ddev; + + drm_kms_helper_hotplug_event(dev); +} + +/* Init display KMS + * + * Returns 0 on success + */ +int amdgpu_dm_init(struct amdgpu_device *adev) +{ + struct dc_init_data init_data; + adev->dm.ddev = adev->ddev; + adev->dm.adev = adev; + + DRM_INFO("DAL is enabled\n"); + /* Zero all the fields */ + memset(&init_data, 0, sizeof(init_data)); + + /* initialize DAL's lock (for SYNC context use) */ + spin_lock_init(&adev->dm.dal_lock); + + /* initialize DAL's mutex */ + mutex_init(&adev->dm.dal_mutex); + + if(amdgpu_dm_irq_init(adev)) { + DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); + goto error; + } + + init_data.asic_id.chip_family = adev->family; + + init_data.asic_id.pci_revision_id = adev->rev_id; + init_data.asic_id.hw_internal_rev = adev->external_rev_id; + + init_data.asic_id.vram_width = adev->mc.vram_width; + /* TODO: initialize init_data.asic_id.vram_type here!!!! */ + init_data.asic_id.atombios_base_address = + adev->mode_info.atom_context->bios; + + init_data.driver = adev; + + adev->dm.cgs_device = amdgpu_cgs_create_device(adev); + + if (!adev->dm.cgs_device) { + DRM_ERROR("amdgpu: failed to create cgs device.\n"); + goto error; + } + + init_data.cgs_device = adev->dm.cgs_device; + + adev->dm.dal = NULL; + + init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; + + /* Display Core create. */ + adev->dm.dc = dc_create(&init_data); + + if (!adev->dm.dc) + DRM_INFO("Display Core failed to initialize!\n"); + + INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func); + + adev->dm.freesync_module = mod_freesync_create(adev->dm.dc); + if (!adev->dm.freesync_module) { + DRM_ERROR( + "amdgpu: failed to initialize freesync_module.\n"); + } else + DRM_INFO("amdgpu: freesync_module init done %p.\n", + adev->dm.freesync_module); + + if (amdgpu_dm_initialize_drm_device(adev)) { + DRM_ERROR( + "amdgpu: failed to initialize sw for display support.\n"); + goto error; + } + + /* Update the actual used number of crtc */ + adev->mode_info.num_crtc = adev->dm.display_indexes_num; + + /* TODO: Add_display_info? */ + + /* TODO use dynamic cursor width */ + adev->ddev->mode_config.cursor_width = 128; + adev->ddev->mode_config.cursor_height = 128; + + if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { + DRM_ERROR( + "amdgpu: failed to initialize sw for display support.\n"); + goto error; + } + + DRM_INFO("KMS initialized.\n"); + + return 0; +error: + amdgpu_dm_fini(adev); + + return -1; +} + +void amdgpu_dm_fini(struct amdgpu_device *adev) +{ + amdgpu_dm_destroy_drm_device(&adev->dm); + /* + * TODO: pageflip, vlank interrupt + * + * amdgpu_dm_irq_fini(adev); + */ + + if (adev->dm.cgs_device) { + amdgpu_cgs_destroy_device(adev->dm.cgs_device); + adev->dm.cgs_device = NULL; + } + if (adev->dm.freesync_module) { + mod_freesync_destroy(adev->dm.freesync_module); + adev->dm.freesync_module = NULL; + } + /* DC Destroy TODO: Replace destroy DAL */ + { + dc_destroy(&adev->dm.dc); + } + return; +} + +/* moved from amdgpu_dm_kms.c */ +void amdgpu_dm_destroy() +{ +} + +static int dm_sw_init(void *handle) +{ + return 0; +} + +static int dm_sw_fini(void *handle) +{ + return 0; +} + +static void detect_link_for_all_connectors(struct drm_device *dev) +{ + struct amdgpu_connector *aconnector; + struct drm_connector *connector; + + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + aconnector = to_amdgpu_connector(connector); + if (aconnector->dc_link->type == dc_connection_mst_branch) { + DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", + aconnector, aconnector->base.base.id); + + if (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) < 0) { + DRM_ERROR("DM_MST: Failed to start MST\n"); + ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; + } + } + } + + drm_modeset_unlock(&dev->mode_config.connection_mutex); +} + +static void s3_handle_mst(struct drm_device *dev, bool suspend) +{ + struct amdgpu_connector *aconnector; + struct drm_connector *connector; + + drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); + + list_for_each_entry(connector, &dev->mode_config.connector_list, head) { + aconnector = to_amdgpu_connector(connector); + if (aconnector->dc_link->type == dc_connection_mst_branch && + !aconnector->mst_port) { + + if (suspend) + drm_dp_mst_topology_mgr_suspend(&aconnector->mst_mgr); + else + drm_dp_mst_topology_mgr_resume(&aconnector->mst_mgr); + } + } + + drm_modeset_unlock(&dev->mode_config.connection_mutex); +} + +static int dm_hw_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + /* Create DAL display manager */ + amdgpu_dm_init(adev); + + amdgpu_dm_hpd_init(adev); + + detect_link_for_all_connectors(adev->ddev); + + return 0; +} + +static int dm_hw_fini(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_dm_hpd_fini(adev); + + amdgpu_dm_irq_fini(adev); + + return 0; +} + +static int dm_suspend(void *handle) +{ + struct amdgpu_device *adev = handle; + struct amdgpu_display_manager *dm = &adev->dm; + int ret = 0; + struct drm_crtc *crtc; + + s3_handle_mst(adev->ddev, true); + + /* flash all pending vblank events and turn interrupt off + * before disabling CRTCs. They will be enabled back in + * dm_display_resume + */ + drm_modeset_lock_all(adev->ddev); + list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + if (acrtc->target) + drm_crtc_vblank_off(crtc); + } + drm_modeset_unlock_all(adev->ddev); + + amdgpu_dm_irq_suspend(adev); + + dc_set_power_state( + dm->dc, + DC_ACPI_CM_POWER_STATE_D3, + DC_VIDEO_POWER_SUSPEND); + + return ret; +} + +struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( + struct drm_atomic_state *state, + struct drm_crtc *crtc, + bool from_state_var) +{ + uint32_t i; + struct drm_connector_state *conn_state; + struct drm_connector *connector; + struct drm_crtc *crtc_from_state; + + for_each_connector_in_state( + state, + connector, + conn_state, + i) { + crtc_from_state = + from_state_var ? + conn_state->crtc : + connector->state->crtc; + + if (crtc_from_state == crtc) + return to_amdgpu_connector(connector); + } + + return NULL; +} + +static int dm_display_resume(struct drm_device *ddev) +{ + int ret = 0; + struct drm_connector *connector; + + struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); + struct drm_plane *plane; + struct drm_crtc *crtc; + struct amdgpu_connector *aconnector; + struct drm_connector_state *conn_state; + + if (!state) + return ENOMEM; + + state->acquire_ctx = ddev->mode_config.acquire_ctx; + + /* Construct an atomic state to restore previous display setting */ + + /* + * Attach connectors to drm_atomic_state + * Should be done in the first place in order to make connectors + * available in state during crtc state processing. It is used for + * making decision if crtc should be disabled in case sink got + * disconnected. + * + * Connectors state crtc with NULL dc_sink should be cleared, because it + * will fail validation during commit + */ + list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { + aconnector = to_amdgpu_connector(connector); + conn_state = drm_atomic_get_connector_state(state, connector); + + ret = PTR_ERR_OR_ZERO(conn_state); + if (ret) + goto err; + } + + /* Attach crtcs to drm_atomic_state*/ + list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { + struct drm_crtc_state *crtc_state = + drm_atomic_get_crtc_state(state, crtc); + + ret = PTR_ERR_OR_ZERO(crtc_state); + if (ret) + goto err; + + /* force a restore */ + crtc_state->mode_changed = true; + } + + + /* Attach planes to drm_atomic_state */ + list_for_each_entry(plane, &ddev->mode_config.plane_list, head) { + + struct drm_crtc *crtc; + struct drm_gem_object *obj; + struct drm_framebuffer *fb; + struct amdgpu_framebuffer *afb; + struct amdgpu_bo *rbo; + int r; + struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane); + + ret = PTR_ERR_OR_ZERO(plane_state); + if (ret) + goto err; + + crtc = plane_state->crtc; + fb = plane_state->fb; + + if (!crtc || !crtc->state || !crtc->state->active) + continue; + + if (!fb) { + DRM_DEBUG_KMS("No FB bound\n"); + return 0; + } + + /* + * Pin back the front buffers, cursor buffer was already pinned + * back in amdgpu_resume_kms + */ + + afb = to_amdgpu_framebuffer(fb); + + obj = afb->obj; + rbo = gem_to_amdgpu_bo(obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL); + + amdgpu_bo_unreserve(rbo); + + if (unlikely(r != 0)) { + DRM_ERROR("Failed to pin framebuffer\n"); + return r; + } + + } + + + /* Call commit internally with the state we just constructed */ + ret = drm_atomic_commit(state); + if (!ret) + return 0; + +err: + DRM_ERROR("Restoring old state failed with %i\n", ret); + drm_atomic_state_put(state); + + return ret; +} + +static int dm_resume(void *handle) +{ + struct amdgpu_device *adev = handle; + struct amdgpu_display_manager *dm = &adev->dm; + + /* power on hardware */ + dc_set_power_state( + dm->dc, + DC_ACPI_CM_POWER_STATE_D0, + DC_VIDEO_POWER_ON); + + return 0; +} + +int amdgpu_dm_display_resume(struct amdgpu_device *adev ) +{ + struct drm_device *ddev = adev->ddev; + struct amdgpu_display_manager *dm = &adev->dm; + struct amdgpu_connector *aconnector; + struct drm_connector *connector; + int ret = 0; + struct drm_crtc *crtc; + + /* program HPD filter */ + dc_resume(dm->dc); + + /* On resume we need to rewrite the MSTM control bits to enamble MST*/ + s3_handle_mst(ddev, false); + + /* + * early enable HPD Rx IRQ, should be done before set mode as short + * pulse interrupts are used for MST + */ + amdgpu_dm_irq_resume_early(adev); + + drm_modeset_lock_all(ddev); + list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + if (acrtc->target) + drm_crtc_vblank_on(crtc); + } + drm_modeset_unlock_all(ddev); + + /* Do detection*/ + list_for_each_entry(connector, + &ddev->mode_config.connector_list, head) { + aconnector = to_amdgpu_connector(connector); + + /* + * this is the case when traversing through already created + * MST connectors, should be skipped + */ + if (aconnector->mst_port) + continue; + + dc_link_detect(aconnector->dc_link, false); + aconnector->dc_sink = NULL; + amdgpu_dm_update_connector_after_detect(aconnector); + } + + drm_modeset_lock_all(ddev); + ret = dm_display_resume(ddev); + drm_modeset_unlock_all(ddev); + + amdgpu_dm_irq_resume(adev); + + return ret; +} + +static const struct amd_ip_funcs amdgpu_dm_funcs = { + .name = "dm", + .early_init = dm_early_init, + .late_init = NULL, + .sw_init = dm_sw_init, + .sw_fini = dm_sw_fini, + .hw_init = dm_hw_init, + .hw_fini = dm_hw_fini, + .suspend = dm_suspend, + .resume = dm_resume, + .is_idle = dm_is_idle, + .wait_for_idle = dm_wait_for_idle, + .check_soft_reset = dm_check_soft_reset, + .soft_reset = dm_soft_reset, + .set_clockgating_state = dm_set_clockgating_state, + .set_powergating_state = dm_set_powergating_state, +}; + +const struct amdgpu_ip_block_version dm_ip_block = +{ + .type = AMD_IP_BLOCK_TYPE_DCE, + .major = 1, + .minor = 0, + .rev = 0, + .funcs = &amdgpu_dm_funcs, +}; + +/* TODO: it is temporary non-const, should fixed later */ +static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { + .atomic_check = amdgpu_dm_atomic_check, + .atomic_commit = amdgpu_dm_atomic_commit +}; + +void amdgpu_dm_update_connector_after_detect( + struct amdgpu_connector *aconnector) +{ + struct drm_connector *connector = &aconnector->base; + struct drm_device *dev = connector->dev; + const struct dc_sink *sink; + + /* MST handled by drm_mst framework */ + if (aconnector->mst_mgr.mst_state == true) + return; + + + sink = aconnector->dc_link->local_sink; + + /* Edid mgmt connector gets first update only in mode_valid hook and then + * the connector sink is set to either fake or physical sink depends on link status. + * don't do it here if u are during boot + */ + if (aconnector->base.force != DRM_FORCE_UNSPECIFIED + && aconnector->dc_em_sink) { + + /* For S3 resume with headless use eml_sink to fake target + * because on resume connecotr->sink is set ti NULL + */ + mutex_lock(&dev->mode_config.mutex); + + if (sink) { + if (aconnector->dc_sink) + amdgpu_dm_remove_sink_from_freesync_module( + connector); + aconnector->dc_sink = sink; + amdgpu_dm_add_sink_to_freesync_module( + connector, aconnector->edid); + } else { + amdgpu_dm_remove_sink_from_freesync_module(connector); + if (!aconnector->dc_sink) + aconnector->dc_sink = aconnector->dc_em_sink; + } + + mutex_unlock(&dev->mode_config.mutex); + return; + } + + /* + * TODO: temporary guard to look for proper fix + * if this sink is MST sink, we should not do anything + */ + if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) + return; + + if (aconnector->dc_sink == sink) { + /* We got a DP short pulse (Link Loss, DP CTS, etc...). + * Do nothing!! */ + DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n", + aconnector->connector_id); + return; + } + + DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", + aconnector->connector_id, aconnector->dc_sink, sink); + + mutex_lock(&dev->mode_config.mutex); + + /* 1. Update status of the drm connector + * 2. Send an event and let userspace tell us what to do */ + if (sink) { + /* TODO: check if we still need the S3 mode update workaround. + * If yes, put it here. */ + if (aconnector->dc_sink) + amdgpu_dm_remove_sink_from_freesync_module( + connector); + + aconnector->dc_sink = sink; + if (sink->dc_edid.length == 0) + aconnector->edid = NULL; + else { + aconnector->edid = + (struct edid *) sink->dc_edid.raw_edid; + + + drm_mode_connector_update_edid_property(connector, + aconnector->edid); + } + amdgpu_dm_add_sink_to_freesync_module(connector, aconnector->edid); + + } else { + amdgpu_dm_remove_sink_from_freesync_module(connector); + drm_mode_connector_update_edid_property(connector, NULL); + aconnector->num_modes = 0; + aconnector->dc_sink = NULL; + } + + mutex_unlock(&dev->mode_config.mutex); +} + +static void handle_hpd_irq(void *param) +{ + struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param; + struct drm_connector *connector = &aconnector->base; + struct drm_device *dev = connector->dev; + + /* In case of failure or MST no need to update connector status or notify the OS + * since (for MST case) MST does this in it's own context. + */ + mutex_lock(&aconnector->hpd_lock); + if (dc_link_detect(aconnector->dc_link, false)) { + amdgpu_dm_update_connector_after_detect(aconnector); + + + drm_modeset_lock_all(dev); + dm_restore_drm_connector_state(dev, connector); + drm_modeset_unlock_all(dev); + + if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) + drm_kms_helper_hotplug_event(dev); + } + mutex_unlock(&aconnector->hpd_lock); + +} + +static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector) +{ + uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; + uint8_t dret; + bool new_irq_handled = false; + int dpcd_addr; + int dpcd_bytes_to_read; + + const int max_process_count = 30; + int process_count = 0; + + const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link); + + if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) { + dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT; + /* DPCD 0x200 - 0x201 for downstream IRQ */ + dpcd_addr = DP_SINK_COUNT; + } else { + dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI; + /* DPCD 0x2002 - 0x2005 for downstream IRQ */ + dpcd_addr = DP_SINK_COUNT_ESI; + } + + dret = drm_dp_dpcd_read( + &aconnector->dm_dp_aux.aux, + dpcd_addr, + esi, + dpcd_bytes_to_read); + + while (dret == dpcd_bytes_to_read && + process_count < max_process_count) { + uint8_t retry; + dret = 0; + + process_count++; + + DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0) + /* handle HPD short pulse irq */ + if (aconnector->mst_mgr.mst_state) + drm_dp_mst_hpd_irq( + &aconnector->mst_mgr, + esi, + &new_irq_handled); +#endif + + if (new_irq_handled) { + /* ACK at DPCD to notify down stream */ + const int ack_dpcd_bytes_to_write = + dpcd_bytes_to_read - 1; + + for (retry = 0; retry < 3; retry++) { + uint8_t wret; + + wret = drm_dp_dpcd_write( + &aconnector->dm_dp_aux.aux, + dpcd_addr + 1, + &esi[1], + ack_dpcd_bytes_to_write); + if (wret == ack_dpcd_bytes_to_write) + break; + } + + /* check if there is new irq to be handle */ + dret = drm_dp_dpcd_read( + &aconnector->dm_dp_aux.aux, + dpcd_addr, + esi, + dpcd_bytes_to_read); + + new_irq_handled = false; + } else + break; + } + + if (process_count == max_process_count) + DRM_DEBUG_KMS("Loop exceeded max iterations\n"); +} + +static void handle_hpd_rx_irq(void *param) +{ + struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param; + struct drm_connector *connector = &aconnector->base; + struct drm_device *dev = connector->dev; + const struct dc_link *dc_link = aconnector->dc_link; + bool is_mst_root_connector = aconnector->mst_mgr.mst_state; + + /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio + * conflict, after implement i2c helper, this mutex should be + * retired. + */ + if (aconnector->dc_link->type != dc_connection_mst_branch) + mutex_lock(&aconnector->hpd_lock); + + if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) && + !is_mst_root_connector) { + /* Downstream Port status changed. */ + if (dc_link_detect(aconnector->dc_link, false)) { + amdgpu_dm_update_connector_after_detect(aconnector); + + + drm_modeset_lock_all(dev); + dm_restore_drm_connector_state(dev, connector); + drm_modeset_unlock_all(dev); + + drm_kms_helper_hotplug_event(dev); + } + } + if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || + (dc_link->type == dc_connection_mst_branch)) + dm_handle_hpd_rx_irq(aconnector); + + if (aconnector->dc_link->type != dc_connection_mst_branch) + mutex_unlock(&aconnector->hpd_lock); +} + +static void register_hpd_handlers(struct amdgpu_device *adev) +{ + struct drm_device *dev = adev->ddev; + struct drm_connector *connector; + struct amdgpu_connector *aconnector; + const struct dc_link *dc_link; + struct dc_interrupt_params int_params = {0}; + + int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; + int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; + + list_for_each_entry(connector, + &dev->mode_config.connector_list, head) { + + aconnector = to_amdgpu_connector(connector); + dc_link = aconnector->dc_link; + + if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { + int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; + int_params.irq_source = dc_link->irq_source_hpd; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + handle_hpd_irq, + (void *) aconnector); + } + + if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) { + + /* Also register for DP short pulse (hpd_rx). */ + int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT; + int_params.irq_source = dc_link->irq_source_hpd_rx; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + handle_hpd_rx_irq, + (void *) aconnector); + } + } +} + +/* Register IRQ sources and initialize IRQ callbacks */ +static int dce110_register_irq_handlers(struct amdgpu_device *adev) +{ + struct dc *dc = adev->dm.dc; + struct common_irq_params *c_irq_params; + struct dc_interrupt_params int_params = {0}; + int r; + int i; + + int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; + int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; + + /* Actions of amdgpu_irq_add_id(): + * 1. Register a set() function with base driver. + * Base driver will call set() function to enable/disable an + * interrupt in DC hardware. + * 2. Register amdgpu_dm_irq_handler(). + * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts + * coming from DC hardware. + * amdgpu_dm_irq_handler() will re-direct the interrupt to DC + * for acknowledging and handling. */ + + for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; + i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); + if (r) { + DRM_ERROR("Failed to add crtc irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_crtc_high_irq, c_irq_params); + } + + for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; + i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); + if (r) { + DRM_ERROR("Failed to add page flip irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_pflip_high_irq, c_irq_params); + + } + + /* HPD */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, + &adev->hpd_irq); + if (r) { + DRM_ERROR("Failed to add hpd irq id!\n"); + return r; + } + + register_hpd_handlers(adev); + + return 0; +} + +static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) +{ + int r; + + adev->mode_info.mode_config_initialized = true; + + amdgpu_dm_mode_funcs.fb_create = + amdgpu_mode_funcs.fb_create; + amdgpu_dm_mode_funcs.output_poll_changed = + amdgpu_mode_funcs.output_poll_changed; + + adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; + + adev->ddev->mode_config.max_width = 16384; + adev->ddev->mode_config.max_height = 16384; + + adev->ddev->mode_config.preferred_depth = 24; + adev->ddev->mode_config.prefer_shadow = 1; + /* indicate support of immediate flip */ + adev->ddev->mode_config.async_page_flip = true; + + adev->ddev->mode_config.fb_base = adev->mc.aper_base; + + r = amdgpu_modeset_create_props(adev); + if (r) + return r; + + return 0; +} + +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ + defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + +static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) +{ + struct amdgpu_display_manager *dm = bl_get_data(bd); + + if (dc_link_set_backlight_level(dm->backlight_link, + bd->props.brightness, 0, 0)) + return 0; + else + return 1; +} + +static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) +{ + return bd->props.brightness; +} + +static const struct backlight_ops amdgpu_dm_backlight_ops = { + .get_brightness = amdgpu_dm_backlight_get_brightness, + .update_status = amdgpu_dm_backlight_update_status, +}; + +void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) +{ + char bl_name[16]; + struct backlight_properties props = { 0 }; + + props.max_brightness = AMDGPU_MAX_BL_LEVEL; + props.type = BACKLIGHT_RAW; + + snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d", + dm->adev->ddev->primary->index); + + dm->backlight_dev = backlight_device_register(bl_name, + dm->adev->ddev->dev, + dm, + &amdgpu_dm_backlight_ops, + &props); + + if (NULL == dm->backlight_dev) + DRM_ERROR("DM: Backlight registration failed!\n"); + else + DRM_INFO("DM: Registered Backlight device: %s\n", bl_name); +} + +#endif + +/* In this architecture, the association + * connector -> encoder -> crtc + * id not really requried. The crtc and connector will hold the + * display_index as an abstraction to use with DAL component + * + * Returns 0 on success + */ +int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) +{ + struct amdgpu_display_manager *dm = &adev->dm; + uint32_t i; + struct amdgpu_connector *aconnector; + struct amdgpu_encoder *aencoder; + struct amdgpu_crtc *acrtc; + uint32_t link_cnt; + + link_cnt = dm->dc->caps.max_links; + + if (amdgpu_dm_mode_config_init(dm->adev)) { + DRM_ERROR("DM: Failed to initialize mode config\n"); + return -1; + } + + for (i = 0; i < dm->dc->caps.max_targets; i++) { + acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); + if (!acrtc) + goto fail; + + if (amdgpu_dm_crtc_init( + dm, + acrtc, + i)) { + DRM_ERROR("KMS: Failed to initialize crtc\n"); + kfree(acrtc); + goto fail; + } + } + + dm->display_indexes_num = dm->dc->caps.max_targets; + + /* loops over all connectors on the board */ + for (i = 0; i < link_cnt; i++) { + + if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) { + DRM_ERROR( + "KMS: Cannot support more than %d display indexes\n", + AMDGPU_DM_MAX_DISPLAY_INDEX); + continue; + } + + aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); + if (!aconnector) + goto fail; + + aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); + if (!aencoder) { + goto fail_free_connector; + } + + if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { + DRM_ERROR("KMS: Failed to initialize encoder\n"); + goto fail_free_encoder; + } + + if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { + DRM_ERROR("KMS: Failed to initialize connector\n"); + goto fail_free_connector; + } + + if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true)) + amdgpu_dm_update_connector_after_detect(aconnector); + } + + /* Software is initialized. Now we can register interrupt handlers. */ + switch (adev->asic_type) { + case CHIP_BONAIRE: + case CHIP_HAWAII: + case CHIP_TONGA: + case CHIP_FIJI: + case CHIP_CARRIZO: + case CHIP_STONEY: + case CHIP_POLARIS11: + case CHIP_POLARIS10: + if (dce110_register_irq_handlers(dm->adev)) { + DRM_ERROR("DM: Failed to initialize IRQ\n"); + return -1; + } + break; + default: + DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); + return -1; + } + + drm_mode_config_reset(dm->ddev); + + return 0; +fail_free_encoder: + kfree(aencoder); +fail_free_connector: + kfree(aconnector); +fail: + return -1; +} + +void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) +{ + drm_mode_config_cleanup(dm->ddev); + return; +} + +/****************************************************************************** + * amdgpu_display_funcs functions + *****************************************************************************/ + +/** + * dm_bandwidth_update - program display watermarks + * + * @adev: amdgpu_device pointer + * + * Calculate and program the display watermarks and line buffer allocation. + */ +static void dm_bandwidth_update(struct amdgpu_device *adev) +{ + AMDGPU_DM_NOT_IMPL("%s\n", __func__); +} + +static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, + u8 level) +{ + /* TODO: translate amdgpu_encoder to display_index and call DAL */ + AMDGPU_DM_NOT_IMPL("%s\n", __func__); +} + +static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder) +{ + /* TODO: translate amdgpu_encoder to display_index and call DAL */ + AMDGPU_DM_NOT_IMPL("%s\n", __func__); + return 0; +} + +/****************************************************************************** + * Page Flip functions + ******************************************************************************/ + +/** + * dm_page_flip - called by amdgpu_flip_work_func(), which is triggered + * via DRM IOCTL, by user mode. + * + * @adev: amdgpu_device pointer + * @crtc_id: crtc to cleanup pageflip on + * @crtc_base: new address of the crtc (GPU MC address) + * + * Does the actual pageflip (surface address update). + */ +static void dm_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) +{ + struct amdgpu_crtc *acrtc; + struct dc_target *target; + struct dc_flip_addrs addr = { {0} }; + + /* + * TODO risk of concurrency issues + * + * This should guarded by the dal_mutex but we can't do this since the + * caller uses a spin_lock on event_lock. + * + * If we wait on the dal_mutex a second page flip interrupt might come, + * spin on the event_lock, disabling interrupts while it does so. At + * this point the core can no longer be pre-empted and return to the + * thread that waited on the dal_mutex and we're deadlocked. + * + * With multiple cores the same essentially happens but might just take + * a little longer to lock up all cores. + * + * The reason we should lock on dal_mutex is so that we can be sure + * nobody messes with acrtc->target after we read and check its value. + * + * We might be able to fix our concurrency issues with a work queue + * where we schedule all work items (mode_set, page_flip, etc.) and + * execute them one by one. Care needs to be taken to still deal with + * any potential concurrency issues arising from interrupt calls. + */ + + acrtc = adev->mode_info.crtcs[crtc_id]; + target = acrtc->target; + + /* + * Received a page flip call after the display has been reset. + * Just return in this case. Everything should be clean-up on reset. + */ + + if (!target) { + WARN_ON(1); + return; + } + + addr.address.grph.addr.low_part = lower_32_bits(crtc_base); + addr.address.grph.addr.high_part = upper_32_bits(crtc_base); + addr.flip_immediate = async; + + DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", + __func__, + addr.address.grph.addr.high_part, + addr.address.grph.addr.low_part); + + dc_flip_surface_addrs( + adev->dm.dc, + dc_target_get_status(target)->surfaces, + &addr, 1); +} + +static int amdgpu_notify_freesync(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct mod_freesync_params freesync_params; + uint8_t num_targets; + uint8_t i; + struct dc_target *target; + + struct amdgpu_device *adev = dev->dev_private; + int r = 0; + + /* Get freesync enable flag from DRM */ + + num_targets = dc_get_current_target_count(adev->dm.dc); + + for (i = 0; i < num_targets; i++) { + + target = dc_get_target_at_index(adev->dm.dc, i); + + mod_freesync_update_state(adev->dm.freesync_module, + target->streams, + target->stream_count, + &freesync_params); + } + + return r; +} + +#ifdef CONFIG_DRM_AMDGPU_CIK +static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = { + .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ + .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ + .vblank_wait = NULL, + .backlight_set_level = + dm_set_backlight_level,/* called unconditionally */ + .backlight_get_level = + dm_get_backlight_level,/* called unconditionally */ + .hpd_sense = NULL,/* called unconditionally */ + .hpd_set_polarity = NULL, /* called unconditionally */ + .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ + .page_flip = dm_page_flip, /* called unconditionally */ + .page_flip_get_scanoutpos = + dm_crtc_get_scanoutpos,/* called unconditionally */ + .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ + .add_connector = NULL, /* VBIOS parsing. DAL does it. */ + .notify_freesync = amdgpu_notify_freesync, +}; +#endif + +static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = { + .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ + .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ + .vblank_wait = NULL, + .backlight_set_level = + dm_set_backlight_level,/* called unconditionally */ + .backlight_get_level = + dm_get_backlight_level,/* called unconditionally */ + .hpd_sense = NULL,/* called unconditionally */ + .hpd_set_polarity = NULL, /* called unconditionally */ + .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ + .page_flip = dm_page_flip, /* called unconditionally */ + .page_flip_get_scanoutpos = + dm_crtc_get_scanoutpos,/* called unconditionally */ + .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ + .add_connector = NULL, /* VBIOS parsing. DAL does it. */ + .notify_freesync = amdgpu_notify_freesync, + +}; + +static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = { + .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ + .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ + .vblank_wait = NULL, + .backlight_set_level = + dm_set_backlight_level,/* called unconditionally */ + .backlight_get_level = + dm_get_backlight_level,/* called unconditionally */ + .hpd_sense = NULL,/* called unconditionally */ + .hpd_set_polarity = NULL, /* called unconditionally */ + .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ + .page_flip = dm_page_flip, /* called unconditionally */ + .page_flip_get_scanoutpos = + dm_crtc_get_scanoutpos,/* called unconditionally */ + .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ + .add_connector = NULL, /* VBIOS parsing. DAL does it. */ + .notify_freesync = amdgpu_notify_freesync, + +}; + +#if defined(CONFIG_DEBUG_KERNEL_DC) + +static ssize_t s3_debug_store( + struct device *device, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + int ret; + int s3_state; + struct pci_dev *pdev = to_pci_dev(device); + struct drm_device *drm_dev = pci_get_drvdata(pdev); + struct amdgpu_device *adev = drm_dev->dev_private; + + ret = kstrtoint(buf, 0, &s3_state); + + if (ret == 0) { + if (s3_state) { + dm_resume(adev); + amdgpu_dm_display_resume(adev); + drm_kms_helper_hotplug_event(adev->ddev); + } else + dm_suspend(adev); + } + + return ret == 0 ? count : 0; +} + +DEVICE_ATTR_WO(s3_debug); + +#endif + +static int dm_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + amdgpu_dm_set_irq_funcs(adev); + + switch (adev->asic_type) { + case CHIP_BONAIRE: + case CHIP_HAWAII: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; +#ifdef CONFIG_DRM_AMDGPU_CIK + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v8_0_display_funcs; +#endif + break; + case CHIP_FIJI: + case CHIP_TONGA: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v10_0_display_funcs; + break; + case CHIP_CARRIZO: + adev->mode_info.num_crtc = 3; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; + break; + case CHIP_STONEY: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 9; + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; + break; + case CHIP_POLARIS11: + adev->mode_info.num_crtc = 5; + adev->mode_info.num_hpd = 5; + adev->mode_info.num_dig = 5; + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; + break; + case CHIP_POLARIS10: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; + break; + default: + DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); + return -EINVAL; + } + + /* Note: Do NOT change adev->audio_endpt_rreg and + * adev->audio_endpt_wreg because they are initialised in + * amdgpu_device_init() */ +#if defined(CONFIG_DEBUG_KERNEL_DC) + device_create_file( + adev->ddev->dev, + &dev_attr_s3_debug); +#endif + + return 0; +} + +bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) +{ + /* TODO */ + return true; +} + +bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) +{ + /* TODO */ + return true; +} + + -- cgit v1.2.3 From 39cc5be276d4ea7d64531f6f207e57f27bdba47d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 13 Dec 2016 15:42:48 -0500 Subject: drm/amd/dc/dm: remove redundant display structs Now that the mc_access functions are gone, we no longer need separate structs for all the different dce families in dm. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 60 ++--------------------- 1 file changed, 4 insertions(+), 56 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ae4ba7777839..fa55147d0c47 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1386,48 +1386,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, return r; } -#ifdef CONFIG_DRM_AMDGPU_CIK -static const struct amdgpu_display_funcs dm_dce_v8_0_display_funcs = { - .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ - .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ - .vblank_wait = NULL, - .backlight_set_level = - dm_set_backlight_level,/* called unconditionally */ - .backlight_get_level = - dm_get_backlight_level,/* called unconditionally */ - .hpd_sense = NULL,/* called unconditionally */ - .hpd_set_polarity = NULL, /* called unconditionally */ - .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ - .page_flip = dm_page_flip, /* called unconditionally */ - .page_flip_get_scanoutpos = - dm_crtc_get_scanoutpos,/* called unconditionally */ - .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ - .add_connector = NULL, /* VBIOS parsing. DAL does it. */ - .notify_freesync = amdgpu_notify_freesync, -}; -#endif - -static const struct amdgpu_display_funcs dm_dce_v10_0_display_funcs = { - .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ - .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ - .vblank_wait = NULL, - .backlight_set_level = - dm_set_backlight_level,/* called unconditionally */ - .backlight_get_level = - dm_get_backlight_level,/* called unconditionally */ - .hpd_sense = NULL,/* called unconditionally */ - .hpd_set_polarity = NULL, /* called unconditionally */ - .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ - .page_flip = dm_page_flip, /* called unconditionally */ - .page_flip_get_scanoutpos = - dm_crtc_get_scanoutpos,/* called unconditionally */ - .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ - .add_connector = NULL, /* VBIOS parsing. DAL does it. */ - .notify_freesync = amdgpu_notify_freesync, - -}; - -static const struct amdgpu_display_funcs dm_dce_v11_0_display_funcs = { +static const struct amdgpu_display_funcs dm_display_funcs = { .bandwidth_update = dm_bandwidth_update, /* called unconditionally */ .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */ .vblank_wait = NULL, @@ -1491,52 +1450,41 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; -#ifdef CONFIG_DRM_AMDGPU_CIK - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v8_0_display_funcs; -#endif break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v10_0_display_funcs; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; break; case CHIP_POLARIS11: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - if (adev->mode_info.funcs == NULL) - adev->mode_info.funcs = &dm_dce_v11_0_display_funcs; break; default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; } + if (adev->mode_info.funcs == NULL) + adev->mode_info.funcs = &dm_display_funcs; + /* Note: Do NOT change adev->audio_endpt_rreg and * adev->audio_endpt_wreg because they are initialised in * amdgpu_device_init() */ -- cgit v1.2.3 From 49c07a99b2bdd6e6ed621f728d58d8535cc87a61 Mon Sep 17 00:00:00 2001 From: Arindam Nath Date: Mon, 5 Dec 2016 19:21:26 +0530 Subject: drm/amd/display: remove DM_NOT_IMPL messages MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some functions like dm_bandwidth_update are placeholders for future implementations. Right now, they simply print messages like "DM_NOT_IMPL: dm_bandwidth_update". This message even though informational, sometimes can create some confusion for users. Since these functions are only skeletons for future, we simply remove the rather un-unecessary messages from these functions. Signed-off-by: Arindam Nath Reviewed-by: Christian König Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fa55147d0c47..396dbd661183 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -48,10 +48,6 @@ #include "modules/inc/mod_freesync.h" -/* Debug facilities */ -#define AMDGPU_DM_NOT_IMPL(fmt, ...) \ - DRM_INFO("DM_NOT_IMPL: " fmt, ##__VA_ARGS__) - /* * dm_vblank_get_counter * @@ -1269,20 +1265,18 @@ void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) */ static void dm_bandwidth_update(struct amdgpu_device *adev) { - AMDGPU_DM_NOT_IMPL("%s\n", __func__); + /* TODO: implement later */ } static void dm_set_backlight_level(struct amdgpu_encoder *amdgpu_encoder, u8 level) { /* TODO: translate amdgpu_encoder to display_index and call DAL */ - AMDGPU_DM_NOT_IMPL("%s\n", __func__); } static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder) { /* TODO: translate amdgpu_encoder to display_index and call DAL */ - AMDGPU_DM_NOT_IMPL("%s\n", __func__); return 0; } -- cgit v1.2.3 From 922aa1e15e03ee2b32f50cd8a9d2c8376a19d22c Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 7 Dec 2016 14:10:05 -0500 Subject: drm/amd/display: Fix refcount over dc_sink. Retain a dc_sink pointer until a new physical pointer arrives in case of new display connected. Signed-off-by: Andrey Grodzovsky Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 396dbd661183..e5ba23253814 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -737,9 +737,17 @@ void amdgpu_dm_update_connector_after_detect( mutex_lock(&dev->mode_config.mutex); if (sink) { - if (aconnector->dc_sink) + if (aconnector->dc_sink) { amdgpu_dm_remove_sink_from_freesync_module( connector); + /* retain and release bellow are used for + * bump up refcount for sink because the link don't point + * to it anymore after disconnect so on next crtc to connector + * reshuffle by UMD we will get into unwanted dc_sink release + */ + if (aconnector->dc_sink != aconnector->dc_em_sink) + dc_sink_release(aconnector->dc_sink); + } aconnector->dc_sink = sink; amdgpu_dm_add_sink_to_freesync_module( connector, aconnector->edid); @@ -747,6 +755,8 @@ void amdgpu_dm_update_connector_after_detect( amdgpu_dm_remove_sink_from_freesync_module(connector); if (!aconnector->dc_sink) aconnector->dc_sink = aconnector->dc_em_sink; + else if (aconnector->dc_sink != aconnector->dc_em_sink) + dc_sink_retain(aconnector->dc_sink); } mutex_unlock(&dev->mode_config.mutex); -- cgit v1.2.3 From b264d3455d9c8ce0bea422a04a867f0a724c7770 Mon Sep 17 00:00:00 2001 From: Jordan Lazare Date: Wed, 14 Dec 2016 15:35:13 -0500 Subject: drm/amd/dal: Add POLARIS12 support (v2) v2: agd: squash in dm fix, rebase Signed-off-by: Jordan Lazare Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 ++- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 3 ++- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 ++++- 4 files changed, 10 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e5ba23253814..2a7802c67eae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1235,6 +1235,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_STONEY: case CHIP_POLARIS11: case CHIP_POLARIS10: + case CHIP_POLARIS12: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); return -1; @@ -1472,6 +1473,7 @@ static int dm_early_init(void *handle) adev->mode_info.num_dig = 9; break; case CHIP_POLARIS11: + case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index f552b0468186..343114b2680f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -60,7 +60,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) break; } if (ASIC_REV_IS_POLARIS10_P(asic_id.hw_internal_rev) || - ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev)) { + ASIC_REV_IS_POLARIS11_M(asic_id.hw_internal_rev) || + ASIC_REV_IS_POLARIS12_V(asic_id.hw_internal_rev)) { dc_version = DCE_VERSION_11_2; } break; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 3a478300b848..85d8b31acd02 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1233,7 +1233,8 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc) const struct resource_caps *dce112_resource_cap( struct hw_asic_id *asic_id) { - if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev)) + if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || + ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) return &polaris_11_resource_cap; else return &polaris_10_resource_cap; diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 119297e3bdc0..46f1e88f5e27 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -85,6 +85,7 @@ /* DCE112 */ #define VI_POLARIS10_P_A0 80 #define VI_POLARIS11_M_A0 90 +#define VI_POLARIS12_V_A0 100 #define VI_UNKNOWN 0xFF @@ -95,7 +96,9 @@ #define ASIC_REV_IS_POLARIS10_P(eChipRev) ((eChipRev >= VI_POLARIS10_P_A0) && \ (eChipRev < VI_POLARIS11_M_A0)) -#define ASIC_REV_IS_POLARIS11_M(eChipRev) (eChipRev >= VI_POLARIS11_M_A0) +#define ASIC_REV_IS_POLARIS11_M(eChipRev) ((eChipRev >= VI_POLARIS11_M_A0) && \ + (eChipRev < VI_POLARIS12_V_A0)) +#define ASIC_REV_IS_POLARIS12_V(eChipRev) (eChipRev >= VI_POLARIS12_V_A0) /* DCE11 */ #define CZ_CARRIZO_A0 0x01 -- cgit v1.2.3 From 7abcf6b5043a94e850d8f38b625fd022492e8303 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 29 Dec 2016 13:21:31 -0500 Subject: drm/amd/display: [MST] Fix startup sequence v3. Problem: MST topology discovery was started before fbdev init causing kernel panic on boot. Fix: Defer MST to late init hook, after fbdev strucutres already initilized. v2: Add explicit late_init hook function in DAL. v3: Change signature of detect_mst_link_for_all_connectors from void* to drm_dev* Signed-off-by: Andrey Grodzovsky Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 ++++++++++++++--------- 1 file changed, 22 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2a7802c67eae..2af4ac0bffcb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -367,27 +367,39 @@ static int dm_sw_fini(void *handle) return 0; } -static void detect_link_for_all_connectors(struct drm_device *dev) +static int detect_mst_link_for_all_connectors(struct drm_device *dev) { struct amdgpu_connector *aconnector; struct drm_connector *connector; + int ret = 0; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { aconnector = to_amdgpu_connector(connector); - if (aconnector->dc_link->type == dc_connection_mst_branch) { - DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", - aconnector, aconnector->base.base.id); - - if (drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true) < 0) { - DRM_ERROR("DM_MST: Failed to start MST\n"); - ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; + if (aconnector->dc_link->type == dc_connection_mst_branch) { + DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", + aconnector, aconnector->base.base.id); + + ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); + if (ret < 0) { + DRM_ERROR("DM_MST: Failed to start MST\n"); + ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single; + return ret; } - } + } } drm_modeset_unlock(&dev->mode_config.connection_mutex); + return ret; +} + +static int dm_late_init(void *handle) +{ + struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev; + int r = detect_mst_link_for_all_connectors(dev); + + return r; } static void s3_handle_mst(struct drm_device *dev, bool suspend) @@ -417,11 +429,8 @@ static int dm_hw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* Create DAL display manager */ amdgpu_dm_init(adev); - amdgpu_dm_hpd_init(adev); - detect_link_for_all_connectors(adev->ddev); - return 0; } @@ -680,7 +689,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) static const struct amd_ip_funcs amdgpu_dm_funcs = { .name = "dm", .early_init = dm_early_init, - .late_init = NULL, + .late_init = dm_late_init, .sw_init = dm_sw_init, .sw_fini = dm_sw_fini, .hw_init = dm_hw_init, -- cgit v1.2.3 From ab2541b67395088b9de8ebf3943ef9ef86bccc41 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Thu, 29 Dec 2016 15:27:12 -0500 Subject: drm/amd/display: Remove dc_target object dc_target does not fit well into DRM framework so removed it. This will prevent the driver from leveraging the pipe-split code for tiled displays, so will have to be handled at a higher level. Most places that used dc_target now directly use dc_stream instead. Signed-off-by: Aric Cyr Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 6 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 47 ++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 349 +++++++--------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 292 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 437 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 183 +++++++++ drivers/gpu/drm/amd/display/dc/core/dc_target.c | 333 ---------------- drivers/gpu/drm/amd/display/dc/dc.h | 194 ++++----- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 - .../drm/amd/display/dc/dce100/dce100_resource.c | 89 ++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 8 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 103 +++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 144 ++++--- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 89 ++--- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 19 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 13 +- 20 files changed, 977 insertions(+), 1337 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/core/dc_target.c (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 3a3adfa16ada..0d92126b4c4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -428,8 +428,8 @@ struct amdgpu_crtc { int otg_inst; uint32_t flip_flags; - /* After Set Mode target will be non-NULL */ - struct dc_target *target; + /* After Set Mode stream will be non-NULL */ + const struct dc_stream *stream; }; struct amdgpu_encoder_atom_dig { @@ -550,7 +550,7 @@ struct amdgpu_connector { const struct dc_sink *dc_sink; const struct dc_link *dc_link; const struct dc_sink *dc_em_sink; - const struct dc_target *target; + const struct dc_stream *stream; void *con_priv; bool dac_load_detect; bool detected_by_load; /* if the connection status was determined by load */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2af4ac0bffcb..214cd38b8135 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -68,12 +68,12 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; - if (NULL == acrtc->target) { - DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + if (NULL == acrtc->stream) { + DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } - return dc_target_get_vblank_counter(acrtc->target); + return dc_stream_get_vblank_counter(acrtc->stream); } } @@ -85,12 +85,12 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; - if (NULL == acrtc->target) { - DRM_ERROR("dc_target is NULL for crtc '%d'!\n", crtc); + if (NULL == acrtc->stream) { + DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } - return dc_target_get_scanoutpos(acrtc->target, vbl, position); + return dc_stream_get_scanoutpos(acrtc->stream, vbl, position); } return 0; @@ -461,7 +461,7 @@ static int dm_suspend(void *handle) drm_modeset_lock_all(adev->ddev); list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) + if (acrtc->stream) drm_crtc_vblank_off(crtc); } drm_modeset_unlock_all(adev->ddev); @@ -655,7 +655,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) drm_modeset_lock_all(ddev); list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) + if (acrtc->stream) drm_crtc_vblank_on(crtc); } drm_modeset_unlock_all(ddev); @@ -740,7 +740,7 @@ void amdgpu_dm_update_connector_after_detect( if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && aconnector->dc_em_sink) { - /* For S3 resume with headless use eml_sink to fake target + /* For S3 resume with headless use eml_sink to fake stream * because on resume connecotr->sink is set ti NULL */ mutex_lock(&dev->mode_config.mutex); @@ -1184,7 +1184,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) return -1; } - for (i = 0; i < dm->dc->caps.max_targets; i++) { + for (i = 0; i < dm->dc->caps.max_streams; i++) { acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); if (!acrtc) goto fail; @@ -1199,7 +1199,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } } - dm->display_indexes_num = dm->dc->caps.max_targets; + dm->display_indexes_num = dm->dc->caps.max_streams; /* loops over all connectors on the board */ for (i = 0; i < link_cnt; i++) { @@ -1318,7 +1318,7 @@ static void dm_page_flip(struct amdgpu_device *adev, int crtc_id, u64 crtc_base, bool async) { struct amdgpu_crtc *acrtc; - struct dc_target *target; + const struct dc_stream *stream; struct dc_flip_addrs addr = { {0} }; /* @@ -1336,7 +1336,7 @@ static void dm_page_flip(struct amdgpu_device *adev, * a little longer to lock up all cores. * * The reason we should lock on dal_mutex is so that we can be sure - * nobody messes with acrtc->target after we read and check its value. + * nobody messes with acrtc->stream after we read and check its value. * * We might be able to fix our concurrency issues with a work queue * where we schedule all work items (mode_set, page_flip, etc.) and @@ -1345,14 +1345,14 @@ static void dm_page_flip(struct amdgpu_device *adev, */ acrtc = adev->mode_info.crtcs[crtc_id]; - target = acrtc->target; + stream = acrtc->stream; /* * Received a page flip call after the display has been reset. * Just return in this case. Everything should be clean-up on reset. */ - if (!target) { + if (!stream) { WARN_ON(1); return; } @@ -1368,7 +1368,7 @@ static void dm_page_flip(struct amdgpu_device *adev, dc_flip_surface_addrs( adev->dm.dc, - dc_target_get_status(target)->surfaces, + dc_stream_get_status(stream)->surfaces, &addr, 1); } @@ -1376,25 +1376,22 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, struct drm_file *filp) { struct mod_freesync_params freesync_params; - uint8_t num_targets; + uint8_t num_streams; uint8_t i; - struct dc_target *target; struct amdgpu_device *adev = dev->dev_private; int r = 0; /* Get freesync enable flag from DRM */ - num_targets = dc_get_current_target_count(adev->dm.dc); + num_streams = dc_get_current_stream_count(adev->dm.dc); - for (i = 0; i < num_targets; i++) { - - target = dc_get_target_at_index(adev->dm.dc, i); + for (i = 0; i < num_streams; i++) { + const struct dc_stream *stream; + stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, - target->streams, - target->stream_count, - &freesync_params); + &stream, 1, &freesync_params); } return r; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index e1b5f7d7b6da..c32fc6d26088 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -120,14 +120,14 @@ static void dm_set_cursor( position.x_hotspot = xorigin; position.y_hotspot = yorigin; - if (!dc_target_set_cursor_attributes( - amdgpu_crtc->target, + if (!dc_stream_set_cursor_attributes( + amdgpu_crtc->stream, &attributes)) { DRM_ERROR("DC failed to set cursor attributes\n"); } - if (!dc_target_set_cursor_position( - amdgpu_crtc->target, + if (!dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); } @@ -260,10 +260,10 @@ static int dm_crtc_cursor_set( position.y = 0; position.hot_spot_enable = false; - if (amdgpu_crtc->target) { + if (amdgpu_crtc->stream) { /*set cursor visible false*/ - dc_target_set_cursor_position( - amdgpu_crtc->target, + dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position); } /*unpin old cursor buffer and update cache*/ @@ -346,9 +346,9 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, position.x_hotspot = xorigin; position.y_hotspot = yorigin; - if (amdgpu_crtc->target) { - if (!dc_target_set_cursor_position( - amdgpu_crtc->target, + if (amdgpu_crtc->stream) { + if (!dc_stream_set_cursor_position( + amdgpu_crtc->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); return -EINVAL; @@ -367,7 +367,7 @@ static void dm_crtc_cursor_reset(struct drm_crtc *crtc) __func__, amdgpu_crtc->cursor_bo); - if (amdgpu_crtc->cursor_bo && amdgpu_crtc->target) { + if (amdgpu_crtc->cursor_bo && amdgpu_crtc->stream) { dm_set_cursor( amdgpu_crtc, amdgpu_crtc->cursor_addr, @@ -635,7 +635,7 @@ static void update_stream_scaling_settings( struct amdgpu_device *adev = dm_state->base.crtc->dev->dev_private; enum amdgpu_rmx_type rmx_type; - struct rect src = { 0 }; /* viewport in target space*/ + struct rect src = { 0 }; /* viewport in composition space*/ struct rect dst = { 0 }; /* stream addressable area */ /* Full screen scaling by default */ @@ -684,11 +684,11 @@ static void dm_dc_surface_commit( struct dc_surface *dc_surface; const struct dc_surface *dc_surfaces[1]; const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct dc_target *dc_target = acrtc->target; + const struct dc_stream *dc_stream = acrtc->stream; - if (!dc_target) { + if (!dc_stream) { dm_error( - "%s: Failed to obtain target on crtc (%d)!\n", + "%s: Failed to obtain stream on crtc (%d)!\n", __func__, acrtc->crtc_id); goto fail; @@ -712,11 +712,11 @@ static void dm_dc_surface_commit( dc_surfaces[0] = dc_surface; - if (false == dc_commit_surfaces_to_target( + if (false == dc_commit_surfaces_to_stream( dc, dc_surfaces, 1, - dc_target)) { + dc_stream)) { dm_error( "%s: Failed to attach surface!\n", __func__); @@ -957,15 +957,14 @@ static void decide_crtc_timing_for_drm_display_mode( } } -static struct dc_target *create_target_for_sink( +static struct dc_stream *create_stream_for_sink( const struct amdgpu_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; - struct dc_target *target = NULL; - struct dc_stream *stream; + struct dc_stream *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -1022,19 +1021,10 @@ static struct dc_target *create_target_for_sink( drm_connector, aconnector->dc_sink); - target = dc_create_target_for_streams(&stream, 1); - dc_stream_release(stream); - - if (NULL == target) { - DRM_ERROR("Failed to create target with streams!\n"); - goto target_create_fail; - } - +stream_create_fail: dm_state_null: drm_connector_null: -target_create_fail: -stream_create_fail: - return target; + return stream; } void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) @@ -1316,8 +1306,7 @@ int amdgpu_dm_connector_mode_valid( struct amdgpu_device *adev = connector->dev->dev_private; struct dc_validation_set val_set = { 0 }; /* TODO: Unhardcode stream count */ - struct dc_stream *streams[1]; - struct dc_target *target; + struct dc_stream *stream; struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || @@ -1335,39 +1324,31 @@ int amdgpu_dm_connector_mode_valid( if (NULL == dc_sink) { DRM_ERROR("dc_sink is NULL!\n"); - goto stream_create_fail; + goto null_sink; } - streams[0] = dc_create_stream_for_sink(dc_sink); - - if (NULL == streams[0]) { + stream = dc_create_stream_for_sink(dc_sink); + if (NULL == stream) { DRM_ERROR("Failed to create stream for sink!\n"); goto stream_create_fail; } drm_mode_set_crtcinfo(mode, 0); - fill_stream_properties_from_drm_display_mode(streams[0], mode, connector); - - target = dc_create_target_for_streams(streams, 1); - val_set.target = target; - - if (NULL == val_set.target) { - DRM_ERROR("Failed to create target with stream!\n"); - goto target_create_fail; - } + fill_stream_properties_from_drm_display_mode(stream, mode, connector); + val_set.stream = stream; val_set.surface_count = 0; - streams[0]->src.width = mode->hdisplay; - streams[0]->src.height = mode->vdisplay; - streams[0]->dst = streams[0]->src; + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; if (dc_validate_resources(adev->dm.dc, &val_set, 1)) result = MODE_OK; - dc_target_release(target); -target_create_fail: - dc_stream_release(streams[0]); + dc_stream_release(stream); + stream_create_fail: +null_sink: /* TODO: error handling*/ return result; } @@ -1562,15 +1543,14 @@ static void dm_plane_helper_cleanup_fb( } } -int dm_create_validation_set_for_target(struct drm_connector *connector, +int dm_create_validation_set_for_connector(struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set) { int result = MODE_ERROR; const struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ - struct dc_stream *streams[1]; - struct dc_target *target; + struct dc_stream *stream; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -1581,35 +1561,24 @@ int dm_create_validation_set_for_target(struct drm_connector *connector, return result; } - streams[0] = dc_create_stream_for_sink(dc_sink); + stream = dc_create_stream_for_sink(dc_sink); - if (NULL == streams[0]) { + if (NULL == stream) { DRM_ERROR("Failed to create stream for sink!\n"); return result; } drm_mode_set_crtcinfo(mode, 0); - fill_stream_properties_from_drm_display_mode(streams[0], mode, connector); + fill_stream_properties_from_drm_display_mode(stream, mode, connector); - target = dc_create_target_for_streams(streams, 1); - val_set->target = target; + val_set->stream = stream; - if (NULL == val_set->target) { - DRM_ERROR("Failed to create target with stream!\n"); - goto fail; - } - - streams[0]->src.width = mode->hdisplay; - streams[0]->src.height = mode->vdisplay; - streams[0]->dst = streams[0]->src; + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; return MODE_OK; - -fail: - dc_stream_release(streams[0]); - return result; - } static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { @@ -2262,23 +2231,21 @@ static bool is_scaling_state_different( return false; } -static void remove_target(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) +static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) { - int i; - /* * we evade vblanks and pflips on crtc that * should be changed */ manage_dm_interrupts(adev, acrtc, false); + /* this is the update mode case */ if (adev->dm.freesync_module) - for (i = 0; i < acrtc->target->stream_count; i++) - mod_freesync_remove_stream( - adev->dm.freesync_module, - acrtc->target->streams[i]); - dc_target_release(acrtc->target); - acrtc->target = NULL; + mod_freesync_remove_stream(adev->dm.freesync_module, + acrtc->stream); + + dc_stream_release(acrtc->stream); + acrtc->stream = NULL; acrtc->otg_inst = -1; acrtc->enabled = false; } @@ -2293,20 +2260,20 @@ int amdgpu_dm_atomic_commit( struct drm_plane *plane; struct drm_plane_state *new_plane_state; struct drm_plane_state *old_plane_state; - uint32_t i, j; + uint32_t i; int32_t ret = 0; - uint32_t commit_targets_count = 0; + uint32_t commit_streams_count = 0; uint32_t new_crtcs_count = 0; uint32_t flip_crtcs_count = 0; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; - struct dc_target *commit_targets[MAX_TARGETS]; - struct amdgpu_crtc *new_crtcs[MAX_TARGETS]; - struct dc_target *new_target; - struct drm_crtc *flip_crtcs[MAX_TARGETS]; - struct amdgpu_flip_work *work[MAX_TARGETS] = {0}; - struct amdgpu_bo *new_abo[MAX_TARGETS] = {0}; + const struct dc_stream *commit_streams[MAX_STREAMS]; + struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; + const struct dc_stream *new_stream; + struct drm_crtc *flip_crtcs[MAX_STREAMS]; + struct amdgpu_flip_work *work[MAX_STREAMS] = {0}; + struct amdgpu_bo *new_abo[MAX_STREAMS] = {0}; /* In this step all new fb would be pinned */ @@ -2422,19 +2389,19 @@ int amdgpu_dm_atomic_commit( case DM_COMMIT_ACTION_DPMS_ON: case DM_COMMIT_ACTION_SET: { struct dm_connector_state *dm_state = NULL; - new_target = NULL; + new_stream = NULL; if (aconnector) dm_state = to_dm_connector_state(aconnector->base.state); - new_target = create_target_for_sink( + new_stream = create_stream_for_sink( aconnector, &crtc->state->mode, dm_state); DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); - if (!new_target) { + if (!new_stream) { /* * this could happen because of issues with * userspace notifications delivery. @@ -2450,23 +2417,23 @@ int amdgpu_dm_atomic_commit( * have a sink to keep the pipe running so that * hw state is consistent with the sw state */ - DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n", + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - if (acrtc->target) - remove_target(adev, acrtc); + if (acrtc->stream) + remove_stream(adev, acrtc); /* * this loop saves set mode crtcs * we needed to enable vblanks once all - * resources acquired in dc after dc_commit_targets + * resources acquired in dc after dc_commit_streams */ new_crtcs[new_crtcs_count] = acrtc; new_crtcs_count++; - acrtc->target = new_target; + acrtc->stream = new_stream; acrtc->enabled = true; acrtc->hw_mode = crtc->state->mode; crtc->hwmode = crtc->state->mode; @@ -2483,10 +2450,8 @@ int amdgpu_dm_atomic_commit( dm_state = to_dm_connector_state(aconnector->base.state); /* Scaling update */ - update_stream_scaling_settings( - &crtc->state->mode, - dm_state, - acrtc->target->streams[0]); + update_stream_scaling_settings(&crtc->state->mode, + dm_state, acrtc->stream); break; } @@ -2494,8 +2459,8 @@ int amdgpu_dm_atomic_commit( case DM_COMMIT_ACTION_RESET: DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); /* i.e. reset mode */ - if (acrtc->target) - remove_target(adev, acrtc); + if (acrtc->stream) + remove_stream(adev, acrtc); break; } /* switch() */ } /* for_each_crtc_in_state() */ @@ -2504,20 +2469,20 @@ int amdgpu_dm_atomic_commit( struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - commit_targets[commit_targets_count] = acrtc->target; - ++commit_targets_count; + if (acrtc->stream) { + commit_streams[commit_streams_count] = acrtc->stream; + ++commit_streams_count; } } /* - * Add streams after required streams from new and replaced targets + * Add streams after required streams from new and replaced streams * are removed from freesync module */ if (adev->dm.freesync_module) { for (i = 0; i < new_crtcs_count; i++) { struct amdgpu_connector *aconnector = NULL; - new_target = new_crtcs[i]->target; + new_stream = new_crtcs[i]->stream; aconnector = amdgpu_dm_find_first_crct_matching_connector( state, @@ -2531,22 +2496,20 @@ int amdgpu_dm_atomic_commit( continue; } - for (j = 0; j < new_target->stream_count; j++) - mod_freesync_add_stream( - adev->dm.freesync_module, - new_target->streams[j], &aconnector->caps); + mod_freesync_add_stream(adev->dm.freesync_module, + new_stream, &aconnector->caps); } } - /* DC is optimized not to do anything if 'targets' didn't change. */ - dc_commit_targets(dm->dc, commit_targets, commit_targets_count); + /* DC is optimized not to do anything if 'streams' didn't change. */ + dc_commit_streams(dm->dc, commit_streams, commit_streams_count); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target != NULL) + if (acrtc->stream != NULL) acrtc->otg_inst = - dc_target_get_status(acrtc->target)->primary_otg_inst; + dc_stream_get_status(acrtc->stream)->primary_otg_inst; } /* update planes when needed */ @@ -2566,7 +2529,7 @@ int amdgpu_dm_atomic_commit( /* Surfaces are created under two scenarios: * 1. This commit is not a page flip. - * 2. This commit is a page flip, and targets are created. + * 2. This commit is a page flip, and streams are created. */ if (!page_flip_needed( plane_state, @@ -2618,13 +2581,9 @@ int amdgpu_dm_atomic_commit( */ struct amdgpu_crtc *acrtc = new_crtcs[i]; - if (adev->dm.freesync_module) { - for (j = 0; j < acrtc->target->stream_count; j++) - mod_freesync_notify_mode_change( - adev->dm.freesync_module, - acrtc->target->streams, - acrtc->target->stream_count); - } + if (adev->dm.freesync_module) + mod_freesync_notify_mode_change( + adev->dm.freesync_module, &acrtc->stream, 1); manage_dm_interrupts(adev, acrtc, true); dm_crtc_cursor_reset(&acrtc->base); @@ -2682,20 +2641,19 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); struct amdgpu_crtc *disconnected_acrtc; const struct dc_sink *sink; - struct dc_target *commit_targets[6]; - struct dc_target *current_target; - uint32_t commit_targets_count = 0; - int i; + const struct dc_stream *commit_streams[MAX_STREAMS]; + const struct dc_stream *current_stream; + uint32_t commit_streams_count = 0; if (!aconnector->dc_sink || !connector->state || !connector->encoder) return; disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); - if (!disconnected_acrtc || !disconnected_acrtc->target) + if (!disconnected_acrtc || !disconnected_acrtc->stream) return; - sink = disconnected_acrtc->target->streams[0]->sink; + sink = disconnected_acrtc->stream->sink; /* * If the previous sink is not released and different from the current, @@ -2706,8 +2664,8 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector struct dm_connector_state *dm_state = to_dm_connector_state(aconnector->base.state); - struct dc_target *new_target = - create_target_for_sink( + struct dc_stream *new_stream = + create_stream_for_sink( aconnector, &disconnected_acrtc->base.state->mode, dm_state); @@ -2720,56 +2678,51 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector manage_dm_interrupts(adev, disconnected_acrtc, false); /* this is the update mode case */ - current_target = disconnected_acrtc->target; + current_stream = disconnected_acrtc->stream; - disconnected_acrtc->target = new_target; + disconnected_acrtc->stream = new_stream; disconnected_acrtc->enabled = true; disconnected_acrtc->hw_mode = disconnected_acrtc->base.state->mode; - commit_targets_count = 0; + commit_streams_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - commit_targets[commit_targets_count] = acrtc->target; - ++commit_targets_count; + if (acrtc->stream) { + commit_streams[commit_streams_count] = acrtc->stream; + ++commit_streams_count; } } - /* DC is optimized not to do anything if 'targets' didn't change. */ - if (!dc_commit_targets(dc, commit_targets, - commit_targets_count)) { + /* DC is optimized not to do anything if 'streams' didn't change. */ + if (!dc_commit_streams(dc, commit_streams, + commit_streams_count)) { DRM_INFO("Failed to restore connector state!\n"); - dc_target_release(disconnected_acrtc->target); - disconnected_acrtc->target = current_target; + dc_stream_release(disconnected_acrtc->stream); + disconnected_acrtc->stream = current_stream; manage_dm_interrupts(adev, disconnected_acrtc, true); return; } if (adev->dm.freesync_module) { + mod_freesync_remove_stream(adev->dm.freesync_module, + current_stream); - for (i = 0; i < current_target->stream_count; i++) - mod_freesync_remove_stream( - adev->dm.freesync_module, - current_target->streams[i]); - - for (i = 0; i < new_target->stream_count; i++) - mod_freesync_add_stream( - adev->dm.freesync_module, - new_target->streams[i], - &aconnector->caps); + mod_freesync_add_stream(adev->dm.freesync_module, + new_stream, &aconnector->caps); } + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target != NULL) { + if (acrtc->stream != NULL) { acrtc->otg_inst = - dc_target_get_status(acrtc->target)->primary_otg_inst; + dc_stream_get_status(acrtc->stream)->primary_otg_inst; } } - dc_target_release(current_target); + dc_stream_release(current_stream); dm_dc_surface_commit(dc, &disconnected_acrtc->base); @@ -2782,13 +2735,13 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_target *target, + const struct dc_stream *stream, const struct dc_surface *surface) { uint32_t i = 0; while (i < set_count) { - if (val_sets[i].target == target) + if (val_sets[i].stream == stream) break; ++i; } @@ -2799,23 +2752,23 @@ static uint32_t add_val_sets_surface( return val_sets[i].surface_count; } -static uint32_t update_in_val_sets_target( +static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, struct drm_crtc **crtcs, uint32_t set_count, - const struct dc_target *old_target, - const struct dc_target *new_target, + const struct dc_stream *old_stream, + const struct dc_stream *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; while (i < set_count) { - if (val_sets[i].target == old_target) + if (val_sets[i].stream == old_stream) break; ++i; } - val_sets[i].target = new_target; + val_sets[i].stream = new_stream; crtcs[i] = crtc; if (i == set_count) { @@ -2829,12 +2782,12 @@ static uint32_t update_in_val_sets_target( static uint32_t remove_from_val_sets( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_target *target) + const struct dc_stream *stream) { int i; for (i = 0; i < set_count; i++) - if (val_sets[i].target == target) + if (val_sets[i].stream == stream) break; if (i == set_count) { @@ -2861,10 +2814,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, int i, j; int ret; int set_count; - int new_target_count; - struct dc_validation_set set[MAX_TARGETS] = {{ 0 }}; - struct dc_target *new_targets[MAX_TARGETS] = { 0 }; - struct drm_crtc *crtc_set[MAX_TARGETS] = { 0 }; + int new_stream_count; + struct dc_validation_set set[MAX_STREAMS] = {{ 0 }}; + struct dc_stream *new_streams[MAX_STREAMS] = { 0 }; + struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 }; struct amdgpu_device *adev = dev->dev_private; struct dc *dc = adev->dm.dc; bool need_to_validate = false; @@ -2880,14 +2833,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ret = -EINVAL; /* copy existing configuration */ - new_target_count = 0; + new_stream_count = 0; set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->target) { - set[set_count].target = acrtc->target; + if (acrtc->stream) { + set[set_count].stream = acrtc->stream; crtc_set[set_count] = crtc; ++set_count; } @@ -2908,7 +2861,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, switch (action) { case DM_COMMIT_ACTION_DPMS_ON: case DM_COMMIT_ACTION_SET: { - struct dc_target *new_target = NULL; + struct dc_stream *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_state = NULL; @@ -2919,30 +2872,30 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dm_state = to_dm_connector_state(conn_state); } - new_target = create_target_for_sink(aconnector, &crtc_state->mode, dm_state); + new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state); /* - * we can have no target on ACTION_SET if a display + * we can have no stream on ACTION_SET if a display * was disconnected during S3, in this case it not and * error, the OS will be updated after detection, and * do the right thing on next atomic commit */ - if (!new_target) { - DRM_DEBUG_KMS("%s: Failed to create new target for crtc %d\n", + if (!new_stream) { + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - new_targets[new_target_count] = new_target; - set_count = update_in_val_sets_target( + new_streams[new_stream_count] = new_stream; + set_count = update_in_val_sets_stream( set, crtc_set, set_count, - acrtc->target, - new_target, + acrtc->stream, + new_stream, crtc); - new_target_count++; + new_stream_count++; need_to_validate = true; break; } @@ -2952,7 +2905,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_state = NULL; struct dm_connector_state *old_dm_state = NULL; - struct dc_target *new_target; + struct dc_stream *new_stream; if (!aconnector) break; @@ -2970,24 +2923,24 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (!is_scaling_state_different(dm_state, old_dm_state)) break; - new_target = create_target_for_sink(aconnector, &crtc_state->mode, dm_state); + new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_state); - if (!new_target) { - DRM_ERROR("%s: Failed to create new target for crtc %d\n", + if (!new_stream) { + DRM_ERROR("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } - new_targets[new_target_count] = new_target; - set_count = update_in_val_sets_target( + new_streams[new_stream_count] = new_stream; + set_count = update_in_val_sets_stream( set, crtc_set, set_count, - acrtc->target, - new_target, + acrtc->stream, + new_stream, crtc); - new_target_count++; + new_stream_count++; need_to_validate = true; break; @@ -2995,11 +2948,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, case DM_COMMIT_ACTION_DPMS_OFF: case DM_COMMIT_ACTION_RESET: /* i.e. reset mode */ - if (acrtc->target) { + if (acrtc->stream) { set_count = remove_from_val_sets( set, set_count, - acrtc->target); + acrtc->stream); } break; } @@ -3035,7 +2988,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, /* Surfaces are created under two scenarios: * 1. This commit is not a page flip. - * 2. This commit is a page flip, and targets are created. + * 2. This commit is a page flip, and streams are created. */ crtc_state = drm_atomic_get_crtc_state(state, crtc); if (!page_flip_needed(plane_state, old_plane_state, @@ -3080,7 +3033,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, add_val_sets_surface( set, set_count, - set[i].target, + set[i].stream, surface); need_to_validate = true; @@ -3097,8 +3050,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dc_surface_release(set[i].surfaces[j]); } } - for (i = 0; i < new_target_count; i++) - dc_target_release(new_targets[i]); + for (i = 0; i < new_stream_count; i++) + dc_stream_release(new_streams[i]); if (ret != 0) DRM_ERROR("Atomic check failed.\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 4f7bd3bae44e..6ed1480a8bc3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -59,7 +59,7 @@ int amdgpu_dm_atomic_commit( int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); -int dm_create_validation_set_for_target( +int dm_create_validation_set_for_stream( struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set); diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 26e2b50e4954..2df163bc83e9 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -13,7 +13,7 @@ AMD_DC = $(addsuffix /Makefile, $(addprefix $(FULL_AMD_DISPLAY_PATH)/dc/,$(DC_LI include $(AMD_DC) -DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_target.o dc_sink.o \ +DISPLAY_CORE = dc.o dc_link.o dc_resource.o dc_hw_sequencer.o dc_sink.o \ dc_surface.o dc_link_hwss.o dc_link_dp.o dc_link_ddc.o dc_debug.o dc_stream.o AMD_DISPLAY_CORE = $(addprefix $(AMDDALPATH)/dc/core/,$(DISPLAY_CORE)) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a7348573ebca..7d4299b9ee1f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -49,15 +49,6 @@ #include "dm_helpers.h" #include "mem_input.h" -/******************************************************************************* - * Private structures - ******************************************************************************/ - -struct dc_target_sync_report { - uint32_t h_count; - uint32_t v_count; -}; - /******************************************************************************* * Private functions ******************************************************************************/ @@ -221,7 +212,7 @@ static void stream_update_scaling( struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(dc); struct validate_context *cur_ctx = core_dc->current_context; - int i, j; + int i; if (src) stream->public.src = *src; @@ -229,20 +220,18 @@ static void stream_update_scaling( if (dst) stream->public.dst = *dst; - for (i = 0; i < cur_ctx->target_count; i++) { - struct core_target *target = cur_ctx->targets[i]; - struct dc_target_status *status = &cur_ctx->target_status[i]; + for (i = 0; i < cur_ctx->stream_count; i++) { + struct core_stream *cur_stream = cur_ctx->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - if (target->public.streams[j] != dc_stream) - continue; + if (stream == cur_stream) { + struct dc_stream_status *status = &cur_ctx->stream_status[i]; if (status->surface_count) - if (!dc_commit_surfaces_to_target( + if (!dc_commit_surfaces_to_stream( &core_dc->public, status->surfaces, status->surface_count, - &target->public)) + &cur_stream->public)) /* Need to debug validation */ BREAK_TO_DEBUGGER(); @@ -634,7 +623,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) full_pipe_count = core_dc->res_pool->pipe_count; if (core_dc->res_pool->underlay_pipe_index >= 0) full_pipe_count--; - core_dc->public.caps.max_targets = min( + core_dc->public.caps.max_streams = min( full_pipe_count, core_dc->res_pool->stream_enc_count); @@ -675,20 +664,20 @@ static bool is_validation_required( const struct validate_context *context = dc->current_context; int i, j; - if (context->target_count != set_count) + if (context->stream_count != set_count) return true; for (i = 0; i < set_count; i++) { - if (set[i].surface_count != context->target_status[i].surface_count) + if (set[i].surface_count != context->stream_status[i].surface_count) return true; - if (!is_target_unchanged(DC_TARGET_TO_CORE(set[i].target), context->targets[i])) + if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) return true; for (j = 0; j < set[i].surface_count; j++) { struct dc_surface temp_surf = { 0 }; - temp_surf = *context->target_status[i].surfaces[j]; + temp_surf = *context->stream_status[i].surfaces[j]; temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; @@ -737,7 +726,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_target *dc_target) + const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -748,7 +737,7 @@ bool dc_validate_guaranteed( goto context_alloc_fail; result = core_dc->res_pool->funcs->validate_guaranteed( - core_dc, dc_target, context); + core_dc, stream, context); resource_validate_ctx_destruct(context); dm_free(context); @@ -838,18 +827,18 @@ static void program_timing_sync( } } -static bool targets_changed( +static bool streams_changed( struct core_dc *dc, - struct dc_target *targets[], - uint8_t target_count) + const struct dc_stream *streams[], + uint8_t stream_count) { uint8_t i; - if (target_count != dc->current_context->target_count) + if (stream_count != dc->current_context->stream_count) return true; - for (i = 0; i < dc->current_context->target_count; i++) { - if (&dc->current_context->targets[i]->public != targets[i]) + for (i = 0; i < dc->current_context->stream_count; i++) { + if (&dc->current_context->streams[i]->public != streams[i]) return true; } @@ -860,74 +849,72 @@ static void fill_display_configs( const struct validate_context *context, struct dm_pp_display_configuration *pp_display_cfg) { - uint8_t i, j, k; - uint8_t num_cfgs = 0; - - for (i = 0; i < context->target_count; i++) { - const struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - const struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct dm_pp_single_disp_config *cfg = - &pp_display_cfg->disp_configs[num_cfgs]; - const struct pipe_ctx *pipe_ctx = NULL; - - for (k = 0; k < MAX_PIPES; k++) - if (stream == - context->res_ctx.pipe_ctx[k].stream) { - pipe_ctx = &context->res_ctx.pipe_ctx[k]; - break; - } + int j; + int num_cfgs = 0; - ASSERT(pipe_ctx != NULL); - - num_cfgs++; - cfg->signal = pipe_ctx->stream->signal; - cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; - cfg->ddi_channel_mapping = - stream->sink->link->ddi_channel_mapping.raw; - cfg->transmitter = - stream->sink->link->link_enc->transmitter; - cfg->link_settings.lane_count = stream->sink->link->public.cur_link_settings.lane_count; - cfg->link_settings.link_rate = stream->sink->link->public.cur_link_settings.link_rate; - cfg->link_settings.link_spread = stream->sink->link->public.cur_link_settings.link_spread; - cfg->sym_clock = stream->phy_pix_clk; - /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; - } + for (j = 0; j < context->stream_count; j++) { + int k; + + const struct core_stream *stream = context->streams[j]; + struct dm_pp_single_disp_config *cfg = + &pp_display_cfg->disp_configs[num_cfgs]; + const struct pipe_ctx *pipe_ctx = NULL; + + for (k = 0; k < MAX_PIPES; k++) + if (stream == context->res_ctx.pipe_ctx[k].stream) { + pipe_ctx = &context->res_ctx.pipe_ctx[k]; + break; + } + + ASSERT(pipe_ctx != NULL); + + num_cfgs++; + cfg->signal = pipe_ctx->stream->signal; + cfg->pipe_idx = pipe_ctx->pipe_idx; + cfg->src_height = stream->public.src.height; + cfg->src_width = stream->public.src.width; + cfg->ddi_channel_mapping = + stream->sink->link->ddi_channel_mapping.raw; + cfg->transmitter = + stream->sink->link->link_enc->transmitter; + cfg->link_settings.lane_count = + stream->sink->link->public.cur_link_settings.lane_count; + cfg->link_settings.link_rate = + stream->sink->link->public.cur_link_settings.link_rate; + cfg->link_settings.link_spread = + stream->sink->link->public.cur_link_settings.link_spread; + cfg->sym_clock = stream->phy_pix_clk; + /* Round v_refresh*/ + cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->public.timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) + / stream->public.timing.v_total; } + pp_display_cfg->display_count = num_cfgs; } static uint32_t get_min_vblank_time_us(const struct validate_context *context) { - uint8_t i, j; + uint8_t j; uint32_t min_vertical_blank_time = -1; - for (i = 0; i < context->target_count; i++) { - const struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - const struct dc_stream *stream = - target->public.streams[j]; + for (j = 0; j < context->stream_count; j++) { + const struct dc_stream *stream = &context->streams[j]->public; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; vertical_blank_in_pixels = stream->timing.h_total * (stream->timing.v_total - stream->timing.v_addressable); + vertical_blank_time = vertical_blank_in_pixels * 1000 / stream->timing.pix_clk_khz; + if (min_vertical_blank_time > vertical_blank_time) min_vertical_blank_time = vertical_blank_time; } - } + return min_vertical_blank_time; } @@ -995,7 +982,7 @@ void pplib_apply_display_requirements( /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { const struct dc_crtc_timing *timing = - &context->targets[0]->public.streams[0]->timing; + &context->streams[0]->public.timing; pp_display_cfg->crtc_index = pp_display_cfg->disp_configs[0].pipe_idx; @@ -1011,34 +998,32 @@ void pplib_apply_display_requirements( } -bool dc_commit_targets( +bool dc_commit_streams( struct dc *dc, - struct dc_target *targets[], - uint8_t target_count) + const struct dc_stream *streams[], + uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_bios *dcb = core_dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; struct validate_context *context; - struct dc_validation_set set[MAX_TARGETS]; + struct dc_validation_set set[MAX_STREAMS]; int i, j, k; - if (false == targets_changed(core_dc, targets, target_count)) + if (false == streams_changed(core_dc, streams, stream_count)) return DC_OK; - dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: %d targets\n", - __func__, - target_count); + dm_logger_write(core_dc->ctx->logger, LOG_DC, "%s: %d streams\n", + __func__, stream_count); - for (i = 0; i < target_count; i++) { - struct dc_target *target = targets[i]; + for (i = 0; i < stream_count; i++) { + const struct dc_stream *stream = streams[i]; - dc_target_log(target, + dc_stream_log(stream, core_dc->ctx->logger, LOG_DC); - set[i].target = targets[i]; + set[i].stream = stream; set[i].surface_count = 0; } @@ -1047,7 +1032,7 @@ bool dc_commit_targets( if (context == NULL) goto context_alloc_fail; - result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, target_count, context); + result = core_dc->res_pool->funcs->validate_with_context(core_dc, set, stream_count, context); if (result != DC_OK){ dm_logger_write(core_dc->ctx->logger, LOG_ERROR, "%s: Context validation failed! dc_status:%d\n", @@ -1068,13 +1053,12 @@ bool dc_commit_targets( program_timing_sync(core_dc, context); - for (i = 0; i < context->target_count; i++) { - struct dc_target *dc_target = &context->targets[i]->public; - struct core_sink *sink = DC_SINK_TO_CORE(dc_target->streams[0]->sink); + for (i = 0; i < context->stream_count; i++) { + const struct core_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->target_status[i].surface_count; j++) { + for (j = 0; j < context->stream_status[i].surface_count; j++) { const struct dc_surface *dc_surface = - context->target_status[i].surfaces[j]; + context->stream_status[i].surfaces[j]; for (k = 0; k < context->res_ctx.pool->pipe_count; k++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[k]; @@ -1088,11 +1072,11 @@ bool dc_commit_targets( } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", - dc_target->streams[0]->timing.h_addressable, - dc_target->streams[0]->timing.v_addressable, - dc_target->streams[0]->timing.h_total, - dc_target->streams[0]->timing.v_total, - dc_target->streams[0]->timing.pix_clk_khz); + context->streams[i]->public.timing.h_addressable, + context->streams[i]->public.timing.v_addressable, + context->streams[i]->public.timing.h_total, + context->streams[i]->public.timing.v_total, + context->streams[i]->public.timing.pix_clk_khz); } pplib_apply_display_requirements(core_dc, @@ -1116,43 +1100,42 @@ context_alloc_fail: return (result == DC_OK); } -bool dc_pre_update_surfaces_to_target( +bool dc_pre_update_surfaces_to_stream( struct dc *dc, const struct dc_surface *const *new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i, j; struct core_dc *core_dc = DC_TO_CORE(dc); uint32_t prev_disp_clk = core_dc->current_context->bw_results.dispclk_khz; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct dc_target_status *target_status = NULL; + struct dc_stream_status *stream_status = NULL; struct validate_context *context; struct validate_context *temp_context; bool ret = true; pre_surface_trace(dc, new_surfaces, new_surface_count); - if (core_dc->current_context->target_count == 0) + if (core_dc->current_context->stream_count == 0) return false; - /* Cannot commit surface to a target that is not commited */ - for (i = 0; i < core_dc->current_context->target_count; i++) - if (target == core_dc->current_context->targets[i]) + /* Cannot commit surface to a stream that is not commited */ + for (i = 0; i < core_dc->current_context->stream_count; i++) + if (dc_stream == &core_dc->current_context->streams[i]->public) break; - if (i == core_dc->current_context->target_count) + if (i == core_dc->current_context->stream_count) return false; - target_status = &core_dc->current_context->target_status[i]; + stream_status = &core_dc->current_context->stream_status[i]; - if (new_surface_count == target_status->surface_count) { + if (new_surface_count == stream_status->surface_count) { bool skip_pre = true; - for (i = 0; i < target_status->surface_count; i++) { + for (i = 0; i < stream_status->surface_count; i++) { struct dc_surface temp_surf = { 0 }; - temp_surf = *target_status->surfaces[i]; + temp_surf = *stream_status->surfaces[i]; temp_surf.clip_rect = new_surfaces[i]->clip_rect; temp_surf.dst_rect.x = new_surfaces[i]->dst_rect.x; temp_surf.dst_rect.y = new_surfaces[i]->dst_rect.y; @@ -1178,13 +1161,13 @@ bool dc_pre_update_surfaces_to_target( resource_validate_ctx_copy_construct(core_dc->current_context, context); dm_logger_write(core_dc->ctx->logger, LOG_DC, - "%s: commit %d surfaces to target 0x%x\n", + "%s: commit %d surfaces to stream 0x%x\n", __func__, new_surface_count, - dc_target); + dc_stream); if (!resource_attach_surfaces_to_context( - new_surfaces, new_surface_count, dc_target, context)) { + new_surfaces, new_surface_count, dc_stream, context)) { BREAK_TO_DEBUGGER(); ret = false; goto unexpected_fail; @@ -1256,7 +1239,7 @@ val_ctx_fail: return ret; } -bool dc_post_update_surfaces_to_target(struct dc *dc) +bool dc_post_update_surfaces_to_stream(struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); int i; @@ -1282,22 +1265,27 @@ bool dc_post_update_surfaces_to_target(struct dc *dc) return true; } -bool dc_commit_surfaces_to_target( +bool dc_commit_surfaces_to_stream( struct dc *dc, const struct dc_surface **new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target) + const struct dc_stream *dc_stream) { - struct dc_surface_update updates[MAX_SURFACES] = { 0 }; - struct dc_flip_addrs flip_addr[MAX_SURFACES] = { 0 }; - struct dc_plane_info plane_info[MAX_SURFACES] = { 0 }; - struct dc_scaling_info scaling_info[MAX_SURFACES] = { 0 }; + struct dc_surface_update updates[MAX_SURFACES]; + struct dc_flip_addrs flip_addr[MAX_SURFACES]; + struct dc_plane_info plane_info[MAX_SURFACES]; + struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; - if (!dc_pre_update_surfaces_to_target( - dc, new_surfaces, new_surface_count, dc_target)) + if (!dc_pre_update_surfaces_to_stream( + dc, new_surfaces, new_surface_count, dc_stream)) return false; + memset(updates, 0, sizeof(updates)); + memset(flip_addr, 0, sizeof(flip_addr)); + memset(plane_info, 0, sizeof(plane_info)); + memset(scaling_info, 0, sizeof(scaling_info)); + for (i = 0; i < new_surface_count; i++) { updates[i].surface = new_surfaces[i]; updates[i].gamma = @@ -1321,13 +1309,13 @@ bool dc_commit_surfaces_to_target( updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_for_target(dc, updates, new_surface_count, dc_target); + dc_update_surfaces_for_stream(dc, updates, new_surface_count, dc_stream); - return dc_post_update_surfaces_to_target(dc); + return dc_post_update_surfaces_to_stream(dc); } -void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates, - int surface_count, struct dc_target *dc_target) +void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, + int surface_count, const struct dc_stream *dc_stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct validate_context *context = core_dc->temp_flip_context; @@ -1377,21 +1365,21 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda can_skip_context_building = false; } - if (!can_skip_context_building && dc_target) { - struct core_target *target = DC_TARGET_TO_CORE(dc_target); + if (!can_skip_context_building && dc_stream) { + const struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - if (core_dc->current_context->target_count == 0) + if (core_dc->current_context->stream_count == 0) return; - /* Cannot commit surface to a target that is not commited */ - for (i = 0; i < core_dc->current_context->target_count; i++) - if (target == core_dc->current_context->targets[i]) + /* Cannot commit surface to a stream that is not commited */ + for (i = 0; i < core_dc->current_context->stream_count; i++) + if (stream == core_dc->current_context->streams[i]) break; - if (i == core_dc->current_context->target_count) + if (i == core_dc->current_context->stream_count) return; if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_target, context)) { + new_surfaces, surface_count, dc_stream, context)) { BREAK_TO_DEBUGGER(); return; } @@ -1578,17 +1566,17 @@ void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *upda core_dc->current_context = context; } -uint8_t dc_get_current_target_count(const struct dc *dc) +uint8_t dc_get_current_stream_count(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - return core_dc->current_context->target_count; + return core_dc->current_context->stream_count; } -struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i) +struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); - if (i < core_dc->current_context->target_count) - return &(core_dc->current_context->targets[i]->public); + if (i < core_dc->current_context->stream_count) + return &(core_dc->current_context->streams[i]->public); return NULL; } @@ -1687,8 +1675,8 @@ void dc_set_power_state( core_dc->hwss.init_hw(core_dc); break; default: - /* NULL means "reset/release all DC targets" */ - dc_commit_targets(dc, NULL, 0); + /* NULL means "reset/release all DC streams" */ + dc_commit_streams(dc, NULL, 0); core_dc->hwss.power_down(core_dc); @@ -1882,11 +1870,3 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } -const struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream) -{ - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); - - return &stream->status; -} - diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 4bb6b1d9c970..1f87b948678b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -591,12 +591,12 @@ enum dc_status resource_build_scaling_params_for_context( return DC_OK; } -static void detach_surfaces_for_target( +static void detach_surfaces_for_stream( struct validate_context *context, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = 0; i < context->res_ctx.pool->pipe_count; i++) { struct pipe_ctx *cur_pipe = &context->res_ctx.pipe_ctx[i]; @@ -646,15 +646,15 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( } /* - * A free_pipe for a target is defined here as a pipe with a stream that belongs - * to the target but has no surface attached yet + * A free_pipe for a stream is defined here as a pipe + * that has no surface attached yet */ -static struct pipe_ctx *acquire_free_pipe_for_target( +static struct pipe_ctx *acquire_free_pipe_for_stream( struct resource_context *res_ctx, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -688,12 +688,12 @@ static struct pipe_ctx *acquire_free_pipe_for_target( } -static void release_free_pipes_for_target( +static void release_free_pipes_for_stream( struct resource_context *res_ctx, - const struct dc_target *dc_target) + const struct dc_stream *dc_stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_target->streams[0]); + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = res_ctx->pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && @@ -706,12 +706,12 @@ static void release_free_pipes_for_target( bool resource_attach_surfaces_to_context( const struct dc_surface * const *surfaces, int surface_count, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { int i; struct pipe_ctx *tail_pipe; - struct dc_target_status *target_status = NULL; + struct dc_stream_status *stream_status = NULL; if (surface_count > MAX_SURFACE_NUM) { @@ -720,13 +720,13 @@ bool resource_attach_surfaces_to_context( return false; } - for (i = 0; i < context->target_count; i++) - if (&context->targets[i]->public == dc_target) { - target_status = &context->target_status[i]; + for (i = 0; i < context->stream_count; i++) + if (&context->streams[i]->public == dc_stream) { + stream_status = &context->stream_status[i]; break; } - if (target_status == NULL) { - dm_error("Existing target not found; failed to attach surfaces\n"); + if (stream_status == NULL) { + dm_error("Existing stream not found; failed to attach surfaces\n"); return false; } @@ -734,16 +734,16 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) dc_surface_retain(surfaces[i]); - detach_surfaces_for_target(context, dc_target); + detach_surfaces_for_stream(context, dc_stream); /* release existing surfaces*/ - for (i = 0; i < target_status->surface_count; i++) - dc_surface_release(target_status->surfaces[i]); + for (i = 0; i < stream_status->surface_count; i++) + dc_surface_release(stream_status->surfaces[i]); - for (i = surface_count; i < target_status->surface_count; i++) - target_status->surfaces[i] = NULL; + for (i = surface_count; i < stream_status->surface_count; i++) + stream_status->surfaces[i] = NULL; - target_status->surface_count = 0; + stream_status->surface_count = 0; if (surface_count == 0) return true; @@ -751,11 +751,11 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { struct core_surface *surface = DC_SURFACE_TO_CORE(surfaces[i]); - struct pipe_ctx *free_pipe = acquire_free_pipe_for_target( - &context->res_ctx, dc_target); + struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( + &context->res_ctx, dc_stream); if (!free_pipe) { - target_status->surfaces[i] = NULL; + stream_status->surfaces[i] = NULL; return false; } @@ -769,13 +769,13 @@ bool resource_attach_surfaces_to_context( tail_pipe = free_pipe; } - release_free_pipes_for_target(&context->res_ctx, dc_target); + release_free_pipes_for_stream(&context->res_ctx, dc_stream); /* assign new surfaces*/ for (i = 0; i < surface_count; i++) - target_status->surfaces[i] = surfaces[i]; + stream_status->surfaces[i] = surfaces[i]; - target_status->surface_count = surface_count; + stream_status->surface_count = surface_count; return true; } @@ -819,25 +819,14 @@ static bool are_stream_backends_same( return true; } -bool is_target_unchanged( - const struct core_target *old_target, const struct core_target *target) +bool is_stream_unchanged( + const struct core_stream *old_stream, const struct core_stream *stream) { - int i; - - if (old_target == target) + if (old_stream == stream) return true; - if (old_target->public.stream_count != target->public.stream_count) - return false; - - for (i = 0; i < old_target->public.stream_count; i++) { - const struct core_stream *old_stream = DC_STREAM_TO_CORE( - old_target->public.streams[i]); - const struct core_stream *stream = DC_STREAM_TO_CORE( - target->public.streams[i]); - if (!are_stream_backends_same(old_stream, stream)) - return false; - } + if (!are_stream_backends_same(old_stream, stream)) + return false; return true; } @@ -851,23 +840,23 @@ bool resource_validate_attach_surfaces( int i, j; for (i = 0; i < set_count; i++) { - for (j = 0; j < old_context->target_count; j++) - if (is_target_unchanged( - old_context->targets[j], - context->targets[i])) { + for (j = 0; j < old_context->stream_count; j++) + if (is_stream_unchanged( + old_context->streams[j], + context->streams[i])) { if (!resource_attach_surfaces_to_context( - old_context->target_status[j].surfaces, - old_context->target_status[j].surface_count, - &context->targets[i]->public, + old_context->stream_status[j].surfaces, + old_context->stream_status[j].surface_count, + &context->streams[i]->public, context)) return false; - context->target_status[i] = old_context->target_status[j]; + context->stream_status[i] = old_context->stream_status[j]; } if (set[i].surface_count != 0) if (!resource_attach_surfaces_to_context( set[i].surfaces, set[i].surface_count, - &context->targets[i]->public, + &context->streams[i]->public, context)) return false; @@ -1001,20 +990,15 @@ static void update_stream_signal(struct core_stream *stream) } bool resource_is_stream_unchanged( - const struct validate_context *old_context, struct core_stream *stream) + const struct validate_context *old_context, const struct core_stream *stream) { - int i, j; - - for (i = 0; i < old_context->target_count; i++) { - struct core_target *old_target = old_context->targets[i]; + int i; - for (j = 0; j < old_target->public.stream_count; j++) { - struct core_stream *old_stream = - DC_STREAM_TO_CORE(old_target->public.streams[j]); + for (i = 0; i < old_context->stream_count; i++) { + const struct core_stream *old_stream = old_context->streams[i]; - if (are_stream_backends_same(old_stream, stream)) + if (are_stream_backends_same(old_stream, stream)) return true; - } } return false; @@ -1036,23 +1020,19 @@ static struct core_stream *find_pll_sharable_stream( const struct core_stream *stream_needs_pll, struct validate_context *context) { - int i, j; + int i; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream_has_pll = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream_has_pll = - DC_STREAM_TO_CORE(target->public.streams[j]); + /* We are looking for non dp, non virtual stream */ + if (resource_are_streams_timing_synchronizable( + stream_needs_pll, stream_has_pll) + && !dc_is_dp_signal(stream_has_pll->signal) + && stream_has_pll->sink->link->public.connector_signal + != SIGNAL_TYPE_VIRTUAL) + return stream_has_pll; - /* We are looking for non dp, non virtual stream */ - if (resource_are_streams_timing_synchronizable( - stream_needs_pll, stream_has_pll) - && !dc_is_dp_signal(stream_has_pll->signal) - && stream_has_pll->sink->link->public.connector_signal - != SIGNAL_TYPE_VIRTUAL) - return stream_has_pll; - } } return NULL; @@ -1091,25 +1071,20 @@ static void calculate_phy_pix_clks( const struct core_dc *dc, struct validate_context *context) { - int i, j; - - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + int i; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - update_stream_signal(stream); + update_stream_signal(stream); - /* update actual pixel clock on all streams */ - if (dc_is_hdmi_signal(stream->signal)) - stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); - else - stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; - } + /* update actual pixel clock on all streams */ + if (dc_is_hdmi_signal(stream->signal)) + stream->phy_pix_clk = get_norm_pix_clk( + &stream->public.timing); + else + stream->phy_pix_clk = + stream->public.timing.pix_clk_khz; } } @@ -1117,136 +1092,122 @@ enum dc_status resource_map_pool_resources( const struct core_dc *dc, struct validate_context *context) { - int i, j, k; + int i, j; calculate_phy_pix_clks(dc, context); - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - - if (!resource_is_stream_unchanged(dc->current_context, stream)) - continue; - - /* mark resources used for stream that is already active */ - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; - const struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[k]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) - continue; + if (!resource_is_stream_unchanged(dc->current_context, stream)) + continue; - pipe_ctx->stream = stream; - copy_pipe_ctx(old_pipe_ctx, pipe_ctx); + /* mark resources used for stream that is already active */ + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; + const struct pipe_ctx *old_pipe_ctx = + &dc->current_context->res_ctx.pipe_ctx[j]; - /* Split pipe resource, do not acquire back end */ - if (!pipe_ctx->stream_enc) - continue; + if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) + continue; - set_stream_engine_in_use( - &context->res_ctx, - pipe_ctx->stream_enc); - - /* Switch to dp clock source only if there is - * no non dp stream that shares the same timing - * with the dp stream. - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - !find_pll_sharable_stream(stream, context)) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; + pipe_ctx->stream = stream; + copy_pipe_ctx(old_pipe_ctx, pipe_ctx); - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + /* Split pipe resource, do not acquire back end */ + if (!pipe_ctx->stream_enc) + continue; - set_audio_in_use(&context->res_ctx, - pipe_ctx->audio); - } + set_stream_engine_in_use( + &context->res_ctx, + pipe_ctx->stream_enc); + + /* Switch to dp clock source only if there is + * no non dp stream that shares the same timing + * with the dp stream. + */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && + !find_pll_sharable_stream(stream, context)) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); + + set_audio_in_use(&context->res_ctx, + pipe_ctx->audio); } } - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; - - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct pipe_ctx *pipe_ctx = NULL; - int pipe_idx = -1; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; - /* acquire new resources */ - pipe_idx = acquire_first_free_pipe( - &context->res_ctx, stream); - if (pipe_idx < 0) - return DC_NO_CONTROLLER_RESOURCE; - - - pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct pipe_ctx *pipe_ctx = NULL; + int pipe_idx = -1; - pipe_ctx->stream_enc = - find_first_free_match_stream_enc_for_link( - &context->res_ctx, stream); - - if (!pipe_ctx->stream_enc) - return DC_NO_STREAM_ENG_RESOURCE; - - set_stream_engine_in_use( + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; + /* acquire new resources */ + pipe_idx = acquire_first_free_pipe(&context->res_ctx, stream); + if (pipe_idx < 0) + return DC_NO_CONTROLLER_RESOURCE; + + + pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + + pipe_ctx->stream_enc = + find_first_free_match_stream_enc_for_link( + &context->res_ctx, stream); + + if (!pipe_ctx->stream_enc) + return DC_NO_STREAM_ENG_RESOURCE; + + set_stream_engine_in_use( + &context->res_ctx, + pipe_ctx->stream_enc); + + /* TODO: Add check if ASIC support and EDID audio */ + if (!stream->sink->converter_disable_audio && + dc_is_audio_capable_signal(pipe_ctx->stream->signal) && + stream->public.audio_info.mode_count) { + pipe_ctx->audio = find_first_free_audio( + &context->res_ctx); + + /* + * Audio assigned in order first come first get. + * There are asics which has number of audio + * resources less then number of pipes + */ + if (pipe_ctx->audio) + set_audio_in_use( &context->res_ctx, - pipe_ctx->stream_enc); - - /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->converter_disable_audio && - dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->public.audio_info.mode_count) { - pipe_ctx->audio = find_first_free_audio( - &context->res_ctx); - - /* - * Audio assigned in order first come first get. - * There are asics which has number of audio - * resources less then number of pipes - */ - if (pipe_ctx->audio) - set_audio_in_use( - &context->res_ctx, - pipe_ctx->audio); - } - - if (j == 0) { - context->target_status[i].primary_otg_inst = - pipe_ctx->tg->inst; - } + pipe_ctx->audio); } + + context->stream_status[i].primary_otg_inst = pipe_ctx->tg->inst; } return DC_OK; } -/* first target in the context is used to populate the rest */ -void validate_guaranteed_copy_target( +/* first stream in the context is used to populate the rest */ +void validate_guaranteed_copy_streams( struct validate_context *context, - int max_targets) + int max_streams) { int i; - for (i = 1; i < max_targets; i++) { - context->targets[i] = context->targets[0]; + for (i = 1; i < max_streams; i++) { + context->streams[i] = context->streams[0]; copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], &context->res_ctx.pipe_ctx[i]); context->res_ctx.pipe_ctx[i].stream = context->res_ctx.pipe_ctx[0].stream; - dc_target_retain(&context->targets[i]->public); - context->target_count++; + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } } @@ -1875,18 +1836,19 @@ void resource_validate_ctx_destruct(struct validate_context *context) { int i, j; - for (i = 0; i < context->target_count; i++) { - for (j = 0; j < context->target_status[i].surface_count; j++) + for (i = 0; i < context->stream_count; i++) { + for (j = 0; j < context->stream_status[i].surface_count; j++) dc_surface_release( - context->target_status[i].surfaces[j]); + context->stream_status[i].surfaces[j]); - context->target_status[i].surface_count = 0; - dc_target_release(&context->targets[i]->public); + context->stream_status[i].surface_count = 0; + dc_stream_release(&context->streams[i]->public); + context->streams[i] = NULL; } } /* - * Copy src_ctx into dst_ctx and retain all surfaces and targets referenced + * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced * by the src_ctx */ void resource_validate_ctx_copy_construct( @@ -1908,11 +1870,11 @@ void resource_validate_ctx_copy_construct( } - for (i = 0; i < dst_ctx->target_count; i++) { - dc_target_retain(&dst_ctx->targets[i]->public); - for (j = 0; j < dst_ctx->target_status[i].surface_count; j++) + for (i = 0; i < dst_ctx->stream_count; i++) { + dc_stream_retain(&dst_ctx->streams[i]->public); + for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) dc_surface_retain( - dst_ctx->target_status[i].surfaces[j]); + dst_ctx->stream_status[i].surfaces[j]); } } @@ -1968,53 +1930,48 @@ enum dc_status resource_map_clock_resources( const struct core_dc *dc, struct validate_context *context) { - int i, j, k; + int i, j; /* acquire new resources */ - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + const struct core_stream *stream = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; + + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (resource_is_stream_unchanged(dc->current_context, stream)) + if (context->res_ctx.pipe_ctx[j].stream != stream) continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + else { + pipe_ctx->clock_source = NULL; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (!dc->public.config.disable_disp_pll_sharing) + resource_find_used_clk_src_for_sharing( + &context->res_ctx, + pipe_ctx); - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + if (pipe_ctx->clock_source == NULL) pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; - else { - pipe_ctx->clock_source = NULL; - - if (!dc->public.config.disable_disp_pll_sharing) - resource_find_used_clk_src_for_sharing( - &context->res_ctx, - pipe_ctx); - - if (pipe_ctx->clock_source == NULL) - pipe_ctx->clock_source = - dc_resource_find_first_free_pll(&context->res_ctx); - } + dc_resource_find_first_free_pll(&context->res_ctx); + } - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); - /* only one cs per stream regardless of mpo */ - break; - } + /* only one cs per stream regardless of mpo */ + break; } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index cda67a78dbfd..bc1f387d1992 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -27,6 +27,8 @@ #include "dc.h" #include "core_types.h" #include "resource.h" +#include "ipp.h" +#include "timing_generator.h" /******************************************************************************* * Private definitions @@ -146,3 +148,184 @@ construct_fail: alloc_fail: return NULL; } + +const struct dc_stream_status *dc_stream_get_status( + const struct dc_stream *dc_stream) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); + + for (i = 0; i < dc->current_context->stream_count; i++) + if (stream == dc->current_context->streams[i]) + return &dc->current_context->stream_status[i]; + + return NULL; +} + +/** + * Update the cursor attributes and set cursor surface address + */ +bool dc_stream_set_cursor_attributes( + const struct dc_stream *dc_stream, + const struct dc_cursor_attributes *attributes) +{ + int i; + struct core_stream *stream; + struct core_dc *core_dc; + struct resource_context *res_ctx; + bool ret = false; + + if (NULL == dc_stream) { + dm_error("DC: dc_stream is NULL!\n"); + return false; + } + if (NULL == attributes) { + dm_error("DC: attributes is NULL!\n"); + return false; + } + + stream = DC_STREAM_TO_CORE(dc_stream); + core_dc = DC_TO_CORE(stream->ctx->dc); + res_ctx = &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + + if (ipp->funcs->ipp_cursor_set_attributes( + ipp, attributes)) + ret = true; + } + } + + return ret; +} + +bool dc_stream_set_cursor_position( + const struct dc_stream *dc_stream, + const struct dc_cursor_position *position) +{ + int i; + struct core_stream *stream; + struct core_dc *core_dc; + struct resource_context *res_ctx; + bool ret = false; + + if (NULL == dc_stream) { + dm_error("DC: dc_stream is NULL!\n"); + return false; + } + + if (NULL == position) { + dm_error("DC: cursor position is NULL!\n"); + return false; + } + + stream = DC_STREAM_TO_CORE(dc_stream); + core_dc = DC_TO_CORE(stream->ctx->dc); + res_ctx = &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; + + if (pipe_ctx->stream == stream) { + struct input_pixel_processor *ipp = pipe_ctx->ipp; + struct dc_cursor_mi_param param = { + .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .ref_clk_khz = 48000,/*todo refclk*/ + .viewport_x_start = pipe_ctx->scl_data.viewport.x, + .viewport_width = pipe_ctx->scl_data.viewport.width, + .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, + }; + + ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); + ret = true; + } + } + + return ret; +} + +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = + &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + + if (res_ctx->pipe_ctx[i].stream != stream) + continue; + + return tg->funcs->get_frame_count(tg); + } + + return 0; +} + +uint32_t dc_stream_get_scanoutpos( + const struct dc_stream *dc_stream, + uint32_t *vbl, + uint32_t *position) +{ + uint8_t i; + struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); + struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); + struct resource_context *res_ctx = + &core_dc->current_context->res_ctx; + + for (i = 0; i < MAX_PIPES; i++) { + struct timing_generator *tg = res_ctx->pipe_ctx[i].tg; + + if (res_ctx->pipe_ctx[i].stream != stream) + continue; + + return tg->funcs->get_scanoutpos(tg, vbl, position); + } + + return 0; +} + + +void dc_stream_log( + const struct dc_stream *stream, + struct dal_logger *dm_logger, + enum dc_log_type log_type) +{ + const struct core_stream *core_stream = + DC_STREAM_TO_CORE(stream); + + dm_logger_write(dm_logger, + log_type, + "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n", + core_stream, + core_stream->public.src.x, + core_stream->public.src.y, + core_stream->public.src.width, + core_stream->public.src.height, + core_stream->public.dst.x, + core_stream->public.dst.y, + core_stream->public.dst.width, + core_stream->public.dst.height); + dm_logger_write(dm_logger, + log_type, + "\tpix_clk_khz: %d, h_total: %d, v_total: %d\n", + core_stream->public.timing.pix_clk_khz, + core_stream->public.timing.h_total, + core_stream->public.timing.v_total); + dm_logger_write(dm_logger, + log_type, + "\tsink name: %s, serial: %d\n", + core_stream->sink->public.edid_caps.display_name, + core_stream->sink->public.edid_caps.serial_number); + dm_logger_write(dm_logger, + log_type, + "\tlink: %d\n", + core_stream->sink->link->public.link_index); +} diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_target.c b/drivers/gpu/drm/amd/display/dc/core/dc_target.c deleted file mode 100644 index 2d25b00b4bff..000000000000 --- a/drivers/gpu/drm/amd/display/dc/core/dc_target.c +++ /dev/null @@ -1,333 +0,0 @@ -/* - * Copyright 2012-15 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include "dm_services.h" -#include "core_types.h" -#include "hw_sequencer.h" -#include "resource.h" -#include "ipp.h" -#include "timing_generator.h" - -struct target { - struct core_target protected; - int ref_count; -}; - -#define DC_TARGET_TO_TARGET(dc_target) \ - container_of(dc_target, struct target, protected.public) -#define CORE_TARGET_TO_TARGET(core_target) \ - container_of(core_target, struct target, protected) - -static void construct( - struct core_target *target, - struct dc_context *ctx, - struct dc_stream *dc_streams[], - uint8_t stream_count) -{ - uint8_t i; - for (i = 0; i < stream_count; i++) { - target->public.streams[i] = dc_streams[i]; - dc_stream_retain(dc_streams[i]); - } - - target->ctx = ctx; - target->public.stream_count = stream_count; -} - -static void destruct(struct core_target *core_target) -{ - int i; - - for (i = 0; i < core_target->public.stream_count; i++) { - dc_stream_release( - (struct dc_stream *)core_target->public.streams[i]); - core_target->public.streams[i] = NULL; - } -} - -void dc_target_retain(const struct dc_target *dc_target) -{ - struct target *target = DC_TARGET_TO_TARGET(dc_target); - - ASSERT(target->ref_count > 0); - target->ref_count++; -} - -void dc_target_release(const struct dc_target *dc_target) -{ - struct target *target = DC_TARGET_TO_TARGET(dc_target); - struct core_target *protected = DC_TARGET_TO_CORE(dc_target); - - ASSERT(target->ref_count > 0); - target->ref_count--; - - if (target->ref_count == 0) { - destruct(protected); - dm_free(target); - } -} - -const struct dc_target_status *dc_target_get_status( - const struct dc_target* dc_target) -{ - uint8_t i; - struct core_target* target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *dc = DC_TO_CORE(target->ctx->dc); - - for (i = 0; i < dc->current_context->target_count; i++) - if (target == dc->current_context->targets[i]) - return &dc->current_context->target_status[i]; - - return NULL; -} - -struct dc_target *dc_create_target_for_streams( - struct dc_stream *dc_streams[], - uint8_t stream_count) -{ - struct core_stream *stream; - struct target *target; - - if (0 == stream_count) - goto target_alloc_fail; - - stream = DC_STREAM_TO_CORE(dc_streams[0]); - - target = dm_alloc(sizeof(struct target)); - - if (NULL == target) - goto target_alloc_fail; - - construct(&target->protected, stream->ctx, dc_streams, stream_count); - - target->ref_count++; - - return &target->protected.public; - -target_alloc_fail: - return NULL; -} - -bool dc_target_is_connected_to_sink( - const struct dc_target * dc_target, - const struct dc_sink *dc_sink) -{ - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - uint8_t i; - for (i = 0; i < target->public.stream_count; i++) { - if (target->public.streams[i]->sink == dc_sink) - return true; - } - return false; -} - -/** - * Update the cursor attributes and set cursor surface address - */ -bool dc_target_set_cursor_attributes( - struct dc_target *dc_target, - const struct dc_cursor_attributes *attributes) -{ - int i, j; - struct core_target *target; - struct core_dc *core_dc; - struct resource_context *res_ctx; - bool ret = false; - - if (NULL == dc_target) { - dm_error("DC: dc_target is NULL!\n"); - return false; - } - if (NULL == attributes) { - dm_error("DC: attributes is NULL!\n"); - return false; - } - - target = DC_TARGET_TO_CORE(dc_target); - core_dc = DC_TO_CORE(target->ctx->dc); - res_ctx = &core_dc->current_context->res_ctx; - - for (i = 0; i < dc_target->stream_count; i++) { - const struct dc_stream *stream = dc_target->streams[i]; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; - - if (&pipe_ctx->stream->public == stream) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; - - if (ipp->funcs->ipp_cursor_set_attributes( - ipp, attributes)) - ret = true; - } - } - } - - return ret; -} - -bool dc_target_set_cursor_position( - struct dc_target *dc_target, - const struct dc_cursor_position *position) -{ - int i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = &core_dc->current_context->res_ctx; - bool ret = false; - - if (NULL == dc_target) { - dm_error("DC: dc_target is NULL!\n"); - return false; - } - - if (NULL == position) { - dm_error("DC: cursor position is NULL!\n"); - return false; - } - - for (i = 0; i < dc_target->stream_count; i++) { - const struct dc_stream *stream = dc_target->streams[i]; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[j]; - - if (&pipe_ctx->stream->public == stream) { - struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_cursor_mi_param param = { - .pixel_clk_khz = stream->timing.pix_clk_khz, - .ref_clk_khz = 48000,/*todo refclk*/ - .viewport_x_start = pipe_ctx->scl_data.viewport.x, - .viewport_width = pipe_ctx->scl_data.viewport.width, - .h_scale_ratio = pipe_ctx->scl_data.ratios.horz, - }; - - ipp->funcs->ipp_cursor_set_position(ipp, position, ¶m); - ret = true; - } - } - } - - return ret; -} - -uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target) -{ - uint8_t i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - - for (i = 0; i < target->public.stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - struct timing_generator *tg = res_ctx->pipe_ctx[j].tg; - - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; - - return tg->funcs->get_frame_count(tg); - } - } - - return 0; -} - -uint32_t dc_target_get_scanoutpos( - const struct dc_target *dc_target, - uint32_t *vbl, - uint32_t *position) -{ - uint8_t i, j; - struct core_target *target = DC_TARGET_TO_CORE(dc_target); - struct core_dc *core_dc = DC_TO_CORE(target->ctx->dc); - struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; - - for (i = 0; i < target->public.stream_count; i++) { - for (j = 0; j < MAX_PIPES; j++) { - struct timing_generator *tg = res_ctx->pipe_ctx[j].tg; - - if (res_ctx->pipe_ctx[j].stream != - DC_STREAM_TO_CORE(target->public.streams[i])) - continue; - - return tg->funcs->get_scanoutpos(tg, vbl, position); - } - } - - return 0; -} - -void dc_target_log( - const struct dc_target *dc_target, - struct dal_logger *dm_logger, - enum dc_log_type log_type) -{ - int i; - - const struct core_target *core_target = - CONST_DC_TARGET_TO_CORE(dc_target); - - dm_logger_write(dm_logger, - log_type, - "core_target 0x%x: stream_count=%d\n", - core_target, - core_target->public.stream_count); - - for (i = 0; i < core_target->public.stream_count; i++) { - const struct core_stream *core_stream = - DC_STREAM_TO_CORE(core_target->public.streams[i]); - - dm_logger_write(dm_logger, - log_type, - "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d;\n", - core_stream, - core_stream->public.src.x, - core_stream->public.src.y, - core_stream->public.src.width, - core_stream->public.src.height, - core_stream->public.dst.x, - core_stream->public.dst.y, - core_stream->public.dst.width, - core_stream->public.dst.height); - dm_logger_write(dm_logger, - log_type, - "\tpix_clk_khz: %d, h_total: %d, v_total: %d\n", - core_stream->public.timing.pix_clk_khz, - core_stream->public.timing.h_total, - core_stream->public.timing.v_total); - dm_logger_write(dm_logger, - log_type, - "\tsink name: %s, serial: %d\n", - core_stream->sink->public.edid_caps.display_name, - core_stream->sink->public.edid_caps.serial_number); - dm_logger_write(dm_logger, - log_type, - "\tlink: %d\n", - core_stream->sink->link->public.link_index); - } -} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e8cb7a4dee80..b814e7b76bbc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -32,8 +32,8 @@ #include "gpio_types.h" #include "link_service_types.h" -#define MAX_TARGETS 6 #define MAX_SURFACES 3 +#define MAX_STREAMS 6 #define MAX_SINKS_PER_LINK 4 /******************************************************************************* @@ -41,7 +41,7 @@ ******************************************************************************/ struct dc_caps { - uint32_t max_targets; + uint32_t max_streams; uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; @@ -139,7 +139,6 @@ struct dc_config { struct dc_debug { bool surface_visual_confirm; bool max_disp_clk; - bool target_trace; bool surface_trace; bool timing_trace; bool validation_trace; @@ -351,95 +350,91 @@ void dc_flip_surface_addrs(struct dc *dc, uint32_t count); /* - * Set up surface attributes and associate to a target - * The surfaces parameter is an absolute set of all surface active for the target. - * If no surfaces are provided, the target will be blanked; no memory read. + * Set up surface attributes and associate to a stream + * The surfaces parameter is an absolute set of all surface active for the stream. + * If no surfaces are provided, the stream will be blanked; no memory read. * Any flip related attribute changes must be done through this interface. * * After this call: - * Surfaces attributes are programmed and configured to be composed into target. + * Surfaces attributes are programmed and configured to be composed into stream. * This does not trigger a flip. No surface address is programmed. */ -bool dc_commit_surfaces_to_target( +bool dc_commit_surfaces_to_stream( struct dc *dc, const struct dc_surface **dc_surfaces, uint8_t surface_count, - struct dc_target *dc_target); + const struct dc_stream *stream); -bool dc_pre_update_surfaces_to_target( +bool dc_pre_update_surfaces_to_stream( struct dc *dc, const struct dc_surface *const *new_surfaces, uint8_t new_surface_count, - struct dc_target *dc_target); + const struct dc_stream *stream); -bool dc_post_update_surfaces_to_target( +bool dc_post_update_surfaces_to_stream( struct dc *dc); -void dc_update_surfaces_for_target(struct dc *dc, struct dc_surface_update *updates, - int surface_count, struct dc_target *dc_target); +void dc_update_surfaces_for_stream(struct dc *dc, struct dc_surface_update *updates, + int surface_count, const struct dc_stream *stream); /******************************************************************************* - * Target Interfaces + * Stream Interfaces ******************************************************************************/ -#define MAX_STREAM_NUM 1 +struct dc_stream { + const struct dc_sink *sink; + struct dc_crtc_timing timing; -struct dc_target { - uint8_t stream_count; - const struct dc_stream *streams[MAX_STREAM_NUM]; -}; + enum dc_color_space output_color_space; -/* - * Target status is returned from dc_target_get_status in order to get the - * the IRQ source, current frame counter and currently attached surfaces. - */ -struct dc_target_status { - int primary_otg_inst; - int cur_frame_count; - int surface_count; - const struct dc_surface *surfaces[MAX_SURFACE_NUM]; -}; + struct rect src; /* composition area */ + struct rect dst; /* stream addressable area */ -struct dc_target *dc_create_target_for_streams( - struct dc_stream *dc_streams[], - uint8_t stream_count); + struct audio_info audio_info; + + bool ignore_msa_timing_param; + + struct freesync_context freesync_ctx; + + const struct dc_transfer_func *out_transfer_func; + struct colorspace_transform gamut_remap_matrix; + struct csc_transform csc_color_matrix; + + /* TODO: dithering */ + /* TODO: custom INFO packets */ + /* TODO: ABM info (DMCU) */ + /* TODO: PSR info */ + /* TODO: CEA VIC */ +}; /* - * Get the current target status. + * Log the current stream state. */ -const struct dc_target_status *dc_target_get_status( - const struct dc_target* dc_target); - -void dc_target_retain(const struct dc_target *dc_target); -void dc_target_release(const struct dc_target *dc_target); -void dc_target_log( - const struct dc_target *dc_target, +void dc_stream_log( + const struct dc_stream *stream, struct dal_logger *dc_logger, enum dc_log_type log_type); -uint8_t dc_get_current_target_count(const struct dc *dc); -struct dc_target *dc_get_target_at_index(const struct dc *dc, uint8_t i); +uint8_t dc_get_current_stream_count(const struct dc *dc); +struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); -bool dc_target_is_connected_to_sink( - const struct dc_target *dc_target, - const struct dc_sink *dc_sink); - -uint32_t dc_target_get_vblank_counter(const struct dc_target *dc_target); +/* + * Return the current frame counter. + */ +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); /* TODO: Return parsed values rather than direct register read * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -uint32_t dc_target_get_scanoutpos( - const struct dc_target *dc_target, - uint32_t *vbl, - uint32_t *position); +uint32_t dc_stream_get_scanoutpos( + const struct dc_stream *stream, uint32_t *vbl, uint32_t *position); /* - * Structure to store surface/target associations for validation + * Structure to store surface/stream associations for validation */ struct dc_validation_set { - const struct dc_target *target; + const struct dc_stream *stream; const struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; @@ -456,8 +451,8 @@ bool dc_validate_resources( uint8_t set_count); /* - * This function takes a target and checks if it is guaranteed to be supported. - * Guaranteed means that MAX_COFUNC*target is supported. + * This function takes a stream and checks if it is guaranteed to be supported. + * Guaranteed means that MAX_COFUNC similar streams are supported. * * After this call: * No hardware is programmed for call. Only validation is done. @@ -465,49 +460,20 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_target *dc_target); + const struct dc_stream *stream); /* - * Set up streams and links associated to targets to drive sinks - * The targets parameter is an absolute set of all active targets. + * Set up streams and links associated to drive sinks + * The streams parameter is an absolute set of all active streams. * * After this call: * Phy, Encoder, Timing Generator are programmed and enabled. - * New targets are enabled with blank stream; no memory read. + * New streams are enabled with blank stream; no memory read. */ -bool dc_commit_targets( +bool dc_commit_streams( struct dc *dc, - struct dc_target *targets[], - uint8_t target_count); - -/******************************************************************************* - * Stream Interfaces - ******************************************************************************/ -struct dc_stream { - const struct dc_sink *sink; - struct dc_crtc_timing timing; - - enum dc_color_space output_color_space; - - struct rect src; /* viewport in target space*/ - struct rect dst; /* stream addressable area */ - - struct audio_info audio_info; - - bool ignore_msa_timing_param; - - struct freesync_context freesync_ctx; - - const struct dc_transfer_func *out_transfer_func; - struct colorspace_transform gamut_remap_matrix; - struct csc_transform csc_color_matrix; - - /* TODO: dithering */ - /* TODO: custom INFO packets */ - /* TODO: ABM info (DMCU) */ - /* TODO: PSR info */ - /* TODO: CEA VIC */ -}; + const struct dc_stream *streams[], + uint8_t stream_count); /** * Create a new default stream for the requested sink @@ -518,6 +484,10 @@ void dc_stream_retain(const struct dc_stream *dc_stream); void dc_stream_release(const struct dc_stream *dc_stream); struct dc_stream_status { + int primary_otg_inst; + int surface_count; + const struct dc_surface *surfaces[MAX_SURFACE_NUM]; + /* * link this stream passes through */ @@ -691,15 +661,15 @@ struct dc_sink_init_data { struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); /******************************************************************************* - * Cursor interfaces - To manages the cursor within a target + * Cursor interfaces - To manages the cursor within a stream ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ -bool dc_target_set_cursor_attributes( - struct dc_target *dc_target, +bool dc_stream_set_cursor_attributes( + const struct dc_stream *stream, const struct dc_cursor_attributes *attributes); -bool dc_target_set_cursor_position( - struct dc_target *dc_target, +bool dc_stream_set_cursor_position( + const struct dc_stream *stream, const struct dc_cursor_position *position); /* Newer interfaces */ @@ -708,36 +678,6 @@ struct dc_cursor { struct dc_cursor_attributes attributes; }; -/* - * Create a new cursor with default values for a given target. - */ -struct dc_cursor *dc_create_cursor_for_target( - const struct dc *dc, - struct dc_target *dc_target); - -/** - * Commit cursor attribute changes such as pixel format and dimensions and - * surface address. - * - * After this call: - * Cursor address and format is programmed to the new values. - * Cursor position is unmodified. - */ -bool dc_commit_cursor( - const struct dc *dc, - struct dc_cursor *cursor); - -/* - * Optimized cursor position update - * - * After this call: - * Cursor position will be programmed as well as enable/disable bit. - */ -bool dc_set_cursor_position( - const struct dc *dc, - struct dc_cursor *cursor, - struct dc_cursor_position *pos); - /******************************************************************************* * Interrupt interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ae9fcca121e6..242dd7b3b6b1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -34,7 +34,6 @@ /* forward declarations */ struct dc_surface; -struct dc_target; struct dc_stream; struct dc_link; struct dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 082f1f053a3a..ae0e7eac2c9d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -741,53 +741,48 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + /* TODO: validate audio ASIC caps, encoder */ + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -818,9 +813,9 @@ static bool dce100_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -846,9 +841,9 @@ enum dc_status dce100_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -858,7 +853,7 @@ enum dc_status dce100_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -876,16 +871,16 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -896,8 +891,8 @@ enum dc_status dce100_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 751dbb88c265..415b12accd2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -753,7 +753,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( stream->public.timing.h_total, stream->public.timing.v_total, stream->public.timing.pix_clk_khz, - context->target_count); + context->stream_count); return DC_OK; } @@ -1055,7 +1055,7 @@ static void reset_single_pipe_hw_ctx( } pipe_ctx->tg->funcs->disable_crtc(pipe_ctx->tg); pipe_ctx->mi->funcs->free_mem_input( - pipe_ctx->mi, context->target_count); + pipe_ctx->mi, context->stream_count); resource_unreference_clock_source( &context->res_ctx, &pipe_ctx->clock_source); @@ -1254,7 +1254,7 @@ enum dc_status dce110_apply_ctx_to_hw( dc->hwss.reset_hw_ctx_wrap(dc, context); /* Skip applying if no targets */ - if (context->target_count <= 0) + if (context->stream_count <= 0) return DC_OK; if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { @@ -1761,7 +1761,7 @@ static void dce110_power_on_pipe_if_needed( pipe_ctx->stream->public.timing.h_total, pipe_ctx->stream->public.timing.v_total, pipe_ctx->stream->public.timing.pix_clk_khz, - context->target_count); + context->stream_count); /* TODO unhardcode*/ color_space_to_black_color(dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 968ee99003fc..cfbb4ef21f8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -817,58 +817,53 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!is_surface_pixel_format_supported(pipe_ctx, - context->res_ctx.pool->underlay_pipe_index)) - return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; + if (!is_surface_pixel_format_supported(pipe_ctx, + context->res_ctx.pool->underlay_pipe_index)) + return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -901,9 +896,9 @@ enum dc_status dce110_validate_bandwidth( dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, - context->targets[0]->public.streams[0]->timing.h_addressable, - context->targets[0]->public.streams[0]->timing.v_addressable, - context->targets[0]->public.streams[0]->timing.pix_clk_khz); + context->streams[0]->public.timing.h_addressable, + context->streams[0]->public.timing.v_addressable, + context->streams[0]->public.timing.pix_clk_khz); if (memcmp(&dc->current_context->bw_results, &context->bw_results, sizeof(context->bw_results))) { @@ -972,9 +967,9 @@ static bool dce110_validate_surface_sets( return false; if (set[i].surfaces[0]->src_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->src_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -988,7 +983,7 @@ static bool dce110_validate_surface_sets( || set[i].surfaces[1]->src_rect.height > 1080) return false; - if (set[i].target->streams[0]->timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) return false; } } @@ -1012,9 +1007,9 @@ enum dc_status dce110_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -1024,7 +1019,7 @@ enum dc_status dce110_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1042,16 +1037,16 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -1062,8 +1057,8 @@ enum dc_status dce110_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 7fca2eb188cf..64fae91dd5eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -779,54 +779,49 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -917,45 +912,40 @@ enum dc_status resource_map_phy_clock_resources( const struct core_dc *dc, struct validate_context *context) { - uint8_t i, j, k; + uint8_t i, j; /* acquire new resources */ - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = - context->res_ctx.pool->dp_clock_source; - else - pipe_ctx->clock_source = - find_matching_pll(&context->res_ctx, - stream); + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + context->res_ctx.pool->dp_clock_source; + else + pipe_ctx->clock_source = + find_matching_pll(&context->res_ctx, + stream); - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - resource_reference_clock_source( - &context->res_ctx, - pipe_ctx->clock_source); + resource_reference_clock_source( + &context->res_ctx, + pipe_ctx->clock_source); - /* only one cs per stream regardless of mpo */ - break; - } + /* only one cs per stream regardless of mpo */ + break; } } @@ -976,9 +966,9 @@ static bool dce112_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -1004,9 +994,9 @@ enum dc_status dce112_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -1016,7 +1006,7 @@ enum dc_status dce112_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -1034,16 +1024,16 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -1054,8 +1044,8 @@ enum dc_status dce112_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index f21eb57857d4..faa8c45a3544 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -43,7 +43,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context); enum dc_status dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index e2bfa7efce1c..bee3a41ffe9f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -731,54 +731,49 @@ static enum dc_status validate_mapped_resource( struct validate_context *context) { enum dc_status status = DC_OK; - uint8_t i, j, k; + uint8_t i, j; - for (i = 0; i < context->target_count; i++) { - struct core_target *target = context->targets[i]; + for (i = 0; i < context->stream_count; i++) { + struct core_stream *stream = context->streams[i]; + struct core_link *link = stream->sink->link; - for (j = 0; j < target->public.stream_count; j++) { - struct core_stream *stream = - DC_STREAM_TO_CORE(target->public.streams[j]); - struct core_link *link = stream->sink->link; - - if (resource_is_stream_unchanged(dc->current_context, stream)) - continue; + if (resource_is_stream_unchanged(dc->current_context, stream)) + continue; - for (k = 0; k < MAX_PIPES; k++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[k]; + for (j = 0; j < MAX_PIPES; j++) { + struct pipe_ctx *pipe_ctx = + &context->res_ctx.pipe_ctx[j]; - if (context->res_ctx.pipe_ctx[k].stream != stream) - continue; + if (context->res_ctx.pipe_ctx[j].stream != stream) + continue; - if (!pipe_ctx->tg->funcs->validate_timing( - pipe_ctx->tg, &stream->public.timing)) - return DC_FAIL_CONTROLLER_VALIDATE; + if (!pipe_ctx->tg->funcs->validate_timing( + pipe_ctx->tg, &stream->public.timing)) + return DC_FAIL_CONTROLLER_VALIDATE; - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, - pipe_ctx)) - return DC_FAIL_ENC_VALIDATE; + if (!link->link_enc->funcs->validate_output_with_stream( + link->link_enc, + pipe_ctx)) + return DC_FAIL_ENC_VALIDATE; - /* TODO: validate audio ASIC caps, encoder */ + /* TODO: validate audio ASIC caps, encoder */ - status = dc_link_validate_mode_timing(stream, - link, - &stream->public.timing); + status = dc_link_validate_mode_timing(stream, + link, + &stream->public.timing); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); + resource_build_info_frame(pipe_ctx); - /* do not need to validate non root pipes */ - break; - } + /* do not need to validate non root pipes */ + break; } } @@ -810,9 +805,9 @@ static bool dce80_validate_surface_sets( return false; if (set[i].surfaces[0]->clip_rect.width - != set[i].target->streams[0]->src.width + != set[i].stream->src.width || set[i].surfaces[0]->clip_rect.height - != set[i].target->streams[0]->src.height) + != set[i].stream->src.height) return false; if (set[i].surfaces[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) @@ -838,9 +833,9 @@ enum dc_status dce80_validate_with_context( context->res_ctx.pool = dc->res_pool; for (i = 0; i < set_count; i++) { - context->targets[i] = DC_TARGET_TO_CORE(set[i].target); - dc_target_retain(&context->targets[i]->public); - context->target_count++; + context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); + dc_stream_retain(&context->streams[i]->public); + context->stream_count++; } result = resource_map_pool_resources(dc, context); @@ -850,7 +845,7 @@ enum dc_status dce80_validate_with_context( if (!resource_validate_attach_surfaces( set, set_count, dc->current_context, context)) { - DC_ERROR("Failed to attach surface to target!\n"); + DC_ERROR("Failed to attach surface to stream!\n"); return DC_FAIL_ATTACH_SURFACES; } @@ -868,16 +863,16 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; context->res_ctx.pool = dc->res_pool; - context->targets[0] = DC_TARGET_TO_CORE(dc_target); - dc_target_retain(&context->targets[0]->public); - context->target_count++; + context->streams[0] = DC_STREAM_TO_CORE(dc_stream); + dc_stream_retain(&context->streams[0]->public); + context->stream_count++; result = resource_map_pool_resources(dc, context); @@ -888,8 +883,8 @@ enum dc_status dce80_validate_guaranteed( result = validate_mapped_resource(dc, context); if (result == DC_OK) { - validate_guaranteed_copy_target( - context, dc->public.caps.max_targets); + validate_guaranteed_copy_streams( + context, dc->public.caps.max_streams); result = resource_build_scaling_params_for_context(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index b5a5207a4df0..7a6444dc2957 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -21,7 +21,6 @@ struct core_dc { uint8_t link_count; struct core_link *links[MAX_PIPES * 2]; - /* TODO: determine max number of targets*/ struct validate_context *current_context; struct validate_context *temp_flip_context; struct validate_context *scratch_val_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index c2d35c2c28bf..66bfcdb57c4c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -32,21 +32,10 @@ #include "dc_bios_types.h" struct core_stream; -/********* core_target *************/ - -#define CONST_DC_TARGET_TO_CORE(dc_target) \ - container_of(dc_target, const struct core_target, public) -#define DC_TARGET_TO_CORE(dc_target) \ - container_of(dc_target, struct core_target, public) #define MAX_PIPES 6 #define MAX_CLOCK_SOURCES 7 -struct core_target { - struct dc_target public; - - struct dc_context *ctx; -}; /********* core_surface **********/ #define DC_SURFACE_TO_CORE(dc_surface) \ @@ -215,7 +204,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - const struct dc_target *dc_target, + const struct dc_stream *stream, struct validate_context *context); enum dc_status (*validate_bandwidth)( @@ -312,9 +301,9 @@ struct resource_context { }; struct validate_context { - struct core_target *targets[MAX_PIPES]; - struct dc_target_status target_status[MAX_PIPES]; - uint8_t target_count; + struct core_stream *streams[MAX_PIPES]; + struct dc_stream_status stream_status[MAX_PIPES]; + uint8_t stream_count; struct resource_context res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index adf297ec33b6..d96c64bb0a70 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -118,25 +118,26 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( bool resource_attach_surfaces_to_context( const struct dc_surface *const *surfaces, int surface_count, - const struct dc_target *dc_target, + const struct dc_stream *dc_stream, struct validate_context *context); struct pipe_ctx *find_idle_secondary_pipe(struct resource_context *res_ctx); bool resource_is_stream_unchanged( - const struct validate_context *old_context, struct core_stream *stream); + const struct validate_context *old_context, const struct core_stream *stream); + +bool is_stream_unchanged( + const struct core_stream *old_stream, const struct core_stream *stream); -bool is_target_unchanged( - const struct core_target *old_target, const struct core_target *target); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, const struct validate_context *old_context, struct validate_context *context); -void validate_guaranteed_copy_target( +void validate_guaranteed_copy_streams( struct validate_context *context, - int max_targets); + int max_streams); void resource_validate_ctx_update_pointer_after_copy( const struct validate_context *src_ctx, -- cgit v1.2.3 From b57de80a51479f19a41f737ddd1ab18028bf9a43 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 19 Apr 2017 13:29:11 -0400 Subject: drm/amd/display: Register on VLBLANK ISR. Switch from VUPDATE to VBLANK. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++------ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 214cd38b8135..b85f34ba158c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -201,7 +201,7 @@ static void dm_crtc_high_irq(void *interrupt_params) uint8_t crtc_index = 0; struct amdgpu_crtc *acrtc; - acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE); + acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK); if (acrtc) crtc_index = acrtc->crtc_id; @@ -1026,9 +1026,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) * amdgpu_dm_irq_handler() will re-direct the interrupt to DC * for acknowledging and handling. */ - for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; - i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); + /* Use VBLANK interrupt */ + for (i = 0; i < adev->mode_info.num_crtc; i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i+1, &adev->crtc_irq); + if (r) { DRM_ERROR("Failed to add crtc irq id!\n"); return r; @@ -1036,9 +1037,9 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; int_params.irq_source = - dc_interrupt_to_irq_source(dc, i, 0); + dc_interrupt_to_irq_source(dc, i+1, 0); - c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1]; + c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; c_irq_params->adev = adev; c_irq_params->irq_src = int_params.irq_source; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1b54566f5da1..d6ebba012e15 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -105,7 +105,7 @@ struct amdgpu_display_manager { pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; struct common_irq_params - vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; + vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; /* this spin lock synchronizes access to 'irq_handler_list_table' */ spinlock_t irq_handler_list_table_lock; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 20e074971bff..682e9c3ad8e5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -736,7 +736,7 @@ static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev, source, crtc_id, state, - IRQ_TYPE_VUPDATE, + IRQ_TYPE_VBLANK, __func__); } -- cgit v1.2.3 From 3d761e7990a27dca7481d4f4e4d6b3751509ab11 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 19 Apr 2017 13:55:35 -0400 Subject: drm/amd/display: Clean index in irq init loop Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Tony Cheng Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b85f34ba158c..0c50433d6ba3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1027,8 +1027,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) * for acknowledging and handling. */ /* Use VBLANK interrupt */ - for (i = 0; i < adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i+1, &adev->crtc_irq); + for (i = 1; i <= adev->mode_info.num_crtc; i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); if (r) { DRM_ERROR("Failed to add crtc irq id!\n"); @@ -1037,7 +1037,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; int_params.irq_source = - dc_interrupt_to_irq_source(dc, i+1, 0); + dc_interrupt_to_irq_source(dc, i, 0); c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; @@ -1048,6 +1048,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) dm_crtc_high_irq, c_irq_params); } + /* Use GRPH_PFLIP interrupt */ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); -- cgit v1.2.3 From 7d4e9bf9835ad081fb5967336cace7f5aa8ffd6d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 21 Feb 2017 17:09:34 -0500 Subject: drm/amd/display: Remove LINUX_VERSION_CODE check Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0c50433d6ba3..d0706e550e84 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -886,14 +886,12 @@ static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector) process_count++; DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 3, 0) /* handle HPD short pulse irq */ if (aconnector->mst_mgr.mst_state) drm_dp_mst_hpd_irq( &aconnector->mst_mgr, esi, &new_irq_handled); -#endif if (new_irq_handled) { /* ACK at DPCD to notify down stream */ -- cgit v1.2.3 From a49dcb88e8159b12d1af5f67d657388c4a1c96cb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 12 Jan 2017 09:09:08 -0500 Subject: drm/amd/display: Use amdgpu mode funcs statically No need to assign them dynamically. This is much more readable. Signed-off-by: Harry Wentland Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d0706e550e84..21dcd6caf628 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -28,6 +28,7 @@ #include "vid.h" #include "amdgpu.h" +#include "amdgpu_display.h" #include "atom.h" #include "amdgpu_dm.h" #include "amdgpu_dm_types.h" @@ -715,6 +716,8 @@ const struct amdgpu_ip_block_version dm_ip_block = /* TODO: it is temporary non-const, should fixed later */ static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { + .fb_create = amdgpu_user_framebuffer_create, + .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = amdgpu_dm_atomic_commit }; @@ -1088,11 +1091,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; - amdgpu_dm_mode_funcs.fb_create = - amdgpu_mode_funcs.fb_create; - amdgpu_dm_mode_funcs.output_poll_changed = - amdgpu_mode_funcs.output_poll_changed; - adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; adev->ddev->mode_config.max_width = 16384; -- cgit v1.2.3 From 54f5499a54fe671c56012684d5a68efbb4fe0b53 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 20 Apr 2017 15:57:05 -0400 Subject: drm/amd/display: Refactor atomic commit implementation. (v2) Modify amdgpu_dm_atomic_comit to implement atomic_comit_tail hook. Unify Buffer objects allocation and dealocation for surface updates and page flips. Simplify wait for fences and target_vbank logic for non blockiing commit. Remove hacky update surface to page flip synchronization we had and rely on atomic framework synchronization logic. v2: Add state->allow_modeset as indicator of page flip call. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 58 +++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 343 ++++++++++----------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 7 +- 3 files changed, 203 insertions(+), 205 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 21dcd6caf628..da499ab7eab5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -149,7 +149,6 @@ static struct amdgpu_crtc *get_crtc_by_otg_inst( static void dm_pflip_high_irq(void *interrupt_params) { - struct amdgpu_flip_work *works; struct amdgpu_crtc *amdgpu_crtc; struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; @@ -165,7 +164,6 @@ static void dm_pflip_high_irq(void *interrupt_params) } spin_lock_irqsave(&adev->ddev->event_lock, flags); - works = amdgpu_crtc->pflip_works; if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){ DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n", @@ -177,22 +175,24 @@ static void dm_pflip_high_irq(void *interrupt_params) return; } - /* page flip completed. clean up */ - amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; - amdgpu_crtc->pflip_works = NULL; /* wakeup usersapce */ - if (works->event) - drm_crtc_send_vblank_event(&amdgpu_crtc->base, - works->event); + if (amdgpu_crtc->event + && amdgpu_crtc->event->event.base.type + == DRM_EVENT_FLIP_COMPLETE) { + drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); + /* page flip completed. clean up */ + amdgpu_crtc->event = NULL; + } else + WARN_ON(1); + amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE; spin_unlock_irqrestore(&adev->ddev->event_lock, flags); - DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE, work: %p,\n", - __func__, amdgpu_crtc->crtc_id, amdgpu_crtc, works); + DRM_DEBUG_DRIVER("%s - crtc :%d[%p], pflip_stat:AMDGPU_FLIP_NONE\n", + __func__, amdgpu_crtc->crtc_id, amdgpu_crtc); drm_crtc_vblank_put(&amdgpu_crtc->base); - schedule_work(&works->unpin_work); } static void dm_crtc_high_irq(void *interrupt_params) @@ -719,7 +719,11 @@ static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, - .atomic_commit = amdgpu_dm_atomic_commit + .atomic_commit = drm_atomic_helper_commit +}; + +static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { + .atomic_commit_tail = amdgpu_dm_atomic_commit_tail }; void amdgpu_dm_update_connector_after_detect( @@ -1092,6 +1096,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; + adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; adev->ddev->mode_config.max_width = 16384; adev->ddev->mode_config.max_height = 16384; @@ -1345,6 +1350,14 @@ static void dm_page_flip(struct amdgpu_device *adev, acrtc = adev->mode_info.crtcs[crtc_id]; stream = acrtc->stream; + + if (acrtc->pflip_status != AMDGPU_FLIP_NONE) { + DRM_ERROR("flip queue: acrtc %d, already busy\n", acrtc->crtc_id); + /* In commit tail framework this cannot happen */ + BUG_ON(0); + } + + /* * Received a page flip call after the display has been reset. * Just return in this case. Everything should be clean-up on reset. @@ -1359,15 +1372,28 @@ static void dm_page_flip(struct amdgpu_device *adev, addr.address.grph.addr.high_part = upper_32_bits(crtc_base); addr.flip_immediate = async; + + if (acrtc->base.state->event && + acrtc->base.state->event->event.base.type == + DRM_EVENT_FLIP_COMPLETE) { + acrtc->event = acrtc->base.state->event; + + /* Set the flip status */ + acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + + /* Mark this event as consumed */ + acrtc->base.state->event = NULL; + } + + dc_flip_surface_addrs(adev->dm.dc, + dc_stream_get_status(stream)->surfaces, + &addr, 1); + DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, addr.address.grph.addr.high_part, addr.address.grph.addr.low_part); - dc_flip_surface_addrs( - adev->dm.dc, - dc_stream_get_status(stream)->surfaces, - &addr, 1); } static int amdgpu_notify_freesync(struct drm_device *dev, void *data, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 008c7a55e992..956ff5a7b9b6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -687,8 +687,18 @@ static void dm_dc_surface_commit( { struct dc_surface *dc_surface; const struct dc_surface *dc_surfaces[1]; - const struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); const struct dc_stream *dc_stream = acrtc->stream; + unsigned long flags; + + spin_lock_irqsave(&crtc->dev->event_lock, flags); + if (acrtc->pflip_status != AMDGPU_FLIP_NONE) { + DRM_ERROR("dm_dc_surface_commit: acrtc %d, already busy\n", acrtc->crtc_id); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + /* In comit tail framework this cannot happen */ + BUG_ON(0); + } + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); if (!dc_stream) { dm_error( @@ -1427,6 +1437,7 @@ static void clear_unrelated_fields(struct drm_plane_state *state) state->fence = NULL; } +/*TODO update because event is always present now */ static bool page_flip_needed( const struct drm_plane_state *new_state, const struct drm_plane_state *old_state, @@ -1482,11 +1493,13 @@ static bool page_flip_needed( page_flip_required = memcmp(&old_state_tmp, &new_state_tmp, sizeof(old_state_tmp)) == 0 ? true:false; + if (new_state->crtc && page_flip_required == false) { acrtc_new = to_amdgpu_crtc(new_state->crtc); if (acrtc_new->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) page_flip_required = true; } + return page_flip_required; } @@ -1512,7 +1525,7 @@ static int dm_plane_helper_prepare_fb( if (unlikely(r != 0)) return r; - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL); + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address); amdgpu_bo_unreserve(rbo); @@ -1521,6 +1534,7 @@ static int dm_plane_helper_prepare_fb( return r; } + amdgpu_bo_ref(rbo); return 0; } @@ -1544,7 +1558,10 @@ static void dm_plane_helper_cleanup_fb( } else { amdgpu_bo_unpin(rbo); amdgpu_bo_unreserve(rbo); + amdgpu_bo_unref(&rbo); } + + afb->address = 0; } int dm_create_validation_set_for_connector(struct drm_connector *connector, @@ -2135,51 +2152,6 @@ static enum dm_commit_action get_dm_commit_action(struct drm_crtc_state *state) } } - -typedef bool (*predicate)(struct amdgpu_crtc *acrtc); - -static void wait_while_pflip_status(struct amdgpu_device *adev, - struct amdgpu_crtc *acrtc, predicate f) { - int count = 0; - while (f(acrtc)) { - /* Spin Wait*/ - msleep(1); - count++; - if (count == 1000) { - DRM_ERROR("%s - crtc:%d[%p], pflip_stat:%d, probable hang!\n", - __func__, acrtc->crtc_id, - acrtc, - acrtc->pflip_status); - - /* we do not expect to hit this case except on Polaris with PHY PLL - * 1. DP to HDMI passive dongle connected - * 2. unplug (headless) - * 3. plug in DP - * 3a. on plug in, DP will try verify link by training, and training - * would disable PHY PLL which HDMI rely on to drive TG - * 3b. this will cause flip interrupt cannot be generated, and we - * exit when timeout expired. however we do not have code to clean - * up flip, flip clean up will happen when the address is written - * with the restore mode change - */ - WARN_ON(1); - break; - } - } - - DRM_DEBUG_DRIVER("%s - Finished waiting for:%d msec, crtc:%d[%p], pflip_stat:%d \n", - __func__, - count, - acrtc->crtc_id, - acrtc, - acrtc->pflip_status); -} - -static bool pflip_in_progress_predicate(struct amdgpu_crtc *acrtc) -{ - return acrtc->pflip_status != AMDGPU_FLIP_NONE; -} - static void manage_dm_interrupts( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, @@ -2201,8 +2173,6 @@ static void manage_dm_interrupts( &adev->pageflip_irq, irq_type); } else { - wait_while_pflip_status(adev, acrtc, - pflip_in_progress_predicate); amdgpu_irq_put( adev, @@ -2212,12 +2182,6 @@ static void manage_dm_interrupts( } } - -static bool pflip_pending_predicate(struct amdgpu_crtc *acrtc) -{ - return acrtc->pflip_status == AMDGPU_FLIP_PENDING; -} - static bool is_scaling_state_different( const struct dm_connector_state *dm_state, const struct dm_connector_state *old_dm_state) @@ -2255,116 +2219,94 @@ static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) acrtc->enabled = false; } -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock) + +/* + * Executes flip + * + * Waits on all BO's fences and for proper vblank count + */ +static void amdgpu_dm_do_flip( + struct drm_crtc *crtc, + struct drm_framebuffer *fb, + uint32_t target) +{ + unsigned long flags; + uint32_t target_vblank; + int r, vpos, hpos; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj); + struct amdgpu_device *adev = crtc->dev->dev_private; + bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + + + /*TODO This might fail and hence better not used, wait + * explicitly on fences instead + * and in general should be called for + * blocking commit to as per framework helpers + * */ + r = amdgpu_bo_reserve(abo, true); + if (unlikely(r != 0)) { + DRM_ERROR("failed to reserve buffer before flip\n"); + BUG_ON(0); + } + + /* Wait for all fences on this FB */ + WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT) < 0); + + amdgpu_bo_unreserve(abo); + + /* Wait for target vblank */ + /* Wait until we're out of the vertical blank period before the one + * targeted by the flip + */ + target_vblank = target - drm_crtc_vblank_count(crtc) + + amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); + + while ((acrtc->enabled && + (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0, + &vpos, &hpos, NULL, NULL, + &crtc->hwmode) + & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && + (int)(target_vblank - + amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { + usleep_range(1000, 1100); + } + + /* Flip */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + /* update crtc fb */ + crtc->primary->fb = fb; + + /* Do the flip (mmio) */ + adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip); + + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", + acrtc->crtc_id); +} + +void amdgpu_dm_atomic_commit_tail( + struct drm_atomic_state *state) { + struct drm_device *dev = state->dev; struct amdgpu_device *adev = dev->dev_private; struct amdgpu_display_manager *dm = &adev->dm; struct drm_plane *plane; - struct drm_plane_state *new_plane_state; struct drm_plane_state *old_plane_state; uint32_t i; - int32_t ret = 0; uint32_t commit_streams_count = 0; uint32_t new_crtcs_count = 0; - uint32_t flip_crtcs_count = 0; struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state; const struct dc_stream *commit_streams[MAX_STREAMS]; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; const struct dc_stream *new_stream; - struct drm_crtc *flip_crtcs[MAX_STREAMS]; - struct amdgpu_flip_work *work[MAX_STREAMS] = {0}; - struct amdgpu_bo *new_abo[MAX_STREAMS] = {0}; - - /* In this step all new fb would be pinned */ - - /* - * TODO: Revisit when we support true asynchronous commit. - * Right now we receive async commit only from pageflip, in which case - * we should not pin/unpin the fb here, it should be done in - * amdgpu_crtc_flip and from the vblank irq handler. - */ - if (!nonblock) { - ret = drm_atomic_helper_prepare_planes(dev, state); - if (ret) - return ret; - } - - /* Page flip if needed */ - for_each_plane_in_state(state, plane, new_plane_state, i) { - struct drm_plane_state *old_plane_state = plane->state; - struct drm_crtc *crtc = new_plane_state->crtc; - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct drm_framebuffer *fb = new_plane_state->fb; - struct drm_crtc_state *crtc_state; + unsigned long flags; + bool wait_for_vblank = true; - if (!fb || !crtc) - continue; - - crtc_state = drm_atomic_get_crtc_state(state, crtc); - - if (!crtc_state->planes_changed || !crtc_state->active) - continue; - - if (page_flip_needed( - new_plane_state, - old_plane_state, - crtc_state->event, - false)) { - ret = amdgpu_crtc_prepare_flip(crtc, - fb, - crtc_state->event, - acrtc->flip_flags, - drm_crtc_vblank_count(crtc), - &work[flip_crtcs_count], - &new_abo[flip_crtcs_count]); - - if (ret) { - /* According to atomic_commit hook API, EINVAL is not allowed */ - if (unlikely(ret == -EINVAL)) - ret = -ENOMEM; - - DRM_ERROR("Atomic commit: Flip for crtc id %d: [%p], " - "failed, errno = %d\n", - acrtc->crtc_id, - acrtc, - ret); - /* cleanup all flip configurations which - * succeeded in this commit - */ - for (i = 0; i < flip_crtcs_count; i++) - amdgpu_crtc_cleanup_flip_ctx( - work[i], - new_abo[i]); - - return ret; - } - - flip_crtcs[flip_crtcs_count] = crtc; - flip_crtcs_count++; - } - } - - /* - * This is the point of no return - everything below never fails except - * when the hw goes bonghits. Which means we can commit the new state on - * the software side now. - */ - - drm_atomic_helper_swap_state(state, true); - - /* - * From this point state become old state really. New state is - * initialized to appropriate objects and could be accessed from there - */ - - /* - * there is no fences usage yet in state. We can skip the following line - * wait_for_fences(dev, state); - */ drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -2520,11 +2462,11 @@ int amdgpu_dm_atomic_commit( for_each_plane_in_state(state, plane, old_plane_state, i) { struct drm_plane_state *plane_state = plane->state; struct drm_crtc *crtc = plane_state->crtc; - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_framebuffer *fb = plane_state->fb; struct drm_connector *connector; struct dm_connector_state *dm_state = NULL; enum dm_commit_action action; + bool pflip_needed; if (!fb || !crtc || !crtc->state->active) continue; @@ -2535,12 +2477,14 @@ int amdgpu_dm_atomic_commit( * 1. This commit is not a page flip. * 2. This commit is a page flip, and streams are created. */ - if (!page_flip_needed( + pflip_needed = !state->allow_modeset && + page_flip_needed( plane_state, old_plane_state, - crtc->state->event, true) || - action == DM_COMMIT_ACTION_DPMS_ON || - action == DM_COMMIT_ACTION_SET) { + crtc->state->event, true); + if (!pflip_needed || + action == DM_COMMIT_ACTION_DPMS_ON || + action == DM_COMMIT_ACTION_SET) { list_for_each_entry(connector, &dev->mode_config.connector_list, head) { if (connector->state->crtc == crtc) { @@ -2567,14 +2511,6 @@ int amdgpu_dm_atomic_commit( if (!dm_state) continue; - /* - * if flip is pending (ie, still waiting for fence to return - * before address is submitted) here, we cannot commit_surface - * as commit_surface will pre-maturely write out the future - * address. wait until flip is submitted before proceeding. - */ - wait_while_pflip_status(adev, acrtc, pflip_pending_predicate); - dm_dc_surface_commit(dm->dc, crtc); } } @@ -2594,43 +2530,77 @@ int amdgpu_dm_atomic_commit( } - /* Do actual flip */ - flip_crtcs_count = 0; for_each_plane_in_state(state, plane, old_plane_state, i) { struct drm_plane_state *plane_state = plane->state; struct drm_crtc *crtc = plane_state->crtc; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_framebuffer *fb = plane_state->fb; + bool pflip_needed; if (!fb || !crtc || !crtc->state->planes_changed || !crtc->state->active) continue; - - if (page_flip_needed( + pflip_needed = !state->allow_modeset && + page_flip_needed( plane_state, old_plane_state, crtc->state->event, - false)) { - amdgpu_crtc_submit_flip( - crtc, - fb, - work[flip_crtcs_count], - new_abo[i]); - flip_crtcs_count++; + false); + + if (pflip_needed) { + amdgpu_dm_do_flip( + crtc, + fb, + drm_crtc_vblank_count(crtc)); + + wait_for_vblank = + acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? + false : true; /*clean up the flags for next usage*/ acrtc->flip_flags = 0; } } - /* In this state all old framebuffers would be unpinned */ - /* TODO: Revisit when we support true asynchronous commit.*/ - if (!nonblock) - drm_atomic_helper_cleanup_planes(dev, state); + /*TODO mark consumed event on all crtc assigned event + * in drm_atomic_helper_setup_commit just to signal completion + */ + spin_lock_irqsave(&adev->ddev->event_lock, flags); + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + if (acrtc->base.state->event && + acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) { + acrtc->event = acrtc->base.state->event; + acrtc->base.state->event = NULL; + } + } + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + /* Signal HW programming completion */ + drm_atomic_helper_commit_hw_done(state); + + if (wait_for_vblank) + drm_atomic_helper_wait_for_vblanks(dev, state); + + /*TODO send vblank event on all crtc assigned event + * in drm_atomic_helper_setup_commit just to signal completion + */ + spin_lock_irqsave(&adev->ddev->event_lock, flags); + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - drm_atomic_state_put(state); + if (acrtc->event && + acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) { + drm_send_event_locked(dev, &acrtc->event->base); + acrtc->event = NULL; + } + } + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); - return ret; + /*TODO Is it to early if actual flip haven't happened yet ?*/ + /* Release old FB */ + drm_atomic_helper_cleanup_planes(dev, state); } /* * This functions handle all cases when set mode does not come upon hotplug. @@ -2982,6 +2952,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dm_connector_state *dm_state = NULL; enum dm_commit_action action; struct drm_crtc_state *crtc_state; + bool pflip_needed; if (!fb || !crtc || crtc_set[i] != crtc || @@ -2995,10 +2966,12 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * 2. This commit is a page flip, and streams are created. */ crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (!page_flip_needed(plane_state, old_plane_state, - crtc_state->event, true) || - action == DM_COMMIT_ACTION_DPMS_ON || - action == DM_COMMIT_ACTION_SET) { + pflip_needed = !state->allow_modeset && + page_flip_needed(plane_state, old_plane_state, + crtc_state->event, true); + if (!pflip_needed || + action == DM_COMMIT_ACTION_DPMS_ON || + action == DM_COMMIT_ACTION_SET) { struct dc_surface *surface; list_for_each_entry(connector, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 4faa1659f7f9..1bbeb87dc9d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -52,10 +52,9 @@ void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool async); +void amdgpu_dm_atomic_commit_tail( + struct drm_atomic_state *state); + int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); -- cgit v1.2.3 From a36214858c9093086c1bf1415af6b67c220d711f Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 20 Apr 2017 15:59:25 -0400 Subject: drm/amd/display: Switch to DRM helpers in s3. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Tony Cheng Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 157 ++-------------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 + drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 4 - 5 files changed, 21 insertions(+), 156 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index da499ab7eab5..a69ce27b8ed6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -451,28 +451,17 @@ static int dm_suspend(void *handle) struct amdgpu_device *adev = handle; struct amdgpu_display_manager *dm = &adev->dm; int ret = 0; - struct drm_crtc *crtc; s3_handle_mst(adev->ddev, true); - /* flash all pending vblank events and turn interrupt off - * before disabling CRTCs. They will be enabled back in - * dm_display_resume - */ - drm_modeset_lock_all(adev->ddev); - list_for_each_entry(crtc, &adev->ddev->mode_config.crtc_list, head) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->stream) - drm_crtc_vblank_off(crtc); - } - drm_modeset_unlock_all(adev->ddev); - amdgpu_dm_irq_suspend(adev); + adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); + dc_set_power_state( dm->dc, - DC_ACPI_CM_POWER_STATE_D3, - DC_VIDEO_POWER_SUSPEND); + DC_ACPI_CM_POWER_STATE_D3 + ); return ret; } @@ -504,120 +493,6 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( return NULL; } -static int dm_display_resume(struct drm_device *ddev) -{ - int ret = 0; - struct drm_connector *connector; - - struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); - struct drm_plane *plane; - struct drm_crtc *crtc; - struct amdgpu_connector *aconnector; - struct drm_connector_state *conn_state; - - if (!state) - return ENOMEM; - - state->acquire_ctx = ddev->mode_config.acquire_ctx; - - /* Construct an atomic state to restore previous display setting */ - - /* - * Attach connectors to drm_atomic_state - * Should be done in the first place in order to make connectors - * available in state during crtc state processing. It is used for - * making decision if crtc should be disabled in case sink got - * disconnected. - * - * Connectors state crtc with NULL dc_sink should be cleared, because it - * will fail validation during commit - */ - list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); - conn_state = drm_atomic_get_connector_state(state, connector); - - ret = PTR_ERR_OR_ZERO(conn_state); - if (ret) - goto err; - } - - /* Attach crtcs to drm_atomic_state*/ - list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { - struct drm_crtc_state *crtc_state = - drm_atomic_get_crtc_state(state, crtc); - - ret = PTR_ERR_OR_ZERO(crtc_state); - if (ret) - goto err; - - /* force a restore */ - crtc_state->mode_changed = true; - } - - - /* Attach planes to drm_atomic_state */ - list_for_each_entry(plane, &ddev->mode_config.plane_list, head) { - - struct drm_crtc *crtc; - struct drm_gem_object *obj; - struct drm_framebuffer *fb; - struct amdgpu_framebuffer *afb; - struct amdgpu_bo *rbo; - int r; - struct drm_plane_state *plane_state = drm_atomic_get_plane_state(state, plane); - - ret = PTR_ERR_OR_ZERO(plane_state); - if (ret) - goto err; - - crtc = plane_state->crtc; - fb = plane_state->fb; - - if (!crtc || !crtc->state || !crtc->state->active) - continue; - - if (!fb) { - DRM_DEBUG_KMS("No FB bound\n"); - return 0; - } - - /* - * Pin back the front buffers, cursor buffer was already pinned - * back in amdgpu_resume_kms - */ - - afb = to_amdgpu_framebuffer(fb); - - obj = afb->obj; - rbo = gem_to_amdgpu_bo(obj); - r = amdgpu_bo_reserve(rbo, false); - if (unlikely(r != 0)) - return r; - - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, NULL); - - amdgpu_bo_unreserve(rbo); - - if (unlikely(r != 0)) { - DRM_ERROR("Failed to pin framebuffer\n"); - return r; - } - - } - - - /* Call commit internally with the state we just constructed */ - ret = drm_atomic_commit(state); - if (!ret) - return 0; - -err: - DRM_ERROR("Restoring old state failed with %i\n", ret); - drm_atomic_state_put(state); - - return ret; -} - static int dm_resume(void *handle) { struct amdgpu_device *adev = handle; @@ -626,8 +501,8 @@ static int dm_resume(void *handle) /* power on hardware */ dc_set_power_state( dm->dc, - DC_ACPI_CM_POWER_STATE_D0, - DC_VIDEO_POWER_ON); + DC_ACPI_CM_POWER_STATE_D0 + ); return 0; } @@ -638,8 +513,10 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_connector *aconnector; struct drm_connector *connector; - int ret = 0; struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + int ret = 0; + int i; /* program HPD filter */ dc_resume(dm->dc); @@ -653,14 +530,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) */ amdgpu_dm_irq_resume_early(adev); - drm_modeset_lock_all(ddev); - list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->stream) - drm_crtc_vblank_on(crtc); - } - drm_modeset_unlock_all(ddev); - /* Do detection*/ list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { @@ -678,9 +547,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) amdgpu_dm_update_connector_after_detect(aconnector); } - drm_modeset_lock_all(ddev); - ret = dm_display_resume(ddev); - drm_modeset_unlock_all(ddev); + /* Force mode set in atomic comit */ + for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i) + crtc_state->active_changed = true; + + ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); amdgpu_dm_irq_resume(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index d6ebba012e15..ee69179636a1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -128,6 +128,11 @@ struct amdgpu_display_manager { struct work_struct mst_hotplug_work; struct mod_freesync *freesync_module; + + /** + * Caches device atomic state for suspend/resume + */ + struct drm_atomic_state *cached_state; }; /* basic init/fini API */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a39b9987b9d6..edcb731a3aea 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1589,21 +1589,15 @@ void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src) void dc_set_power_state( struct dc *dc, - enum dc_acpi_cm_power_state power_state, - enum dc_video_power_state video_power_state) + enum dc_acpi_cm_power_state power_state) { struct core_dc *core_dc = DC_TO_CORE(dc); - core_dc->previous_power_state = core_dc->current_power_state; - core_dc->current_power_state = video_power_state; - switch (power_state) { case DC_ACPI_CM_POWER_STATE_D0: core_dc->hwss.init_hw(core_dc); break; default: - /* NULL means "reset/release all DC streams" */ - dc_commit_streams(dc, NULL, 0); core_dc->hwss.power_down(core_dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 69ae94bb209f..e2c2a0bf764d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -705,8 +705,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index( void dc_set_power_state( struct dc *dc, - enum dc_acpi_cm_power_state power_state, - enum dc_video_power_state video_power_state); + enum dc_acpi_cm_power_state power_state); void dc_resume(const struct dc *dc); /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index 7a6444dc2957..8d87f490dc1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -26,10 +26,6 @@ struct core_dc { struct validate_context *scratch_val_ctx; struct resource_pool *res_pool; - /*Power State*/ - enum dc_video_power_state previous_power_state; - enum dc_video_power_state current_power_state; - /* Display Engine Clock levels */ struct dm_pp_clock_levels sclk_lvls; -- cgit v1.2.3 From 2c8ad2d5a20c8b7425b547dd4a969ffecad29b39 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:20:24 -0400 Subject: drm/amd/display: Enable DCE12 support This wires DCE12 support into DC and enables it. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 + drivers/gpu/drm/amd/display/Kconfig | 7 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 10 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 22 ++- drivers/gpu/drm/amd/display/dc/Makefile | 4 + drivers/gpu/drm/amd/display/dc/bios/Makefile | 8 ++ .../amd/display/dc/bios/bios_parser_interface.c | 14 ++ drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 117 ++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc.c | 29 ++++ drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 11 ++ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 19 +++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++ drivers/gpu/drm/amd/display/dc/dc.h | 27 ++++ drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 46 +++++++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 + drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 149 +++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 20 +++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 8 ++ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 14 ++ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 35 +++++ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 34 +++++ drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 72 ++++++++++ .../drm/amd/display/dc/dce/dce_stream_encoder.h | 100 ++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 68 ++++++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 53 +++++++- .../drm/amd/display/dc/dce110/dce110_mem_input.c | 3 + .../display/dc/dce110/dce110_timing_generator.h | 3 + drivers/gpu/drm/amd/display/dc/dce120/Makefile | 12 ++ .../gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 3 + drivers/gpu/drm/amd/display/dc/dm_services.h | 89 ++++++++++++ drivers/gpu/drm/amd/display/dc/dm_services_types.h | 27 ++++ drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 ++ drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 ++ drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 +- drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 ++ drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 ++ .../gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 3 + .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 23 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 4 + drivers/gpu/drm/amd/display/dc/irq/Makefile | 12 ++ drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 3 + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 4 + drivers/gpu/drm/amd/display/include/dal_types.h | 3 + 44 files changed, 1143 insertions(+), 8 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/dce120/Makefile (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2efb486e283d..96955c9b4cdf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1984,8 +1984,12 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_STONEY: case CHIP_POLARIS11: case CHIP_POLARIS10: + case CHIP_POLARIS12: case CHIP_TONGA: case CHIP_FIJI: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: +#endif #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; #else diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 47c8e2940a91..32826a0eafe7 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,6 +17,13 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. +config DRM_AMD_DC_DCE12_0 + bool "Vega10 family" + depends on DRM_AMD_DC + help + Choose this option if you want to have + VG family for display engine. + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a69ce27b8ed6..9157772a0af3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -888,6 +888,10 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) struct dc_interrupt_params int_params = {0}; int r; int i; + unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; + + if (adev->asic_type == CHIP_VEGA10) + client_id = AMDGPU_IH_CLIENTID_DCE; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; @@ -904,7 +908,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) /* Use VBLANK interrupt */ for (i = 1; i <= adev->mode_info.num_crtc; i++) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->crtc_irq); + r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); if (r) { DRM_ERROR("Failed to add crtc irq id!\n"); @@ -927,7 +931,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) /* Use GRPH_PFLIP interrupt */ for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) { - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq); + r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq); if (r) { DRM_ERROR("Failed to add page flip irq id!\n"); return r; @@ -948,8 +952,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) } /* HPD */ - r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, - &adev->hpd_irq); + r = amdgpu_irq_add_id(adev, client_id, + VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq); if (r) { DRM_ERROR("Failed to add hpd irq id!\n"); return r; @@ -1119,6 +1123,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: +#endif if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); return -1; @@ -1312,6 +1319,7 @@ static const struct amdgpu_display_funcs dm_display_funcs = { }; + #if defined(CONFIG_DEBUG_KERNEL_DC) static ssize_t s3_debug_store( @@ -1384,6 +1392,13 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case CHIP_VEGA10: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index 1ddc56cfbdc4..df53092abc39 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -402,6 +402,16 @@ bool dm_pp_notify_wm_clock_changes( return false; } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dm_pp_notify_wm_clock_changes_soc15( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) +{ + /* TODO: to be implemented */ + return false; +} +#endif + bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, struct dm_pp_power_level_change_request *level_change_req) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 098a801ae745..01aaf968854d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -494,7 +494,7 @@ static void fill_plane_attributes_from_fb( memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - /* Fill GFX8 params */ + /* Fill GFX params */ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { unsigned bankw, bankh, mtaspect, tile_split, num_banks; @@ -523,6 +523,26 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + if (adev->asic_type == CHIP_VEGA10) { + /* Fill GFX9 params */ + surface->tiling_info.gfx9.num_pipes = + adev->gfx.config.gb_addr_config_fields.num_pipes; + surface->tiling_info.gfx9.num_banks = + adev->gfx.config.gb_addr_config_fields.num_banks; + surface->tiling_info.gfx9.pipe_interleave = + adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; + surface->tiling_info.gfx9.num_shader_engines = + adev->gfx.config.gb_addr_config_fields.num_se; + surface->tiling_info.gfx9.max_compressed_frags = + adev->gfx.config.gb_addr_config_fields.max_compress_frags; + surface->tiling_info.gfx9.swizzle = + AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); + surface->tiling_info.gfx9.shaderEnable = 1; + } +#endif + + surface->plane_size.grph.surface_size.x = 0; surface->plane_size.grph.surface_size.y = 0; surface->plane_size.grph.surface_size.width = fb->width; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 2df163bc83e9..a580cab6bf56 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,6 +4,10 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +DC_LIBS += dce120 +endif + DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 876614d37412..770248429a81 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -4,6 +4,10 @@ BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +BIOS += command_table2.o command_table_helper2.o bios_parser2.o +endif + AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) AMD_DISPLAY_FILES += $(AMD_DAL_BIOS) @@ -21,3 +25,7 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce80/command_table_helper_dce80.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o + +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o +endif diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c index 42272c35df2d..7fe2a791ef42 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c @@ -29,6 +29,10 @@ #include "bios_parser_interface.h" #include "bios_parser.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "bios_parser2.h" +#endif + struct dc_bios *dal_bios_parser_create( struct bp_init_data *init, @@ -36,7 +40,17 @@ struct dc_bios *dal_bios_parser_create( { struct dc_bios *bios = NULL; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bios = firmware_parser_create(init, dce_version); + + if (bios == NULL) + /* TODO: remove dce_version from bios_parser. + * cannot remove today because dal enum to bp enum translation is dce specific + */ + bios = bios_parser_create(init, dce_version); +#else bios = bios_parser_create(init, dce_version); +#endif return bios; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index ab8d1e931846..aa98762346d2 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -50,6 +50,11 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi return BW_CALCS_VERSION_POLARIS11; return BW_CALCS_VERSION_INVALID; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case FAMILY_AI: + return BW_CALCS_VERSION_VEGA10; +#endif + default: return BW_CALCS_VERSION_INVALID; } @@ -2430,6 +2435,118 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case BW_CALCS_VERSION_VEGA10: + vbios.memory_type = bw_def_hbm; + vbios.dram_channel_width_in_bits = 128; + vbios.number_of_dram_channels = asic_id.vram_width / vbios.dram_channel_width_in_bits; + vbios.number_of_dram_banks = 16; + vbios.high_yclk = bw_int_to_fixed(2400); + vbios.mid_yclk = bw_int_to_fixed(1700); + vbios.low_yclk = bw_int_to_fixed(1000); + vbios.low_sclk = bw_int_to_fixed(300); + vbios.mid1_sclk = bw_int_to_fixed(350); + vbios.mid2_sclk = bw_int_to_fixed(400); + vbios.mid3_sclk = bw_int_to_fixed(500); + vbios.mid4_sclk = bw_int_to_fixed(600); + vbios.mid5_sclk = bw_int_to_fixed(700); + vbios.mid6_sclk = bw_int_to_fixed(760); + vbios.high_sclk = bw_int_to_fixed(776); + vbios.low_voltage_max_dispclk = bw_int_to_fixed(460); + vbios.mid_voltage_max_dispclk = bw_int_to_fixed(670); + vbios.high_voltage_max_dispclk = bw_int_to_fixed(1133); + vbios.low_voltage_max_phyclk = bw_int_to_fixed(540); + vbios.mid_voltage_max_phyclk = bw_int_to_fixed(810); + vbios.high_voltage_max_phyclk = bw_int_to_fixed(810); + vbios.data_return_bus_width = bw_int_to_fixed(32); + vbios.trc = bw_int_to_fixed(48); + vbios.dmifmc_urgent_latency = bw_int_to_fixed(3); + vbios.stutter_self_refresh_exit_latency = bw_frc_to_fixed(75, 10); + vbios.stutter_self_refresh_entry_latency = bw_frc_to_fixed(19, 10); + vbios.nbp_state_change_latency = bw_int_to_fixed(39); + vbios.mcifwrmc_urgent_latency = bw_int_to_fixed(10); + vbios.scatter_gather_enable = false; + vbios.down_spread_percentage = bw_frc_to_fixed(5, 10); + vbios.cursor_width = 32; + vbios.average_compression_rate = 4; + vbios.number_of_request_slots_gmc_reserves_for_dmif_per_channel = 8; + vbios.blackout_duration = bw_int_to_fixed(0); /* us */ + vbios.maximum_blackout_recovery_time = bw_int_to_fixed(0); + + dceip.large_cursor = false; + dceip.dmif_request_buffer_size = bw_int_to_fixed(2304); + dceip.dmif_pipe_en_fbc_chunk_tracker = true; + dceip.cursor_max_outstanding_group_num = 1; + dceip.lines_interleaved_into_lb = 2; + dceip.chunk_width = 256; + dceip.number_of_graphics_pipes = 6; + dceip.number_of_underlay_pipes = 0; + dceip.low_power_tiling_mode = 0; + dceip.display_write_back_supported = true; + dceip.argb_compression_support = true; + dceip.underlay_vscaler_efficiency6_bit_per_component = + bw_frc_to_fixed(35556, 10000); + dceip.underlay_vscaler_efficiency8_bit_per_component = + bw_frc_to_fixed(34286, 10000); + dceip.underlay_vscaler_efficiency10_bit_per_component = + bw_frc_to_fixed(32, 10); + dceip.underlay_vscaler_efficiency12_bit_per_component = + bw_int_to_fixed(3); + dceip.graphics_vscaler_efficiency6_bit_per_component = + bw_frc_to_fixed(35, 10); + dceip.graphics_vscaler_efficiency8_bit_per_component = + bw_frc_to_fixed(34286, 10000); + dceip.graphics_vscaler_efficiency10_bit_per_component = + bw_frc_to_fixed(32, 10); + dceip.graphics_vscaler_efficiency12_bit_per_component = + bw_int_to_fixed(3); + dceip.alpha_vscaler_efficiency = bw_int_to_fixed(3); + dceip.max_dmif_buffer_allocated = 4; + dceip.graphics_dmif_size = 24576; + dceip.underlay_luma_dmif_size = 19456; + dceip.underlay_chroma_dmif_size = 23552; + dceip.pre_downscaler_enabled = true; + dceip.underlay_downscale_prefetch_enabled = false; + dceip.lb_write_pixels_per_dispclk = bw_int_to_fixed(1); + dceip.lb_size_per_component444 = bw_int_to_fixed(245952); + dceip.graphics_lb_nodownscaling_multi_line_prefetching = true; + dceip.stutter_and_dram_clock_state_change_gated_before_cursor = + bw_int_to_fixed(1); + dceip.underlay420_luma_lb_size_per_component = bw_int_to_fixed( + 82176); + dceip.underlay420_chroma_lb_size_per_component = + bw_int_to_fixed(164352); + dceip.underlay422_lb_size_per_component = bw_int_to_fixed( + 82176); + dceip.cursor_chunk_width = bw_int_to_fixed(64); + dceip.cursor_dcp_buffer_lines = bw_int_to_fixed(4); + dceip.underlay_maximum_width_efficient_for_tiling = + bw_int_to_fixed(1920); + dceip.underlay_maximum_height_efficient_for_tiling = + bw_int_to_fixed(1080); + dceip.peak_pte_request_to_eviction_ratio_limiting_multiple_displays_or_single_rotated_display = + bw_frc_to_fixed(3, 10); + dceip.peak_pte_request_to_eviction_ratio_limiting_single_display_no_rotation = + bw_int_to_fixed(25); + dceip.minimum_outstanding_pte_request_limit = bw_int_to_fixed( + 2); + dceip.maximum_total_outstanding_pte_requests_allowed_by_saw = + bw_int_to_fixed(128); + dceip.limit_excessive_outstanding_dmif_requests = true; + dceip.linear_mode_line_request_alternation_slice = + bw_int_to_fixed(64); + dceip.scatter_gather_lines_of_pte_prefetching_in_linear_mode = + 32; + dceip.display_write_back420_luma_mcifwr_buffer_size = 12288; + dceip.display_write_back420_chroma_mcifwr_buffer_size = 8192; + dceip.request_efficiency = bw_frc_to_fixed(8, 10); + dceip.dispclk_per_request = bw_int_to_fixed(2); + dceip.dispclk_ramping_factor = bw_frc_to_fixed(105, 100); + dceip.display_pipe_throughput_factor = bw_frc_to_fixed(105, 100); + dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; + dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); + break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b9ca9688f8a3..28ed8eaee1ff 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1815,3 +1815,32 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) +{ + int i; + struct core_dc *core_dc = DC_TO_CORE(dc); + struct mem_input *mi = NULL; + + for (i = 0; i < core_dc->res_pool->pipe_count; i++) { + if (core_dc->res_pool->mis[i] != NULL) { + mi = core_dc->res_pool->mis[i]; + break; + } + } + if (mi == NULL) { + dm_error("no mem_input!\n"); + return false; + } + + if (mi->funcs->mem_input_update_dchub) + mi->funcs->mem_input_update_dchub(mi, dh_data); + else + ASSERT(mi->funcs->mem_input_update_dchub); + + + return true; + +} +#endif + diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 85ddf5fc4291..079558ab81c0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -141,6 +141,12 @@ void pre_surface_trace( surface->format, surface->rotation, surface->stereo_format); + +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + surface->tiling_info.gfx9.swizzle); +#endif + SURFACE_TRACE("\n"); } SURFACE_TRACE("\n"); @@ -221,6 +227,11 @@ void update_surface_trace( update->plane_info->tiling_info.gfx8.pipe_config, update->plane_info->tiling_info.gfx8.array_mode, update->plane_info->visible); + + #if defined (CONFIG_DRM_AMD_DC_DCE12_0) + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + update->plane_info->tiling_info.gfx9.swizzle); + #endif } if (update->scaling_info) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 5ca72afe8f6f..f13da7c227f4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1217,6 +1217,25 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + uint32_t dp_phyclk_in_khz; + const struct clocks_value clocks_value = + pipe_ctx->dis_clk->cur_clocks_value; + + /* 27mhz = 27000000hz= 27000khz */ + dp_phyclk_in_khz = link_settings.link_rate * 27000; + + if (((clocks_value.max_non_dp_phyclk_in_khz != 0) && + (dp_phyclk_in_khz > clocks_value.max_non_dp_phyclk_in_khz)) || + (dp_phyclk_in_khz > clocks_value.max_dp_phyclk_in_khz)) { + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + dp_phyclk_in_khz, + false, + true); + } +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 6119973c7f0a..77ef3304d2bc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,6 +39,9 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/dce120_resource.h" +#endif enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) { @@ -65,6 +68,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) dc_version = DCE_VERSION_11_2; } break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case FAMILY_AI: + dc_version = DCE_VERSION_12_0; + break; +#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -97,6 +105,12 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce112_create_resource_pool( num_virtual_links, dc); break; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + res_pool = dce120_create_resource_pool( + num_virtual_links, dc); + break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c6c0cf500ae8..bc15065e489b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,6 +55,9 @@ struct dc_caps { struct dc_dcc_surface_param { enum surface_pixel_format format; struct dc_size surface_size; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + enum swizzle_mode_values swizzle_mode; +#endif enum dc_scan_direction scan; }; @@ -143,6 +146,9 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bool disable_pplib_clock_request; +#endif bool disable_clock_gate; bool disable_dmcu; bool force_abm_enable; @@ -157,6 +163,23 @@ struct dc { struct dc_debug debug; }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +enum frame_buffer_mode { + FRAME_BUFFER_MODE_LOCAL_ONLY = 0, + FRAME_BUFFER_MODE_ZFB_ONLY, + FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, +} ; + +struct dchub_init_data { + bool dchub_initialzied; + bool dchub_info_valid; + int64_t zfb_phys_addr_base; + int64_t zfb_mc_base_addr; + uint64_t zfb_size_in_byte; + enum frame_buffer_mode fb_mode; +}; +#endif + struct dc_init_data { struct hw_asic_id asic_id; void *driver; /* ctx */ @@ -177,6 +200,10 @@ struct dc *dc_create(const struct dc_init_data *init_params); void dc_destroy(struct dc **dc); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); +#endif + /******************************************************************************* * Surface Interfaces ******************************************************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 75e16ac70f5f..63813404276d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -259,6 +259,36 @@ enum tile_mode_values { DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, }; +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) +enum swizzle_mode_values { + DC_SW_LINEAR = 0, + DC_SW_256B_S = 1, + DC_SW_256_D = 2, + DC_SW_256_R = 3, + DC_SW_4KB_S = 5, + DC_SW_4KB_D = 6, + DC_SW_4KB_R = 7, + DC_SW_64KB_S = 9, + DC_SW_64KB_D = 10, + DC_SW_64KB_R = 11, + DC_SW_VAR_S = 13, + DC_SW_VAR_D = 14, + DC_SW_VAR_R = 15, + DC_SW_64KB_S_T = 17, + DC_SW_64KB_D_T = 18, + DC_SW_4KB_S_X = 21, + DC_SW_4KB_D_X = 22, + DC_SW_4KB_R_X = 23, + DC_SW_64KB_S_X = 25, + DC_SW_64KB_D_X = 26, + DC_SW_64KB_R_X = 27, + DC_SW_VAR_S_X = 29, + DC_SW_VAR_D_X = 30, + DC_SW_VAR_R_X = 31, + DC_SW_MAX +}; +#endif + union dc_tiling_info { struct { @@ -323,6 +353,22 @@ union dc_tiling_info { enum array_mode_values array_mode; } gfx8; +#if defined (CONFIG_DRM_AMD_DC_DCE12_0) + struct { + unsigned int num_pipes; + unsigned int num_banks; + unsigned int pipe_interleave; + unsigned int num_shader_engines; + unsigned int num_rb_per_se; + unsigned int max_compressed_frags; + bool shaderEnable; + + enum swizzle_mode_values swizzle; + bool meta_linear; + bool rb_aligned; + bool pipe_aligned; + } gfx9; +#endif }; /* Rotation angle */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 1d6a9da45ba6..f53dc157db97 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -585,6 +585,9 @@ static uint32_t dce110_get_pix_clk_dividers( pll_settings, pix_clk_params); break; case DCE_VERSION_11_2: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: +#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -868,6 +871,9 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: +#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index ac1febafcaa4..9c743e51c091 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -80,6 +80,20 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +static struct state_dependent_clocks dce120_max_clks_by_state[] = { +/*ClocksStateInvalid - should not be used*/ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ +{ .display_clk_khz = 0, .pixel_clk_khz = 0 }, +/*ClocksStateLow*/ +{ .display_clk_khz = 460000, .pixel_clk_khz = 400000 }, +/*ClocksStateNominal*/ +{ .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, +/*ClocksStatePerformance*/ +{ .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; +#endif + /* Starting point for each divider range.*/ enum dce_divider_range_start { DIVIDER_RANGE_01_START = 200, /* 2.00*/ @@ -483,6 +497,103 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) } } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +static bool dce_apply_clock_voltage_request( + struct display_clock *clk, + enum dm_pp_clock_type clocks_type, + int clocks_in_khz, + bool pre_mode_set, + bool update_dp_phyclk) +{ + struct dm_pp_clock_for_voltage_req clock_voltage_req = {0}; + + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + case DM_PP_CLOCK_TYPE_PIXELCLK: + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + break; + default: + BREAK_TO_DEBUGGER(); + return false; + } + + clock_voltage_req.clk_type = clocks_type; + clock_voltage_req.clocks_in_khz = clocks_in_khz; + + /* to pplib */ + if (pre_mode_set) { + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + if (clocks_in_khz > clk->cur_clocks_value.dispclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.dispclk_notify_pplib_done = true; + } else + clk->cur_clocks_value.dispclk_notify_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.dispclk_in_khz = clocks_in_khz; + break; + case DM_PP_CLOCK_TYPE_PIXELCLK: + if (clocks_in_khz > clk->cur_clocks_value.max_pixelclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.pixelclk_notify_pplib_done = true; + } else + clk->cur_clocks_value.pixelclk_notify_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.max_pixelclk_in_khz = clocks_in_khz; + break; + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + if (clocks_in_khz > clk->cur_clocks_value.max_non_dp_phyclk_in_khz) { + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + clk->cur_clocks_value.phyclk_notigy_pplib_done = true; + } else + clk->cur_clocks_value.phyclk_notigy_pplib_done = false; + /* no matter incrase or decrase clock, update current clock value */ + clk->cur_clocks_value.max_non_dp_phyclk_in_khz = clocks_in_khz; + break; + default: + ASSERT(0); + break; + } + } else { + switch (clocks_type) { + case DM_PP_CLOCK_TYPE_DISPLAY_CLK: + if (!clk->cur_clocks_value.dispclk_notify_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + case DM_PP_CLOCK_TYPE_PIXELCLK: + if (!clk->cur_clocks_value.pixelclk_notify_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + case DM_PP_CLOCK_TYPE_DISPLAYPHYCLK: + if (!clk->cur_clocks_value.phyclk_notigy_pplib_done) + dm_pp_apply_clock_for_voltage_request( + clk->ctx, &clock_voltage_req); + break; + default: + ASSERT(0); + break; + } + } + + if (update_dp_phyclk && (clocks_in_khz > + clk->cur_clocks_value.max_dp_phyclk_in_khz)) + clk->cur_clocks_value.max_dp_phyclk_in_khz = clocks_in_khz; + + return true; +} + +static const struct display_clock_funcs dce120_funcs = { + .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, + .apply_clock_voltage_request = dce_apply_clock_voltage_request, + .set_clock = dce112_set_clock +}; +#endif + static const struct display_clock_funcs dce112_funcs = { .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, .get_required_clocks_state = dce_get_required_clocks_state, @@ -623,6 +734,44 @@ struct display_clock *dce112_disp_clk_create( return &clk_dce->base; } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct display_clock *dce120_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask) +{ + struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; + + if (clk_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + memcpy(clk_dce->max_clks_by_state, + dce120_max_clks_by_state, + sizeof(dce120_max_clks_by_state)); + + dce_disp_clk_construct( + clk_dce, ctx, regs, clk_shift, clk_mask); + + clk_dce->base.funcs = &dce120_funcs; + + /* new in dce120 */ + if (!ctx->dc->debug.disable_pplib_clock_request && + dm_pp_get_clock_levels_by_type_with_voltage( + ctx, DM_PP_CLOCK_TYPE_DISPLAY_CLK, &clk_level_info) + && clk_level_info.num_levels) + clk_dce->max_displ_clk_in_khz = + clk_level_info.data[clk_level_info.num_levels - 1].clocks_in_khz; + else + clk_dce->max_displ_clk_in_khz = 1133000; + + return &clk_dce->base; +} +#endif + void dce_disp_clk_destroy(struct display_clock **disp_clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 020ab9d5434d..18787f6d4e2a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,6 +45,14 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ + CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ + CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ + CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#endif + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ @@ -118,6 +126,10 @@ struct dce_disp_clk { int gpu_pll_ss_divider; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* max disp_clk from PPLIB for max validation display clock*/ + int max_displ_clk_in_khz; +#endif }; @@ -139,6 +151,14 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct display_clock *dce120_disp_clk_create( + struct dc_context *ctx, + const struct dce_disp_clk_registers *regs, + const struct dce_disp_clk_shift *clk_shift, + const struct dce_disp_clk_mask *clk_mask); +#endif + void dce_disp_clk_destroy(struct display_clock **disp_clk); #endif /* _DCE_CLOCKS_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index 70e0652be071..ff7984b08095 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -186,6 +186,14 @@ struct dce_hwseq_registers { HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ + HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ + HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#endif + #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ type DCFEV_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index f337d607e36c..f6a1006a6472 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -31,6 +31,13 @@ #define TO_DCE110_LINK_ENC(link_encoder)\ container_of(link_encoder, struct dce110_link_encoder, base) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +/* Not found regs in dce120 spec + * BIOS_SCRATCH_2 + * DP_DPHY_INTERNAL_CTRL + */ +#endif + #define AUX_REG_LIST(id)\ SRI(AUX_CONTROL, DP_AUX, id), \ SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) @@ -79,6 +86,13 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + #define LE_DCE120_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SR(DCI_MEM_PWR_STATUS) +#endif + #define LE_DCE80_REG_LIST(id)\ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ LE_COMMON_REG_LIST_BASE(id) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index e14a21cedfd5..c494f712b5b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -187,6 +187,20 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, nbp_wm); } +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { + REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, + PSTATE_CHANGE_WATERMARK_MASK, wm_select); + + REG_UPDATE_3(DPG_PIPE_LOW_POWER_CONTROL, + PSTATE_CHANGE_ENABLE, 1, + PSTATE_CHANGE_URGENT_DURING_REQUEST, 1, + PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, 1); + + REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, + PSTATE_CHANGE_WATERMARK, nbp_wm); + } +#endif } static void program_stutter_watermark(struct mem_input *mi, @@ -196,6 +210,12 @@ static void program_stutter_watermark(struct mem_input *mi, REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_STUTTER_CONTROL2)) + REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, + STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); + else +#endif REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); } @@ -234,6 +254,21 @@ void dce_mem_input_program_display_marks(struct mem_input *mi, static void program_tiling(struct mem_input *mi, const union dc_tiling_info *info) { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ + REG_UPDATE_6(GRPH_CONTROL, + GRPH_SW_MODE, info->gfx9.swizzle, + GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), + GRPH_NUM_SHADER_ENGINES, log_2(info->gfx9.num_shader_engines), + GRPH_NUM_PIPES, log_2(info->gfx9.num_pipes), + GRPH_COLOR_EXPANSION_MODE, 1, + GRPH_SE_ENABLE, info->gfx9.shaderEnable); + /* TODO: DCP0_GRPH_CONTROL__GRPH_SE_ENABLE where to get info + GRPH_SE_ENABLE, 1, + GRPH_Z, 0); + */ + } +#endif if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index ec053c241901..9e18c2a34e85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -58,6 +58,15 @@ MI_DCE11_2_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define MI_DCE12_REG_LIST(id)\ + MI_DCE_BASE_REG_LIST(id),\ + MI_DCE_PTE_REG_LIST(id),\ + SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ + SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ + SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) +#endif + struct dce_mem_input_registers { /* DCP */ uint32_t GRPH_ENABLE; @@ -163,6 +172,31 @@ struct dce_mem_input_registers { MI_DCE11_2_MASK_SH_LIST(mask_sh),\ MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ + SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) + +#define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ + SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ + SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ + SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) + +#define MI_DCE12_MASK_SH_LIST(mask_sh)\ + MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ + MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ + MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ + MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) +#endif + #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ type GRPH_X_START; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index a5afc0298d6f..4784ced6fc80 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -107,6 +107,14 @@ enum dce110_opp_reg_type { SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ SRI(CONTROL, FMT_MEMORY, id) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define OPP_DCE_120_REG_LIST(id) \ + OPP_COMMON_REG_LIST_BASE(id), \ + SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ + SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ + SRI(CONTROL, FMT_MEMORY, id) +#endif + #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -197,6 +205,70 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ + OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\ + OPP_SF(DCFE0_DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\ + OPP_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\ + OPP_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\ + OPP_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ + OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ + OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ + OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ + OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ + OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ + OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) +#endif + #define OPP_REG_FIELD_LIST(type) \ type DCP_REGAMMA_MEM_PWR_DIS; \ type DCP_LUT_MEM_PWR_DIS; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 458a37000956..c784c1b961c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -187,6 +187,91 @@ #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB1, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB2, mask_sh),\ + SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB3, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC0_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_GENERIC_PACKET_CONTROL0, HDMI_GENERIC1_LINE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_PACKET_GEN_VERSION, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_KEEPOUT_MODE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_DATA_SCRAMBLE_EN, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, mask_sh),\ + SE_SF(DIG0_AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_GC, HDMI_GC_AVMUTE, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_X, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_CNTL, DP_MSE_RATE_Y, mask_sh),\ + SE_SF(DP0_DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP1_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_MPG_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, mask_sh),\ + SE_SF(DP0_DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, mask_sh),\ + SE_SF(DP0_DP_STEER_FIFO, DP_STEER_FIFO_RESET, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\ + SE_SF(DP0_DP_VID_N, DP_VID_N, mask_sh),\ + SE_SF(DP0_DP_VID_M, DP_VID_M, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, DIG_START, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, mask_sh),\ + SE_SF(DIG0_HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL2, AFMT_60958_OSF_OVRD, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUDIO_PRIORITY, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_0, HDMI_ACR_CTS_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_32_1, HDMI_ACR_N_32, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_0, HDMI_ACR_CTS_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_44_1, HDMI_ACR_N_44, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_0, HDMI_ACR_CTS_48, mask_sh),\ + SE_SF(DIG0_HDMI_ACR_48_1, HDMI_ACR_N_48, mask_sh),\ + SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, mask_sh),\ + SE_SF(DIG0_AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, mask_sh),\ + SE_SF(DIG0_AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, mask_sh),\ + SE_SF(DIG0_AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, mask_sh),\ + SE_SF(DP0_DP_SEC_AUD_N, DP_SEC_AUD_N, mask_sh),\ + SE_SF(DP0_DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ASP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ATP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AIP_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_ACM_ENABLE, mask_sh),\ + SE_SF(DIG0_AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, mask_sh),\ + SE_SF(DIG0_AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, mask_sh),\ + SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ + SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) +#endif + +#define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) + #define SE_COMMON_MASK_SH_LIST_DCE80_100(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh),\ SE_SF(TMDS_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ @@ -209,6 +294,21 @@ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC2_UPDATE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_DYN_RANGE, mask_sh),\ + SE_SF(DP0_DP_PIXEL_FORMAT, DP_YCBCR_RANGE, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, mask_sh),\ + SE_SF(DIG0_HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ + SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#endif + struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; uint8_t AFMT_GENERIC0_UPDATE; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index b2cf9bfb0094..aa6bc4fc80c5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -153,6 +153,74 @@ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \ + XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \ + XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \ + XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \ + XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \ + XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \ + XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \ + XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \ + XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \ + XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \ + XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \ + XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \ + XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \ + XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \ + XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \ + XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ + XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ + XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) +#endif + #define XFM_REG_FIELD_LIST(type) \ type OUT_CLAMP_MIN_B_CB; \ type OUT_CLAMP_MAX_B_CB; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 041830e05b67..66d5f346f195 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1396,9 +1396,12 @@ static uint32_t get_max_pixel_clock_for_all_paths( return max_pix_clk; } -/* - * Find clock state based on clock requested. if clock value is 0, simply +/* Find clock state based on clock requested. if clock value is 0, simply * set clock state as requested without finding clock state by clock value + *TODO: when dce120_hw_sequencer.c is created, override apply_min_clock. + * + * TODOFPGA remove TODO after implement dal_display_clock_get_cur_clocks_value + * etc support for dcn1.0 */ static void apply_min_clocks( struct core_dc *dc, @@ -1425,6 +1428,30 @@ static void apply_min_clocks( } /* TODOFPGA */ +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* TODO: This is incorrect. Figure out how to fix. */ + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + pipe_ctx->dis_clk->cur_clocks_value.dispclk_in_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_PIXELCLK, + pipe_ctx->dis_clk->cur_clocks_value.max_pixelclk_in_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + pipe_ctx->dis_clk->cur_clocks_value.max_non_dp_phyclk_in_khz, + pre_mode_set, + false); + return; +#endif } /* get the required state based on state dependent clocks: @@ -1441,6 +1468,28 @@ static void apply_min_clocks( pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, *clocks_state); } else { +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAY_CLK, + req_clocks.display_clk_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_PIXELCLK, + req_clocks.pixel_clk_khz, + pre_mode_set, + false); + + pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( + pipe_ctx->dis_clk, + DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, + req_clocks.pixel_clk_khz, + pre_mode_set, + false); +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index 1643fb5d4b04..3ffb845f843a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -409,6 +409,9 @@ static struct mem_input_funcs dce110_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + .mem_input_update_dchub = NULL +#endif }; /*****************************************/ /* Constructor, Destructor */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index dcb49fe452c5..55f0a94e7cae 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -108,6 +108,9 @@ struct dce110_timing_generator { uint32_t min_h_front_porch; uint32_t min_h_back_porch; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + /* DCE 12 */ +#endif uint32_t min_h_sync_width; uint32_t min_v_sync_width; uint32_t min_v_blank; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/Makefile b/drivers/gpu/drm/amd/display/dc/dce120/Makefile new file mode 100644 index 000000000000..3c6b3fa98ddc --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dce120/Makefile @@ -0,0 +1,12 @@ +# +# Makefile for the 'controller' sub-component of DAL. +# It provides the control and status of HW CRTC block. + + +DCE120 = dce120_resource.o dce120_timing_generator.o \ +dce120_ipp.o dce120_ipp_cursor.o dce120_ipp_gamma.o \ +dce120_mem_input.o dce120_hw_sequencer.o + +AMD_DAL_DCE120 = $(addprefix $(AMDDALPATH)/dc/dce120/,$(DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_DCE120) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index 704a7ce62080..2f22931f457b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -54,6 +54,9 @@ static struct mem_input_funcs dce80_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + .mem_input_update_dchub = NULL +#endif }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index 73c0f1f83999..bdc7cb045eed 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,6 +192,89 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + +/* These macros need to be used with soc15 registers in order to retrieve + * the actual offset. + */ +#define REG_OFFSET(reg) (reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX]) +#define REG_BIF_OFFSET(reg) (reg + NBIF_BASE.instance[0].segment[reg##_BASE_IDX]) + +#define dm_write_reg_soc15(ctx, reg, inst_offset, value) \ + dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) + +#define dm_read_reg_soc15(ctx, reg, inst_offset) \ + dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) + +#define generic_reg_update_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ + dm_read_reg_func(ctx, mm##reg_name + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + inst_offset, __func__), \ + n, __VA_ARGS__) + +#define generic_reg_set_soc15(ctx, inst_offset, reg_name, n, ...)\ + generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ + n, __VA_ARGS__) + +#define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ + get_reg_field_value_ex(\ + (reg_value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +#define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ + (reg_value) = set_reg_field_value_ex(\ + (reg_value),\ + (value),\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ + block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) + +/* TODO get rid of this pos*/ +static inline bool wait_reg_func( + const struct dc_context *ctx, + uint32_t addr, + uint32_t mask, + uint8_t shift, + uint32_t condition_value, + unsigned int interval_us, + unsigned int timeout_us) +{ + uint32_t field_value; + uint32_t reg_val; + unsigned int count = 0; + + if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) + timeout_us *= 655; /* 6553 give about 30 second before time out */ + + do { + /* try once without sleeping */ + if (count > 0) { + if (interval_us >= 1000) + msleep(interval_us/1000); + else + udelay(interval_us); + } + reg_val = dm_read_reg(ctx, addr); + field_value = get_reg_field_value_ex(reg_val, mask, shift); + count += interval_us; + + } while (field_value != condition_value && count <= timeout_us); + + ASSERT(count <= timeout_us); + + return count <= timeout_us; +} + +#define wait_reg(ctx, inst_offset, reg_name, reg_field, condition_value)\ + wait_reg_func(\ + ctx,\ + mm##reg_name + inst_offset + DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX],\ + reg_name ## __ ## reg_field ## _MASK,\ + reg_name ## __ ## reg_field ## __SHIFT,\ + condition_value,\ + 20000,\ + 200000) + +#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -254,6 +337,12 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +bool dm_pp_notify_wm_clock_changes_soc15( + const struct dc_context *ctx, + struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); +#endif + /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned * by dc_service_pp_pre_dce_clock_change(), in the 'output' parameter. diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 460971dc3a70..8d2661583f21 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -141,6 +141,33 @@ struct dm_pp_wm_sets_with_clock_ranges { struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; }; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct dm_pp_clock_range_for_dmif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_dcfclk_clk_in_khz; + uint32_t wm_max_dcfclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_clock_range_for_mcif_wm_set_soc15 { + enum dm_pp_wm_set_id wm_set_id; + uint32_t wm_min_socclk_clk_in_khz; + uint32_t wm_max_socclk_clk_in_khz; + uint32_t wm_min_memg_clk_in_khz; + uint32_t wm_max_mem_clk_in_khz; +}; + +struct dm_pp_wm_sets_with_clock_ranges_soc15 { + uint32_t num_wm_dmif_sets; + uint32_t num_wm_mcif_sets; + struct dm_pp_clock_range_for_dmif_wm_set_soc15 + wm_dmif_clocks_ranges[MAX_WM_SETS]; + struct dm_pp_clock_range_for_mcif_wm_set_soc15 + wm_mcif_clocks_ranges[MAX_WM_SETS]; +}; +#endif + #define MAX_DISPLAY_CONFIGS 6 struct dm_pp_display_configuration { diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index a15c257fd2fa..8cf12a8ca28f 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -28,6 +28,17 @@ AMD_DAL_GPIO_DCE110 = $(addprefix $(AMDDALPATH)/dc/gpio/dce110/,$(GPIO_DCE110)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110) +############################################################################### +# DCE 12x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o + +AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index f1a6fa7391c6..66ea3b31b980 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -44,6 +44,10 @@ #include "dce110/hw_factory_dce110.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/hw_factory_dce120.h" +#endif + #include "diagnostics/hw_factory_diag.h" /* @@ -72,6 +76,11 @@ bool dal_hw_factory_init( case DCE_VERSION_11_2: dal_hw_factory_dce110_init(factory); return true; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + dal_hw_factory_dce120_init(factory); + return true; +#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 23e097fa5ace..10e86447f179 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -42,7 +42,9 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" - +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/hw_translate_dce120.h" +#endif #include "diagnostics/hw_translate_diag.h" /* @@ -68,6 +70,11 @@ bool dal_hw_translate_init( case DCE_VERSION_11_2: dal_hw_translate_dce110_init(translate); return true; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + dal_hw_translate_dce120_init(translate); + return true; +#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 83dfc437aae4..99aa5d8fb9a7 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -47,6 +47,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) +############################################################################### +# DCE 120 family +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +I2CAUX_DCE120 = i2caux_dce120.o + +AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120)) + +AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 5391655af23a..ea3bd75e0555 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -57,6 +57,10 @@ #include "dce112/i2caux_dce112.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/i2caux_dce120.h" +#endif + #include "diagnostics/i2caux_diag.h" /* @@ -80,6 +84,10 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce110_create(ctx); case DCE_VERSION_10_0: return dal_i2caux_dce100_create(ctx); + #if defined(CONFIG_DRM_AMD_DC_DCE12_0) + case DCE_VERSION_12_0: + return dal_i2caux_dce120_create(ctx); + #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h index 16f06fa2d69c..a7eaecd32aea 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -40,6 +40,9 @@ enum bw_calcs_version { BW_CALCS_VERSION_POLARIS10, BW_CALCS_VERSION_POLARIS11, BW_CALCS_VERSION_STONEY, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + BW_CALCS_VERSION_VEGA10 +#endif }; /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index e163f5818dd9..bf77aa6172e1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -28,6 +28,18 @@ #include "dm_services_types.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +struct clocks_value { + int dispclk_in_khz; + int max_pixelclk_in_khz; + int max_non_dp_phyclk_in_khz; + int max_dp_phyclk_in_khz; + bool dispclk_notify_pplib_done; + bool pixelclk_notify_pplib_done; + bool phyclk_notigy_pplib_done; +}; +#endif + /* Structure containing all state-dependent clocks * (dependent on "enum clocks_state") */ struct state_dependent_clocks { @@ -41,6 +53,9 @@ struct display_clock { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + struct clocks_value cur_clocks_value; +#endif }; struct display_clock_funcs { @@ -56,6 +71,14 @@ struct display_clock_funcs { int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + bool (*apply_clock_voltage_request)( + struct display_clock *disp_clk, + enum dm_pp_clock_type clocks_type, + int clocks_in_khz, + bool pre_mode_set, + bool update_dp_phyclk); +#endif }; #endif /* __DISPLAY_CLOCK_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index ed980aed1677..6c0600696d02 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -100,6 +100,10 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + void (*mem_input_update_dchub)(struct mem_input *mem_input, + struct dchub_init_data *dh_data); +#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 02710333ce0a..140e49811dd1 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -26,3 +26,15 @@ IRQ_DCE11 = irq_service_dce110.o AMD_DAL_IRQ_DCE11 = $(addprefix $(AMDDALPATH)/dc/irq/dce110/,$(IRQ_DCE11)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11) + +############################################################################### +# DCE 12x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCE12_0 +IRQ_DCE12 = irq_service_dce120.o + +AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) +endif + diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index fbaa2fc00ddb..a1b6d83b1cbb 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -33,6 +33,9 @@ #include "dce80/irq_service_dce80.h" +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#include "dce120/irq_service_dce120.h" +#endif #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 46f1e88f5e27..15c0b8c14b30 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -123,6 +123,10 @@ #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ #define FAMILY_CZ 135 /* Carrizo */ +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) +#define FAMILY_AI 141 +#endif + #define FAMILY_UNKNOWN 0xFF #endif /* __DAL_ASIC_ID_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index ada5b19e85eb..e24c1ef58d2f 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -38,6 +38,9 @@ enum dce_version { DCE_VERSION_10_0, DCE_VERSION_11_0, DCE_VERSION_11_2, +#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + DCE_VERSION_12_0, +#endif DCE_VERSION_MAX, }; -- cgit v1.2.3 From 8fa9ca2ec6919656db87391a1633692ee8d57c22 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:21:43 -0400 Subject: drm/amd/display: Remove DCE12 guards Signed-off-by: Jordan Lazare Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 -- drivers/gpu/drm/amd/display/Kconfig | 7 ------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 2 -- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 2 -- drivers/gpu/drm/amd/display/dc/Makefile | 3 --- drivers/gpu/drm/amd/display/dc/bios/Makefile | 4 ---- .../drm/amd/display/dc/bios/bios_parser_interface.c | 10 +--------- .../drm/amd/display/dc/bios/command_table_helper2.c | 2 -- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 4 ---- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 6 +----- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 6 ------ drivers/gpu/drm/amd/display/dc/dc.h | 8 -------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 6 ------ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 6 ------ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 18 +++++++----------- drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 8 ++------ drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_opp.h | 4 ---- .../gpu/drm/amd/display/dc/dce/dce_stream_encoder.h | 4 ---- drivers/gpu/drm/amd/display/dc/dce/dce_transform.h | 2 -- .../drm/amd/display/dc/dce110/dce110_hw_sequencer.c | 5 ----- .../gpu/drm/amd/display/dc/dce110/dce110_mem_input.c | 2 -- .../amd/display/dc/dce110/dce110_timing_generator.h | 2 -- .../gpu/drm/amd/display/dc/dce120/dce120_resource.c | 14 +++++--------- drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c | 2 -- drivers/gpu/drm/amd/display/dc/dm_services.h | 4 ---- drivers/gpu/drm/amd/display/dc/dm_services_types.h | 2 -- drivers/gpu/drm/amd/display/dc/gpio/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 4 ---- drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 4 ---- drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 4 ---- drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h | 6 ------ drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 2 -- drivers/gpu/drm/amd/display/dc/irq/Makefile | 2 -- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 -- drivers/gpu/drm/amd/display/include/dal_asic_id.h | 2 -- drivers/gpu/drm/amd/display/include/dal_types.h | 2 -- 45 files changed, 16 insertions(+), 175 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 96955c9b4cdf..df95dd8439b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1987,9 +1987,7 @@ bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type) case CHIP_POLARIS12: case CHIP_TONGA: case CHIP_FIJI: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: -#endif #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA) return amdgpu_dc != 0; #else diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 32826a0eafe7..47c8e2940a91 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,13 +17,6 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. -config DRM_AMD_DC_DCE12_0 - bool "Vega10 family" - depends on DRM_AMD_DC - help - Choose this option if you want to have - VG family for display engine. - config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9157772a0af3..97d949affcfb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1123,9 +1123,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_POLARIS11: case CHIP_POLARIS10: case CHIP_POLARIS12: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: -#endif if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); return -1; @@ -1392,13 +1390,11 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case CHIP_VEGA10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; -#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index df53092abc39..a8a53b85905a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -402,7 +402,6 @@ bool dm_pp_notify_wm_clock_changes( return false; } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dm_pp_notify_wm_clock_changes_soc15( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges) @@ -410,7 +409,6 @@ bool dm_pp_notify_wm_clock_changes_soc15( /* TODO: to be implemented */ return false; } -#endif bool dm_pp_apply_power_level_change_request( const struct dc_context *ctx, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 01aaf968854d..1c1c643439b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -523,7 +523,6 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) if (adev->asic_type == CHIP_VEGA10) { /* Fill GFX9 params */ surface->tiling_info.gfx9.num_pipes = @@ -540,7 +539,6 @@ static void fill_plane_attributes_from_fb( AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); surface->tiling_info.gfx9.shaderEnable = 1; } -#endif surface->plane_size.grph.surface_size.x = 0; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index a580cab6bf56..1a79762425ea 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,10 +4,7 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual -ifdef CONFIG_DRM_AMD_DC_DCE12_0 DC_LIBS += dce120 -endif - DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/Makefile b/drivers/gpu/drm/amd/display/dc/bios/Makefile index 770248429a81..a26cc605462d 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/Makefile +++ b/drivers/gpu/drm/amd/display/dc/bios/Makefile @@ -4,9 +4,7 @@ BIOS = bios_parser.o bios_parser_interface.o bios_parser_helper.o command_table.o command_table_helper.o -ifdef CONFIG_DRM_AMD_DC_DCE12_0 BIOS += command_table2.o command_table_helper2.o bios_parser2.o -endif AMD_DAL_BIOS = $(addprefix $(AMDDALPATH)/dc/bios/,$(BIOS)) @@ -26,6 +24,4 @@ AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce110/command_table_helper_dce110.o AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper_dce112.o -ifdef CONFIG_DRM_AMD_DC_DCE12_0 AMD_DISPLAY_FILES += $(AMDDALPATH)/dc/bios/dce112/command_table_helper2_dce112.o -endif diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c index 7fe2a791ef42..0079a1e26efd 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_interface.c @@ -29,9 +29,7 @@ #include "bios_parser_interface.h" #include "bios_parser.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "bios_parser2.h" -#endif struct dc_bios *dal_bios_parser_create( @@ -40,17 +38,11 @@ struct dc_bios *dal_bios_parser_create( { struct dc_bios *bios = NULL; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bios = firmware_parser_create(init, dce_version); + /* Fall back to old bios parser for older asics */ if (bios == NULL) - /* TODO: remove dce_version from bios_parser. - * cannot remove today because dal enum to bp enum translation is dce specific - */ bios = bios_parser_create(init, dce_version); -#else - bios = bios_parser_create(init, dce_version); -#endif return bios; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index b0dcad260be6..1cc3df1d5698 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -53,11 +53,9 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCE_VERSION_11_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; -#endif default: /* Unsupported DCE */ diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index aa98762346d2..c855e49eb116 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -50,10 +50,8 @@ static enum bw_calcs_version bw_calcs_version_from_asic_id(struct hw_asic_id asi return BW_CALCS_VERSION_POLARIS11; return BW_CALCS_VERSION_INVALID; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case FAMILY_AI: return BW_CALCS_VERSION_VEGA10; -#endif default: return BW_CALCS_VERSION_INVALID; @@ -2435,7 +2433,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case BW_CALCS_VERSION_VEGA10: vbios.memory_type = bw_def_hbm; vbios.dram_channel_width_in_bits = 128; @@ -2546,7 +2543,6 @@ void bw_calcs_init(struct bw_calcs_dceip *bw_dceip, dceip.scatter_gather_pte_request_rows_in_tiling_mode = 2; dceip.mcifwr_all_surfaces_burst_time = bw_int_to_fixed(0); break; -#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 28ed8eaee1ff..d6041e842347 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1815,7 +1815,6 @@ void dc_link_remove_remote_sink(const struct dc_link *link, const struct dc_sink } } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) { int i; @@ -1842,5 +1841,4 @@ bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data) return true; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 079558ab81c0..fb48b8909e7f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -142,10 +142,8 @@ void pre_surface_trace( surface->rotation, surface->stereo_format); -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", surface->tiling_info.gfx9.swizzle); -#endif SURFACE_TRACE("\n"); } @@ -228,10 +226,8 @@ void update_surface_trace( update->plane_info->tiling_info.gfx8.array_mode, update->plane_info->visible); - #if defined (CONFIG_DRM_AMD_DC_DCE12_0) - SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", + SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", update->plane_info->tiling_info.gfx9.swizzle); - #endif } if (update->scaling_info) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index f13da7c227f4..74dd272d7452 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1217,7 +1217,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, DM_PP_CLOCKS_STATE_NOMINAL); } else { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) uint32_t dp_phyclk_in_khz; const struct clocks_value clocks_value = pipe_ctx->dis_clk->cur_clocks_value; @@ -1235,7 +1234,6 @@ static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) false, true); } -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 77ef3304d2bc..ad37d0efca2e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,9 +39,7 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/dce120_resource.h" -#endif enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) { @@ -68,11 +66,9 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) dc_version = DCE_VERSION_11_2; } break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case FAMILY_AI: dc_version = DCE_VERSION_12_0; break; -#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -105,12 +101,10 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce112_create_resource_pool( num_virtual_links, dc); break; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: res_pool = dce120_create_resource_pool( num_virtual_links, dc); break; -#endif default: break; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index bc15065e489b..106addc937ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,9 +55,7 @@ struct dc_caps { struct dc_dcc_surface_param { enum surface_pixel_format format; struct dc_size surface_size; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) enum swizzle_mode_values swizzle_mode; -#endif enum dc_scan_direction scan; }; @@ -146,9 +144,7 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool disable_pplib_clock_request; -#endif bool disable_clock_gate; bool disable_dmcu; bool force_abm_enable; @@ -163,7 +159,6 @@ struct dc { struct dc_debug debug; }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) enum frame_buffer_mode { FRAME_BUFFER_MODE_LOCAL_ONLY = 0, FRAME_BUFFER_MODE_ZFB_ONLY, @@ -178,7 +173,6 @@ struct dchub_init_data { uint64_t zfb_size_in_byte; enum frame_buffer_mode fb_mode; }; -#endif struct dc_init_data { struct hw_asic_id asic_id; @@ -200,9 +194,7 @@ struct dc *dc_create(const struct dc_init_data *init_params); void dc_destroy(struct dc **dc); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dc_init_dchub(struct dc *dc, struct dchub_init_data *dh_data); -#endif /******************************************************************************* * Surface Interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 63813404276d..33e3377f69fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -259,7 +259,6 @@ enum tile_mode_values { DC_ADDR_SURF_MICRO_TILING_NON_DISPLAY = 0x1, }; -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) enum swizzle_mode_values { DC_SW_LINEAR = 0, DC_SW_256B_S = 1, @@ -287,7 +286,6 @@ enum swizzle_mode_values { DC_SW_VAR_R_X = 31, DC_SW_MAX }; -#endif union dc_tiling_info { @@ -353,7 +351,6 @@ union dc_tiling_info { enum array_mode_values array_mode; } gfx8; -#if defined (CONFIG_DRM_AMD_DC_DCE12_0) struct { unsigned int num_pipes; unsigned int num_banks; @@ -368,7 +365,6 @@ union dc_tiling_info { bool rb_aligned; bool pipe_aligned; } gfx9; -#endif }; /* Rotation angle */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index f53dc157db97..bd4524ef3a37 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -585,9 +585,7 @@ static uint32_t dce110_get_pix_clk_dividers( pll_settings, pix_clk_params); break; case DCE_VERSION_11_2: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: -#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -871,9 +869,7 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: -#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 9c743e51c091..263f8900e39c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -80,7 +80,6 @@ static struct state_dependent_clocks dce112_max_clks_by_state[] = { /*ClocksStatePerformance*/ { .display_clk_khz = 1132000, .pixel_clk_khz = 600000 } }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) static struct state_dependent_clocks dce120_max_clks_by_state[] = { /*ClocksStateInvalid - should not be used*/ { .display_clk_khz = 0, .pixel_clk_khz = 0 }, @@ -92,7 +91,6 @@ static struct state_dependent_clocks dce120_max_clks_by_state[] = { { .display_clk_khz = 670000, .pixel_clk_khz = 600000 }, /*ClocksStatePerformance*/ { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } }; -#endif /* Starting point for each divider range.*/ enum dce_divider_range_start { @@ -497,7 +495,6 @@ static void dce_clock_read_ss_info(struct dce_disp_clk *clk_dce) } } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) static bool dce_apply_clock_voltage_request( struct display_clock *clk, enum dm_pp_clock_type clocks_type, @@ -592,7 +589,6 @@ static const struct display_clock_funcs dce120_funcs = { .apply_clock_voltage_request = dce_apply_clock_voltage_request, .set_clock = dce112_set_clock }; -#endif static const struct display_clock_funcs dce112_funcs = { .get_dp_ref_clk_frequency = dce_clocks_get_dp_ref_freq, @@ -734,7 +730,6 @@ struct display_clock *dce112_disp_clk_create( return &clk_dce->base; } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct display_clock *dce120_disp_clk_create( struct dc_context *ctx, const struct dce_disp_clk_registers *regs, @@ -770,7 +765,6 @@ struct display_clock *dce120_disp_clk_create( return &clk_dce->base; } -#endif void dce_disp_clk_destroy(struct display_clock **disp_clk) { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 18787f6d4e2a..2fd00e45395c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,13 +45,11 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ CLK_SF(DCCG_DFS_MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(DCCG_DFS_MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) -#endif #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ @@ -126,10 +124,8 @@ struct dce_disp_clk { int gpu_pll_ss_divider; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* max disp_clk from PPLIB for max validation display clock*/ int max_displ_clk_in_khz; -#endif }; @@ -151,13 +147,11 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct display_clock *dce120_disp_clk_create( struct dc_context *ctx, const struct dce_disp_clk_registers *regs, const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask); -#endif void dce_disp_clk_destroy(struct display_clock **disp_clk); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index ff7984b08095..c66585188ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -186,13 +186,11 @@ struct dce_hwseq_registers { HWSEQ_DCE10_MASK_SH_LIST(mask_sh),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define HWSEQ_DCE12_MASK_SH_LIST(mask_sh)\ HWSEQ_DCEF_MASK_SH_LIST(mask_sh, DCFE0_DCFE_),\ HWSEQ_BLND_MASK_SH_LIST(mask_sh, BLND0_BLND_),\ HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) -#endif #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index f6a1006a6472..25ba583dbb8f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -31,12 +31,10 @@ #define TO_DCE110_LINK_ENC(link_encoder)\ container_of(link_encoder, struct dce110_link_encoder, base) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* Not found regs in dce120 spec * BIOS_SCRATCH_2 * DP_DPHY_INTERNAL_CTRL */ -#endif #define AUX_REG_LIST(id)\ SRI(AUX_CONTROL, DP_AUX, id), \ @@ -86,16 +84,14 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) - #define LE_DCE120_REG_LIST(id)\ - LE_COMMON_REG_LIST_BASE(id), \ - SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ - SR(DCI_MEM_PWR_STATUS) -#endif +#define LE_DCE120_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SR(DCI_MEM_PWR_STATUS) - #define LE_DCE80_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) +#define LE_DCE80_REG_LIST(id)\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + LE_COMMON_REG_LIST_BASE(id) struct dce110_link_enc_aux_registers { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index c494f712b5b5..7acd87152811 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -187,7 +187,7 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, nbp_wm); } -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) + if (REG(DPG_PIPE_LOW_POWER_CONTROL)) { REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, wm_select); @@ -200,7 +200,6 @@ static void program_nbp_watermark(struct mem_input *mi, REG_UPDATE(DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, nbp_wm); } -#endif } static void program_stutter_watermark(struct mem_input *mi, @@ -210,12 +209,10 @@ static void program_stutter_watermark(struct mem_input *mi, REG_UPDATE(DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, wm_select); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) if (REG(DPG_PIPE_STUTTER_CONTROL2)) REG_UPDATE(DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); else -#endif REG_UPDATE(DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, stutter_mark); } @@ -254,7 +251,6 @@ void dce_mem_input_program_display_marks(struct mem_input *mi, static void program_tiling(struct mem_input *mi, const union dc_tiling_info *info) { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) if (mi->masks->GRPH_SW_MODE) { /* GFX9 */ REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, @@ -268,7 +264,7 @@ static void program_tiling(struct mem_input *mi, GRPH_Z, 0); */ } -#endif + if (mi->masks->GRPH_ARRAY_MODE) { /* GFX8 */ REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h index 9e18c2a34e85..6af533bdf98c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.h @@ -58,14 +58,12 @@ MI_DCE11_2_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define MI_DCE12_REG_LIST(id)\ MI_DCE_BASE_REG_LIST(id),\ MI_DCE_PTE_REG_LIST(id),\ SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id) -#endif struct dce_mem_input_registers { /* DCP */ @@ -172,7 +170,6 @@ struct dce_mem_input_registers { MI_DCE11_2_MASK_SH_LIST(mask_sh),\ MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ @@ -195,7 +192,6 @@ struct dce_mem_input_registers { MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_) -#endif #define MI_REG_FIELD_LIST(type) \ type GRPH_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h index 4784ced6fc80..03ce9ba50b64 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.h @@ -107,13 +107,11 @@ enum dce110_opp_reg_type { SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ SRI(CONTROL, FMT_MEMORY, id) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define OPP_DCE_120_REG_LIST(id) \ OPP_COMMON_REG_LIST_BASE(id), \ SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \ SRI(DCFE_MEM_PWR_STATUS, DCFE, id), \ SRI(CONTROL, FMT_MEMORY, id) -#endif #define OPP_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -205,7 +203,6 @@ enum dce110_opp_reg_type { OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\ OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\ OPP_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\ @@ -267,7 +264,6 @@ enum dce110_opp_reg_type { OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) -#endif #define OPP_REG_FIELD_LIST(type) \ type DCP_REGAMMA_MEM_PWR_DIS; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index c784c1b961c6..c2f4050fc6dc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -187,7 +187,6 @@ #define SE_COMMON_MASK_SH_LIST_DCE_COMMON(mask_sh)\ SE_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh)\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_INDEX, mask_sh),\ SE_SF(DIG0_AFMT_GENERIC_HDR, AFMT_GENERIC_HB0, mask_sh),\ @@ -267,7 +266,6 @@ SE_SF(DIG0_HDMI_CONTROL, HDMI_CLOCK_CHANNEL_RATE, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_PIXEL_ENCODING, mask_sh),\ SE_SF(DIG0_DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh) -#endif #define SE_COMMON_MASK_SH_LIST_SOC(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) @@ -294,7 +292,6 @@ SE_SF(DIG_FE_CNTL, TMDS_COLOR_FORMAT, mask_sh),\ SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define SE_COMMON_MASK_SH_LIST_DCE120(mask_sh)\ SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC0_UPDATE, mask_sh),\ @@ -307,7 +304,6 @@ SE_SF(DP0_DP_SEC_CNTL, DP_SEC_AVI_ENABLE, mask_sh),\ SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) -#endif struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h index aa6bc4fc80c5..da2a02434665 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.h @@ -153,7 +153,6 @@ XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh) -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \ XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \ @@ -219,7 +218,6 @@ XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \ XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \ XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh) -#endif #define XFM_REG_FIELD_LIST(type) \ type OUT_CLAMP_MIN_B_CB; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 66d5f346f195..cb7a673e15e9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -1427,8 +1427,6 @@ static void apply_min_clocks( return; } - /* TODOFPGA */ -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* TODO: This is incorrect. Figure out how to fix. */ pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( pipe_ctx->dis_clk, @@ -1451,7 +1449,6 @@ static void apply_min_clocks( pre_mode_set, false); return; -#endif } /* get the required state based on state dependent clocks: @@ -1468,7 +1465,6 @@ static void apply_min_clocks( pipe_ctx->dis_clk->funcs->set_min_clocks_state( pipe_ctx->dis_clk, *clocks_state); } else { -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) pipe_ctx->dis_clk->funcs->apply_clock_voltage_request( pipe_ctx->dis_clk, DM_PP_CLOCK_TYPE_DISPLAY_CLK, @@ -1489,7 +1485,6 @@ static void apply_min_clocks( req_clocks.pixel_clk_khz, pre_mode_set, false); -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c index 3ffb845f843a..a20feaedfca4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_mem_input.c @@ -409,9 +409,7 @@ static struct mem_input_funcs dce110_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) .mem_input_update_dchub = NULL -#endif }; /*****************************************/ /* Constructor, Destructor */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index 55f0a94e7cae..378509b8e56c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -108,9 +108,7 @@ struct dce110_timing_generator { uint32_t min_h_front_porch; uint32_t min_h_back_porch; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* DCE 12 */ -#endif uint32_t min_h_sync_width; uint32_t min_v_sync_width; uint32_t min_v_blank; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 9a1984b36592..efa58889058b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -909,6 +909,7 @@ static bool construct( { unsigned int i; struct dc_context *ctx = dc->ctx; + struct irq_service_init_data irq_init_data; ctx->dc_bios->regs = &bios_regs; @@ -997,15 +998,10 @@ static bool construct( goto res_create_fail; } - { - #if defined(CONFIG_DRM_AMD_DC_DCE12_0) - struct irq_service_init_data init_data; - init_data.ctx = dc->ctx; - pool->base.irqs = dal_irq_service_dce120_create(&init_data); - if (!pool->base.irqs) - goto irqs_create_fail; - #endif - } + irq_init_data.ctx = dc->ctx; + pool->base.irqs = dal_irq_service_dce120_create(&irq_init_data); + if (!pool->base.irqs) + goto irqs_create_fail; for (i = 0; i < pool->base.pipe_count; i++) { pool->base.timing_generators[i] = diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c index 2f22931f457b..ebb8df3cdf4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_mem_input.c @@ -54,9 +54,7 @@ static struct mem_input_funcs dce80_mem_input_funcs = { dce_mem_input_program_surface_config, .mem_input_is_flip_pending = dce110_mem_input_is_flip_pending, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) .mem_input_update_dchub = NULL -#endif }; /*****************************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index bdc7cb045eed..cf6ecfcadd5e 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -192,7 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx, unsigned int delay_between_poll_us, unsigned int time_out_num_tries, const char *func_name); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) /* These macros need to be used with soc15 registers in order to retrieve * the actual offset. @@ -274,7 +273,6 @@ static inline bool wait_reg_func( 20000,\ 200000) -#endif /************************************** * Power Play (PP) interfaces **************************************/ @@ -337,11 +335,9 @@ bool dm_pp_notify_wm_clock_changes( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges *wm_with_clock_ranges); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool dm_pp_notify_wm_clock_changes_soc15( const struct dc_context *ctx, struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges); -#endif /* DAL calls this function to notify PP about completion of Mode Set. * For PP it means that current DCE clocks are those which were returned diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 8d2661583f21..c631dec489e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -141,7 +141,6 @@ struct dm_pp_wm_sets_with_clock_ranges { struct dm_pp_clock_range_for_wm_set wm_clk_ranges[MAX_WM_SETS]; }; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct dm_pp_clock_range_for_dmif_wm_set_soc15 { enum dm_pp_wm_set_id wm_set_id; uint32_t wm_min_dcfclk_clk_in_khz; @@ -166,7 +165,6 @@ struct dm_pp_wm_sets_with_clock_ranges_soc15 { struct dm_pp_clock_range_for_mcif_wm_set_soc15 wm_mcif_clocks_ranges[MAX_WM_SETS]; }; -#endif #define MAX_DISPLAY_CONFIGS 6 diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 8cf12a8ca28f..5e831aff4830 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -31,13 +31,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE110) ############################################################################### # DCE 12x ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 GPIO_DCE120 = hw_translate_dce120.o hw_factory_dce120.o AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) -endif ############################################################################### # Diagnostics on FPGA diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 66ea3b31b980..29ba83d2c211 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -44,9 +44,7 @@ #include "dce110/hw_factory_dce110.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/hw_factory_dce120.h" -#endif #include "diagnostics/hw_factory_diag.h" @@ -76,11 +74,9 @@ bool dal_hw_factory_init( case DCE_VERSION_11_2: dal_hw_factory_dce110_init(factory); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: dal_hw_factory_dce120_init(factory); return true; -#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 10e86447f179..872edda54536 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -42,9 +42,7 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/hw_translate_dce120.h" -#endif #include "diagnostics/hw_translate_diag.h" /* @@ -70,11 +68,9 @@ bool dal_hw_translate_init( case DCE_VERSION_11_2: dal_hw_translate_dce110_init(translate); return true; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: dal_hw_translate_dce120_init(translate); return true; -#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index 99aa5d8fb9a7..a636768d06d5 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -50,13 +50,11 @@ AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) ############################################################################### # DCE 120 family ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 I2CAUX_DCE120 = i2caux_dce120.o AMD_DAL_I2CAUX_DCE120 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce120/,$(I2CAUX_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE120) -endif ############################################################################### # Diagnostics on FPGA diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index ea3bd75e0555..bd84b932aaae 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -57,9 +57,7 @@ #include "dce112/i2caux_dce112.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/i2caux_dce120.h" -#endif #include "diagnostics/i2caux_diag.h" @@ -84,10 +82,8 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce110_create(ctx); case DCE_VERSION_10_0: return dal_i2caux_dce100_create(ctx); - #if defined(CONFIG_DRM_AMD_DC_DCE12_0) case DCE_VERSION_12_0: return dal_i2caux_dce120_create(ctx); - #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h index a7eaecd32aea..81fab9ef3637 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/bandwidth_calcs.h @@ -40,9 +40,7 @@ enum bw_calcs_version { BW_CALCS_VERSION_POLARIS10, BW_CALCS_VERSION_POLARIS11, BW_CALCS_VERSION_STONEY, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) BW_CALCS_VERSION_VEGA10 -#endif }; /******************************************************************************* diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index bf77aa6172e1..79aa75c150ec 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -28,7 +28,6 @@ #include "dm_services_types.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct clocks_value { int dispclk_in_khz; int max_pixelclk_in_khz; @@ -38,7 +37,6 @@ struct clocks_value { bool pixelclk_notify_pplib_done; bool phyclk_notigy_pplib_done; }; -#endif /* Structure containing all state-dependent clocks * (dependent on "enum clocks_state") */ @@ -53,9 +51,7 @@ struct display_clock { enum dm_pp_clocks_state max_clks_state; enum dm_pp_clocks_state cur_min_clks_state; -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) struct clocks_value cur_clocks_value; -#endif }; struct display_clock_funcs { @@ -71,14 +67,12 @@ struct display_clock_funcs { int (*get_dp_ref_clk_frequency)(struct display_clock *disp_clk); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) bool (*apply_clock_voltage_request)( struct display_clock *disp_clk, enum dm_pp_clock_type clocks_type, int clocks_in_khz, bool pre_mode_set, bool update_dp_phyclk); -#endif }; #endif /* __DISPLAY_CLOCK_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 6c0600696d02..7ec4027700d8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -100,10 +100,8 @@ struct mem_input_funcs { bool (*mem_input_is_flip_pending)(struct mem_input *mem_input); -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) void (*mem_input_update_dchub)(struct mem_input *mem_input, struct dchub_init_data *dh_data); -#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 140e49811dd1..222f36e3074f 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -30,11 +30,9 @@ AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE11) ############################################################################### # DCE 12x ############################################################################### -ifdef CONFIG_DRM_AMD_DC_DCE12_0 IRQ_DCE12 = irq_service_dce120.o AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) -endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index a1b6d83b1cbb..5255c14254df 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -33,9 +33,7 @@ #include "dce80/irq_service_dce80.h" -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #include "dce120/irq_service_dce120.h" -#endif #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 15c0b8c14b30..6dab058f8f3c 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -123,9 +123,7 @@ #define FAMILY_VI 130 /* Volcanic Islands: Iceland (V), Tonga (M) */ #define FAMILY_CZ 135 /* Carrizo */ -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) #define FAMILY_AI 141 -#endif #define FAMILY_UNKNOWN 0xFF diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index e24c1ef58d2f..0cefde14aa02 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -38,9 +38,7 @@ enum dce_version { DCE_VERSION_10_0, DCE_VERSION_11_0, DCE_VERSION_11_2, -#if defined(CONFIG_DRM_AMD_DC_DCE12_0) DCE_VERSION_12_0, -#endif DCE_VERSION_MAX, }; -- cgit v1.2.3 From ce75805e0a63843af71a07e7e95443866e118af0 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 22 Feb 2017 14:24:11 -0500 Subject: drm/amd/display: Unhardcode cursor size reported back to UMD. This will return back MAX cursor size for given ASIC. Signed-off-by: Andrey Grodzovsky Reviewed-by: Jordan Lazare Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 97d949affcfb..c559c71d558e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -311,8 +311,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev) /* TODO: Add_display_info? */ /* TODO use dynamic cursor width */ - adev->ddev->mode_config.cursor_width = 128; - adev->ddev->mode_config.cursor_height = 128; + adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size; + adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size; if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) { DRM_ERROR( -- cgit v1.2.3 From e902915507bd20115e1e21bc99ea36ea7986cebc Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 23 Mar 2017 15:30:35 -0400 Subject: drm/amd/display: use CRTC_VERTICAL_INTERRUPT0 as a trigger for VBLANK. Register ISR hnadler on the new interrupt. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c559c71d558e..b08ec453b773 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -907,9 +907,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) * for acknowledging and handling. */ /* Use VBLANK interrupt */ - for (i = 1; i <= adev->mode_info.num_crtc; i++) { + for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) { r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq); - if (r) { DRM_ERROR("Failed to add crtc irq id!\n"); return r; -- cgit v1.2.3 From d4e13b0db124345be93bc2ff39ecb48409da2c9b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:24:01 -0400 Subject: drm/amd/display: decouple per-crtc-plane model Current design has per-crtc-plane model. As a result, for asic's that support underlay, are unable to expose it to user space for modesetting. To enable this, the drm driver intialisation now runs for number of surfaces instead of stream/crtc. This patch plumbs surface capabilities to drm framework so that it can be effectively used by user space. Tests: (On Chromium OS for Stoney Only) * 'modetest -p' now shows additional plane with YUV capabilities in case of CZ and ST. * 'plane_test' fails with below error: [drm:amdgpu_dm_connector_atomic_set_property [amdgpu]] *ERROR* Unsupported screen depth 0 as ther is no support for YUYV * Checked multimonitor display works fine Signed-off-by: Shirish S Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 +++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 67 ++++++++++++++----- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 76 +++++++++++++++------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 5 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../drm/amd/display/dc/dce100/dce100_resource.c | 2 + .../drm/amd/display/dc/dce110/dce110_resource.c | 2 + .../drm/amd/display/dc/dce112/dce112_resource.c | 2 + .../drm/amd/display/dc/dce120/dce120_resource.c | 2 + .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 + 10 files changed, 127 insertions(+), 40 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index e5d2ce48cb1e..362d9559f065 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -60,6 +60,7 @@ struct amdgpu_hpd; #define AMDGPU_MAX_HPD_PINS 6 #define AMDGPU_MAX_CRTCS 6 +#define AMDGPU_MAX_PLANES 6 #define AMDGPU_MAX_AFMT_BLOCKS 9 enum amdgpu_rmx_type { @@ -327,6 +328,7 @@ struct amdgpu_mode_info { struct card_info *atom_card_info; bool mode_config_initialized; struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; + struct amdgpu_plane *planes[AMDGPU_MAX_PLANES]; struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; /* DVI-I properties */ struct drm_property *coherent_mode_property; @@ -356,6 +358,7 @@ struct amdgpu_mode_info { int num_dig; /* number of dig blocks */ int disp_priority; const struct amdgpu_display_funcs *funcs; + enum drm_plane_type *plane_type; }; #define AMDGPU_MAX_BL_LEVEL 0xFF @@ -436,6 +439,11 @@ struct amdgpu_crtc { struct drm_pending_vblank_event *event; }; +struct amdgpu_plane { + struct drm_plane base; + enum drm_plane_type plane_type; +}; + struct amdgpu_encoder_atom_dig { bool linkb; /* atom dig */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b08ec453b773..d76448d04423 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -49,6 +49,28 @@ #include "modules/inc/mod_freesync.h" +static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, +}; + +static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ +}; + +static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_PRIMARY, + DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ +}; + /* * dm_vblank_get_counter * @@ -1051,30 +1073,34 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) uint32_t i; struct amdgpu_connector *aconnector; struct amdgpu_encoder *aencoder; - struct amdgpu_crtc *acrtc; + struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; link_cnt = dm->dc->caps.max_links; - if (amdgpu_dm_mode_config_init(dm->adev)) { DRM_ERROR("DM: Failed to initialize mode config\n"); - return -1; + goto fail; } - for (i = 0; i < dm->dc->caps.max_streams; i++) { - acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); - if (!acrtc) - goto fail; + for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), + GFP_KERNEL); + if (!mode_info->planes[i]) { + DRM_ERROR("KMS: Failed to allocate surface\n"); + goto fail_free_planes; + } + mode_info->planes[i]->plane_type = mode_info->plane_type[i]; + if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) { + DRM_ERROR("KMS: Failed to initialize plane\n"); + goto fail_free_planes; + } + } - if (amdgpu_dm_crtc_init( - dm, - acrtc, - i)) { + for (i = 0; i < dm->dc->caps.max_streams; i++) + if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { DRM_ERROR("KMS: Failed to initialize crtc\n"); - kfree(acrtc); - goto fail; + goto fail_free_planes; } - } dm->display_indexes_num = dm->dc->caps.max_streams; @@ -1125,12 +1151,12 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_VEGA10: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - return -1; + goto fail_free_encoder; } break; default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - return -1; + goto fail_free_encoder; } drm_mode_config_reset(dm->ddev); @@ -1140,6 +1166,9 @@ fail_free_encoder: kfree(aencoder); fail_free_connector: kfree(aconnector); +fail_free_planes: + for (i = 0; i < dm->dc->caps.max_surfaces; i++) + kfree(mode_info->planes[i]); fail: return -1; } @@ -1361,33 +1390,39 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; + adev->mode_info.plane_type = dm_surfaces_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index ee9239ab734c..1751f138c36a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1446,6 +1446,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { }; static const struct drm_plane_funcs dm_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, .reset = drm_atomic_helper_plane_reset, .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .atomic_destroy_state = drm_atomic_helper_plane_destroy_state @@ -1577,38 +1579,67 @@ static uint32_t rgb_formats[] = { DRM_FORMAT_ABGR2101010, }; -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct amdgpu_crtc *acrtc, - uint32_t crtc_index) +static uint32_t yuv_formats[] = { + DRM_FORMAT_YUYV, + DRM_FORMAT_YVYU, + DRM_FORMAT_UYVY, + DRM_FORMAT_VYUY, +}; + +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs) { - int res = -ENOMEM; + int res = -EPERM; - struct drm_plane *primary_plane = - kzalloc(sizeof(*primary_plane), GFP_KERNEL); + switch (aplane->plane_type) { + case DRM_PLANE_TYPE_PRIMARY: + aplane->base.format_default = true; - if (!primary_plane) - goto fail_plane; + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + rgb_formats, + ARRAY_SIZE(rgb_formats), + NULL, aplane->plane_type, NULL); + break; + case DRM_PLANE_TYPE_OVERLAY: + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + yuv_formats, + ARRAY_SIZE(yuv_formats), + NULL, aplane->plane_type, NULL); + break; + case DRM_PLANE_TYPE_CURSOR: + DRM_ERROR("KMS: Cursor plane not implemented."); + break; + } - primary_plane->format_default = true; + drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); - res = drm_universal_plane_init( - dm->adev->ddev, - primary_plane, - 0, - &dm_plane_funcs, - rgb_formats, - ARRAY_SIZE(rgb_formats), - NULL, - DRM_PLANE_TYPE_PRIMARY, NULL); + return res; +} - primary_plane->crtc = &acrtc->base; +int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t crtc_index) +{ + struct amdgpu_crtc *acrtc; + int res = -ENOMEM; - drm_plane_helper_add(primary_plane, &dm_plane_helper_funcs); + acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); + if (!acrtc) + goto fail; res = drm_crtc_init_with_planes( dm->ddev, &acrtc->base, - primary_plane, + plane, NULL, &amdgpu_dm_crtc_funcs, NULL); @@ -1628,8 +1659,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, return 0; fail: - kfree(primary_plane); -fail_plane: + kfree(acrtc); acrtc->crtc_id = -1; return res; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 1bbeb87dc9d0..ab6d51dbbf4b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -34,8 +34,11 @@ struct dc_validation_set; struct dc_surface; /*TODO Jodan Hersen use the one in amdgpu_dm*/ +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs); int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct amdgpu_crtc *amdgpu_crtc, + struct drm_plane *plane, uint32_t link_index); int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, struct amdgpu_connector *amdgpu_connector, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 0731045f6084..9dd8b2ad4c59 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -45,6 +45,7 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; + uint32_t max_surfaces; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index b6f77f88be9c..d1685df09815 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -1035,6 +1035,8 @@ static bool construct( } } + dc->public.caps.max_surfaces = pool->base.pipe_count; + if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) goto res_create_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index e3002031c40d..065a2986b666 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1455,6 +1455,8 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 32aa1b5bf1f9..ece3ec72363d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1409,6 +1409,8 @@ static bool construct( &res_create_funcs)) goto res_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) goto res_create_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index efa58889058b..f677a77ca6e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -1060,6 +1060,8 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; + dc->public.caps.max_surfaces = pool->base.pipe_count; + bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); bw_calcs_data_update_from_pplib(dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index a3e8182885b2..752e0e7579b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -1043,6 +1043,8 @@ static bool construct( } } + dc->public.caps.max_surfaces = pool->base.pipe_count; + if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) goto res_create_fail; -- cgit v1.2.3 From f2a0f5e6b23d6649577081df3762e41abee04691 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 3 Apr 2017 13:36:26 -0400 Subject: drm/amd/display: Fix cleanup in amdgpu_dm_initialize_drm_device Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d76448d04423..1077af91884f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1071,15 +1071,15 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) { struct amdgpu_display_manager *dm = &adev->dm; uint32_t i; - struct amdgpu_connector *aconnector; - struct amdgpu_encoder *aencoder; + struct amdgpu_connector *aconnector = NULL; + struct amdgpu_encoder *aencoder = NULL; struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; link_cnt = dm->dc->caps.max_links; if (amdgpu_dm_mode_config_init(dm->adev)) { DRM_ERROR("DM: Failed to initialize mode config\n"); - goto fail; + return -1; } for (i = 0; i < dm->dc->caps.max_surfaces; i++) { @@ -1116,7 +1116,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); if (!aconnector) - goto fail; + goto fail_free_planes; aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); if (!aencoder) { @@ -1130,7 +1130,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { DRM_ERROR("KMS: Failed to initialize connector\n"); - goto fail_free_connector; + goto fail_free_encoder; } if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true)) @@ -1169,7 +1169,6 @@ fail_free_connector: fail_free_planes: for (i = 0; i < dm->dc->caps.max_surfaces; i++) kfree(mode_info->planes[i]); -fail: return -1; } -- cgit v1.2.3 From 9faa423716b17b0c9ba92fd12737968de6918d88 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 31 Mar 2017 14:15:31 -0400 Subject: drm/amd/display: Fix s3 hang on resume. Avoid enabling CRTC_VERTICAL_INTERRUPT0 twice on resume. It's enabled once from within manage_dm_interrupts in mode set and another explicitly from amdgpu_dm_irq_resume_late. Seems it lead to CRTC hang. Signed-off-by: Andrey Grodzovsky Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 16 +++++++++++----- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h | 2 +- 3 files changed, 13 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1077af91884f..30148b4eabae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -575,7 +575,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); - amdgpu_dm_irq_resume(adev); + amdgpu_dm_irq_resume_late(adev); return ret; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 682e9c3ad8e5..4aee146a848f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -504,8 +504,11 @@ int amdgpu_dm_irq_suspend( DRM_DEBUG_KMS("DM_IRQ: suspend\n"); - /* disable HW interrupt */ - for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) { + /** + * Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK + * will be disabled from manage_dm_interrupts on disable CRTC. + */ + for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6RX; src++) { hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) @@ -544,7 +547,7 @@ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev) return 0; } -int amdgpu_dm_irq_resume(struct amdgpu_device *adev) +int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev) { int src; struct list_head *hnd_list_h, *hnd_list_l; @@ -554,8 +557,11 @@ int amdgpu_dm_irq_resume(struct amdgpu_device *adev) DRM_DEBUG_KMS("DM_IRQ: resume\n"); - /* re-enable HW interrupt */ - for (src = DC_IRQ_SOURCE_HPD1; src < DAL_IRQ_SOURCES_NUMBER; src++) { + /** + * Renable HW interrupt for HPD and only since FLIP and VBLANK + * will be enabled from manage_dm_interrupts on enable CRTC. + */ + for (src = DC_IRQ_SOURCE_HPD1; src < DC_IRQ_SOURCE_HPD6; src++) { hnd_list_l = &adev->dm.irq_handler_list_low_tab[src].head; hnd_list_h = &adev->dm.irq_handler_list_high_tab[src]; if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h)) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h index 9339861c8897..9d3007634266 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.h @@ -117,6 +117,6 @@ int amdgpu_dm_irq_suspend(struct amdgpu_device *adev); * */ int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev); -int amdgpu_dm_irq_resume(struct amdgpu_device *adev); +int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev); #endif /* __AMDGPU_DM_IRQ_H__ */ -- cgit v1.2.3 From 6f43fd6297c478995b6a9e61482272137ec36260 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:25:11 -0400 Subject: drm/amd/display: fix nullptr on vega initialization Signed-off-by: Jordan Lazare Reviewed-by: Tony Cheng Reviewed-by: Roman Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 30148b4eabae..a9b4eb0099ac 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1427,6 +1427,7 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_surfaces_type_default; break; default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); -- cgit v1.2.3 From 7df498fa4c241610ee22cfcfa648628d2ef908fd Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 10 Apr 2017 15:37:32 -0400 Subject: drm/amd/display: Allow planes on all crtcs 4.9 kernel will always add the assigned crtc to possible_crtcs on a plane. This is no longer the case on newer kernels. Make sure we allow any plane on any crtc. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a9b4eb0099ac..1b39bf9b4278 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1090,7 +1090,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_planes; } mode_info->planes[i]->plane_type = mode_info->plane_type[i]; - if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 1)) { + if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) { DRM_ERROR("KMS: Failed to initialize plane\n"); goto fail_free_planes; } -- cgit v1.2.3 From 753c66c91b5430816eedb67138017fd4e2143d52 Mon Sep 17 00:00:00 2001 From: Mario Kleiner Date: Mon, 24 Apr 2017 11:46:44 +0200 Subject: drm/amd/display: Fix race between vblank irq and pageflip irq. (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since DC now uses CRTC_VERTICAL_INTERRUPT0 as VBLANK irq trigger and vblank interrupts actually happen earliest at start of vblank, instead of a bit before vblank, we no longer need some of the fudging logic to deal with too early vblank irq handling (grep for lb_vblank_lead_lines). This itself fixes a pageflip scheduling bug in DC, caused by uninitialized use of lb_vblank_lead_lines, with a wrong startup value of 0. Thanks to the new vblank irq trigger this value of zero is now actually correct for DC :). A new problem is that vblank irq's race against pflip irq's, and as both can fire at first line of vblank, it is no longer guaranteed that vblank irq handling (therefore -> drm_handle_vblank() -> drm_update_vblank_count()) executes before pflip irq handling for a given vblank interval when a pageflip completes. Therefore the vblank count and timestamps emitted to user-space as part of the pageflip completion event will be often stale and cause new timestamping and swap scheduling errors in user-space. This was observed with large frequency on R9 380 Tonga Pro. Fix this by enforcing a vblank count+timestamp update right before emitting the pageflip completion event from the pflip irq handler. The logic in core drm_update_vblank_count() makes sure that no redundant or conflicting updates happen, iow. the call turns into a no-op if it wasn't needed for that vblank, burning a few microseconds of cpu time though. Successfully tested on AMD R9 380 "Tonga Pro" (VI/DCE 10) with DC enabled on the current DC staging branch. Independent measurement of pageflip completion timing with special hardware measurement equipment now confirms correct pageflip timestamps and counts in the pageflip completion events. v2: Review comments by Michel, drop outdated paragraph about problem already fixed in 2nd patch of the series. Add acked/r-b by Harry and Michel. Signed-off-by: Mario Kleiner Acked-by: Harry Wentland (v1) Reviewed-by: Michel Dänzer Cc: Andrey Grodzovsky Cc: Alex Deucher Cc: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1b39bf9b4278..93f10bc772c4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -202,6 +202,9 @@ static void dm_pflip_high_irq(void *interrupt_params) if (amdgpu_crtc->event && amdgpu_crtc->event->event.base.type == DRM_EVENT_FLIP_COMPLETE) { + /* Update to correct count/ts if racing with vblank irq */ + drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); + drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); /* page flip completed. clean up */ amdgpu_crtc->event = NULL; -- cgit v1.2.3 From 81c509633aa93442d58b895f773892b3e8d936cf Mon Sep 17 00:00:00 2001 From: Sylvia Tsai Date: Tue, 11 Apr 2017 15:15:28 -0400 Subject: drm/amd/display: Parse scanline registers They could differ between ASIC generations Signed-off-by: Sylvia Tsai Signed-off-by: Harry Wentland Acked-by: Harry Wentland Reviewed-by: Tony Cheng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 21 ++++++--- drivers/gpu/drm/amd/display/dc/dc.h | 7 ++- .../display/dc/dce110/dce110_timing_generator.c | 54 ++++++++++------------ .../display/dc/dce110/dce110_timing_generator.h | 8 ++-- .../display/dc/dce120/dce120_timing_generator.c | 42 ++++++++--------- .../drm/amd/display/dc/inc/hw/timing_generator.h | 8 ++-- 7 files changed, 89 insertions(+), 66 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 93f10bc772c4..84995a48ec61 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -103,6 +103,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, u32 *vbl, u32 *position) { + uint32_t v_blank_start, v_blank_end, h_position, v_position; + if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc)) return -EINVAL; else { @@ -113,7 +115,18 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, return 0; } - return dc_stream_get_scanoutpos(acrtc->stream, vbl, position); + /* + * TODO rework base driver to use values directly. + * for now parse it back into reg-format + */ + dc_stream_get_scanoutpos(acrtc->stream, + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); + + *position = (v_position) || (h_position << 16); + *vbl = (v_blank_start) || (v_blank_end << 16); } return 0; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index bf209f7bbf98..3dbd6c0885d8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -282,12 +282,14 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) return 0; } -uint32_t dc_stream_get_scanoutpos( - const struct dc_stream *dc_stream, - uint32_t *vbl, - uint32_t *position) +bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { uint8_t i; + bool ret = false; struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = @@ -299,10 +301,17 @@ uint32_t dc_stream_get_scanoutpos( if (res_ctx->pipe_ctx[i].stream != stream) continue; - return tg->funcs->get_scanoutpos(tg, vbl, position); + tg->funcs->get_scanoutpos(tg, + v_blank_start, + v_blank_end, + h_position, + v_position); + + ret = true; + break; } - return 0; + return ret; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 97af8f63eec3..7d548b4d0299 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -484,8 +484,11 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -uint32_t dc_stream_get_scanoutpos( - const struct dc_stream *stream, uint32_t *vbl, uint32_t *position); +bool dc_stream_get_scanoutpos(const struct dc_stream *stream, + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); /* * Structure to store surface/stream associations for validation diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c index 006412be7a02..7070aaf9e433 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c @@ -574,29 +574,26 @@ void dce110_timing_generator_get_crtc_positions( * @param [out] vpos, hpos ***************************************************************************** */ -uint32_t dce110_timing_generator_get_crtc_scanoutpos( +void dce110_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position) + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - /* TODO 1: Update the implementation once caller is updated - * WARNING!! This function is returning the whole register value - * because the caller is expecting it instead of proper vertical and - * horizontal position. This should be a temporary implementation - * until the caller is updated. */ - /* TODO 2: re-use dce110_timing_generator_get_crtc_positions() */ - - *vbl = dm_read_reg(tg->ctx, + uint32_t v_blank_start_end = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_V_BLANK_START_END)); - *position = dm_read_reg(tg->ctx, - CRTC_REG(mmCRTC_STATUS_POSITION)); + *v_blank_start = get_reg_field_value(v_blank_start_end, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + *v_blank_end = get_reg_field_value(v_blank_start_end, + CRTC_V_BLANK_START_END, + CRTC_V_BLANK_END); - /* @TODO: return value should indicate if current - * crtc is inside vblank*/ - return 0; + dce110_timing_generator_get_crtc_positions(tg, h_position, v_position); } /* TODO: is it safe to assume that mask/shift of Primary and Underlay @@ -1875,34 +1872,31 @@ void dce110_tg_set_colors(struct timing_generator *tg, bool dce110_arm_vert_intr(struct timing_generator *tg, uint8_t width) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - uint32_t vbl = 0; + uint32_t v_blank_start = 0; + uint32_t v_blank_end = 0; uint32_t val = 0; - uint32_t position, vbl_start; + uint32_t h_position, v_position; tg->funcs->get_scanoutpos( tg, - &vbl, - &position); + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); - if (vbl == 0) + if (v_blank_start == 0 || v_blank_end == 0) return false; - vbl_start = - get_reg_field_value( - vbl, - CRTC_V_BLANK_START_END, - CRTC_V_BLANK_START); - set_reg_field_value( val, - vbl_start, + v_blank_start, CRTC_VERTICAL_INTERRUPT0_POSITION, CRTC_VERTICAL_INTERRUPT0_LINE_START); - /* Set interaval width for interrupt to fire to 1 scanline */ + /* Set interval width for interrupt to fire to 1 scanline */ set_reg_field_value( val, - vbl_start + width, + v_blank_start + width, CRTC_VERTICAL_INTERRUPT0_POSITION, CRTC_VERTICAL_INTERRUPT0_LINE_END); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h index ca387b40fc67..f14a4d91cd8e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h @@ -230,10 +230,12 @@ void dce110_timing_generator_set_static_screen_control( struct timing_generator *tg, uint32_t value); -uint32_t dce110_timing_generator_get_crtc_scanoutpos( +void dce110_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position); + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); void dce110_timing_generator_enable_advanced_request( struct timing_generator *tg, diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c index 95cb1768aeb5..1318df7ed47e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c @@ -576,24 +576,28 @@ void dce120_timing_generator_set_drr( } } -uint32_t dce120_timing_generator_get_crtc_scanoutpos( +void dce120_timing_generator_get_crtc_scanoutpos( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position) + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - *vbl = dm_read_reg_soc15( + uint32_t v_blank_start_end = dm_read_reg_soc15( tg->ctx, mmCRTC0_CRTC_V_BLANK_START_END, tg110->offsets.crtc); - *position = dm_read_reg_soc15( - tg->ctx, - mmCRTC0_CRTC_STATUS_POSITION, - tg110->offsets.crtc); + *v_blank_start = get_reg_field_value(v_blank_start_end, + CRTC0_CRTC_V_BLANK_START_END, + CRTC_V_BLANK_START); + *v_blank_end = get_reg_field_value(v_blank_start_end, + CRTC0_CRTC_V_BLANK_START_END, + CRTC_V_BLANK_END); - return 0; + dce120_timing_generator_get_crtc_positions(tg, h_position, v_position); } void dce120_timing_generator_enable_advanced_request( @@ -1044,26 +1048,22 @@ static bool dce120_arm_vert_intr( uint8_t width) { struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); - uint32_t vbl, position, vbl_start; + uint32_t v_blank_start, v_blank_end, h_position, v_position; tg->funcs->get_scanoutpos( tg, - &vbl, - &position); + &v_blank_start, + &v_blank_end, + &h_position, + &v_position); - if (vbl == 0) + if (v_blank_start == 0 || v_blank_end == 0) return false; - vbl_start = - get_reg_field_value( - vbl, - CRTC0_CRTC_V_BLANK_START_END, - CRTC_V_BLANK_START); - CRTC_REG_SET_2( CRTC0_CRTC_VERTICAL_INTERRUPT0_POSITION, - CRTC_VERTICAL_INTERRUPT0_LINE_START, vbl_start, - CRTC_VERTICAL_INTERRUPT0_LINE_END, vbl_start + width); + CRTC_VERTICAL_INTERRUPT0_LINE_START, v_blank_start, + CRTC_VERTICAL_INTERRUPT0_LINE_END, v_blank_start + width); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 51902a4f8798..b3deaf2d8173 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -120,10 +120,12 @@ struct timing_generator_funcs { int32_t *h_position, int32_t *v_position); uint32_t (*get_frame_count)(struct timing_generator *tg); - uint32_t (*get_scanoutpos)( + void (*get_scanoutpos)( struct timing_generator *tg, - uint32_t *vbl, - uint32_t *position); + uint32_t *v_blank_start, + uint32_t *v_blank_end, + uint32_t *h_position, + uint32_t *v_position); void (*set_early_control)(struct timing_generator *tg, uint32_t early_cntl); void (*wait_for_state)(struct timing_generator *tg, -- cgit v1.2.3 From 03ea364c8e156b2bb5c64465718e8ebd75e3df22 Mon Sep 17 00:00:00 2001 From: Arindam Nath Date: Wed, 26 Apr 2017 17:39:56 +0530 Subject: drm/amd/display: fix resume hang because of DP short pulse There is a hard hang observed during resume from S3 when the system receives a DP short pulse interrupt. This is because there are two code paths contending for GPIO access for AUX channel transactions. One such path is through amdgpu_dm_display_resume() function which is invoked from the regular system resume code path. The other path is through handle_hpd_rx_irq(), which is invoked in response to system receiving DP short pulse interrupt. handle_hpd_rx_irq() guards against conflicting GPIO access using hpd_lock, but the GPIO access from amdgpu_dm_display_resume() remains unguarded. This patch makes sure we use hpd_lock inside amdgpu_dm_display_resume() to avoid race conditions for GPIO access. Signed-off-by: Arindam Nath Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 84995a48ec61..74e32246ff30 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -580,9 +580,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) if (aconnector->mst_port) continue; + mutex_lock(&aconnector->hpd_lock); dc_link_detect(aconnector->dc_link, false); aconnector->dc_sink = NULL; amdgpu_dm_update_connector_after_detect(aconnector); + mutex_unlock(&aconnector->hpd_lock); } /* Force mode set in atomic comit */ -- cgit v1.2.3 From ff5ef99248662ef98a64c11c5370ecd9fbbf57a6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Jun 2017 16:27:42 -0400 Subject: drm/amdgpu/display: Enable DCN in DC Enable DCN in DC. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 7 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 115 ++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3 +- drivers/gpu/drm/amd/display/dc/Makefile | 5 + .../amd/display/dc/bios/command_table_helper2.c | 5 + drivers/gpu/drm/amd/display/dc/calcs/Makefile | 8 + drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 19 ++ drivers/gpu/drm/amd/display/dc/dc.h | 18 ++ drivers/gpu/drm/amd/display/dc/dce/dce_abm.h | 49 ++++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 31 +++ .../gpu/drm/amd/display/dc/dce/dce_clock_source.h | 21 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 15 ++ drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h | 9 + drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 245 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h | 21 ++ drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 15 ++ .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 16 +- .../drm/amd/display/dc/dce/dce_stream_encoder.c | 264 +++++++++++++++++++++ .../drm/amd/display/dc/dce/dce_stream_encoder.h | 69 ++++++ .../amd/display/dc/dce110/dce110_hw_sequencer.c | 29 +++ drivers/gpu/drm/amd/display/dc/dm_services.h | 4 + drivers/gpu/drm/amd/display/dc/dm_services_types.h | 1 + drivers/gpu/drm/amd/display/dc/gpio/Makefile | 11 + drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 9 +- drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c | 9 + drivers/gpu/drm/amd/display/dc/i2caux/Makefile | 11 + drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c | 8 + drivers/gpu/drm/amd/display/dc/inc/core_dc.h | 5 + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 26 ++ .../gpu/drm/amd/display/dc/inc/hw/display_clock.h | 7 + drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h | 1 + drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 41 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 110 +++++++++ drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 1 + .../drm/amd/display/dc/inc/hw/timing_generator.h | 16 ++ drivers/gpu/drm/amd/display/dc/irq/Makefile | 10 + drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 5 + drivers/gpu/drm/amd/display/include/dal_asic_id.h | 13 + drivers/gpu/drm/amd/display/include/dal_types.h | 5 +- 39 files changed, 1250 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 47c8e2940a91..5c3bb3581842 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -17,6 +17,13 @@ config DRM_AMD_DC_PRE_VEGA by default. This includes Polaris, Carrizo, Tonga, Bonaire, and Hawaii. +config DRM_AMD_DC_DCN1_0 + bool "DCN 1.0 Raven family" + depends on DRM_AMD_DC + help + Choose this option if you want to have + RV family for display engine + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 74e32246ff30..4ec86ed5622f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -49,6 +49,16 @@ #include "modules/inc/mod_freesync.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "ivsrcid/irqsrcs_dcn_1_0.h" + +#include "raven1/DCN/dcn_1_0_offset.h" +#include "raven1/DCN/dcn_1_0_sh_mask.h" +#include "vega10/soc15ip.h" + +#include "soc15_common.h" +#endif + static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -930,7 +940,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int i; unsigned client_id = AMDGPU_IH_CLIENTID_LEGACY; - if (adev->asic_type == CHIP_VEGA10) + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_RAVEN) client_id = AMDGPU_IH_CLIENTID_DCE; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; @@ -1003,6 +1014,92 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) return 0; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +/* Register IRQ sources and initialize IRQ callbacks */ +static int dcn10_register_irq_handlers(struct amdgpu_device *adev) +{ + struct dc *dc = adev->dm.dc; + struct common_irq_params *c_irq_params; + struct dc_interrupt_params int_params = {0}; + int r; + int i; + + int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; + int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT; + + /* Actions of amdgpu_irq_add_id(): + * 1. Register a set() function with base driver. + * Base driver will call set() function to enable/disable an + * interrupt in DC hardware. + * 2. Register amdgpu_dm_irq_handler(). + * Base driver will call amdgpu_dm_irq_handler() for ALL interrupts + * coming from DC hardware. + * amdgpu_dm_irq_handler() will re-direct the interrupt to DC + * for acknowledging and handling. + * */ + + /* Use VSTARTUP interrupt */ + for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP; + i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1; + i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->crtc_irq); + + if (r) { + DRM_ERROR("Failed to add crtc irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_crtc_high_irq, c_irq_params); + } + + /* Use GRPH_PFLIP interrupt */ + for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT; + i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1; + i++) { + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, i, &adev->pageflip_irq); + if (r) { + DRM_ERROR("Failed to add page flip irq id!\n"); + return r; + } + + int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT; + int_params.irq_source = + dc_interrupt_to_irq_source(dc, i, 0); + + c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST]; + + c_irq_params->adev = adev; + c_irq_params->irq_src = int_params.irq_source; + + amdgpu_dm_irq_register_interrupt(adev, &int_params, + dm_pflip_high_irq, c_irq_params); + + } + + /* HPD */ + r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT, + &adev->hpd_irq); + if (r) { + DRM_ERROR("Failed to add hpd irq id!\n"); + return r; + } + + register_hpd_handlers(adev); + + return 0; +} +#endif + static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) { int r; @@ -1172,6 +1269,14 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_encoder; } break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + if (dcn10_register_irq_handlers(dm->adev)) { + DRM_ERROR("DM: Failed to initialize IRQ\n"); + goto fail_free_encoder; + } + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); goto fail_free_encoder; @@ -1447,6 +1552,14 @@ static int dm_early_init(void *handle) adev->mode_info.num_dig = 6; adev->mode_info.plane_type = dm_surfaces_type_default; break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case CHIP_RAVEN: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 4; + adev->mode_info.num_dig = 4; + adev->mode_info.plane_type = dm_surfaces_type_default; + break; +#endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); return -EINVAL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 0f09e8b903d3..bca6769e7481 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -562,7 +562,8 @@ static void fill_plane_attributes_from_fb( surface->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - if (adev->asic_type == CHIP_VEGA10) { + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ surface->tiling_info.gfx9.num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; diff --git a/drivers/gpu/drm/amd/display/dc/Makefile b/drivers/gpu/drm/amd/display/dc/Makefile index 1a79762425ea..4f83e3011743 100644 --- a/drivers/gpu/drm/amd/display/dc/Makefile +++ b/drivers/gpu/drm/amd/display/dc/Makefile @@ -4,7 +4,12 @@ DC_LIBS = basics bios calcs dce gpio i2caux irq virtual +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +DC_LIBS += dcn10 dml +endif + DC_LIBS += dce120 + DC_LIBS += dce112 DC_LIBS += dce110 DC_LIBS += dce100 diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c index 1cc3df1d5698..84b1f515aa47 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c @@ -53,6 +53,11 @@ bool dal_bios_parser_init_cmd_tbl_helper2( case DCE_VERSION_11_2: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + *h = dal_cmd_tbl_helper_dce112_get_table2(); + return true; +#endif case DCE_VERSION_12_0: *h = dal_cmd_tbl_helper_dce112_get_table2(); return true; diff --git a/drivers/gpu/drm/amd/display/dc/calcs/Makefile b/drivers/gpu/drm/amd/display/dc/calcs/Makefile index 63a0edbc32e7..a095472bf4b5 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/Makefile +++ b/drivers/gpu/drm/amd/display/dc/calcs/Makefile @@ -3,8 +3,16 @@ # It calculates Bandwidth and Watermarks values for HW programming # +CFLAGS_dcn_calcs.o := -mhard-float -msse -mpreferred-stack-boundary=4 +CFLAGS_dcn_calc_auto.o := -mhard-float -msse -mpreferred-stack-boundary=4 +CFLAGS_dcn_calc_math.o := -mhard-float -msse -mpreferred-stack-boundary=4 + BW_CALCS = dce_calcs.o bw_fixed.o custom_float.o +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +BW_CALCS += dcn_calcs.o dcn_calc_math.o dcn_calc_auto.o +endif + AMD_DAL_BW_CALCS = $(addprefix $(AMDDALPATH)/dc/calcs/,$(BW_CALCS)) AMD_DISPLAY_FILES += $(AMD_DAL_BW_CALCS) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2de86f8364a3..ae8b221c85aa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -39,6 +39,9 @@ #include "dce100/dce100_resource.h" #include "dce110/dce110_resource.h" #include "dce112/dce112_resource.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/dcn10_resource.h" +#endif #include "dce120/dce120_resource.h" enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) @@ -69,6 +72,11 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id) case FAMILY_AI: dc_version = DCE_VERSION_12_0; break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case FAMILY_RV: + dc_version = DCN_VERSION_1_0; + break; +#endif default: dc_version = DCE_VERSION_UNKNOWN; break; @@ -105,6 +113,13 @@ struct resource_pool *dc_create_resource_pool( res_pool = dce120_create_resource_pool( num_virtual_links, dc); break; + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + res_pool = dcn10_create_resource_pool( + num_virtual_links, dc); + break; +#endif default: break; } @@ -1188,6 +1203,10 @@ static int acquire_first_free_pipe( pipe_ctx->dis_clk = pool->display_clock; pipe_ctx->pipe_idx = i; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + pipe_ctx->mpc_idx = -1; +#endif + pipe_ctx->stream = stream; return i; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 87675f032949..d74bbdce1090 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -94,7 +94,13 @@ struct dc_surface; struct validate_context; struct dc_cap_funcs { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + bool (*get_dcc_compression_cap)(const struct dc *dc, + const struct dc_dcc_surface_param *input, + struct dc_surface_dcc_cap *output); +#else int i; +#endif }; struct dc_stream_funcs { @@ -164,6 +170,18 @@ struct dc_debug { bool disable_stutter; bool disable_dcc; bool disable_dfs_bypass; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + bool disable_dpp_power_gate; + bool disable_hubp_power_gate; + bool disable_pplib_wm_range; + bool use_dml_wm; + bool use_max_voltage; + int sr_exit_time_ns; + int sr_enter_plus_exit_time_ns; + int urgent_latency_ns; + int percent_of_ideal_drambw; + int dram_clock_change_latency_ns; +#endif bool disable_pplib_clock_request; bool disable_clock_gate; bool disable_dmcu; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h index 56087b36bdeb..e0abd2d49370 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h @@ -54,6 +54,22 @@ SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ SR(BIOS_SCRATCH_2) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define ABM_DCN10_REG_LIST(id)\ + ABM_COMMON_REG_LIST_DCE_BASE(), \ + SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ + SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ + SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ + SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ + SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ + SRI(BL1_PWM_USER_LEVEL, ABM, id), \ + SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ + SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ + NBIO_SR(BIOS_SCRATCH_2) +#endif + #define ABM_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -105,6 +121,39 @@ ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ + ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_VMAX_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ + ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ + ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ + BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ + BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ + ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ + BL1_PWM_USER_LEVEL, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ + ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ + ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ + ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) +#endif + #define ABM_REG_FIELD_LIST(type) \ type ABM1_HG_NUM_OF_BINS_SEL; \ type ABM1_HG_VMAX_SEL; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index bd4524ef3a37..142b3a01c204 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -586,6 +586,9 @@ static uint32_t dce110_get_pix_clk_dividers( break; case DCE_VERSION_11_2: case DCE_VERSION_12_0: +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: +#endif dce112_get_pix_clk_dividers_helper(clk_src, pll_settings, pix_clk_params); break; @@ -815,6 +818,31 @@ static bool dce110_program_pix_clk( struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); struct bp_pixel_clock_parameters bp_pc_params = {0}; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (IS_FPGA_MAXIMUS_DC(clock_source->ctx->dce_environment)) { + unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; + unsigned dp_dto_ref_kHz = 600000; + /* DPREF clock from FPGA TODO: Does FPGA have this value? */ + unsigned clock_kHz = pll_settings->actual_pix_clk; + + /* For faster simulation, if mode pixe clock less than 290MHz, + * pixel clock can be hard coded to 290Mhz. For 4K mode, pixel clock + * is greater than 500Mhz, need real pixel clock + * clock_kHz = 290000; + */ + /* TODO: un-hardcode when we can set display clock properly*/ + /*clock_kHz = pix_clk_params->requested_pix_clk;*/ + clock_kHz = 290000; + + /* Set DTO values: phase = target clock, modulo = reference clock */ + REG_WRITE(PHASE[inst], clock_kHz); + REG_WRITE(MODULO[inst], dp_dto_ref_kHz); + + /* Enable DTO */ + REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); + return true; + } +#endif /* First disable SS * ATOMBIOS will enable by default SS on PLL for DP, * do not disable it here @@ -870,6 +898,9 @@ static bool dce110_program_pix_clk( break; case DCE_VERSION_11_2: case DCE_VERSION_12_0: +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: +#endif if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = pll_settings->use_external_clk; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 28984c79fc46..e8bc98b3b622 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -55,6 +55,27 @@ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(PHASE, DP_DTO, 2),\ + SRII(PHASE, DP_DTO, 3),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 2),\ + SRII(MODULO, DP_DTO, 3),\ + SRII(PIXEL_RATE_CNTL, OTG, 0), \ + SRII(PIXEL_RATE_CNTL, OTG, 1), \ + SRII(PIXEL_RATE_CNTL, OTG, 2), \ + SRII(PIXEL_RATE_CNTL, OTG, 3) + +#define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ + CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) +#endif + #define CS_REG_FIELD_LIST(type) \ type PLL_REF_DIV_SRC; \ type DCCG_DEEP_COLOR_CNTL1; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 81cb138cdc38..6e56d8308d66 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -29,6 +29,10 @@ #include "fixed32_32.h" #include "bios_parser_interface.h" #include "dc.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn_calcs.h" +#include "core_dc.h" +#endif #define TO_DCE_CLOCKS(clocks)\ container_of(clocks, struct dce_disp_clk, base) @@ -400,6 +404,10 @@ static void dce112_set_clock( bp->funcs->set_dce_clock(bp, &dce_clk_params); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + dce_psr_wait_loop(clk_dce, requested_clk_khz); +#endif + } static void dce_clock_read_integrated_info(struct dce_disp_clk *clk_dce) @@ -596,6 +604,13 @@ static bool dce_apply_clock_voltage_request( } } if (send_request) { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc); + /*use dcfclk request voltage*/ + clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock_voltage_req.clocks_in_khz = + dcn_find_dcfclk_suits_all(core_dc, &clk->cur_clocks_value); +#endif dm_pp_apply_clock_for_voltage_request( clk->ctx, &clock_voltage_req); } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h index 29ff470086e5..103e905291a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.h @@ -45,6 +45,15 @@ CLK_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ CLK_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define CLK_DCN10_REG_LIST()\ + SR(DPREFCLK_CNTL), \ + SR(DENTIST_DISPCLK_CNTL), \ + SR(MASTER_COMM_DATA_REG1), \ + SR(MASTER_COMM_CMD_REG), \ + SR(MASTER_COMM_CNTL_REG) +#endif + #define CLK_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \ CLK_SF(DCCG_DFS_DPREFCLK_CNTL, DPREFCLK_SRC_SEL, mask_sh), \ CLK_SF(DCCG_DFS_DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, mask_sh), \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index da7f86b61de4..c58328cd787b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -252,12 +252,234 @@ static void dce_dmcu_setup_psr(struct dmcu *dmcu, REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +bool dcn10_dmcu_load_iram(struct dmcu *dmcu, + unsigned int start_offset, + const char *src, + unsigned int bytes) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int count = 0; + + REG_UPDATE(DMCU_CTRL, DMCU_ENABLE, 1); + + /* Enable write access to IRAM */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 1, + IRAM_WR_ADDR_AUTO_INC, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + REG_WRITE(DMCU_IRAM_WR_CTRL, start_offset); + + for (count = 0; count < bytes; count++) + REG_WRITE(DMCU_IRAM_WR_DATA, src[count]); + + /* Disable write access to IRAM to allow dynamic sleep state */ + REG_UPDATE_2(DMCU_RAM_ACCESS_CTRL, + IRAM_HOST_ACCESS_EN, 0, + IRAM_WR_ADDR_AUTO_INC, 0); + + return true; +} + +static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + uint32_t psrStateOffset = 0xf0; + + /* Enable write access to IRAM */ + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 1); + + REG_WAIT(DMU_MEM_PWR_CNTL, DMCU_IRAM_MEM_PWR_STATE, 0, 2, 10); + + /* Write address to IRAM_RD_ADDR in DMCU_IRAM_RD_CTRL */ + REG_WRITE(DMCU_IRAM_RD_CTRL, psrStateOffset); + + /* Read data from IRAM_RD_DATA in DMCU_IRAM_RD_DATA*/ + *psr_state = REG_READ(DMCU_IRAM_RD_DATA); + + /* Disable write access to IRAM after finished using IRAM + * in order to allow dynamic sleep state + */ + REG_UPDATE(DMCU_RAM_ACCESS_CTRL, IRAM_HOST_ACCESS_EN, 0); +} + +static void dcn10_dmcu_set_psr_enable(struct dmcu *dmcu, bool enable) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + + unsigned int retryCount; + uint32_t psr_state = 0; + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* setDMCUParam_Cmd */ + if (enable) + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + PSR_ENABLE); + else + REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, + PSR_EXIT); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); + + /* Below loops 1000 x 500us = 500 ms. + * Exit PSR may need to wait 1-2 frames to power up. Timeout after at + * least a few frames. Should never hit the max retry assert below. + */ + for (retryCount = 0; retryCount <= 1000; retryCount++) { + dcn10_get_dmcu_psr_state(dmcu, &psr_state); + if (enable) { + if (psr_state != 0) + break; + } else { + if (psr_state == 0) + break; + } + dm_delay_in_microseconds(dmcu->ctx, 500); + } + + /* assert if max retry hit */ + ASSERT(retryCount <= 1000); +} + +static void dcn10_dmcu_setup_psr(struct dmcu *dmcu, + struct core_link *link, + struct psr_context *psr_context) +{ + struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(dmcu); + + unsigned int dmcu_max_retry_on_wait_reg_ready = 801; + unsigned int dmcu_wait_reg_ready_interval = 100; + + union dce_dmcu_psr_config_data_reg1 masterCmdData1; + union dce_dmcu_psr_config_data_reg2 masterCmdData2; + union dce_dmcu_psr_config_data_reg3 masterCmdData3; + + link->link_enc->funcs->psr_program_dp_dphy_fast_training(link->link_enc, + psr_context->psrExitLinkTrainingRequired); + + /* Enable static screen interrupts for PSR supported display */ + /* Disable the interrupt coming from other displays. */ + REG_UPDATE_4(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 0, + STATIC_SCREEN2_INT_TO_UC_EN, 0, + STATIC_SCREEN3_INT_TO_UC_EN, 0, + STATIC_SCREEN4_INT_TO_UC_EN, 0); + + switch (psr_context->controllerId) { + /* Driver uses case 1 for unconfigured */ + case 1: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 1); + break; + case 2: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN2_INT_TO_UC_EN, 1); + break; + case 3: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN3_INT_TO_UC_EN, 1); + break; + case 4: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN4_INT_TO_UC_EN, 1); + break; + case 5: + /* CZ/NL only has 4 CRTC!! + * really valid. + * There is no interrupt enable mask for these instances. + */ + break; + case 6: + /* CZ/NL only has 4 CRTC!! + * These are here because they are defined in HW regspec, + * but not really valid. There is no interrupt enable mask + * for these instances. + */ + break; + default: + REG_UPDATE(DMCU_INTERRUPT_TO_UC_EN_MASK, + STATIC_SCREEN1_INT_TO_UC_EN, 1); + break; + } + + link->link_enc->funcs->psr_program_secondary_packet(link->link_enc, + psr_context->sdpTransmitLineNumDeadline); + + if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION) + REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1); + + /* waitDMCUReadyForCmd */ + REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0, + dmcu_wait_reg_ready_interval, + dmcu_max_retry_on_wait_reg_ready); + + /* setDMCUParam_PSRHostConfigData */ + masterCmdData1.u32All = 0; + masterCmdData1.bits.timehyst_frames = psr_context->timehyst_frames; + masterCmdData1.bits.hyst_lines = psr_context->hyst_lines; + masterCmdData1.bits.rfb_update_auto_en = + psr_context->rfb_update_auto_en; + masterCmdData1.bits.dp_port_num = psr_context->transmitterId; + masterCmdData1.bits.dcp_sel = psr_context->controllerId; + masterCmdData1.bits.phy_type = psr_context->phyType; + masterCmdData1.bits.frame_cap_ind = + psr_context->psrFrameCaptureIndicationReq; + masterCmdData1.bits.aux_chan = psr_context->channel; + masterCmdData1.bits.aux_repeat = psr_context->aux_repeats; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), + masterCmdData1.u32All); + + masterCmdData2.u32All = 0; + masterCmdData2.bits.dig_fe = psr_context->engineId; + masterCmdData2.bits.dig_be = psr_context->transmitterId; + masterCmdData2.bits.skip_wait_for_pll_lock = + psr_context->skipPsrWaitForPllLock; + masterCmdData2.bits.frame_delay = psr_context->frame_delay; + masterCmdData2.bits.smu_phy_id = psr_context->smuPhyId; + masterCmdData2.bits.num_of_controllers = + psr_context->numberOfControllers; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), + masterCmdData2.u32All); + + masterCmdData3.u32All = 0; + masterCmdData3.bits.psr_level = psr_context->psr_level.u32all; + dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), + masterCmdData3.u32All); + + /* setDMCUParam_Cmd */ + REG_UPDATE(MASTER_COMM_CMD_REG, + MASTER_COMM_CMD_REG_BYTE0, PSR_SET); + + /* notifyDMCUMsg */ + REG_UPDATE(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 1); +} + +#endif + static const struct dmcu_funcs dce_funcs = { .load_iram = dce_dmcu_load_iram, .set_psr_enable = dce_dmcu_set_psr_enable, .setup_psr = dce_dmcu_setup_psr, }; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +static const struct dmcu_funcs dcn10_funcs = { + .load_iram = dcn10_dmcu_load_iram, + .set_psr_enable = dcn10_dmcu_set_psr_enable, + .setup_psr = dcn10_dmcu_setup_psr, +}; +#endif + static void dce_dmcu_construct( struct dce_dmcu *dmcu_dce, struct dc_context *ctx, @@ -296,6 +518,29 @@ struct dmcu *dce_dmcu_create( return &dmcu_dce->base; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct dmcu *dcn10_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask) +{ + struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + + if (dmcu_dce == NULL) { + BREAK_TO_DEBUGGER(); + return NULL; + } + + dce_dmcu_construct( + dmcu_dce, ctx, regs, dmcu_shift, dmcu_mask); + + dmcu_dce->base.funcs = &dcn10_funcs; + + return &dmcu_dce->base; +} +#endif + void dce_dmcu_destroy(struct dmcu **dmcu) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h index 7dc25386c2bf..584682ba1f77 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h @@ -48,6 +48,12 @@ DMCU_COMMON_REG_LIST_DCE_BASE(), \ SR(DCI_MEM_PWR_STATUS) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define DMCU_DCN10_REG_LIST()\ + DMCU_COMMON_REG_LIST_DCE_BASE(), \ + SR(DMU_MEM_PWR_CNTL) +#endif + #define DMCU_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -76,6 +82,13 @@ DMCU_SF(DCI_MEM_PWR_STATUS, \ DMCU_IRAM_MEM_PWR_STATE, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ + DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ + DMCU_SF(DMU_MEM_PWR_CNTL, \ + DMCU_IRAM_MEM_PWR_STATE, mask_sh) +#endif + #define DMCU_REG_FIELD_LIST(type) \ type DMCU_IRAM_MEM_PWR_STATE; \ type IRAM_HOST_ACCESS_EN; \ @@ -190,6 +203,14 @@ struct dmcu *dce_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct dmcu *dcn10_dmcu_create( + struct dc_context *ctx, + const struct dce_dmcu_registers *regs, + const struct dce_dmcu_shift *dmcu_shift, + const struct dce_dmcu_mask *dmcu_mask); +#endif + void dce_dmcu_destroy(struct dmcu **dmcu); #endif /* _DCE_ABM_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index c66585188ecd..dd13f47b6446 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -121,6 +121,12 @@ HWSEQ_PIXEL_RATE_REG_LIST(CRTC), \ HWSEQ_PHYPLL_REG_LIST(CRTC) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define HWSEQ_DCN1_REG_LIST()\ + HWSEQ_PIXEL_RATE_REG_LIST(OTG), \ + HWSEQ_PHYPLL_REG_LIST(OTG) +#endif + struct dce_hwseq_registers { uint32_t DCFE_CLOCK_CONTROL[6]; uint32_t DCFEV_CLOCK_CONTROL; @@ -129,6 +135,9 @@ struct dce_hwseq_registers { uint32_t BLND_CONTROL[6]; uint32_t BLNDV_CONTROL; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* DCE + DCN */ +#endif uint32_t CRTC_H_BLANK_START_END[6]; uint32_t PIXEL_RATE_CNTL[6]; uint32_t PHYPLL_PIXEL_RATE_CNTL[6]; @@ -192,6 +201,12 @@ struct dce_hwseq_registers { HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, CRTC0_),\ HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, CRTC0_) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define HWSEQ_DCN1_MASK_SH_LIST(mask_sh)\ + HWSEQ_PIXEL_RATE_MASK_SH_LIST(mask_sh, OTG0_),\ + HWSEQ_PHYPLL_MASK_SH_LIST(mask_sh, OTG0_) +#endif + #define HWSEQ_REG_FIED_LIST(type) \ type DCFE_CLOCK_ENABLE; \ type DCFEV_CLOCK_ENABLE; \ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 4e0b5d965355..8b04996d5b89 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -78,6 +78,10 @@ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ SR(DCI_MEM_PWR_STATUS) +#define LE_DCE80_REG_LIST(id)\ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + LE_COMMON_REG_LIST_BASE(id) + #define LE_DCE100_REG_LIST(id)\ LE_COMMON_REG_LIST_BASE(id), \ SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ @@ -97,9 +101,15 @@ SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ SR(DCI_MEM_PWR_STATUS) -#define LE_DCE80_REG_LIST(id)\ - SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ - LE_COMMON_REG_LIST_BASE(id) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + #define LE_DCN10_REG_LIST(id)\ + LE_COMMON_REG_LIST_BASE(id), \ + SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ + SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ + SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ + SR(DMU_MEM_PWR_CNTL) +#endif + struct dce110_link_enc_aux_registers { uint32_t AUX_CONTROL; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c index 9713def6e481..a065e4ae6cba 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c @@ -147,6 +147,46 @@ static void dce110_update_generic_info_packet( AFMT_GENERIC0_UPDATE, (packet_index == 0), AFMT_GENERIC2_UPDATE, (packet_index == 2)); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(AFMT_VBI_PACKET_CONTROL1)) { + switch (packet_index) { + case 0: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC0_FRAME_UPDATE, 1); + break; + case 1: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC1_FRAME_UPDATE, 1); + break; + case 2: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC2_FRAME_UPDATE, 1); + break; + case 3: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC3_FRAME_UPDATE, 1); + break; + case 4: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC4_FRAME_UPDATE, 1); + break; + case 5: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC5_FRAME_UPDATE, 1); + break; + case 6: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC6_FRAME_UPDATE, 1); + break; + case 7: + REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, + AFMT_GENERIC7_FRAME_UPDATE, 1); + break; + default: + break; + } + } +#endif } static void dce110_update_hdmi_info_packet( @@ -202,6 +242,36 @@ static void dce110_update_hdmi_info_packet( HDMI_GENERIC1_SEND, send, HDMI_GENERIC1_LINE, line); break; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case 4: + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, + HDMI_GENERIC0_CONT, cont, + HDMI_GENERIC0_SEND, send, + HDMI_GENERIC0_LINE, line); + break; + case 5: + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, + HDMI_GENERIC1_CONT, cont, + HDMI_GENERIC1_SEND, send, + HDMI_GENERIC1_LINE, line); + break; + case 6: + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, + HDMI_GENERIC0_CONT, cont, + HDMI_GENERIC0_SEND, send, + HDMI_GENERIC0_LINE, line); + break; + case 7: + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, + HDMI_GENERIC1_CONT, cont, + HDMI_GENERIC1_SEND, send, + HDMI_GENERIC1_LINE, line); + break; +#endif default: /* invalid HW packet index */ dm_logger_write( @@ -218,9 +288,24 @@ static void dce110_stream_encoder_dp_set_stream_attribute( struct dc_crtc_timing *crtc_timing, enum dc_color_space output_color_space) { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + uint32_t h_active_start; + uint32_t v_active_start; + uint32_t misc0 = 0; + uint32_t misc1 = 0; + uint32_t h_blank; + uint32_t h_back_porch; + uint8_t synchronous_clock = 0; /* asynchronous mode */ + uint8_t colorimetry_bpc; +#endif struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_DB_CNTL)) + REG_UPDATE(DP_DB_CNTL, DP_DB_DISABLE, 1); +#endif + /* set pixel encoding */ switch (crtc_timing->pixel_encoding) { case PIXEL_ENCODING_YCBCR422: @@ -249,6 +334,10 @@ static void dce110_stream_encoder_dp_set_stream_attribute( if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->DP_VID_N_MUL) + REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); +#endif break; default: REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, @@ -256,6 +345,11 @@ static void dce110_stream_encoder_dp_set_stream_attribute( break; } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_MISC)) + misc1 = REG_READ(DP_MSA_MISC); +#endif + /* set color depth */ switch (crtc_timing->display_color_depth) { @@ -289,6 +383,128 @@ static void dce110_stream_encoder_dp_set_stream_attribute( DP_DYN_RANGE, 0, DP_YCBCR_RANGE, 0); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + switch (crtc_timing->display_color_depth) { + case COLOR_DEPTH_666: + colorimetry_bpc = 0; + break; + case COLOR_DEPTH_888: + colorimetry_bpc = 1; + break; + case COLOR_DEPTH_101010: + colorimetry_bpc = 2; + break; + case COLOR_DEPTH_121212: + colorimetry_bpc = 3; + break; + default: + colorimetry_bpc = 0; + break; + } + + misc0 = misc0 | synchronous_clock; + misc0 = colorimetry_bpc << 5; + + if (REG(DP_MSA_TIMING_PARAM1)) { + switch (output_color_space) { + case COLOR_SPACE_SRGB: + misc0 = misc0 | 0x0;; + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + break; + case COLOR_SPACE_SRGB_LIMITED: + misc0 = misc0 | 0x8; /* bit3=1 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + break; + case COLOR_SPACE_YCBCR601: + misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/; + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ + else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) + misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ + break; + case COLOR_SPACE_YCBCR709: + misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ + misc1 = misc1 & ~0x80; /* bit7 = 0*/ + if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) + misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ + else if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR444) + misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ + break; + case COLOR_SPACE_2020_RGB_FULLRANGE: + case COLOR_SPACE_2020_RGB_LIMITEDRANGE: + case COLOR_SPACE_2020_YCBCR: + case COLOR_SPACE_ADOBERGB: + case COLOR_SPACE_UNKNOWN: + case COLOR_SPACE_YCBCR601_LIMITED: + case COLOR_SPACE_YCBCR709_LIMITED: + /* do nothing */ + break; + } + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (REG(DP_MSA_COLORIMETRY)) + REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); + + if (REG(DP_MSA_MISC)) + REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ + + /* dcn new register + * dc_crtc_timing is vesa dmt struct. data from edid + */ + if (REG(DP_MSA_TIMING_PARAM1)) + REG_SET_2(DP_MSA_TIMING_PARAM1, 0, + DP_MSA_HTOTAL, crtc_timing->h_total, + DP_MSA_VTOTAL, crtc_timing->v_total); +#endif + + /* calcuate from vesa timing parameters + * h_active_start related to leading edge of sync + */ + + h_blank = crtc_timing->h_total - crtc_timing->h_border_left - + crtc_timing->h_addressable - crtc_timing->h_border_right; + + h_back_porch = h_blank - crtc_timing->h_front_porch - + crtc_timing->h_sync_width; + + /* start at begining of left border */ + h_active_start = crtc_timing->h_sync_width + h_back_porch; + + + v_active_start = crtc_timing->v_total - crtc_timing->v_border_top - + crtc_timing->v_addressable - crtc_timing->v_border_bottom - + crtc_timing->v_front_porch; + + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* start at begining of left border */ + if (REG(DP_MSA_TIMING_PARAM2)) + REG_SET_2(DP_MSA_TIMING_PARAM2, 0, + DP_MSA_HSTART, h_active_start, + DP_MSA_VSTART, v_active_start); + + if (REG(DP_MSA_TIMING_PARAM3)) + REG_SET_4(DP_MSA_TIMING_PARAM3, 0, + DP_MSA_HSYNCWIDTH, + crtc_timing->h_sync_width, + DP_MSA_HSYNCPOLARITY, + !crtc_timing->flags.HSYNC_POSITIVE_POLARITY, + DP_MSA_VSYNCWIDTH, + crtc_timing->v_sync_width, + DP_MSA_VSYNCPOLARITY, + !crtc_timing->flags.VSYNC_POSITIVE_POLARITY); + + /* HWDITH include border or overscan */ + if (REG(DP_MSA_TIMING_PARAM4)) + REG_SET_2(DP_MSA_TIMING_PARAM4, 0, + DP_MSA_HWIDTH, crtc_timing->h_border_left + + crtc_timing->h_addressable + crtc_timing->h_border_right, + DP_MSA_VHEIGHT, crtc_timing->v_border_top + + crtc_timing->v_addressable + crtc_timing->v_border_bottom); +#endif + } +#endif } static void dce110_stream_encoder_set_stream_attribute_helper( @@ -533,6 +749,19 @@ static void dce110_stream_encoder_update_hdmi_info_packets( dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->HDMI_DB_DISABLE) { + /* for bring up, disable dp double TODO */ + if (REG(HDMI_DB_CONTROL)) + REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); + + dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); + dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); + dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); + dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); + dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); + } +#endif } static void dce110_stream_encoder_stop_hdmi_info_packets( @@ -558,6 +787,26 @@ static void dce110_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC1_LINE, 0, HDMI_GENERIC1_SEND, 0); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* stop generic packets 2 & 3 on HDMI */ + if (REG(HDMI_GENERIC_PACKET_CONTROL2)) + REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, + HDMI_GENERIC0_CONT, 0, + HDMI_GENERIC0_LINE, 0, + HDMI_GENERIC0_SEND, 0, + HDMI_GENERIC1_CONT, 0, + HDMI_GENERIC1_LINE, 0, + HDMI_GENERIC1_SEND, 0); + + if (REG(HDMI_GENERIC_PACKET_CONTROL3)) + REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, + HDMI_GENERIC0_CONT, 0, + HDMI_GENERIC0_LINE, 0, + HDMI_GENERIC0_SEND, 0, + HDMI_GENERIC1_CONT, 0, + HDMI_GENERIC1_LINE, 0, + HDMI_GENERIC1_SEND, 0); +#endif } static void dce110_stream_encoder_update_dp_info_packets( @@ -621,6 +870,21 @@ static void dce110_stream_encoder_stop_dp_info_packets( DP_SEC_STREAM_ENABLE, 0); } +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (enc110->se_mask->DP_SEC_GSP7_ENABLE) { + REG_SET_10(DP_SEC_CNTL, 0, + DP_SEC_GSP0_ENABLE, 0, + DP_SEC_GSP1_ENABLE, 0, + DP_SEC_GSP2_ENABLE, 0, + DP_SEC_GSP3_ENABLE, 0, + DP_SEC_GSP4_ENABLE, 0, + DP_SEC_GSP5_ENABLE, 0, + DP_SEC_GSP6_ENABLE, 0, + DP_SEC_GSP7_ENABLE, 0, + DP_SEC_MPG_ENABLE, 0, + DP_SEC_STREAM_ENABLE, 0); + } +#endif /* this register shared with audio info frame. * therefore we need to keep master enabled * if at least one of the fields is not 0 */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h index 850e12a8db61..0b548cb3af14 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.h @@ -97,6 +97,23 @@ SE_COMMON_REG_LIST_DCE_BASE(id), \ SRI(AFMT_CNTL, DIG, id) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define SE_DCN_REG_LIST(id)\ + SE_COMMON_REG_LIST_BASE(id),\ + SRI(AFMT_CNTL, DIG, id),\ + SRI(AFMT_VBI_PACKET_CONTROL1, DIG, id),\ + SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \ + SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \ + SRI(DP_DB_CNTL, DP, id), \ + SRI(DP_MSA_MISC, DP, id), \ + SRI(DP_MSA_COLORIMETRY, DP, id), \ + SRI(DP_MSA_TIMING_PARAM1, DP, id), \ + SRI(DP_MSA_TIMING_PARAM2, DP, id), \ + SRI(DP_MSA_TIMING_PARAM3, DP, id), \ + SRI(DP_MSA_TIMING_PARAM4, DP, id), \ + SRI(HDMI_DB_CONTROL, DIG, id) +#endif + #define SE_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -311,6 +328,48 @@ SE_SF(DIG0_AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, mask_sh),\ SE_SF(DP0_DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define SE_COMMON_MASK_SH_LIST_DCN10(mask_sh)\ + SE_COMMON_MASK_SH_LIST_SOC(mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE_PENDING, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\ + SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP4_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP5_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP6_ENABLE, mask_sh),\ + SE_SF(DP0_DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, mask_sh),\ + SE_SF(DP0_DP_DB_CNTL, DP_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_MSA_COLORIMETRY, DP_MSA_MISC0, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_HTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM1, DP_MSA_VTOTAL, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_HSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM2, DP_MSA_VSTART, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_HSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM3, DP_MSA_VSYNCPOLARITY, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_HWIDTH, mask_sh),\ + SE_SF(DP0_DP_MSA_TIMING_PARAM4, DP_MSA_VHEIGHT, mask_sh),\ + SE_SF(DIG0_HDMI_DB_CONTROL, HDMI_DB_DISABLE, mask_sh),\ + SE_SF(DP0_DP_VID_TIMING, DP_VID_N_MUL, mask_sh) +#endif + struct dce_stream_encoder_shift { uint8_t AFMT_GENERIC_INDEX; uint8_t AFMT_GENERIC0_UPDATE; @@ -625,6 +684,16 @@ struct dce110_stream_enc_registers { uint32_t HDMI_ACR_48_0; uint32_t HDMI_ACR_48_1; uint32_t TMDS_CNTL; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + uint32_t DP_DB_CNTL; + uint32_t DP_MSA_MISC; + uint32_t DP_MSA_COLORIMETRY; + uint32_t DP_MSA_TIMING_PARAM1; + uint32_t DP_MSA_TIMING_PARAM2; + uint32_t DP_MSA_TIMING_PARAM3; + uint32_t DP_MSA_TIMING_PARAM4; + uint32_t HDMI_DB_CONTROL; +#endif }; struct dce110_stream_encoder { diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index dc4c16416370..c89df8acb458 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -947,6 +947,12 @@ static void program_scaler(const struct core_dc *dc, { struct tg_color color = {0}; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + /* TOFPGA */ + if (pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth == NULL) + return; +#endif + if (dc->public.debug.surface_visual_confirm) get_surface_visual_confirm_color(pipe_ctx, &color); else @@ -1113,6 +1119,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( program_scaler(dc, pipe_ctx); /* mst support - use total stream count */ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (pipe_ctx->mi->funcs->allocate_mem_input != NULL) +#endif pipe_ctx->mi->funcs->allocate_mem_input( pipe_ctx->mi, stream->public.timing.h_total, @@ -1637,6 +1646,26 @@ enum dc_status dce110_apply_ctx_to_hw( /*TODO: when pplib works*/ apply_min_clocks(dc, context, &clocks_state, true); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (context->fclk_khz + > dc->current_context->fclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; + clock.clocks_in_khz = context->fclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->fclk_khz = clock.clocks_in_khz; + } + if (context->dcfclk_khz + > dc->current_context->dcfclk_khz) { + struct dm_pp_clock_for_voltage_req clock; + + clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; + clock.clocks_in_khz = context->dcfclk_khz; + dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); + dc->current_context->dcfclk_khz = clock.clocks_in_khz; + } +#endif if (context->dispclk_khz > dc->current_context->dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h index cf6ecfcadd5e..fb61e333aefd 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services.h @@ -75,6 +75,10 @@ BREAK_TO_DEBUGGER(); \ } while (0) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include +#endif + #define dm_alloc(size) kzalloc(size, GFP_KERNEL) #define dm_realloc(ptr, size) krealloc(ptr, size, GFP_KERNEL) #define dm_free(ptr) kfree(ptr) diff --git a/drivers/gpu/drm/amd/display/dc/dm_services_types.h b/drivers/gpu/drm/amd/display/dc/dm_services_types.h index 408141c6776e..b28304531d8a 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_services_types.h +++ b/drivers/gpu/drm/amd/display/dc/dm_services_types.h @@ -69,6 +69,7 @@ enum dm_pp_clock_type { DM_PP_CLOCK_TYPE_ENGINE_CLK, /* System clock */ DM_PP_CLOCK_TYPE_MEMORY_CLK, DM_PP_CLOCK_TYPE_DCFCLK, + DM_PP_CLOCK_TYPE_DCEFCLK, DM_PP_CLOCK_TYPE_SOCCLK, DM_PP_CLOCK_TYPE_PIXELCLK, DM_PP_CLOCK_TYPE_DISPLAYPHYCLK, diff --git a/drivers/gpu/drm/amd/display/dc/gpio/Makefile b/drivers/gpu/drm/amd/display/dc/gpio/Makefile index 5e831aff4830..70d01a9e9676 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/Makefile +++ b/drivers/gpu/drm/amd/display/dc/gpio/Makefile @@ -37,6 +37,17 @@ AMD_DAL_GPIO_DCE120 = $(addprefix $(AMDDALPATH)/dc/gpio/dce120/,$(GPIO_DCE120)) AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCE120) +############################################################################### +# DCN 1x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +GPIO_DCN10 = hw_translate_dcn10.o hw_factory_dcn10.o + +AMD_DAL_GPIO_DCN10 = $(addprefix $(AMDDALPATH)/dc/gpio/dcn10/,$(GPIO_DCN10)) + +AMD_DISPLAY_FILES += $(AMD_DAL_GPIO_DCN10) +endif + ############################################################################### # Diagnostics on FPGA ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 29ba83d2c211..8a8b619a60a8 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -43,8 +43,10 @@ #include "dce80/hw_factory_dce80.h" #include "dce110/hw_factory_dce110.h" - #include "dce120/hw_factory_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/hw_factory_dcn10.h" +#endif #include "diagnostics/hw_factory_diag.h" @@ -77,6 +79,11 @@ bool dal_hw_factory_init( case DCE_VERSION_12_0: dal_hw_factory_dce120_init(factory); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_factory_dcn10_init(factory); + return true; +#endif default: ASSERT_CRITICAL(false); return false; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c index 872edda54536..36c082bda4ae 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c @@ -43,6 +43,10 @@ #include "dce80/hw_translate_dce80.h" #include "dce110/hw_translate_dce110.h" #include "dce120/hw_translate_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/hw_translate_dcn10.h" +#endif + #include "diagnostics/hw_translate_diag.h" /* @@ -71,6 +75,11 @@ bool dal_hw_translate_init( case DCE_VERSION_12_0: dal_hw_translate_dce120_init(translate); return true; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + dal_hw_translate_dcn10_init(translate); + return true; +#endif default: BREAK_TO_DEBUGGER(); return false; diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile index a636768d06d5..55603400acd9 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/Makefile +++ b/drivers/gpu/drm/amd/display/dc/i2caux/Makefile @@ -47,6 +47,17 @@ AMD_DAL_I2CAUX_DCE112 = $(addprefix $(AMDDALPATH)/dc/i2caux/dce112/,$(I2CAUX_DCE AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCE112) +############################################################################### +# DCN 1.0 family +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +I2CAUX_DCN1 = i2caux_dcn10.o + +AMD_DAL_I2CAUX_DCN1 = $(addprefix $(AMDDALPATH)/dc/i2caux/dcn10/,$(I2CAUX_DCN1)) + +AMD_DISPLAY_FILES += $(AMD_DAL_I2CAUX_DCN1) +endif + ############################################################################### # DCE 120 family ############################################################################### diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c index 0743265e933c..983645b1be78 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2caux.c @@ -59,6 +59,10 @@ #include "dce120/i2caux_dce120.h" +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/i2caux_dcn10.h" +#endif + #include "diagnostics/i2caux_diag.h" /* @@ -84,6 +88,10 @@ struct i2caux *dal_i2caux_create( return dal_i2caux_dce100_create(ctx); case DCE_VERSION_12_0: return dal_i2caux_dce120_create(ctx); + #if defined(CONFIG_DRM_AMD_DC_DCN1_0) + case DCN_VERSION_1_0: + return dal_i2caux_dcn10_create(ctx); + #endif default: BREAK_TO_DEBUGGER(); return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h index f9363f642f92..392cff2cd558 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_dc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_dc.h @@ -30,6 +30,11 @@ struct core_dc { /* Inputs into BW and WM calculations. */ struct bw_calcs_dceip bw_dceip; struct bw_calcs_vbios bw_vbios; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct dcn_soc_bounding_box dcn_soc; + struct dcn_ip_params dcn_ip; + struct display_mode_lib dml; +#endif /* HW functions */ struct hw_sequencer_funcs hwss; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 9e5e0ba5b10b..c1273d6142c4 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -28,8 +28,11 @@ #include "dc.h" #include "dce_calcs.h" +#include "dcn_calcs.h" #include "ddc_service_types.h" #include "dc_bios_types.h" +#include "mem_input.h" +#include "mpc.h" struct core_stream; @@ -254,6 +257,7 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; + struct mpc *mpc; const struct resource_funcs *funcs; const struct resource_caps *res_cap; @@ -287,10 +291,20 @@ struct pipe_ctx { struct pipe_ctx *top_pipe; struct pipe_ctx *bottom_pipe; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + uint8_t mpc_idx; + struct _vcs_dpi_display_dlg_regs_st dlg_regs; + struct _vcs_dpi_display_ttu_regs_st ttu_regs; + struct _vcs_dpi_display_rq_regs_st rq_regs; + struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; +#endif }; struct resource_context { struct pipe_ctx pipe_ctx[MAX_PIPES]; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + struct mpc_tree_cfg mpc_tree[MAX_PIPES]; +#endif bool is_stream_enc_acquired[MAX_PIPES * 2]; bool is_audio_acquired[MAX_PIPES]; uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; @@ -309,6 +323,18 @@ struct validate_context { /* Note: these are big structures, do *not* put on stack! */ struct dm_pp_display_configuration pp_display_cfg; int dispclk_khz; +#ifdef CONFIG_DRM_AMD_DC_DCN1_0 + int dppclk_khz; + bool dppclk_div; + int dcfclk_khz; + int dcfclk_deep_sleep_khz; + int socclk_khz; + int fclk_khz; + int dram_ccm_us; + int min_active_dram_ccm_us; + struct dcn_watermark_set watermarks; + struct dcn_bw_internal_vars dcn_bw_vars; +#endif }; #endif /* _CORE_TYPES_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h index 97f26b55535f..240ab11d1d30 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/display_clock.h @@ -37,6 +37,13 @@ struct clocks_value { bool dispclk_notify_pplib_done; bool pixelclk_notify_pplib_done; bool phyclk_notigy_pplib_done; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + int dcfclock_in_khz; + int dppclk_in_khz; + int mclk_in_khz; + int phyclk_in_khz; + int common_vdd_level; +#endif }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h index 2d472d8ef555..0f952e5b3ae8 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/ipp.h @@ -122,6 +122,7 @@ struct ipp_funcs { struct input_pixel_processor *ipp, const struct pwl_params *params); + void (*ipp_destroy)(struct input_pixel_processor **ipp); }; #endif /* __DAL_IPP_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 179f5ad70f48..0880ce98c90c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -31,6 +31,30 @@ #include "dce/dce_mem_input.h" /* temporary */ +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dml/display_mode_structs.h" + +struct cstate_pstate_watermarks_st { + uint32_t cstate_exit_ns; + uint32_t cstate_enter_plus_exit_ns; + uint32_t pstate_change_ns; +}; + +struct dcn_watermarks { + uint32_t pte_meta_urgent_ns; + uint32_t urgent_ns; + struct cstate_pstate_watermarks_st cstate_pstate; +}; + +struct dcn_watermark_set { + struct dcn_watermarks a; + struct dcn_watermarks b; + struct dcn_watermarks c; + struct dcn_watermarks d; +}; + +#endif + struct stutter_modes { bool enhanced; bool quad_dmif_buffer; @@ -52,6 +76,23 @@ struct mem_input { }; struct mem_input_funcs { +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_watermarks)( + struct mem_input *mem_input, + struct dcn_watermark_set *watermarks, + unsigned int refclk_period_ns); + + void (*mem_input_setup)( + struct mem_input *mem_input, + struct _vcs_dpi_display_dlg_regs_st *dlg_regs, + struct _vcs_dpi_display_ttu_regs_st *ttu_regs, + struct _vcs_dpi_display_rq_regs_st *rq_regs, + struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest); + + void (*disable_request)(struct mem_input *mem_input); + +#endif + void (*mem_input_program_display_marks)( struct mem_input *mem_input, struct bw_watermarks nbp, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h new file mode 100644 index 000000000000..2e86ebe5eeda --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -0,0 +1,110 @@ +/* Copyright 2012-15 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __DC_MPC_H__ +#define __DC_MPC_H__ + +/* define the maximum number of pipes + * MAX_NUM_PIPPES = MAX_PIPES defined in core_type.h + */ +enum { + MAX_NUM_PIPPES = 6 +}; + +enum blend_mode { + DIGI_BYPASS = 0, /* digital bypass */ + TOP_PASSTHRU, /* top layer pass through */ + TOP_BLND /* top layer blend */ +}; + +/* This structure define the mpc tree configuration + * num_pipes - number of pipes of the tree + * opp_id - instance id of OPP to drive MPC + * dpp- array of DPP index + * mpcc - array of MPCC index + * mode - the most bottom layer MPCC mode control. + * All other layers need to be program to 3 + * + * The connection will be: + * mpcc[num_pipes-1]->mpcc[num_pipes-2]->...->mpcc[1]->mpcc[0]->OPP[opp_id] + * dpp[0]->mpcc[0] + * dpp[1]->mpcc[1] + * ... + * dpp[num_pipes-1]->mpcc[num_pipes-1] + * mpcc[0] is the most top layer of MPC tree, + * mpcc[num_pipes-1] is the most bottom layer. + */ + +struct mpc_tree_cfg { + uint8_t num_pipes; + uint8_t opp_id; + /* dpp pipes for blend */ + uint8_t dpp[MAX_NUM_PIPPES]; + /* mpcc insatnces for blend */ + uint8_t mpcc[MAX_NUM_PIPPES]; + enum blend_mode mode; +}; + +struct mpcc_blnd_cfg { + /* 0- perpixel alpha, 1- perpixel alpha combined with global gain, + * 2- global alpha + */ + uint8_t alpha_mode; + uint8_t global_gain; + uint8_t global_alpha; + bool overlap_only; + bool pre_multiplied_alpha; +}; + +struct mpcc_sm_cfg { + bool enable; + /* 0-single plane, 2-row subsampling, 4-column subsampling, + * 6-checkboard subsampling + */ + uint8_t sm_mode; + bool frame_alt; /* 0- disable, 1- enable */ + bool field_alt; /* 0- disable, 1- enable */ + /* 0-no force, 2-force frame polarity from top, + * 3-force frame polarity from bottom + */ + uint8_t force_next_frame_porlarity; + /* 0-no force, 2-force field polarity from top, + * 3-force field polarity from bottom + */ + uint8_t force_next_field_polarity; +}; + +struct mpcc_vupdate_lock_cfg { + bool cfg_lock; + bool adr_lock; + bool adr_cfg_lock; + bool cur0_lock; + bool cur1_lock; +}; + +struct mpc { + struct dc_context *ctx; +}; + +#endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index 92c99c3b9002..64d43257db96 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -27,6 +27,7 @@ #define __DAL_OPP_H__ #include "hw_shared.h" +#include "dc_hw_types.h" #include "transform.h" struct fixed31_32; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 00cdaaae455c..9f130affb31c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -91,10 +91,22 @@ enum crtc_state { CRTC_STATE_VBLANK = 0, CRTC_STATE_VACTIVE }; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +struct _dlg_otg_param { + int vstartup_start; + int vupdate_offset; + int vupdate_width; + int vready_offset; + enum signal_type signal; +}; +#endif struct timing_generator { const struct timing_generator_funcs *funcs; struct dc_bios *bp; struct dc_context *ctx; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + struct _dlg_otg_param dlg_otg_param; +#endif int inst; }; @@ -155,6 +167,10 @@ struct timing_generator_funcs { bool (*arm_vert_intr)(struct timing_generator *tg, uint8_t width); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + void (*program_global_sync)(struct timing_generator *tg); + void (*enable_optc_clock)(struct timing_generator *tg, bool enable); +#endif }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/Makefile b/drivers/gpu/drm/amd/display/dc/irq/Makefile index 222f36e3074f..c7e93f7223bd 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/Makefile +++ b/drivers/gpu/drm/amd/display/dc/irq/Makefile @@ -36,3 +36,13 @@ AMD_DAL_IRQ_DCE12 = $(addprefix $(AMDDALPATH)/dc/irq/dce120/,$(IRQ_DCE12)) AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCE12) +############################################################################### +# DCN 1x +############################################################################### +ifdef CONFIG_DRM_AMD_DC_DCN1_0 +IRQ_DCN1 = irq_service_dcn10.o + +AMD_DAL_IRQ_DCN1 = $(addprefix $(AMDDALPATH)/dc/irq/dcn10/,$(IRQ_DCN1)) + +AMD_DISPLAY_FILES += $(AMD_DAL_IRQ_DCN1) +endif diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index 5255c14254df..0a1fae4ef83a 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -35,6 +35,11 @@ #include "dce120/irq_service_dce120.h" + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#include "dcn10/irq_service_dcn10.h" +#endif + #include "reg_helper.h" #include "irq_service.h" diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 6dab058f8f3c..3d2ed5c83734 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -109,6 +109,19 @@ #define ASIC_REV_IS_STONEY(rev) \ ((rev >= STONEY_A0) && (rev < CZ_UNKNOWN)) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +/* DCN1_0 */ +#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */ +#define RAVEN_A0 0x01 +#define RAVEN_UNKNOWN 0xFF + +#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) +#endif + +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) +#define FAMILY_RV 142 /* DCN 1*/ +#endif + /* * ASIC chip ID */ diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 0cefde14aa02..50a2a3ebf36d 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -39,7 +39,10 @@ enum dce_version { DCE_VERSION_11_0, DCE_VERSION_11_2, DCE_VERSION_12_0, - DCE_VERSION_MAX, +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + DCN_VERSION_1_0, +#endif + DCN_VERSION_MAX }; #endif /* __DAL_TYPES_H__ */ -- cgit v1.2.3 From e806208dc1daebf3b236d0188709d943cf0d9f16 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 12 May 2017 16:19:15 -0400 Subject: drm/amd/display: Fix slow FPS. Typo in expresion. Signed-off-by: Andrey Grodzovsky Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4ec86ed5622f..a2c00c0bf007 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -135,8 +135,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, &h_position, &v_position); - *position = (v_position) || (h_position << 16); - *vbl = (v_blank_start) || (v_blank_end << 16); + *position = v_position | (h_position << 16); + *vbl = v_blank_start | (v_blank_end << 16); } return 0; -- cgit v1.2.3 From 3379da831b4032e3d7cac2cb199293e59f0c9e9f Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 15 May 2017 13:59:31 -0400 Subject: drm/amd/display: Use dc_update_surfaces_for_stream for flip. Today we use special interface for flip because of fear of cuncurency issues over dc->current_ctx. This should be no longer an issue when flipping on multiple CRTCs concurently since for fast update (as flip is) no new context is created and the exsisitng is not destroyed. For full updates case when removing or adding streams on once CRTC while flipping on another Adding all current active CRTC's states to the atomic commit in amdgpu_dm_atomic_check will garntee that any such full update commit will wait for completion of any outstanding flip. Signed-off-by: Andrey Grodzovsky Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++++--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 23 +++++++++++++++++++++- 2 files changed, 28 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a2c00c0bf007..7e28f9870b86 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1349,6 +1349,7 @@ static void dm_page_flip(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc; const struct dc_stream *stream; struct dc_flip_addrs addr = { {0} }; + struct dc_surface_update surface_updates[1] = { {0} }; /* * TODO risk of concurrency issues @@ -1411,9 +1412,11 @@ static void dm_page_flip(struct amdgpu_device *adev, acrtc->base.state->event = NULL; } - dc_flip_surface_addrs(adev->dm.dc, - dc_stream_get_status(stream)->surfaces, - &addr, 1); + surface_updates->surface = dc_stream_get_status(stream)->surfaces[0]; + surface_updates->flip_addr = &addr; + + + dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, stream); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 9c0dc9d07626..7d989b6738e4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2901,6 +2901,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dc *dc = adev->dm.dc; bool need_to_validate = false; struct validate_context *context; + bool wait_4_prev_commits = false; ret = drm_atomic_helper_check(dev, state); @@ -2977,6 +2978,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_stream_count++; need_to_validate = true; + wait_4_prev_commits = true; break; } @@ -3022,6 +3024,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_stream_count++; need_to_validate = true; + wait_4_prev_commits = true; break; } @@ -3033,6 +3036,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, set, set_count, acrtc->stream); + wait_4_prev_commits = true; } break; } @@ -3125,9 +3129,26 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, context = dc_get_validate_context(dc, set, set_count); - if (need_to_validate == false || set_count == 0 || context) + if (need_to_validate == false || set_count == 0 || context) { + ret = 0; + if (wait_4_prev_commits) { + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct drm_crtc_state *crtc_state; + + if (acrtc->stream) { + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + break; + } + } + } + } + } + if (context) { dc_resource_validate_ctx_destruct(context); dm_free(context); -- cgit v1.2.3 From 21de3396b44a67429c6b6a3f2d697fb261c76054 Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Mon, 22 May 2017 13:11:15 +0800 Subject: drm/amd/display: call amdgpu_dm_fini when hw_fini. to free up drm mode_config info. fix issue: unload amdgpu, can't load amdgpu again. [drm:drm_debugfs_init [drm]] *ERROR* Cannot create /sys/kernel/debug/dri/0 [drm:drm_minor_register [drm]] *ERROR* DRM: Failed to initialize /sys/kernel/debug/dri. Signed-off-by: Rex Zhu Acked-by: Alex Deucher Reviewed-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 ++--- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++++- 2 files changed, 8 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7e28f9870b86..74415fdf7ed8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -395,9 +395,8 @@ void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } /* DC Destroy TODO: Replace destroy DAL */ - { + if (adev->dm.dc) dc_destroy(&adev->dm.dc); - } return; } @@ -490,7 +489,7 @@ static int dm_hw_fini(void *handle) amdgpu_dm_hpd_fini(adev); amdgpu_dm_irq_fini(adev); - + amdgpu_dm_fini(adev); return 0; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 773f0efc449b..b428c7c6559b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1541,7 +1541,12 @@ enum dc_irq_source dc_interrupt_to_irq_source( void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable) { - struct core_dc *core_dc = DC_TO_CORE(dc); + struct core_dc *core_dc; + + if (dc == NULL) + return; + core_dc = DC_TO_CORE(dc); + dal_irq_service_set(core_dc->res_pool->irqs, src, enable); } -- cgit v1.2.3 From 1605b3bef8454a8906333f7a0ca0fb177422100d Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 5 Apr 2017 12:02:45 -0400 Subject: drm/amd/display: Remove redundant member from amdgpu_plane. Signed-off-by: Andrey Grodzovsky Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 74415fdf7ed8..6b25a7ba2f7d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1203,7 +1203,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) DRM_ERROR("KMS: Failed to allocate surface\n"); goto fail_free_planes; } - mode_info->planes[i]->plane_type = mode_info->plane_type[i]; + mode_info->planes[i]->base.type = mode_info->plane_type[i]; if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) { DRM_ERROR("KMS: Failed to initialize plane\n"); goto fail_free_planes; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 068ed85bdc6d..b99f6ef499d1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1557,7 +1557,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, { int res = -EPERM; - switch (aplane->plane_type) { + switch (aplane->base.type) { case DRM_PLANE_TYPE_PRIMARY: aplane->base.format_default = true; @@ -1568,7 +1568,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, &dm_plane_funcs, rgb_formats, ARRAY_SIZE(rgb_formats), - NULL, aplane->plane_type, NULL); + NULL, aplane->base.type, NULL); break; case DRM_PLANE_TYPE_OVERLAY: res = drm_universal_plane_init( @@ -1578,7 +1578,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, &dm_plane_funcs, yuv_formats, ARRAY_SIZE(yuv_formats), - NULL, aplane->plane_type, NULL); + NULL, aplane->base.type, NULL); break; case DRM_PLANE_TYPE_CURSOR: res = drm_universal_plane_init( @@ -1588,7 +1588,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, &dm_plane_funcs, cursor_formats, ARRAY_SIZE(cursor_formats), - NULL, aplane->plane_type, NULL); + NULL, aplane->base.type, NULL); break; } -- cgit v1.2.3 From 70470154104e935eed36478169550eda577dcdb3 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Sun, 4 Jun 2017 09:11:56 -0400 Subject: drm/amd/display: Get rid of seperate flip function. This code is remanant of pre atomic age when flip was a standalone IOCTL. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 97 ---------------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 37 ++++++++- 2 files changed, 34 insertions(+), 100 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6b25a7ba2f7d..df4cccb4be7a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1328,102 +1328,6 @@ static u8 dm_get_backlight_level(struct amdgpu_encoder *amdgpu_encoder) return 0; } -/****************************************************************************** - * Page Flip functions - ******************************************************************************/ - -/** - * dm_page_flip - called by amdgpu_flip_work_func(), which is triggered - * via DRM IOCTL, by user mode. - * - * @adev: amdgpu_device pointer - * @crtc_id: crtc to cleanup pageflip on - * @crtc_base: new address of the crtc (GPU MC address) - * - * Does the actual pageflip (surface address update). - */ -static void dm_page_flip(struct amdgpu_device *adev, - int crtc_id, u64 crtc_base, bool async) -{ - struct amdgpu_crtc *acrtc; - const struct dc_stream *stream; - struct dc_flip_addrs addr = { {0} }; - struct dc_surface_update surface_updates[1] = { {0} }; - - /* - * TODO risk of concurrency issues - * - * This should guarded by the dal_mutex but we can't do this since the - * caller uses a spin_lock on event_lock. - * - * If we wait on the dal_mutex a second page flip interrupt might come, - * spin on the event_lock, disabling interrupts while it does so. At - * this point the core can no longer be pre-empted and return to the - * thread that waited on the dal_mutex and we're deadlocked. - * - * With multiple cores the same essentially happens but might just take - * a little longer to lock up all cores. - * - * The reason we should lock on dal_mutex is so that we can be sure - * nobody messes with acrtc->stream after we read and check its value. - * - * We might be able to fix our concurrency issues with a work queue - * where we schedule all work items (mode_set, page_flip, etc.) and - * execute them one by one. Care needs to be taken to still deal with - * any potential concurrency issues arising from interrupt calls. - */ - - acrtc = adev->mode_info.crtcs[crtc_id]; - stream = acrtc->stream; - - - if (acrtc->pflip_status != AMDGPU_FLIP_NONE) { - DRM_ERROR("flip queue: acrtc %d, already busy\n", acrtc->crtc_id); - /* In commit tail framework this cannot happen */ - BUG_ON(0); - } - - - /* - * Received a page flip call after the display has been reset. - * Just return in this case. Everything should be clean-up on reset. - */ - - if (!stream) { - WARN_ON(1); - return; - } - - addr.address.grph.addr.low_part = lower_32_bits(crtc_base); - addr.address.grph.addr.high_part = upper_32_bits(crtc_base); - addr.flip_immediate = async; - - - if (acrtc->base.state->event && - acrtc->base.state->event->event.base.type == - DRM_EVENT_FLIP_COMPLETE) { - acrtc->event = acrtc->base.state->event; - - /* Set the flip status */ - acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; - - /* Mark this event as consumed */ - acrtc->base.state->event = NULL; - } - - surface_updates->surface = dc_stream_get_status(stream)->surfaces[0]; - surface_updates->flip_addr = &addr; - - - dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, stream); - - DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", - __func__, - addr.address.grph.addr.high_part, - addr.address.grph.addr.low_part); - -} - static int amdgpu_notify_freesync(struct drm_device *dev, void *data, struct drm_file *filp) { @@ -1460,7 +1364,6 @@ static const struct amdgpu_display_funcs dm_display_funcs = { .hpd_sense = NULL,/* called unconditionally */ .hpd_set_polarity = NULL, /* called unconditionally */ .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */ - .page_flip = dm_page_flip, /* called unconditionally */ .page_flip_get_scanoutpos = dm_crtc_get_scanoutpos,/* called unconditionally */ .add_encoder = NULL, /* VBIOS parsing. DAL does it. */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 165f91fa1206..6c4d0d1d4367 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2198,6 +2198,8 @@ static void amdgpu_dm_do_flip( struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj); struct amdgpu_device *adev = crtc->dev->dev_private; bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + struct dc_flip_addrs addr = { {0} }; + struct dc_surface_update surface_updates[1] = { {0} }; /* Prepare wait for target vblank early - before the fence-waits */ target_vblank = target - drm_crtc_vblank_count(crtc) + @@ -2211,7 +2213,7 @@ static void amdgpu_dm_do_flip( r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) { DRM_ERROR("failed to reserve buffer before flip\n"); - BUG_ON(0); + WARN_ON(1); } /* Wait for all fences on this FB */ @@ -2239,8 +2241,37 @@ static void amdgpu_dm_do_flip( /* update crtc fb */ crtc->primary->fb = fb; - /* Do the flip (mmio) */ - adev->mode_info.funcs->page_flip(adev, acrtc->crtc_id, afb->address, async_flip); + WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); + WARN_ON(!acrtc->stream); + + addr.address.grph.addr.low_part = lower_32_bits(afb->address); + addr.address.grph.addr.high_part = upper_32_bits(afb->address); + addr.flip_immediate = async_flip; + + + if (acrtc->base.state->event && + acrtc->base.state->event->event.base.type == + DRM_EVENT_FLIP_COMPLETE) { + acrtc->event = acrtc->base.state->event; + + /* Set the flip status */ + acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + + /* Mark this event as consumed */ + acrtc->base.state->event = NULL; + } + + surface_updates->surface = dc_stream_get_status(acrtc->stream)->surfaces[0]; + surface_updates->flip_addr = &addr; + + + dc_update_surfaces_for_stream(adev->dm.dc, surface_updates, 1, acrtc->stream); + + DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", + __func__, + addr.address.grph.addr.high_part, + addr.address.grph.addr.low_part); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", -- cgit v1.2.3 From 1159898a88db33877bd8378714c6f647afab7f9b Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 7 Jun 2017 18:28:43 -0400 Subject: drm/amd/display: Handle commit plane with no FB. 1) Always call flip ISR, for any surface comit, not only for page flip. 2) For events not signaled in flip ISR, handle them in end of commit_tail. 3)Fix race condition between subsequent atomic calls by removing current state access AFTER drm_atomic_helper_commit_hw_done was called. After this call a pending next commit will swap in his own state into objects and proceed. Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 127 +++++++++++---------- 2 files changed, 70 insertions(+), 63 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index df4cccb4be7a..98e0dbe2a4de 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -222,15 +222,15 @@ static void dm_pflip_high_irq(void *interrupt_params) /* wakeup usersapce */ - if (amdgpu_crtc->event - && amdgpu_crtc->event->event.base.type - == DRM_EVENT_FLIP_COMPLETE) { + if (amdgpu_crtc->event) { /* Update to correct count/ts if racing with vblank irq */ drm_crtc_accurate_vblank_count(&amdgpu_crtc->base); drm_crtc_send_vblank_event(&amdgpu_crtc->base, amdgpu_crtc->event); + /* page flip completed. clean up */ amdgpu_crtc->event = NULL; + } else WARN_ON(1); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 6c4d0d1d4367..b19536d0e045 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2180,6 +2180,24 @@ static void handle_cursor_update( } +static void prepare_flip_isr(struct amdgpu_crtc *acrtc) +{ + + assert_spin_locked(&acrtc->base.dev->event_lock); + WARN_ON(acrtc->event); + + acrtc->event = acrtc->base.state->event; + + /* Set the flip status */ + acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + + /* Mark this event as consumed */ + acrtc->base.state->event = NULL; + + DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", + acrtc->crtc_id); +} + /* * Executes flip * @@ -2249,17 +2267,8 @@ static void amdgpu_dm_do_flip( addr.flip_immediate = async_flip; - if (acrtc->base.state->event && - acrtc->base.state->event->event.base.type == - DRM_EVENT_FLIP_COMPLETE) { - acrtc->event = acrtc->base.state->event; - - /* Set the flip status */ - acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; - - /* Mark this event as consumed */ - acrtc->base.state->event = NULL; - } + if (acrtc->base.state->event) + prepare_flip_isr(acrtc); surface_updates->surface = dc_stream_get_status(acrtc->stream)->surfaces[0]; surface_updates->flip_addr = &addr; @@ -2274,8 +2283,6 @@ static void amdgpu_dm_do_flip( spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", - acrtc->crtc_id); } static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, @@ -2289,13 +2296,13 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane_state *old_plane_state; const struct dc_stream *dc_stream_attach; const struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); int planes_count = 0; /* update planes when needed */ for_each_plane_in_state(state, plane, old_plane_state, i) { struct drm_plane_state *plane_state = plane->state; struct drm_crtc *crtc = plane_state->crtc; - struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(crtc); struct drm_framebuffer *fb = plane_state->fb; struct drm_connector *connector; struct dm_connector_state *con_state = NULL; @@ -2306,7 +2313,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, continue; } - if (!fb || !crtc || !crtc->state->active) + if (!fb || !crtc || pcrtc != crtc || !crtc->state->active) continue; pflip_needed = !state->allow_modeset; @@ -2339,17 +2346,21 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, continue; - if (crtc == pcrtc) { - add_surface(dm->dc, crtc, plane, - &dc_surfaces_constructed[planes_count]); - if (dc_surfaces_constructed[planes_count] == NULL) { - dm_error("%s: Failed to add surface!\n", __func__); - continue; - } - dc_stream_attach = acrtc_attach->stream; - planes_count++; + + add_surface(dm->dc, crtc, plane, + &dc_surfaces_constructed[planes_count]); + if (dc_surfaces_constructed[planes_count] == NULL) { + dm_error("%s: Failed to add surface!\n", __func__); + continue; } + dc_stream_attach = acrtc_attach->stream; + planes_count++; + } else if (crtc->state->planes_changed) { + /* Assume even ONE crtc with immediate flip means + * entire can't wait for VBLANK + * TODO Check if it's correct + */ *wait_for_vblank = acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? false : true; @@ -2359,6 +2370,8 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, fb, drm_crtc_vblank_count(crtc) + *wait_for_vblank); + /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */ + /*clean up the flags for next usage*/ acrtc_attach->flip_flags = 0; } @@ -2366,15 +2379,27 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, } if (planes_count) { + unsigned long flags; + + if (pcrtc->state->event) { + + drm_crtc_vblank_get(pcrtc); + + spin_lock_irqsave(&pcrtc->dev->event_lock, flags); + prepare_flip_isr(acrtc_attach); + spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); + } + if (false == dc_commit_surfaces_to_stream(dm->dc, dc_surfaces_constructed, planes_count, - dc_stream_attach)) { + dc_stream_attach)) dm_error("%s: Failed to attach surface!\n", __func__); - return; - } + for (i = 0; i < planes_count; i++) dc_surface_release(dc_surfaces_constructed[i]); + } else { + /*TODO BUG Here should go disable planes on CRTC. */ } } @@ -2405,7 +2430,6 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc_state *new_state = crtc->state; acrtc = to_amdgpu_crtc(crtc); - aconnector = amdgpu_dm_find_first_crct_matching_connector( state, @@ -2571,14 +2595,6 @@ void amdgpu_dm_atomic_commit_tail( dc_stream_get_status(acrtc->stream)->primary_otg_inst; } - /* update planes when needed per crtc*/ - for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(pcrtc); - - if (acrtc->stream) - amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); - } - for (i = 0; i < new_crtcs_count; i++) { /* * loop to enable interrupts on newly arrived crtc @@ -2592,19 +2608,27 @@ void amdgpu_dm_atomic_commit_tail( manage_dm_interrupts(adev, acrtc, true); } + /* update planes when needed per crtc*/ + for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(pcrtc); + + if (acrtc->stream) + amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); + } + - /*TODO mark consumed event on all crtc assigned event - * in drm_atomic_helper_setup_commit just to signal completion + /* + * send vblank event on all events not handled in flip and + * mark consumed event for drm_atomic_helper_commit_hw_done */ spin_lock_irqsave(&adev->ddev->event_lock, flags); for_each_crtc_in_state(state, crtc, old_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (acrtc->base.state->event && - acrtc->base.state->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) { - acrtc->event = acrtc->base.state->event; - acrtc->base.state->event = NULL; - } + if (acrtc->base.state->event) + drm_send_event_locked(dev, &crtc->state->event->base); + + acrtc->base.state->event = NULL; } spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -2614,23 +2638,6 @@ void amdgpu_dm_atomic_commit_tail( if (wait_for_vblank) drm_atomic_helper_wait_for_vblanks(dev, state); - /*TODO send vblank event on all crtc assigned event - * in drm_atomic_helper_setup_commit just to signal completion - */ - spin_lock_irqsave(&adev->ddev->event_lock, flags); - for_each_crtc_in_state(state, crtc, old_crtc_state, i) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - - if (acrtc->event && - acrtc->event->event.base.type != DRM_EVENT_FLIP_COMPLETE) { - drm_send_event_locked(dev, &acrtc->event->base); - acrtc->event = NULL; - } - } - spin_unlock_irqrestore(&adev->ddev->event_lock, flags); - - /*TODO Is it to early if actual flip haven't happened yet ?*/ - /* Release old FB */ drm_atomic_helper_cleanup_planes(dev, state); } -- cgit v1.2.3 From 92f3ac403d132400b7147bb4262fea4ad254aa3d Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Fri, 16 Jun 2017 15:59:17 -0400 Subject: drm/amd/display: Workaround IGT multiplane restriction IGT currently does not properly commit changes on planes with multiple possible CRTC's. Set one valid CRTC for each plane for now, plus one underlay plane on Carizzo and Stoney that is valid for all CRTCs. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 98e0dbe2a4de..f018de2e7dfe 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1189,6 +1189,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) struct amdgpu_encoder *aencoder = NULL; struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; + unsigned long possible_crtcs; link_cnt = dm->dc->caps.max_links; if (amdgpu_dm_mode_config_init(dm->adev)) { @@ -1204,7 +1205,18 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_planes; } mode_info->planes[i]->base.type = mode_info->plane_type[i]; - if (amdgpu_dm_plane_init(dm, mode_info->planes[i], 0xff)) { + + /* + * HACK: IGT tests expect that each plane can only have one + * one possible CRTC. For now, set one CRTC for each + * plane that is not an underlay, but still allow multiple + * CRTCs for underlay planes. + */ + possible_crtcs = 1 << i; + if (i >= dm->dc->caps.max_streams) + possible_crtcs = 0xff; + + if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) { DRM_ERROR("KMS: Failed to initialize plane\n"); goto fail_free_planes; } -- cgit v1.2.3 From d7ec53d9dd0086644aa97d22463976b04b51307e Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 4 Jul 2017 13:28:57 -0400 Subject: drm/amd/display: Move kms_atomic support flag to dm_early_init. Signed-off-by: Andrey Grodzovsky Reviewed-by: Jordan Lazare Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a350fc9b2a70..2368792b7d67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2071,10 +2071,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; - if (amdgpu_device_has_dc_support(adev)) - adev->ddev->driver->driver_features |= DRIVER_ATOMIC; - - DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n", amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device, pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f018de2e7dfe..8062f8c18114 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1421,6 +1421,7 @@ static int dm_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + adev->ddev->driver->driver_features |= DRIVER_ATOMIC; amdgpu_dm_set_irq_funcs(adev); switch (adev->asic_type) { -- cgit v1.2.3 From b3663f705a522b7807a1916c94a24448c6a40abc Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 27 Jun 2017 11:12:37 -0400 Subject: drm/amd/display: Make mode_config_funcs const Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8062f8c18114..353165c6da1e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -634,8 +634,7 @@ const struct amdgpu_ip_block_version dm_ip_block = .funcs = &amdgpu_dm_funcs, }; -/* TODO: it is temporary non-const, should fixed later */ -static struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { +static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, -- cgit v1.2.3 From ca3268c45b85d61365ba74939650ae519ecff572 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 27 Jun 2017 11:55:43 -0400 Subject: drm/amd/display: Create dm_atomic_state We really want to use the new private_atomic_state but can't right now as we have to maintain some backward compatibility to older kernels. For now let's follow Intel's approach and extend the drm_atomic_state. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 +++++++++++++++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 8 +++++ 2 files changed, 44 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 353165c6da1e..a95c9ba64235 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -634,11 +634,46 @@ const struct amdgpu_ip_block_version dm_ip_block = .funcs = &amdgpu_dm_funcs, }; + +struct drm_atomic_state * +dm_atomic_state_alloc(struct drm_device *dev) +{ + struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + + if (!state || drm_atomic_state_init(dev, &state->base) < 0) { + kfree(state); + return NULL; + } + + return &state->base; +} + +void dm_atomic_state_clear(struct drm_atomic_state *s) +{ + struct dm_atomic_state *state = to_dm_atomic_state(s); + drm_atomic_state_default_clear(&state->base); +} + + +static void dm_atomic_state_free(struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + + drm_atomic_state_default_release(state); + + kfree(dm_state); +} + + + static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, - .atomic_commit = drm_atomic_helper_commit + .atomic_commit = drm_atomic_helper_commit, + .atomic_state_alloc = dm_atomic_state_alloc, + .atomic_state_clear = dm_atomic_state_clear, + .atomic_state_free = dm_atomic_state_free, }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index bf20d57a99e0..9ba7fdd20519 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -27,6 +27,7 @@ #define __AMDGPU_DM_TYPES_H__ #include +#include struct amdgpu_framebuffer; struct amdgpu_display_manager; @@ -48,6 +49,13 @@ struct dm_crtc_state { #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) +struct dm_atomic_state { + struct drm_atomic_state base; +}; + +#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) + + /*TODO Jodan Hersen use the one in amdgpu_dm*/ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, struct amdgpu_plane *aplane, -- cgit v1.2.3 From b29fc8661d5c732a5689afa751983ee27141ad37 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 3 Mar 2017 14:50:00 -0500 Subject: drm/amd/display: Add correct retain/release Needed by objs in dm_atomic_state Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 6 ++++++ 2 files changed, 16 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a95c9ba64235..ba20a8cce7df 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -658,9 +658,19 @@ void dm_atomic_state_clear(struct drm_atomic_state *s) static void dm_atomic_state_free(struct drm_atomic_state *state) { struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + int i, j; drm_atomic_state_default_release(state); + for (i = 0; i < dm_state->set_count; i++) { + for (j = 0; j < dm_state->set[i].surface_count; j++) { + dc_surface_release(dm_state->set[i].surfaces[j]); + } + } + + for (i = 0; i < dm_state->set_count; i++) + dc_stream_release(dm_state->set[i].stream); + kfree(dm_state); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 751dd13b54e3..54d31f474d76 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2874,11 +2874,15 @@ static uint32_t update_in_val_sets_stream( } val_sets[i].stream = new_stream; + dc_stream_retain(new_stream); crtcs[i] = crtc; if (i == set_count) { /* nothing found. add new one to the end */ return set_count + 1; + } else { + /* update. relase old stream */ + dc_stream_release(old_stream); } return set_count; @@ -2900,6 +2904,7 @@ static uint32_t remove_from_val_sets( return set_count; } + dc_stream_release(stream); set_count--; for (; i < set_count; i++) { @@ -3004,6 +3009,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); if (acrtc->stream) { + dc_stream_retain(acrtc->stream); dm_state->set[dm_state->set_count].stream = acrtc->stream; crtc_set[dm_state->set_count] = crtc; ++dm_state->set_count; -- cgit v1.2.3 From 89a1fc5924cc7c315117be79878f2a6d2d69b576 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 29 Jun 2017 10:41:17 -0400 Subject: drm/amd/display: Update atomic state hooks. Reimplement atomic_state_alloc and atomic_state_clear to release validate_ctx. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 25 +++++++++------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 2 +- 2 files changed, 11 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ba20a8cce7df..2cfc1846f4c4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -648,33 +648,29 @@ dm_atomic_state_alloc(struct drm_device *dev) return &state->base; } -void dm_atomic_state_clear(struct drm_atomic_state *s) -{ - struct dm_atomic_state *state = to_dm_atomic_state(s); - drm_atomic_state_default_clear(&state->base); -} - -static void dm_atomic_state_free(struct drm_atomic_state *state) +void dm_atomic_state_clear(struct drm_atomic_state *state) { struct dm_atomic_state *dm_state = to_dm_atomic_state(state); int i, j; - drm_atomic_state_default_release(state); - for (i = 0; i < dm_state->set_count; i++) { for (j = 0; j < dm_state->set[i].surface_count; j++) { dc_surface_release(dm_state->set[i].surfaces[j]); + dm_state->set[i].surfaces[j] = NULL; } - } - for (i = 0; i < dm_state->set_count; i++) dc_stream_release(dm_state->set[i].stream); + dm_state->set[i].stream = NULL; + } + dm_state->set_count = 0; - kfree(dm_state); -} - + dc_resource_validate_ctx_destruct(dm_state->context); + dm_free(dm_state->context); + dm_state->context = NULL; + drm_atomic_state_default_clear(state); +} static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, @@ -683,7 +679,6 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .atomic_commit = drm_atomic_helper_commit, .atomic_state_alloc = dm_atomic_state_alloc, .atomic_state_clear = dm_atomic_state_clear, - .atomic_state_free = dm_atomic_state_free, }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index ab07a9f0934d..10e4823968c8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2695,6 +2695,7 @@ void amdgpu_dm_atomic_commit_tail( /* DC is optimized not to do anything if 'streams' didn't change. */ WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); @@ -3069,7 +3070,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, __func__, acrtc->base.base.id); break; } - new_stream->priv = acrtc; new_streams[new_stream_count] = new_stream; dm_state->set_count = update_in_val_sets_stream( -- cgit v1.2.3 From da5c47f682abe61eb81291cb663b77828fda0688 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 29 Jun 2017 12:03:59 -0400 Subject: drm/amd/display: Remove acrtc->stream Remove acrtc->stream and move it into dm_crtc_state. This allows to get rid of dm_atomic_state->dm_set. Also reuse streams created in atomic_check during commit. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 403 +++++++++++---------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 9 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 - 4 files changed, 226 insertions(+), 221 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2cfc1846f4c4..4b844e5c5dcd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -100,13 +100,16 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) return 0; else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state( + acrtc->base.state); - if (NULL == acrtc->stream) { + + if (acrtc_state->stream == NULL) { DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } - return dc_stream_get_vblank_counter(acrtc->stream); + return dc_stream_get_vblank_counter(acrtc_state->stream); } } @@ -119,8 +122,10 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, return -EINVAL; else { struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc]; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state( + acrtc->base.state); - if (NULL == acrtc->stream) { + if (acrtc_state->stream == NULL) { DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); return 0; } @@ -129,7 +134,7 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, * TODO rework base driver to use values directly. * for now parse it back into reg-format */ - dc_stream_get_scanoutpos(acrtc->stream, + dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start, &v_blank_end, &h_position, @@ -652,22 +657,12 @@ dm_atomic_state_alloc(struct drm_device *dev) void dm_atomic_state_clear(struct drm_atomic_state *state) { struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - int i, j; - - for (i = 0; i < dm_state->set_count; i++) { - for (j = 0; j < dm_state->set[i].surface_count; j++) { - dc_surface_release(dm_state->set[i].surfaces[j]); - dm_state->set[i].surfaces[j] = NULL; - } - dc_stream_release(dm_state->set[i].stream); - dm_state->set[i].stream = NULL; + if (dm_state->context) { + dc_resource_validate_ctx_destruct(dm_state->context); + dm_free(dm_state->context); + dm_state->context = NULL; } - dm_state->set_count = 0; - - dc_resource_validate_ctx_destruct(dm_state->context); - dm_free(dm_state->context); - dm_state->context = NULL; drm_atomic_state_default_clear(state); } @@ -676,7 +671,7 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, - .atomic_commit = drm_atomic_helper_commit, + .atomic_commit = amdgpu_dm_atomic_commit, .atomic_state_alloc = dm_atomic_state_alloc, .atomic_state_clear = dm_atomic_state_clear, }; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 10e4823968c8..c222cdb59ac1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -86,6 +86,7 @@ static void dm_set_cursor( struct drm_crtc *crtc = &amdgpu_crtc->base; int x, y; int xorigin = 0, yorigin = 0; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); amdgpu_crtc->cursor_width = width; amdgpu_crtc->cursor_height = height; @@ -124,13 +125,13 @@ static void dm_set_cursor( position.y_hotspot = yorigin; if (!dc_stream_set_cursor_attributes( - amdgpu_crtc->stream, + acrtc_state->stream, &attributes)) { DRM_ERROR("DC failed to set cursor attributes\n"); } if (!dc_stream_set_cursor_position( - amdgpu_crtc->stream, + acrtc_state->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); } @@ -143,6 +144,7 @@ static int dm_crtc_cursor_set( uint32_t height) { struct dc_cursor_position position; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); int ret; @@ -162,10 +164,10 @@ static int dm_crtc_cursor_set( position.x = 0; position.y = 0; - if (amdgpu_crtc->stream) { + if (acrtc_state->stream) { /*set cursor visible false*/ dc_stream_set_cursor_position( - amdgpu_crtc->stream, + acrtc_state->stream, &position); } goto release; @@ -196,6 +198,7 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); int xorigin = 0, yorigin = 0; struct dc_cursor_position position; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); amdgpu_crtc->cursor_x = x; amdgpu_crtc->cursor_y = y; @@ -233,9 +236,9 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, position.x_hotspot = xorigin; position.y_hotspot = yorigin; - if (amdgpu_crtc->stream) { + if (acrtc_state->stream) { if (!dc_stream_set_cursor_position( - amdgpu_crtc->stream, + acrtc_state->stream, &position)) { DRM_ERROR("DC failed to set cursor position\n"); return -EINVAL; @@ -611,7 +614,8 @@ static void add_surface(struct dc *dc, { struct dc_surface *dc_surface; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - const struct dc_stream *dc_stream = acrtc->stream; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + const struct dc_stream *dc_stream = acrtc_state->stream; unsigned long flags; spin_lock_irqsave(&crtc->dev->event_lock, flags); @@ -965,11 +969,10 @@ static void dm_crtc_destroy_state(struct drm_crtc *crtc, { struct dm_crtc_state *cur = to_dm_crtc_state(state); - if (cur->dc_stream) { - /* TODO Destroy dc_stream objects are stream object is flattened */ - dm_free(cur->dc_stream); - } else - WARN_ON(1); + /* TODO Destroy dc_stream objects are stream object is flattened */ + if (cur->stream) + dc_stream_release(cur->stream); + __drm_atomic_helper_crtc_destroy_state(state); @@ -988,40 +991,29 @@ static void dm_crtc_reset_state(struct drm_crtc *crtc) if (WARN_ON(!state)) return; - crtc->state = &state->base; crtc->state->crtc = crtc; - state->dc_stream = dm_alloc(sizeof(*state->dc_stream)); - WARN_ON(!state->dc_stream); } static struct drm_crtc_state * dm_crtc_duplicate_state(struct drm_crtc *crtc) { struct dm_crtc_state *state, *cur; - struct dc_stream *dc_stream; - - if (WARN_ON(!crtc->state)) - return NULL; cur = to_dm_crtc_state(crtc->state); - if (WARN_ON(!cur->dc_stream)) - return NULL; - dc_stream = dm_alloc(sizeof(*dc_stream)); - if (WARN_ON(!dc_stream)) + if (WARN_ON(!crtc->state)) return NULL; state = dm_alloc(sizeof(*state)); - if (WARN_ON(!state)) { - dm_free(dc_stream); - return NULL; - } __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); - state->dc_stream = dc_stream; + if (cur->stream) { + state->stream = cur->stream; + dc_stream_retain(state->stream); + } /* TODO Duplicate dc_stream after objects are stream object is flattened */ @@ -2238,21 +2230,15 @@ static bool is_scaling_state_different( return false; } -static void remove_stream(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc) +static void remove_stream( + struct amdgpu_device *adev, + struct amdgpu_crtc *acrtc, + const struct dc_stream *stream) { - /* - * we evade vblanks and pflips on crtc that - * should be changed - */ - manage_dm_interrupts(adev, acrtc, false); - /* this is the update mode case */ if (adev->dm.freesync_module) - mod_freesync_remove_stream(adev->dm.freesync_module, - acrtc->stream); + mod_freesync_remove_stream(adev->dm.freesync_module, stream); - dc_stream_release(acrtc->stream); - acrtc->stream = NULL; acrtc->otg_inst = -1; acrtc->enabled = false; } @@ -2324,6 +2310,8 @@ static void amdgpu_dm_do_flip( bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; struct dc_flip_addrs addr = { {0} }; struct dc_surface_update surface_updates[1] = { {0} }; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + /* Prepare wait for target vblank early - before the fence-waits */ target_vblank = target - drm_crtc_vblank_count(crtc) + @@ -2366,7 +2354,7 @@ static void amdgpu_dm_do_flip( crtc->primary->fb = fb; WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); - WARN_ON(!acrtc->stream); + WARN_ON(!acrtc_state->stream); addr.address.grph.addr.low_part = lower_32_bits(afb->address); addr.address.grph.addr.high_part = upper_32_bits(afb->address); @@ -2376,11 +2364,11 @@ static void amdgpu_dm_do_flip( if (acrtc->base.state->event) prepare_flip_isr(acrtc); - surface_updates->surface = dc_stream_get_status(acrtc->stream)->surfaces[0]; + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; surface_updates->flip_addr = &addr; - dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc->stream, NULL); + dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, @@ -2403,6 +2391,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, const struct dc_stream *dc_stream_attach; const struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; /* update planes when needed */ @@ -2457,7 +2446,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, dm_error("%s: Failed to add surface!\n", __func__); continue; } - dc_stream_attach = acrtc_attach->stream; + dc_stream_attach = acrtc_state->stream; planes_count++; } else if (crtc->state->planes_changed) { @@ -2511,6 +2500,37 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, } } + +int amdgpu_dm_atomic_commit( + struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock) +{ + struct drm_crtc *crtc; + struct drm_crtc_state *new_state; + struct amdgpu_device *adev = dev->dev_private; + int i; + + /* + * We evade vblanks and pflips on crtc that + * should be changed. We do it here to flush & disable + * interrupts before drm_swap_state is called in drm_atomic_helper_commit + * it will update crtc->dm_crtc_state->stream pointer which is used in + * the ISRs. + */ + for_each_crtc_in_state(state, crtc, new_state, i) { + struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream) + manage_dm_interrupts(adev, acrtc, false); + } + + return drm_atomic_helper_commit(dev, state, nonblock); + + /*TODO Handle EINTR, reenable IRQ*/ +} + void amdgpu_dm_atomic_commit_tail( struct drm_atomic_state *state) { @@ -2528,6 +2548,7 @@ void amdgpu_dm_atomic_commit_tail( bool wait_for_vblank = true; struct drm_connector *connector; struct drm_connector_state *old_conn_state; + struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -2535,16 +2556,10 @@ void amdgpu_dm_atomic_commit_tail( /* update changed items */ for_each_crtc_in_state(state, crtc, old_crtc_state, i) { - struct amdgpu_crtc *acrtc; - struct amdgpu_connector *aconnector = NULL; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_crtc_state *new_state = crtc->state; - - acrtc = to_amdgpu_crtc(crtc); - aconnector = - amdgpu_dm_find_first_crct_matching_connector( - state, - crtc, - false); + new_acrtc_state = to_dm_crtc_state(new_state); + old_acrtc_state = to_dm_crtc_state(old_crtc_state); DRM_DEBUG_KMS( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " @@ -2563,109 +2578,60 @@ void amdgpu_dm_atomic_commit_tail( */ if (modeset_required(new_state)) { - struct dm_connector_state *dm_conn_state = NULL; - new_stream = NULL; - - if (aconnector) - dm_conn_state = to_dm_connector_state(aconnector->base.state); - - new_stream = create_stream_for_sink( - aconnector, - &crtc->state->mode, - dm_conn_state); DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); - if (!new_stream) { + if (!new_acrtc_state->stream) { /* - * this could happen because of issues with - * userspace notifications delivery. - * In this case userspace tries to set mode on - * display which is disconnect in fact. - * dc_sink in NULL in this case on aconnector. - * We expect reset mode will come soon. - * - * This can also happen when unplug is done - * during resume sequence ended - * - * In this case, we want to pretend we still - * have a sink to keep the pipe running so that - * hw state is consistent with the sw state - */ + * this could happen because of issues with + * userspace notifications delivery. + * In this case userspace tries to set mode on + * display which is disconnect in fact. + * dc_sink in NULL in this case on aconnector. + * We expect reset mode will come soon. + * + * This can also happen when unplug is done + * during resume sequence ended + * + * In this case, we want to pretend we still + * have a sink to keep the pipe running so that + * hw state is consistent with the sw state + */ DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); - break; + continue; } - if (acrtc->stream) - remove_stream(adev, acrtc); - /* TODO clean this stupid hack */ - for (j = 0; j < dm_state->set_count; j++) - if (dm_state->set[j].stream->priv == acrtc) { - ASSERT(acrtc->stream == NULL); - new_stream = dm_state->set[j].stream; - break; - } + if (old_acrtc_state->stream) + remove_stream(adev, acrtc, old_acrtc_state->stream); + /* * this loop saves set mode crtcs * we needed to enable vblanks once all * resources acquired in dc after dc_commit_streams */ + + /*TODO move all this into dm_crtc_state, get rid of + * new_crtcs array and use old and new atomic states + * instead + */ new_crtcs[new_crtcs_count] = acrtc; new_crtcs_count++; - acrtc->stream = new_stream; acrtc->enabled = true; acrtc->hw_mode = crtc->state->mode; crtc->hwmode = crtc->state->mode; } else if (modereset_required(new_state)) { - DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); + /* i.e. reset mode */ - if (acrtc->stream) - remove_stream(adev, acrtc); + if (old_acrtc_state->stream) + remove_stream(adev, acrtc, old_acrtc_state->stream); } } /* for_each_crtc_in_state() */ - /* Handle scaling and undersacn changes*/ - for_each_connector_in_state(state, connector, old_conn_state, i) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - struct dm_connector_state *con_new_state = - to_dm_connector_state(aconnector->base.state); - struct dm_connector_state *con_old_state = - to_dm_connector_state(old_conn_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); - const struct dc_stream_status *status = NULL; - - /* Skip any modesets/resets */ - if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) - continue; - - /* Skip any thing not scale or underscan chnages */ - if (!is_scaling_state_different(con_new_state, con_old_state)) - continue; - - update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream *)acrtc->stream); - - status = dc_stream_get_status(acrtc->stream); - WARN_ON(!status); - WARN_ON(!status->surface_count); - - if (!acrtc->stream) - continue; - - /*TODO How it works with MPO ?*/ - if (!dc_commit_surfaces_to_stream( - dm->dc, - (const struct dc_surface **)status->surfaces, - status->surface_count, - acrtc->stream)) - dm_error("%s: Failed to update stream scaling!\n", __func__); - } - /* * Add streams after required streams from new and replaced streams * are removed from freesync module @@ -2673,7 +2639,9 @@ void amdgpu_dm_atomic_commit_tail( if (adev->dm.freesync_module) { for (i = 0; i < new_crtcs_count; i++) { struct amdgpu_connector *aconnector = NULL; - new_stream = new_crtcs[i]->stream; + new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); + + new_stream = new_acrtc_state->stream; aconnector = amdgpu_dm_find_first_crct_matching_connector( state, @@ -2698,35 +2666,77 @@ void amdgpu_dm_atomic_commit_tail( list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + new_acrtc_state = to_dm_crtc_state(crtc->state); - if (acrtc->stream != NULL) { - const struct dc_stream_status *status = dc_stream_get_status(acrtc->stream); + if (new_acrtc_state->stream != NULL) { + const struct dc_stream_status *status = + dc_stream_get_status(new_acrtc_state->stream); if (!status) - DC_ERR("got no status for stream %p on acrtc%p\n", acrtc->stream, acrtc); + DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc); else acrtc->otg_inst = status->primary_otg_inst; } } + /* Handle scaling and undersacn changes*/ + for_each_connector_in_state(state, connector, old_conn_state, i) { + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct dm_connector_state *con_new_state = + to_dm_connector_state(aconnector->base.state); + struct dm_connector_state *con_old_state = + to_dm_connector_state(old_conn_state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); + const struct dc_stream_status *status = NULL; + + /* Skip any modesets/resets */ + if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) + continue; + + /* Skip any thing not scale or underscan changes */ + if (!is_scaling_state_different(con_new_state, con_old_state)) + continue; + + new_acrtc_state = to_dm_crtc_state(acrtc->base.state); + + update_stream_scaling_settings(&con_new_state->base.crtc->mode, + con_new_state, (struct dc_stream *)new_acrtc_state->stream); + + status = dc_stream_get_status(new_acrtc_state->stream); + WARN_ON(!status); + WARN_ON(!status->surface_count); + + if (!new_acrtc_state->stream) + continue; + + /*TODO How it works with MPO ?*/ + if (!dc_commit_surfaces_to_stream( + dm->dc, + (const struct dc_surface **)status->surfaces, + status->surface_count, + new_acrtc_state->stream)) + dm_error("%s: Failed to update stream scaling!\n", __func__); + } + for (i = 0; i < new_crtcs_count; i++) { /* * loop to enable interrupts on newly arrived crtc */ struct amdgpu_crtc *acrtc = new_crtcs[i]; + new_acrtc_state = to_dm_crtc_state(acrtc->base.state); if (adev->dm.freesync_module) mod_freesync_notify_mode_change( - adev->dm.freesync_module, &acrtc->stream, 1); + adev->dm.freesync_module, &new_acrtc_state->stream, 1); manage_dm_interrupts(adev, acrtc, true); } /* update planes when needed per crtc*/ for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(pcrtc); + new_acrtc_state = to_dm_crtc_state(pcrtc->state); - if (acrtc->stream) + if (new_acrtc_state->stream) amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); } @@ -2822,13 +2832,15 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector { struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); struct amdgpu_crtc *disconnected_acrtc; + struct dm_crtc_state *acrtc_state; if (!aconnector->dc_sink || !connector->state || !connector->encoder) return; disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); + acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); - if (!disconnected_acrtc || !disconnected_acrtc->stream) + if (!disconnected_acrtc || !acrtc_state->stream) return; /* @@ -2836,7 +2848,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector * we deduce we are in a state where we can not rely on usermode call * to turn on the display, so we do it here */ - if (disconnected_acrtc->stream->sink != aconnector->dc_sink) + if (acrtc_state->stream->sink != aconnector->dc_sink) dm_force_atomic_commit(&aconnector->base); } @@ -2880,17 +2892,11 @@ static uint32_t update_in_val_sets_stream( } val_sets[i].stream = new_stream; - dc_stream_retain(new_stream); crtcs[i] = crtc; - if (i == set_count) { + if (i == set_count) /* nothing found. add new one to the end */ return set_count + 1; - } else { - /* update. relase old stream */ - dc_stream_release(old_stream); - - } return set_count; } @@ -2911,7 +2917,6 @@ static uint32_t remove_from_val_sets( return set_count; } - dc_stream_release(stream); set_count--; for (; i < set_count; i++) { @@ -2981,14 +2986,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_plane_state *plane_state; int i, j; int ret; - int new_stream_count; - struct dc_stream *new_streams[MAX_STREAMS] = { 0 }; struct drm_crtc *crtc_set[MAX_STREAMS] = { 0 }; struct amdgpu_device *adev = dev->dev_private; struct dc *dc = adev->dm.dc; bool need_to_validate = false; struct drm_connector *connector; struct drm_connector_state *conn_state; + int set_count; + struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; + struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + /* * This bool will be set for true for any modeset/reset * or surface update which implies non fast surfae update. @@ -3008,17 +3015,16 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dm_state = to_dm_atomic_state(state); /* copy existing configuration */ - new_stream_count = 0; - dm_state->set_count = 0; + set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + old_acrtc_state = to_dm_crtc_state(crtc->state); - if (acrtc->stream) { - dc_stream_retain(acrtc->stream); - dm_state->set[dm_state->set_count].stream = acrtc->stream; - crtc_set[dm_state->set_count] = crtc; - ++dm_state->set_count; + if (old_acrtc_state->stream) { + dc_stream_retain(old_acrtc_state->stream); + set[set_count].stream = old_acrtc_state->stream; + crtc_set[set_count] = crtc; + ++set_count; } } @@ -3026,7 +3032,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; - + old_acrtc_state = to_dm_crtc_state(crtc->state); + new_acrtc_state = to_dm_crtc_state(crtc_state); acrtc = to_amdgpu_crtc(crtc); aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); @@ -3057,7 +3064,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, } new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state); - new_stream->priv = acrtc; /* * we can have no stream on ACTION_SET if a display @@ -3071,27 +3077,33 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, break; } - new_streams[new_stream_count] = new_stream; - dm_state->set_count = update_in_val_sets_stream( - dm_state->set, + if (new_acrtc_state->stream) + dc_stream_release(new_acrtc_state->stream); + new_acrtc_state->stream = new_stream; + + set_count = update_in_val_sets_stream( + set, crtc_set, - dm_state->set_count, - acrtc->stream, - new_stream, + set_count, + old_acrtc_state->stream, + new_acrtc_state->stream, crtc); - new_stream_count++; need_to_validate = true; aquire_global_lock = true; } else if (modereset_required(crtc_state)) { /* i.e. reset mode */ - if (acrtc->stream) { - dm_state->set_count = remove_from_val_sets( - dm_state->set, - dm_state->set_count, - acrtc->stream); + if (new_acrtc_state->stream) { + set_count = remove_from_val_sets( + set, + set_count, + new_acrtc_state->stream); + + dc_stream_release(new_acrtc_state->stream); + new_acrtc_state->stream = NULL; + aquire_global_lock = true; } } @@ -3112,6 +3124,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, } /* Check scaling and undersacn changes*/ + /*TODO Removed scaling changes validation due to inability to commit + * new stream into context w\o causing full reset. Need to + * decide how to handle. + */ for_each_connector_in_state(state, connector, conn_state, i) { struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); struct dm_connector_state *con_old_state = @@ -3119,7 +3135,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dm_connector_state *con_new_state = to_dm_connector_state(conn_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); - struct dc_stream *new_stream; /* Skip any modesets/resets */ if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) @@ -3129,32 +3144,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (!is_scaling_state_different(con_new_state, con_old_state)) continue; - new_stream = create_stream_for_sink( - aconnector, - &acrtc->base.state->mode, - con_new_state); - - if (!new_stream) { - DRM_ERROR("%s: Failed to create new stream for crtc %d\n", - __func__, acrtc->base.base.id); - continue; - } - - new_streams[new_stream_count] = new_stream; - dm_state->set_count = update_in_val_sets_stream( - dm_state->set, - crtc_set, - dm_state->set_count, - acrtc->stream, - new_stream, - &acrtc->base); - - new_stream_count++; need_to_validate = true; aquire_global_lock = true; } - for (i = 0; i < dm_state->set_count; i++) { + for (i = 0; i < set_count; i++) { for_each_plane_in_state(state, plane, plane_state, j) { struct drm_crtc *crtc = plane_state->crtc; struct drm_framebuffer *fb = plane_state->fb; @@ -3210,9 +3204,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, plane_state, false); - add_val_sets_surface(dm_state->set, - dm_state->set_count, - dm_state->set[i].stream, + add_val_sets_surface(set, + set_count, + set[i].stream, surface); need_to_validate = true; @@ -3221,9 +3215,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, } } - dm_state->context = dc_get_validate_context(dc, dm_state->set, dm_state->set_count); + dm_state->context = dc_get_validate_context(dc, set, set_count); - if (need_to_validate == false || dm_state->set_count == 0 || dm_state->context) { + if (need_to_validate == false || set_count == 0 || dm_state->context) { ret = 0; /* * For full updates case when @@ -3239,6 +3233,21 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, } + /* TODO until surfaces are moved into dm_plane_state release them + * here + */ + for (i = 0; i < set_count; i++) + for (j = 0; j < set[i].surface_count; j++) + dc_surface_release(set[i].surfaces[j]); + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + old_acrtc_state = to_dm_crtc_state(crtc->state); + + if (old_acrtc_state->stream) + dc_stream_release(old_acrtc_state->stream); + } + + if (ret != 0) { if (ret == -EDEADLK) DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index 1e444cb5123d..36cb1c840810 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -45,7 +45,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - struct dc_stream *dc_stream; + const struct dc_stream *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) @@ -53,8 +53,6 @@ struct dm_crtc_state { struct dm_atomic_state { struct drm_atomic_state base; - struct dc_validation_set set[MAX_STREAMS]; - int set_count; struct validate_context *context; }; @@ -83,6 +81,11 @@ void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); int amdgpu_dm_connector_get_modes(struct drm_connector *connector); +int amdgpu_dm_atomic_commit( + struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock); + void amdgpu_dm_atomic_commit_tail( struct drm_atomic_state *state); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5d65416304b0..42c1aa8d68af 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -481,8 +481,6 @@ struct dc_stream { /* TODO: ABM info (DMCU) */ /* TODO: PSR info */ /* TODO: CEA VIC */ - - void *priv; }; struct dc_stream_update { -- cgit v1.2.3 From adef2ce36e6ad76888159ea6225da54019d0ff0e Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 10 Jul 2017 16:24:42 -0400 Subject: drm/amd/display: Leave all validate_ctx life cycle management to DC. Follow DC fix. Signed-off-by: Andrey Grodzovsky Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 --------------- 1 file changed, 15 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4b844e5c5dcd..63d23c6e7574 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -653,27 +653,12 @@ dm_atomic_state_alloc(struct drm_device *dev) return &state->base; } - -void dm_atomic_state_clear(struct drm_atomic_state *state) -{ - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - - if (dm_state->context) { - dc_resource_validate_ctx_destruct(dm_state->context); - dm_free(dm_state->context); - dm_state->context = NULL; - } - - drm_atomic_state_default_clear(state); -} - static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = amdgpu_dm_atomic_commit, .atomic_state_alloc = dm_atomic_state_alloc, - .atomic_state_clear = dm_atomic_state_clear, }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { -- cgit v1.2.3 From 0a323b84fab27fe51d35a4c55c73484c45c50f14 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Tue, 11 Jul 2017 14:42:57 -0400 Subject: drm/amd/display: Release dm_state->context when state is cleared. Handling a use case of TEST_ONLY request from DRM where commit is not goiing to be called. We need to release the allocated dc_validate_context in this case. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++++++++++++++++++++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 1 + 2 files changed, 24 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 63d23c6e7574..e16e87173db3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -653,12 +653,35 @@ dm_atomic_state_alloc(struct drm_device *dev) return &state->base; } +static void +dm_atomic_state_clear(struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + + if (dm_state->context) { + dc_release_validate_context(dm_state->context); + dm_state->context = NULL; + } + + drm_atomic_state_default_clear(state); +} + +static void +dm_atomic_state_alloc_free(struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + drm_atomic_state_default_release(state); + kfree(dm_state); +} + static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_user_framebuffer_create, .output_poll_changed = amdgpu_output_poll_changed, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = amdgpu_dm_atomic_commit, .atomic_state_alloc = dm_atomic_state_alloc, + .atomic_state_clear = dm_atomic_state_clear, + .atomic_state_free = dm_atomic_state_alloc_free }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 248b397a6a7d..af4de578dadb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -3144,6 +3144,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail_planes; + WARN_ON(dm_state->context); dm_state->context = dc_get_validate_context(dc, set, set_count); if (!dm_state->context) { ret = -EINVAL; -- cgit v1.2.3 From 0a214e2fb6b0a56519b6d5efab4b21475c233ee0 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Thu, 13 Jul 2017 10:56:48 -0400 Subject: drm/amd/display: Release cached atomic state in S3. Fixes memory leak. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e16e87173db3..a41d271f21a3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -508,6 +508,7 @@ static int dm_suspend(void *handle) amdgpu_dm_irq_suspend(adev); + WARN_ON(adev->dm.cached_state); adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); dc_set_power_state( @@ -607,6 +608,9 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); + drm_atomic_state_put(adev->dm.cached_state); + adev->dm.cached_state = NULL; + amdgpu_dm_irq_resume_late(adev); return ret; -- cgit v1.2.3 From 8ee65d7c93cb082d6c1ca584b7565c1cc08e7861 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Wed, 19 Jul 2017 13:18:26 -0400 Subject: drm/amd/display: Return hpd_irq_dpcd from hpd_rx handler Signed-off-by: Wenjing Liu Reviewed-by: Wenjing Liu Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 5 ++++- drivers/gpu/drm/amd/display/dc/dc.h | 3 ++- 3 files changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a41d271f21a3..26fbadba97dd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -914,7 +914,7 @@ static void handle_hpd_rx_irq(void *param) if (aconnector->dc_link->type != dc_connection_mst_branch) mutex_lock(&aconnector->hpd_lock); - if (dc_link_handle_hpd_rx_irq(aconnector->dc_link) && + if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) && !is_mst_root_connector) { /* Downstream Port status changed. */ if (dc_link_detect(aconnector->dc_link, false)) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index dd3f57fce834..445cd226d36d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1924,7 +1924,7 @@ static void handle_automated_test(struct core_link *link) sizeof(test_response)); } -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link) +bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, union hpd_irq_data *out_hpd_irq_dpcd_data) { struct core_link *link = DC_LINK_TO_LINK(dc_link); union hpd_irq_data hpd_irq_dpcd_data = {{{{0}}}}; @@ -1939,12 +1939,15 @@ bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link) "%s: Got short pulse HPD on link %d\n", __func__, link->public.link_index); + /* All the "handle_hpd_irq_xxx()" methods * should be called only after * dal_dpsst_ls_read_hpd_irq_data * Order of calls is important too */ result = read_hpd_rx_irq_data(link, &hpd_irq_dpcd_data); + if (out_hpd_irq_dpcd_data) + *out_hpd_irq_dpcd_data = hpd_irq_dpcd_data; if (result != DC_OK) { dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 07f064f53d85..7ecbff792e66 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -755,7 +755,8 @@ bool dc_link_detect(const struct dc_link *dc_link, bool boot); * detection. * false - no change in Downstream port status. No further action required * from DM. */ -bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link); +bool dc_link_handle_hpd_rx_irq(const struct dc_link *dc_link, + union hpd_irq_data *hpd_irq_dpcd_data); struct dc_sink_init_data; -- cgit v1.2.3 From b73a22d3257f9ec237c46be12d74b58d5a925d8c Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 24 Jul 2017 14:04:27 -0400 Subject: drm/amd/display: Roll core_sink into dc_sink Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 60 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 30 +++++------ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 19 ++++--- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 21 +------- 11 files changed, 72 insertions(+), 91 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index c558f700df35..8d939e3b3f15 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -562,9 +562,9 @@ struct amdgpu_connector { int num_modes; /* The 'old' sink - before an HPD. * The 'current' sink is in dc_link->sink. */ - const struct dc_sink *dc_sink; + struct dc_sink *dc_sink; struct dc_link *dc_link; - const struct dc_sink *dc_em_sink; + struct dc_sink *dc_em_sink; const struct dc_stream *stream; void *con_priv; bool dac_load_detect; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 26fbadba97dd..696a4112c8d9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -697,7 +697,7 @@ void amdgpu_dm_update_connector_after_detect( { struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; - const struct dc_sink *sink; + struct dc_sink *sink; /* MST handled by drm_mst framework */ if (aconnector->mst_mgr.mst_state == true) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 4885403f5cec..13708bcb83cd 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -1266,7 +1266,7 @@ int amdgpu_dm_connector_mode_valid( struct drm_display_mode *mode) { int result = MODE_ERROR; - const struct dc_sink *dc_sink; + struct dc_sink *dc_sink; struct amdgpu_device *adev = connector->dev->dev_private; struct dc_validation_set val_set = { 0 }; /* TODO: Unhardcode stream count */ @@ -1535,7 +1535,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, struct drm_display_mode *mode, struct dc_validation_set *val_set) { int result = MODE_ERROR; - const struct dc_sink *dc_sink = + struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ struct dc_stream *stream; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 73740e2a5819..30374ffaae0b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -939,7 +939,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c program_timing_sync(core_dc, context); for (i = 0; i < context->stream_count; i++) { - const struct core_sink *sink = context->streams[i]->sink; + const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { const struct dc_surface *surface = @@ -1984,7 +1984,7 @@ void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink) } } -void dc_link_remove_remote_sink(struct dc_link *link, const struct dc_sink *sink) +void dc_link_remove_remote_sink(struct dc_link *link, struct dc_sink *sink) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 428dbff8505b..e7062069d9a1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -541,8 +541,7 @@ bool dc_link_detect(struct dc_link *link, bool boot) struct audio_support *aud_support = &link->dc->res_pool->audio_support; enum dc_edid_status edid_status; struct dc_context *dc_ctx = link->ctx; - struct dc_sink *dc_sink; - struct core_sink *sink = NULL; + struct dc_sink *sink; enum dc_connection_type new_connection_type = dc_connection_none; if (link->connector_signal == SIGNAL_TYPE_VIRTUAL) @@ -637,22 +636,21 @@ bool dc_link_detect(struct dc_link *link, bool boot) sink_init_data.link = link; sink_init_data.sink_signal = sink_caps.signal; - dc_sink = dc_sink_create(&sink_init_data); - if (!dc_sink) { + sink = dc_sink_create(&sink_init_data); + if (!sink) { DC_ERROR("Failed to create sink!\n"); return false; } - dc_sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; - dc_sink->converter_disable_audio = converter_disable_audio; + sink->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock; + sink->converter_disable_audio = converter_disable_audio; - sink = DC_SINK_TO_CORE(dc_sink); - link->local_sink = &sink->public; + link->local_sink = sink; edid_status = dm_helpers_read_local_edid( link->ctx, link, - &sink->public); + sink); switch (edid_status) { case EDID_BAD_CHECKSUM: @@ -669,16 +667,16 @@ bool dc_link_detect(struct dc_link *link, bool boot) } /* HDMI-DVI Dongle */ - if (dc_sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && - !dc_sink->edid_caps.edid_hdmi) - dc_sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; + if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A && + !sink->edid_caps.edid_hdmi) + sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK; /* Connectivity log: detection */ - for (i = 0; i < sink->public.dc_edid.length / EDID_BLOCK_SIZE; i++) { + for (i = 0; i < sink->dc_edid.length / EDID_BLOCK_SIZE; i++) { CONN_DATA_DETECT(link, - &sink->public.dc_edid.raw_edid[i * EDID_BLOCK_SIZE], + &sink->dc_edid.raw_edid[i * EDID_BLOCK_SIZE], EDID_BLOCK_SIZE, - "%s: [Block %d] ", sink->public.edid_caps.display_name, i); + "%s: [Block %d] ", sink->edid_caps.display_name, i); } dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER, @@ -692,16 +690,16 @@ bool dc_link_detect(struct dc_link *link, bool boot) "speaker_flag = %d, " "audio_mode_count = %d\n", __func__, - sink->public.edid_caps.manufacturer_id, - sink->public.edid_caps.product_id, - sink->public.edid_caps.serial_number, - sink->public.edid_caps.manufacture_week, - sink->public.edid_caps.manufacture_year, - sink->public.edid_caps.display_name, - sink->public.edid_caps.speaker_flags, - sink->public.edid_caps.audio_mode_count); - - for (i = 0; i < sink->public.edid_caps.audio_mode_count; i++) { + sink->edid_caps.manufacturer_id, + sink->edid_caps.product_id, + sink->edid_caps.serial_number, + sink->edid_caps.manufacture_week, + sink->edid_caps.manufacture_year, + sink->edid_caps.display_name, + sink->edid_caps.speaker_flags, + sink->edid_caps.audio_mode_count); + + for (i = 0; i < sink->edid_caps.audio_mode_count; i++) { dm_logger_write(link->ctx->logger, LOG_DETECTION_EDID_PARSER, "%s: mode number = %d, " "format_code = %d, " @@ -710,10 +708,10 @@ bool dc_link_detect(struct dc_link *link, bool boot) "sample_size = %d\n", __func__, i, - sink->public.edid_caps.audio_modes[i].format_code, - sink->public.edid_caps.audio_modes[i].channel_count, - sink->public.edid_caps.audio_modes[i].sample_rate, - sink->public.edid_caps.audio_modes[i].sample_size); + sink->edid_caps.audio_modes[i].format_code, + sink->edid_caps.audio_modes[i].channel_count, + sink->edid_caps.audio_modes[i].sample_rate, + sink->edid_caps.audio_modes[i].sample_size); } } else { @@ -732,7 +730,7 @@ bool dc_link_detect(struct dc_link *link, bool boot) } LINK_INFO("link=%d, dc_sink_in=%p is now %s\n", - link->link_index, &sink->public, + link->link_index, sink, (sink_caps.signal == SIGNAL_TYPE_NONE ? "Disconnected":"Connected")); @@ -1347,7 +1345,7 @@ enum dc_status dc_link_validate_mode_timing( struct dc_link *link, const struct dc_crtc_timing *timing) { - uint32_t max_pix_clk = stream->sink->public.dongle_max_pix_clk; + uint32_t max_pix_clk = stream->sink->dongle_max_pix_clk; /* A hack to avoid failing any modes for EDID override feature on * topology change such as lower quality cable for DP or different dongle diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 7a3d090f8465..7cb572ff3cba 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1528,7 +1528,7 @@ enum dc_status resource_map_pool_resources( pipe_ctx->stream_enc); /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->public.converter_disable_audio && + if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && stream->public.audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index 1f7985ad5dba..a83f1243a9d1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -31,15 +31,15 @@ * Private functions ******************************************************************************/ -static void destruct(struct core_sink *sink) +static void destruct(struct dc_sink *sink) { - if (sink->public.dc_container_id) { - dm_free(sink->public.dc_container_id); - sink->public.dc_container_id = NULL; + if (sink->dc_container_id) { + dm_free(sink->dc_container_id); + sink->dc_container_id = NULL; } } -static bool construct(struct core_sink *sink, const struct dc_sink_init_data *init_params) +static bool construct(struct dc_sink *sink, const struct dc_sink_init_data *init_params) { struct dc_link *link = init_params->link; @@ -47,12 +47,12 @@ static bool construct(struct core_sink *sink, const struct dc_sink_init_data *in if (!link) return false; - sink->public.sink_signal = init_params->sink_signal; + sink->sink_signal = init_params->sink_signal; sink->link = link; sink->ctx = link->ctx; - sink->public.dongle_max_pix_clk = init_params->dongle_max_pix_clk; - sink->public.converter_disable_audio = init_params->converter_disable_audio; - sink->public.dc_container_id = NULL; + sink->dongle_max_pix_clk = init_params->dongle_max_pix_clk; + sink->converter_disable_audio = init_params->converter_disable_audio; + sink->dc_container_id = NULL; return true; } @@ -61,18 +61,14 @@ static bool construct(struct core_sink *sink, const struct dc_sink_init_data *in * Public functions ******************************************************************************/ -void dc_sink_retain(const struct dc_sink *dc_sink) +void dc_sink_retain(struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); - ASSERT(sink->ref_count > 0); ++sink->ref_count; } -void dc_sink_release(const struct dc_sink *dc_sink) +void dc_sink_release(struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); - ASSERT(sink->ref_count > 0); --sink->ref_count; @@ -84,7 +80,7 @@ void dc_sink_release(const struct dc_sink *dc_sink) struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) { - struct core_sink *sink = dm_alloc(sizeof(*sink)); + struct dc_sink *sink = dm_alloc(sizeof(*sink)); if (NULL == sink) goto alloc_fail; @@ -94,7 +90,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) ++sink->ref_count; - return &sink->public; + return sink; construct_fail: dm_free(sink); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a329709de360..5b356ddf5614 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -46,11 +46,11 @@ struct stream { ******************************************************************************/ static bool construct(struct core_stream *stream, - const struct dc_sink *dc_sink_data) + struct dc_sink *dc_sink_data) { uint32_t i = 0; - stream->sink = DC_SINK_TO_CORE(dc_sink_data); + stream->sink = dc_sink_data; stream->ctx = stream->sink->ctx; stream->public.sink = dc_sink_data; @@ -97,7 +97,7 @@ static bool construct(struct core_stream *stream, static void destruct(struct core_stream *stream) { - dc_sink_release(&stream->sink->public); + dc_sink_release(stream->sink); if (stream->public.out_transfer_func != NULL) { dc_transfer_func_release( stream->public.out_transfer_func); @@ -130,9 +130,8 @@ void dc_stream_release(const struct dc_stream *public) } struct dc_stream *dc_create_stream_for_sink( - const struct dc_sink *dc_sink) + struct dc_sink *sink) { - struct core_sink *sink = DC_SINK_TO_CORE(dc_sink); struct stream *stream; if (sink == NULL) @@ -143,7 +142,7 @@ struct dc_stream *dc_create_stream_for_sink( if (NULL == stream) goto alloc_fail; - if (false == construct(&stream->protected, dc_sink)) + if (false == construct(&stream->protected, sink)) goto construct_fail; stream->ref_count++; @@ -350,8 +349,8 @@ void dc_stream_log( dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", - core_stream->sink->public.edid_caps.display_name, - core_stream->sink->public.edid_caps.serial_number); + core_stream->sink->edid_caps.display_name, + core_stream->sink->edid_caps.serial_number); dm_logger_write(dm_logger, log_type, "\tlink: %d\n", diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e15e8fb1eefe..77bd54659a8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -629,7 +629,7 @@ bool dc_enable_stereo( /** * Create a new default stream for the requested sink */ -struct dc_stream *dc_create_stream_for_sink(const struct dc_sink *dc_sink); +struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); void dc_stream_retain(const struct dc_stream *dc_stream); void dc_stream_release(const struct dc_stream *dc_stream); @@ -712,9 +712,9 @@ struct link_mst_stream_allocation_table { * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. */ struct dc_link { - const struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; + struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; unsigned int sink_count; - const struct dc_sink *local_sink; + struct dc_sink *local_sink; unsigned int link_index; enum dc_connection_type type; enum signal_type connector_signal; @@ -825,7 +825,7 @@ struct dc_sink *dc_link_add_remote_sink( void dc_link_remove_remote_sink( struct dc_link *link, - const struct dc_sink *sink); + struct dc_sink *sink); /* Used by diagnostics for virtual link at the moment */ void dc_link_set_sink(struct dc_link *link, struct dc_sink *sink); @@ -879,10 +879,17 @@ struct dc_sink { void *priv; struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; bool converter_disable_audio; + + /* private to DC core */ + struct dc_link *link; + struct dc_context *ctx; + + /* private to dc_sink.c */ + int ref_count; }; -void dc_sink_retain(const struct dc_sink *sink); -void dc_sink_release(const struct dc_sink *sink); +void dc_sink_retain(struct dc_sink *sink); +void dc_sink_release(struct dc_sink *sink); const struct audio **dc_get_audios(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index fe8084e290a3..58701fdb7c94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -657,7 +657,7 @@ static enum dc_status bios_parser_crtc_source_select( * encoder block * note: video bios clears all FMT setting here. */ struct bp_crtc_source_select crtc_source_select = {0}; - const struct core_sink *sink = pipe_ctx->stream->sink; + const struct dc_sink *sink = pipe_ctx->stream->sink; crtc_source_select.engine_id = pipe_ctx->stream_enc->id; crtc_source_select.controller_id = pipe_ctx->pipe_idx + 1; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index eed31a827a90..1d733c837854 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -68,7 +68,7 @@ struct core_stream { /* field internal to DC */ struct dc_context *ctx; - const struct core_sink *sink; + struct dc_sink *sink; /* used by DCP and FMT */ struct bit_depth_reduction_params bit_depth_params; @@ -80,25 +80,6 @@ struct core_stream { struct dc_stream_status status; }; -/************ core_sink *****************/ - -#define DC_SINK_TO_CORE(dc_sink) \ - container_of(dc_sink, struct core_sink, public) - -struct core_sink { - /** The public, read-only (for DM) area of sink. **/ - struct dc_sink public; - /** End-of-public area. **/ - - /** The 'protected' area - read/write access, for use only inside DC **/ - /* not used for now */ - struct dc_link *link; - struct dc_context *ctx; - - /* private to dc_sink.c */ - int ref_count; -}; - /************ link *****************/ struct link_init_data { const struct core_dc *dc; -- cgit v1.2.3 From 4fa086b9b6640818c053c79d4d7104790ba76cb7 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Tue, 25 Jul 2017 20:51:26 -0400 Subject: drm/amd/display: Roll core_stream into dc_stream Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 16 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 92 ++++---- drivers/gpu/drm/amd/display/dc/core/dc.c | 107 ++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 41 ++-- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 7 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 259 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 118 +++++----- drivers/gpu/drm/amd/display/dc/dc.h | 71 +++--- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 10 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 12 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 176 +++++++------- .../drm/amd/display/dc/dce110/dce110_resource.c | 46 ++-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 12 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 72 +++--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 36 +-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 33 +-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 3 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 14 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 60 +++-- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 +-- 31 files changed, 612 insertions(+), 649 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 696a4112c8d9..c802437f4858 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1401,7 +1401,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - const struct dc_stream *stream; + struct dc_stream *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c index 0fcd9b373172..80d4e2670cc2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c @@ -2196,7 +2196,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - const struct dc_stream *stream) + struct dc_stream *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -2351,7 +2351,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - const struct dc_stream *dc_stream_attach; + struct dc_stream *dc_stream_attach; struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -2487,7 +2487,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - const struct dc_stream *new_stream; + struct dc_stream *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -2822,8 +2822,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *old_stream, - const struct dc_stream *new_stream, + struct dc_stream *old_stream, + struct dc_stream *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h index c565787cd782..94de6a3736fc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h @@ -45,7 +45,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - const struct dc_stream *stream; + struct dc_stream *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 5ef44ff4bcf8..9a850227eeeb 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2610,9 +2610,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2707,9 +2707,9 @@ static void populate_initial_data( data->fbc_en[num_displays + 4] = false; data->lpt_en[num_displays + 4] = false; - data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total); - data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total); - data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000); + data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); + data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); + data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); if (pipe[i].surface) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; @@ -2759,9 +2759,9 @@ static void populate_initial_data( break; } } else { - data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_addressable); + data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; - data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_addressable); + data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable); data->h_taps[num_displays + 4] = bw_int_to_fixed(1); data->v_taps[num_displays + 4] = bw_int_to_fixed(1); data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1); diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1651b7548d40..ef10a8b49379 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -365,7 +365,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } - input->dest.vactive = pipe->stream->public.timing.v_addressable; + input->dest.vactive = pipe->stream->timing.v_addressable; input->dest.recout_width = pipe->scl_data.recout.width; input->dest.recout_height = pipe->scl_data.recout.height; @@ -373,24 +373,24 @@ static void pipe_ctx_to_e2e_pipe_params ( input->dest.full_recout_width = pipe->scl_data.recout.width; input->dest.full_recout_height = pipe->scl_data.recout.height; - input->dest.htotal = pipe->stream->public.timing.h_total; - input->dest.hblank_start = input->dest.htotal - pipe->stream->public.timing.h_front_porch; + input->dest.htotal = pipe->stream->timing.h_total; + input->dest.hblank_start = input->dest.htotal - pipe->stream->timing.h_front_porch; input->dest.hblank_end = input->dest.hblank_start - - pipe->stream->public.timing.h_addressable - - pipe->stream->public.timing.h_border_left - - pipe->stream->public.timing.h_border_right; + - pipe->stream->timing.h_addressable + - pipe->stream->timing.h_border_left + - pipe->stream->timing.h_border_right; - input->dest.vtotal = pipe->stream->public.timing.v_total; - input->dest.vblank_start = input->dest.vtotal - pipe->stream->public.timing.v_front_porch; + input->dest.vtotal = pipe->stream->timing.v_total; + input->dest.vblank_start = input->dest.vtotal - pipe->stream->timing.v_front_porch; input->dest.vblank_end = input->dest.vblank_start - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_border_bottom - - pipe->stream->public.timing.v_border_top; - - input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0; + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_border_bottom + - pipe->stream->timing.v_border_top; + + input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0; input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset; @@ -851,14 +851,14 @@ bool dcn_validate_bandwidth( v->underscan_output[input_idx] = false; /* taken care of in recout already*/ v->interlace_output[input_idx] = false; - v->htotal[input_idx] = pipe->stream->public.timing.h_total; - v->vtotal[input_idx] = pipe->stream->public.timing.v_total; - v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total - - pipe->stream->public.timing.v_addressable - - pipe->stream->public.timing.v_front_porch; - v->vactive[input_idx] = pipe->stream->public.timing.v_addressable; - v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f; - if (pipe->stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + v->htotal[input_idx] = pipe->stream->timing.h_total; + v->vtotal[input_idx] = pipe->stream->timing.v_total; + v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total + - pipe->stream->timing.v_addressable + - pipe->stream->timing.v_front_porch; + v->vactive[input_idx] = pipe->stream->timing.v_addressable; + v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f; + if (pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) v->pixel_clock[input_idx] /= 2; @@ -867,10 +867,10 @@ bool dcn_validate_bandwidth( v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; v->lb_bit_per_pixel[input_idx] = 30; - v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable; - v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable; - v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable; + v->viewport_width[input_idx] = pipe->stream->timing.h_addressable; + v->viewport_height[input_idx] = pipe->stream->timing.v_addressable; + v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable; + v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable; v->override_hta_ps[input_idx] = 1; v->override_vta_ps[input_idx] = 1; v->override_hta_pschroma[input_idx] = 1; @@ -995,22 +995,22 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; - vesa_sync_start = pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom + - pipe->stream->public.timing.v_front_porch; + pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; + vesa_sync_start = pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom + + pipe->stream->timing.v_front_porch; - asic_blank_end = (pipe->stream->public.timing.v_total - + asic_blank_end = (pipe->stream->timing.v_total - vesa_sync_start - - pipe->stream->public.timing.v_border_top) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + pipe->stream->timing.v_border_top) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); asic_blank_start = asic_blank_end + - (pipe->stream->public.timing.v_border_top + - pipe->stream->public.timing.v_addressable + - pipe->stream->public.timing.v_border_bottom) - * (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0); + (pipe->stream->timing.v_border_top + + pipe->stream->timing.v_addressable + + pipe->stream->timing.v_border_bottom) + * (pipe->stream->timing.flags.INTERLACE ? 1 : 0); pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; @@ -1019,13 +1019,13 @@ bool dcn_validate_bandwidth( struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || - ((pipe->stream->public.view_format == + ((pipe->stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || - pipe->stream->public.view_format == + pipe->stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) && - (pipe->stream->public.timing.timing_3d_format == + (pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM || - pipe->stream->public.timing.timing_3d_format == + pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { /* update previously split pipe */ @@ -1034,8 +1034,8 @@ bool dcn_validate_bandwidth( hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx]; hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; - hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total; - hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total; + hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total; + hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total; hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start; hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end; } else { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index bab07f8d4880..df8c5ca6b22a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,19 +149,19 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.set_drr(&pipe, 1, vmin, vmax); /* build and update the info frame */ @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - const struct dc_stream **stream, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[0]); + struct dc_stream *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -189,7 +189,7 @@ static bool stream_get_crtc_position(struct dc *dc, struct pipe_ctx *pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe->stream == core_stream && pipe->stream_enc) { + if (pipe->stream == stream && pipe->stream_enc) { core_dc->hwss.get_position(&pipe, 1, &position); *v_pos = position.vertical_count; @@ -203,15 +203,12 @@ static bool stream_get_crtc_position(struct dc *dc, static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { - + if (core_dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_gamut_remap(pipes); ret = true; @@ -221,22 +218,21 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i = 0; bool ret = false; struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { pipes = &core_dc->current_context->res_ctx.pipe_ctx[i]; core_dc->hwss.program_csc_matrix(pipes, - core_stream->public.output_color_space, - core_stream->public.csc_color_matrix.matrix); + stream->output_color_space, + stream->csc_color_matrix.matrix); ret = true; } } @@ -245,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, const struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -256,11 +252,11 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream[i]); + struct dc_stream *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream - == core_stream) { + == stream) { pipes_affected[num_pipes_affected++] = &core_dc->current_context->res_ctx.pipe_ctx[j]; } @@ -337,10 +333,9 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(const struct dc_stream *dc_stream, +void set_dither_option(struct dc_stream *stream, enum dc_dither_option option) { - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; @@ -351,21 +346,21 @@ void set_dither_option(const struct dc_stream *dc_stream, if (option > DITHER_OPTION_MAX) return; if (option == DITHER_OPTION_DEFAULT) { - switch (stream->public.timing.display_color_depth) { + switch (stream->timing.display_color_depth) { case COLOR_DEPTH_666: - stream->public.dither_option = DITHER_OPTION_SPATIAL6; + stream->dither_option = DITHER_OPTION_SPATIAL6; break; case COLOR_DEPTH_888: - stream->public.dither_option = DITHER_OPTION_SPATIAL8; + stream->dither_option = DITHER_OPTION_SPATIAL8; break; case COLOR_DEPTH_101010: - stream->public.dither_option = DITHER_OPTION_SPATIAL10; + stream->dither_option = DITHER_OPTION_SPATIAL10; break; default: option = DITHER_OPTION_DISABLE; } } else { - stream->public.dither_option = option; + stream->dither_option = option; } resource_build_bit_depth_reduction_params(stream, ¶ms); @@ -644,7 +639,7 @@ static bool is_validation_required( if (set[i].surface_count != context->stream_status[i].surface_count) return true; - if (!is_stream_unchanged(DC_STREAM_TO_CORE(set[i].stream), context->streams[i])) + if (!is_stream_unchanged(set[i].stream, context->streams[i])) return true; for (j = 0; j < set[i].surface_count; j++) { @@ -754,7 +749,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream) + struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -869,7 +864,7 @@ static bool context_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != &context->streams[i]->public) + if (dc->current_context->streams[i] != context->streams[i]) return true; } @@ -878,7 +873,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { uint8_t i; @@ -887,7 +882,7 @@ static bool streams_changed( return true; for (i = 0; i < dc->current_context->stream_count; i++) { - if (&dc->current_context->streams[i]->public != streams[i]) + if (dc->current_context->streams[i] != streams[i]) return true; } @@ -897,7 +892,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { bool ret = true; @@ -915,7 +910,7 @@ bool dc_enable_stereo( else pipe = &core_dc->current_context->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { - if (streams[j] && streams[j] == &pipe->stream->public && + if (streams[j] && streams[j] == pipe->stream && core_dc->hwss.setup_stereo) core_dc->hwss.setup_stereo(pipe, core_dc); } @@ -943,10 +938,10 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - const struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) - dc_streams[i] = &context->streams[i]->public; + dc_streams[i] = context->streams[i]; if (!dcb->funcs->is_accelerated_mode(dcb)) core_dc->hwss.enable_accelerated_mode(core_dc); @@ -985,11 +980,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", - context->streams[i]->public.timing.h_addressable, - context->streams[i]->public.timing.v_addressable, - context->streams[i]->public.timing.h_total, - context->streams[i]->public.timing.v_total, - context->streams[i]->public.timing.pix_clk_khz); + context->streams[i]->timing.h_addressable, + context->streams[i]->timing.v_addressable, + context->streams[i]->timing.h_total, + context->streams[i]->timing.v_total, + context->streams[i]->timing.pix_clk_khz); } dc_enable_stereo(dc, context, dc_streams, context->stream_count); @@ -1016,7 +1011,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - const struct dc_stream *stream = &context->streams[i]->public; + struct dc_stream *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1031,7 +1026,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1047,8 +1042,8 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - const struct dc_stream *stream = streams[i]; - const struct dc_stream_status *status = dc_stream_get_status(stream); + struct dc_stream *stream = streams[i]; + struct dc_stream_status *status = dc_stream_get_status(stream); int j; dc_stream_log(stream, @@ -1120,7 +1115,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **new_surfaces, uint8_t new_surface_count, - const struct dc_stream *dc_stream) + struct dc_stream *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1377,7 +1372,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1385,7 +1380,6 @@ void dc_update_surfaces_and_stream(struct dc *dc, int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct dc_context *dc_ctx = core_dc->ctx; /* Currently this function do not result in any HW programming @@ -1398,7 +1392,8 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (surface_count == 0) return; - stream_status = dc_stream_get_status(dc_stream); + stream_status = dc_stream_get_status(stream); + ASSERT(stream_status); if (!stream_status) return; /* Cannot commit surface to stream that is not committed */ @@ -1415,19 +1410,19 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (stream_update) { if ((stream_update->src.height != 0) && (stream_update->src.width != 0)) - stream->public.src = stream_update->src; + stream->src = stream_update->src; if ((stream_update->dst.height != 0) && (stream_update->dst.width != 0)) - stream->public.dst = stream_update->dst; + stream->dst = stream_update->dst; if (stream_update->out_transfer_func && stream_update->out_transfer_func != - dc_stream->out_transfer_func) { - if (dc_stream->out_transfer_func != NULL) - dc_transfer_func_release(dc_stream->out_transfer_func); + stream->out_transfer_func) { + if (stream->out_transfer_func != NULL) + dc_transfer_func_release(stream->out_transfer_func); dc_transfer_func_retain(stream_update->out_transfer_func); - stream->public.out_transfer_func = + stream->out_transfer_func = stream_update->out_transfer_func; } } @@ -1469,7 +1464,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, dc_stream, + new_surfaces, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1617,7 +1612,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, core_dc, pipe_ctx->surface, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ - dc_stream_set_cursor_position(&pipe_ctx->stream->public, &position); + dc_stream_set_cursor_position(pipe_ctx->stream, &position); if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); @@ -1712,7 +1707,7 @@ struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) - return &(core_dc->current_context->streams[i]->public); + return core_dc->current_context->streams[i]; return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 9a5df3a848b5..bf127a88e533 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -321,8 +321,8 @@ void context_timing_trace( TIMING_TRACE("OTG_%d H_tot:%d V_tot:%d H_pos:%d V_pos:%d\n", pipe_ctx->tg->inst, - pipe_ctx->stream->public.timing.h_total, - pipe_ctx->stream->public.timing.v_total, + pipe_ctx->stream->timing.h_total, + pipe_ctx->stream->timing.v_total, h_pos[i], v_pos[i]); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index fd2ae181cff2..2487046457c8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1151,7 +1151,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) &downspread.raw, sizeof(downspread)); downspread.bits.IGNORE_MSA_TIMING_PARAM = - (stream->public.ignore_msa_timing_param) ? 1 : 0; + (stream->ignore_msa_timing_param) ? 1 : 0; core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, &downspread.raw, sizeof(downspread)); @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1258,13 +1258,13 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) dal_ddc_service_write_scdc_data( stream->sink->link->ddc, stream->phy_pix_clk, - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE); + stream->timing.flags.LTE_340MCSC_SCRAMBLE); memset(&stream->sink->link->cur_link_settings, 0, sizeof(struct dc_link_settings)); - display_color_depth = stream->public.timing.display_color_depth; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + display_color_depth = stream->timing.display_color_depth; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) display_color_depth = COLOR_DEPTH_888; link->link_enc->funcs->enable_tmds_output( @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1377,7 +1377,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, uint32_t frame_ramp, const struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); - struct core_stream *core_stream = NULL; struct abm *abm = core_dc->res_pool->abm; unsigned int controller_id = 0; int i; @@ -1390,11 +1389,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { - core_stream = DC_STREAM_TO_CORE(stream); for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx. pipe_ctx[i].stream - == core_stream) + == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ @@ -1457,7 +1455,6 @@ bool dc_link_setup_psr(struct dc_link *link, { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct dmcu *dmcu = core_dc->res_pool->dmcu; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); int i; psr_context->controllerId = CONTROLLER_ID_UNDEFINED; @@ -1501,7 +1498,7 @@ bool dc_link_setup_psr(struct dc_link *link, for (i = 0; i < MAX_PIPES; i++) { if (core_dc->current_context->res_ctx.pipe_ctx[i].stream - == core_stream) { + == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ @@ -1590,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1699,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1717,7 +1714,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* get calculate VC payload for stream: stream_alloc */ if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, true)) { update_mst_stream_alloc_table( @@ -1759,11 +1756,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) /* send down message */ dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, true); /* slot X.Y for only current stream */ @@ -1781,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1806,7 +1803,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { if (dm_helpers_dp_mst_write_payload_allocation_table( stream->ctx, - &stream->public, + stream, &proposed_table, false)) { @@ -1848,11 +1845,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) if (mst_mode) { dm_helpers_dp_mst_poll_for_allocation_change_trigger( stream->ctx, - &stream->public); + stream); dm_helpers_dp_mst_send_payload_allocation( stream->ctx, - &stream->public, + stream, false); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index c7b400786121..d9754b5f2543 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1434,7 +1434,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct core_stream *stream, +void decide_link_settings(struct dc_stream *stream, struct dc_link_settings *link_setting) { @@ -1446,8 +1446,7 @@ void decide_link_settings(struct core_stream *stream, uint32_t req_bw; uint32_t link_bw; - req_bw = bandwidth_in_kbps_from_timing( - &stream->public.timing); + req_bw = bandwidth_in_kbps_from_timing(&stream->timing); link = stream->sink->link; @@ -2327,7 +2326,7 @@ static void set_crtc_test_pattern(struct dc_link *link, { enum controller_dp_test_pattern controller_test_pattern; enum dc_color_depth color_depth = pipe_ctx-> - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; struct bit_depth_reduction_params params; memset(¶ms, 0, sizeof(params)); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 5bdcd5067116..76dc16916821 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -78,7 +78,7 @@ void dp_enable_link_phy( pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { pipes[i].clock_source = dp_cs; pipes[i].pix_clk_params.requested_pix_clk = - pipes[i].stream->public.timing.pix_clk_khz; + pipes[i].stream->timing.pix_clk_khz; pipes[i].clock_source->funcs->program_pix_clk( pipes[i].clock_source, &pipes[i].pix_clk_params, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index eeefc9c33633..ddbd3de63a8d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,25 +294,25 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2) + struct dc_stream *stream1, + struct dc_stream *stream2) { - if (stream1->public.timing.h_total != stream2->public.timing.h_total) + if (stream1->timing.h_total != stream2->timing.h_total) return false; - if (stream1->public.timing.v_total != stream2->public.timing.v_total) + if (stream1->timing.v_total != stream2->timing.v_total) return false; - if (stream1->public.timing.h_addressable - != stream2->public.timing.h_addressable) + if (stream1->timing.h_addressable + != stream2->timing.h_addressable) return false; - if (stream1->public.timing.v_addressable - != stream2->public.timing.v_addressable) + if (stream1->timing.v_addressable + != stream2->timing.v_addressable) return false; - if (stream1->public.timing.pix_clk_khz - != stream2->public.timing.pix_clk_khz) + if (stream1->timing.pix_clk_khz + != stream2->timing.pix_clk_khz) return false; if (stream1->phy_pix_clk != stream2->phy_pix_clk @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - const struct dc_stream *stream = &pipe_ctx->stream->public; + const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -539,38 +539,38 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->surface->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); - pipe_ctx->scl_data.recout.x = stream->public.dst.x; - if (stream->public.src.x < surf_clip.x) + pipe_ctx->scl_data.recout.x = stream->dst.x; + if (stream->src.x < surf_clip.x) pipe_ctx->scl_data.recout.x += (surf_clip.x - - stream->public.src.x) * stream->public.dst.width - / stream->public.src.width; + - stream->src.x) * stream->dst.width + / stream->src.width; pipe_ctx->scl_data.recout.width = surf_clip.width * - stream->public.dst.width / stream->public.src.width; + stream->dst.width / stream->src.width; if (pipe_ctx->scl_data.recout.width + pipe_ctx->scl_data.recout.x > - stream->public.dst.x + stream->public.dst.width) + stream->dst.x + stream->dst.width) pipe_ctx->scl_data.recout.width = - stream->public.dst.x + stream->public.dst.width + stream->dst.x + stream->dst.width - pipe_ctx->scl_data.recout.x; - pipe_ctx->scl_data.recout.y = stream->public.dst.y; - if (stream->public.src.y < surf_clip.y) + pipe_ctx->scl_data.recout.y = stream->dst.y; + if (stream->src.y < surf_clip.y) pipe_ctx->scl_data.recout.y += (surf_clip.y - - stream->public.src.y) * stream->public.dst.height - / stream->public.src.height; + - stream->src.y) * stream->dst.height + / stream->src.height; pipe_ctx->scl_data.recout.height = surf_clip.height * - stream->public.dst.height / stream->public.src.height; + stream->dst.height / stream->src.height; if (pipe_ctx->scl_data.recout.height + pipe_ctx->scl_data.recout.y > - stream->public.dst.y + stream->public.dst.height) + stream->dst.y + stream->dst.height) pipe_ctx->scl_data.recout.height = - stream->public.dst.y + stream->public.dst.height + stream->dst.y + stream->dst.height - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; /* Floor primary pipe, ceil 2ndary pipe */ @@ -582,7 +582,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip } } else if (pipe_ctx->bottom_pipe && pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { - if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else pipe_ctx->scl_data.recout.width /= 2; @@ -592,14 +592,14 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->public.dst.x + (surface->dst_rect.x - stream->public.src.x) - * stream->public.dst.width / stream->public.src.width - + recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + * stream->dst.width / stream->src.width - surf_src.x * surface->dst_rect.width / surf_src.width - * stream->public.dst.width / stream->public.src.width; - recout_full_y = stream->public.dst.y + (surface->dst_rect.y - stream->public.src.y) - * stream->public.dst.height / stream->public.src.height - + * stream->dst.width / stream->src.width; + recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + * stream->dst.height / stream->src.height - surf_src.y * surface->dst_rect.height / surf_src.height - * stream->public.dst.height / stream->public.src.height; + * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; recout_skip->height = pipe_ctx->scl_data.recout.y - recout_full_y; @@ -608,12 +608,12 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; - const int in_w = stream->public.src.width; - const int in_h = stream->public.src.height; - const int out_w = stream->public.dst.width; - const int out_h = stream->public.dst.height; + const int in_w = stream->src.width; + const int in_h = stream->src.height; + const int out_w = stream->dst.width; + const int out_h = stream->dst.height; if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || pipe_ctx->surface->rotation == ROTATION_ANGLE_270) @@ -626,9 +626,9 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) surf_src.height, surface->dst_rect.height); - if (stream->public.view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) + if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; - else if (stream->public.view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) + else if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.ratios.vert.value *= 2; pipe_ctx->scl_data.ratios.vert.value = div64_s64( @@ -815,7 +815,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { const struct dc_surface *surface = pipe_ctx->surface; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream) + struct dc_stream *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,11 +940,10 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct pipe_ctx *head_pipe = NULL; @@ -980,10 +979,9 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - const struct dc_stream *dc_stream) + struct dc_stream *stream) { int i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); for (i = MAX_PIPES - 1; i >= 0; i--) { /* never release the topmost pipe*/ @@ -999,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1033,14 +1031,13 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_surface * const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context, const struct resource_pool *pool) { int i; struct pipe_ctx *tail_pipe; struct dc_stream_status *stream_status = NULL; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); if (surface_count > MAX_SURFACE_NUM) { @@ -1050,7 +1047,7 @@ bool resource_attach_surfaces_to_context( } for (i = 0; i < context->stream_count; i++) - if (&context->streams[i]->public == dc_stream) { + if (context->streams[i] == stream) { stream_status = &context->stream_status[i]; break; } @@ -1081,7 +1078,7 @@ bool resource_attach_surfaces_to_context( for (i = 0; i < surface_count; i++) { struct dc_surface *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - context, pool, dc_stream); + context, pool, stream); #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (!free_pipe) { @@ -1109,7 +1106,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = free_pipe; } - release_free_pipes_for_stream(&context->res_ctx, dc_stream); + release_free_pipes_for_stream(&context->res_ctx, stream); /* assign new surfaces*/ for (i = 0; i < surface_count; i++) @@ -1121,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(const struct core_stream *cur_stream, - const struct core_stream *new_stream) +static bool is_timing_changed(struct dc_stream *cur_stream, + struct dc_stream *new_stream) { if (cur_stream == NULL) return true; @@ -1134,18 +1131,17 @@ static bool is_timing_changed(const struct core_stream *cur_stream, return true; /* If output color space is changed, need to reprogram info frames */ - if (cur_stream->public.output_color_space != - new_stream->public.output_color_space) + if (cur_stream->output_color_space != new_stream->output_color_space) return true; return memcmp( - &cur_stream->public.timing, - &new_stream->public.timing, + &cur_stream->timing, + &new_stream->timing, sizeof(struct dc_crtc_timing)) != 0; } static bool are_stream_backends_same( - const struct core_stream *stream_a, const struct core_stream *stream_b) + struct dc_stream *stream_a, struct dc_stream *stream_b) { if (stream_a == stream_b) return true; @@ -1160,7 +1156,7 @@ static bool are_stream_backends_same( } bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream) + struct dc_stream *old_stream, struct dc_stream *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1186,7 +1182,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( old_context->stream_status[j].surfaces, old_context->stream_status[j].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; @@ -1195,7 +1191,7 @@ bool resource_validate_attach_surfaces( if (!resource_attach_surfaces_to_context( set[i].surfaces, set[i].surface_count, - &context->streams[i]->public, + context->streams[i], context, pool)) return false; @@ -1237,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; @@ -1267,7 +1263,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { int i; int j = -1; @@ -1318,22 +1314,22 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct core_stream *stream) +static void update_stream_signal(struct dc_stream *stream) { - if (stream->public.output_signal == SIGNAL_TYPE_NONE) { - struct dc_sink *dc_sink = stream->public.sink; + if (stream->output_signal == SIGNAL_TYPE_NONE) { + struct dc_sink *dc_sink = stream->sink; if (dc_sink->sink_signal == SIGNAL_TYPE_NONE) stream->signal = stream->sink->link->connector_signal; else stream->signal = dc_sink->sink_signal; } else { - stream->signal = stream->public.output_signal; + stream->signal = stream->output_signal; } if (dc_is_dvi_signal(stream->signal)) { - if (stream->public.timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && - stream->public.sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) + if (stream->timing.pix_clk_khz > TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST && + stream->sink->sink_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) stream->signal = SIGNAL_TYPE_DVI_DUAL_LINK; else stream->signal = SIGNAL_TYPE_DVI_SINGLE_LINK; @@ -1341,12 +1337,12 @@ static void update_stream_signal(struct core_stream *stream) } bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream) + struct validate_context *old_context, struct dc_stream *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - const struct core_stream *old_stream = old_context->streams[i]; + struct dc_stream *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1359,7 +1355,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_surface *surface = to_pipe_ctx->surface; - struct core_stream *stream = to_pipe_ctx->stream; + struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1367,14 +1363,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct core_stream *find_pll_sharable_stream( - const struct core_stream *stream_needs_pll, +static struct dc_stream *find_pll_sharable_stream( + struct dc_stream *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream_has_pll = context->streams[i]; + struct dc_stream *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1418,17 +1414,17 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct core_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream *stream) { update_stream_signal(stream); /* update actual pixel clock on all streams */ if (dc_is_hdmi_signal(stream->signal)) stream->phy_pix_clk = get_norm_pix_clk( - &stream->public.timing); + &stream->timing); else stream->phy_pix_clk = - stream->public.timing.pix_clk_khz; + stream->timing.pix_clk_khz; } enum dc_status resource_map_pool_resources( @@ -1440,7 +1436,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1493,7 +1489,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1524,7 +1520,7 @@ enum dc_status resource_map_pool_resources( /* TODO: Add check if ASIC support and EDID audio */ if (!stream->sink->converter_disable_audio && dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->public.audio_info.mode_count) { + stream->audio_info.mode_count) { pipe_ctx->audio = find_first_free_audio( &context->res_ctx, pool); @@ -1560,7 +1556,7 @@ void validate_guaranteed_copy_streams( context->res_ctx.pipe_ctx[i].stream = context->res_ctx.pipe_ctx[0].stream; - dc_stream_retain(&context->streams[i]->public); + dc_stream_retain(context->streams[i]); context->stream_count++; } } @@ -1588,7 +1584,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1602,12 +1598,12 @@ static void set_avi_info_frame( uint8_t byte_index = 0; union hdmi_info_packet *hdmi_info = &info_frame.avi_info_packet.info_packet_hdmi; union display_content_support support = {0}; - unsigned int vic = pipe_ctx->stream->public.timing.vic; + unsigned int vic = pipe_ctx->stream->timing.vic; enum dc_timing_3d_format format; - color_space = pipe_ctx->stream->public.output_color_space; + color_space = pipe_ctx->stream->output_color_space; if (color_space == COLOR_SPACE_UNKNOWN) - color_space = (stream->public.timing.pixel_encoding == PIXEL_ENCODING_RGB)? + color_space = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? COLOR_SPACE_SRGB:COLOR_SPACE_YCBCR709; /* Initialize header */ @@ -1622,7 +1618,7 @@ static void set_avi_info_frame( * according to HDMI 2.0 spec (Section 10.1) */ - switch (stream->public.timing.pixel_encoding) { + switch (stream->timing.pixel_encoding) { case PIXEL_ENCODING_YCBCR422: pixel_encoding = 1; break; @@ -1664,7 +1660,7 @@ static void set_avi_info_frame( color_space == COLOR_SPACE_YCBCR601_LIMITED) hdmi_info->bits.C0_C1 = COLORIMETRY_ITU601; else { - if (stream->public.timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) BREAK_TO_DEBUGGER(); hdmi_info->bits.C0_C1 = COLORIMETRY_NO_DATA; } @@ -1679,7 +1675,7 @@ static void set_avi_info_frame( } /* TODO: un-hardcode aspect ratio */ - aspect = stream->public.timing.aspect_ratio; + aspect = stream->timing.aspect_ratio; switch (aspect) { case ASPECT_RATIO_4_3: @@ -1705,7 +1701,7 @@ static void set_avi_info_frame( itc = true; itc_value = 1; - support = stream->public.sink->edid_caps.content_support; + support = stream->sink->edid_caps.content_support; if (itc) { if (!support.bits.valid_content_type) { @@ -1744,8 +1740,8 @@ static void set_avi_info_frame( /* TODO : We should handle YCC quantization */ /* but we do not have matrix calculation */ - if (stream->public.sink->edid_caps.qs_bit == 1 && - stream->public.sink->edid_caps.qy_bit == 1) { + if (stream->sink->edid_caps.qs_bit == 1 && + stream->sink->edid_caps.qy_bit == 1) { if (color_space == COLOR_SPACE_SRGB || color_space == COLOR_SPACE_2020_RGB_FULLRANGE) { hdmi_info->bits.Q0_Q1 = RGB_QUANTIZATION_FULL_RANGE; @@ -1764,11 +1760,11 @@ static void set_avi_info_frame( } ///VIC - format = stream->public.timing.timing_3d_format; + format = stream->timing.timing_3d_format; /*todo, add 3DStereo support*/ if (format != TIMING_3D_FORMAT_NONE) { // Based on HDMI specs hdmi vic needs to be converted to cea vic when 3D is enabled - switch (pipe_ctx->stream->public.timing.hdmi_vic) { + switch (pipe_ctx->stream->timing.hdmi_vic) { case 1: vic = 95; break; @@ -1797,12 +1793,12 @@ static void set_avi_info_frame( * barBottom: Line Number of Start of Bottom Bar. * barLeft: Pixel Number of End of Left Bar. * barRight: Pixel Number of Start of Right Bar. */ - hdmi_info->bits.bar_top = stream->public.timing.v_border_top; - hdmi_info->bits.bar_bottom = (stream->public.timing.v_total - - stream->public.timing.v_border_bottom + 1); - hdmi_info->bits.bar_left = stream->public.timing.h_border_left; - hdmi_info->bits.bar_right = (stream->public.timing.h_total - - stream->public.timing.h_border_right + 1); + hdmi_info->bits.bar_top = stream->timing.v_border_top; + hdmi_info->bits.bar_bottom = (stream->timing.v_total + - stream->timing.v_border_bottom + 1); + hdmi_info->bits.bar_left = stream->timing.h_border_left; + hdmi_info->bits.bar_right = (stream->timing.h_total + - stream->timing.h_border_right + 1); /* check_sum - Calculate AFMT_AVI_INFO0 ~ AFMT_AVI_INFO3 */ check_sum = &info_frame.avi_info_packet.info_packet_hdmi.packet_raw_data.sb[0]; @@ -1830,7 +1826,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1842,16 +1838,16 @@ static void set_vendor_info_packet( info_packet->valid = false; - format = stream->public.timing.timing_3d_format; - if (stream->public.view_format == VIEW_3D_FORMAT_NONE) + format = stream->timing.timing_3d_format; + if (stream->view_format == VIEW_3D_FORMAT_NONE) format = TIMING_3D_FORMAT_NONE; /* Can be different depending on packet content */ length = 5; - if (stream->public.timing.hdmi_vic != 0 - && stream->public.timing.h_total >= 3840 - && stream->public.timing.v_total >= 2160) + if (stream->timing.hdmi_vic != 0 + && stream->timing.h_total >= 3840 + && stream->timing.v_total >= 2160) hdmi_vic_mode = true; /* According to HDMI 1.4a CTS, VSIF should be sent @@ -1918,7 +1914,7 @@ static void set_vendor_info_packet( /*PB5: If PB4 is set to 0x1 (extended resolution format) * fill PB5 with the correct HDMI VIC code */ if (hdmi_vic_mode) - info_packet->sb[5] = stream->public.timing.hdmi_vic; + info_packet->sb[5] = stream->timing.hdmi_vic; /* Header */ info_packet->hb0 = HDMI_INFOFRAME_TYPE_VENDOR; /* VSIF packet type. */ @@ -1943,7 +1939,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { /* SPD info packet for FreeSync */ @@ -1953,7 +1949,7 @@ static void set_spd_info_packet( /* Check if Freesync is supported. Return if false. If true, * set the corresponding bit in the info packet */ - if (stream->public.freesync_ctx.supported == false) + if (stream->freesync_ctx.supported == false) return; if (dc_is_hdmi_signal(stream->signal)) { @@ -2018,20 +2014,20 @@ static void set_spd_info_packet( /* PB6 = [Bits 7:3 = Reserved] */ info_packet->sb[6] = 0x00; - if (stream->public.freesync_ctx.supported == true) + if (stream->freesync_ctx.supported == true) /* PB6 = [Bit 0 = FreeSync Supported] */ info_packet->sb[6] |= 0x01; - if (stream->public.freesync_ctx.enabled == true) + if (stream->freesync_ctx.enabled == true) /* PB6 = [Bit 1 = FreeSync Enabled] */ info_packet->sb[6] |= 0x02; - if (stream->public.freesync_ctx.active == true) + if (stream->freesync_ctx.active == true) /* PB6 = [Bit 2 = FreeSync Active] */ info_packet->sb[6] |= 0x04; /* PB7 = FreeSync Minimum refresh rate (Hz) */ - info_packet->sb[7] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[7] = (unsigned char) (stream->freesync_ctx. min_refresh_in_micro_hz / 1000000); /* PB8 = FreeSync Maximum refresh rate (Hz) @@ -2040,7 +2036,7 @@ static void set_spd_info_packet( * of the panel, because we should never go above the field * rate of the mode timing set. */ - info_packet->sb[8] = (unsigned char) (stream->public.freesync_ctx. + info_packet->sb[8] = (unsigned char) (stream->freesync_ctx. nominal_refresh_in_micro_hz / 1000000); /* PB9 - PB27 = Reserved */ @@ -2065,7 +2061,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_surface *surface, - struct core_stream *stream) + struct dc_stream *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2168,7 +2164,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct core_stream *stream) + struct dc_stream *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2218,7 +2214,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) context->stream_status[i].surfaces[j]); context->stream_status[i].surface_count = 0; - dc_stream_release(&context->streams[i]->public); + dc_stream_release(context->streams[i]); context->streams[i] = NULL; } } @@ -2248,7 +2244,7 @@ void dc_resource_validate_ctx_copy_construct( } for (i = 0; i < dst_ctx->stream_count; i++) { - dc_stream_retain(&dst_ctx->streams[i]->public); + dc_stream_retain(dst_ctx->streams[i]); for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) dc_surface_retain( dst_ctx->stream_status[i].surfaces[j]); @@ -2321,7 +2317,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - const struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2401,12 +2397,12 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth) { - enum dc_dither_option option = stream->public.dither_option; + enum dc_dither_option option = stream->dither_option; enum dc_pixel_encoding pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; memset(fmt_bit_depth, 0, sizeof(*fmt_bit_depth)); @@ -2511,31 +2507,30 @@ void resource_build_bit_depth_reduction_params(const struct core_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - struct dc_link *link = core_stream->sink->link; + struct dc_link *link = stream->sink->link; struct timing_generator *tg = core_dc->res_pool->timing_generators[0]; enum dc_status res = DC_OK; - calculate_phy_pix_clks(core_stream); + calculate_phy_pix_clks(stream); - if (!tg->funcs->validate_timing(tg, &core_stream->public.timing)) + if (!tg->funcs->validate_timing(tg, &stream->timing)) res = DC_FAIL_CONTROLLER_VALIDATE; if (res == DC_OK) if (!link->link_enc->funcs->validate_output_with_stream( - link->link_enc, core_stream)) + link->link_enc, stream)) res = DC_FAIL_ENC_VALIDATE; /* TODO: validate audio ASIC caps, encoder */ if (res == DC_OK) - res = dc_link_validate_mode_timing(core_stream, + res = dc_link_validate_mode_timing(stream, link, - &core_stream->public.timing); + &stream->timing); if (res != DC_OK) DC_ERROR("Failed validation for stream %p, err:%d, !\n", diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 5b356ddf5614..46ad1bc12f63 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -35,24 +35,24 @@ ******************************************************************************/ struct stream { - struct core_stream protected; + struct dc_stream protected; int ref_count; }; -#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected.public) +#define DC_STREAM_TO_STREAM(dc_stream) container_of(dc_stream, struct stream, protected) /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct core_stream *stream, +static bool construct(struct dc_stream *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; stream->sink = dc_sink_data; stream->ctx = stream->sink->ctx; - stream->public.sink = dc_sink_data; + stream->sink = dc_sink_data; dc_sink_retain(dc_sink_data); @@ -60,52 +60,52 @@ static bool construct(struct core_stream *stream, /* TODO - Remove this translation */ for (i = 0; i < (dc_sink_data->edid_caps.audio_mode_count); i++) { - stream->public.audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; - stream->public.audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; - stream->public.audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; - stream->public.audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; + stream->audio_info.modes[i].channel_count = dc_sink_data->edid_caps.audio_modes[i].channel_count; + stream->audio_info.modes[i].format_code = dc_sink_data->edid_caps.audio_modes[i].format_code; + stream->audio_info.modes[i].sample_rates.all = dc_sink_data->edid_caps.audio_modes[i].sample_rate; + stream->audio_info.modes[i].sample_size = dc_sink_data->edid_caps.audio_modes[i].sample_size; } - stream->public.audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; - stream->public.audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; - stream->public.audio_info.video_latency = dc_sink_data->edid_caps.video_latency; + stream->audio_info.mode_count = dc_sink_data->edid_caps.audio_mode_count; + stream->audio_info.audio_latency = dc_sink_data->edid_caps.audio_latency; + stream->audio_info.video_latency = dc_sink_data->edid_caps.video_latency; memmove( - stream->public.audio_info.display_name, + stream->audio_info.display_name, dc_sink_data->edid_caps.display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); - stream->public.audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; - stream->public.audio_info.product_id = dc_sink_data->edid_caps.product_id; - stream->public.audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; + stream->audio_info.manufacture_id = dc_sink_data->edid_caps.manufacturer_id; + stream->audio_info.product_id = dc_sink_data->edid_caps.product_id; + stream->audio_info.flags.all = dc_sink_data->edid_caps.speaker_flags; if (dc_sink_data->dc_container_id != NULL) { struct dc_container_id *dc_container_id = dc_sink_data->dc_container_id; - stream->public.audio_info.port_id[0] = dc_container_id->portId[0]; - stream->public.audio_info.port_id[1] = dc_container_id->portId[1]; + stream->audio_info.port_id[0] = dc_container_id->portId[0]; + stream->audio_info.port_id[1] = dc_container_id->portId[1]; } else { /* TODO - WindowDM has implemented, other DMs need Unhardcode port_id */ - stream->public.audio_info.port_id[0] = 0x5558859e; - stream->public.audio_info.port_id[1] = 0xd989449; + stream->audio_info.port_id[0] = 0x5558859e; + stream->audio_info.port_id[1] = 0xd989449; } /* EDID CAP translation for HDMI 2.0 */ - stream->public.timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; + stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; stream->status.link = stream->sink->link; return true; } -static void destruct(struct core_stream *stream) +static void destruct(struct dc_stream *stream) { dc_sink_release(stream->sink); - if (stream->public.out_transfer_func != NULL) { + if (stream->out_transfer_func != NULL) { dc_transfer_func_release( - stream->public.out_transfer_func); - stream->public.out_transfer_func = NULL; + stream->out_transfer_func); + stream->out_transfer_func = NULL; } } -void dc_stream_retain(const struct dc_stream *dc_stream) +void dc_stream_retain(struct dc_stream *dc_stream) { struct stream *stream = DC_STREAM_TO_STREAM(dc_stream); @@ -113,17 +113,16 @@ void dc_stream_retain(const struct dc_stream *dc_stream) stream->ref_count++; } -void dc_stream_release(const struct dc_stream *public) +void dc_stream_release(struct dc_stream *public) { struct stream *stream = DC_STREAM_TO_STREAM(public); - struct core_stream *protected = DC_STREAM_TO_CORE(public); if (public != NULL) { ASSERT(stream->ref_count > 0); stream->ref_count--; if (stream->ref_count == 0) { - destruct(protected); + destruct(public); dm_free(stream); } } @@ -147,7 +146,7 @@ struct dc_stream *dc_create_stream_for_sink( stream->ref_count++; - return &stream->protected.public; + return &stream->protected; construct_fail: dm_free(stream); @@ -157,10 +156,9 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream) + struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); for (i = 0; i < dc->current_context->stream_count; i++) { @@ -176,15 +174,14 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *dc_stream, + const struct dc_stream *stream, const struct dc_cursor_attributes *attributes) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -193,7 +190,6 @@ bool dc_stream_set_cursor_attributes( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -213,15 +209,14 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - const struct dc_stream *dc_stream, + struct dc_stream *stream, const struct dc_cursor_position *position) { int i; - struct core_stream *stream; struct core_dc *core_dc; struct resource_context *res_ctx; - if (NULL == dc_stream) { + if (NULL == stream) { dm_error("DC: dc_stream is NULL!\n"); return false; } @@ -231,7 +226,6 @@ bool dc_stream_set_cursor_position( return false; } - stream = DC_STREAM_TO_CORE(dc_stream); core_dc = DC_TO_CORE(stream->ctx->dc); res_ctx = &core_dc->current_context->res_ctx; @@ -240,7 +234,7 @@ bool dc_stream_set_cursor_position( struct input_pixel_processor *ipp = pipe_ctx->ipp; struct dc_cursor_position pos_cpy = *position; struct dc_cursor_mi_param param = { - .pixel_clk_khz = dc_stream->timing.pix_clk_khz, + .pixel_clk_khz = stream->timing.pix_clk_khz, .ref_clk_khz = core_dc->res_pool->ref_clock_inKhz, .viewport_x_start = pipe_ctx->scl_data.viewport.x, .viewport_width = pipe_ctx->scl_data.viewport.width, @@ -264,10 +258,9 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) { uint8_t i; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -284,7 +277,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *dc_stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, +bool dc_stream_get_scanoutpos(const struct dc_stream *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -292,7 +285,6 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *dc_stream, { uint8_t i; bool ret = false; - struct core_stream *stream = DC_STREAM_TO_CORE(dc_stream); struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &core_dc->current_context->res_ctx; @@ -322,37 +314,35 @@ void dc_stream_log( struct dal_logger *dm_logger, enum dc_log_type log_type) { - const struct core_stream *core_stream = - DC_STREAM_TO_CORE(stream); dm_logger_write(dm_logger, log_type, "core_stream 0x%x: src: %d, %d, %d, %d; dst: %d, %d, %d, %d, colorSpace:%d\n", - core_stream, - core_stream->public.src.x, - core_stream->public.src.y, - core_stream->public.src.width, - core_stream->public.src.height, - core_stream->public.dst.x, - core_stream->public.dst.y, - core_stream->public.dst.width, - core_stream->public.dst.height, - core_stream->public.output_color_space); + stream, + stream->src.x, + stream->src.y, + stream->src.width, + stream->src.height, + stream->dst.x, + stream->dst.y, + stream->dst.width, + stream->dst.height, + stream->output_color_space); dm_logger_write(dm_logger, log_type, "\tpix_clk_khz: %d, h_total: %d, v_total: %d, pixelencoder:%d, displaycolorDepth:%d\n", - core_stream->public.timing.pix_clk_khz, - core_stream->public.timing.h_total, - core_stream->public.timing.v_total, - core_stream->public.timing.pixel_encoding, - core_stream->public.timing.display_color_depth); + stream->timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pixel_encoding, + stream->timing.display_color_depth); dm_logger_write(dm_logger, log_type, "\tsink name: %s, serial: %d\n", - core_stream->sink->edid_caps.display_name, - core_stream->sink->edid_caps.serial_number); + stream->sink->edid_caps.display_name, + stream->sink->edid_caps.serial_number); dm_logger_write(dm_logger, log_type, "\tlink: %d\n", - core_stream->sink->link->link_index); + stream->sink->link->link_index); } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f87f6c12494c..b20f7bfcdc1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -32,6 +32,7 @@ #include "gpio_types.h" #include "link_service_types.h" #include "grph_object_ctrl_defs.h" +#include #define MAX_SURFACES 3 #define MAX_STREAMS 6 @@ -106,12 +107,12 @@ struct dc_cap_funcs { struct dc_stream_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); @@ -120,14 +121,14 @@ struct dc_stream_funcs { const struct dc_stream *stream); bool (*program_csc_matrix)(struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void (*set_static_screen_events)(struct dc *dc, - const struct dc_stream **stream, + struct dc_stream **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(const struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream *stream, enum dc_dither_option option); }; @@ -428,7 +429,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_surface **dc_surfaces, uint8_t surface_count, - const struct dc_stream *stream); + struct dc_stream *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -468,6 +469,18 @@ enum surface_update_type { /******************************************************************************* * Stream Interfaces ******************************************************************************/ + +struct dc_stream_status { + int primary_otg_inst; + int surface_count; + struct dc_surface *surfaces[MAX_SURFACE_NUM]; + + /* + * link this stream passes through + */ + struct dc_link *link; +}; + struct dc_stream { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -495,6 +508,21 @@ struct dc_stream { /* TODO: ABM info (DMCU) */ /* TODO: PSR info */ /* TODO: CEA VIC */ + + /* from core_stream struct */ + struct dc_context *ctx; + + /* used by DCP and FMT */ + struct bit_depth_reduction_params bit_depth_params; + struct clamping_and_pixel_encoding_params clamping; + + int phy_pix_clk; + enum signal_type signal; + + struct dc_stream_status status; + + /* from stream struct */ + int ref_count; }; struct dc_stream_update { @@ -521,7 +549,7 @@ struct dc_stream_update { void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct dc_stream_update *stream_update); /* @@ -554,12 +582,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - const struct dc_stream *stream; + struct dc_stream *stream; struct dc_surface *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); /* * This function takes a set of resources and checks that they are cofunctional. @@ -587,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - const struct dc_stream *stream); + struct dc_stream *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -616,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -625,7 +653,7 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - const struct dc_stream *streams[], + struct dc_stream *streams[], uint8_t stream_count); /** @@ -633,22 +661,11 @@ bool dc_enable_stereo( */ struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(const struct dc_stream *dc_stream); -void dc_stream_release(const struct dc_stream *dc_stream); - -struct dc_stream_status { - int primary_otg_inst; - int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; - - /* - * link this stream passes through - */ - struct dc_link *link; -}; +void dc_stream_retain(struct dc_stream *dc_stream); +void dc_stream_release(struct dc_stream *dc_stream); struct dc_stream_status *dc_stream_get_status( - const struct dc_stream *dc_stream); + struct dc_stream *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -915,7 +932,7 @@ bool dc_stream_set_cursor_attributes( const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - const struct dc_stream *stream, + struct dc_stream *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index aff0a440d4d3..24d0c48258ee 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) + const struct dc_stream *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; @@ -1021,22 +1021,22 @@ bool dce110_link_encoder_validate_output_with_stream( enc110, stream->sink->link->connector_signal, stream->signal, - &stream->public.timing); + &stream->timing); break; case SIGNAL_TYPE_HDMI_TYPE_A: is_valid = dce110_link_encoder_validate_hdmi_output( enc110, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk); break; case SIGNAL_TYPE_DISPLAY_PORT: case SIGNAL_TYPE_DISPLAY_PORT_MST: is_valid = dce110_link_encoder_validate_dp_output( - enc110, &stream->public.timing); + enc110, &stream->timing); break; case SIGNAL_TYPE_EDP: is_valid = - (stream->public.timing. + (stream->timing. pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; break; case SIGNAL_TYPE_VIRTUAL: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index ded6c61304e6..a47b075f4869 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -199,7 +199,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream); + const struct dc_stream *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 3d25a90e49b4..cf98f2471023 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -734,8 +734,8 @@ enum dc_status dce100_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -765,13 +765,13 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 119365960cd0..15f6eeef343d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,21 +623,21 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct output_pixel_processor *opp = pipe_ctx->opp; opp->funcs->opp_power_on_regamma_lut(opp, true); opp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_SRGB); } else if (dce110_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &opp->regamma_params)) { + stream->out_transfer_func, &opp->regamma_params)) { opp->funcs->opp_program_regamma_pwl(opp, &opp->regamma_params); opp->funcs->opp_set_regamma_mode(opp, OPP_REGAMMA_USER); } else { @@ -702,7 +702,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) enum dc_lane_count lane_count = pipe_ctx->stream->sink->link->cur_link_settings.lane_count; - struct dc_crtc_timing *timing = &pipe_ctx->stream->public.timing; + struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct dc_link *link = pipe_ctx->stream->sink->link; /* 1. update AVI info frame (HDMI, DP) @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -797,7 +797,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, /* only 3 items below are used by unblank */ params.pixel_clk_khz = - pipe_ctx->stream->public.timing.pix_clk_khz; + pipe_ctx->stream->timing.pix_clk_khz; params.link_settings.link_rate = link_settings->link_rate; pipe_ctx->stream_enc->funcs->dp_unblank(pipe_ctx->stream_enc, ¶ms); } @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -841,33 +841,33 @@ static void build_audio_output( /* audio_crtc_info */ audio_output->crtc_info.h_total = - stream->public.timing.h_total; + stream->timing.h_total; /* * Audio packets are sent during actual CRTC blank physical signal, we * need to specify actual active signal portion */ audio_output->crtc_info.h_active = - stream->public.timing.h_addressable - + stream->public.timing.h_border_left - + stream->public.timing.h_border_right; + stream->timing.h_addressable + + stream->timing.h_border_left + + stream->timing.h_border_right; audio_output->crtc_info.v_active = - stream->public.timing.v_addressable - + stream->public.timing.v_border_top - + stream->public.timing.v_border_bottom; + stream->timing.v_addressable + + stream->timing.v_border_top + + stream->timing.v_border_bottom; audio_output->crtc_info.pixel_repetition = 1; audio_output->crtc_info.interlaced = - stream->public.timing.flags.INTERLACE; + stream->timing.flags.INTERLACE; audio_output->crtc_info.refresh_rate = - (stream->public.timing.pix_clk_khz*1000)/ - (stream->public.timing.h_total*stream->public.timing.v_total); + (stream->timing.pix_clk_khz*1000)/ + (stream->timing.h_total*stream->timing.v_total); audio_output->crtc_info.color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; audio_output->crtc_info.requested_pixel_clock = pipe_ctx->pix_clk_params.requested_pix_clk; @@ -878,7 +878,7 @@ static void build_audio_output( /*for HDMI, audio ACR is with deep color ratio factor*/ if (dc_is_hdmi_signal(pipe_ctx->stream->signal) && audio_output->crtc_info.requested_pixel_clock == - stream->public.timing.pix_clk_khz) { + stream->timing.pix_clk_khz) { if (pipe_ctx->pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { audio_output->crtc_info.requested_pixel_clock = audio_output->crtc_info.requested_pixel_clock/2; @@ -959,7 +959,7 @@ static void program_scaler(const struct core_dc *dc, get_surface_visual_confirm_color(pipe_ctx, &color); else color_space_to_black_color(dc, - pipe_ctx->stream->public.output_color_space, + pipe_ctx->stream->output_color_space, &color); pipe_ctx->xfm->funcs->transform_set_pixel_storage_depth( @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -990,7 +990,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( /* program blank color */ color_space_to_black_color(dc, - stream->public.output_color_space, &black_color); + stream->output_color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, &black_color); @@ -1011,7 +1011,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->tg->funcs->set_static_screen_control( @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1047,7 +1047,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->opp->funcs->opp_set_dyn_expansion( pipe_ctx->opp, COLOR_SPACE_YCBCR601, - stream->public.timing.display_color_depth, + stream->timing.display_color_depth, pipe_ctx->stream->signal); /* FPGA does not program backend */ @@ -1074,7 +1074,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( pipe_ctx->stream_enc->funcs->setup_stereo_sync( pipe_ctx->stream_enc, pipe_ctx->tg->inst, - stream->public.timing.timing_3d_format != TIMING_3D_FORMAT_NONE); + stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE); /*vbios crtc_source_selection and encoder_setup will override fmt_C*/ @@ -1086,20 +1086,20 @@ static enum dc_status apply_single_controller_ctx_to_hw( if (dc_is_dp_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dp_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, - stream->public.output_color_space); + &stream->timing, + stream->output_color_space); if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->hdmi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, stream->phy_pix_clk, pipe_ctx->audio != NULL); if (dc_is_dvi_signal(pipe_ctx->stream->signal)) pipe_ctx->stream_enc->funcs->dvi_set_stream_attribute( pipe_ctx->stream_enc, - &stream->public.timing, + &stream->timing, (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ? true : false); @@ -1129,9 +1129,9 @@ static enum dc_status apply_single_controller_ctx_to_hw( #endif pipe_ctx->mi->funcs->allocate_mem_input( pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); pipe_ctx->stream->sink->link->psr_enabled = false; @@ -1228,7 +1228,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct core_stream *stream) + const struct dc_stream *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -1236,8 +1236,8 @@ static uint32_t compute_pstate_blackout_duration( pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24; total_dest_line_time_ns = 1000000UL * - stream->public.timing.h_total / - stream->public.timing.pix_clk_khz + + stream->timing.h_total / + stream->timing.pix_clk_khz + pstate_blackout_duration_ns; return total_dest_line_time_ns; @@ -1805,19 +1805,19 @@ enum dc_status dce110_apply_ctx_to_hw( pipe_ctx->stream_enc->funcs->dp_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); else pipe_ctx->stream_enc->funcs->hdmi_audio_setup( pipe_ctx->stream_enc, pipe_ctx->audio->inst, - &pipe_ctx->stream->public.audio_info, + &pipe_ctx->stream->audio_info, &audio_output.crtc_info); pipe_ctx->audio->funcs->az_configure( pipe_ctx->audio, pipe_ctx->stream->signal, &audio_output.crtc_info, - &pipe_ctx->stream->public.audio_info); + &pipe_ctx->stream->audio_info); } status = apply_single_controller_ctx_to_hw( @@ -1862,13 +1862,13 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) default_adjust.out_color_space = COLOR_SPACE_SRGB; else default_adjust.out_color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; default_adjust.surface_pixel_format = pipe_ctx->scl_data.format; /* display color depth */ default_adjust.color_depth = - pipe_ctx->stream->public.timing.display_color_depth; + pipe_ctx->stream->timing.display_color_depth; /* Lb color depth */ default_adjust.lb_color_depth = pipe_ctx->scl_data.lb_params.depth; @@ -1932,35 +1932,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1987,48 +1987,48 @@ static void set_plane_config( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -2260,7 +2260,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct core_stream *stream = context->streams[j]; + const struct dc_stream *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2276,8 +2276,8 @@ void dce110_fill_display_configs( num_cfgs++; cfg->signal = pipe_ctx->stream->signal; cfg->pipe_idx = pipe_ctx->pipe_idx; - cfg->src_height = stream->public.src.height; - cfg->src_width = stream->public.src.width; + cfg->src_height = stream->src.height; + cfg->src_width = stream->src.width; cfg->ddi_channel_mapping = stream->sink->link->ddi_channel_mapping.raw; cfg->transmitter = @@ -2290,10 +2290,10 @@ void dce110_fill_display_configs( stream->sink->link->cur_link_settings.link_spread; cfg->sym_clock = stream->phy_pix_clk; /* Round v_refresh*/ - cfg->v_refresh = stream->public.timing.pix_clk_khz * 1000; - cfg->v_refresh /= stream->public.timing.h_total; - cfg->v_refresh = (cfg->v_refresh + stream->public.timing.v_total / 2) - / stream->public.timing.v_total; + cfg->v_refresh = stream->timing.pix_clk_khz * 1000; + cfg->v_refresh /= stream->timing.h_total; + cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) + / stream->timing.v_total; } pp_display_cfg->display_count = num_cfgs; @@ -2305,7 +2305,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - const struct dc_stream *stream = &context->streams[j]->public; + struct dc_stream *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; @@ -2388,7 +2388,7 @@ static void pplib_apply_display_requirements( /* TODO: is this still applicable?*/ if (pp_display_cfg->display_count == 1) { const struct dc_crtc_timing *timing = - &context->streams[0]->public.timing; + &context->streams[0]->timing; pp_display_cfg->crtc_index = pp_display_cfg->disp_configs[0].pipe_idx; @@ -2441,48 +2441,48 @@ static void dce110_program_front_end_for_pipe( dce_enable_fe_clock(dc->hwseq, pipe_ctx->pipe_idx, true); set_default_colors(pipe_ctx); - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { tbl_entry.color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; for (i = 0; i < 12; i++) tbl_entry.regval[i] = - pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + pipe_ctx->stream->csc_color_matrix.matrix[i]; pipe_ctx->opp->funcs->opp_set_csc_adjustment (pipe_ctx->opp, &tbl_entry); } - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index c773351e93af..cc25c4b6c06f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,13 +718,13 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; + const struct dc_stream *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it * in pll_adjust_pix_clk */ - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -733,15 +733,15 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding == + pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420); - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) { pixel_clk_params->color_depth = COLOR_DEPTH_888; } - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) { pixel_clk_params->requested_pix_clk = pixel_clk_params->requested_pix_clk / 2; } } @@ -755,7 +755,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pll_settings); resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; return DC_OK; } @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -837,9 +837,9 @@ bool dce110_validate_bandwidth( dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION, "%s: %dx%d@%d Bandwidth validation failed!\n", __func__, - context->streams[0]->public.timing.h_addressable, - context->streams[0]->public.timing.v_addressable, - context->streams[0]->public.timing.pix_clk_khz); + context->streams[0]->timing.h_addressable, + context->streams[0]->timing.v_addressable, + context->streams[0]->timing.pix_clk_khz); if (memcmp(&dc->current_context->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { @@ -942,8 +942,8 @@ enum dc_status dce110_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -973,13 +973,13 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; @@ -1041,18 +1041,18 @@ static struct pipe_ctx *dce110_acquire_underlay( */ pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg, - &stream->public.timing, + &stream->timing, false); pipe_ctx->tg->funcs->enable_advanced_request( pipe_ctx->tg, true, - &stream->public.timing); + &stream->timing); pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi, - stream->public.timing.h_total, - stream->public.timing.v_total, - stream->public.timing.pix_clk_khz, + stream->timing.h_total, + stream->timing.v_total, + stream->timing.pix_clk_khz, context->stream_count); color_space_to_black_color(dc, diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 19cd99923b24..9589208ea0c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -698,7 +698,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct core_stream *const stream) + const struct dc_stream *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -729,7 +729,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -843,7 +843,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -916,8 +916,8 @@ enum dc_status dce112_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -947,13 +947,13 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index c6c0bbac5335..cb2c69fb05a6 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 0123006e5360..2fde43c91ad0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -676,7 +676,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -750,8 +750,8 @@ enum dc_status dce80_validate_with_context( return DC_FAIL_SURFACE_VALIDATE; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -780,13 +780,13 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index e738387d8ba3..1531b52e61c2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -684,12 +684,12 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; - bool enableStereo = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? + bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? false:true; - bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY; /* by upper caller loop, pipe0 is parent pipe and be called first. @@ -722,7 +722,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( pipe_ctx->tg->funcs->program_timing( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, true); pipe_ctx->opp->funcs->opp_set_stereo_polarity( @@ -742,7 +742,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( &stream->clamping); #endif /* program otg blank color */ - color_space = stream->public.output_color_space; + color_space = stream->output_color_space; color_space_to_black_color(dc, color_space, &black_color); pipe_ctx->tg->funcs->set_blank_color( pipe_ctx->tg, @@ -1053,16 +1053,16 @@ static bool patch_address_for_sbs_tb_stereo( bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && - (pipe_ctx->stream->public.timing.timing_3d_format == + (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || - pipe_ctx->stream->public.timing.timing_3d_format == + pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { *addr = surface->address.grph_stereo.left_addr; surface->address.grph_stereo.left_addr = surface->address.grph_stereo.right_addr; return true; } else { - if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE && + if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; surface->address.grph_stereo.right_addr = @@ -1456,7 +1456,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream) + const struct dc_stream *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -1465,14 +1465,14 @@ static bool dcn10_set_output_transfer_func( xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; - if (stream->public.out_transfer_func && - stream->public.out_transfer_func->type == + if (stream->out_transfer_func && + stream->out_transfer_func->type == TF_TYPE_PREDEFINED && - stream->public.out_transfer_func->tf == + stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) { xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); } else if (dcn10_translate_regamma_to_hw_format( - stream->public.out_transfer_func, &xfm->regamma_params)) { + stream->out_transfer_func, &xfm->regamma_params)) { xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); } else { @@ -1756,35 +1756,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; - if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) { + if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; adjust.temperature_matrix[0] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[0]; + gamut_remap_matrix.matrix[0]; adjust.temperature_matrix[1] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[1]; + gamut_remap_matrix.matrix[1]; adjust.temperature_matrix[2] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[2]; + gamut_remap_matrix.matrix[2]; adjust.temperature_matrix[3] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[4]; + gamut_remap_matrix.matrix[4]; adjust.temperature_matrix[4] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[5]; + gamut_remap_matrix.matrix[5]; adjust.temperature_matrix[5] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[6]; + gamut_remap_matrix.matrix[6]; adjust.temperature_matrix[6] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[8]; + gamut_remap_matrix.matrix[8]; adjust.temperature_matrix[7] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[9]; + gamut_remap_matrix.matrix[9]; adjust.temperature_matrix[8] = pipe_ctx->stream-> - public.gamut_remap_matrix.matrix[10]; + gamut_remap_matrix.matrix[10]; } pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust); @@ -1798,14 +1798,14 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, int i; struct out_csc_color_matrix tbl_entry; - if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment + if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { enum dc_color_space color_space = - pipe_ctx->stream->public.output_color_space; + pipe_ctx->stream->output_color_space; //uint16_t matrix[12]; for (i = 0; i < 12; i++) - tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i]; + tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; tbl_entry.color_space = color_space; //tbl_entry.regval = matrix; @@ -1967,7 +1967,7 @@ static void update_dchubp_dpp( * pre-multiplied alpha. */ mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace( - pipe_ctx->stream->public.output_color_space) + pipe_ctx->stream->output_color_space) && per_pixel_alpha; pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg); @@ -1975,7 +1975,7 @@ static void update_dchubp_dpp( dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color); } else { color_space_to_black_color( - dc, pipe_ctx->stream->public.output_color_space, + dc, pipe_ctx->stream->output_color_space, &black_color); } pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color); @@ -1991,7 +1991,7 @@ static void update_dchubp_dpp( program_gamut_remap(pipe_ctx); /*TODO add adjustments parameters*/ - ocsc.out_color_space = pipe_ctx->stream->public.output_color_space; + ocsc.out_color_space = pipe_ctx->stream->output_color_space; pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc); mi->funcs->mem_input_program_surface_config( @@ -2346,11 +2346,11 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct core_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream *stream, struct crtc_stereo_flags *flags) { - enum view_3d_format view_format = stream->public.view_format; + enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ - stream->public.timing.timing_3d_format; + stream->timing.timing_3d_format; bool non_stereo_timing = false; if (timing_3d_format == TIMING_3D_FORMAT_NONE || @@ -2374,7 +2374,7 @@ static void dcn10_config_stereo_parameters( flags->DISABLE_STEREO_DP_SYNC = 1; } flags->RIGHT_EYE_POLARITY =\ - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY; + stream->timing.flags.RIGHT_EYE_3D_POLARITY; if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING) flags->FRAME_PACKED = 1; } @@ -2385,18 +2385,18 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct core_stream *stream = pipe_ctx->stream; + struct dc_stream *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); pipe_ctx->opp->funcs->opp_set_stereo_polarity( pipe_ctx->opp, flags.PROGRAM_STEREO == 1 ? true:false, - stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); + stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false); pipe_ctx->tg->funcs->program_stereo( pipe_ctx->tg, - &stream->public.timing, + &stream->timing, &flags); return; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index b901ef9689a6..33beb0bc3ddf 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -787,8 +787,8 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct core_stream *stream = pipe_ctx->stream; - pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz; + const struct dc_stream *stream = pipe_ctx->stream; + pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1; @@ -797,23 +797,23 @@ static void get_pixel_clock_parameters( LINK_RATE_REF_FREQ_IN_KHZ; pixel_clk_params->flags.ENABLE_SS = 0; pixel_clk_params->color_depth = - stream->public.timing.display_color_depth; + stream->timing.display_color_depth; pixel_clk_params->flags.DISPLAY_BLANKED = 1; - pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding; + pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) pixel_clk_params->color_depth = COLOR_DEPTH_888; - if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) + if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) pixel_clk_params->requested_pix_clk /= 2; } -static void build_clamping_params(struct core_stream *stream) +static void build_clamping_params(struct dc_stream *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; - stream->clamping.c_depth = stream->public.timing.display_color_depth; - stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding; + stream->clamping.c_depth = stream->timing.display_color_depth; + stream->clamping.pixel_encoding = stream->timing.pixel_encoding; } static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) @@ -826,7 +826,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) &pipe_ctx->pix_clk_params, &pipe_ctx->pll_settings); - pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding; + pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(pipe_ctx->stream, &pipe_ctx->stream->bit_depth_params); @@ -844,7 +844,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct core_stream *stream = context->streams[i]; + struct dc_stream *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -852,7 +852,7 @@ static enum dc_status build_mapped_resource( resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); stream->clamping.pixel_encoding = - stream->public.timing.pixel_encoding; + stream->timing.pixel_encoding; resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); @@ -896,8 +896,8 @@ enum dc_status dcn10_validate_with_context( return result; for (i = 0; i < set_count; i++) { - context->streams[i] = DC_STREAM_TO_CORE(set[i].stream); - dc_stream_retain(&context->streams[i]->public); + context->streams[i] = set[i].stream; + dc_stream_retain(context->streams[i]); context->stream_count++; } @@ -929,13 +929,13 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; - context->streams[0] = DC_STREAM_TO_CORE(dc_stream); - dc_stream_retain(&context->streams[0]->public); + context->streams[0] = dc_stream; + dc_stream_retain(context->streams[0]); context->stream_count++; result = resource_map_pool_resources(dc, context, NULL); @@ -960,7 +960,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream) + struct dc_stream *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 5a47d4c94df6..2ae5a607fb5a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,41 +36,18 @@ #include "mpc.h" #endif -struct core_stream; - #define MAX_CLOCK_SOURCES 7 void enable_surface_flip_reporting(struct dc_surface *dc_surface, uint32_t controller_id); -/********* core_stream ************/ #include "grph_object_id.h" #include "link_encoder.h" #include "stream_encoder.h" #include "clock_source.h" #include "audio.h" #include "hw_sequencer_types.h" -#include "opp.h" - -#define DC_STREAM_TO_CORE(dc_stream) container_of( \ - dc_stream, struct core_stream, public) - -struct core_stream { - struct dc_stream public; - - /* field internal to DC */ - struct dc_context *ctx; - struct dc_sink *sink; - /* used by DCP and FMT */ - struct bit_depth_reduction_params bit_depth_params; - struct clamping_and_pixel_encoding_params clamping; - - int phy_pix_clk; - enum signal_type signal; - - struct dc_stream_status status; -}; /************ link *****************/ struct link_init_data { @@ -85,7 +62,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct core_stream *stream, + const struct dc_stream *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -117,7 +94,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - const struct dc_stream *stream, + struct dc_stream *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -127,7 +104,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct core_stream *stream); + struct dc_stream *stream); }; struct audio_support{ @@ -178,7 +155,7 @@ struct resource_pool { struct pipe_ctx { struct dc_surface *surface; - struct core_stream *stream; + struct dc_stream *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -264,7 +241,7 @@ union bw_context { }; struct validate_context { - struct core_stream *streams[MAX_PIPES]; + struct dc_stream *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index d9af028a39df..5b4185053e9c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct core_stream; +struct dc_stream; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct core_stream *stream, + struct dc_stream *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 0ee738774f9f..28fb02fb677e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -17,7 +17,6 @@ struct encoder_set_dp_phy_pattern_param; struct link_mst_stream_allocation_table; struct dc_link_settings; struct link_training_settings; -struct core_stream; struct pipe_ctx; struct encoder_init_data { @@ -94,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct core_stream *stream); + struct link_encoder *enc, const struct dc_stream *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index a3eec078dead..b2f7ba2115c9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct core_stream *stream); + const struct dc_stream *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ed94df16a2d3..571bfae62a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - const struct core_stream *stream1, - const struct core_stream *stream2); + struct dc_stream *stream1, + struct dc_stream *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - const struct core_stream *stream); + struct dc_stream *stream); bool resource_attach_surfaces_to_context( struct dc_surface *const *surfaces, int surface_count, - const struct dc_stream *dc_stream, + struct dc_stream *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,10 +130,10 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - const struct validate_context *old_context, const struct core_stream *stream); + struct validate_context *old_context, struct dc_stream *stream); bool is_stream_unchanged( - const struct core_stream *old_stream, const struct core_stream *stream); + struct dc_stream *old_stream, struct dc_stream *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -164,7 +164,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(const struct core_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index d312874d95b5..dd024c99fb7e 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct core_stream *stream) { return true; } + const struct dc_stream *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index a989d5de9f3c..358f8a855a59 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - const struct dc_stream *stream; + struct dc_stream *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index = 0; @@ -244,9 +244,8 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream *stream, struct mod_freesync_caps *caps) { - struct core_stream *core_stream = NULL; struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; int persistent_freesync_enable = 0; @@ -258,7 +257,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, return false; core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync); - core_stream = DC_STREAM_TO_CORE(stream); core_dc = DC_TO_CORE(core_freesync->dc); flag.save_per_edid = true; @@ -315,7 +313,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, if (caps->supported && nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz && nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz) - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; core_freesync->num_entities++; return true; @@ -324,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -346,14 +344,12 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { unsigned int index; struct freesync_context *ctx; - struct core_stream *core_stream; - core_stream = DC_STREAM_TO_CORE(stream); - ctx = &core_stream->public.freesync_ctx; + ctx = &stream->freesync_ctx; index = map_index_from_stream(core_freesync, stream); @@ -372,19 +368,17 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - const struct dc_stream *stream) + struct dc_stream *stream) { - struct core_stream *core_stream = DC_STREAM_TO_CORE(stream); - unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { - core_stream->public.ignore_msa_timing_param = 1; + stream->ignore_msa_timing_param = 1; update_stream_freesync_context(core_freesync, stream); } } static void calc_freesync_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -458,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(const struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -467,7 +461,7 @@ static void calc_v_total_from_duration(const struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -563,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -735,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -845,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -935,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -971,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1023,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1041,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1060,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1113,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1135,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1157,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1185,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams) + struct dc_stream **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1310,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + struct dc_stream *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1409,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index) + struct dc_stream *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1440,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 53c428b97902..2b9d45100bdd 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - const struct dc_stream *stream); + struct dc_stream *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *streams, + struct dc_stream *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - const struct dc_stream *stream, + struct dc_stream *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams); + struct dc_stream **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - const struct dc_stream **streams, int num_streams, + struct dc_stream **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3 From e7b07ceef2a650e5ed8ca37997689e086c680daf Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 10 Aug 2017 13:29:07 -0400 Subject: drm/amd/display: Merge amdgpu_dm_types and amdgpu_dm This separation stopped making sense a long time ago. Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/Makefile | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3245 ++++++++++++++++++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 108 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 - .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 1 - .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.c | 3286 -------------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_types.h | 135 - 8 files changed, 3350 insertions(+), 3430 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c delete mode 100644 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile index 698b1d4f83f5..4699e47aa76b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/Makefile @@ -4,7 +4,7 @@ -AMDGPUDM = amdgpu_dm_types.o amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o +AMDGPUDM = amdgpu_dm.o amdgpu_dm_irq.o amdgpu_dm_mst_types.o ifneq ($(CONFIG_DRM_AMD_DC),) AMDGPUDM += amdgpu_dm_services.o amdgpu_dm_helpers.o diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c802437f4858..646a946a2571 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -31,21 +31,27 @@ #include "amdgpu_display.h" #include "atom.h" #include "amdgpu_dm.h" -#include "amdgpu_dm_types.h" +#include "amdgpu_pm.h" #include "amd_shared.h" #include "amdgpu_dm_irq.h" #include "dm_helpers.h" +#include "dm_services_types.h" +#include "amdgpu_dm_mst_types.h" #include "ivsrcid/ivsrcid_vislands30.h" #include #include #include +#include +#include #include #include #include +#include +#include #include "modules/inc/mod_freesync.h" @@ -59,6 +65,11 @@ #include "soc15_common.h" #endif +#include "modules/inc/mod_freesync.h" + +#include "i2caux_interface.h" + + static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -1552,8 +1563,3238 @@ bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) { - /* TODO */ + /* TODO */ return true; +} + + +struct dm_connector_state { + struct drm_connector_state base; + + enum amdgpu_rmx_type scaling; + uint8_t underscan_vborder; + uint8_t underscan_hborder; + bool underscan_enable; +}; + +#define to_dm_connector_state(x)\ + container_of((x), struct dm_connector_state, base) + +static bool modeset_required(struct drm_crtc_state *crtc_state) +{ + if (!drm_atomic_crtc_needs_modeset(crtc_state)) + return false; + + if (!crtc_state->enable) + return false; + + return crtc_state->active; +} + +static bool modereset_required(struct drm_crtc_state *crtc_state) +{ + if (!drm_atomic_crtc_needs_modeset(crtc_state)) + return false; + + return !crtc_state->enable || !crtc_state->active; +} + +void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) +{ + drm_encoder_cleanup(encoder); + kfree(encoder); +} + +static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { + .destroy = amdgpu_dm_encoder_destroy, +}; + +static void dm_set_cursor( + struct amdgpu_crtc *amdgpu_crtc, + uint64_t gpu_addr, + uint32_t width, + uint32_t height) +{ + struct dc_cursor_attributes attributes; + struct dc_cursor_position position; + struct drm_crtc *crtc = &amdgpu_crtc->base; + int x, y; + int xorigin = 0, yorigin = 0; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + + amdgpu_crtc->cursor_width = width; + amdgpu_crtc->cursor_height = height; + + attributes.address.high_part = upper_32_bits(gpu_addr); + attributes.address.low_part = lower_32_bits(gpu_addr); + attributes.width = width; + attributes.height = height; + attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; + attributes.rotation_angle = 0; + attributes.attribute_flags.value = 0; + + attributes.pitch = attributes.width; + + x = amdgpu_crtc->cursor_x; + y = amdgpu_crtc->cursor_y; + + /* avivo cursor are offset into the total surface */ + x += crtc->primary->state->src_x >> 16; + y += crtc->primary->state->src_y >> 16; + + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + + position.enable = true; + position.x = x; + position.y = y; + + position.x_hotspot = xorigin; + position.y_hotspot = yorigin; + + if (!dc_stream_set_cursor_attributes( + acrtc_state->stream, + &attributes)) { + DRM_ERROR("DC failed to set cursor attributes\n"); + } + + if (!dc_stream_set_cursor_position( + acrtc_state->stream, + &position)) { + DRM_ERROR("DC failed to set cursor position\n"); + } +} + +static int dm_crtc_cursor_set( + struct drm_crtc *crtc, + uint64_t address, + uint32_t width, + uint32_t height) +{ + struct dc_cursor_position position; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + + int ret; + + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + ret = EINVAL; + + DRM_DEBUG_KMS( + "%s: crtc_id=%d with size %d to %d \n", + __func__, + amdgpu_crtc->crtc_id, + width, + height); + + if (!address) { + /* turn off cursor */ + position.enable = false; + position.x = 0; + position.y = 0; + + if (acrtc_state->stream) { + /*set cursor visible false*/ + dc_stream_set_cursor_position( + acrtc_state->stream, + &position); + } + goto release; + + } + + if ((width > amdgpu_crtc->max_cursor_width) || + (height > amdgpu_crtc->max_cursor_height)) { + DRM_ERROR( + "%s: bad cursor width or height %d x %d\n", + __func__, + width, + height); + goto release; + } + + /*program new cursor bo to hardware*/ + dm_set_cursor(amdgpu_crtc, address, width, height); + +release: + return ret; + +} + +static int dm_crtc_cursor_move(struct drm_crtc *crtc, + int x, int y) +{ + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + int xorigin = 0, yorigin = 0; + struct dc_cursor_position position; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + + amdgpu_crtc->cursor_x = x; + amdgpu_crtc->cursor_y = y; + + /* avivo cursor are offset into the total surface */ + x += crtc->primary->state->src_x >> 16; + y += crtc->primary->state->src_y >> 16; + + /* + * TODO: for cursor debugging unguard the following + */ +#if 0 + DRM_DEBUG_KMS( + "%s: x %d y %d c->x %d c->y %d\n", + __func__, + x, + y, + crtc->x, + crtc->y); +#endif + + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + + position.enable = true; + position.x = x; + position.y = y; + + position.x_hotspot = xorigin; + position.y_hotspot = yorigin; + + if (acrtc_state->stream) { + if (!dc_stream_set_cursor_position( + acrtc_state->stream, + &position)) { + DRM_ERROR("DC failed to set cursor position\n"); + return -EINVAL; + } + } + + return 0; +} + +static bool fill_rects_from_plane_state( + const struct drm_plane_state *state, + struct dc_surface *surface) +{ + surface->src_rect.x = state->src_x >> 16; + surface->src_rect.y = state->src_y >> 16; + /*we ignore for now mantissa and do not to deal with floating pixels :(*/ + surface->src_rect.width = state->src_w >> 16; + + if (surface->src_rect.width == 0) + return false; + + surface->src_rect.height = state->src_h >> 16; + if (surface->src_rect.height == 0) + return false; + + surface->dst_rect.x = state->crtc_x; + surface->dst_rect.y = state->crtc_y; + + if (state->crtc_w == 0) + return false; + + surface->dst_rect.width = state->crtc_w; + + if (state->crtc_h == 0) + return false; + + surface->dst_rect.height = state->crtc_h; + + surface->clip_rect = surface->dst_rect; + + switch (state->rotation & DRM_MODE_ROTATE_MASK) { + case DRM_MODE_ROTATE_0: + surface->rotation = ROTATION_ANGLE_0; + break; + case DRM_MODE_ROTATE_90: + surface->rotation = ROTATION_ANGLE_90; + break; + case DRM_MODE_ROTATE_180: + surface->rotation = ROTATION_ANGLE_180; + break; + case DRM_MODE_ROTATE_270: + surface->rotation = ROTATION_ANGLE_270; + break; + default: + surface->rotation = ROTATION_ANGLE_0; + break; + } + return true; } +static int get_fb_info( + const struct amdgpu_framebuffer *amdgpu_fb, + uint64_t *tiling_flags, + uint64_t *fb_location) +{ + struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); + int r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) { + DRM_ERROR("Unable to reserve buffer\n"); + return r; + } + + if (fb_location) + *fb_location = amdgpu_bo_gpu_offset(rbo); + + if (tiling_flags) + amdgpu_bo_get_tiling_flags(rbo, tiling_flags); + + amdgpu_bo_unreserve(rbo); + + return r; +} + +static int fill_plane_attributes_from_fb( + struct amdgpu_device *adev, + struct dc_surface *surface, + const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) +{ + uint64_t tiling_flags; + uint64_t fb_location = 0; + unsigned int awidth; + const struct drm_framebuffer *fb = &amdgpu_fb->base; + int ret = 0; + struct drm_format_name_buf format_name; + + ret = get_fb_info( + amdgpu_fb, + &tiling_flags, + addReq == true ? &fb_location:NULL); + + if (ret) + return ret; + + switch (fb->format->format) { + case DRM_FORMAT_C8: + surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; + break; + case DRM_FORMAT_RGB565: + surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; + break; + case DRM_FORMAT_XRGB8888: + case DRM_FORMAT_ARGB8888: + surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; + break; + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; + break; + case DRM_FORMAT_XBGR2101010: + case DRM_FORMAT_ABGR2101010: + surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; + break; + case DRM_FORMAT_NV21: + surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; + break; + case DRM_FORMAT_NV12: + surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; + break; + default: + DRM_ERROR("Unsupported screen format %s\n", + drm_get_format_name(fb->format->format, &format_name)); + return -EINVAL; + } + + if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + surface->address.type = PLN_ADDR_TYPE_GRAPHICS; + surface->address.grph.addr.low_part = lower_32_bits(fb_location); + surface->address.grph.addr.high_part = upper_32_bits(fb_location); + surface->plane_size.grph.surface_size.x = 0; + surface->plane_size.grph.surface_size.y = 0; + surface->plane_size.grph.surface_size.width = fb->width; + surface->plane_size.grph.surface_size.height = fb->height; + surface->plane_size.grph.surface_pitch = + fb->pitches[0] / fb->format->cpp[0]; + /* TODO: unhardcode */ + surface->color_space = COLOR_SPACE_SRGB; + + } else { + awidth = ALIGN(fb->width, 64); + surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; + surface->address.video_progressive.luma_addr.low_part + = lower_32_bits(fb_location); + surface->address.video_progressive.chroma_addr.low_part + = lower_32_bits(fb_location) + + (awidth * fb->height); + surface->plane_size.video.luma_size.x = 0; + surface->plane_size.video.luma_size.y = 0; + surface->plane_size.video.luma_size.width = awidth; + surface->plane_size.video.luma_size.height = fb->height; + /* TODO: unhardcode */ + surface->plane_size.video.luma_pitch = awidth; + + surface->plane_size.video.chroma_size.x = 0; + surface->plane_size.video.chroma_size.y = 0; + surface->plane_size.video.chroma_size.width = awidth; + surface->plane_size.video.chroma_size.height = fb->height; + surface->plane_size.video.chroma_pitch = awidth / 2; + + /* TODO: unhardcode */ + surface->color_space = COLOR_SPACE_YCBCR709; + } + + memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); + + /* Fill GFX params */ + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) + { + unsigned bankw, bankh, mtaspect, tile_split, num_banks; + + bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); + bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); + mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); + tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); + num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); + + /* XXX fix me for VI */ + surface->tiling_info.gfx8.num_banks = num_banks; + surface->tiling_info.gfx8.array_mode = + DC_ARRAY_2D_TILED_THIN1; + surface->tiling_info.gfx8.tile_split = tile_split; + surface->tiling_info.gfx8.bank_width = bankw; + surface->tiling_info.gfx8.bank_height = bankh; + surface->tiling_info.gfx8.tile_aspect = mtaspect; + surface->tiling_info.gfx8.tile_mode = + DC_ADDR_SURF_MICRO_TILING_DISPLAY; + } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) + == DC_ARRAY_1D_TILED_THIN1) { + surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; + } + + surface->tiling_info.gfx8.pipe_config = + AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); + + if (adev->asic_type == CHIP_VEGA10 || + adev->asic_type == CHIP_RAVEN) { + /* Fill GFX9 params */ + surface->tiling_info.gfx9.num_pipes = + adev->gfx.config.gb_addr_config_fields.num_pipes; + surface->tiling_info.gfx9.num_banks = + adev->gfx.config.gb_addr_config_fields.num_banks; + surface->tiling_info.gfx9.pipe_interleave = + adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; + surface->tiling_info.gfx9.num_shader_engines = + adev->gfx.config.gb_addr_config_fields.num_se; + surface->tiling_info.gfx9.max_compressed_frags = + adev->gfx.config.gb_addr_config_fields.max_compress_frags; + surface->tiling_info.gfx9.num_rb_per_se = + adev->gfx.config.gb_addr_config_fields.num_rb_per_se; + surface->tiling_info.gfx9.swizzle = + AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); + surface->tiling_info.gfx9.shaderEnable = 1; + } + + surface->visible = true; + surface->scaling_quality.h_taps_c = 0; + surface->scaling_quality.v_taps_c = 0; + + /* is this needed? is surface zeroed at allocation? */ + surface->scaling_quality.h_taps = 0; + surface->scaling_quality.v_taps = 0; + surface->stereo_format = PLANE_STEREO_FORMAT_NONE; + + return ret; + +} + +#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256 + +static void fill_gamma_from_crtc_state( + const struct drm_crtc_state *crtc_state, + struct dc_surface *dc_surface) +{ + int i; + struct dc_gamma *gamma; + struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data; + + gamma = dc_create_gamma(); + + if (gamma == NULL) { + WARN_ON(1); + return; + } + + for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) { + gamma->red[i] = lut[i].red; + gamma->green[i] = lut[i].green; + gamma->blue[i] = lut[i].blue; + } + + dc_surface->gamma_correction = gamma; +} + +static int fill_plane_attributes( + struct amdgpu_device *adev, + struct dc_surface *surface, + struct drm_plane_state *plane_state, + struct drm_crtc_state *crtc_state, + bool addrReq) +{ + const struct amdgpu_framebuffer *amdgpu_fb = + to_amdgpu_framebuffer(plane_state->fb); + const struct drm_crtc *crtc = plane_state->crtc; + struct dc_transfer_func *input_tf; + int ret = 0; + + if (!fill_rects_from_plane_state(plane_state, surface)) + return -EINVAL; + + ret = fill_plane_attributes_from_fb( + crtc->dev->dev_private, + surface, + amdgpu_fb, + addrReq); + + if (ret) + return ret; + + input_tf = dc_create_transfer_func(); + + if (input_tf == NULL) + return -ENOMEM; + + input_tf->type = TF_TYPE_PREDEFINED; + input_tf->tf = TRANSFER_FUNCTION_SRGB; + + surface->in_transfer_func = input_tf; + + /* In case of gamma set, update gamma value */ + if (crtc_state->gamma_lut) + fill_gamma_from_crtc_state(crtc_state, surface); + + return ret; +} + +/*****************************************************************************/ + +struct amdgpu_connector *aconnector_from_drm_crtc_id( + const struct drm_crtc *crtc) +{ + struct drm_device *dev = crtc->dev; + struct drm_connector *connector; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_connector *aconnector; + + list_for_each_entry(connector, + &dev->mode_config.connector_list, head) { + + aconnector = to_amdgpu_connector(connector); + + if (aconnector->base.state->crtc != &acrtc->base) + continue; + + /* Found the connector */ + return aconnector; + } + + /* If we get here, not found. */ + return NULL; +} + +static void update_stream_scaling_settings( + const struct drm_display_mode *mode, + const struct dm_connector_state *dm_state, + struct dc_stream *stream) +{ + enum amdgpu_rmx_type rmx_type; + + struct rect src = { 0 }; /* viewport in composition space*/ + struct rect dst = { 0 }; /* stream addressable area */ + + /* no mode. nothing to be done */ + if (!mode) + return; + + /* Full screen scaling by default */ + src.width = mode->hdisplay; + src.height = mode->vdisplay; + dst.width = stream->timing.h_addressable; + dst.height = stream->timing.v_addressable; + + rmx_type = dm_state->scaling; + if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { + if (src.width * dst.height < + src.height * dst.width) { + /* height needs less upscaling/more downscaling */ + dst.width = src.width * + dst.height / src.height; + } else { + /* width needs less upscaling/more downscaling */ + dst.height = src.height * + dst.width / src.width; + } + } else if (rmx_type == RMX_CENTER) { + dst = src; + } + + dst.x = (stream->timing.h_addressable - dst.width) / 2; + dst.y = (stream->timing.v_addressable - dst.height) / 2; + + if (dm_state->underscan_enable) { + dst.x += dm_state->underscan_hborder / 2; + dst.y += dm_state->underscan_vborder / 2; + dst.width -= dm_state->underscan_hborder; + dst.height -= dm_state->underscan_vborder; + } + + stream->src = src; + stream->dst = dst; + + DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", + dst.x, dst.y, dst.width, dst.height); + +} + +static enum dc_color_depth convert_color_depth_from_display_info( + const struct drm_connector *connector) +{ + uint32_t bpc = connector->display_info.bpc; + + /* Limited color depth to 8bit + * TODO: Still need to handle deep color*/ + if (bpc > 8) + bpc = 8; + + switch (bpc) { + case 0: + /* Temporary Work around, DRM don't parse color depth for + * EDID revision before 1.4 + * TODO: Fix edid parsing + */ + return COLOR_DEPTH_888; + case 6: + return COLOR_DEPTH_666; + case 8: + return COLOR_DEPTH_888; + case 10: + return COLOR_DEPTH_101010; + case 12: + return COLOR_DEPTH_121212; + case 14: + return COLOR_DEPTH_141414; + case 16: + return COLOR_DEPTH_161616; + default: + return COLOR_DEPTH_UNDEFINED; + } +} + +static enum dc_aspect_ratio get_aspect_ratio( + const struct drm_display_mode *mode_in) +{ + int32_t width = mode_in->crtc_hdisplay * 9; + int32_t height = mode_in->crtc_vdisplay * 16; + if ((width - height) < 10 && (width - height) > -10) + return ASPECT_RATIO_16_9; + else + return ASPECT_RATIO_4_3; +} + +static enum dc_color_space get_output_color_space( + const struct dc_crtc_timing *dc_crtc_timing) +{ + enum dc_color_space color_space = COLOR_SPACE_SRGB; + + switch (dc_crtc_timing->pixel_encoding) { + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR420: + { + /* + * 27030khz is the separation point between HDTV and SDTV + * according to HDMI spec, we use YCbCr709 and YCbCr601 + * respectively + */ + if (dc_crtc_timing->pix_clk_khz > 27030) { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR709_LIMITED; + else + color_space = COLOR_SPACE_YCBCR709; + } else { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR601_LIMITED; + else + color_space = COLOR_SPACE_YCBCR601; + } + + } + break; + case PIXEL_ENCODING_RGB: + color_space = COLOR_SPACE_SRGB; + break; + + default: + WARN_ON(1); + break; + } + + return color_space; +} + +/*****************************************************************************/ + +static void fill_stream_properties_from_drm_display_mode( + struct dc_stream *stream, + const struct drm_display_mode *mode_in, + const struct drm_connector *connector) +{ + struct dc_crtc_timing *timing_out = &stream->timing; + memset(timing_out, 0, sizeof(struct dc_crtc_timing)); + + timing_out->h_border_left = 0; + timing_out->h_border_right = 0; + timing_out->v_border_top = 0; + timing_out->v_border_bottom = 0; + /* TODO: un-hardcode */ + + if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) + && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; + else + timing_out->pixel_encoding = PIXEL_ENCODING_RGB; + + timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; + timing_out->display_color_depth = convert_color_depth_from_display_info( + connector); + timing_out->scan_type = SCANNING_TYPE_NODATA; + timing_out->hdmi_vic = 0; + timing_out->vic = drm_match_cea_mode(mode_in); + + timing_out->h_addressable = mode_in->crtc_hdisplay; + timing_out->h_total = mode_in->crtc_htotal; + timing_out->h_sync_width = + mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; + timing_out->h_front_porch = + mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; + timing_out->v_total = mode_in->crtc_vtotal; + timing_out->v_addressable = mode_in->crtc_vdisplay; + timing_out->v_front_porch = + mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; + timing_out->v_sync_width = + mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; + timing_out->pix_clk_khz = mode_in->crtc_clock; + timing_out->aspect_ratio = get_aspect_ratio(mode_in); + if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) + timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; + if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) + timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; + + stream->output_color_space = get_output_color_space(timing_out); + + { + struct dc_transfer_func *tf = dc_create_transfer_func(); + tf->type = TF_TYPE_PREDEFINED; + tf->tf = TRANSFER_FUNCTION_SRGB; + stream->out_transfer_func = tf; + } +} + +static void fill_audio_info( + struct audio_info *audio_info, + const struct drm_connector *drm_connector, + const struct dc_sink *dc_sink) +{ + int i = 0; + int cea_revision = 0; + const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; + + audio_info->manufacture_id = edid_caps->manufacturer_id; + audio_info->product_id = edid_caps->product_id; + + cea_revision = drm_connector->display_info.cea_rev; + + while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS && + edid_caps->display_name[i]) { + audio_info->display_name[i] = edid_caps->display_name[i]; + i++; + } + + if(cea_revision >= 3) { + audio_info->mode_count = edid_caps->audio_mode_count; + + for (i = 0; i < audio_info->mode_count; ++i) { + audio_info->modes[i].format_code = + (enum audio_format_code) + (edid_caps->audio_modes[i].format_code); + audio_info->modes[i].channel_count = + edid_caps->audio_modes[i].channel_count; + audio_info->modes[i].sample_rates.all = + edid_caps->audio_modes[i].sample_rate; + audio_info->modes[i].sample_size = + edid_caps->audio_modes[i].sample_size; + } + } + + audio_info->flags.all = edid_caps->speaker_flags; + + /* TODO: We only check for the progressive mode, check for interlace mode too */ + if(drm_connector->latency_present[0]) { + audio_info->video_latency = drm_connector->video_latency[0]; + audio_info->audio_latency = drm_connector->audio_latency[0]; + } + + /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ + +} + +static void copy_crtc_timing_for_drm_display_mode( + const struct drm_display_mode *src_mode, + struct drm_display_mode *dst_mode) +{ + dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; + dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; + dst_mode->crtc_clock = src_mode->crtc_clock; + dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; + dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; + dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start; + dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; + dst_mode->crtc_htotal = src_mode->crtc_htotal; + dst_mode->crtc_hskew = src_mode->crtc_hskew; + dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; + dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; + dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; + dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; + dst_mode->crtc_vtotal = src_mode->crtc_vtotal; +} + +static void decide_crtc_timing_for_drm_display_mode( + struct drm_display_mode *drm_mode, + const struct drm_display_mode *native_mode, + bool scale_enabled) +{ + if (scale_enabled) { + copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); + } else if (native_mode->clock == drm_mode->clock && + native_mode->htotal == drm_mode->htotal && + native_mode->vtotal == drm_mode->vtotal) { + copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); + } else { + /* no scaling nor amdgpu inserted, no need to patch */ + } +} + +static struct dc_stream *create_stream_for_sink( + struct amdgpu_connector *aconnector, + const struct drm_display_mode *drm_mode, + const struct dm_connector_state *dm_state) +{ + struct drm_display_mode *preferred_mode = NULL; + const struct drm_connector *drm_connector; + struct dc_stream *stream = NULL; + struct drm_display_mode mode = *drm_mode; + bool native_mode_found = false; + + if (NULL == aconnector) { + DRM_ERROR("aconnector is NULL!\n"); + goto drm_connector_null; + } + + if (NULL == dm_state) { + DRM_ERROR("dm_state is NULL!\n"); + goto dm_state_null; + } + drm_connector = &aconnector->base; + stream = dc_create_stream_for_sink(aconnector->dc_sink); + if (NULL == stream) { + DRM_ERROR("Failed to create stream for sink!\n"); + goto stream_create_fail; + } + + list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { + /* Search for preferred mode */ + if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { + native_mode_found = true; + break; + } + } + if (!native_mode_found) + preferred_mode = list_first_entry_or_null( + &aconnector->base.modes, + struct drm_display_mode, + head); + + if (NULL == preferred_mode) { + /* This may not be an error, the use case is when we we have no + * usermode calls to reset and set mode upon hotplug. In this + * case, we call set mode ourselves to restore the previous mode + * and the modelist may not be filled in in time. + */ + DRM_INFO("No preferred mode found\n"); + } else { + decide_crtc_timing_for_drm_display_mode( + &mode, preferred_mode, + dm_state->scaling != RMX_OFF); + } + + fill_stream_properties_from_drm_display_mode(stream, + &mode, &aconnector->base); + update_stream_scaling_settings(&mode, dm_state, stream); + + fill_audio_info( + &stream->audio_info, + drm_connector, + aconnector->dc_sink); + +stream_create_fail: +dm_state_null: +drm_connector_null: + return stream; +} + +void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) +{ + drm_crtc_cleanup(crtc); + kfree(crtc); +} + +static void dm_crtc_destroy_state(struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct dm_crtc_state *cur = to_dm_crtc_state(state); + + /* TODO Destroy dc_stream objects are stream object is flattened */ + if (cur->stream) + dc_stream_release(cur->stream); + + + __drm_atomic_helper_crtc_destroy_state(state); + + + kfree(state); +} + +static void dm_crtc_reset_state(struct drm_crtc *crtc) +{ + struct dm_crtc_state *state; + + if (crtc->state) + dm_crtc_destroy_state(crtc, crtc->state); + + state = kzalloc(sizeof(*state), GFP_KERNEL); + if (WARN_ON(!state)) + return; + + crtc->state = &state->base; + crtc->state->crtc = crtc; + +} + +static struct drm_crtc_state * +dm_crtc_duplicate_state(struct drm_crtc *crtc) +{ + struct dm_crtc_state *state, *cur; + + cur = to_dm_crtc_state(crtc->state); + + if (WARN_ON(!crtc->state)) + return NULL; + + state = dm_alloc(sizeof(*state)); + + __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); + + if (cur->stream) { + state->stream = cur->stream; + dc_stream_retain(state->stream); + } + + /* TODO Duplicate dc_stream after objects are stream object is flattened */ + + return &state->base; +} + +/* Implemented only the options currently availible for the driver */ +static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { + .reset = dm_crtc_reset_state, + .destroy = amdgpu_dm_crtc_destroy, + .gamma_set = drm_atomic_helper_legacy_gamma_set, + .set_config = drm_atomic_helper_set_config, + .page_flip = drm_atomic_helper_page_flip, + .atomic_duplicate_state = dm_crtc_duplicate_state, + .atomic_destroy_state = dm_crtc_destroy_state, +}; + +static enum drm_connector_status +amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) +{ + bool connected; + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + + /* Notes: + * 1. This interface is NOT called in context of HPD irq. + * 2. This interface *is called* in context of user-mode ioctl. Which + * makes it a bad place for *any* MST-related activit. */ + + if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) + connected = (aconnector->dc_sink != NULL); + else + connected = (aconnector->base.force == DRM_FORCE_ON); + + return (connected ? connector_status_connected : + connector_status_disconnected); +} + +int amdgpu_dm_connector_atomic_set_property( + struct drm_connector *connector, + struct drm_connector_state *connector_state, + struct drm_property *property, + uint64_t val) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct dm_connector_state *dm_old_state = + to_dm_connector_state(connector->state); + struct dm_connector_state *dm_new_state = + to_dm_connector_state(connector_state); + + int ret = -EINVAL; + + if (property == dev->mode_config.scaling_mode_property) { + enum amdgpu_rmx_type rmx_type; + + switch (val) { + case DRM_MODE_SCALE_CENTER: + rmx_type = RMX_CENTER; + break; + case DRM_MODE_SCALE_ASPECT: + rmx_type = RMX_ASPECT; + break; + case DRM_MODE_SCALE_FULLSCREEN: + rmx_type = RMX_FULL; + break; + case DRM_MODE_SCALE_NONE: + default: + rmx_type = RMX_OFF; + break; + } + + if (dm_old_state->scaling == rmx_type) + return 0; + + dm_new_state->scaling = rmx_type; + ret = 0; + } else if (property == adev->mode_info.underscan_hborder_property) { + dm_new_state->underscan_hborder = val; + ret = 0; + } else if (property == adev->mode_info.underscan_vborder_property) { + dm_new_state->underscan_vborder = val; + ret = 0; + } else if (property == adev->mode_info.underscan_property) { + dm_new_state->underscan_enable = val; + ret = 0; + } + + return ret; +} + +int amdgpu_dm_connector_atomic_get_property( + struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + struct dm_connector_state *dm_state = + to_dm_connector_state(state); + int ret = -EINVAL; + + if (property == dev->mode_config.scaling_mode_property) { + switch (dm_state->scaling) { + case RMX_CENTER: + *val = DRM_MODE_SCALE_CENTER; + break; + case RMX_ASPECT: + *val = DRM_MODE_SCALE_ASPECT; + break; + case RMX_FULL: + *val = DRM_MODE_SCALE_FULLSCREEN; + break; + case RMX_OFF: + default: + *val = DRM_MODE_SCALE_NONE; + break; + } + ret = 0; + } else if (property == adev->mode_info.underscan_hborder_property) { + *val = dm_state->underscan_hborder; + ret = 0; + } else if (property == adev->mode_info.underscan_vborder_property) { + *val = dm_state->underscan_vborder; + ret = 0; + } else if (property == adev->mode_info.underscan_property) { + *val = dm_state->underscan_enable; + ret = 0; + } + return ret; +} + +void amdgpu_dm_connector_destroy(struct drm_connector *connector) +{ + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + const struct dc_link *link = aconnector->dc_link; + struct amdgpu_device *adev = connector->dev->dev_private; + struct amdgpu_display_manager *dm = &adev->dm; +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ + defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + + if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) { + amdgpu_dm_register_backlight_device(dm); + + if (dm->backlight_dev) { + backlight_device_unregister(dm->backlight_dev); + dm->backlight_dev = NULL; + } + + } +#endif + drm_connector_unregister(connector); + drm_connector_cleanup(connector); + kfree(connector); +} + +void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) +{ + struct dm_connector_state *state = + to_dm_connector_state(connector->state); + + kfree(state); + + state = kzalloc(sizeof(*state), GFP_KERNEL); + + if (state) { + state->scaling = RMX_OFF; + state->underscan_enable = false; + state->underscan_hborder = 0; + state->underscan_vborder = 0; + + connector->state = &state->base; + connector->state->connector = connector; + } +} + +struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( + struct drm_connector *connector) +{ + struct dm_connector_state *state = + to_dm_connector_state(connector->state); + + struct dm_connector_state *new_state = + kmemdup(state, sizeof(*state), GFP_KERNEL); + + if (new_state) { + __drm_atomic_helper_connector_duplicate_state(connector, + &new_state->base); + return &new_state->base; + } + + return NULL; +} + +static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { + .reset = amdgpu_dm_connector_funcs_reset, + .detect = amdgpu_dm_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = amdgpu_dm_connector_destroy, + .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, + .atomic_set_property = amdgpu_dm_connector_atomic_set_property, + .atomic_get_property = amdgpu_dm_connector_atomic_get_property +}; + +static struct drm_encoder *best_encoder(struct drm_connector *connector) +{ + int enc_id = connector->encoder_ids[0]; + struct drm_mode_object *obj; + struct drm_encoder *encoder; + + DRM_DEBUG_KMS("Finding the best encoder\n"); + + /* pick the encoder ids */ + if (enc_id) { + obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER); + if (!obj) { + DRM_ERROR("Couldn't find a matching encoder for our connector\n"); + return NULL; + } + encoder = obj_to_encoder(obj); + return encoder; + } + DRM_ERROR("No encoder id\n"); + return NULL; +} + +static int get_modes(struct drm_connector *connector) +{ + return amdgpu_dm_connector_get_modes(connector); +} + +static void create_eml_sink(struct amdgpu_connector *aconnector) +{ + struct dc_sink_init_data init_params = { + .link = aconnector->dc_link, + .sink_signal = SIGNAL_TYPE_VIRTUAL + }; + struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data; + + if (!aconnector->base.edid_blob_ptr || + !aconnector->base.edid_blob_ptr->data) { + DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", + aconnector->base.name); + + aconnector->base.force = DRM_FORCE_OFF; + aconnector->base.override_edid = false; + return; + } + + aconnector->edid = edid; + + aconnector->dc_em_sink = dc_link_add_remote_sink( + aconnector->dc_link, + (uint8_t *)edid, + (edid->extensions + 1) * EDID_LENGTH, + &init_params); + + if (aconnector->base.force + == DRM_FORCE_ON) + aconnector->dc_sink = aconnector->dc_link->local_sink ? + aconnector->dc_link->local_sink : + aconnector->dc_em_sink; +} + +static void handle_edid_mgmt(struct amdgpu_connector *aconnector) +{ + struct dc_link *link = (struct dc_link *)aconnector->dc_link; + + /* In case of headless boot with force on for DP managed connector + * Those settings have to be != 0 to get initial modeset + */ + if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { + link->verified_link_cap.lane_count = LANE_COUNT_FOUR; + link->verified_link_cap.link_rate = LINK_RATE_HIGH2; + } + + + aconnector->base.override_edid = true; + create_eml_sink(aconnector); +} + +int amdgpu_dm_connector_mode_valid( + struct drm_connector *connector, + struct drm_display_mode *mode) +{ + int result = MODE_ERROR; + struct dc_sink *dc_sink; + struct amdgpu_device *adev = connector->dev->dev_private; + /* TODO: Unhardcode stream count */ + struct dc_stream *stream; + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + + if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || + (mode->flags & DRM_MODE_FLAG_DBLSCAN)) + return result; + + /* Only run this the first time mode_valid is called to initilialize + * EDID mgmt + */ + if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && + !aconnector->dc_em_sink) + handle_edid_mgmt(aconnector); + + dc_sink = to_amdgpu_connector(connector)->dc_sink; + + if (NULL == dc_sink) { + DRM_ERROR("dc_sink is NULL!\n"); + goto fail; + } + + stream = dc_create_stream_for_sink(dc_sink); + if (NULL == stream) { + DRM_ERROR("Failed to create stream for sink!\n"); + goto fail; + } + + drm_mode_set_crtcinfo(mode, 0); + fill_stream_properties_from_drm_display_mode(stream, mode, connector); + + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; + + if (dc_validate_stream(adev->dm.dc, stream)) + result = MODE_OK; + + dc_stream_release(stream); + +fail: + /* TODO: error handling*/ + return result; +} + +static const struct drm_connector_helper_funcs +amdgpu_dm_connector_helper_funcs = { + /* + * If hotplug a second bigger display in FB Con mode, bigger resolution + * modes will be filtered by drm_mode_validate_size(), and those modes + * is missing after user start lightdm. So we need to renew modes list. + * in get_modes call back, not just return the modes count + */ + .get_modes = get_modes, + .mode_valid = amdgpu_dm_connector_mode_valid, + .best_encoder = best_encoder +}; + +static void dm_crtc_helper_disable(struct drm_crtc *crtc) +{ +} + +static int dm_crtc_helper_atomic_check( + struct drm_crtc *crtc, + struct drm_crtc_state *state) +{ + struct amdgpu_device *adev = crtc->dev->dev_private; + struct dc *dc = adev->dm.dc; + struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); + int ret = -EINVAL; + + if (unlikely(!dm_crtc_state->stream && modeset_required(state))) { + WARN_ON(1); + return ret; + } + + /* In some use cases, like reset, no stream is attached */ + if (!dm_crtc_state->stream) + return 0; + + if (dc_validate_stream(dc, dm_crtc_state->stream)) + return 0; + + return ret; +} + +static bool dm_crtc_helper_mode_fixup( + struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) +{ + return true; +} + +static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { + .disable = dm_crtc_helper_disable, + .atomic_check = dm_crtc_helper_atomic_check, + .mode_fixup = dm_crtc_helper_mode_fixup +}; + +static void dm_encoder_helper_disable(struct drm_encoder *encoder) +{ + +} + +static int dm_encoder_helper_atomic_check( + struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + return 0; +} + +const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { + .disable = dm_encoder_helper_disable, + .atomic_check = dm_encoder_helper_atomic_check +}; + +static void dm_drm_plane_reset(struct drm_plane *plane) +{ + struct dm_plane_state *amdgpu_state = NULL; + + if (plane->state) + plane->funcs->atomic_destroy_state(plane, plane->state); + + amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); + + if (amdgpu_state) { + plane->state = &amdgpu_state->base; + plane->state->plane = plane; + plane->state->rotation = DRM_MODE_ROTATE_0; + } else + WARN_ON(1); +} + +static struct drm_plane_state * +dm_drm_plane_duplicate_state(struct drm_plane *plane) +{ + struct dm_plane_state *dm_plane_state, *old_dm_plane_state; + + old_dm_plane_state = to_dm_plane_state(plane->state); + dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); + if (!dm_plane_state) + return NULL; + + __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); + + if (old_dm_plane_state->surface) { + dm_plane_state->surface = old_dm_plane_state->surface; + dc_surface_retain(dm_plane_state->surface); + } + + return &dm_plane_state->base; +} + +void dm_drm_plane_destroy_state(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + + if (dm_plane_state->surface) + dc_surface_release(dm_plane_state->surface); + + __drm_atomic_helper_plane_destroy_state(state); + kfree(dm_plane_state); +} + +static const struct drm_plane_funcs dm_plane_funcs = { + .update_plane = drm_atomic_helper_update_plane, + .disable_plane = drm_atomic_helper_disable_plane, + .destroy = drm_plane_cleanup, + .reset = dm_drm_plane_reset, + .atomic_duplicate_state = dm_drm_plane_duplicate_state, + .atomic_destroy_state = dm_drm_plane_destroy_state, +}; + +static int dm_plane_helper_prepare_fb( + struct drm_plane *plane, + struct drm_plane_state *new_state) +{ + struct amdgpu_framebuffer *afb; + struct drm_gem_object *obj; + struct amdgpu_bo *rbo; + int r; + struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; + unsigned int awidth; + + dm_plane_state_old = to_dm_plane_state(plane->state); + dm_plane_state_new = to_dm_plane_state(new_state); + + if (!new_state->fb) { + DRM_DEBUG_KMS("No FB bound\n"); + return 0; + } + + afb = to_amdgpu_framebuffer(new_state->fb); + + obj = afb->obj; + rbo = gem_to_amdgpu_bo(obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r != 0)) + return r; + + r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address); + + + amdgpu_bo_unreserve(rbo); + + if (unlikely(r != 0)) { + DRM_ERROR("Failed to pin framebuffer\n"); + return r; + } + + amdgpu_bo_ref(rbo); + + if (dm_plane_state_new->surface && + dm_plane_state_old->surface != dm_plane_state_new->surface) { + struct dc_surface *surface = dm_plane_state_new->surface; + + if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + surface->address.grph.addr.low_part = lower_32_bits(afb->address); + surface->address.grph.addr.high_part = upper_32_bits(afb->address); + } else { + awidth = ALIGN(new_state->fb->width, 64); + surface->address.video_progressive.luma_addr.low_part + = lower_32_bits(afb->address); + surface->address.video_progressive.chroma_addr.low_part + = lower_32_bits(afb->address) + + (awidth * new_state->fb->height); + } + } + + /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer + * prepare and cleanup in drm_atomic_helper_prepare_planes + * and drm_atomic_helper_cleanup_planes because fb doens't in s3. + * IN 4.10 kernel this code should be removed and amdgpu_device_suspend + * code touching fram buffers should be avoided for DC. + */ + if (plane->type == DRM_PLANE_TYPE_CURSOR) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc); + + acrtc->cursor_bo = obj; + } + return 0; +} + +static void dm_plane_helper_cleanup_fb( + struct drm_plane *plane, + struct drm_plane_state *old_state) +{ + struct amdgpu_bo *rbo; + struct amdgpu_framebuffer *afb; + int r; + + if (!old_state->fb) + return; + + afb = to_amdgpu_framebuffer(old_state->fb); + rbo = gem_to_amdgpu_bo(afb->obj); + r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) { + DRM_ERROR("failed to reserve rbo before unpin\n"); + return; + } else { + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + amdgpu_bo_unref(&rbo); + }; +} + +int dm_create_validation_set_for_connector(struct drm_connector *connector, + struct drm_display_mode *mode, struct dc_validation_set *val_set) +{ + int result = MODE_ERROR; + struct dc_sink *dc_sink = + to_amdgpu_connector(connector)->dc_sink; + /* TODO: Unhardcode stream count */ + struct dc_stream *stream; + + if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || + (mode->flags & DRM_MODE_FLAG_DBLSCAN)) + return result; + + if (NULL == dc_sink) { + DRM_ERROR("dc_sink is NULL!\n"); + return result; + } + + stream = dc_create_stream_for_sink(dc_sink); + + if (NULL == stream) { + DRM_ERROR("Failed to create stream for sink!\n"); + return result; + } + + drm_mode_set_crtcinfo(mode, 0); + + fill_stream_properties_from_drm_display_mode(stream, mode, connector); + + val_set->stream = stream; + + stream->src.width = mode->hdisplay; + stream->src.height = mode->vdisplay; + stream->dst = stream->src; + + return MODE_OK; +} + +static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { + .prepare_fb = dm_plane_helper_prepare_fb, + .cleanup_fb = dm_plane_helper_cleanup_fb, +}; + +/* + * TODO: these are currently initialized to rgb formats only. + * For future use cases we should either initialize them dynamically based on + * plane capabilities, or initialize this array to all formats, so internal drm + * check will succeed, and let DC to implement proper check + */ +static uint32_t rgb_formats[] = { + DRM_FORMAT_RGB888, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, + DRM_FORMAT_XRGB2101010, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ARGB2101010, + DRM_FORMAT_ABGR2101010, +}; + +static uint32_t yuv_formats[] = { + DRM_FORMAT_NV12, + DRM_FORMAT_NV21, +}; + +static const u32 cursor_formats[] = { + DRM_FORMAT_ARGB8888 +}; + +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs) +{ + int res = -EPERM; + + switch (aplane->base.type) { + case DRM_PLANE_TYPE_PRIMARY: + aplane->base.format_default = true; + + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + rgb_formats, + ARRAY_SIZE(rgb_formats), + NULL, aplane->base.type, NULL); + break; + case DRM_PLANE_TYPE_OVERLAY: + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + yuv_formats, + ARRAY_SIZE(yuv_formats), + NULL, aplane->base.type, NULL); + break; + case DRM_PLANE_TYPE_CURSOR: + res = drm_universal_plane_init( + dm->adev->ddev, + &aplane->base, + possible_crtcs, + &dm_plane_funcs, + cursor_formats, + ARRAY_SIZE(cursor_formats), + NULL, aplane->base.type, NULL); + break; + } + + drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); + + return res; +} + +int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t crtc_index) +{ + struct amdgpu_crtc *acrtc = NULL; + struct amdgpu_plane *cursor_plane; + + int res = -ENOMEM; + + cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); + if (!cursor_plane) + goto fail; + + cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; + res = amdgpu_dm_plane_init(dm, cursor_plane, 0); + + acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); + if (!acrtc) + goto fail; + + res = drm_crtc_init_with_planes( + dm->ddev, + &acrtc->base, + plane, + &cursor_plane->base, + &amdgpu_dm_crtc_funcs, NULL); + + if (res) + goto fail; + + drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); + + acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; + acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; + + acrtc->crtc_id = crtc_index; + acrtc->base.enabled = false; + + dm->adev->mode_info.crtcs[crtc_index] = acrtc; + drm_mode_crtc_set_gamma_size(&acrtc->base, 256); + + return 0; + +fail: + if (acrtc) + kfree(acrtc); + if (cursor_plane) + kfree(cursor_plane); + acrtc->crtc_id = -1; + return res; +} + + +static int to_drm_connector_type(enum signal_type st) +{ + switch (st) { + case SIGNAL_TYPE_HDMI_TYPE_A: + return DRM_MODE_CONNECTOR_HDMIA; + case SIGNAL_TYPE_EDP: + return DRM_MODE_CONNECTOR_eDP; + case SIGNAL_TYPE_RGB: + return DRM_MODE_CONNECTOR_VGA; + case SIGNAL_TYPE_DISPLAY_PORT: + case SIGNAL_TYPE_DISPLAY_PORT_MST: + return DRM_MODE_CONNECTOR_DisplayPort; + case SIGNAL_TYPE_DVI_DUAL_LINK: + case SIGNAL_TYPE_DVI_SINGLE_LINK: + return DRM_MODE_CONNECTOR_DVID; + case SIGNAL_TYPE_VIRTUAL: + return DRM_MODE_CONNECTOR_VIRTUAL; + + default: + return DRM_MODE_CONNECTOR_Unknown; + } +} + +static void amdgpu_dm_get_native_mode(struct drm_connector *connector) +{ + const struct drm_connector_helper_funcs *helper = + connector->helper_private; + struct drm_encoder *encoder; + struct amdgpu_encoder *amdgpu_encoder; + + encoder = helper->best_encoder(connector); + + if (encoder == NULL) + return; + + amdgpu_encoder = to_amdgpu_encoder(encoder); + + amdgpu_encoder->native_mode.clock = 0; + + if (!list_empty(&connector->probed_modes)) { + struct drm_display_mode *preferred_mode = NULL; + list_for_each_entry(preferred_mode, + &connector->probed_modes, + head) { + if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { + amdgpu_encoder->native_mode = *preferred_mode; + } + break; + } + + } +} + +static struct drm_display_mode *amdgpu_dm_create_common_mode( + struct drm_encoder *encoder, char *name, + int hdisplay, int vdisplay) +{ + struct drm_device *dev = encoder->dev; + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *mode = NULL; + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + + mode = drm_mode_duplicate(dev, native_mode); + + if(mode == NULL) + return NULL; + + mode->hdisplay = hdisplay; + mode->vdisplay = vdisplay; + mode->type &= ~DRM_MODE_TYPE_PREFERRED; + strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); + + return mode; + +} + +static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, + struct drm_connector *connector) +{ + struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); + struct drm_display_mode *mode = NULL; + struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + int i; + int n; + struct mode_size { + char name[DRM_DISPLAY_MODE_LEN]; + int w; + int h; + }common_modes[] = { + { "640x480", 640, 480}, + { "800x600", 800, 600}, + { "1024x768", 1024, 768}, + { "1280x720", 1280, 720}, + { "1280x800", 1280, 800}, + {"1280x1024", 1280, 1024}, + { "1440x900", 1440, 900}, + {"1680x1050", 1680, 1050}, + {"1600x1200", 1600, 1200}, + {"1920x1080", 1920, 1080}, + {"1920x1200", 1920, 1200} + }; + + n = sizeof(common_modes) / sizeof(common_modes[0]); + + for (i = 0; i < n; i++) { + struct drm_display_mode *curmode = NULL; + bool mode_existed = false; + + if (common_modes[i].w > native_mode->hdisplay || + common_modes[i].h > native_mode->vdisplay || + (common_modes[i].w == native_mode->hdisplay && + common_modes[i].h == native_mode->vdisplay)) + continue; + + list_for_each_entry(curmode, &connector->probed_modes, head) { + if (common_modes[i].w == curmode->hdisplay && + common_modes[i].h == curmode->vdisplay) { + mode_existed = true; + break; + } + } + + if (mode_existed) + continue; + + mode = amdgpu_dm_create_common_mode(encoder, + common_modes[i].name, common_modes[i].w, + common_modes[i].h); + drm_mode_probed_add(connector, mode); + amdgpu_connector->num_modes++; + } +} + +static void amdgpu_dm_connector_ddc_get_modes( + struct drm_connector *connector, + struct edid *edid) +{ + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + + if (edid) { + /* empty probed_modes */ + INIT_LIST_HEAD(&connector->probed_modes); + amdgpu_connector->num_modes = + drm_add_edid_modes(connector, edid); + + drm_edid_to_eld(connector, edid); + + amdgpu_dm_get_native_mode(connector); + } else + amdgpu_connector->num_modes = 0; +} + +int amdgpu_dm_connector_get_modes(struct drm_connector *connector) +{ + const struct drm_connector_helper_funcs *helper = + connector->helper_private; + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + struct drm_encoder *encoder; + struct edid *edid = amdgpu_connector->edid; + + encoder = helper->best_encoder(connector); + + amdgpu_dm_connector_ddc_get_modes(connector, edid); + amdgpu_dm_connector_add_common_modes(encoder, connector); + return amdgpu_connector->num_modes; +} + +void amdgpu_dm_connector_init_helper( + struct amdgpu_display_manager *dm, + struct amdgpu_connector *aconnector, + int connector_type, + struct dc_link *link, + int link_index) +{ + struct amdgpu_device *adev = dm->ddev->dev_private; + + aconnector->connector_id = link_index; + aconnector->dc_link = link; + aconnector->base.interlace_allowed = false; + aconnector->base.doublescan_allowed = false; + aconnector->base.stereo_allowed = false; + aconnector->base.dpms = DRM_MODE_DPMS_OFF; + aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ + + mutex_init(&aconnector->hpd_lock); + + /*configure suport HPD hot plug connector_>polled default value is 0 + * which means HPD hot plug not supported*/ + switch (connector_type) { + case DRM_MODE_CONNECTOR_HDMIA: + aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; + break; + case DRM_MODE_CONNECTOR_DisplayPort: + aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; + break; + case DRM_MODE_CONNECTOR_DVID: + aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; + break; + default: + break; + } + + drm_object_attach_property(&aconnector->base.base, + dm->ddev->mode_config.scaling_mode_property, + DRM_MODE_SCALE_NONE); + + drm_object_attach_property(&aconnector->base.base, + adev->mode_info.underscan_property, + UNDERSCAN_OFF); + drm_object_attach_property(&aconnector->base.base, + adev->mode_info.underscan_hborder_property, + 0); + drm_object_attach_property(&aconnector->base.base, + adev->mode_info.underscan_vborder_property, + 0); + +} + +int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) +{ + struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); + struct ddc_service *ddc_service = i2c->ddc_service; + struct i2c_command cmd; + int i; + int result = -EIO; + + cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL); + + if (!cmd.payloads) + return result; + + cmd.number_of_payloads = num; + cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; + cmd.speed = 100; + + for (i = 0; i < num; i++) { + cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); + cmd.payloads[i].address = msgs[i].addr; + cmd.payloads[i].length = msgs[i].len; + cmd.payloads[i].data = msgs[i].buf; + } + + if (dal_i2caux_submit_i2c_command( + ddc_service->ctx->i2caux, + ddc_service->ddc_pin, + &cmd)) + result = num; + + kfree(cmd.payloads); + return result; +} + +u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) +{ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + +static const struct i2c_algorithm amdgpu_dm_i2c_algo = { + .master_xfer = amdgpu_dm_i2c_xfer, + .functionality = amdgpu_dm_i2c_func, +}; + +static struct amdgpu_i2c_adapter *create_i2c( + struct ddc_service *ddc_service, + int link_index, + int *res) +{ + struct amdgpu_device *adev = ddc_service->ctx->driver_context; + struct amdgpu_i2c_adapter *i2c; + + i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL); + i2c->base.owner = THIS_MODULE; + i2c->base.class = I2C_CLASS_DDC; + i2c->base.dev.parent = &adev->pdev->dev; + i2c->base.algo = &amdgpu_dm_i2c_algo; + snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); + i2c_set_adapdata(&i2c->base, i2c); + i2c->ddc_service = ddc_service; + + return i2c; +} + +/* Note: this function assumes that dc_link_detect() was called for the + * dc_link which will be represented by this aconnector. */ +int amdgpu_dm_connector_init( + struct amdgpu_display_manager *dm, + struct amdgpu_connector *aconnector, + uint32_t link_index, + struct amdgpu_encoder *aencoder) +{ + int res = 0; + int connector_type; + struct dc *dc = dm->dc; + struct dc_link *link = dc_get_link_at_index(dc, link_index); + struct amdgpu_i2c_adapter *i2c; + ((struct dc_link *)link)->priv = aconnector; + + DRM_DEBUG_KMS("%s()\n", __func__); + + i2c = create_i2c(link->ddc, link->link_index, &res); + aconnector->i2c = i2c; + res = i2c_add_adapter(&i2c->base); + + if (res) { + DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); + goto out_free; + } + + connector_type = to_drm_connector_type(link->connector_signal); + + res = drm_connector_init( + dm->ddev, + &aconnector->base, + &amdgpu_dm_connector_funcs, + connector_type); + + if (res) { + DRM_ERROR("connector_init failed\n"); + aconnector->connector_id = -1; + goto out_free; + } + + drm_connector_helper_add( + &aconnector->base, + &amdgpu_dm_connector_helper_funcs); + + amdgpu_dm_connector_init_helper( + dm, + aconnector, + connector_type, + link, + link_index); + + drm_mode_connector_attach_encoder( + &aconnector->base, &aencoder->base); + + drm_connector_register(&aconnector->base); + + if (connector_type == DRM_MODE_CONNECTOR_DisplayPort + || connector_type == DRM_MODE_CONNECTOR_eDP) + amdgpu_dm_initialize_dp_connector(dm, aconnector); + +#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ + defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) + + /* NOTE: this currently will create backlight device even if a panel + * is not connected to the eDP/LVDS connector. + * + * This is less than ideal but we don't have sink information at this + * stage since detection happens after. We can't do detection earlier + * since MST detection needs connectors to be created first. + */ + if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) { + /* Event if registration failed, we should continue with + * DM initialization because not having a backlight control + * is better then a black screen. */ + amdgpu_dm_register_backlight_device(dm); + + if (dm->backlight_dev) + dm->backlight_link = link; + } +#endif + +out_free: + if (res) { + kfree(i2c); + aconnector->i2c = NULL; + } + return res; +} + +int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) +{ + switch (adev->mode_info.num_crtc) { + case 1: + return 0x1; + case 2: + return 0x3; + case 3: + return 0x7; + case 4: + return 0xf; + case 5: + return 0x1f; + case 6: + default: + return 0x3f; + } +} + +int amdgpu_dm_encoder_init( + struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index) +{ + struct amdgpu_device *adev = dev->dev_private; + + int res = drm_encoder_init(dev, + &aencoder->base, + &amdgpu_dm_encoder_funcs, + DRM_MODE_ENCODER_TMDS, + NULL); + + aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); + + if (!res) + aencoder->encoder_id = link_index; + else + aencoder->encoder_id = -1; + + drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); + + return res; +} + +static void manage_dm_interrupts( + struct amdgpu_device *adev, + struct amdgpu_crtc *acrtc, + bool enable) +{ + /* + * this is not correct translation but will work as soon as VBLANK + * constant is the same as PFLIP + */ + int irq_type = + amdgpu_crtc_idx_to_irq_type( + adev, + acrtc->crtc_id); + + if (enable) { + drm_crtc_vblank_on(&acrtc->base); + amdgpu_irq_get( + adev, + &adev->pageflip_irq, + irq_type); + } else { + + amdgpu_irq_put( + adev, + &adev->pageflip_irq, + irq_type); + drm_crtc_vblank_off(&acrtc->base); + } +} + +static bool is_scaling_state_different( + const struct dm_connector_state *dm_state, + const struct dm_connector_state *old_dm_state) +{ + if (dm_state->scaling != old_dm_state->scaling) + return true; + if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { + if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) + return true; + } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { + if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) + return true; + } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder + || dm_state->underscan_vborder != old_dm_state->underscan_vborder) + return true; + return false; +} + +static void remove_stream( + struct amdgpu_device *adev, + struct amdgpu_crtc *acrtc, + struct dc_stream *stream) +{ + /* this is the update mode case */ + if (adev->dm.freesync_module) + mod_freesync_remove_stream(adev->dm.freesync_module, stream); + + acrtc->otg_inst = -1; + acrtc->enabled = false; +} + +static void handle_cursor_update( + struct drm_plane *plane, + struct drm_plane_state *old_plane_state) +{ + if (!plane->state->fb && !old_plane_state->fb) + return; + + /* Check if it's a cursor on/off update or just cursor move*/ + if (plane->state->fb == old_plane_state->fb) + dm_crtc_cursor_move( + plane->state->crtc, + plane->state->crtc_x, + plane->state->crtc_y); + else { + struct amdgpu_framebuffer *afb = + to_amdgpu_framebuffer(plane->state->fb); + dm_crtc_cursor_set( + (!!plane->state->fb) ? + plane->state->crtc : + old_plane_state->crtc, + (!!plane->state->fb) ? + afb->address : + 0, + plane->state->crtc_w, + plane->state->crtc_h); + } +} + + +static void prepare_flip_isr(struct amdgpu_crtc *acrtc) +{ + + assert_spin_locked(&acrtc->base.dev->event_lock); + WARN_ON(acrtc->event); + + acrtc->event = acrtc->base.state->event; + + /* Set the flip status */ + acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + + /* Mark this event as consumed */ + acrtc->base.state->event = NULL; + + DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", + acrtc->crtc_id); +} + +/* + * Executes flip + * + * Waits on all BO's fences and for proper vblank count + */ +static void amdgpu_dm_do_flip( + struct drm_crtc *crtc, + struct drm_framebuffer *fb, + uint32_t target) +{ + unsigned long flags; + uint32_t target_vblank; + int r, vpos, hpos; + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj); + struct amdgpu_device *adev = crtc->dev->dev_private; + bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + struct dc_flip_addrs addr = { {0} }; + struct dc_surface_update surface_updates[1] = { {0} }; + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); + + + /* Prepare wait for target vblank early - before the fence-waits */ + target_vblank = target - drm_crtc_vblank_count(crtc) + + amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); + + /*TODO This might fail and hence better not used, wait + * explicitly on fences instead + * and in general should be called for + * blocking commit to as per framework helpers + * */ + r = amdgpu_bo_reserve(abo, true); + if (unlikely(r != 0)) { + DRM_ERROR("failed to reserve buffer before flip\n"); + WARN_ON(1); + } + + /* Wait for all fences on this FB */ + WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT) < 0); + + amdgpu_bo_unreserve(abo); + + /* Wait until we're out of the vertical blank period before the one + * targeted by the flip + */ + while ((acrtc->enabled && + (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0, + &vpos, &hpos, NULL, NULL, + &crtc->hwmode) + & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && + (int)(target_vblank - + amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { + usleep_range(1000, 1100); + } + + /* Flip */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + /* update crtc fb */ + crtc->primary->fb = fb; + + WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); + WARN_ON(!acrtc_state->stream); + + addr.address.grph.addr.low_part = lower_32_bits(afb->address); + addr.address.grph.addr.high_part = upper_32_bits(afb->address); + addr.flip_immediate = async_flip; + + + if (acrtc->base.state->event) + prepare_flip_isr(acrtc); + + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; + surface_updates->flip_addr = &addr; + + + dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); + + DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", + __func__, + addr.address.grph.addr.high_part, + addr.address.grph.addr.low_part); + + + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); +} + +static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, + struct drm_device *dev, + struct amdgpu_display_manager *dm, + struct drm_crtc *pcrtc, + bool *wait_for_vblank) +{ + uint32_t i; + struct drm_plane *plane; + struct drm_plane_state *old_plane_state; + struct dc_stream *dc_stream_attach; + struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); + int planes_count = 0; + unsigned long flags; + + /* update planes when needed */ + for_each_plane_in_state(state, plane, old_plane_state, i) { + struct drm_plane_state *plane_state = plane->state; + struct drm_crtc *crtc = plane_state->crtc; + struct drm_framebuffer *fb = plane_state->fb; + bool pflip_needed; + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + + if (plane->type == DRM_PLANE_TYPE_CURSOR) { + handle_cursor_update(plane, old_plane_state); + continue; + } + + if (!fb || !crtc || pcrtc != crtc || !crtc->state->active || + (!crtc->state->planes_changed && + !pcrtc->state->color_mgmt_changed)) + continue; + + pflip_needed = !state->allow_modeset; + + spin_lock_irqsave(&crtc->dev->event_lock, flags); + if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { + DRM_ERROR("add_surface: acrtc %d, already busy\n", + acrtc_attach->crtc_id); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + /* In comit tail framework this cannot happen */ + WARN_ON(1); + } + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + + if (!pflip_needed) { + WARN_ON(!dm_plane_state->surface); + + dc_surfaces_constructed[planes_count] = dm_plane_state->surface; + + dc_stream_attach = acrtc_state->stream; + planes_count++; + + } else if (crtc->state->planes_changed) { + /* Assume even ONE crtc with immediate flip means + * entire can't wait for VBLANK + * TODO Check if it's correct + */ + *wait_for_vblank = + acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? + false : true; + + /* TODO: Needs rework for multiplane flip */ + if (plane->type == DRM_PLANE_TYPE_PRIMARY) + drm_crtc_vblank_get(crtc); + + amdgpu_dm_do_flip( + crtc, + fb, + drm_crtc_vblank_count(crtc) + *wait_for_vblank); + + /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */ + + /*clean up the flags for next usage*/ + acrtc_attach->flip_flags = 0; + } + + } + + if (planes_count) { + unsigned long flags; + + if (pcrtc->state->event) { + + drm_crtc_vblank_get(pcrtc); + + spin_lock_irqsave(&pcrtc->dev->event_lock, flags); + prepare_flip_isr(acrtc_attach); + spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); + } + + if (false == dc_commit_surfaces_to_stream(dm->dc, + dc_surfaces_constructed, + planes_count, + dc_stream_attach)) + dm_error("%s: Failed to attach surface!\n", __func__); + } else { + /*TODO BUG Here should go disable planes on CRTC. */ + } +} + + +int amdgpu_dm_atomic_commit( + struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock) +{ + struct drm_crtc *crtc; + struct drm_crtc_state *new_state; + struct amdgpu_device *adev = dev->dev_private; + int i; + + /* + * We evade vblanks and pflips on crtc that + * should be changed. We do it here to flush & disable + * interrupts before drm_swap_state is called in drm_atomic_helper_commit + * it will update crtc->dm_crtc_state->stream pointer which is used in + * the ISRs. + */ + for_each_crtc_in_state(state, crtc, new_state, i) { + struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream) + manage_dm_interrupts(adev, acrtc, false); + } + + return drm_atomic_helper_commit(dev, state, nonblock); + + /*TODO Handle EINTR, reenable IRQ*/ +} + +void amdgpu_dm_atomic_commit_tail( + struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_display_manager *dm = &adev->dm; + struct dm_atomic_state *dm_state; + uint32_t i, j; + uint32_t new_crtcs_count = 0; + struct drm_crtc *crtc, *pcrtc; + struct drm_crtc_state *old_crtc_state; + struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; + struct dc_stream *new_stream = NULL; + unsigned long flags; + bool wait_for_vblank = true; + struct drm_connector *connector; + struct drm_connector_state *old_conn_state; + struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + + drm_atomic_helper_update_legacy_modeset_state(dev, state); + + dm_state = to_dm_atomic_state(state); + + /* update changed items */ + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + struct drm_crtc_state *new_state = crtc->state; + new_acrtc_state = to_dm_crtc_state(new_state); + old_acrtc_state = to_dm_crtc_state(old_crtc_state); + + DRM_DEBUG_KMS( + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " + "planes_changed:%d, mode_changed:%d,active_changed:%d," + "connectors_changed:%d\n", + acrtc->crtc_id, + new_state->enable, + new_state->active, + new_state->planes_changed, + new_state->mode_changed, + new_state->active_changed, + new_state->connectors_changed); + + /* handles headless hotplug case, updating new_state and + * aconnector as needed + */ + + if (modeset_required(new_state)) { + + DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); + + if (!new_acrtc_state->stream) { + /* + * this could happen because of issues with + * userspace notifications delivery. + * In this case userspace tries to set mode on + * display which is disconnect in fact. + * dc_sink in NULL in this case on aconnector. + * We expect reset mode will come soon. + * + * This can also happen when unplug is done + * during resume sequence ended + * + * In this case, we want to pretend we still + * have a sink to keep the pipe running so that + * hw state is consistent with the sw state + */ + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + __func__, acrtc->base.base.id); + continue; + } + + + if (old_acrtc_state->stream) + remove_stream(adev, acrtc, old_acrtc_state->stream); + + + /* + * this loop saves set mode crtcs + * we needed to enable vblanks once all + * resources acquired in dc after dc_commit_streams + */ + + /*TODO move all this into dm_crtc_state, get rid of + * new_crtcs array and use old and new atomic states + * instead + */ + new_crtcs[new_crtcs_count] = acrtc; + new_crtcs_count++; + + acrtc->enabled = true; + acrtc->hw_mode = crtc->state->mode; + crtc->hwmode = crtc->state->mode; + } else if (modereset_required(new_state)) { + DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); + + /* i.e. reset mode */ + if (old_acrtc_state->stream) + remove_stream(adev, acrtc, old_acrtc_state->stream); + } + } /* for_each_crtc_in_state() */ + + /* + * Add streams after required streams from new and replaced streams + * are removed from freesync module + */ + if (adev->dm.freesync_module) { + for (i = 0; i < new_crtcs_count; i++) { + struct amdgpu_connector *aconnector = NULL; + new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); + + new_stream = new_acrtc_state->stream; + aconnector = + amdgpu_dm_find_first_crct_matching_connector( + state, + &new_crtcs[i]->base, + false); + if (!aconnector) { + DRM_INFO( + "Atomic commit: Failed to find connector for acrtc id:%d " + "skipping freesync init\n", + new_crtcs[i]->crtc_id); + continue; + } + + mod_freesync_add_stream(adev->dm.freesync_module, + new_stream, &aconnector->caps); + } + } + + if (dm_state->context) + WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); + + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + new_acrtc_state = to_dm_crtc_state(crtc->state); + + if (new_acrtc_state->stream != NULL) { + const struct dc_stream_status *status = + dc_stream_get_status(new_acrtc_state->stream); + + if (!status) + DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc); + else + acrtc->otg_inst = status->primary_otg_inst; + } + } + + /* Handle scaling and undersacn changes*/ + for_each_connector_in_state(state, connector, old_conn_state, i) { + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct dm_connector_state *con_new_state = + to_dm_connector_state(aconnector->base.state); + struct dm_connector_state *con_old_state = + to_dm_connector_state(old_conn_state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); + struct dc_stream_status *status = NULL; + + /* Skip any modesets/resets */ + if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) + continue; + + /* Skip any thing not scale or underscan changes */ + if (!is_scaling_state_different(con_new_state, con_old_state)) + continue; + + new_acrtc_state = to_dm_crtc_state(acrtc->base.state); + + update_stream_scaling_settings(&con_new_state->base.crtc->mode, + con_new_state, (struct dc_stream *)new_acrtc_state->stream); + + status = dc_stream_get_status(new_acrtc_state->stream); + WARN_ON(!status); + WARN_ON(!status->surface_count); + + if (!new_acrtc_state->stream) + continue; + + /*TODO How it works with MPO ?*/ + if (!dc_commit_surfaces_to_stream( + dm->dc, + status->surfaces, + status->surface_count, + new_acrtc_state->stream)) + dm_error("%s: Failed to update stream scaling!\n", __func__); + } + + for (i = 0; i < new_crtcs_count; i++) { + /* + * loop to enable interrupts on newly arrived crtc + */ + struct amdgpu_crtc *acrtc = new_crtcs[i]; + new_acrtc_state = to_dm_crtc_state(acrtc->base.state); + + if (adev->dm.freesync_module) + mod_freesync_notify_mode_change( + adev->dm.freesync_module, &new_acrtc_state->stream, 1); + + manage_dm_interrupts(adev, acrtc, true); + } + + /* update planes when needed per crtc*/ + for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { + new_acrtc_state = to_dm_crtc_state(pcrtc->state); + + if (new_acrtc_state->stream) + amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); + } + + + /* + * send vblank event on all events not handled in flip and + * mark consumed event for drm_atomic_helper_commit_hw_done + */ + spin_lock_irqsave(&adev->ddev->event_lock, flags); + for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + + if (acrtc->base.state->event) + drm_send_event_locked(dev, &crtc->state->event->base); + + acrtc->base.state->event = NULL; + } + spin_unlock_irqrestore(&adev->ddev->event_lock, flags); + + /* Signal HW programming completion */ + drm_atomic_helper_commit_hw_done(state); + + if (wait_for_vblank) + drm_atomic_helper_wait_for_vblanks(dev, state); + + drm_atomic_helper_cleanup_planes(dev, state); +} + + +static int dm_force_atomic_commit(struct drm_connector *connector) +{ + int ret = 0; + struct drm_device *ddev = connector->dev; + struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); + struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); + struct drm_plane *plane = disconnected_acrtc->base.primary; + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + struct drm_plane_state *plane_state; + + if (!state) + return -ENOMEM; + + state->acquire_ctx = ddev->mode_config.acquire_ctx; + + /* Construct an atomic state to restore previous display setting */ + + /* + * Attach connectors to drm_atomic_state + */ + conn_state = drm_atomic_get_connector_state(state, connector); + + ret = PTR_ERR_OR_ZERO(conn_state); + if (ret) + goto err; + + /* Attach crtc to drm_atomic_state*/ + crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); + + ret = PTR_ERR_OR_ZERO(crtc_state); + if (ret) + goto err; + + /* force a restore */ + crtc_state->mode_changed = true; + + /* Attach plane to drm_atomic_state */ + plane_state = drm_atomic_get_plane_state(state, plane); + + ret = PTR_ERR_OR_ZERO(plane_state); + if (ret) + goto err; + + + /* Call commit internally with the state we just constructed */ + ret = drm_atomic_commit(state); + if (!ret) + return 0; + +err: + DRM_ERROR("Restoring old state failed with %i\n", ret); + drm_atomic_state_put(state); + + return ret; +} + +/* + * This functions handle all cases when set mode does not come upon hotplug. + * This include when the same display is unplugged then plugged back into the + * same port and when we are running without usermode desktop manager supprot + */ +void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector) +{ + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_crtc *disconnected_acrtc; + struct dm_crtc_state *acrtc_state; + + if (!aconnector->dc_sink || !connector->state || !connector->encoder) + return; + + disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); + acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); + + if (!disconnected_acrtc || !acrtc_state->stream) + return; + + /* + * If the previous sink is not released and different from the current, + * we deduce we are in a state where we can not rely on usermode call + * to turn on the display, so we do it here + */ + if (acrtc_state->stream->sink != aconnector->dc_sink) + dm_force_atomic_commit(&aconnector->base); +} + +static uint32_t add_val_sets_surface( + struct dc_validation_set *val_sets, + uint32_t set_count, + const struct dc_stream *stream, + struct dc_surface *surface) +{ + uint32_t i = 0, j = 0; + + while (i < set_count) { + if (val_sets[i].stream == stream) { + while (val_sets[i].surfaces[j]) + j++; + break; + } + ++i; + } + + val_sets[i].surfaces[j] = surface; + val_sets[i].surface_count++; + + return val_sets[i].surface_count; +} + +static uint32_t update_in_val_sets_stream( + struct dc_validation_set *val_sets, + uint32_t set_count, + struct dc_stream *old_stream, + struct dc_stream *new_stream, + struct drm_crtc *crtc) +{ + uint32_t i = 0; + + while (i < set_count) { + if (val_sets[i].stream == old_stream) + break; + ++i; + } + + val_sets[i].stream = new_stream; + + if (i == set_count) + /* nothing found. add new one to the end */ + return set_count + 1; + + return set_count; +} + +static uint32_t remove_from_val_sets( + struct dc_validation_set *val_sets, + uint32_t set_count, + const struct dc_stream *stream) +{ + int i; + + for (i = 0; i < set_count; i++) + if (val_sets[i].stream == stream) + break; + + if (i == set_count) { + /* nothing found */ + return set_count; + } + + set_count--; + + for (; i < set_count; i++) { + val_sets[i] = val_sets[i + 1]; + } + + return set_count; +} + +/*` + * Grabs all modesetting locks to serialize against any blocking commits, + * Waits for completion of all non blocking commits. + */ +static int do_aquire_global_lock( + struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct drm_crtc *crtc; + struct drm_crtc_commit *commit; + long ret; + + /* Adding all modeset locks to aquire_ctx will + * ensure that when the framework release it the + * extra locks we are locking here will get released to + */ + ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); + if (ret) + return ret; + + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + spin_lock(&crtc->commit_lock); + commit = list_first_entry_or_null(&crtc->commit_list, + struct drm_crtc_commit, commit_entry); + if (commit) + drm_crtc_commit_get(commit); + spin_unlock(&crtc->commit_lock); + + if (!commit) + continue; + + /* Make sure all pending HW programming completed and + * page flips done + */ + ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); + + if (ret > 0) + ret = wait_for_completion_interruptible_timeout( + &commit->flip_done, 10*HZ); + + if (ret == 0) + DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " + "timed out\n", crtc->base.id, crtc->name); + + drm_crtc_commit_put(commit); + } + + return ret < 0 ? ret : 0; +} + +int amdgpu_dm_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + struct drm_plane *plane; + struct drm_plane_state *plane_state; + int i, j; + int ret; + struct amdgpu_device *adev = dev->dev_private; + struct dc *dc = adev->dm.dc; + struct drm_connector *connector; + struct drm_connector_state *conn_state; + int set_count; + struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; + struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + + /* + * This bool will be set for true for any modeset/reset + * or surface update which implies non fast surface update. + */ + bool lock_and_validation_needed = false; + + ret = drm_atomic_helper_check_modeset(dev, state); + + if (ret) { + DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); + return ret; + } + + dm_state = to_dm_atomic_state(state); + + /* copy existing configuration */ + set_count = 0; + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + + old_acrtc_state = to_dm_crtc_state(crtc->state); + + if (old_acrtc_state->stream) { + dc_stream_retain(old_acrtc_state->stream); + set[set_count].stream = old_acrtc_state->stream; + ++set_count; + } + } + + /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ + /* update changed items */ + for_each_crtc_in_state(state, crtc, crtc_state, i) { + struct amdgpu_crtc *acrtc = NULL; + struct amdgpu_connector *aconnector = NULL; + old_acrtc_state = to_dm_crtc_state(crtc->state); + new_acrtc_state = to_dm_crtc_state(crtc_state); + acrtc = to_amdgpu_crtc(crtc); + + aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); + + DRM_DEBUG_KMS( + "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " + "planes_changed:%d, mode_changed:%d,active_changed:%d," + "connectors_changed:%d\n", + acrtc->crtc_id, + crtc_state->enable, + crtc_state->active, + crtc_state->planes_changed, + crtc_state->mode_changed, + crtc_state->active_changed, + crtc_state->connectors_changed); + + if (modeset_required(crtc_state)) { + + struct dc_stream *new_stream = NULL; + struct drm_connector_state *conn_state = NULL; + struct dm_connector_state *dm_conn_state = NULL; + + if (aconnector) { + conn_state = drm_atomic_get_connector_state(state, &aconnector->base); + if (IS_ERR(conn_state)) { + ret = PTR_ERR_OR_ZERO(conn_state); + goto fail; + } + + dm_conn_state = to_dm_connector_state(conn_state); + } + + new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state); + + /* + * we can have no stream on ACTION_SET if a display + * was disconnected during S3, in this case it not and + * error, the OS will be updated after detection, and + * do the right thing on next atomic commit + */ + if (!new_stream) { + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + __func__, acrtc->base.base.id); + break; + } + + if (new_acrtc_state->stream) + dc_stream_release(new_acrtc_state->stream); + + new_acrtc_state->stream = new_stream; + + set_count = update_in_val_sets_stream( + set, + set_count, + old_acrtc_state->stream, + new_acrtc_state->stream, + crtc); + + lock_and_validation_needed = true; + + } else if (modereset_required(crtc_state)) { + + /* i.e. reset mode */ + if (new_acrtc_state->stream) { + set_count = remove_from_val_sets( + set, + set_count, + new_acrtc_state->stream); + + dc_stream_release(new_acrtc_state->stream); + new_acrtc_state->stream = NULL; + + lock_and_validation_needed = true; + } + } + + + /* + * Hack: Commit needs planes right now, specifically for gamma + * TODO rework commit to check CRTC for gamma change + */ + if (crtc_state->color_mgmt_changed) { + + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + goto fail; + } + } + + /* Check scaling and undersacn changes*/ + /*TODO Removed scaling changes validation due to inability to commit + * new stream into context w\o causing full reset. Need to + * decide how to handle. + */ + for_each_connector_in_state(state, connector, conn_state, i) { + struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct dm_connector_state *con_old_state = + to_dm_connector_state(aconnector->base.state); + struct dm_connector_state *con_new_state = + to_dm_connector_state(conn_state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); + + /* Skip any modesets/resets */ + if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) + continue; + + /* Skip any thing not scale or underscan chnages */ + if (!is_scaling_state_different(con_new_state, con_old_state)) + continue; + + lock_and_validation_needed = true; + } + + for_each_crtc_in_state(state, crtc, crtc_state, i) { + new_acrtc_state = to_dm_crtc_state(crtc_state); + + for_each_plane_in_state(state, plane, plane_state, j) { + struct drm_crtc *plane_crtc = plane_state->crtc; + struct drm_framebuffer *fb = plane_state->fb; + bool pflip_needed; + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + + /*TODO Implement atomic check for cursor plane */ + if (plane->type == DRM_PLANE_TYPE_CURSOR) + continue; + + if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active) + continue; + + WARN_ON(!new_acrtc_state->stream); + + pflip_needed = !state->allow_modeset; + if (!pflip_needed) { + struct dc_surface *surface; + + surface = dc_create_surface(dc); + + ret = fill_plane_attributes( + plane_crtc->dev->dev_private, + surface, + plane_state, + crtc_state, + false); + if (ret) + goto fail; + + + if (dm_plane_state->surface) + dc_surface_release(dm_plane_state->surface); + + dm_plane_state->surface = surface; + + add_val_sets_surface(set, + set_count, + new_acrtc_state->stream, + surface); + + lock_and_validation_needed = true; + } + } + } + + /* Run this here since we want to validate the streams we created */ + ret = drm_atomic_helper_check_planes(dev, state); + if (ret) + goto fail; + + /* + * For full updates case when + * removing/adding/updating streams on once CRTC while flipping + * on another CRTC, + * acquiring global lock will guarantee that any such full + * update commit + * will wait for completion of any outstanding flip using DRMs + * synchronization events. + */ + + if (lock_and_validation_needed) { + + ret = do_aquire_global_lock(dev, state); + if (ret) + goto fail; + WARN_ON(dm_state->context); + dm_state->context = dc_get_validate_context(dc, set, set_count); + if (!dm_state->context) { + ret = -EINVAL; + goto fail; + } + } + + /* Must be success */ + WARN_ON(ret); + return ret; + +fail: + if (ret == -EDEADLK) + DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n"); + else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) + DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n"); + else + DRM_ERROR("Atomic check failed with err: %d .\n", ret); + + return ret; +} + +static bool is_dp_capable_without_timing_msa( + struct dc *dc, + struct amdgpu_connector *amdgpu_connector) +{ + uint8_t dpcd_data; + bool capable = false; + + if (amdgpu_connector->dc_link && + dm_helpers_dp_read_dpcd( + NULL, + amdgpu_connector->dc_link, + DP_DOWN_STREAM_PORT_COUNT, + &dpcd_data, + sizeof(dpcd_data))) { + capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; + } + + return capable; +} +void amdgpu_dm_add_sink_to_freesync_module( + struct drm_connector *connector, + struct edid *edid) +{ + int i; + uint64_t val_capable; + bool edid_check_required; + struct detailed_timing *timing; + struct detailed_non_pixel *data; + struct detailed_data_monitor_range *range; + struct amdgpu_connector *amdgpu_connector = + to_amdgpu_connector(connector); + + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + edid_check_required = false; + if (!amdgpu_connector->dc_sink) { + DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); + return; + } + if (!adev->dm.freesync_module) + return; + /* + * if edid non zero restrict freesync only for dp and edp + */ + if (edid) { + if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT + || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { + edid_check_required = is_dp_capable_without_timing_msa( + adev->dm.dc, + amdgpu_connector); + } + } + val_capable = 0; + if (edid_check_required == true && (edid->version > 1 || + (edid->version == 1 && edid->revision > 1))) { + for (i = 0; i < 4; i++) { + + timing = &edid->detailed_timings[i]; + data = &timing->data.other_data; + range = &data->data.range; + /* + * Check if monitor has continuous frequency mode + */ + if (data->type != EDID_DETAIL_MONITOR_RANGE) + continue; + /* + * Check for flag range limits only. If flag == 1 then + * no additional timing information provided. + * Default GTF, GTF Secondary curve and CVT are not + * supported + */ + if (range->flags != 1) + continue; + + amdgpu_connector->min_vfreq = range->min_vfreq; + amdgpu_connector->max_vfreq = range->max_vfreq; + amdgpu_connector->pixel_clock_mhz = + range->pixel_clock_mhz * 10; + break; + } + + if (amdgpu_connector->max_vfreq - + amdgpu_connector->min_vfreq > 10) { + amdgpu_connector->caps.supported = true; + amdgpu_connector->caps.min_refresh_in_micro_hz = + amdgpu_connector->min_vfreq * 1000000; + amdgpu_connector->caps.max_refresh_in_micro_hz = + amdgpu_connector->max_vfreq * 1000000; + val_capable = 1; + } + } + + /* + * TODO figure out how to notify user-mode or DRM of freesync caps + * once we figure out how to deal with freesync in an upstreamable + * fashion + */ + +} + +void amdgpu_dm_remove_sink_from_freesync_module( + struct drm_connector *connector) +{ + /* + * TODO fill in once we figure out how to deal with freesync in + * an upstreamable fashion + */ +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ee69179636a1..16b2e0849a65 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -26,9 +26,9 @@ #ifndef __AMDGPU_DM_H__ #define __AMDGPU_DM_H__ -/* -#include "linux/switch.h" -*/ +#include +#include +#include "dc.h" /* * This file contains the definition for amdgpu_display_manager @@ -173,4 +173,106 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_crtc *crtc, bool from_state_var); + +struct amdgpu_framebuffer; +struct amdgpu_display_manager; +struct dc_validation_set; +struct dc_surface; +/* TODO rename to dc_stream_state */ +struct dc_stream; + + +struct dm_plane_state { + struct drm_plane_state base; + struct dc_surface *surface; +}; + +struct dm_crtc_state { + struct drm_crtc_state base; + struct dc_stream *stream; +}; + +#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) + +struct dm_atomic_state { + struct drm_atomic_state base; + + struct validate_context *context; +}; + +#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) + + +/*TODO Jodan Hersen use the one in amdgpu_dm*/ +int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs); +int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t link_index); +int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, + struct amdgpu_connector *amdgpu_connector, + uint32_t link_index, + struct amdgpu_encoder *amdgpu_encoder); +int amdgpu_dm_encoder_init( + struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index); + +void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc); +void amdgpu_dm_connector_destroy(struct drm_connector *connector); +void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); + +int amdgpu_dm_connector_get_modes(struct drm_connector *connector); + +int amdgpu_dm_atomic_commit( + struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock); + +void amdgpu_dm_atomic_commit_tail( + struct drm_atomic_state *state); + +int amdgpu_dm_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state); + +void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); +struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( + struct drm_connector *connector); +int amdgpu_dm_connector_atomic_set_property( + struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + uint64_t val); + +int amdgpu_dm_connector_atomic_get_property( + struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val); + +int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); + +void amdgpu_dm_connector_init_helper( + struct amdgpu_display_manager *dm, + struct amdgpu_connector *aconnector, + int connector_type, + struct dc_link *link, + int link_index); + +int amdgpu_dm_connector_mode_valid( + struct drm_connector *connector, + struct drm_display_mode *mode); + +void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); + +void amdgpu_dm_add_sink_to_freesync_module( + struct drm_connector *connector, + struct edid *edid); + +void amdgpu_dm_remove_sink_from_freesync_module( + struct drm_connector *connector); + +extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; + #endif /* __AMDGPU_DM_H__ */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 6c19a07709df..0a615583de63 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -38,7 +38,6 @@ #include "dc.h" #include "amdgpu_dm.h" #include "amdgpu_dm_irq.h" -#include "amdgpu_dm_types.h" #include "dm_helpers.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ec91a52c002f..82e4d49fb184 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -27,7 +27,7 @@ #include #include "dm_services.h" #include "amdgpu.h" -#include "amdgpu_dm_types.h" +#include "amdgpu_dm.h" #include "amdgpu_dm_mst_types.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index a8a53b85905a..3348e90a0a37 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -33,7 +33,6 @@ #include "amdgpu.h" #include "amdgpu_dm.h" #include "amdgpu_dm_irq.h" -#include "amdgpu_dm_types.h" #include "amdgpu_pm.h" /****************************************************************************** diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c deleted file mode 100644 index 80d4e2670cc2..000000000000 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c +++ /dev/null @@ -1,3286 +0,0 @@ -/* - * Copyright 2012-13 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#include -#include - -#include -#include -#include -#include -#include - - -#include "amdgpu.h" -#include "amdgpu_pm.h" -#include "dm_helpers.h" -#include "dm_services_types.h" - -// We need to #undef FRAME_SIZE and DEPRECATED because they conflict -// with ptrace-abi.h's #define's of them. -#undef FRAME_SIZE -#undef DEPRECATED - -#include "dc.h" - -#include "amdgpu_dm_types.h" -#include "amdgpu_dm_mst_types.h" - -#include "modules/inc/mod_freesync.h" - -#include "i2caux_interface.h" - -struct dm_connector_state { - struct drm_connector_state base; - - enum amdgpu_rmx_type scaling; - uint8_t underscan_vborder; - uint8_t underscan_hborder; - bool underscan_enable; -}; - -#define to_dm_connector_state(x)\ - container_of((x), struct dm_connector_state, base) - -static bool modeset_required(struct drm_crtc_state *crtc_state) -{ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return false; - - if (!crtc_state->enable) - return false; - - return crtc_state->active; -} - -static bool modereset_required(struct drm_crtc_state *crtc_state) -{ - if (!drm_atomic_crtc_needs_modeset(crtc_state)) - return false; - - return !crtc_state->enable || !crtc_state->active; -} - -void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) -{ - drm_encoder_cleanup(encoder); - kfree(encoder); -} - -static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { - .destroy = amdgpu_dm_encoder_destroy, -}; - -static void dm_set_cursor( - struct amdgpu_crtc *amdgpu_crtc, - uint64_t gpu_addr, - uint32_t width, - uint32_t height) -{ - struct dc_cursor_attributes attributes; - struct dc_cursor_position position; - struct drm_crtc *crtc = &amdgpu_crtc->base; - int x, y; - int xorigin = 0, yorigin = 0; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - - attributes.address.high_part = upper_32_bits(gpu_addr); - attributes.address.low_part = lower_32_bits(gpu_addr); - attributes.width = width; - attributes.height = height; - attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; - attributes.rotation_angle = 0; - attributes.attribute_flags.value = 0; - - attributes.pitch = attributes.width; - - x = amdgpu_crtc->cursor_x; - y = amdgpu_crtc->cursor_y; - - /* avivo cursor are offset into the total surface */ - x += crtc->primary->state->src_x >> 16; - y += crtc->primary->state->src_y >> 16; - - if (x < 0) { - xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); - x = 0; - } - if (y < 0) { - yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); - y = 0; - } - - position.enable = true; - position.x = x; - position.y = y; - - position.x_hotspot = xorigin; - position.y_hotspot = yorigin; - - if (!dc_stream_set_cursor_attributes( - acrtc_state->stream, - &attributes)) { - DRM_ERROR("DC failed to set cursor attributes\n"); - } - - if (!dc_stream_set_cursor_position( - acrtc_state->stream, - &position)) { - DRM_ERROR("DC failed to set cursor position\n"); - } -} - -static int dm_crtc_cursor_set( - struct drm_crtc *crtc, - uint64_t address, - uint32_t width, - uint32_t height) -{ - struct dc_cursor_position position; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - int ret; - - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - ret = EINVAL; - - DRM_DEBUG_KMS( - "%s: crtc_id=%d with size %d to %d \n", - __func__, - amdgpu_crtc->crtc_id, - width, - height); - - if (!address) { - /* turn off cursor */ - position.enable = false; - position.x = 0; - position.y = 0; - - if (acrtc_state->stream) { - /*set cursor visible false*/ - dc_stream_set_cursor_position( - acrtc_state->stream, - &position); - } - goto release; - - } - - if ((width > amdgpu_crtc->max_cursor_width) || - (height > amdgpu_crtc->max_cursor_height)) { - DRM_ERROR( - "%s: bad cursor width or height %d x %d\n", - __func__, - width, - height); - goto release; - } - - /*program new cursor bo to hardware*/ - dm_set_cursor(amdgpu_crtc, address, width, height); - -release: - return ret; - -} - -static int dm_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - int xorigin = 0, yorigin = 0; - struct dc_cursor_position position; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; - - /* avivo cursor are offset into the total surface */ - x += crtc->primary->state->src_x >> 16; - y += crtc->primary->state->src_y >> 16; - - /* - * TODO: for cursor debugging unguard the following - */ -#if 0 - DRM_DEBUG_KMS( - "%s: x %d y %d c->x %d c->y %d\n", - __func__, - x, - y, - crtc->x, - crtc->y); -#endif - - if (x < 0) { - xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); - x = 0; - } - if (y < 0) { - yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); - y = 0; - } - - position.enable = true; - position.x = x; - position.y = y; - - position.x_hotspot = xorigin; - position.y_hotspot = yorigin; - - if (acrtc_state->stream) { - if (!dc_stream_set_cursor_position( - acrtc_state->stream, - &position)) { - DRM_ERROR("DC failed to set cursor position\n"); - return -EINVAL; - } - } - - return 0; -} - -static bool fill_rects_from_plane_state( - const struct drm_plane_state *state, - struct dc_surface *surface) -{ - surface->src_rect.x = state->src_x >> 16; - surface->src_rect.y = state->src_y >> 16; - /*we ignore for now mantissa and do not to deal with floating pixels :(*/ - surface->src_rect.width = state->src_w >> 16; - - if (surface->src_rect.width == 0) - return false; - - surface->src_rect.height = state->src_h >> 16; - if (surface->src_rect.height == 0) - return false; - - surface->dst_rect.x = state->crtc_x; - surface->dst_rect.y = state->crtc_y; - - if (state->crtc_w == 0) - return false; - - surface->dst_rect.width = state->crtc_w; - - if (state->crtc_h == 0) - return false; - - surface->dst_rect.height = state->crtc_h; - - surface->clip_rect = surface->dst_rect; - - switch (state->rotation & DRM_MODE_ROTATE_MASK) { - case DRM_MODE_ROTATE_0: - surface->rotation = ROTATION_ANGLE_0; - break; - case DRM_MODE_ROTATE_90: - surface->rotation = ROTATION_ANGLE_90; - break; - case DRM_MODE_ROTATE_180: - surface->rotation = ROTATION_ANGLE_180; - break; - case DRM_MODE_ROTATE_270: - surface->rotation = ROTATION_ANGLE_270; - break; - default: - surface->rotation = ROTATION_ANGLE_0; - break; - } - - return true; -} -static int get_fb_info( - const struct amdgpu_framebuffer *amdgpu_fb, - uint64_t *tiling_flags, - uint64_t *fb_location) -{ - struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); - int r = amdgpu_bo_reserve(rbo, false); - if (unlikely(r)) { - DRM_ERROR("Unable to reserve buffer\n"); - return r; - } - - if (fb_location) - *fb_location = amdgpu_bo_gpu_offset(rbo); - - if (tiling_flags) - amdgpu_bo_get_tiling_flags(rbo, tiling_flags); - - amdgpu_bo_unreserve(rbo); - - return r; -} - -static int fill_plane_attributes_from_fb( - struct amdgpu_device *adev, - struct dc_surface *surface, - const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) -{ - uint64_t tiling_flags; - uint64_t fb_location = 0; - unsigned int awidth; - const struct drm_framebuffer *fb = &amdgpu_fb->base; - int ret = 0; - struct drm_format_name_buf format_name; - - ret = get_fb_info( - amdgpu_fb, - &tiling_flags, - addReq == true ? &fb_location:NULL); - - if (ret) - return ret; - - switch (fb->format->format) { - case DRM_FORMAT_C8: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; - break; - case DRM_FORMAT_RGB565: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; - break; - case DRM_FORMAT_XRGB8888: - case DRM_FORMAT_ARGB8888: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; - break; - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; - break; - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; - break; - case DRM_FORMAT_NV21: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; - break; - case DRM_FORMAT_NV12: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; - break; - default: - DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(fb->format->format, &format_name)); - return -EINVAL; - } - - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.type = PLN_ADDR_TYPE_GRAPHICS; - surface->address.grph.addr.low_part = lower_32_bits(fb_location); - surface->address.grph.addr.high_part = upper_32_bits(fb_location); - surface->plane_size.grph.surface_size.x = 0; - surface->plane_size.grph.surface_size.y = 0; - surface->plane_size.grph.surface_size.width = fb->width; - surface->plane_size.grph.surface_size.height = fb->height; - surface->plane_size.grph.surface_pitch = - fb->pitches[0] / fb->format->cpp[0]; - /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_SRGB; - - } else { - awidth = ALIGN(fb->width, 64); - surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - surface->address.video_progressive.luma_addr.low_part - = lower_32_bits(fb_location); - surface->address.video_progressive.chroma_addr.low_part - = lower_32_bits(fb_location) + - (awidth * fb->height); - surface->plane_size.video.luma_size.x = 0; - surface->plane_size.video.luma_size.y = 0; - surface->plane_size.video.luma_size.width = awidth; - surface->plane_size.video.luma_size.height = fb->height; - /* TODO: unhardcode */ - surface->plane_size.video.luma_pitch = awidth; - - surface->plane_size.video.chroma_size.x = 0; - surface->plane_size.video.chroma_size.y = 0; - surface->plane_size.video.chroma_size.width = awidth; - surface->plane_size.video.chroma_size.height = fb->height; - surface->plane_size.video.chroma_pitch = awidth / 2; - - /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_YCBCR709; - } - - memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - - /* Fill GFX params */ - if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) - { - unsigned bankw, bankh, mtaspect, tile_split, num_banks; - - bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); - bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); - mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); - tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); - num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); - - /* XXX fix me for VI */ - surface->tiling_info.gfx8.num_banks = num_banks; - surface->tiling_info.gfx8.array_mode = - DC_ARRAY_2D_TILED_THIN1; - surface->tiling_info.gfx8.tile_split = tile_split; - surface->tiling_info.gfx8.bank_width = bankw; - surface->tiling_info.gfx8.bank_height = bankh; - surface->tiling_info.gfx8.tile_aspect = mtaspect; - surface->tiling_info.gfx8.tile_mode = - DC_ADDR_SURF_MICRO_TILING_DISPLAY; - } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) - == DC_ARRAY_1D_TILED_THIN1) { - surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; - } - - surface->tiling_info.gfx8.pipe_config = - AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); - - if (adev->asic_type == CHIP_VEGA10 || - adev->asic_type == CHIP_RAVEN) { - /* Fill GFX9 params */ - surface->tiling_info.gfx9.num_pipes = - adev->gfx.config.gb_addr_config_fields.num_pipes; - surface->tiling_info.gfx9.num_banks = - adev->gfx.config.gb_addr_config_fields.num_banks; - surface->tiling_info.gfx9.pipe_interleave = - adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; - surface->tiling_info.gfx9.num_shader_engines = - adev->gfx.config.gb_addr_config_fields.num_se; - surface->tiling_info.gfx9.max_compressed_frags = - adev->gfx.config.gb_addr_config_fields.max_compress_frags; - surface->tiling_info.gfx9.num_rb_per_se = - adev->gfx.config.gb_addr_config_fields.num_rb_per_se; - surface->tiling_info.gfx9.swizzle = - AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); - surface->tiling_info.gfx9.shaderEnable = 1; - } - - surface->visible = true; - surface->scaling_quality.h_taps_c = 0; - surface->scaling_quality.v_taps_c = 0; - - /* is this needed? is surface zeroed at allocation? */ - surface->scaling_quality.h_taps = 0; - surface->scaling_quality.v_taps = 0; - surface->stereo_format = PLANE_STEREO_FORMAT_NONE; - - return ret; - -} - -#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256 - -static void fill_gamma_from_crtc_state( - const struct drm_crtc_state *crtc_state, - struct dc_surface *dc_surface) -{ - int i; - struct dc_gamma *gamma; - struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data; - - gamma = dc_create_gamma(); - - if (gamma == NULL) { - WARN_ON(1); - return; - } - - for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) { - gamma->red[i] = lut[i].red; - gamma->green[i] = lut[i].green; - gamma->blue[i] = lut[i].blue; - } - - dc_surface->gamma_correction = gamma; -} - -static int fill_plane_attributes( - struct amdgpu_device *adev, - struct dc_surface *surface, - struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state, - bool addrReq) -{ - const struct amdgpu_framebuffer *amdgpu_fb = - to_amdgpu_framebuffer(plane_state->fb); - const struct drm_crtc *crtc = plane_state->crtc; - struct dc_transfer_func *input_tf; - int ret = 0; - - if (!fill_rects_from_plane_state(plane_state, surface)) - return -EINVAL; - - ret = fill_plane_attributes_from_fb( - crtc->dev->dev_private, - surface, - amdgpu_fb, - addrReq); - - if (ret) - return ret; - - input_tf = dc_create_transfer_func(); - - if (input_tf == NULL) - return -ENOMEM; - - input_tf->type = TF_TYPE_PREDEFINED; - input_tf->tf = TRANSFER_FUNCTION_SRGB; - - surface->in_transfer_func = input_tf; - - /* In case of gamma set, update gamma value */ - if (crtc_state->gamma_lut) - fill_gamma_from_crtc_state(crtc_state, surface); - - return ret; -} - -/*****************************************************************************/ - -struct amdgpu_connector *aconnector_from_drm_crtc_id( - const struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_connector *connector; - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct amdgpu_connector *aconnector; - - list_for_each_entry(connector, - &dev->mode_config.connector_list, head) { - - aconnector = to_amdgpu_connector(connector); - - if (aconnector->base.state->crtc != &acrtc->base) - continue; - - /* Found the connector */ - return aconnector; - } - - /* If we get here, not found. */ - return NULL; -} - -static void update_stream_scaling_settings( - const struct drm_display_mode *mode, - const struct dm_connector_state *dm_state, - struct dc_stream *stream) -{ - enum amdgpu_rmx_type rmx_type; - - struct rect src = { 0 }; /* viewport in composition space*/ - struct rect dst = { 0 }; /* stream addressable area */ - - /* no mode. nothing to be done */ - if (!mode) - return; - - /* Full screen scaling by default */ - src.width = mode->hdisplay; - src.height = mode->vdisplay; - dst.width = stream->timing.h_addressable; - dst.height = stream->timing.v_addressable; - - rmx_type = dm_state->scaling; - if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) { - if (src.width * dst.height < - src.height * dst.width) { - /* height needs less upscaling/more downscaling */ - dst.width = src.width * - dst.height / src.height; - } else { - /* width needs less upscaling/more downscaling */ - dst.height = src.height * - dst.width / src.width; - } - } else if (rmx_type == RMX_CENTER) { - dst = src; - } - - dst.x = (stream->timing.h_addressable - dst.width) / 2; - dst.y = (stream->timing.v_addressable - dst.height) / 2; - - if (dm_state->underscan_enable) { - dst.x += dm_state->underscan_hborder / 2; - dst.y += dm_state->underscan_vborder / 2; - dst.width -= dm_state->underscan_hborder; - dst.height -= dm_state->underscan_vborder; - } - - stream->src = src; - stream->dst = dst; - - DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", - dst.x, dst.y, dst.width, dst.height); - -} - -static enum dc_color_depth convert_color_depth_from_display_info( - const struct drm_connector *connector) -{ - uint32_t bpc = connector->display_info.bpc; - - /* Limited color depth to 8bit - * TODO: Still need to handle deep color*/ - if (bpc > 8) - bpc = 8; - - switch (bpc) { - case 0: - /* Temporary Work around, DRM don't parse color depth for - * EDID revision before 1.4 - * TODO: Fix edid parsing - */ - return COLOR_DEPTH_888; - case 6: - return COLOR_DEPTH_666; - case 8: - return COLOR_DEPTH_888; - case 10: - return COLOR_DEPTH_101010; - case 12: - return COLOR_DEPTH_121212; - case 14: - return COLOR_DEPTH_141414; - case 16: - return COLOR_DEPTH_161616; - default: - return COLOR_DEPTH_UNDEFINED; - } -} - -static enum dc_aspect_ratio get_aspect_ratio( - const struct drm_display_mode *mode_in) -{ - int32_t width = mode_in->crtc_hdisplay * 9; - int32_t height = mode_in->crtc_vdisplay * 16; - if ((width - height) < 10 && (width - height) > -10) - return ASPECT_RATIO_16_9; - else - return ASPECT_RATIO_4_3; -} - -static enum dc_color_space get_output_color_space( - const struct dc_crtc_timing *dc_crtc_timing) -{ - enum dc_color_space color_space = COLOR_SPACE_SRGB; - - switch (dc_crtc_timing->pixel_encoding) { - case PIXEL_ENCODING_YCBCR422: - case PIXEL_ENCODING_YCBCR444: - case PIXEL_ENCODING_YCBCR420: - { - /* - * 27030khz is the separation point between HDTV and SDTV - * according to HDMI spec, we use YCbCr709 and YCbCr601 - * respectively - */ - if (dc_crtc_timing->pix_clk_khz > 27030) { - if (dc_crtc_timing->flags.Y_ONLY) - color_space = - COLOR_SPACE_YCBCR709_LIMITED; - else - color_space = COLOR_SPACE_YCBCR709; - } else { - if (dc_crtc_timing->flags.Y_ONLY) - color_space = - COLOR_SPACE_YCBCR601_LIMITED; - else - color_space = COLOR_SPACE_YCBCR601; - } - - } - break; - case PIXEL_ENCODING_RGB: - color_space = COLOR_SPACE_SRGB; - break; - - default: - WARN_ON(1); - break; - } - - return color_space; -} - -/*****************************************************************************/ - -static void fill_stream_properties_from_drm_display_mode( - struct dc_stream *stream, - const struct drm_display_mode *mode_in, - const struct drm_connector *connector) -{ - struct dc_crtc_timing *timing_out = &stream->timing; - memset(timing_out, 0, sizeof(struct dc_crtc_timing)); - - timing_out->h_border_left = 0; - timing_out->h_border_right = 0; - timing_out->v_border_top = 0; - timing_out->v_border_bottom = 0; - /* TODO: un-hardcode */ - - if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444) - && stream->sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) - timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444; - else - timing_out->pixel_encoding = PIXEL_ENCODING_RGB; - - timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; - timing_out->display_color_depth = convert_color_depth_from_display_info( - connector); - timing_out->scan_type = SCANNING_TYPE_NODATA; - timing_out->hdmi_vic = 0; - timing_out->vic = drm_match_cea_mode(mode_in); - - timing_out->h_addressable = mode_in->crtc_hdisplay; - timing_out->h_total = mode_in->crtc_htotal; - timing_out->h_sync_width = - mode_in->crtc_hsync_end - mode_in->crtc_hsync_start; - timing_out->h_front_porch = - mode_in->crtc_hsync_start - mode_in->crtc_hdisplay; - timing_out->v_total = mode_in->crtc_vtotal; - timing_out->v_addressable = mode_in->crtc_vdisplay; - timing_out->v_front_porch = - mode_in->crtc_vsync_start - mode_in->crtc_vdisplay; - timing_out->v_sync_width = - mode_in->crtc_vsync_end - mode_in->crtc_vsync_start; - timing_out->pix_clk_khz = mode_in->crtc_clock; - timing_out->aspect_ratio = get_aspect_ratio(mode_in); - if (mode_in->flags & DRM_MODE_FLAG_PHSYNC) - timing_out->flags.HSYNC_POSITIVE_POLARITY = 1; - if (mode_in->flags & DRM_MODE_FLAG_PVSYNC) - timing_out->flags.VSYNC_POSITIVE_POLARITY = 1; - - stream->output_color_space = get_output_color_space(timing_out); - - { - struct dc_transfer_func *tf = dc_create_transfer_func(); - tf->type = TF_TYPE_PREDEFINED; - tf->tf = TRANSFER_FUNCTION_SRGB; - stream->out_transfer_func = tf; - } -} - -static void fill_audio_info( - struct audio_info *audio_info, - const struct drm_connector *drm_connector, - const struct dc_sink *dc_sink) -{ - int i = 0; - int cea_revision = 0; - const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps; - - audio_info->manufacture_id = edid_caps->manufacturer_id; - audio_info->product_id = edid_caps->product_id; - - cea_revision = drm_connector->display_info.cea_rev; - - while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS && - edid_caps->display_name[i]) { - audio_info->display_name[i] = edid_caps->display_name[i]; - i++; - } - - if(cea_revision >= 3) { - audio_info->mode_count = edid_caps->audio_mode_count; - - for (i = 0; i < audio_info->mode_count; ++i) { - audio_info->modes[i].format_code = - (enum audio_format_code) - (edid_caps->audio_modes[i].format_code); - audio_info->modes[i].channel_count = - edid_caps->audio_modes[i].channel_count; - audio_info->modes[i].sample_rates.all = - edid_caps->audio_modes[i].sample_rate; - audio_info->modes[i].sample_size = - edid_caps->audio_modes[i].sample_size; - } - } - - audio_info->flags.all = edid_caps->speaker_flags; - - /* TODO: We only check for the progressive mode, check for interlace mode too */ - if(drm_connector->latency_present[0]) { - audio_info->video_latency = drm_connector->video_latency[0]; - audio_info->audio_latency = drm_connector->audio_latency[0]; - } - - /* TODO: For DP, video and audio latency should be calculated from DPCD caps */ - -} - -static void copy_crtc_timing_for_drm_display_mode( - const struct drm_display_mode *src_mode, - struct drm_display_mode *dst_mode) -{ - dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; - dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; - dst_mode->crtc_clock = src_mode->crtc_clock; - dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; - dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; - dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start; - dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; - dst_mode->crtc_htotal = src_mode->crtc_htotal; - dst_mode->crtc_hskew = src_mode->crtc_hskew; - dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start; - dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end; - dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start; - dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end; - dst_mode->crtc_vtotal = src_mode->crtc_vtotal; -} - -static void decide_crtc_timing_for_drm_display_mode( - struct drm_display_mode *drm_mode, - const struct drm_display_mode *native_mode, - bool scale_enabled) -{ - if (scale_enabled) { - copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); - } else if (native_mode->clock == drm_mode->clock && - native_mode->htotal == drm_mode->htotal && - native_mode->vtotal == drm_mode->vtotal) { - copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); - } else { - /* no scaling nor amdgpu inserted, no need to patch */ - } -} - -static struct dc_stream *create_stream_for_sink( - struct amdgpu_connector *aconnector, - const struct drm_display_mode *drm_mode, - const struct dm_connector_state *dm_state) -{ - struct drm_display_mode *preferred_mode = NULL; - const struct drm_connector *drm_connector; - struct dc_stream *stream = NULL; - struct drm_display_mode mode = *drm_mode; - bool native_mode_found = false; - - if (NULL == aconnector) { - DRM_ERROR("aconnector is NULL!\n"); - goto drm_connector_null; - } - - if (NULL == dm_state) { - DRM_ERROR("dm_state is NULL!\n"); - goto dm_state_null; - } - - drm_connector = &aconnector->base; - stream = dc_create_stream_for_sink(aconnector->dc_sink); - - if (NULL == stream) { - DRM_ERROR("Failed to create stream for sink!\n"); - goto stream_create_fail; - } - - list_for_each_entry(preferred_mode, &aconnector->base.modes, head) { - /* Search for preferred mode */ - if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { - native_mode_found = true; - break; - } - } - if (!native_mode_found) - preferred_mode = list_first_entry_or_null( - &aconnector->base.modes, - struct drm_display_mode, - head); - - if (NULL == preferred_mode) { - /* This may not be an error, the use case is when we we have no - * usermode calls to reset and set mode upon hotplug. In this - * case, we call set mode ourselves to restore the previous mode - * and the modelist may not be filled in in time. - */ - DRM_INFO("No preferred mode found\n"); - } else { - decide_crtc_timing_for_drm_display_mode( - &mode, preferred_mode, - dm_state->scaling != RMX_OFF); - } - - fill_stream_properties_from_drm_display_mode(stream, - &mode, &aconnector->base); - update_stream_scaling_settings(&mode, dm_state, stream); - - fill_audio_info( - &stream->audio_info, - drm_connector, - aconnector->dc_sink); - -stream_create_fail: -dm_state_null: -drm_connector_null: - return stream; -} - -void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) -{ - drm_crtc_cleanup(crtc); - kfree(crtc); -} - -static void dm_crtc_destroy_state(struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - struct dm_crtc_state *cur = to_dm_crtc_state(state); - - /* TODO Destroy dc_stream objects are stream object is flattened */ - if (cur->stream) - dc_stream_release(cur->stream); - - - __drm_atomic_helper_crtc_destroy_state(state); - - - kfree(state); -} - -static void dm_crtc_reset_state(struct drm_crtc *crtc) -{ - struct dm_crtc_state *state; - - if (crtc->state) - dm_crtc_destroy_state(crtc, crtc->state); - - state = kzalloc(sizeof(*state), GFP_KERNEL); - if (WARN_ON(!state)) - return; - - crtc->state = &state->base; - crtc->state->crtc = crtc; - -} - -static struct drm_crtc_state * -dm_crtc_duplicate_state(struct drm_crtc *crtc) -{ - struct dm_crtc_state *state, *cur; - - cur = to_dm_crtc_state(crtc->state); - - if (WARN_ON(!crtc->state)) - return NULL; - - state = dm_alloc(sizeof(*state)); - - __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); - - if (cur->stream) { - state->stream = cur->stream; - dc_stream_retain(state->stream); - } - - /* TODO Duplicate dc_stream after objects are stream object is flattened */ - - return &state->base; -} - -/* Implemented only the options currently availible for the driver */ -static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { - .reset = dm_crtc_reset_state, - .destroy = amdgpu_dm_crtc_destroy, - .gamma_set = drm_atomic_helper_legacy_gamma_set, - .set_config = drm_atomic_helper_set_config, - .page_flip = drm_atomic_helper_page_flip, - .atomic_duplicate_state = dm_crtc_duplicate_state, - .atomic_destroy_state = dm_crtc_destroy_state, -}; - -static enum drm_connector_status -amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) -{ - bool connected; - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - - /* Notes: - * 1. This interface is NOT called in context of HPD irq. - * 2. This interface *is called* in context of user-mode ioctl. Which - * makes it a bad place for *any* MST-related activit. */ - - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) - connected = (aconnector->dc_sink != NULL); - else - connected = (aconnector->base.force == DRM_FORCE_ON); - - return (connected ? connector_status_connected : - connector_status_disconnected); -} - -int amdgpu_dm_connector_atomic_set_property( - struct drm_connector *connector, - struct drm_connector_state *connector_state, - struct drm_property *property, - uint64_t val) -{ - struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; - struct dm_connector_state *dm_old_state = - to_dm_connector_state(connector->state); - struct dm_connector_state *dm_new_state = - to_dm_connector_state(connector_state); - - int ret = -EINVAL; - - if (property == dev->mode_config.scaling_mode_property) { - enum amdgpu_rmx_type rmx_type; - - switch (val) { - case DRM_MODE_SCALE_CENTER: - rmx_type = RMX_CENTER; - break; - case DRM_MODE_SCALE_ASPECT: - rmx_type = RMX_ASPECT; - break; - case DRM_MODE_SCALE_FULLSCREEN: - rmx_type = RMX_FULL; - break; - case DRM_MODE_SCALE_NONE: - default: - rmx_type = RMX_OFF; - break; - } - - if (dm_old_state->scaling == rmx_type) - return 0; - - dm_new_state->scaling = rmx_type; - ret = 0; - } else if (property == adev->mode_info.underscan_hborder_property) { - dm_new_state->underscan_hborder = val; - ret = 0; - } else if (property == adev->mode_info.underscan_vborder_property) { - dm_new_state->underscan_vborder = val; - ret = 0; - } else if (property == adev->mode_info.underscan_property) { - dm_new_state->underscan_enable = val; - ret = 0; - } - - return ret; -} - -int amdgpu_dm_connector_atomic_get_property( - struct drm_connector *connector, - const struct drm_connector_state *state, - struct drm_property *property, - uint64_t *val) -{ - struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; - struct dm_connector_state *dm_state = - to_dm_connector_state(state); - int ret = -EINVAL; - - if (property == dev->mode_config.scaling_mode_property) { - switch (dm_state->scaling) { - case RMX_CENTER: - *val = DRM_MODE_SCALE_CENTER; - break; - case RMX_ASPECT: - *val = DRM_MODE_SCALE_ASPECT; - break; - case RMX_FULL: - *val = DRM_MODE_SCALE_FULLSCREEN; - break; - case RMX_OFF: - default: - *val = DRM_MODE_SCALE_NONE; - break; - } - ret = 0; - } else if (property == adev->mode_info.underscan_hborder_property) { - *val = dm_state->underscan_hborder; - ret = 0; - } else if (property == adev->mode_info.underscan_vborder_property) { - *val = dm_state->underscan_vborder; - ret = 0; - } else if (property == adev->mode_info.underscan_property) { - *val = dm_state->underscan_enable; - ret = 0; - } - return ret; -} - -void amdgpu_dm_connector_destroy(struct drm_connector *connector) -{ - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - const struct dc_link *link = aconnector->dc_link; - struct amdgpu_device *adev = connector->dev->dev_private; - struct amdgpu_display_manager *dm = &adev->dm; -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - - if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) { - amdgpu_dm_register_backlight_device(dm); - - if (dm->backlight_dev) { - backlight_device_unregister(dm->backlight_dev); - dm->backlight_dev = NULL; - } - - } -#endif - drm_connector_unregister(connector); - drm_connector_cleanup(connector); - kfree(connector); -} - -void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) -{ - struct dm_connector_state *state = - to_dm_connector_state(connector->state); - - kfree(state); - - state = kzalloc(sizeof(*state), GFP_KERNEL); - - if (state) { - state->scaling = RMX_OFF; - state->underscan_enable = false; - state->underscan_hborder = 0; - state->underscan_vborder = 0; - - connector->state = &state->base; - connector->state->connector = connector; - } -} - -struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( - struct drm_connector *connector) -{ - struct dm_connector_state *state = - to_dm_connector_state(connector->state); - - struct dm_connector_state *new_state = - kmemdup(state, sizeof(*state), GFP_KERNEL); - - if (new_state) { - __drm_atomic_helper_connector_duplicate_state(connector, - &new_state->base); - return &new_state->base; - } - - return NULL; -} - -static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { - .reset = amdgpu_dm_connector_funcs_reset, - .detect = amdgpu_dm_connector_detect, - .fill_modes = drm_helper_probe_single_connector_modes, - .destroy = amdgpu_dm_connector_destroy, - .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, - .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, - .atomic_set_property = amdgpu_dm_connector_atomic_set_property, - .atomic_get_property = amdgpu_dm_connector_atomic_get_property -}; - -static struct drm_encoder *best_encoder(struct drm_connector *connector) -{ - int enc_id = connector->encoder_ids[0]; - struct drm_mode_object *obj; - struct drm_encoder *encoder; - - DRM_DEBUG_KMS("Finding the best encoder\n"); - - /* pick the encoder ids */ - if (enc_id) { - obj = drm_mode_object_find(connector->dev, enc_id, DRM_MODE_OBJECT_ENCODER); - if (!obj) { - DRM_ERROR("Couldn't find a matching encoder for our connector\n"); - return NULL; - } - encoder = obj_to_encoder(obj); - return encoder; - } - DRM_ERROR("No encoder id\n"); - return NULL; -} - -static int get_modes(struct drm_connector *connector) -{ - return amdgpu_dm_connector_get_modes(connector); -} - -static void create_eml_sink(struct amdgpu_connector *aconnector) -{ - struct dc_sink_init_data init_params = { - .link = aconnector->dc_link, - .sink_signal = SIGNAL_TYPE_VIRTUAL - }; - struct edid *edid = (struct edid *) aconnector->base.edid_blob_ptr->data; - - if (!aconnector->base.edid_blob_ptr || - !aconnector->base.edid_blob_ptr->data) { - DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n", - aconnector->base.name); - - aconnector->base.force = DRM_FORCE_OFF; - aconnector->base.override_edid = false; - return; - } - - aconnector->edid = edid; - - aconnector->dc_em_sink = dc_link_add_remote_sink( - aconnector->dc_link, - (uint8_t *)edid, - (edid->extensions + 1) * EDID_LENGTH, - &init_params); - - if (aconnector->base.force - == DRM_FORCE_ON) - aconnector->dc_sink = aconnector->dc_link->local_sink ? - aconnector->dc_link->local_sink : - aconnector->dc_em_sink; -} - -static void handle_edid_mgmt(struct amdgpu_connector *aconnector) -{ - struct dc_link *link = (struct dc_link *)aconnector->dc_link; - - /* In case of headless boot with force on for DP managed connector - * Those settings have to be != 0 to get initial modeset - */ - if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) { - link->verified_link_cap.lane_count = LANE_COUNT_FOUR; - link->verified_link_cap.link_rate = LINK_RATE_HIGH2; - } - - - aconnector->base.override_edid = true; - create_eml_sink(aconnector); -} - -int amdgpu_dm_connector_mode_valid( - struct drm_connector *connector, - struct drm_display_mode *mode) -{ - int result = MODE_ERROR; - struct dc_sink *dc_sink; - struct amdgpu_device *adev = connector->dev->dev_private; - /* TODO: Unhardcode stream count */ - struct dc_stream *stream; - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - - if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || - (mode->flags & DRM_MODE_FLAG_DBLSCAN)) - return result; - - /* Only run this the first time mode_valid is called to initilialize - * EDID mgmt - */ - if (aconnector->base.force != DRM_FORCE_UNSPECIFIED && - !aconnector->dc_em_sink) - handle_edid_mgmt(aconnector); - - dc_sink = to_amdgpu_connector(connector)->dc_sink; - - if (NULL == dc_sink) { - DRM_ERROR("dc_sink is NULL!\n"); - goto fail; - } - - stream = dc_create_stream_for_sink(dc_sink); - if (NULL == stream) { - DRM_ERROR("Failed to create stream for sink!\n"); - goto fail; - } - - drm_mode_set_crtcinfo(mode, 0); - fill_stream_properties_from_drm_display_mode(stream, mode, connector); - - stream->src.width = mode->hdisplay; - stream->src.height = mode->vdisplay; - stream->dst = stream->src; - - if (dc_validate_stream(adev->dm.dc, stream)) - result = MODE_OK; - - dc_stream_release(stream); - -fail: - /* TODO: error handling*/ - return result; -} - -static const struct drm_connector_helper_funcs -amdgpu_dm_connector_helper_funcs = { - /* - * If hotplug a second bigger display in FB Con mode, bigger resolution - * modes will be filtered by drm_mode_validate_size(), and those modes - * is missing after user start lightdm. So we need to renew modes list. - * in get_modes call back, not just return the modes count - */ - .get_modes = get_modes, - .mode_valid = amdgpu_dm_connector_mode_valid, - .best_encoder = best_encoder -}; - -static void dm_crtc_helper_disable(struct drm_crtc *crtc) -{ -} - -static int dm_crtc_helper_atomic_check( - struct drm_crtc *crtc, - struct drm_crtc_state *state) -{ - struct amdgpu_device *adev = crtc->dev->dev_private; - struct dc *dc = adev->dm.dc; - struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); - int ret = -EINVAL; - - if (unlikely(!dm_crtc_state->stream && modeset_required(state))) { - WARN_ON(1); - return ret; - } - - /* In some use cases, like reset, no stream is attached */ - if (!dm_crtc_state->stream) - return 0; - - if (dc_validate_stream(dc, dm_crtc_state->stream)) - return 0; - - return ret; -} - -static bool dm_crtc_helper_mode_fixup( - struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) -{ - return true; -} - -static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { - .disable = dm_crtc_helper_disable, - .atomic_check = dm_crtc_helper_atomic_check, - .mode_fixup = dm_crtc_helper_mode_fixup -}; - -static void dm_encoder_helper_disable(struct drm_encoder *encoder) -{ - -} - -static int dm_encoder_helper_atomic_check( - struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - return 0; -} - -const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { - .disable = dm_encoder_helper_disable, - .atomic_check = dm_encoder_helper_atomic_check -}; - -static void dm_drm_plane_reset(struct drm_plane *plane) -{ - struct dm_plane_state *amdgpu_state = NULL; - - if (plane->state) - plane->funcs->atomic_destroy_state(plane, plane->state); - - amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); - - if (amdgpu_state) { - plane->state = &amdgpu_state->base; - plane->state->plane = plane; - plane->state->rotation = DRM_MODE_ROTATE_0; - } - else - WARN_ON(1); -} - -static struct drm_plane_state * -dm_drm_plane_duplicate_state(struct drm_plane *plane) -{ - struct dm_plane_state *dm_plane_state, *old_dm_plane_state; - - old_dm_plane_state = to_dm_plane_state(plane->state); - dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL); - if (!dm_plane_state) - return NULL; - - __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); - - if (old_dm_plane_state->surface) { - dm_plane_state->surface = old_dm_plane_state->surface; - dc_surface_retain(dm_plane_state->surface); - } - - return &dm_plane_state->base; -} - -void dm_drm_plane_destroy_state(struct drm_plane *plane, - struct drm_plane_state *state) -{ - struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); - - __drm_atomic_helper_plane_destroy_state(state); - kfree(dm_plane_state); -} - -static const struct drm_plane_funcs dm_plane_funcs = { - .update_plane = drm_atomic_helper_update_plane, - .disable_plane = drm_atomic_helper_disable_plane, - .destroy = drm_plane_cleanup, - .reset = dm_drm_plane_reset, - .atomic_duplicate_state = dm_drm_plane_duplicate_state, - .atomic_destroy_state = dm_drm_plane_destroy_state, -}; - -static int dm_plane_helper_prepare_fb( - struct drm_plane *plane, - struct drm_plane_state *new_state) -{ - struct amdgpu_framebuffer *afb; - struct drm_gem_object *obj; - struct amdgpu_bo *rbo; - int r; - struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; - unsigned int awidth; - - dm_plane_state_old = to_dm_plane_state(plane->state); - dm_plane_state_new = to_dm_plane_state(new_state); - - if (!new_state->fb) { - DRM_DEBUG_KMS("No FB bound\n"); - return 0; - } - - afb = to_amdgpu_framebuffer(new_state->fb); - - obj = afb->obj; - rbo = gem_to_amdgpu_bo(obj); - r = amdgpu_bo_reserve(rbo, false); - if (unlikely(r != 0)) - return r; - - r = amdgpu_bo_pin(rbo, AMDGPU_GEM_DOMAIN_VRAM, &afb->address); - - - amdgpu_bo_unreserve(rbo); - - if (unlikely(r != 0)) { - DRM_ERROR("Failed to pin framebuffer\n"); - return r; - } - - amdgpu_bo_ref(rbo); - - if (dm_plane_state_new->surface && - dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_surface *surface = dm_plane_state_new->surface; - - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.grph.addr.low_part = lower_32_bits(afb->address); - surface->address.grph.addr.high_part = upper_32_bits(afb->address); - } else { - awidth = ALIGN(new_state->fb->width, 64); - surface->address.video_progressive.luma_addr.low_part - = lower_32_bits(afb->address); - surface->address.video_progressive.chroma_addr.low_part - = lower_32_bits(afb->address) + - (awidth * new_state->fb->height); - } - } - - /* It's a hack for s3 since in 4.9 kernel filter out cursor buffer - * prepare and cleanup in drm_atomic_helper_prepare_planes - * and drm_atomic_helper_cleanup_planes because fb doens't in s3. - * IN 4.10 kernel this code should be removed and amdgpu_device_suspend - * code touching fram buffers should be avoided for DC. - */ - if (plane->type == DRM_PLANE_TYPE_CURSOR) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(new_state->crtc); - - acrtc->cursor_bo = obj; - } - return 0; -} - -static void dm_plane_helper_cleanup_fb( - struct drm_plane *plane, - struct drm_plane_state *old_state) -{ - struct amdgpu_bo *rbo; - struct amdgpu_framebuffer *afb; - int r; - - if (!old_state->fb) - return; - - afb = to_amdgpu_framebuffer(old_state->fb); - rbo = gem_to_amdgpu_bo(afb->obj); - r = amdgpu_bo_reserve(rbo, false); - if (unlikely(r)) { - DRM_ERROR("failed to reserve rbo before unpin\n"); - return; - } else { - amdgpu_bo_unpin(rbo); - amdgpu_bo_unreserve(rbo); - amdgpu_bo_unref(&rbo); - }; -} - -int dm_create_validation_set_for_connector(struct drm_connector *connector, - struct drm_display_mode *mode, struct dc_validation_set *val_set) -{ - int result = MODE_ERROR; - struct dc_sink *dc_sink = - to_amdgpu_connector(connector)->dc_sink; - /* TODO: Unhardcode stream count */ - struct dc_stream *stream; - - if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || - (mode->flags & DRM_MODE_FLAG_DBLSCAN)) - return result; - - if (NULL == dc_sink) { - DRM_ERROR("dc_sink is NULL!\n"); - return result; - } - - stream = dc_create_stream_for_sink(dc_sink); - - if (NULL == stream) { - DRM_ERROR("Failed to create stream for sink!\n"); - return result; - } - - drm_mode_set_crtcinfo(mode, 0); - - fill_stream_properties_from_drm_display_mode(stream, mode, connector); - - val_set->stream = stream; - - stream->src.width = mode->hdisplay; - stream->src.height = mode->vdisplay; - stream->dst = stream->src; - - return MODE_OK; -} - -static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { - .prepare_fb = dm_plane_helper_prepare_fb, - .cleanup_fb = dm_plane_helper_cleanup_fb, -}; - -/* - * TODO: these are currently initialized to rgb formats only. - * For future use cases we should either initialize them dynamically based on - * plane capabilities, or initialize this array to all formats, so internal drm - * check will succeed, and let DC to implement proper check - */ -static uint32_t rgb_formats[] = { - DRM_FORMAT_RGB888, - DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGBA8888, - DRM_FORMAT_XRGB2101010, - DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ARGB2101010, - DRM_FORMAT_ABGR2101010, -}; - -static uint32_t yuv_formats[] = { - DRM_FORMAT_NV12, - DRM_FORMAT_NV21, -}; - -static const u32 cursor_formats[] = { - DRM_FORMAT_ARGB8888 -}; - -int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs) -{ - int res = -EPERM; - - switch (aplane->base.type) { - case DRM_PLANE_TYPE_PRIMARY: - aplane->base.format_default = true; - - res = drm_universal_plane_init( - dm->adev->ddev, - &aplane->base, - possible_crtcs, - &dm_plane_funcs, - rgb_formats, - ARRAY_SIZE(rgb_formats), - NULL, aplane->base.type, NULL); - break; - case DRM_PLANE_TYPE_OVERLAY: - res = drm_universal_plane_init( - dm->adev->ddev, - &aplane->base, - possible_crtcs, - &dm_plane_funcs, - yuv_formats, - ARRAY_SIZE(yuv_formats), - NULL, aplane->base.type, NULL); - break; - case DRM_PLANE_TYPE_CURSOR: - res = drm_universal_plane_init( - dm->adev->ddev, - &aplane->base, - possible_crtcs, - &dm_plane_funcs, - cursor_formats, - ARRAY_SIZE(cursor_formats), - NULL, aplane->base.type, NULL); - break; - } - - drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); - - return res; -} - -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct drm_plane *plane, - uint32_t crtc_index) -{ - struct amdgpu_crtc *acrtc = NULL; - struct amdgpu_plane *cursor_plane; - - int res = -ENOMEM; - - cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL); - if (!cursor_plane) - goto fail; - - cursor_plane->base.type = DRM_PLANE_TYPE_CURSOR; - res = amdgpu_dm_plane_init(dm, cursor_plane, 0); - - acrtc = kzalloc(sizeof(struct amdgpu_crtc), GFP_KERNEL); - if (!acrtc) - goto fail; - - res = drm_crtc_init_with_planes( - dm->ddev, - &acrtc->base, - plane, - &cursor_plane->base, - &amdgpu_dm_crtc_funcs, NULL); - - if (res) - goto fail; - - drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); - - acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; - acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; - - acrtc->crtc_id = crtc_index; - acrtc->base.enabled = false; - - dm->adev->mode_info.crtcs[crtc_index] = acrtc; - drm_mode_crtc_set_gamma_size(&acrtc->base, 256); - - return 0; - -fail: - if (acrtc) - kfree(acrtc); - if (cursor_plane) - kfree(cursor_plane); - acrtc->crtc_id = -1; - return res; -} - - -static int to_drm_connector_type(enum signal_type st) -{ - switch (st) { - case SIGNAL_TYPE_HDMI_TYPE_A: - return DRM_MODE_CONNECTOR_HDMIA; - case SIGNAL_TYPE_EDP: - return DRM_MODE_CONNECTOR_eDP; - case SIGNAL_TYPE_RGB: - return DRM_MODE_CONNECTOR_VGA; - case SIGNAL_TYPE_DISPLAY_PORT: - case SIGNAL_TYPE_DISPLAY_PORT_MST: - return DRM_MODE_CONNECTOR_DisplayPort; - case SIGNAL_TYPE_DVI_DUAL_LINK: - case SIGNAL_TYPE_DVI_SINGLE_LINK: - return DRM_MODE_CONNECTOR_DVID; - case SIGNAL_TYPE_VIRTUAL: - return DRM_MODE_CONNECTOR_VIRTUAL; - - default: - return DRM_MODE_CONNECTOR_Unknown; - } -} - -static void amdgpu_dm_get_native_mode(struct drm_connector *connector) -{ - const struct drm_connector_helper_funcs *helper = - connector->helper_private; - struct drm_encoder *encoder; - struct amdgpu_encoder *amdgpu_encoder; - - encoder = helper->best_encoder(connector); - - if (encoder == NULL) - return; - - amdgpu_encoder = to_amdgpu_encoder(encoder); - - amdgpu_encoder->native_mode.clock = 0; - - if (!list_empty(&connector->probed_modes)) { - struct drm_display_mode *preferred_mode = NULL; - list_for_each_entry(preferred_mode, - &connector->probed_modes, - head) { - if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { - amdgpu_encoder->native_mode = *preferred_mode; - } - break; - } - - } -} - -static struct drm_display_mode *amdgpu_dm_create_common_mode( - struct drm_encoder *encoder, char *name, - int hdisplay, int vdisplay) -{ - struct drm_device *dev = encoder->dev; - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct drm_display_mode *mode = NULL; - struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; - - mode = drm_mode_duplicate(dev, native_mode); - - if(mode == NULL) - return NULL; - - mode->hdisplay = hdisplay; - mode->vdisplay = vdisplay; - mode->type &= ~DRM_MODE_TYPE_PREFERRED; - strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); - - return mode; - -} - -static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, - struct drm_connector *connector) -{ - struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); - struct drm_display_mode *mode = NULL; - struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); - int i; - int n; - struct mode_size { - char name[DRM_DISPLAY_MODE_LEN]; - int w; - int h; - }common_modes[] = { - { "640x480", 640, 480}, - { "800x600", 800, 600}, - { "1024x768", 1024, 768}, - { "1280x720", 1280, 720}, - { "1280x800", 1280, 800}, - {"1280x1024", 1280, 1024}, - { "1440x900", 1440, 900}, - {"1680x1050", 1680, 1050}, - {"1600x1200", 1600, 1200}, - {"1920x1080", 1920, 1080}, - {"1920x1200", 1920, 1200} - }; - - n = sizeof(common_modes) / sizeof(common_modes[0]); - - for (i = 0; i < n; i++) { - struct drm_display_mode *curmode = NULL; - bool mode_existed = false; - - if (common_modes[i].w > native_mode->hdisplay || - common_modes[i].h > native_mode->vdisplay || - (common_modes[i].w == native_mode->hdisplay && - common_modes[i].h == native_mode->vdisplay)) - continue; - - list_for_each_entry(curmode, &connector->probed_modes, head) { - if (common_modes[i].w == curmode->hdisplay && - common_modes[i].h == curmode->vdisplay) { - mode_existed = true; - break; - } - } - - if (mode_existed) - continue; - - mode = amdgpu_dm_create_common_mode(encoder, - common_modes[i].name, common_modes[i].w, - common_modes[i].h); - drm_mode_probed_add(connector, mode); - amdgpu_connector->num_modes++; - } -} - -static void amdgpu_dm_connector_ddc_get_modes( - struct drm_connector *connector, - struct edid *edid) -{ - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); - - if (edid) { - /* empty probed_modes */ - INIT_LIST_HEAD(&connector->probed_modes); - amdgpu_connector->num_modes = - drm_add_edid_modes(connector, edid); - - drm_edid_to_eld(connector, edid); - - amdgpu_dm_get_native_mode(connector); - } else - amdgpu_connector->num_modes = 0; -} - -int amdgpu_dm_connector_get_modes(struct drm_connector *connector) -{ - const struct drm_connector_helper_funcs *helper = - connector->helper_private; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); - struct drm_encoder *encoder; - struct edid *edid = amdgpu_connector->edid; - - encoder = helper->best_encoder(connector); - - amdgpu_dm_connector_ddc_get_modes(connector, edid); - amdgpu_dm_connector_add_common_modes(encoder, connector); - return amdgpu_connector->num_modes; -} - -void amdgpu_dm_connector_init_helper( - struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, - int connector_type, - struct dc_link *link, - int link_index) -{ - struct amdgpu_device *adev = dm->ddev->dev_private; - - aconnector->connector_id = link_index; - aconnector->dc_link = link; - aconnector->base.interlace_allowed = false; - aconnector->base.doublescan_allowed = false; - aconnector->base.stereo_allowed = false; - aconnector->base.dpms = DRM_MODE_DPMS_OFF; - aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ - - mutex_init(&aconnector->hpd_lock); - - /*configure suport HPD hot plug connector_>polled default value is 0 - * which means HPD hot plug not supported*/ - switch (connector_type) { - case DRM_MODE_CONNECTOR_HDMIA: - aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; - break; - case DRM_MODE_CONNECTOR_DisplayPort: - aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; - break; - case DRM_MODE_CONNECTOR_DVID: - aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; - break; - default: - break; - } - - drm_object_attach_property(&aconnector->base.base, - dm->ddev->mode_config.scaling_mode_property, - DRM_MODE_SCALE_NONE); - - drm_object_attach_property(&aconnector->base.base, - adev->mode_info.underscan_property, - UNDERSCAN_OFF); - drm_object_attach_property(&aconnector->base.base, - adev->mode_info.underscan_hborder_property, - 0); - drm_object_attach_property(&aconnector->base.base, - adev->mode_info.underscan_vborder_property, - 0); - -} - -int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg *msgs, int num) -{ - struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); - struct ddc_service *ddc_service = i2c->ddc_service; - struct i2c_command cmd; - int i; - int result = -EIO; - - cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL); - - if (!cmd.payloads) - return result; - - cmd.number_of_payloads = num; - cmd.engine = I2C_COMMAND_ENGINE_DEFAULT; - cmd.speed = 100; - - for (i = 0; i < num; i++) { - cmd.payloads[i].write = !(msgs[i].flags & I2C_M_RD); - cmd.payloads[i].address = msgs[i].addr; - cmd.payloads[i].length = msgs[i].len; - cmd.payloads[i].data = msgs[i].buf; - } - - if (dal_i2caux_submit_i2c_command( - ddc_service->ctx->i2caux, - ddc_service->ddc_pin, - &cmd)) - result = num; - - kfree(cmd.payloads); - return result; -} - -u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) -{ - return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; -} - -static const struct i2c_algorithm amdgpu_dm_i2c_algo = { - .master_xfer = amdgpu_dm_i2c_xfer, - .functionality = amdgpu_dm_i2c_func, -}; - -static struct amdgpu_i2c_adapter *create_i2c( - struct ddc_service *ddc_service, - int link_index, - int *res) -{ - struct amdgpu_device *adev = ddc_service->ctx->driver_context; - struct amdgpu_i2c_adapter *i2c; - - i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL); - i2c->base.owner = THIS_MODULE; - i2c->base.class = I2C_CLASS_DDC; - i2c->base.dev.parent = &adev->pdev->dev; - i2c->base.algo = &amdgpu_dm_i2c_algo; - snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); - i2c_set_adapdata(&i2c->base, i2c); - i2c->ddc_service = ddc_service; - - return i2c; -} - -/* Note: this function assumes that dc_link_detect() was called for the - * dc_link which will be represented by this aconnector. */ -int amdgpu_dm_connector_init( - struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, - uint32_t link_index, - struct amdgpu_encoder *aencoder) -{ - int res = 0; - int connector_type; - struct dc *dc = dm->dc; - struct dc_link *link = dc_get_link_at_index(dc, link_index); - struct amdgpu_i2c_adapter *i2c; - ((struct dc_link *)link)->priv = aconnector; - - DRM_DEBUG_KMS("%s()\n", __func__); - - i2c = create_i2c(link->ddc, link->link_index, &res); - aconnector->i2c = i2c; - res = i2c_add_adapter(&i2c->base); - - if (res) { - DRM_ERROR("Failed to register hw i2c %d\n", link->link_index); - goto out_free; - } - - connector_type = to_drm_connector_type(link->connector_signal); - - res = drm_connector_init( - dm->ddev, - &aconnector->base, - &amdgpu_dm_connector_funcs, - connector_type); - - if (res) { - DRM_ERROR("connector_init failed\n"); - aconnector->connector_id = -1; - goto out_free; - } - - drm_connector_helper_add( - &aconnector->base, - &amdgpu_dm_connector_helper_funcs); - - amdgpu_dm_connector_init_helper( - dm, - aconnector, - connector_type, - link, - link_index); - - drm_mode_connector_attach_encoder( - &aconnector->base, &aencoder->base); - - drm_connector_register(&aconnector->base); - - if (connector_type == DRM_MODE_CONNECTOR_DisplayPort - || connector_type == DRM_MODE_CONNECTOR_eDP) - amdgpu_dm_initialize_dp_connector(dm, aconnector); - -#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\ - defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) - - /* NOTE: this currently will create backlight device even if a panel - * is not connected to the eDP/LVDS connector. - * - * This is less than ideal but we don't have sink information at this - * stage since detection happens after. We can't do detection earlier - * since MST detection needs connectors to be created first. - */ - if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) { - /* Event if registration failed, we should continue with - * DM initialization because not having a backlight control - * is better then a black screen. */ - amdgpu_dm_register_backlight_device(dm); - - if (dm->backlight_dev) - dm->backlight_link = link; - } -#endif - -out_free: - if (res) { - kfree(i2c); - aconnector->i2c = NULL; - } - return res; -} - -int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) -{ - switch (adev->mode_info.num_crtc) { - case 1: - return 0x1; - case 2: - return 0x3; - case 3: - return 0x7; - case 4: - return 0xf; - case 5: - return 0x1f; - case 6: - default: - return 0x3f; - } -} - -int amdgpu_dm_encoder_init( - struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index) -{ - struct amdgpu_device *adev = dev->dev_private; - - int res = drm_encoder_init(dev, - &aencoder->base, - &amdgpu_dm_encoder_funcs, - DRM_MODE_ENCODER_TMDS, - NULL); - - aencoder->base.possible_crtcs = amdgpu_dm_get_encoder_crtc_mask(adev); - - if (!res) - aencoder->encoder_id = link_index; - else - aencoder->encoder_id = -1; - - drm_encoder_helper_add(&aencoder->base, &amdgpu_dm_encoder_helper_funcs); - - return res; -} - -static void manage_dm_interrupts( - struct amdgpu_device *adev, - struct amdgpu_crtc *acrtc, - bool enable) -{ - /* - * this is not correct translation but will work as soon as VBLANK - * constant is the same as PFLIP - */ - int irq_type = - amdgpu_crtc_idx_to_irq_type( - adev, - acrtc->crtc_id); - - if (enable) { - drm_crtc_vblank_on(&acrtc->base); - amdgpu_irq_get( - adev, - &adev->pageflip_irq, - irq_type); - } else { - - amdgpu_irq_put( - adev, - &adev->pageflip_irq, - irq_type); - drm_crtc_vblank_off(&acrtc->base); - } -} - -static bool is_scaling_state_different( - const struct dm_connector_state *dm_state, - const struct dm_connector_state *old_dm_state) -{ - if (dm_state->scaling != old_dm_state->scaling) - return true; - if (!dm_state->underscan_enable && old_dm_state->underscan_enable) { - if (old_dm_state->underscan_hborder != 0 && old_dm_state->underscan_vborder != 0) - return true; - } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { - if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) - return true; - } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder - || dm_state->underscan_vborder != old_dm_state->underscan_vborder) - return true; - return false; -} - -static void remove_stream( - struct amdgpu_device *adev, - struct amdgpu_crtc *acrtc, - struct dc_stream *stream) -{ - /* this is the update mode case */ - if (adev->dm.freesync_module) - mod_freesync_remove_stream(adev->dm.freesync_module, stream); - - acrtc->otg_inst = -1; - acrtc->enabled = false; -} - -static void handle_cursor_update( - struct drm_plane *plane, - struct drm_plane_state *old_plane_state) -{ - if (!plane->state->fb && !old_plane_state->fb) - return; - - /* Check if it's a cursor on/off update or just cursor move*/ - if (plane->state->fb == old_plane_state->fb) - dm_crtc_cursor_move( - plane->state->crtc, - plane->state->crtc_x, - plane->state->crtc_y); - else { - struct amdgpu_framebuffer *afb = - to_amdgpu_framebuffer(plane->state->fb); - dm_crtc_cursor_set( - (!!plane->state->fb) ? - plane->state->crtc : - old_plane_state->crtc, - (!!plane->state->fb) ? - afb->address : - 0, - plane->state->crtc_w, - plane->state->crtc_h); - } -} - - -static void prepare_flip_isr(struct amdgpu_crtc *acrtc) -{ - - assert_spin_locked(&acrtc->base.dev->event_lock); - WARN_ON(acrtc->event); - - acrtc->event = acrtc->base.state->event; - - /* Set the flip status */ - acrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; - - /* Mark this event as consumed */ - acrtc->base.state->event = NULL; - - DRM_DEBUG_DRIVER("crtc:%d, pflip_stat:AMDGPU_FLIP_SUBMITTED\n", - acrtc->crtc_id); -} - -/* - * Executes flip - * - * Waits on all BO's fences and for proper vblank count - */ -static void amdgpu_dm_do_flip( - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - uint32_t target) -{ - unsigned long flags; - uint32_t target_vblank; - int r, vpos, hpos; - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj); - struct amdgpu_device *adev = crtc->dev->dev_private; - bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; - struct dc_flip_addrs addr = { {0} }; - struct dc_surface_update surface_updates[1] = { {0} }; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - - /* Prepare wait for target vblank early - before the fence-waits */ - target_vblank = target - drm_crtc_vblank_count(crtc) + - amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); - - /*TODO This might fail and hence better not used, wait - * explicitly on fences instead - * and in general should be called for - * blocking commit to as per framework helpers - * */ - r = amdgpu_bo_reserve(abo, true); - if (unlikely(r != 0)) { - DRM_ERROR("failed to reserve buffer before flip\n"); - WARN_ON(1); - } - - /* Wait for all fences on this FB */ - WARN_ON(reservation_object_wait_timeout_rcu(abo->tbo.resv, true, false, - MAX_SCHEDULE_TIMEOUT) < 0); - - amdgpu_bo_unreserve(abo); - - /* Wait until we're out of the vertical blank period before the one - * targeted by the flip - */ - while ((acrtc->enabled && - (amdgpu_get_crtc_scanoutpos(adev->ddev, acrtc->crtc_id, 0, - &vpos, &hpos, NULL, NULL, - &crtc->hwmode) - & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK)) == - (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_IN_VBLANK) && - (int)(target_vblank - - amdgpu_get_vblank_counter_kms(adev->ddev, acrtc->crtc_id)) > 0)) { - usleep_range(1000, 1100); - } - - /* Flip */ - spin_lock_irqsave(&crtc->dev->event_lock, flags); - /* update crtc fb */ - crtc->primary->fb = fb; - - WARN_ON(acrtc->pflip_status != AMDGPU_FLIP_NONE); - WARN_ON(!acrtc_state->stream); - - addr.address.grph.addr.low_part = lower_32_bits(afb->address); - addr.address.grph.addr.high_part = upper_32_bits(afb->address); - addr.flip_immediate = async_flip; - - - if (acrtc->base.state->event) - prepare_flip_isr(acrtc); - - surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; - surface_updates->flip_addr = &addr; - - - dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); - - DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", - __func__, - addr.address.grph.addr.high_part, - addr.address.grph.addr.low_part); - - - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); -} - -static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, - struct drm_device *dev, - struct amdgpu_display_manager *dm, - struct drm_crtc *pcrtc, - bool *wait_for_vblank) -{ - uint32_t i; - struct drm_plane *plane; - struct drm_plane_state *old_plane_state; - struct dc_stream *dc_stream_attach; - struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; - struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); - int planes_count = 0; - unsigned long flags; - - /* update planes when needed */ - for_each_plane_in_state(state, plane, old_plane_state, i) { - struct drm_plane_state *plane_state = plane->state; - struct drm_crtc *crtc = plane_state->crtc; - struct drm_framebuffer *fb = plane_state->fb; - bool pflip_needed; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); - - if (plane->type == DRM_PLANE_TYPE_CURSOR) { - handle_cursor_update(plane, old_plane_state); - continue; - } - - if (!fb || !crtc || pcrtc != crtc || !crtc->state->active || - (!crtc->state->planes_changed && - !pcrtc->state->color_mgmt_changed)) - continue; - - pflip_needed = !state->allow_modeset; - - spin_lock_irqsave(&crtc->dev->event_lock, flags); - if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { - DRM_ERROR("add_surface: acrtc %d, already busy\n", - acrtc_attach->crtc_id); - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - /* In comit tail framework this cannot happen */ - WARN_ON(1); - } - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - - if (!pflip_needed) { - WARN_ON(!dm_plane_state->surface); - - dc_surfaces_constructed[planes_count] = dm_plane_state->surface; - - dc_stream_attach = acrtc_state->stream; - planes_count++; - - } else if (crtc->state->planes_changed) { - /* Assume even ONE crtc with immediate flip means - * entire can't wait for VBLANK - * TODO Check if it's correct - */ - *wait_for_vblank = - acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? - false : true; - - /* TODO: Needs rework for multiplane flip */ - if (plane->type == DRM_PLANE_TYPE_PRIMARY) - drm_crtc_vblank_get(crtc); - - amdgpu_dm_do_flip( - crtc, - fb, - drm_crtc_vblank_count(crtc) + *wait_for_vblank); - - /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */ - - /*clean up the flags for next usage*/ - acrtc_attach->flip_flags = 0; - } - - } - - if (planes_count) { - unsigned long flags; - - if (pcrtc->state->event) { - - drm_crtc_vblank_get(pcrtc); - - spin_lock_irqsave(&pcrtc->dev->event_lock, flags); - prepare_flip_isr(acrtc_attach); - spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); - } - - if (false == dc_commit_surfaces_to_stream(dm->dc, - dc_surfaces_constructed, - planes_count, - dc_stream_attach)) - dm_error("%s: Failed to attach surface!\n", __func__); - } else { - /*TODO BUG Here should go disable planes on CRTC. */ - } -} - - -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock) -{ - struct drm_crtc *crtc; - struct drm_crtc_state *new_state; - struct amdgpu_device *adev = dev->dev_private; - int i; - - /* - * We evade vblanks and pflips on crtc that - * should be changed. We do it here to flush & disable - * interrupts before drm_swap_state is called in drm_atomic_helper_commit - * it will update crtc->dm_crtc_state->stream pointer which is used in - * the ISRs. - */ - for_each_crtc_in_state(state, crtc, new_state, i) { - struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - - if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream) - manage_dm_interrupts(adev, acrtc, false); - } - - return drm_atomic_helper_commit(dev, state, nonblock); - - /*TODO Handle EINTR, reenable IRQ*/ -} - -void amdgpu_dm_atomic_commit_tail( - struct drm_atomic_state *state) -{ - struct drm_device *dev = state->dev; - struct amdgpu_device *adev = dev->dev_private; - struct amdgpu_display_manager *dm = &adev->dm; - struct dm_atomic_state *dm_state; - uint32_t i, j; - uint32_t new_crtcs_count = 0; - struct drm_crtc *crtc, *pcrtc; - struct drm_crtc_state *old_crtc_state; - struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream *new_stream = NULL; - unsigned long flags; - bool wait_for_vblank = true; - struct drm_connector *connector; - struct drm_connector_state *old_conn_state; - struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; - - drm_atomic_helper_update_legacy_modeset_state(dev, state); - - dm_state = to_dm_atomic_state(state); - - /* update changed items */ - for_each_crtc_in_state(state, crtc, old_crtc_state, i) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct drm_crtc_state *new_state = crtc->state; - new_acrtc_state = to_dm_crtc_state(new_state); - old_acrtc_state = to_dm_crtc_state(old_crtc_state); - - DRM_DEBUG_KMS( - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " - "planes_changed:%d, mode_changed:%d,active_changed:%d," - "connectors_changed:%d\n", - acrtc->crtc_id, - new_state->enable, - new_state->active, - new_state->planes_changed, - new_state->mode_changed, - new_state->active_changed, - new_state->connectors_changed); - - /* handles headless hotplug case, updating new_state and - * aconnector as needed - */ - - if (modeset_required(new_state)) { - - DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); - - if (!new_acrtc_state->stream) { - /* - * this could happen because of issues with - * userspace notifications delivery. - * In this case userspace tries to set mode on - * display which is disconnect in fact. - * dc_sink in NULL in this case on aconnector. - * We expect reset mode will come soon. - * - * This can also happen when unplug is done - * during resume sequence ended - * - * In this case, we want to pretend we still - * have a sink to keep the pipe running so that - * hw state is consistent with the sw state - */ - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", - __func__, acrtc->base.base.id); - continue; - } - - - if (old_acrtc_state->stream) - remove_stream(adev, acrtc, old_acrtc_state->stream); - - - /* - * this loop saves set mode crtcs - * we needed to enable vblanks once all - * resources acquired in dc after dc_commit_streams - */ - - /*TODO move all this into dm_crtc_state, get rid of - * new_crtcs array and use old and new atomic states - * instead - */ - new_crtcs[new_crtcs_count] = acrtc; - new_crtcs_count++; - - acrtc->enabled = true; - acrtc->hw_mode = crtc->state->mode; - crtc->hwmode = crtc->state->mode; - } else if (modereset_required(new_state)) { - DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); - - /* i.e. reset mode */ - if (old_acrtc_state->stream) - remove_stream(adev, acrtc, old_acrtc_state->stream); - } - } /* for_each_crtc_in_state() */ - - /* - * Add streams after required streams from new and replaced streams - * are removed from freesync module - */ - if (adev->dm.freesync_module) { - for (i = 0; i < new_crtcs_count; i++) { - struct amdgpu_connector *aconnector = NULL; - new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); - - new_stream = new_acrtc_state->stream; - aconnector = - amdgpu_dm_find_first_crct_matching_connector( - state, - &new_crtcs[i]->base, - false); - if (!aconnector) { - DRM_INFO( - "Atomic commit: Failed to find connector for acrtc id:%d " - "skipping freesync init\n", - new_crtcs[i]->crtc_id); - continue; - } - - mod_freesync_add_stream(adev->dm.freesync_module, - new_stream, &aconnector->caps); - } - } - - if (dm_state->context) - WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); - - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - new_acrtc_state = to_dm_crtc_state(crtc->state); - - if (new_acrtc_state->stream != NULL) { - const struct dc_stream_status *status = - dc_stream_get_status(new_acrtc_state->stream); - - if (!status) - DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc); - else - acrtc->otg_inst = status->primary_otg_inst; - } - } - - /* Handle scaling and undersacn changes*/ - for_each_connector_in_state(state, connector, old_conn_state, i) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - struct dm_connector_state *con_new_state = - to_dm_connector_state(aconnector->base.state); - struct dm_connector_state *con_old_state = - to_dm_connector_state(old_conn_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); - struct dc_stream_status *status = NULL; - - /* Skip any modesets/resets */ - if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) - continue; - - /* Skip any thing not scale or underscan changes */ - if (!is_scaling_state_different(con_new_state, con_old_state)) - continue; - - new_acrtc_state = to_dm_crtc_state(acrtc->base.state); - - update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream *)new_acrtc_state->stream); - - status = dc_stream_get_status(new_acrtc_state->stream); - WARN_ON(!status); - WARN_ON(!status->surface_count); - - if (!new_acrtc_state->stream) - continue; - - /*TODO How it works with MPO ?*/ - if (!dc_commit_surfaces_to_stream( - dm->dc, - status->surfaces, - status->surface_count, - new_acrtc_state->stream)) - dm_error("%s: Failed to update stream scaling!\n", __func__); - } - - for (i = 0; i < new_crtcs_count; i++) { - /* - * loop to enable interrupts on newly arrived crtc - */ - struct amdgpu_crtc *acrtc = new_crtcs[i]; - new_acrtc_state = to_dm_crtc_state(acrtc->base.state); - - if (adev->dm.freesync_module) - mod_freesync_notify_mode_change( - adev->dm.freesync_module, &new_acrtc_state->stream, 1); - - manage_dm_interrupts(adev, acrtc, true); - } - - /* update planes when needed per crtc*/ - for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { - new_acrtc_state = to_dm_crtc_state(pcrtc->state); - - if (new_acrtc_state->stream) - amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); - } - - - /* - * send vblank event on all events not handled in flip and - * mark consumed event for drm_atomic_helper_commit_hw_done - */ - spin_lock_irqsave(&adev->ddev->event_lock, flags); - for_each_crtc_in_state(state, crtc, old_crtc_state, i) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - - if (acrtc->base.state->event) - drm_send_event_locked(dev, &crtc->state->event->base); - - acrtc->base.state->event = NULL; - } - spin_unlock_irqrestore(&adev->ddev->event_lock, flags); - - /* Signal HW programming completion */ - drm_atomic_helper_commit_hw_done(state); - - if (wait_for_vblank) - drm_atomic_helper_wait_for_vblanks(dev, state); - - drm_atomic_helper_cleanup_planes(dev, state); -} - - -static int dm_force_atomic_commit(struct drm_connector *connector) -{ - int ret = 0; - struct drm_device *ddev = connector->dev; - struct drm_atomic_state *state = drm_atomic_state_alloc(ddev); - struct amdgpu_crtc *disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); - struct drm_plane *plane = disconnected_acrtc->base.primary; - struct drm_connector_state *conn_state; - struct drm_crtc_state *crtc_state; - struct drm_plane_state *plane_state; - - if (!state) - return -ENOMEM; - - state->acquire_ctx = ddev->mode_config.acquire_ctx; - - /* Construct an atomic state to restore previous display setting */ - - /* - * Attach connectors to drm_atomic_state - */ - conn_state = drm_atomic_get_connector_state(state, connector); - - ret = PTR_ERR_OR_ZERO(conn_state); - if (ret) - goto err; - - /* Attach crtc to drm_atomic_state*/ - crtc_state = drm_atomic_get_crtc_state(state, &disconnected_acrtc->base); - - ret = PTR_ERR_OR_ZERO(crtc_state); - if (ret) - goto err; - - /* force a restore */ - crtc_state->mode_changed = true; - - /* Attach plane to drm_atomic_state */ - plane_state = drm_atomic_get_plane_state(state, plane); - - ret = PTR_ERR_OR_ZERO(plane_state); - if (ret) - goto err; - - - /* Call commit internally with the state we just constructed */ - ret = drm_atomic_commit(state); - if (!ret) - return 0; - -err: - DRM_ERROR("Restoring old state failed with %i\n", ret); - drm_atomic_state_put(state); - - return ret; -} - -/* - * This functions handle all cases when set mode does not come upon hotplug. - * This include when the same display is unplugged then plugged back into the - * same port and when we are running without usermode desktop manager supprot - */ -void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector) -{ - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - struct amdgpu_crtc *disconnected_acrtc; - struct dm_crtc_state *acrtc_state; - - if (!aconnector->dc_sink || !connector->state || !connector->encoder) - return; - - disconnected_acrtc = to_amdgpu_crtc(connector->encoder->crtc); - acrtc_state = to_dm_crtc_state(disconnected_acrtc->base.state); - - if (!disconnected_acrtc || !acrtc_state->stream) - return; - - /* - * If the previous sink is not released and different from the current, - * we deduce we are in a state where we can not rely on usermode call - * to turn on the display, so we do it here - */ - if (acrtc_state->stream->sink != aconnector->dc_sink) - dm_force_atomic_commit(&aconnector->base); -} - -static uint32_t add_val_sets_surface( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream *stream, - struct dc_surface *surface) -{ - uint32_t i = 0, j = 0; - - while (i < set_count) { - if (val_sets[i].stream == stream) { - while (val_sets[i].surfaces[j]) - j++; - break; - } - ++i; - } - - val_sets[i].surfaces[j] = surface; - val_sets[i].surface_count++; - - return val_sets[i].surface_count; -} - -static uint32_t update_in_val_sets_stream( - struct dc_validation_set *val_sets, - uint32_t set_count, - struct dc_stream *old_stream, - struct dc_stream *new_stream, - struct drm_crtc *crtc) -{ - uint32_t i = 0; - - while (i < set_count) { - if (val_sets[i].stream == old_stream) - break; - ++i; - } - - val_sets[i].stream = new_stream; - - if (i == set_count) - /* nothing found. add new one to the end */ - return set_count + 1; - - return set_count; -} - -static uint32_t remove_from_val_sets( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream *stream) -{ - int i; - - for (i = 0; i < set_count; i++) - if (val_sets[i].stream == stream) - break; - - if (i == set_count) { - /* nothing found */ - return set_count; - } - - set_count--; - - for (; i < set_count; i++) { - val_sets[i] = val_sets[i + 1]; - } - - return set_count; -} - -/*` - * Grabs all modesetting locks to serialize against any blocking commits, - * Waits for completion of all non blocking commits. - */ -static int do_aquire_global_lock( - struct drm_device *dev, - struct drm_atomic_state *state) -{ - struct drm_crtc *crtc; - struct drm_crtc_commit *commit; - long ret; - - /* Adding all modeset locks to aquire_ctx will - * ensure that when the framework release it the - * extra locks we are locking here will get released to - */ - ret = drm_modeset_lock_all_ctx(dev, state->acquire_ctx); - if (ret) - return ret; - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - spin_lock(&crtc->commit_lock); - commit = list_first_entry_or_null(&crtc->commit_list, - struct drm_crtc_commit, commit_entry); - if (commit) - drm_crtc_commit_get(commit); - spin_unlock(&crtc->commit_lock); - - if (!commit) - continue; - - /* Make sure all pending HW programming completed and - * page flips done - */ - ret = wait_for_completion_interruptible_timeout(&commit->hw_done, 10*HZ); - - if (ret > 0) - ret = wait_for_completion_interruptible_timeout( - &commit->flip_done, 10*HZ); - - if (ret == 0) - DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " - "timed out\n", crtc->base.id, crtc->name); - - drm_crtc_commit_put(commit); - } - - return ret < 0 ? ret : 0; -} - -int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) -{ - struct dm_atomic_state *dm_state; - struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; - struct drm_plane *plane; - struct drm_plane_state *plane_state; - int i, j; - int ret; - struct amdgpu_device *adev = dev->dev_private; - struct dc *dc = adev->dm.dc; - struct drm_connector *connector; - struct drm_connector_state *conn_state; - int set_count; - struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; - struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; - - /* - * This bool will be set for true for any modeset/reset - * or surface update which implies non fast surface update. - */ - bool lock_and_validation_needed = false; - - ret = drm_atomic_helper_check_modeset(dev, state); - - if (ret) { - DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); - return ret; - } - - dm_state = to_dm_atomic_state(state); - - /* copy existing configuration */ - set_count = 0; - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - - old_acrtc_state = to_dm_crtc_state(crtc->state); - - if (old_acrtc_state->stream) { - dc_stream_retain(old_acrtc_state->stream); - set[set_count].stream = old_acrtc_state->stream; - ++set_count; - } - } - - /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ - /* update changed items */ - for_each_crtc_in_state(state, crtc, crtc_state, i) { - struct amdgpu_crtc *acrtc = NULL; - struct amdgpu_connector *aconnector = NULL; - old_acrtc_state = to_dm_crtc_state(crtc->state); - new_acrtc_state = to_dm_crtc_state(crtc_state); - acrtc = to_amdgpu_crtc(crtc); - - aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); - - DRM_DEBUG_KMS( - "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " - "planes_changed:%d, mode_changed:%d,active_changed:%d," - "connectors_changed:%d\n", - acrtc->crtc_id, - crtc_state->enable, - crtc_state->active, - crtc_state->planes_changed, - crtc_state->mode_changed, - crtc_state->active_changed, - crtc_state->connectors_changed); - - if (modeset_required(crtc_state)) { - - struct dc_stream *new_stream = NULL; - struct drm_connector_state *conn_state = NULL; - struct dm_connector_state *dm_conn_state = NULL; - - if (aconnector) { - conn_state = drm_atomic_get_connector_state(state, &aconnector->base); - if (IS_ERR(conn_state)) { - ret = PTR_ERR_OR_ZERO(conn_state); - goto fail; - } - - dm_conn_state = to_dm_connector_state(conn_state); - } - - new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state); - - /* - * we can have no stream on ACTION_SET if a display - * was disconnected during S3, in this case it not and - * error, the OS will be updated after detection, and - * do the right thing on next atomic commit - */ - if (!new_stream) { - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", - __func__, acrtc->base.base.id); - break; - } - - if (new_acrtc_state->stream) - dc_stream_release(new_acrtc_state->stream); - - new_acrtc_state->stream = new_stream; - - set_count = update_in_val_sets_stream( - set, - set_count, - old_acrtc_state->stream, - new_acrtc_state->stream, - crtc); - - lock_and_validation_needed = true; - - } else if (modereset_required(crtc_state)) { - - /* i.e. reset mode */ - if (new_acrtc_state->stream) { - set_count = remove_from_val_sets( - set, - set_count, - new_acrtc_state->stream); - - dc_stream_release(new_acrtc_state->stream); - new_acrtc_state->stream = NULL; - - lock_and_validation_needed = true; - } - } - - - /* - * Hack: Commit needs planes right now, specifically for gamma - * TODO rework commit to check CRTC for gamma change - */ - if (crtc_state->color_mgmt_changed) { - - ret = drm_atomic_add_affected_planes(state, crtc); - if (ret) - goto fail; - } - } - - /* Check scaling and undersacn changes*/ - /*TODO Removed scaling changes validation due to inability to commit - * new stream into context w\o causing full reset. Need to - * decide how to handle. - */ - for_each_connector_in_state(state, connector, conn_state, i) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - struct dm_connector_state *con_old_state = - to_dm_connector_state(aconnector->base.state); - struct dm_connector_state *con_new_state = - to_dm_connector_state(conn_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); - - /* Skip any modesets/resets */ - if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) - continue; - - /* Skip any thing not scale or underscan chnages */ - if (!is_scaling_state_different(con_new_state, con_old_state)) - continue; - - lock_and_validation_needed = true; - } - - for_each_crtc_in_state(state, crtc, crtc_state, i) { - new_acrtc_state = to_dm_crtc_state(crtc_state); - - for_each_plane_in_state(state, plane, plane_state, j) { - struct drm_crtc *plane_crtc = plane_state->crtc; - struct drm_framebuffer *fb = plane_state->fb; - bool pflip_needed; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); - - /*TODO Implement atomic check for cursor plane */ - if (plane->type == DRM_PLANE_TYPE_CURSOR) - continue; - - if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active) - continue; - - WARN_ON(!new_acrtc_state->stream); - - pflip_needed = !state->allow_modeset; - if (!pflip_needed) { - struct dc_surface *surface; - - surface = dc_create_surface(dc); - - ret = fill_plane_attributes( - plane_crtc->dev->dev_private, - surface, - plane_state, - crtc_state, - false); - if (ret) - goto fail; - - - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); - - dm_plane_state->surface = surface; - - add_val_sets_surface(set, - set_count, - new_acrtc_state->stream, - surface); - - lock_and_validation_needed = true; - } - } - } - - /* Run this here since we want to validate the streams we created */ - ret = drm_atomic_helper_check_planes(dev, state); - if (ret) - goto fail; - - /* - * For full updates case when - * removing/adding/updating streams on once CRTC while flipping - * on another CRTC, - * acquiring global lock will guarantee that any such full - * update commit - * will wait for completion of any outstanding flip using DRMs - * synchronization events. - */ - - if (lock_and_validation_needed) { - - ret = do_aquire_global_lock(dev, state); - if (ret) - goto fail; - WARN_ON(dm_state->context); - dm_state->context = dc_get_validate_context(dc, set, set_count); - if (!dm_state->context) { - ret = -EINVAL; - goto fail; - } - } - - /* Must be success */ - WARN_ON(ret); - return ret; - -fail: - if (ret == -EDEADLK) - DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n"); - else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) - DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n"); - else - DRM_ERROR("Atomic check failed with err: %d .\n", ret); - - return ret; -} - -static bool is_dp_capable_without_timing_msa( - struct dc *dc, - struct amdgpu_connector *amdgpu_connector) -{ - uint8_t dpcd_data; - bool capable = false; - - if (amdgpu_connector->dc_link && - dm_helpers_dp_read_dpcd( - NULL, - amdgpu_connector->dc_link, - DP_DOWN_STREAM_PORT_COUNT, - &dpcd_data, - sizeof(dpcd_data))) { - capable = (dpcd_data & DP_MSA_TIMING_PAR_IGNORED) ? true:false; - } - - return capable; -} -void amdgpu_dm_add_sink_to_freesync_module( - struct drm_connector *connector, - struct edid *edid) -{ - int i; - uint64_t val_capable; - bool edid_check_required; - struct detailed_timing *timing; - struct detailed_non_pixel *data; - struct detailed_data_monitor_range *range; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); - - struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; - edid_check_required = false; - if (!amdgpu_connector->dc_sink) { - DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); - return; - } - if (!adev->dm.freesync_module) - return; - /* - * if edid non zero restrict freesync only for dp and edp - */ - if (edid) { - if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT - || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { - edid_check_required = is_dp_capable_without_timing_msa( - adev->dm.dc, - amdgpu_connector); - } - } - val_capable = 0; - if (edid_check_required == true && (edid->version > 1 || - (edid->version == 1 && edid->revision > 1))) { - for (i = 0; i < 4; i++) { - - timing = &edid->detailed_timings[i]; - data = &timing->data.other_data; - range = &data->data.range; - /* - * Check if monitor has continuous frequency mode - */ - if (data->type != EDID_DETAIL_MONITOR_RANGE) - continue; - /* - * Check for flag range limits only. If flag == 1 then - * no additional timing information provided. - * Default GTF, GTF Secondary curve and CVT are not - * supported - */ - if (range->flags != 1) - continue; - - amdgpu_connector->min_vfreq = range->min_vfreq; - amdgpu_connector->max_vfreq = range->max_vfreq; - amdgpu_connector->pixel_clock_mhz = - range->pixel_clock_mhz * 10; - break; - } - - if (amdgpu_connector->max_vfreq - - amdgpu_connector->min_vfreq > 10) { - amdgpu_connector->caps.supported = true; - amdgpu_connector->caps.min_refresh_in_micro_hz = - amdgpu_connector->min_vfreq * 1000000; - amdgpu_connector->caps.max_refresh_in_micro_hz = - amdgpu_connector->max_vfreq * 1000000; - val_capable = 1; - } - } - - /* - * TODO figure out how to notify user-mode or DRM of freesync caps - * once we figure out how to deal with freesync in an upstreamable - * fashion - */ - -} - -void amdgpu_dm_remove_sink_from_freesync_module( - struct drm_connector *connector) -{ - /* - * TODO fill in once we figure out how to deal with freesync in - * an upstreamable fashion - */ -} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h deleted file mode 100644 index 94de6a3736fc..000000000000 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright 2012-13 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __AMDGPU_DM_TYPES_H__ -#define __AMDGPU_DM_TYPES_H__ - -#include -#include -#include "dc.h" - -struct amdgpu_framebuffer; -struct amdgpu_display_manager; -struct dc_validation_set; -struct dc_surface; -/* TODO rename to dc_stream_state */ -struct dc_stream; - - -struct dm_plane_state { - struct drm_plane_state base; - struct dc_surface *surface; -}; - -struct dm_crtc_state { - struct drm_crtc_state base; - struct dc_stream *stream; -}; - -#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) - -struct dm_atomic_state { - struct drm_atomic_state base; - - struct validate_context *context; -}; - -#define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) - - -/*TODO Jodan Hersen use the one in amdgpu_dm*/ -int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs); -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct drm_plane *plane, - uint32_t link_index); -int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, - struct amdgpu_connector *amdgpu_connector, - uint32_t link_index, - struct amdgpu_encoder *amdgpu_encoder); -int amdgpu_dm_encoder_init( - struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index); - -void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc); -void amdgpu_dm_connector_destroy(struct drm_connector *connector); -void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); - -int amdgpu_dm_connector_get_modes(struct drm_connector *connector); - -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); - -void amdgpu_dm_atomic_commit_tail( - struct drm_atomic_state *state); - -int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); - -void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); -struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( - struct drm_connector *connector); - -int amdgpu_dm_connector_atomic_set_property( - struct drm_connector *connector, - struct drm_connector_state *state, - struct drm_property *property, - uint64_t val); - -int amdgpu_dm_connector_atomic_get_property( - struct drm_connector *connector, - const struct drm_connector_state *state, - struct drm_property *property, - uint64_t *val); - -int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); - -void amdgpu_dm_connector_init_helper( - struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, - int connector_type, - struct dc_link *link, - int link_index); - -int amdgpu_dm_connector_mode_valid( - struct drm_connector *connector, - struct drm_display_mode *mode); - -void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); - -void amdgpu_dm_add_sink_to_freesync_module( - struct drm_connector *connector, - struct edid *edid); - -void amdgpu_dm_remove_sink_from_freesync_module( - struct drm_connector *connector); - -extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; - -#endif /* __AMDGPU_DM_TYPES_H__ */ -- cgit v1.2.3 From b830ebc910f641286ea0b816614db43d1135fc1a Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 26 Jul 2017 21:03:22 -0400 Subject: drm/amd/display: Fix ckeckpatch problems in amdgpu_dm Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 179 ++++++++++++---------- 1 file changed, 94 insertions(+), 85 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 646a946a2571..02ca9d6225eb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1682,14 +1682,13 @@ static int dm_crtc_cursor_set( int ret; struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - ret = EINVAL; + ret = EINVAL; - DRM_DEBUG_KMS( - "%s: crtc_id=%d with size %d to %d \n", - __func__, - amdgpu_crtc->crtc_id, - width, - height); + DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d \n", + __func__, + amdgpu_crtc->crtc_id, + width, + height); if (!address) { /* turn off cursor */ @@ -1839,6 +1838,7 @@ static int get_fb_info( { struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); int r = amdgpu_bo_reserve(rbo, false); + if (unlikely(r)) { DRM_ERROR("Unable to reserve buffer\n"); return r; @@ -1946,10 +1946,9 @@ static int fill_plane_attributes_from_fb( memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); - /* Fill GFX params */ - if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) - { - unsigned bankw, bankh, mtaspect, tile_split, num_banks; + /* Fill GFX8 params */ + if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { + unsigned int bankw, bankh, mtaspect, tile_split, num_banks; bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); @@ -2162,7 +2161,8 @@ static enum dc_color_depth convert_color_depth_from_display_info( uint32_t bpc = connector->display_info.bpc; /* Limited color depth to 8bit - * TODO: Still need to handle deep color*/ + * TODO: Still need to handle deep color + */ if (bpc > 8) bpc = 8; @@ -2195,6 +2195,7 @@ static enum dc_aspect_ratio get_aspect_ratio( { int32_t width = mode_in->crtc_hdisplay * 9; int32_t height = mode_in->crtc_vdisplay * 16; + if ((width - height) < 10 && (width - height) > -10) return ASPECT_RATIO_16_9; else @@ -2252,6 +2253,7 @@ static void fill_stream_properties_from_drm_display_mode( const struct drm_connector *connector) { struct dc_crtc_timing *timing_out = &stream->timing; + memset(timing_out, 0, sizeof(struct dc_crtc_timing)); timing_out->h_border_left = 0; @@ -2296,6 +2298,7 @@ static void fill_stream_properties_from_drm_display_mode( { struct dc_transfer_func *tf = dc_create_transfer_func(); + tf->type = TF_TYPE_PREDEFINED; tf->tf = TRANSFER_FUNCTION_SRGB; stream->out_transfer_func = tf; @@ -2322,7 +2325,7 @@ static void fill_audio_info( i++; } - if(cea_revision >= 3) { + if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; for (i = 0; i < audio_info->mode_count; ++i) { @@ -2341,7 +2344,7 @@ static void fill_audio_info( audio_info->flags.all = edid_caps->speaker_flags; /* TODO: We only check for the progressive mode, check for interlace mode too */ - if(drm_connector->latency_present[0]) { + if (drm_connector->latency_present[0]) { audio_info->video_latency = drm_connector->video_latency[0]; audio_info->audio_latency = drm_connector->audio_latency[0]; } @@ -2359,7 +2362,7 @@ static void copy_crtc_timing_for_drm_display_mode( dst_mode->crtc_clock = src_mode->crtc_clock; dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start; dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end; - dst_mode->crtc_hsync_start= src_mode->crtc_hsync_start; + dst_mode->crtc_hsync_start = src_mode->crtc_hsync_start; dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end; dst_mode->crtc_htotal = src_mode->crtc_htotal; dst_mode->crtc_hskew = src_mode->crtc_hskew; @@ -2397,12 +2400,12 @@ static struct dc_stream *create_stream_for_sink( struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; - if (NULL == aconnector) { + if (aconnector == NULL) { DRM_ERROR("aconnector is NULL!\n"); goto drm_connector_null; } - if (NULL == dm_state) { + if (dm_state == NULL) { DRM_ERROR("dm_state is NULL!\n"); goto dm_state_null; } @@ -2410,7 +2413,7 @@ static struct dc_stream *create_stream_for_sink( drm_connector = &aconnector->base; stream = dc_create_stream_for_sink(aconnector->dc_sink); - if (NULL == stream) { + if (stream == NULL) { DRM_ERROR("Failed to create stream for sink!\n"); goto stream_create_fail; } @@ -2428,7 +2431,7 @@ static struct dc_stream *create_stream_for_sink( struct drm_display_mode, head); - if (NULL == preferred_mode) { + if (preferred_mode == NULL) { /* This may not be an error, the use case is when we we have no * usermode calls to reset and set mode upon hotplug. In this * case, we call set mode ourselves to restore the previous mode @@ -2818,13 +2821,13 @@ int amdgpu_dm_connector_mode_valid( dc_sink = to_amdgpu_connector(connector)->dc_sink; - if (NULL == dc_sink) { + if (dc_sink == NULL) { DRM_ERROR("dc_sink is NULL!\n"); goto fail; } stream = dc_create_stream_for_sink(dc_sink); - if (NULL == stream) { + if (stream == NULL) { DRM_ERROR("Failed to create stream for sink!\n"); goto fail; } @@ -2849,11 +2852,11 @@ fail: static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { /* - * If hotplug a second bigger display in FB Con mode, bigger resolution - * modes will be filtered by drm_mode_validate_size(), and those modes - * is missing after user start lightdm. So we need to renew modes list. - * in get_modes call back, not just return the modes count - */ + * If hotplug a second bigger display in FB Con mode, bigger resolution + * modes will be filtered by drm_mode_validate_size(), and those modes + * is missing after user start lightdm. So we need to renew modes list. + * in get_modes call back, not just return the modes count + */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .best_encoder = best_encoder @@ -3064,11 +3067,11 @@ static void dm_plane_helper_cleanup_fb( if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin\n"); return; - } else { - amdgpu_bo_unpin(rbo); - amdgpu_bo_unreserve(rbo); - amdgpu_bo_unref(&rbo); - }; + } + + amdgpu_bo_unpin(rbo); + amdgpu_bo_unreserve(rbo); + amdgpu_bo_unref(&rbo); } int dm_create_validation_set_for_connector(struct drm_connector *connector, @@ -3084,14 +3087,14 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, (mode->flags & DRM_MODE_FLAG_DBLSCAN)) return result; - if (NULL == dc_sink) { + if (dc_sink == NULL) { DRM_ERROR("dc_sink is NULL!\n"); return result; } stream = dc_create_stream_for_sink(dc_sink); - if (NULL == stream) { + if (stream == NULL) { DRM_ERROR("Failed to create stream for sink!\n"); return result; } @@ -3230,10 +3233,8 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, return 0; fail: - if (acrtc) - kfree(acrtc); - if (cursor_plane) - kfree(cursor_plane); + kfree(acrtc); + kfree(cursor_plane); acrtc->crtc_id = -1; return res; } @@ -3280,12 +3281,13 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector) if (!list_empty(&connector->probed_modes)) { struct drm_display_mode *preferred_mode = NULL; + list_for_each_entry(preferred_mode, - &connector->probed_modes, - head) { - if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) { - amdgpu_encoder->native_mode = *preferred_mode; - } + &connector->probed_modes, + head) { + if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) + amdgpu_encoder->native_mode = *preferred_mode; + break; } @@ -3303,7 +3305,7 @@ static struct drm_display_mode *amdgpu_dm_create_common_mode( mode = drm_mode_duplicate(dev, native_mode); - if(mode == NULL) + if (mode == NULL) return NULL; mode->hdisplay = hdisplay; @@ -3329,7 +3331,7 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, char name[DRM_DISPLAY_MODE_LEN]; int w; int h; - }common_modes[] = { + } common_modes[] = { { "640x480", 640, 480}, { "800x600", 800, 600}, { "1024x768", 1024, 768}, @@ -3343,21 +3345,21 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, {"1920x1200", 1920, 1200} }; - n = sizeof(common_modes) / sizeof(common_modes[0]); + n = ARRAY_SIZE(common_modes); for (i = 0; i < n; i++) { struct drm_display_mode *curmode = NULL; bool mode_existed = false; if (common_modes[i].w > native_mode->hdisplay || - common_modes[i].h > native_mode->vdisplay || - (common_modes[i].w == native_mode->hdisplay && - common_modes[i].h == native_mode->vdisplay)) - continue; + common_modes[i].h > native_mode->vdisplay || + (common_modes[i].w == native_mode->hdisplay && + common_modes[i].h == native_mode->vdisplay)) + continue; list_for_each_entry(curmode, &connector->probed_modes, head) { if (common_modes[i].w == curmode->hdisplay && - common_modes[i].h == curmode->vdisplay) { + common_modes[i].h == curmode->vdisplay) { mode_existed = true; break; } @@ -3429,8 +3431,9 @@ void amdgpu_dm_connector_init_helper( mutex_init(&aconnector->hpd_lock); - /*configure suport HPD hot plug connector_>polled default value is 0 - * which means HPD hot plug not supported*/ + /* configure support HPD hot plug connector_>polled default value is 0 + * which means HPD hot plug not supported + */ switch (connector_type) { case DRM_MODE_CONNECTOR_HDMIA: aconnector->base.polled = DRM_CONNECTOR_POLL_HPD; @@ -3470,7 +3473,7 @@ int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, int i; int result = -EIO; - cmd.payloads = kzalloc(num * sizeof(struct i2c_payload), GFP_KERNEL); + cmd.payloads = kcalloc(num, sizeof(struct i2c_payload), GFP_KERNEL); if (!cmd.payloads) return result; @@ -3514,12 +3517,12 @@ static struct amdgpu_i2c_adapter *create_i2c( struct amdgpu_device *adev = ddc_service->ctx->driver_context; struct amdgpu_i2c_adapter *i2c; - i2c = kzalloc(sizeof (struct amdgpu_i2c_adapter), GFP_KERNEL); + i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); i2c->base.owner = THIS_MODULE; i2c->base.class = I2C_CLASS_DDC; i2c->base.dev.parent = &adev->pdev->dev; i2c->base.algo = &amdgpu_dm_i2c_algo; - snprintf(i2c->base.name, sizeof (i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); + snprintf(i2c->base.name, sizeof(i2c->base.name), "AMDGPU DM i2c hw bus %d", link_index); i2c_set_adapdata(&i2c->base, i2c); i2c->ddc_service = ddc_service; @@ -3527,7 +3530,8 @@ static struct amdgpu_i2c_adapter *create_i2c( } /* Note: this function assumes that dc_link_detect() was called for the - * dc_link which will be represented by this aconnector. */ + * dc_link which will be represented by this aconnector. + */ int amdgpu_dm_connector_init( struct amdgpu_display_manager *dm, struct amdgpu_connector *aconnector, @@ -3599,7 +3603,8 @@ int amdgpu_dm_connector_init( if (link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) { /* Event if registration failed, we should continue with * DM initialization because not having a backlight control - * is better then a black screen. */ + * is better then a black screen. + */ amdgpu_dm_register_backlight_device(dm); if (dm->backlight_dev) @@ -3701,9 +3706,9 @@ static bool is_scaling_state_different( } else if (dm_state->underscan_enable && !old_dm_state->underscan_enable) { if (dm_state->underscan_hborder != 0 && dm_state->underscan_vborder != 0) return true; - } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder - || dm_state->underscan_vborder != old_dm_state->underscan_vborder) - return true; + } else if (dm_state->underscan_hborder != old_dm_state->underscan_hborder || + dm_state->underscan_vborder != old_dm_state->underscan_vborder) + return true; return false; } @@ -3794,11 +3799,11 @@ static void amdgpu_dm_do_flip( target_vblank = target - drm_crtc_vblank_count(crtc) + amdgpu_get_vblank_counter_kms(crtc->dev, acrtc->crtc_id); - /*TODO This might fail and hence better not used, wait + /* TODO This might fail and hence better not used, wait * explicitly on fences instead * and in general should be called for * blocking commit to as per framework helpers - * */ + */ r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) { DRM_ERROR("failed to reserve buffer before flip\n"); @@ -3897,7 +3902,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, DRM_ERROR("add_surface: acrtc %d, already busy\n", acrtc_attach->crtc_id); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - /* In comit tail framework this cannot happen */ + /* In commit tail framework this cannot happen */ WARN_ON(1); } spin_unlock_irqrestore(&crtc->dev->event_lock, flags); @@ -4016,6 +4021,7 @@ void amdgpu_dm_atomic_commit_tail( for_each_crtc_in_state(state, crtc, old_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_crtc_state *new_state = crtc->state; + new_acrtc_state = to_dm_crtc_state(new_state); old_acrtc_state = to_dm_crtc_state(old_crtc_state); @@ -4041,20 +4047,20 @@ void amdgpu_dm_atomic_commit_tail( if (!new_acrtc_state->stream) { /* - * this could happen because of issues with - * userspace notifications delivery. - * In this case userspace tries to set mode on - * display which is disconnect in fact. - * dc_sink in NULL in this case on aconnector. - * We expect reset mode will come soon. - * - * This can also happen when unplug is done - * during resume sequence ended - * - * In this case, we want to pretend we still - * have a sink to keep the pipe running so that - * hw state is consistent with the sw state - */ + * this could happen because of issues with + * userspace notifications delivery. + * In this case userspace tries to set mode on + * display which is disconnect in fact. + * dc_sink in NULL in this case on aconnector. + * We expect reset mode will come soon. + * + * This can also happen when unplug is done + * during resume sequence ended + * + * In this case, we want to pretend we still + * have a sink to keep the pipe running so that + * hw state is consistent with the sw state + */ DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); continue; @@ -4097,6 +4103,7 @@ void amdgpu_dm_atomic_commit_tail( if (adev->dm.freesync_module) { for (i = 0; i < new_crtcs_count; i++) { struct amdgpu_connector *aconnector = NULL; + new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); new_stream = new_acrtc_state->stream; @@ -4106,10 +4113,9 @@ void amdgpu_dm_atomic_commit_tail( &new_crtcs[i]->base, false); if (!aconnector) { - DRM_INFO( - "Atomic commit: Failed to find connector for acrtc id:%d " - "skipping freesync init\n", - new_crtcs[i]->crtc_id); + DRM_INFO("Atomic commit: Failed to find connector for acrtc id:%d " + "skipping freesync init\n", + new_crtcs[i]->crtc_id); continue; } @@ -4124,6 +4130,7 @@ void amdgpu_dm_atomic_commit_tail( list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + new_acrtc_state = to_dm_crtc_state(crtc->state); if (new_acrtc_state->stream != NULL) { @@ -4181,6 +4188,7 @@ void amdgpu_dm_atomic_commit_tail( * loop to enable interrupts on newly arrived crtc */ struct amdgpu_crtc *acrtc = new_crtcs[i]; + new_acrtc_state = to_dm_crtc_state(acrtc->base.state); if (adev->dm.freesync_module) @@ -4375,9 +4383,8 @@ static uint32_t remove_from_val_sets( set_count--; - for (; i < set_count; i++) { + for (; i < set_count; i++) val_sets[i] = val_sets[i + 1]; - } return set_count; } @@ -4424,7 +4431,7 @@ static int do_aquire_global_lock( if (ret == 0) DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done " - "timed out\n", crtc->base.id, crtc->name); + "timed out\n", crtc->base.id, crtc->name); drm_crtc_commit_put(commit); } @@ -4483,6 +4490,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; + old_acrtc_state = to_dm_crtc_state(crtc->state); new_acrtc_state = to_dm_crtc_state(crtc_state); acrtc = to_amdgpu_crtc(crtc); @@ -4591,7 +4599,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) continue; - /* Skip any thing not scale or underscan chnages */ + /* Skip any thing not scale or underscan changes */ if (!is_scaling_state_different(con_new_state, con_old_state)) continue; @@ -4724,6 +4732,7 @@ void amdgpu_dm_add_sink_to_freesync_module( struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; + edid_check_required = false; if (!amdgpu_connector->dc_sink) { DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); -- cgit v1.2.3 From a32e24b486e80417e62d34f60d625783affff431 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 27 Jul 2017 19:53:55 -0400 Subject: drm/amd/display: Initial prototype of FBC implementation - Protected by ENABLE_FBC compile flag - DC part will follow Signed-off-by: Roman Li Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 +++++++++++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 12 ++++++++++ 2 files changed, 41 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 02ca9d6225eb..dfb04c5776ad 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -297,6 +297,30 @@ static void hotplug_notify_work_func(struct work_struct *work) drm_kms_helper_hotplug_event(dev); } +#ifdef ENABLE_FBC +#include "dal_asic_id.h" +/* Allocate memory for FBC compressed data */ +/* TODO: Dynamic allocation */ +#define AMDGPU_FBC_SIZE (3840 * 2160 * 4) + +void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev) +{ + int r; + struct dm_comressor_info *compressor = &adev->dm.compressor; + + if (!compressor->bo_ptr) { + r = amdgpu_bo_create_kernel(adev, AMDGPU_FBC_SIZE, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM, &compressor->bo_ptr, + &compressor->gpu_addr, &compressor->cpu_addr); + + if (r) + DRM_ERROR("DM: Failed to initialize fbc\n"); + } + +} +#endif + + /* Init display KMS * * Returns 0 on success @@ -347,6 +371,11 @@ int amdgpu_dm_init(struct amdgpu_device *adev) init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; +#ifdef ENABLE_FBC + if (adev->family == FAMILY_CZ) + amdgpu_dm_initialize_fbc(adev); + init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr; +#endif /* Display Core create. */ adev->dm.dc = dc_create(&init_data); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 16b2e0849a65..ce0223af7d5f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -72,6 +72,15 @@ struct irq_list_head { struct work_struct work; }; +#ifdef ENABLE_FBC +struct dm_comressor_info { + void *cpu_addr; + struct amdgpu_bo *bo_ptr; + uint64_t gpu_addr; +}; +#endif + + struct amdgpu_display_manager { struct dal *dal; struct dc *dc; @@ -133,6 +142,9 @@ struct amdgpu_display_manager { * Caches device atomic state for suspend/resume */ struct drm_atomic_state *cached_state; +#ifdef ENABLE_FBC + struct dm_comressor_info compressor; +#endif }; /* basic init/fini API */ -- cgit v1.2.3 From cbd194881e05844cc54573480aac8df3fd97222d Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 26 Jul 2017 15:52:28 -0400 Subject: drm/amd/display: Implement plane atomic_check. Use per surface validation hook. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dfb04c5776ad..baa788ba6f55 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3141,9 +3141,26 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, return MODE_OK; } +int dm_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) +{ + struct amdgpu_device *adev = plane->dev->dev_private; + struct dc *dc = adev->dm.dc; + struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); + + if (!dm_plane_state->surface) + return true; + + if (dc_validate_surface(dc, dm_plane_state->surface)) + return 0; + + return -EINVAL; +} + static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = dm_plane_helper_prepare_fb, .cleanup_fb = dm_plane_helper_cleanup_fb, + .atomic_check = dm_plane_atomic_check, }; /* -- cgit v1.2.3 From 9b690ef3c70422cdcd0cf912db33f2c92ef4a53f Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 28 Jul 2017 13:11:00 -0400 Subject: drm/amd/display: Avoid full modeset when not required Fix IGT test case (kms_atomic_transition) -DRM sets the mode_changed flag, while we don't need to do a full modeset. -We want to override the mode_changed flag in this case If we don't do this, we will still bypass the modeset in DC. This will fail to update the new stream_status, causing nullptr at a later stage when trying to access stream_status" We now avoid this by discarding the new_stream instead of partially filling it. Signed-off-by: Bhawanpreet Lakha Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 97 +++++++++++++++-------- 1 file changed, 62 insertions(+), 35 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index baa788ba6f55..7b597a0a2ab9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1608,8 +1608,16 @@ struct dm_connector_state { #define to_dm_connector_state(x)\ container_of((x), struct dm_connector_state, base) -static bool modeset_required(struct drm_crtc_state *crtc_state) +static bool modeset_required(struct drm_crtc_state *crtc_state, + struct dc_stream *new_stream, + struct dc_stream *old_stream) { + if (dc_is_stream_unchanged(new_stream, old_stream)) { + crtc_state->mode_changed = false; + DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d", + crtc_state->mode_changed); + } + if (!drm_atomic_crtc_needs_modeset(crtc_state)) return false; @@ -2904,7 +2912,8 @@ static int dm_crtc_helper_atomic_check( struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state); int ret = -EINVAL; - if (unlikely(!dm_crtc_state->stream && modeset_required(state))) { + if (unlikely(!dm_crtc_state->stream && + modeset_required(state, NULL, dm_crtc_state->stream))) { WARN_ON(1); return ret; } @@ -4087,7 +4096,7 @@ void amdgpu_dm_atomic_commit_tail( * aconnector as needed */ - if (modeset_required(new_state)) { + if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) { DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); @@ -4536,6 +4545,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; + struct dc_stream *new_stream = NULL; + struct drm_connector_state *conn_state = NULL; + struct dm_connector_state *dm_conn_state = NULL; old_acrtc_state = to_dm_crtc_state(crtc->state); new_acrtc_state = to_dm_crtc_state(crtc_state); @@ -4555,23 +4567,50 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, crtc_state->active_changed, crtc_state->connectors_changed); - if (modeset_required(crtc_state)) { + if (modereset_required(crtc_state)) { - struct dc_stream *new_stream = NULL; - struct drm_connector_state *conn_state = NULL; - struct dm_connector_state *dm_conn_state = NULL; + /* i.e. reset mode */ + if (new_acrtc_state->stream) { + set_count = remove_from_val_sets( + set, + set_count, + new_acrtc_state->stream); + + dc_stream_release(new_acrtc_state->stream); + new_acrtc_state->stream = NULL; + + lock_and_validation_needed = true; + } + + } else { if (aconnector) { - conn_state = drm_atomic_get_connector_state(state, &aconnector->base); + conn_state = drm_atomic_get_connector_state(state, + &aconnector->base); + if (IS_ERR(conn_state)) { ret = PTR_ERR_OR_ZERO(conn_state); goto fail; } dm_conn_state = to_dm_connector_state(conn_state); + + new_stream = create_stream_for_sink(aconnector, + &crtc_state->mode, + dm_conn_state); + + if (!new_stream) { + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + __func__, acrtc->base.base.id); + break; + } + + } - new_stream = create_stream_for_sink(aconnector, &crtc_state->mode, dm_conn_state); + if (modeset_required(crtc_state, new_stream, + old_acrtc_state->stream)) { + /* * we can have no stream on ACTION_SET if a display @@ -4579,39 +4618,27 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * error, the OS will be updated after detection, and * do the right thing on next atomic commit */ - if (!new_stream) { - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", - __func__, acrtc->base.base.id); - break; - } - - if (new_acrtc_state->stream) - dc_stream_release(new_acrtc_state->stream); - - new_acrtc_state->stream = new_stream; - - set_count = update_in_val_sets_stream( - set, - set_count, - old_acrtc_state->stream, - new_acrtc_state->stream, - crtc); - lock_and_validation_needed = true; + if (new_acrtc_state->stream) + dc_stream_release(new_acrtc_state->stream); - } else if (modereset_required(crtc_state)) { + new_acrtc_state->stream = new_stream; - /* i.e. reset mode */ - if (new_acrtc_state->stream) { - set_count = remove_from_val_sets( + set_count = update_in_val_sets_stream( set, set_count, - new_acrtc_state->stream); - - dc_stream_release(new_acrtc_state->stream); - new_acrtc_state->stream = NULL; + old_acrtc_state->stream, + new_acrtc_state->stream, + crtc); lock_and_validation_needed = true; + } else { + /* + * The new stream is unused, so we release it + */ + if (new_stream) + dc_stream_release(new_stream); + } } -- cgit v1.2.3 From c9614aeb12f80fa7a787e608d75b707175997edd Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:24:04 -0400 Subject: drm/amd/display: Rename dc_surface to dc_plane_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_surface/struct dc_plane_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_update/struct dc_surface_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_status/struct dc_surface_status/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_plane_state_dcc_cap/struct dc_surface_dcc_cap/g' Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 18 +++++++++--------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 16 ++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 22 +++++++++++----------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 6 +++--- .../drm/amd/display/dc/dce100/dce100_resource.h | 2 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 14 +++++++------- .../drm/amd/display/dc/dce112/dce112_resource.c | 2 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 2 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 6 +++--- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 ++-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 22 files changed, 84 insertions(+), 84 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7b597a0a2ab9..af6bed907d10 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1819,7 +1819,7 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_surface *surface) + struct dc_plane_state *surface) { surface->src_rect.x = state->src_x >> 16; surface->src_rect.y = state->src_y >> 16; @@ -1894,7 +1894,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -2048,7 +2048,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_surface *dc_surface) + struct dc_plane_state *dc_surface) { int i; struct dc_gamma *gamma; @@ -2072,7 +2072,7 @@ static void fill_gamma_from_crtc_state( static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_surface *surface, + struct dc_plane_state *surface, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -3059,7 +3059,7 @@ static int dm_plane_helper_prepare_fb( if (dm_plane_state_new->surface && dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_surface *surface = dm_plane_state_new->surface; + struct dc_plane_state *surface = dm_plane_state_new->surface; if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { surface->address.grph.addr.low_part = lower_32_bits(afb->address); @@ -3160,7 +3160,7 @@ int dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->surface) return true; - if (dc_validate_surface(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->surface)) return 0; return -EINVAL; @@ -3926,7 +3926,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream *dc_stream_attach; - struct dc_surface *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -4377,7 +4377,7 @@ static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream *stream, - struct dc_surface *surface) + struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4699,7 +4699,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_surface *surface; + struct dc_plane_state *surface; surface = dc_create_surface(dc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index ce0223af7d5f..dcf1f77390a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -189,14 +189,14 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( struct amdgpu_framebuffer; struct amdgpu_display_manager; struct dc_validation_set; -struct dc_surface; +struct dc_plane_state; /* TODO rename to dc_stream_state */ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_surface *surface; + struct dc_plane_state *surface; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5acf4c697ae8..500788c35d70 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -645,7 +645,7 @@ static bool is_validation_required( return true; for (j = 0; j < set[i].surface_count; j++) { - struct dc_surface temp_surf; + struct dc_plane_state temp_surf; memset(&temp_surf, 0, sizeof(temp_surf)); temp_surf = *context->stream_status[i].surfaces[j]; @@ -684,7 +684,7 @@ static bool validate_surfaces( for (i = 0; i < set_count; i++) for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_surface(dc, set[i].surfaces[j])) + if (!dc_validate_plane(dc, set[i].surfaces[j])) return false; return true; @@ -978,7 +978,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c const struct dc_sink *sink = context->streams[i]->sink; for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_surface *surface = + const struct dc_plane_state *surface = context->stream_status[i].surfaces[j]; core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); @@ -1136,7 +1136,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **new_surfaces, + struct dc_plane_state **new_surfaces, uint8_t new_surface_count, struct dc_stream *dc_stream) { @@ -1220,7 +1220,7 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { int j; @@ -1470,7 +1470,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_surface *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) new_surfaces[i] = srf_updates[i].surface; @@ -1496,7 +1496,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* save update parameters into surface */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (srf_updates[i].flip_addr) { surface->address = srf_updates[i].flip_addr->address; @@ -1599,7 +1599,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; @@ -1649,7 +1649,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = srf_updates[i].surface; + struct dc_plane_state *surface = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index bf127a88e533..e8d4b8c3ac2b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count) { int i; @@ -46,7 +46,7 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_surface *surface = surfaces[i]; + const struct dc_plane_state *surface = surfaces[i]; SURFACE_TRACE("Surface %d:\n", i); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 005eac5fae80..fd1d6be79fee 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,7 +430,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; @@ -529,7 +529,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; @@ -607,7 +607,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; const struct dc_stream *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_surface *surface = pipe_ctx->surface; + const struct dc_plane_state *surface = pipe_ctx->surface; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_surface * const *surfaces, + struct dc_plane_state * const *surfaces, int surface_count, struct dc_stream *stream, struct validate_context *context, @@ -1075,7 +1075,7 @@ bool resource_attach_surfaces_to_context( tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_surface *surface = surfaces[i]; + struct dc_plane_state *surface = surfaces[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1351,7 +1351,7 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_surface *surface = to_pipe_ctx->surface; + struct dc_plane_state *surface = to_pipe_ctx->surface; struct dc_stream *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_surface *surface, + struct dc_plane_state *surface, struct dc_stream *stream) { uint16_t i = 0; @@ -2534,13 +2534,13 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) return res == DC_OK; } -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface) +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state) { struct core_dc *core_dc = DC_TO_CORE(dc); /* TODO For now validates pixel format only */ - if (core_dc->res_pool->funcs->validate_surface) - return core_dc->res_pool->funcs->validate_surface(surface) == DC_OK; + if (core_dc->res_pool->funcs->validate_plane) + return core_dc->res_pool->funcs->validate_plane(plane_state) == DC_OK; return true; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index eded6b7da97d..941b3671375d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,7 +34,7 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_surface *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) { surface->ctx = ctx; memset(&surface->hdr_static_ctx, @@ -42,7 +42,7 @@ static bool construct(struct dc_context *ctx, struct dc_surface *surface) return true; } -static void destruct(struct dc_surface *surface) +static void destruct(struct dc_plane_state *surface) { if (surface->gamma_correction != NULL) { dc_gamma_release(&surface->gamma_correction); @@ -57,18 +57,18 @@ static void destruct(struct dc_surface *surface) /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_surface *surface, +void enable_surface_flip_reporting(struct dc_plane_state *surface, uint32_t controller_id) { surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_surface *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_surface(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_surface *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); if (NULL == surface) goto alloc_fail; @@ -88,7 +88,7 @@ alloc_fail: } const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface) + const struct dc_plane_state *dc_surface) { const struct dc_surface_status *surface_status; struct core_dc *core_dc; @@ -120,13 +120,13 @@ const struct dc_surface_status *dc_surface_get_status( return surface_status; } -void dc_surface_retain(struct dc_surface *surface) +void dc_surface_retain(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); ++surface->ref_count; } -void dc_surface_release(struct dc_surface *surface) +void dc_surface_release(struct dc_plane_state *surface) { ASSERT(surface->ref_count > 0); --surface->ref_count; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d03218d6210a..d1943b9644d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -92,7 +92,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; -struct dc_surface; +struct dc_plane_state; struct validate_context; struct dc_cap_funcs { @@ -310,7 +310,7 @@ struct dc_surface_status { bool is_right_eye; }; -struct dc_surface { +struct dc_plane_state { struct dc_plane_address address; struct scaling_taps scaling_quality; @@ -367,7 +367,7 @@ struct dc_scaling_info { }; struct dc_surface_update { - struct dc_surface *surface; + struct dc_plane_state *surface; /* isr safe update parameters. null means no updates */ struct dc_flip_addrs *flip_addr; @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_surface *dc_create_surface(const struct dc *dc); +struct dc_plane_state *dc_create_surface(const struct dc *dc); const struct dc_surface_status *dc_surface_get_status( - const struct dc_surface *dc_surface); + const struct dc_plane_state *dc_surface); -void dc_surface_retain(struct dc_surface *dc_surface); -void dc_surface_release(struct dc_surface *dc_surface); +void dc_surface_retain(struct dc_plane_state *dc_surface); +void dc_surface_release(struct dc_plane_state *dc_surface); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -424,7 +424,7 @@ struct dc_flip_addrs { bool dc_commit_surfaces_to_stream( struct dc *dc, - struct dc_surface **dc_surfaces, + struct dc_plane_state **dc_surfaces, uint8_t surface_count, struct dc_stream *stream); @@ -470,7 +470,7 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; int surface_count; - struct dc_surface *surfaces[MAX_SURFACE_NUM]; + struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -582,13 +582,13 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, */ struct dc_validation_set { struct dc_stream *stream; - struct dc_surface *surfaces[MAX_SURFACES]; + struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); -bool dc_validate_surface(const struct dc *dc, const struct dc_surface *surface); +bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* * This function takes a set of resources and checks that they are cofunctional. * diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 4c5e797da5b1..3c0b47373dfb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -528,7 +528,7 @@ enum dc_quantization_range { /* XFM */ -/* used in struct dc_surface */ +/* used in struct dc_plane_state */ struct scaling_taps { uint32_t v_taps; uint32_t h_taps; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index ee9e6bc88c32..4fb9584452a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -34,7 +34,7 @@ #include "grph_object_defs.h" /* forward declarations */ -struct dc_surface; +struct dc_plane_state; struct dc_stream; struct dc_link; struct dc_sink; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index c46b3e82cdcc..af59ab93796a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,7 +197,7 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_surface *surface) +bool dce_use_lut(const struct dc_plane_state *surface) { switch (surface->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index ade7507e99c7..d5cb98a92c53 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_surface *surface); +bool dce_use_lut(const struct dc_plane_state *surface); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 59f4caf057f7..2cf2fefc3d79 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -804,10 +804,10 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) *pool = NULL; } -enum dc_status dce100_validate_surface(const struct dc_surface *surface) +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) { - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return DC_OK; return DC_FAIL_SURFACE_VALIDATE; @@ -819,7 +819,7 @@ static const struct resource_funcs dce100_res_pool_funcs = { .validate_with_context = dce100_validate_with_context, .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, - .validate_surface = dce100_validate_surface, + .validate_plane = dce100_validate_plane, }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h index 13fc637eb731..edc50caf04d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h @@ -16,6 +16,6 @@ struct resource_pool *dce100_create_resource_pool( uint8_t num_virtual_links, struct core_dc *dc); -enum dc_status dce100_validate_surface(const struct dc_surface *surface); +enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state); #endif /* DCE100_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 1f18fcf52661..84dc8916de96 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,7 +215,7 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface) + const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2123,7 +2123,7 @@ static void set_plane_config( static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2138,7 +2138,7 @@ static void update_plane_addr(const struct core_dc *dc, void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2614,7 +2614,7 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 495f38750ae4..c68372fa1292 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -994,7 +994,7 @@ static const struct resource_funcs dce112_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b31307b9d3e3..45f5fd63ce14 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -701,7 +701,7 @@ static const struct resource_funcs dce120_res_pool_funcs = { .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static void bw_calcs_data_update_from_pplib(struct core_dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 6eeb5e9f656f..bcb66447b558 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -825,7 +825,7 @@ static const struct resource_funcs dce80_res_pool_funcs = { .validate_with_context = dce80_validate_with_context, .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, - .validate_surface = dce100_validate_surface + .validate_plane = dce100_validate_plane }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index fa19c6b92f29..3979cb03cf8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1038,7 +1038,7 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; bool sec_split = pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == pipe_ctx->surface; if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && @@ -1065,7 +1065,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; if (surface == NULL) return; @@ -1080,7 +1080,7 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_surface *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_surface *dc_surface = pipe_ctx->surface; + struct dc_plane_state *dc_surface = pipe_ctx->surface; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1898,7 +1898,7 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; union plane_size size = surface->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context) { int i, be_idx; @@ -2468,7 +2468,7 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_surface *surface = pipe_ctx->surface; + struct dc_plane_state *surface = pipe_ctx->surface; struct timing_generator *tg = pipe_ctx->tg; if (surface->ctx->dc->debug.sanity_checks) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index da52971d3f06..44a87c9427f7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_surface *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, uint32_t controller_id); #include "grph_object_id.h" @@ -104,7 +104,7 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_stream *stream); - enum dc_status (*validate_surface)(const struct dc_surface *surface); + enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; struct audio_support{ @@ -154,7 +154,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_surface *surface; + struct dc_plane_state *surface; struct dc_stream *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index b2f7ba2115c9..c529ddd2e0d5 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_surface *surface, + const struct dc_plane_state *surface, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_surface *surface); + const struct dc_plane_state *surface); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ca3f49379bea..bfd7cfc86df0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream *stream); bool resource_attach_surfaces_to_context( - struct dc_surface *const *surfaces, + struct dc_plane_state *const *surfaces, int surface_count, struct dc_stream *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0a872472ecba..0e978d921fdf 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_surface *const *surfaces, + const struct dc_plane_state *const *surfaces, int surface_count); void update_surface_trace( -- cgit v1.2.3 From 0971c40e180696c3512b9a63ca7ca5161cbfce32 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:33:33 -0400 Subject: drm/amd/display: Rename dc_stream to dc_stream_state find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream/struct dc_stream_state/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_update/struct dc_stream_update/g' find -name Makefile -o -name Kconfig -o -name "*.c" -o -name "*.h" \ -o -name "*.cpp" -o -name "*.hpp" | \ xargs sed -i 's/struct dc_stream_state_status/struct dc_stream_status/g' Plus some manual changes Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 ++++++------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 38 ++++++------ drivers/gpu/drm/amd/display/dc/core/dc_link.c | 18 +++--- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 68 +++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 26 ++++----- drivers/gpu/drm/amd/display/dc/dc.h | 58 +++++++++--------- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 4 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 16 ++--- .../drm/amd/display/dc/dce110/dce110_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 4 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 8 +-- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dm_helpers.h | 6 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 11 ++-- drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h | 4 +- .../gpu/drm/amd/display/dc/inc/hw/link_encoder.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 13 ++--- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../drm/amd/display/modules/freesync/freesync.c | 50 ++++++++-------- .../gpu/drm/amd/display/modules/inc/mod_freesync.h | 28 ++++----- 29 files changed, 222 insertions(+), 222 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index af6bed907d10..497104a29d89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -116,7 +116,8 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -137,7 +138,8 @@ static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, acrtc->base.state); if (acrtc_state->stream == NULL) { - DRM_ERROR("dc_stream is NULL for crtc '%d'!\n", crtc); + DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n", + crtc); return 0; } @@ -1441,7 +1443,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data, num_streams = dc_get_current_stream_count(adev->dm.dc); for (i = 0; i < num_streams; i++) { - struct dc_stream *stream; + struct dc_stream_state *stream; stream = dc_get_stream_at_index(adev->dm.dc, i); mod_freesync_update_state(adev->dm.freesync_module, @@ -1609,8 +1611,8 @@ struct dm_connector_state { container_of((x), struct dm_connector_state, base) static bool modeset_required(struct drm_crtc_state *crtc_state, - struct dc_stream *new_stream, - struct dc_stream *old_stream) + struct dc_stream_state *new_stream, + struct dc_stream_state *old_stream) { if (dc_is_stream_unchanged(new_stream, old_stream)) { crtc_state->mode_changed = false; @@ -2141,7 +2143,7 @@ struct amdgpu_connector *aconnector_from_drm_crtc_id( static void update_stream_scaling_settings( const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, - struct dc_stream *stream) + struct dc_stream_state *stream) { enum amdgpu_rmx_type rmx_type; @@ -2285,7 +2287,7 @@ static enum dc_color_space get_output_color_space( /*****************************************************************************/ static void fill_stream_properties_from_drm_display_mode( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct drm_display_mode *mode_in, const struct drm_connector *connector) { @@ -2426,14 +2428,14 @@ static void decide_crtc_timing_for_drm_display_mode( } } -static struct dc_stream *create_stream_for_sink( +static struct dc_stream_state *create_stream_for_sink( struct amdgpu_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; - struct dc_stream *stream = NULL; + struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -2842,7 +2844,7 @@ int amdgpu_dm_connector_mode_valid( struct dc_sink *dc_sink; struct amdgpu_device *adev = connector->dev->dev_private; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || @@ -3119,7 +3121,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, struct dc_sink *dc_sink = to_amdgpu_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ - struct dc_stream *stream; + struct dc_stream_state *stream; if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -3770,7 +3772,7 @@ static bool is_scaling_state_different( static void remove_stream( struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -3925,7 +3927,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, uint32_t i; struct drm_plane *plane; struct drm_plane_state *old_plane_state; - struct dc_stream *dc_stream_attach; + struct dc_stream_state *dc_stream_attach; struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); @@ -4061,7 +4063,7 @@ void amdgpu_dm_atomic_commit_tail( struct drm_crtc *crtc, *pcrtc; struct drm_crtc_state *old_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; @@ -4220,7 +4222,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(acrtc->base.state); update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream *)new_acrtc_state->stream); + con_new_state, (struct dc_stream_state *)new_acrtc_state->stream); status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); @@ -4376,7 +4378,7 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector static uint32_t add_val_sets_surface( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_plane_state *surface) { uint32_t i = 0, j = 0; @@ -4399,8 +4401,8 @@ static uint32_t add_val_sets_surface( static uint32_t update_in_val_sets_stream( struct dc_validation_set *val_sets, uint32_t set_count, - struct dc_stream *old_stream, - struct dc_stream *new_stream, + struct dc_stream_state *old_stream, + struct dc_stream_state *new_stream, struct drm_crtc *crtc) { uint32_t i = 0; @@ -4423,7 +4425,7 @@ static uint32_t update_in_val_sets_stream( static uint32_t remove_from_val_sets( struct dc_validation_set *val_sets, uint32_t set_count, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { int i; @@ -4545,7 +4547,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; - struct dc_stream *new_stream = NULL; + struct dc_stream_state *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_conn_state = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index dcf1f77390a8..cca65a37b213 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -201,7 +201,7 @@ struct dm_plane_state { struct dm_crtc_state { struct drm_crtc_state base; - struct dc_stream *stream; + struct dc_stream_state *stream; }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0a615583de63..4a124537dc9a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -174,7 +174,7 @@ static void get_payload_table( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable) { @@ -264,7 +264,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct amdgpu_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; @@ -290,7 +290,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable) { struct amdgpu_connector *aconnector; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 500788c35d70..8b6b7631d776 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -149,12 +149,12 @@ failed_alloc: } static bool stream_adjust_vmin_vmax(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, int vmin, int vmax) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; @@ -175,12 +175,12 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, } static bool stream_get_crtc_position(struct dc *dc, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos) { /* TODO: Support multiple streams */ struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_stream *stream = streams[0]; + struct dc_stream_state *stream = streams[0]; int i = 0; bool ret = false; struct crtc_position position; @@ -200,7 +200,7 @@ static bool stream_get_crtc_position(struct dc *dc, return ret; } -static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) +static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -218,7 +218,7 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream *stream) return ret; } -static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) +static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); int i = 0; @@ -241,7 +241,7 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream *stream) } static void set_static_screen_events(struct dc *dc, - struct dc_stream **streams, + struct dc_stream_state **streams, int num_streams, const struct dc_static_screen_events *events) { @@ -252,7 +252,7 @@ static void set_static_screen_events(struct dc *dc, int num_pipes_affected = 0; for (i = 0; i < num_streams; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { if (core_dc->current_context->res_ctx.pipe_ctx[j].stream @@ -333,7 +333,7 @@ static void set_test_pattern( cust_pattern_size); } -void set_dither_option(struct dc_stream *stream, +void set_dither_option(struct dc_stream_state *stream, enum dc_dither_option option) { struct bit_depth_reduction_params params; @@ -769,7 +769,7 @@ context_alloc_fail: bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); enum dc_status result = DC_ERROR_UNEXPECTED; @@ -893,7 +893,7 @@ static bool context_changed( static bool streams_changed( struct core_dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { uint8_t i; @@ -912,7 +912,7 @@ static bool streams_changed( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { bool ret = true; @@ -958,7 +958,7 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c enum dc_status result = DC_ERROR_UNEXPECTED; struct pipe_ctx *pipe; int i, j, k, l; - struct dc_stream *dc_streams[MAX_STREAMS] = {0}; + struct dc_stream_state *dc_streams[MAX_STREAMS] = {0}; for (i = 0; i < context->stream_count; i++) dc_streams[i] = context->streams[i]; @@ -1031,7 +1031,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) __func__, context->stream_count); for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; dc_stream_log(stream, core_dc->ctx->logger, @@ -1046,7 +1046,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1062,7 +1062,7 @@ bool dc_commit_streams( __func__, stream_count); for (i = 0; i < stream_count; i++) { - struct dc_stream *stream = streams[i]; + struct dc_stream_state *stream = streams[i]; struct dc_stream_status *status = dc_stream_get_status(stream); int j; @@ -1138,7 +1138,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **new_surfaces, uint8_t new_surface_count, - struct dc_stream *dc_stream) + struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -1395,7 +1395,7 @@ enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_stream_update *stream_update) { struct core_dc *core_dc = DC_TO_CORE(dc); @@ -1723,7 +1723,7 @@ uint8_t dc_get_current_stream_count(const struct dc *dc) return core_dc->current_context->stream_count; } -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i) +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i) { struct core_dc *core_dc = DC_TO_CORE(dc); if (i < core_dc->current_context->stream_count) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index a983a5ee3172..7a2fe2f3e65c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode( static void enable_stream_features(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; union down_spread_ctrl downspread; @@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx) static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_status status; bool skip_video_pattern; struct dc_link *link = stream->sink->link; @@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx) static void enable_link_hdmi(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; enum dc_color_depth display_color_depth; @@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal) } enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing) { @@ -1374,7 +1374,7 @@ enum dc_status dc_link_validate_mode_timing( bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream) + uint32_t frame_ramp, const struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); struct abm *abm = core_dc->res_pool->abm; @@ -1450,7 +1450,7 @@ bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state) } bool dc_link_setup_psr(struct dc_link *link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context) { struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc); @@ -1587,7 +1587,7 @@ void core_link_resume(struct dc_link *link) program_hpd_filter(link); } -static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream) +static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream) { struct dc_link_settings *link_settings = &stream->sink->link->cur_link_settings; @@ -1696,7 +1696,7 @@ static void update_mst_stream_alloc_table( */ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; @@ -1778,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx) static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; struct link_encoder *link_encoder = link->link_enc; struct stream_encoder *stream_encoder = pipe_ctx->stream_enc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 17506345f97a..50724f9a8e2c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -1433,7 +1433,7 @@ bool dp_validate_mode_timing( return false; } -void decide_link_settings(struct dc_stream *stream, +void decide_link_settings(struct dc_stream_state *stream, struct dc_link_settings *link_setting) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fd1d6be79fee..ce0415f26600 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -294,8 +294,8 @@ void resource_reference_clock_source( } bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2) + struct dc_stream_state *stream1, + struct dc_stream_state *stream2) { if (stream1->timing.h_total != stream2->timing.h_total) return false; @@ -431,7 +431,7 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; struct rect surf_src = surface->src_rect; struct rect clip = { 0 }; @@ -530,7 +530,7 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; struct rect surf_clip = surface->clip_rect; int recout_full_x, recout_full_y; @@ -608,7 +608,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { const struct dc_plane_state *surface = pipe_ctx->surface; - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; struct rect surf_src = surface->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; @@ -920,7 +920,7 @@ struct pipe_ctx *find_idle_secondary_pipe( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; for (i = 0; i < MAX_PIPES; i++) { @@ -940,7 +940,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( static struct pipe_ctx *acquire_free_pipe_for_stream( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; struct resource_context *res_ctx = &context->res_ctx; @@ -979,7 +979,7 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( static void release_free_pipes_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -997,7 +997,7 @@ static void release_free_pipes_for_stream( static int acquire_first_split_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1030,7 +1030,7 @@ static int acquire_first_split_pipe( bool resource_attach_surfaces_to_context( struct dc_plane_state * const *surfaces, int surface_count, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context, const struct resource_pool *pool) { @@ -1118,8 +1118,8 @@ bool resource_attach_surfaces_to_context( } -static bool is_timing_changed(struct dc_stream *cur_stream, - struct dc_stream *new_stream) +static bool is_timing_changed(struct dc_stream_state *cur_stream, + struct dc_stream_state *new_stream) { if (cur_stream == NULL) return true; @@ -1141,7 +1141,7 @@ static bool is_timing_changed(struct dc_stream *cur_stream, } static bool are_stream_backends_same( - struct dc_stream *stream_a, struct dc_stream *stream_b) + struct dc_stream_state *stream_a, struct dc_stream_state *stream_b) { if (stream_a == stream_b) return true; @@ -1156,7 +1156,7 @@ static bool are_stream_backends_same( } bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream) + struct dc_stream_state *old_stream, struct dc_stream_state *stream) { if (!are_stream_backends_same(old_stream, stream)) @@ -1233,7 +1233,7 @@ static void set_audio_in_use( static int acquire_first_free_pipe( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; @@ -1260,7 +1260,7 @@ static int acquire_first_free_pipe( static struct stream_encoder *find_first_free_match_stream_enc_for_link( struct resource_context *res_ctx, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i; int j = -1; @@ -1311,7 +1311,7 @@ static struct audio *find_first_free_audio( return 0; } -static void update_stream_signal(struct dc_stream *stream) +static void update_stream_signal(struct dc_stream_state *stream) { if (stream->output_signal == SIGNAL_TYPE_NONE) { struct dc_sink *dc_sink = stream->sink; @@ -1334,12 +1334,12 @@ static void update_stream_signal(struct dc_stream *stream) } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream) + struct validate_context *old_context, struct dc_stream_state *stream) { int i; for (i = 0; i < old_context->stream_count; i++) { - struct dc_stream *old_stream = old_context->streams[i]; + struct dc_stream_state *old_stream = old_context->streams[i]; if (are_stream_backends_same(old_stream, stream)) return true; @@ -1352,7 +1352,7 @@ static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { struct dc_plane_state *surface = to_pipe_ctx->surface; - struct dc_stream *stream = to_pipe_ctx->stream; + struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; @@ -1360,14 +1360,14 @@ static void copy_pipe_ctx( to_pipe_ctx->surface = surface; } -static struct dc_stream *find_pll_sharable_stream( - struct dc_stream *stream_needs_pll, +static struct dc_stream_state *find_pll_sharable_stream( + struct dc_stream_state *stream_needs_pll, struct validate_context *context) { int i; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream_has_pll = context->streams[i]; + struct dc_stream_state *stream_has_pll = context->streams[i]; /* We are looking for non dp, non virtual stream */ if (resource_are_streams_timing_synchronizable( @@ -1411,7 +1411,7 @@ static int get_norm_pix_clk(const struct dc_crtc_timing *timing) return normalized_pix_clk; } -static void calculate_phy_pix_clks(struct dc_stream *stream) +static void calculate_phy_pix_clks(struct dc_stream_state *stream) { update_stream_signal(stream); @@ -1433,7 +1433,7 @@ enum dc_status resource_map_pool_resources( int i, j; for (i = 0; old_context && i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -1486,7 +1486,7 @@ enum dc_status resource_map_pool_resources( } for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; struct pipe_ctx *pipe_ctx = NULL; int pipe_idx = -1; @@ -1581,7 +1581,7 @@ static void set_avi_info_frame( struct encoder_info_packet *info_packet, struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space = COLOR_SPACE_UNKNOWN; struct info_frame info_frame = { {0} }; uint32_t pixel_encoding = 0; @@ -1821,7 +1821,7 @@ static void set_avi_info_frame( static void set_vendor_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint32_t length = 0; bool hdmi_vic_mode = false; @@ -1934,7 +1934,7 @@ static void set_vendor_info_packet( static void set_spd_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { /* SPD info packet for FreeSync */ @@ -2056,7 +2056,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, struct dc_plane_state *surface, - struct dc_stream *stream) + struct dc_stream_state *stream) { uint16_t i = 0; enum signal_type signal = stream->signal; @@ -2159,7 +2159,7 @@ static void set_hdr_static_info_packet( static void set_vsc_info_packet( struct encoder_info_packet *info_packet, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int vscPacketRevision = 0; unsigned int i; @@ -2312,7 +2312,7 @@ enum dc_status resource_map_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -2392,7 +2392,7 @@ bool pipe_need_reprogram( return false; } -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth) { enum dc_dither_option option = stream->dither_option; @@ -2502,7 +2502,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream) +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream) { struct core_dc *core_dc = DC_TO_CORE(dc); struct dc_context *dc_ctx = core_dc->ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a77e1e80d7c2..7a87f38f2324 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -34,7 +34,7 @@ * Private functions ******************************************************************************/ -static bool construct(struct dc_stream *stream, +static bool construct(struct dc_stream_state *stream, struct dc_sink *dc_sink_data) { uint32_t i = 0; @@ -84,7 +84,7 @@ static bool construct(struct dc_stream *stream, return true; } -static void destruct(struct dc_stream *stream) +static void destruct(struct dc_stream_state *stream) { dc_sink_release(stream->sink); if (stream->out_transfer_func != NULL) { @@ -94,14 +94,14 @@ static void destruct(struct dc_stream *stream) } } -void dc_stream_retain(struct dc_stream *stream) +void dc_stream_retain(struct dc_stream_state *stream) { ASSERT(stream->ref_count > 0); stream->ref_count++; } -void dc_stream_release(struct dc_stream *stream) +void dc_stream_release(struct dc_stream_state *stream) { if (stream != NULL) { @@ -115,15 +115,15 @@ void dc_stream_release(struct dc_stream *stream) } } -struct dc_stream *dc_create_stream_for_sink( +struct dc_stream_state *dc_create_stream_for_sink( struct dc_sink *sink) { - struct dc_stream *stream; + struct dc_stream_state *stream; if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream)); + stream = dm_alloc(sizeof(struct dc_stream_state)); if (NULL == stream) goto alloc_fail; @@ -143,7 +143,7 @@ alloc_fail: } struct dc_stream_status *dc_stream_get_status( - struct dc_stream *stream) + struct dc_stream_state *stream) { uint8_t i; struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); @@ -161,7 +161,7 @@ struct dc_stream_status *dc_stream_get_status( * Update the cursor attributes and set cursor surface address */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes) { int i; @@ -196,7 +196,7 @@ bool dc_stream_set_cursor_attributes( } bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position) { int i; @@ -245,7 +245,7 @@ bool dc_stream_set_cursor_position( return true; } -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) { uint8_t i; struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc); @@ -264,7 +264,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream) return 0; } -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -297,7 +297,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dm_logger, enum dc_log_type log_type) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d1943b9644d4..ab805965e321 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -101,30 +101,30 @@ struct dc_cap_funcs { struct dc_surface_dcc_cap *output); }; -struct dc_stream_funcs { +struct dc_stream_state_funcs { bool (*adjust_vmin_vmax)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, int vmin, int vmax); bool (*get_crtc_position)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, unsigned int *v_pos, unsigned int *nom_v_pos); bool (*set_gamut_remap)(struct dc *dc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); bool (*program_csc_matrix)(struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void (*set_static_screen_events)(struct dc *dc, - struct dc_stream **stream, + struct dc_stream_state **stream, int num_streams, const struct dc_static_screen_events *events); - void (*set_dither_option)(struct dc_stream *stream, + void (*set_dither_option)(struct dc_stream_state *stream, enum dc_dither_option option); }; @@ -190,7 +190,7 @@ struct dc_debug { struct dc { struct dc_caps caps; struct dc_cap_funcs cap_funcs; - struct dc_stream_funcs stream_funcs; + struct dc_stream_state_funcs stream_funcs; struct dc_link_funcs link_funcs; struct dc_config config; struct dc_debug debug; @@ -426,7 +426,7 @@ bool dc_commit_surfaces_to_stream( struct dc *dc, struct dc_plane_state **dc_surfaces, uint8_t surface_count, - struct dc_stream *stream); + struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -478,7 +478,7 @@ struct dc_stream_status { struct dc_link *link; }; -struct dc_stream { +struct dc_stream_state { struct dc_sink *sink; struct dc_crtc_timing timing; @@ -529,7 +529,7 @@ struct dc_stream_update { }; bool dc_is_stream_unchanged( - struct dc_stream *old_stream, struct dc_stream *stream); + struct dc_stream_state *old_stream, struct dc_stream_state *stream); /* * Setup stream attributes if no stream updates are provided @@ -548,30 +548,30 @@ bool dc_is_stream_unchanged( void dc_update_surfaces_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); /* * Log the current stream state. */ void dc_stream_log( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dal_logger *dc_logger, enum dc_log_type log_type); uint8_t dc_get_current_stream_count(const struct dc *dc); -struct dc_stream *dc_get_stream_at_index(const struct dc *dc, uint8_t i); +struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i); /* * Return the current frame counter. */ -uint32_t dc_stream_get_vblank_counter(const struct dc_stream *stream); +uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream); /* TODO: Return parsed values rather than direct register read * This has a dependency on the caller (amdgpu_get_crtc_scanoutpos) * being refactored properly to be dce-specific */ -bool dc_stream_get_scanoutpos(const struct dc_stream *stream, +bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *v_blank_start, uint32_t *v_blank_end, uint32_t *h_position, @@ -581,12 +581,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream, * Structure to store surface/stream associations for validation */ struct dc_validation_set { - struct dc_stream *stream; + struct dc_stream_state *stream; struct dc_plane_state *surfaces[MAX_SURFACES]; uint8_t surface_count; }; -bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream); +bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state); /* @@ -615,7 +615,7 @@ bool dc_validate_resources( bool dc_validate_guaranteed( const struct dc *dc, - struct dc_stream *stream); + struct dc_stream_state *stream); void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, @@ -644,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_commit_streams( struct dc *dc, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /* * Enable stereo when commit_streams is not required, @@ -653,19 +653,19 @@ bool dc_commit_streams( bool dc_enable_stereo( struct dc *dc, struct validate_context *context, - struct dc_stream *streams[], + struct dc_stream_state *streams[], uint8_t stream_count); /** * Create a new default stream for the requested sink */ -struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink); +struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink); -void dc_stream_retain(struct dc_stream *dc_stream); -void dc_stream_release(struct dc_stream *dc_stream); +void dc_stream_retain(struct dc_stream_state *dc_stream); +void dc_stream_release(struct dc_stream_state *dc_stream); struct dc_stream_status *dc_stream_get_status( - struct dc_stream *dc_stream); + struct dc_stream_state *dc_stream); enum surface_update_type dc_check_update_surfaces_for_stream( struct dc *dc, @@ -804,7 +804,7 @@ const struct graphics_object_id dc_get_link_id_at_index( /* Set backlight level of an embedded panel (eDP, LVDS). */ bool dc_link_set_backlight_level(const struct dc_link *dc_link, uint32_t level, - uint32_t frame_ramp, const struct dc_stream *stream); + uint32_t frame_ramp, const struct dc_stream_state *stream); bool dc_link_set_abm_disable(const struct dc_link *dc_link); @@ -813,7 +813,7 @@ bool dc_link_set_psr_enable(const struct dc_link *dc_link, bool enable); bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state); bool dc_link_setup_psr(struct dc_link *dc_link, - const struct dc_stream *stream, struct psr_config *psr_config, + const struct dc_stream_state *stream, struct psr_config *psr_config, struct psr_context *psr_context); /* Request DC to detect if there is a Panel connected. @@ -927,11 +927,11 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container ******************************************************************************/ /* TODO: Deprecated once we switch to dc_set_cursor_position */ bool dc_stream_set_cursor_attributes( - const struct dc_stream *stream, + const struct dc_stream_state *stream, const struct dc_cursor_attributes *attributes); bool dc_stream_set_cursor_position( - struct dc_stream *stream, + struct dc_stream_state *stream, const struct dc_cursor_position *position); /* Newer interfaces */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 4fb9584452a4..a47f7472ea92 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -35,7 +35,7 @@ /* forward declarations */ struct dc_plane_state; -struct dc_stream; +struct dc_stream_state; struct dc_link; struct dc_sink; struct dal; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 24d0c48258ee..5bb2ac71f297 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); bool is_valid; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h index 5f05ca65281e..5960fb933f1f 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h @@ -196,7 +196,7 @@ bool dce110_link_encoder_validate_wireless_output( bool dce110_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /****************** HW programming ************************/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 2cf2fefc3d79..98fb7f02a6fe 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -765,7 +765,7 @@ enum dc_status dce100_validate_with_context( enum dc_status dce100_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 84dc8916de96..e4310a376116 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -623,7 +623,7 @@ static bool dce110_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dce110_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -745,7 +745,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx) void dce110_disable_stream(struct pipe_ctx *pipe_ctx) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct dc_link *link = stream->sink->link; if (pipe_ctx->audio) { @@ -833,7 +833,7 @@ static void build_audio_output( const struct pipe_ctx *pipe_ctx, struct audio_output *audio_output) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; audio_output->engine_id = pipe_ctx->stream_enc->id; audio_output->signal = pipe_ctx->stream->signal; @@ -981,7 +981,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1037,7 +1037,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; @@ -1229,7 +1229,7 @@ void dce110_enable_accelerated_mode(struct core_dc *dc) static uint32_t compute_pstate_blackout_duration( struct bw_fixed blackout_duration, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { uint32_t total_dest_line_time_ns; uint32_t pstate_blackout_duration_ns; @@ -2325,7 +2325,7 @@ void dce110_fill_display_configs( for (j = 0; j < context->stream_count; j++) { int k; - const struct dc_stream *stream = context->streams[j]; + const struct dc_stream_state *stream = context->streams[j]; struct dm_pp_single_disp_config *cfg = &pp_display_cfg->disp_configs[num_cfgs]; const struct pipe_ctx *pipe_ctx = NULL; @@ -2370,7 +2370,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) uint32_t min_vertical_blank_time = -1; for (j = 0; j < context->stream_count; j++) { - struct dc_stream *stream = context->streams[j]; + struct dc_stream_state *stream = context->streams[j]; uint32_t vertical_blank_in_pixels = 0; uint32_t vertical_blank_time = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 5c1790b61290..89b21bd57a35 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -718,7 +718,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; /*TODO: is this halved for YCbCr 420? in that case we might want to move * the pixel clock normalization for hdmi up to here instead of doing it @@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -973,7 +973,7 @@ enum dc_status dce110_validate_with_context( enum dc_status dce110_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed( static struct pipe_ctx *dce110_acquire_underlay( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct core_dc *dc = DC_TO_CORE(stream->ctx->dc); struct resource_context *res_ctx = &context->res_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index c68372fa1292..68554d6edd94 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -700,7 +700,7 @@ static void destruct(struct dce110_resource_pool *pool) static struct clock_source *find_matching_pll( struct resource_context *res_ctx, const struct resource_pool *pool, - const struct dc_stream *const stream) + const struct dc_stream_state *const stream) { switch (stream->sink->link->link_enc->transmitter) { case TRANSMITTER_UNIPHY_A: @@ -731,7 +731,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -845,7 +845,7 @@ enum dc_status resource_map_phy_clock_resources( /* acquire new resources */ for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -949,7 +949,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index cb2c69fb05a6..feef559f1ecd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context( enum dc_status dce112_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context); bool dce112_validate_bandwidth( diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index bcb66447b558..734b35eddeed 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -677,7 +677,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) continue; @@ -781,7 +781,7 @@ enum dc_status dce80_validate_with_context( enum dc_status dce80_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 3979cb03cf8d..866f63d1259d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -679,7 +679,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( struct validate_context *context, struct core_dc *dc) { - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; enum dc_color_space color_space; struct tg_color black_color = {0}; bool enableStereo = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ? @@ -1445,7 +1445,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func static bool dcn10_set_output_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream) + const struct dc_stream_state *stream) { struct transform *xfm = pipe_ctx->xfm; @@ -2321,7 +2321,7 @@ static void set_plane_config( } static void dcn10_config_stereo_parameters( - struct dc_stream *stream, struct crtc_stereo_flags *flags) + struct dc_stream_state *stream, struct crtc_stereo_flags *flags) { enum view_3d_format view_format = stream->view_format; enum dc_timing_3d_format timing_3d_format =\ @@ -2360,7 +2360,7 @@ static void dcn10_config_stereo_parameters( static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc) { struct crtc_stereo_flags flags = { 0 }; - struct dc_stream *stream = pipe_ctx->stream; + struct dc_stream_state *stream = pipe_ctx->stream; dcn10_config_stereo_parameters(stream, &flags); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 9d44f42cbf96..5a9fcbc22d04 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -774,7 +774,7 @@ static void get_pixel_clock_parameters( const struct pipe_ctx *pipe_ctx, struct pixel_clk_params *pixel_clk_params) { - const struct dc_stream *stream = pipe_ctx->stream; + const struct dc_stream_state *stream = pipe_ctx->stream; pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz; pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id; pixel_clk_params->signal_type = pipe_ctx->stream->signal; @@ -796,7 +796,7 @@ static void get_pixel_clock_parameters( } -static void build_clamping_params(struct dc_stream *stream) +static void build_clamping_params(struct dc_stream_state *stream) { stream->clamping.clamping_level = CLAMPING_FULL_RANGE; stream->clamping.c_depth = stream->timing.display_color_depth; @@ -831,7 +831,7 @@ static enum dc_status build_mapped_resource( uint8_t i, j; for (i = 0; i < context->stream_count; i++) { - struct dc_stream *stream = context->streams[i]; + struct dc_stream_state *stream = context->streams[i]; if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { @@ -916,7 +916,7 @@ enum dc_status dcn10_validate_with_context( enum dc_status dcn10_validate_guaranteed( const struct core_dc *dc, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -947,7 +947,7 @@ enum dc_status dcn10_validate_guaranteed( static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream) + struct dc_stream_state *stream) { struct resource_context *res_ctx = &context->res_ctx; struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index e8bd501feb48..39010325cef9 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -45,7 +45,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( */ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dp_mst_stream_allocation_table *proposed_table, bool enable); @@ -54,13 +54,13 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( */ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); /* * Sends ALLOCATE_PAYLOAD message. */ bool dm_helpers_dp_mst_send_payload_allocation( struct dc_context *ctx, - const struct dc_stream *stream, + const struct dc_stream_state *stream, bool enable); bool dm_helpers_dp_mst_start_top_mgr( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 44a87c9427f7..d5c0f9e34ce9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -60,7 +60,7 @@ struct dc_link *link_create(const struct link_init_data *init_params); void link_destroy(struct dc_link **link); enum dc_status dc_link_validate_mode_timing( - const struct dc_stream *stream, + const struct dc_stream_state *stream, struct dc_link *link, const struct dc_crtc_timing *timing); @@ -92,7 +92,7 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( const struct core_dc *dc, - struct dc_stream *stream, + struct dc_stream_state *stream, struct validate_context *context); bool (*validate_bandwidth)( @@ -102,8 +102,7 @@ struct resource_funcs { struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, - struct dc_stream *stream); - + struct dc_stream_state *stream); enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); }; @@ -155,7 +154,7 @@ struct resource_pool { struct pipe_ctx { struct dc_plane_state *surface; - struct dc_stream *stream; + struct dc_stream_state *stream; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -240,7 +239,7 @@ union bw_context { }; struct validate_context { - struct dc_stream *streams[MAX_PIPES]; + struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h index 1a4a605cb449..7168dcc70ae7 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h @@ -30,7 +30,7 @@ #define LINK_TRAINING_RETRY_DELAY 50 /* ms */ struct dc_link; -struct dc_stream; +struct dc_stream_state; struct dc_link_settings; bool dp_hbr_verify_link_cap( @@ -50,7 +50,7 @@ bool dp_validate_mode_timing( const struct dc_crtc_timing *timing); void decide_link_settings( - struct dc_stream *stream, + struct dc_stream_state *stream, struct dc_link_settings *link_setting); bool perform_link_training_with_retries( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 28fb02fb677e..38e4070806cb 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -93,7 +93,7 @@ struct link_encoder { struct link_encoder_funcs { bool (*validate_output_with_stream)( - struct link_encoder *enc, const struct dc_stream *stream); + struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); void (*setup)(struct link_encoder *enc, enum signal_type signal); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index c529ddd2e0d5..7e03f8d45b2b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -92,7 +92,7 @@ struct hw_sequencer_funcs { bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_stream *stream); + const struct dc_stream_state *stream); void (*power_down)(struct core_dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index bfd7cfc86df0..aef1197cf749 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -103,8 +103,8 @@ void resource_reference_clock_source( struct clock_source *clock_source); bool resource_are_streams_timing_synchronizable( - struct dc_stream *stream1, - struct dc_stream *stream2); + struct dc_stream_state *stream1, + struct dc_stream_state *stream2); struct clock_source *resource_find_used_clk_src_for_sharing( struct resource_context *res_ctx, @@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll( struct pipe_ctx *resource_get_head_pipe_for_stream( struct resource_context *res_ctx, - struct dc_stream *stream); + struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( struct dc_plane_state *const *surfaces, int surface_count, - struct dc_stream *dc_stream, + struct dc_stream_state *dc_stream, struct validate_context *context, const struct resource_pool *pool); @@ -130,8 +130,7 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream *stream); - + struct validate_context *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], @@ -162,7 +161,7 @@ bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, struct pipe_ctx *pipe_ctx); -void resource_build_bit_depth_reduction_params(struct dc_stream *stream, +void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, struct bit_depth_reduction_params *fmt_bit_depth); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index dd024c99fb7e..57b5a3babdf8 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -30,7 +30,7 @@ static bool virtual_link_encoder_validate_output_with_stream( struct link_encoder *enc, - const struct dc_stream *stream) { return true; } + const struct dc_stream_state *stream) { return true; } static void virtual_link_encoder_hw_init(struct link_encoder *enc) {} diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 358f8a855a59..f0a3e4332a09 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -111,7 +111,7 @@ struct freesync_state { }; struct freesync_entity { - struct dc_stream *stream; + struct dc_stream_state *stream; struct mod_freesync_caps *caps; struct freesync_state state; struct mod_freesync_user_enable user_enable; @@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) * on the core_freesync->map and returns the corresponding index */ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = 0; @@ -244,7 +244,7 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync, } bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps) + struct dc_stream_state *stream, struct mod_freesync_caps *caps) { struct core_dc *core_dc = NULL; struct core_freesync *core_freesync = NULL; @@ -322,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, } bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { int i = 0; struct core_freesync *core_freesync = NULL; @@ -344,7 +344,7 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, } static void update_stream_freesync_context(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index; struct freesync_context *ctx; @@ -368,7 +368,7 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync, } static void update_stream(struct core_freesync *core_freesync, - struct dc_stream *stream) + struct dc_stream_state *stream) { unsigned int index = map_index_from_stream(core_freesync, stream); if (core_freesync->map[index].caps->supported) { @@ -378,7 +378,7 @@ static void update_stream(struct core_freesync *core_freesync, } static void calc_freesync_range(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct freesync_state *state, unsigned int min_refresh_in_uhz, unsigned int max_refresh_in_uhz) @@ -452,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync, min_frame_duration_in_ns) / 2000; } -static void calc_v_total_from_duration(struct dc_stream *stream, +static void calc_v_total_from_duration(struct dc_stream_state *stream, unsigned int duration_in_ns, int *v_total_nominal) { *v_total_nominal = div64_u64(div64_u64(((unsigned long long)( @@ -461,7 +461,7 @@ static void calc_v_total_from_duration(struct dc_stream *stream, } static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int index, int *v_total) { unsigned int frame_duration = 0; @@ -557,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state) * Sets freesync mode on a stream depending on current freesync state. */ static bool set_freesync_on_streams(struct core_freesync *core_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { int v_total_nominal = 0, v_total_min = 0, v_total_max = 0; unsigned int stream_idx, map_index = 0; @@ -729,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync, } void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int index, v_total, inserted_frame_v_total = 0; unsigned int min_frame_duration_in_ns, vmax, vmin = 0; @@ -839,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, } void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params) { bool freesync_program_required = false; @@ -929,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync, bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params) { unsigned int index = 0; @@ -965,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync, } bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable) { unsigned int stream_index, map_index; @@ -1017,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable) { unsigned int index = 0; @@ -1035,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, } bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active) { unsigned int index = 0; @@ -1054,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, } bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps) @@ -1107,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh) { @@ -1129,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, } bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax) { @@ -1151,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, } bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos) { @@ -1179,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, } void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams) + struct dc_stream_state **streams, int num_streams) { unsigned int stream_index, map_index; struct freesync_state *state; @@ -1239,7 +1239,7 @@ void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, * is required, depending on the times calculated */ static void update_timestamps(struct core_freesync *core_freesync, - const struct dc_stream *stream, unsigned int map_index, + const struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1304,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync, } static void apply_below_the_range(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index, + struct dc_stream_state *stream, unsigned int map_index, unsigned int last_render_time_in_us) { unsigned int inserted_frame_duration_in_us = 0; @@ -1403,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync, } static void apply_fixed_refresh(struct core_freesync *core_freesync, - struct dc_stream *stream, unsigned int map_index) + struct dc_stream_state *stream, unsigned int map_index) { unsigned int vmin = 0, vmax = 0; struct freesync_state *state = &core_freesync->map[map_index].state; @@ -1434,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync, } void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp_in_us) { unsigned int stream_index, map_index, last_render_time_in_us = 0; diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h index 2b9d45100bdd..84b53425f2c8 100644 --- a/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h +++ b/drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h @@ -101,67 +101,67 @@ struct mod_freesync_params { * Add stream to be tracked by module */ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream, struct mod_freesync_caps *caps); + struct dc_stream_state *stream, struct mod_freesync_caps *caps); /* * Remove stream to be tracked by module */ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync, - struct dc_stream *stream); + struct dc_stream_state *stream); /* * Update the freesync state flags for each display and program * freesync accordingly */ void mod_freesync_update_state(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_params *freesync_params); bool mod_freesync_get_state(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_params *freesync_params); bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, struct mod_freesync_user_enable *user_enable); bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, bool *is_ramp_active); bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *streams, + struct dc_stream_state *streams, unsigned int min_refresh, unsigned int max_refresh, struct mod_freesync_caps *caps); bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *min_refresh, unsigned int *max_refresh); bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *vmin, unsigned int *vmax); bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync, - struct dc_stream *stream, + struct dc_stream_state *stream, unsigned int *nom_v_pos, unsigned int *v_pos); void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams); + struct dc_stream_state **streams, int num_streams); void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync, - struct dc_stream **streams, int num_streams, + struct dc_stream_state **streams, int num_streams, unsigned int curr_time_stamp); #endif -- cgit v1.2.3 From 3be5262e353b8ab97c528bfc7d0dd3c820e4ba27 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 27 Jul 2017 09:55:38 -0400 Subject: drm/amd/display: Rename more dc_surface stuff to plane_state Signed-off-by: Harry Wentland Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 288 +++++++++++---------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 20 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 52 ++-- drivers/gpu/drm/amd/display/dc/core/dc.c | 130 +++++----- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 188 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 190 +++++++------- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 74 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 32 +-- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 8 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 125 +++++---- .../drm/amd/display/dc/dce110/dce110_resource.c | 20 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 8 +- .../drm/amd/display/dc/dce120/dce120_resource.c | 2 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 8 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 140 +++++----- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 2 +- 24 files changed, 658 insertions(+), 657 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 497104a29d89..08567b3631cf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -70,7 +70,7 @@ #include "i2caux_interface.h" -static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -79,14 +79,14 @@ static enum drm_plane_type dm_surfaces_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, }; -static enum drm_plane_type dm_surfaces_type_carizzo[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ }; -static enum drm_plane_type dm_surfaces_type_stoney[AMDGPU_MAX_PLANES] = { +static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ @@ -1285,11 +1285,11 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) return -1; } - for (i = 0; i < dm->dc->caps.max_surfaces; i++) { + for (i = 0; i < dm->dc->caps.max_planes; i++) { mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); if (!mode_info->planes[i]) { - DRM_ERROR("KMS: Failed to allocate surface\n"); + DRM_ERROR("KMS: Failed to allocate plane\n"); goto fail_free_planes; } mode_info->planes[i]->base.type = mode_info->plane_type[i]; @@ -1389,7 +1389,7 @@ fail_free_encoder: fail_free_connector: kfree(aconnector); fail_free_planes: - for (i = 0; i < dm->dc->caps.max_surfaces; i++) + for (i = 0; i < dm->dc->caps.max_planes; i++) kfree(mode_info->planes[i]); return -1; } @@ -1518,52 +1518,52 @@ static int dm_early_init(void *handle) adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 7; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_CARRIZO: adev->mode_info.num_crtc = 3; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_carizzo; + adev->mode_info.plane_type = dm_plane_type_carizzo; break; case CHIP_STONEY: adev->mode_info.num_crtc = 2; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; - adev->mode_info.plane_type = dm_surfaces_type_stoney; + adev->mode_info.plane_type = dm_plane_type_stoney; break; case CHIP_POLARIS11: case CHIP_POLARIS12: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; case CHIP_VEGA10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: adev->mode_info.num_crtc = 4; adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; - adev->mode_info.plane_type = dm_surfaces_type_default; + adev->mode_info.plane_type = dm_plane_type_default; break; #endif default: @@ -1821,50 +1821,50 @@ static int dm_crtc_cursor_move(struct drm_crtc *crtc, static bool fill_rects_from_plane_state( const struct drm_plane_state *state, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { - surface->src_rect.x = state->src_x >> 16; - surface->src_rect.y = state->src_y >> 16; + plane_state->src_rect.x = state->src_x >> 16; + plane_state->src_rect.y = state->src_y >> 16; /*we ignore for now mantissa and do not to deal with floating pixels :(*/ - surface->src_rect.width = state->src_w >> 16; + plane_state->src_rect.width = state->src_w >> 16; - if (surface->src_rect.width == 0) + if (plane_state->src_rect.width == 0) return false; - surface->src_rect.height = state->src_h >> 16; - if (surface->src_rect.height == 0) + plane_state->src_rect.height = state->src_h >> 16; + if (plane_state->src_rect.height == 0) return false; - surface->dst_rect.x = state->crtc_x; - surface->dst_rect.y = state->crtc_y; + plane_state->dst_rect.x = state->crtc_x; + plane_state->dst_rect.y = state->crtc_y; if (state->crtc_w == 0) return false; - surface->dst_rect.width = state->crtc_w; + plane_state->dst_rect.width = state->crtc_w; if (state->crtc_h == 0) return false; - surface->dst_rect.height = state->crtc_h; + plane_state->dst_rect.height = state->crtc_h; - surface->clip_rect = surface->dst_rect; + plane_state->clip_rect = plane_state->dst_rect; switch (state->rotation & DRM_MODE_ROTATE_MASK) { case DRM_MODE_ROTATE_0: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; case DRM_MODE_ROTATE_90: - surface->rotation = ROTATION_ANGLE_90; + plane_state->rotation = ROTATION_ANGLE_90; break; case DRM_MODE_ROTATE_180: - surface->rotation = ROTATION_ANGLE_180; + plane_state->rotation = ROTATION_ANGLE_180; break; case DRM_MODE_ROTATE_270: - surface->rotation = ROTATION_ANGLE_270; + plane_state->rotation = ROTATION_ANGLE_270; break; default: - surface->rotation = ROTATION_ANGLE_0; + plane_state->rotation = ROTATION_ANGLE_0; break; } @@ -1896,7 +1896,7 @@ static int get_fb_info( static int fill_plane_attributes_from_fb( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) { uint64_t tiling_flags; @@ -1916,28 +1916,28 @@ static int fill_plane_attributes_from_fb( switch (fb->format->format) { case DRM_FORMAT_C8: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; break; case DRM_FORMAT_RGB565: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565; break; case DRM_FORMAT_XRGB8888: case DRM_FORMAT_ARGB8888: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888; break; case DRM_FORMAT_XRGB2101010: case DRM_FORMAT_ARGB2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010; break; case DRM_FORMAT_XBGR2101010: case DRM_FORMAT_ABGR2101010: - surface->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; break; case DRM_FORMAT_NV21: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; break; case DRM_FORMAT_NV12: - surface->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; + plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; default: DRM_ERROR("Unsupported screen format %s\n", @@ -1945,45 +1945,45 @@ static int fill_plane_attributes_from_fb( return -EINVAL; } - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.type = PLN_ADDR_TYPE_GRAPHICS; - surface->address.grph.addr.low_part = lower_32_bits(fb_location); - surface->address.grph.addr.high_part = upper_32_bits(fb_location); - surface->plane_size.grph.surface_size.x = 0; - surface->plane_size.grph.surface_size.y = 0; - surface->plane_size.grph.surface_size.width = fb->width; - surface->plane_size.grph.surface_size.height = fb->height; - surface->plane_size.grph.surface_pitch = + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.type = PLN_ADDR_TYPE_GRAPHICS; + plane_state->address.grph.addr.low_part = lower_32_bits(fb_location); + plane_state->address.grph.addr.high_part = upper_32_bits(fb_location); + plane_state->plane_size.grph.surface_size.x = 0; + plane_state->plane_size.grph.surface_size.y = 0; + plane_state->plane_size.grph.surface_size.width = fb->width; + plane_state->plane_size.grph.surface_size.height = fb->height; + plane_state->plane_size.grph.surface_pitch = fb->pitches[0] / fb->format->cpp[0]; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_SRGB; + plane_state->color_space = COLOR_SPACE_SRGB; } else { awidth = ALIGN(fb->width, 64); - surface->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; - surface->address.video_progressive.luma_addr.low_part + plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(fb_location); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(fb_location) + (awidth * fb->height); - surface->plane_size.video.luma_size.x = 0; - surface->plane_size.video.luma_size.y = 0; - surface->plane_size.video.luma_size.width = awidth; - surface->plane_size.video.luma_size.height = fb->height; + plane_state->plane_size.video.luma_size.x = 0; + plane_state->plane_size.video.luma_size.y = 0; + plane_state->plane_size.video.luma_size.width = awidth; + plane_state->plane_size.video.luma_size.height = fb->height; /* TODO: unhardcode */ - surface->plane_size.video.luma_pitch = awidth; + plane_state->plane_size.video.luma_pitch = awidth; - surface->plane_size.video.chroma_size.x = 0; - surface->plane_size.video.chroma_size.y = 0; - surface->plane_size.video.chroma_size.width = awidth; - surface->plane_size.video.chroma_size.height = fb->height; - surface->plane_size.video.chroma_pitch = awidth / 2; + plane_state->plane_size.video.chroma_size.x = 0; + plane_state->plane_size.video.chroma_size.y = 0; + plane_state->plane_size.video.chroma_size.width = awidth; + plane_state->plane_size.video.chroma_size.height = fb->height; + plane_state->plane_size.video.chroma_pitch = awidth / 2; /* TODO: unhardcode */ - surface->color_space = COLOR_SPACE_YCBCR709; + plane_state->color_space = COLOR_SPACE_YCBCR709; } - memset(&surface->tiling_info, 0, sizeof(surface->tiling_info)); + memset(&plane_state->tiling_info, 0, sizeof(plane_state->tiling_info)); /* Fill GFX8 params */ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { @@ -1996,51 +1996,51 @@ static int fill_plane_attributes_from_fb( num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); /* XXX fix me for VI */ - surface->tiling_info.gfx8.num_banks = num_banks; - surface->tiling_info.gfx8.array_mode = + plane_state->tiling_info.gfx8.num_banks = num_banks; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_2D_TILED_THIN1; - surface->tiling_info.gfx8.tile_split = tile_split; - surface->tiling_info.gfx8.bank_width = bankw; - surface->tiling_info.gfx8.bank_height = bankh; - surface->tiling_info.gfx8.tile_aspect = mtaspect; - surface->tiling_info.gfx8.tile_mode = + plane_state->tiling_info.gfx8.tile_split = tile_split; + plane_state->tiling_info.gfx8.bank_width = bankw; + plane_state->tiling_info.gfx8.bank_height = bankh; + plane_state->tiling_info.gfx8.tile_aspect = mtaspect; + plane_state->tiling_info.gfx8.tile_mode = DC_ADDR_SURF_MICRO_TILING_DISPLAY; } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_1D_TILED_THIN1) { - surface->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; + plane_state->tiling_info.gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1; } - surface->tiling_info.gfx8.pipe_config = + plane_state->tiling_info.gfx8.pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); if (adev->asic_type == CHIP_VEGA10 || adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ - surface->tiling_info.gfx9.num_pipes = + plane_state->tiling_info.gfx9.num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; - surface->tiling_info.gfx9.num_banks = + plane_state->tiling_info.gfx9.num_banks = adev->gfx.config.gb_addr_config_fields.num_banks; - surface->tiling_info.gfx9.pipe_interleave = + plane_state->tiling_info.gfx9.pipe_interleave = adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; - surface->tiling_info.gfx9.num_shader_engines = + plane_state->tiling_info.gfx9.num_shader_engines = adev->gfx.config.gb_addr_config_fields.num_se; - surface->tiling_info.gfx9.max_compressed_frags = + plane_state->tiling_info.gfx9.max_compressed_frags = adev->gfx.config.gb_addr_config_fields.max_compress_frags; - surface->tiling_info.gfx9.num_rb_per_se = + plane_state->tiling_info.gfx9.num_rb_per_se = adev->gfx.config.gb_addr_config_fields.num_rb_per_se; - surface->tiling_info.gfx9.swizzle = + plane_state->tiling_info.gfx9.swizzle = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); - surface->tiling_info.gfx9.shaderEnable = 1; + plane_state->tiling_info.gfx9.shaderEnable = 1; } - surface->visible = true; - surface->scaling_quality.h_taps_c = 0; - surface->scaling_quality.v_taps_c = 0; + plane_state->visible = true; + plane_state->scaling_quality.h_taps_c = 0; + plane_state->scaling_quality.v_taps_c = 0; - /* is this needed? is surface zeroed at allocation? */ - surface->scaling_quality.h_taps = 0; - surface->scaling_quality.v_taps = 0; - surface->stereo_format = PLANE_STEREO_FORMAT_NONE; + /* is this needed? is plane_state zeroed at allocation? */ + plane_state->scaling_quality.h_taps = 0; + plane_state->scaling_quality.v_taps = 0; + plane_state->stereo_format = PLANE_STEREO_FORMAT_NONE; return ret; @@ -2050,7 +2050,7 @@ static int fill_plane_attributes_from_fb( static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_surface) + struct dc_plane_state *plane_state) { int i; struct dc_gamma *gamma; @@ -2069,12 +2069,12 @@ static void fill_gamma_from_crtc_state( gamma->blue[i] = lut[i].blue; } - dc_surface->gamma_correction = gamma; + plane_state->gamma_correction = gamma; } static int fill_plane_attributes( struct amdgpu_device *adev, - struct dc_plane_state *surface, + struct dc_plane_state *dc_plane_state, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state, bool addrReq) @@ -2085,12 +2085,12 @@ static int fill_plane_attributes( struct dc_transfer_func *input_tf; int ret = 0; - if (!fill_rects_from_plane_state(plane_state, surface)) + if (!fill_rects_from_plane_state(plane_state, dc_plane_state)) return -EINVAL; ret = fill_plane_attributes_from_fb( crtc->dev->dev_private, - surface, + dc_plane_state, amdgpu_fb, addrReq); @@ -2105,11 +2105,11 @@ static int fill_plane_attributes( input_tf->type = TF_TYPE_PREDEFINED; input_tf->tf = TRANSFER_FUNCTION_SRGB; - surface->in_transfer_func = input_tf; + dc_plane_state->in_transfer_func = input_tf; /* In case of gamma set, update gamma value */ if (crtc_state->gamma_lut) - fill_gamma_from_crtc_state(crtc_state, surface); + fill_gamma_from_crtc_state(crtc_state, dc_plane_state); return ret; } @@ -2991,9 +2991,9 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base); - if (old_dm_plane_state->surface) { - dm_plane_state->surface = old_dm_plane_state->surface; - dc_surface_retain(dm_plane_state->surface); + if (old_dm_plane_state->dc_state) { + dm_plane_state->dc_state = old_dm_plane_state->dc_state; + dc_plane_state_retain(dm_plane_state->dc_state); } return &dm_plane_state->base; @@ -3004,8 +3004,8 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); __drm_atomic_helper_plane_destroy_state(state); kfree(dm_plane_state); @@ -3059,18 +3059,18 @@ static int dm_plane_helper_prepare_fb( amdgpu_bo_ref(rbo); - if (dm_plane_state_new->surface && - dm_plane_state_old->surface != dm_plane_state_new->surface) { - struct dc_plane_state *surface = dm_plane_state_new->surface; + if (dm_plane_state_new->dc_state && + dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) { + struct dc_plane_state *plane_state = dm_plane_state_new->dc_state; - if (surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { - surface->address.grph.addr.low_part = lower_32_bits(afb->address); - surface->address.grph.addr.high_part = upper_32_bits(afb->address); + if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) { + plane_state->address.grph.addr.low_part = lower_32_bits(afb->address); + plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); } else { awidth = ALIGN(new_state->fb->width, 64); - surface->address.video_progressive.luma_addr.low_part + plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address); - surface->address.video_progressive.chroma_addr.low_part + plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(afb->address) + (awidth * new_state->fb->height); } @@ -3159,10 +3159,10 @@ int dm_plane_atomic_check(struct drm_plane *plane, struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); - if (!dm_plane_state->surface) + if (!dm_plane_state->dc_state) return true; - if (dc_validate_plane(dc, dm_plane_state->surface)) + if (dc_validate_plane(dc, dm_plane_state->dc_state)) return 0; return -EINVAL; @@ -3848,6 +3848,7 @@ static void amdgpu_dm_do_flip( struct amdgpu_device *adev = crtc->dev->dev_private; bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; struct dc_flip_addrs addr = { {0} }; + /* TODO eliminate or rename surface_update */ struct dc_surface_update surface_updates[1] = { {0} }; struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); @@ -3903,11 +3904,11 @@ static void amdgpu_dm_do_flip( if (acrtc->base.state->event) prepare_flip_isr(acrtc); - surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->surfaces[0]; + surface_updates->surface = dc_stream_get_status(acrtc_state->stream)->plane_states[0]; surface_updates->flip_addr = &addr; - dc_update_surfaces_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); + dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, @@ -3918,7 +3919,7 @@ static void amdgpu_dm_do_flip( spin_unlock_irqrestore(&crtc->dev->event_lock, flags); } -static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, +static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct drm_device *dev, struct amdgpu_display_manager *dm, struct drm_crtc *pcrtc, @@ -3928,7 +3929,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, struct drm_plane *plane; struct drm_plane_state *old_plane_state; struct dc_stream_state *dc_stream_attach; - struct dc_plane_state *dc_surfaces_constructed[MAX_SURFACES]; + struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); int planes_count = 0; @@ -3956,8 +3957,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_lock_irqsave(&crtc->dev->event_lock, flags); if (acrtc_attach->pflip_status != AMDGPU_FLIP_NONE) { - DRM_ERROR("add_surface: acrtc %d, already busy\n", - acrtc_attach->crtc_id); + DRM_ERROR("%s: acrtc %d, already busy\n", + __func__, + acrtc_attach->crtc_id); spin_unlock_irqrestore(&crtc->dev->event_lock, flags); /* In commit tail framework this cannot happen */ WARN_ON(1); @@ -3965,9 +3967,9 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&crtc->dev->event_lock, flags); if (!pflip_needed) { - WARN_ON(!dm_plane_state->surface); + WARN_ON(!dm_plane_state->dc_state); - dc_surfaces_constructed[planes_count] = dm_plane_state->surface; + plane_states_constructed[planes_count] = dm_plane_state->dc_state; dc_stream_attach = acrtc_state->stream; planes_count++; @@ -4010,11 +4012,11 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state, spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); } - if (false == dc_commit_surfaces_to_stream(dm->dc, - dc_surfaces_constructed, - planes_count, - dc_stream_attach)) - dm_error("%s: Failed to attach surface!\n", __func__); + if (false == dc_commit_planes_to_stream(dm->dc, + plane_states_constructed, + planes_count, + dc_stream_attach)) + dm_error("%s: Failed to attach plane!\n", __func__); } else { /*TODO BUG Here should go disable planes on CRTC. */ } @@ -4226,16 +4228,16 @@ void amdgpu_dm_atomic_commit_tail( status = dc_stream_get_status(new_acrtc_state->stream); WARN_ON(!status); - WARN_ON(!status->surface_count); + WARN_ON(!status->plane_count); if (!new_acrtc_state->stream) continue; /*TODO How it works with MPO ?*/ - if (!dc_commit_surfaces_to_stream( + if (!dc_commit_planes_to_stream( dm->dc, - status->surfaces, - status->surface_count, + status->plane_states, + status->plane_count, new_acrtc_state->stream)) dm_error("%s: Failed to update stream scaling!\n", __func__); } @@ -4260,7 +4262,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(pcrtc->state); if (new_acrtc_state->stream) - amdgpu_dm_commit_surfaces(state, dev, dm, pcrtc, &wait_for_vblank); + amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); } @@ -4375,27 +4377,27 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector dm_force_atomic_commit(&aconnector->base); } -static uint32_t add_val_sets_surface( +static uint32_t add_val_sets_plane( struct dc_validation_set *val_sets, uint32_t set_count, const struct dc_stream_state *stream, - struct dc_plane_state *surface) + struct dc_plane_state *plane_state) { uint32_t i = 0, j = 0; while (i < set_count) { if (val_sets[i].stream == stream) { - while (val_sets[i].surfaces[j]) + while (val_sets[i].plane_states[j]) j++; break; } ++i; } - val_sets[i].surfaces[j] = surface; - val_sets[i].surface_count++; + val_sets[i].plane_states[j] = plane_state; + val_sets[i].plane_count++; - return val_sets[i].surface_count; + return val_sets[i].plane_count; } static uint32_t update_in_val_sets_stream( @@ -4516,7 +4518,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, /* * This bool will be set for true for any modeset/reset - * or surface update which implies non fast surface update. + * or plane update which implies non fast surface update. */ bool lock_and_validation_needed = false; @@ -4701,13 +4703,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, pflip_needed = !state->allow_modeset; if (!pflip_needed) { - struct dc_plane_state *surface; + struct dc_plane_state *dc_plane_state; - surface = dc_create_surface(dc); + dc_plane_state = dc_create_plane_state(dc); ret = fill_plane_attributes( plane_crtc->dev->dev_private, - surface, + dc_plane_state, plane_state, crtc_state, false); @@ -4715,15 +4717,15 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; - if (dm_plane_state->surface) - dc_surface_release(dm_plane_state->surface); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->surface = surface; + dm_plane_state->dc_state = dc_plane_state; - add_val_sets_surface(set, + add_val_sets_plane(set, set_count, new_acrtc_state->stream, - surface); + dc_plane_state); lock_and_validation_needed = true; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index cca65a37b213..e0a5632f00a3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -196,7 +196,7 @@ struct dc_stream; struct dm_plane_state { struct drm_plane_state base; - struct dc_plane_state *surface; + struct dc_plane_state *dc_state; }; struct dm_crtc_state { diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index 9a850227eeeb..28dbd18b2d86 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2594,15 +2594,15 @@ static void populate_initial_data( if (!pipe[i].stream || !pipe[i].bottom_pipe) continue; - ASSERT(pipe[i].surface); + ASSERT(pipe[i].plane_state); if (num_displays == 0) { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d0_underlay_mode = bw_def_underlay_only; else data->d0_underlay_mode = bw_def_blend; } else { - if (!pipe[i].surface->visible) + if (!pipe[i].plane_state->visible) data->d1_underlay_mode = bw_def_underlay_only; else data->d1_underlay_mode = bw_def_blend; @@ -2620,7 +2620,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2636,7 +2636,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: case SURFACE_PIXEL_FORMAT_GRPH_RGB565: @@ -2670,14 +2670,14 @@ static void populate_initial_data( data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.height); data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.viewport.width); data->pitch_in_pixels[num_displays * 2 + j] = bw_int_to_fixed( - pipe[i].bottom_pipe->surface->plane_size.grph.surface_pitch); + pipe[i].bottom_pipe->plane_state->plane_size.grph.surface_pitch); data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.h_taps); data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->scl_data.taps.v_taps); data->h_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.horz.value); data->v_scale_ratio[num_displays * 2 + j] = fixed31_32_to_bw_fixed( pipe[i].bottom_pipe->scl_data.ratios.vert.value); - switch (pipe[i].bottom_pipe->surface->rotation) { + switch (pipe[i].bottom_pipe->plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays * 2 + j] = bw_int_to_fixed(0); break; @@ -2710,7 +2710,7 @@ static void populate_initial_data( data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total); data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total); data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000); - if (pipe[i].surface) { + if (pipe[i].plane_state) { data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width); data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4]; data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height); @@ -2718,7 +2718,7 @@ static void populate_initial_data( data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.taps.v_taps); data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.horz.value); data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].scl_data.ratios.vert.value); - switch (pipe[i].surface->rotation) { + switch (pipe[i].plane_state->rotation) { case ROTATION_ANGLE_0: data->rotation_angle[num_displays + 4] = bw_int_to_fixed(0); break; @@ -2734,7 +2734,7 @@ static void populate_initial_data( default: break; } - switch (pipe[i].surface->format) { + switch (pipe[i].plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 7f7cb8ff124d..404b39e7b44b 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -233,16 +233,16 @@ static void pipe_ctx_to_e2e_pipe_params ( struct _vcs_dpi_display_pipe_params_st *input) { input->src.is_hsplit = false; - if (pipe->top_pipe != NULL && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->surface == pipe->surface) + else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) input->src.is_hsplit = true; - input->src.dcc = pipe->surface->dcc.enable; + input->src.dcc = pipe->plane_state->dcc.enable; input->src.dcc_rate = 1; - input->src.meta_pitch = pipe->surface->dcc.grph.meta_pitch; + input->src.meta_pitch = pipe->plane_state->dcc.grph.meta_pitch; input->src.source_scan = dm_horz; - input->src.sw_mode = pipe->surface->tiling_info.gfx9.swizzle; + input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; input->src.viewport_width = pipe->scl_data.viewport.width; input->src.viewport_height = pipe->scl_data.viewport.height; @@ -251,7 +251,7 @@ static void pipe_ctx_to_e2e_pipe_params ( input->src.cur0_src_width = 128; /* TODO: Cursor calcs, not curently stored */ input->src.cur0_bpp = 32; - switch (pipe->surface->tiling_info.gfx9.swizzle) { + switch (pipe->plane_state->tiling_info.gfx9.swizzle) { /* for 4/8/16 high tiles */ case DC_SW_LINEAR: input->src.is_display_sw = 1; @@ -299,7 +299,7 @@ static void pipe_ctx_to_e2e_pipe_params ( break; } - switch (pipe->surface->rotation) { + switch (pipe->plane_state->rotation) { case ROTATION_ANGLE_0: case ROTATION_ANGLE_180: input->src.source_scan = dm_horz; @@ -314,7 +314,7 @@ static void pipe_ctx_to_e2e_pipe_params ( } /* TODO: Fix pixel format mappings */ - switch (pipe->surface->format) { + switch (pipe->plane_state->format) { case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: input->src.source_format = dm_420_8; @@ -455,7 +455,7 @@ static void dcn_bw_calc_rq_dlg_ttu( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); } static void dcn_dml_wm_override( @@ -478,7 +478,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; input[in_idx].clks_cfg.dcfclk_mhz = v->dcfclk; @@ -516,7 +516,7 @@ static void dcn_dml_wm_override( for (i = 0, in_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; - if (!pipe->stream || !pipe->surface) + if (!pipe->stream || !pipe->plane_state) continue; dml_rq_dlg_get_dlg_reg(dml, @@ -527,7 +527,7 @@ static void dcn_dml_wm_override( true, true, v->pte_enable == dcn_bw_yes, - pipe->surface->flip_immediate); + pipe->plane_state->flip_immediate); in_idx++; } dm_free(input); @@ -541,7 +541,7 @@ static void split_stream_across_pipes( { int pipe_idx = secondary_pipe->pipe_idx; - if (!primary_pipe->surface) + if (!primary_pipe->plane_state) return; *secondary_pipe = *primary_pipe; @@ -843,7 +843,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; v->underscan_output[input_idx] = false; /* taken care of in recout already*/ @@ -869,7 +869,7 @@ bool dcn_validate_bandwidth( } } - if (!pipe->surface){ + if (!pipe->plane_state) { v->dcc_enable[input_idx] = dcn_bw_yes; v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32; v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s; @@ -889,8 +889,8 @@ bool dcn_validate_bandwidth( v->viewport_width[input_idx] = pipe->scl_data.viewport.width; v->scaler_rec_out_width[input_idx] = pipe->scl_data.recout.width; v->scaler_recout_height[input_idx] = pipe->scl_data.recout.height; - if (pipe->bottom_pipe && pipe->bottom_pipe->surface == pipe->surface) { - if (pipe->surface->rotation % 2 == 0) { + if (pipe->bottom_pipe && pipe->bottom_pipe->plane_state == pipe->plane_state) { + if (pipe->plane_state->rotation % 2 == 0) { int viewport_end = pipe->scl_data.viewport.width + pipe->scl_data.viewport.x; int viewport_b_end = pipe->bottom_pipe->scl_data.viewport.width @@ -919,17 +919,17 @@ bool dcn_validate_bandwidth( + pipe->bottom_pipe->scl_data.recout.width; } - v->dcc_enable[input_idx] = pipe->surface->dcc.enable ? dcn_bw_yes : dcn_bw_no; + v->dcc_enable[input_idx] = pipe->plane_state->dcc.enable ? dcn_bw_yes : dcn_bw_no; v->source_pixel_format[input_idx] = tl_pixel_format_to_bw_defs( - pipe->surface->format); + pipe->plane_state->format); v->source_surface_mode[input_idx] = tl_sw_mode_to_bw_defs( - pipe->surface->tiling_info.gfx9.swizzle); + pipe->plane_state->tiling_info.gfx9.swizzle); v->lb_bit_per_pixel[input_idx] = tl_lb_bpp_to_int(pipe->scl_data.lb_params.depth); v->override_hta_ps[input_idx] = pipe->scl_data.taps.h_taps; v->override_vta_ps[input_idx] = pipe->scl_data.taps.v_taps; v->override_hta_pschroma[input_idx] = pipe->scl_data.taps.h_taps_c; v->override_vta_pschroma[input_idx] = pipe->scl_data.taps.v_taps_c; - v->source_scan[input_idx] = (pipe->surface->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; + v->source_scan[input_idx] = (pipe->plane_state->rotation % 2) ? dcn_bw_vert : dcn_bw_hor; } if (v->is_line_buffer_bpp_fixed == dcn_bw_yes) v->lb_bit_per_pixel[input_idx] = v->line_buffer_fixed_bpp; @@ -996,7 +996,7 @@ bool dcn_validate_bandwidth( if (!pipe->stream) continue; /* skip all but first of split pipes */ - if (pipe->top_pipe && pipe->top_pipe->surface == pipe->surface) + if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) continue; pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; @@ -1024,7 +1024,7 @@ bool dcn_validate_bandwidth( pipe->pipe_dlg_param.vblank_start = asic_blank_start; pipe->pipe_dlg_param.vblank_end = asic_blank_end; - if (pipe->surface) { + if (pipe->plane_state) { struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe; if (v->dpp_per_plane[input_idx] == 2 || @@ -1036,7 +1036,7 @@ bool dcn_validate_bandwidth( TIMING_3D_FORMAT_TOP_AND_BOTTOM || pipe->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE))) { - if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* update previously split pipe */ hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width[input_idx]; hsplit_pipe->pipe_dlg_param.vupdate_offset = v->v_update_offset[input_idx]; @@ -1057,12 +1057,12 @@ bool dcn_validate_bandwidth( } dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe); - } else if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) { + } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) { /* merge previously split pipe */ pipe->bottom_pipe = hsplit_pipe->bottom_pipe; if (hsplit_pipe->bottom_pipe) hsplit_pipe->bottom_pipe->top_pipe = pipe; - hsplit_pipe->surface = NULL; + hsplit_pipe->plane_state = NULL; hsplit_pipe->stream = NULL; hsplit_pipe->top_pipe = NULL; hsplit_pipe->bottom_pipe = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8b6b7631d776..ffc9c05e2fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -639,21 +639,21 @@ static bool is_validation_required( for (i = 0; i < set_count; i++) { - if (set[i].surface_count != context->stream_status[i].surface_count) + if (set[i].plane_count != context->stream_status[i].plane_count) return true; if (!dc_is_stream_unchanged(set[i].stream, context->streams[i])) return true; - for (j = 0; j < set[i].surface_count; j++) { - struct dc_plane_state temp_surf; - memset(&temp_surf, 0, sizeof(temp_surf)); + for (j = 0; j < set[i].plane_count; j++) { + struct dc_plane_state temp_plane; + memset(&temp_plane, 0, sizeof(temp_plane)); - temp_surf = *context->stream_status[i].surfaces[j]; - temp_surf.clip_rect = set[i].surfaces[j]->clip_rect; - temp_surf.dst_rect.x = set[i].surfaces[j]->dst_rect.x; - temp_surf.dst_rect.y = set[i].surfaces[j]->dst_rect.y; + temp_plane = *context->stream_status[i].plane_states[j]; + temp_plane.clip_rect = set[i].plane_states[j]->clip_rect; + temp_plane.dst_rect.x = set[i].plane_states[j]->dst_rect.x; + temp_plane.dst_rect.y = set[i].plane_states[j]->dst_rect.y; - if (memcmp(&temp_surf, set[i].surfaces[j], sizeof(temp_surf)) != 0) + if (memcmp(&temp_plane, set[i].plane_states[j], sizeof(temp_plane)) != 0) return true; } } @@ -683,8 +683,8 @@ static bool validate_surfaces( int i, j; for (i = 0; i < set_count; i++) - for (j = 0; j < set[i].surface_count; j++) - if (!dc_validate_plane(dc, set[i].surfaces[j])) + for (j = 0; j < set[i].plane_count; j++) + if (!dc_validate_plane(dc, set[i].plane_states[j])) return false; return true; @@ -977,11 +977,11 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->stream_status[i].surface_count; j++) { - const struct dc_plane_state *surface = - context->stream_status[i].surfaces[j]; + for (j = 0; j < context->stream_status[i].plane_count; j++) { + const struct dc_plane_state *plane_state = + context->stream_status[i].plane_states[j]; - core_dc->hwss.apply_ctx_for_surface(core_dc, surface, context); + core_dc->hwss.apply_ctx_for_surface(core_dc, plane_state, context); /* * enable stereo @@ -1073,9 +1073,9 @@ bool dc_commit_streams( set[i].stream = stream; if (status) { - set[i].surface_count = status->surface_count; - for (j = 0; j < status->surface_count; j++) - set[i].surfaces[j] = status->surfaces[j]; + set[i].plane_count = status->plane_count; + for (j = 0; j < status->plane_count; j++) + set[i].plane_states[j] = status->plane_states[j]; } } @@ -1122,7 +1122,7 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) for (i = 0; i < core_dc->res_pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == NULL - || context->res_ctx.pipe_ctx[i].surface == NULL) + || context->res_ctx.pipe_ctx[i].plane_state == NULL) core_dc->hwss.power_down_front_end(core_dc, i); /* 3rd param should be true, temp w/a for RV*/ @@ -1134,10 +1134,10 @@ bool dc_post_update_surfaces_to_stream(struct dc *dc) return true; } -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **new_surfaces, - uint8_t new_surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *dc_stream) { struct dc_surface_update updates[MAX_SURFACES]; @@ -1162,37 +1162,37 @@ bool dc_commit_surfaces_to_stream( stream_update->dst = dc_stream->dst; stream_update->out_transfer_func = dc_stream->out_transfer_func; - for (i = 0; i < new_surface_count; i++) { - updates[i].surface = new_surfaces[i]; + for (i = 0; i < new_plane_count; i++) { + updates[i].surface = plane_states[i]; updates[i].gamma = - (struct dc_gamma *)new_surfaces[i]->gamma_correction; - updates[i].in_transfer_func = new_surfaces[i]->in_transfer_func; - flip_addr[i].address = new_surfaces[i]->address; - flip_addr[i].flip_immediate = new_surfaces[i]->flip_immediate; - plane_info[i].color_space = new_surfaces[i]->color_space; - plane_info[i].format = new_surfaces[i]->format; - plane_info[i].plane_size = new_surfaces[i]->plane_size; - plane_info[i].rotation = new_surfaces[i]->rotation; - plane_info[i].horizontal_mirror = new_surfaces[i]->horizontal_mirror; - plane_info[i].stereo_format = new_surfaces[i]->stereo_format; - plane_info[i].tiling_info = new_surfaces[i]->tiling_info; - plane_info[i].visible = new_surfaces[i]->visible; - plane_info[i].per_pixel_alpha = new_surfaces[i]->per_pixel_alpha; - plane_info[i].dcc = new_surfaces[i]->dcc; - scaling_info[i].scaling_quality = new_surfaces[i]->scaling_quality; - scaling_info[i].src_rect = new_surfaces[i]->src_rect; - scaling_info[i].dst_rect = new_surfaces[i]->dst_rect; - scaling_info[i].clip_rect = new_surfaces[i]->clip_rect; + (struct dc_gamma *)plane_states[i]->gamma_correction; + updates[i].in_transfer_func = plane_states[i]->in_transfer_func; + flip_addr[i].address = plane_states[i]->address; + flip_addr[i].flip_immediate = plane_states[i]->flip_immediate; + plane_info[i].color_space = plane_states[i]->color_space; + plane_info[i].format = plane_states[i]->format; + plane_info[i].plane_size = plane_states[i]->plane_size; + plane_info[i].rotation = plane_states[i]->rotation; + plane_info[i].horizontal_mirror = plane_states[i]->horizontal_mirror; + plane_info[i].stereo_format = plane_states[i]->stereo_format; + plane_info[i].tiling_info = plane_states[i]->tiling_info; + plane_info[i].visible = plane_states[i]->visible; + plane_info[i].per_pixel_alpha = plane_states[i]->per_pixel_alpha; + plane_info[i].dcc = plane_states[i]->dcc; + scaling_info[i].scaling_quality = plane_states[i]->scaling_quality; + scaling_info[i].src_rect = plane_states[i]->src_rect; + scaling_info[i].dst_rect = plane_states[i]->dst_rect; + scaling_info[i].clip_rect = plane_states[i]->clip_rect; updates[i].flip_addr = &flip_addr[i]; updates[i].plane_info = &plane_info[i]; updates[i].scaling_info = &scaling_info[i]; } - dc_update_surfaces_and_stream( + dc_update_planes_and_stream( dc, updates, - new_surface_count, + new_plane_count, dc_stream, stream_update); dc_post_update_surfaces_to_stream(dc); @@ -1220,14 +1220,14 @@ void dc_release_validate_context(struct validate_context *context) static bool is_surface_in_context( const struct validate_context *context, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { int j; for (j = 0; j < MAX_PIPES; j++) { const struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (surface == pipe_ctx->surface) { + if (plane_state == pipe_ctx->plane_state) { return true; } } @@ -1371,7 +1371,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( int i; enum surface_update_type overall_type = UPDATE_TYPE_FAST; - if (stream_status == NULL || stream_status->surface_count != surface_count) + if (stream_status == NULL || stream_status->plane_count != surface_count) return UPDATE_TYPE_FULL; if (stream_update) @@ -1393,7 +1393,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) @@ -1470,10 +1470,10 @@ void dc_update_surfaces_and_stream(struct dc *dc, update_surface_trace(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { - struct dc_plane_state *new_surfaces[MAX_SURFACES] = {0}; + struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; for (i = 0; i < surface_count; i++) - new_surfaces[i] = srf_updates[i].surface; + new_planes[i] = srf_updates[i].surface; /* initialize scratch memory for building context */ context = dm_alloc(sizeof(*context)); @@ -1487,7 +1487,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* add surface to context */ if (!resource_attach_surfaces_to_context( - new_surfaces, surface_count, stream, + new_planes, surface_count, stream, context, core_dc->res_pool)) { BREAK_TO_DEBUGGER(); goto fail; @@ -1542,7 +1542,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != surface) continue; resource_build_scaling_params(pipe_ctx); @@ -1599,14 +1599,14 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Lock pipes for provided surfaces, or all active if full update*/ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (update_type != UPDATE_TYPE_FULL && pipe_ctx->surface != surface) + if (update_type != UPDATE_TYPE_FULL && pipe_ctx->plane_state != plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( @@ -1622,15 +1622,15 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; struct pipe_ctx *cur_pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[j]; - bool is_new_pipe_surface = cur_pipe_ctx->surface != pipe_ctx->surface; + bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; - if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->surface) + if (update_type != UPDATE_TYPE_FULL || !pipe_ctx->plane_state) continue; if (!pipe_ctx->top_pipe) core_dc->hwss.apply_ctx_for_surface( - core_dc, pipe_ctx->surface, context); + core_dc, pipe_ctx->plane_state, context); /* TODO: this is a hack w/a for switching from mpo to pipe split */ dc_stream_set_cursor_position(pipe_ctx->stream, &position); @@ -1638,7 +1638,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (is_new_pipe_surface) { core_dc->hwss.update_plane_addr(core_dc, pipe_ctx); core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); core_dc->hwss.set_output_transfer_func( pipe_ctx, pipe_ctx->stream); } @@ -1649,16 +1649,16 @@ void dc_update_surfaces_and_stream(struct dc *dc, /* Perform requested Updates */ for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; + struct dc_plane_state *plane_state = srf_updates[i].surface; if (update_type == UPDATE_TYPE_MED) core_dc->hwss.apply_ctx_for_surface( - core_dc, surface, context); + core_dc, plane_state, context); for (j = 0; j < core_dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; if (srf_updates[i].flip_addr) @@ -1669,7 +1669,7 @@ void dc_update_surfaces_and_stream(struct dc *dc, if (srf_updates[i].in_transfer_func) core_dc->hwss.set_input_transfer_func( - pipe_ctx, pipe_ctx->surface); + pipe_ctx, pipe_ctx->plane_state); if (stream_update != NULL && stream_update->out_transfer_func != NULL) { @@ -1690,9 +1690,9 @@ void dc_update_surfaces_and_stream(struct dc *dc, for (j = 0; j < surface_count; j++) { if (update_type != UPDATE_TYPE_FULL && - srf_updates[j].surface != pipe_ctx->surface) + srf_updates[j].surface != pipe_ctx->plane_state) continue; - if (!pipe_ctx->surface || pipe_ctx->top_pipe) + if (!pipe_ctx->plane_state || pipe_ctx->top_pipe) continue; core_dc->hwss.pipe_control_lock( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index e8d4b8c3ac2b..ca4f1db4a58a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -38,7 +38,7 @@ void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count) { int i; @@ -46,111 +46,111 @@ void pre_surface_trace( struct dal_logger *logger = core_dc->ctx->logger; for (i = 0; i < surface_count; i++) { - const struct dc_plane_state *surface = surfaces[i]; + const struct dc_plane_state *plane_state = plane_states[i]; - SURFACE_TRACE("Surface %d:\n", i); + SURFACE_TRACE("Planes %d:\n", i); SURFACE_TRACE( - "surface->visible = %d;\n" - "surface->flip_immediate = %d;\n" - "surface->address.type = %d;\n" - "surface->address.grph.addr.quad_part = 0x%X;\n" - "surface->address.grph.meta_addr.quad_part = 0x%X;\n" - "surface->scaling_quality.h_taps = %d;\n" - "surface->scaling_quality.v_taps = %d;\n" - "surface->scaling_quality.h_taps_c = %d;\n" - "surface->scaling_quality.v_taps_c = %d;\n", - surface->visible, - surface->flip_immediate, - surface->address.type, - surface->address.grph.addr.quad_part, - surface->address.grph.meta_addr.quad_part, - surface->scaling_quality.h_taps, - surface->scaling_quality.v_taps, - surface->scaling_quality.h_taps_c, - surface->scaling_quality.v_taps_c); + "plane_state->visible = %d;\n" + "plane_state->flip_immediate = %d;\n" + "plane_state->address.type = %d;\n" + "plane_state->address.grph.addr.quad_part = 0x%X;\n" + "plane_state->address.grph.meta_addr.quad_part = 0x%X;\n" + "plane_state->scaling_quality.h_taps = %d;\n" + "plane_state->scaling_quality.v_taps = %d;\n" + "plane_state->scaling_quality.h_taps_c = %d;\n" + "plane_state->scaling_quality.v_taps_c = %d;\n", + plane_state->visible, + plane_state->flip_immediate, + plane_state->address.type, + plane_state->address.grph.addr.quad_part, + plane_state->address.grph.meta_addr.quad_part, + plane_state->scaling_quality.h_taps, + plane_state->scaling_quality.v_taps, + plane_state->scaling_quality.h_taps_c, + plane_state->scaling_quality.v_taps_c); SURFACE_TRACE( - "surface->src_rect.x = %d;\n" - "surface->src_rect.y = %d;\n" - "surface->src_rect.width = %d;\n" - "surface->src_rect.height = %d;\n" - "surface->dst_rect.x = %d;\n" - "surface->dst_rect.y = %d;\n" - "surface->dst_rect.width = %d;\n" - "surface->dst_rect.height = %d;\n" - "surface->clip_rect.x = %d;\n" - "surface->clip_rect.y = %d;\n" - "surface->clip_rect.width = %d;\n" - "surface->clip_rect.height = %d;\n", - surface->src_rect.x, - surface->src_rect.y, - surface->src_rect.width, - surface->src_rect.height, - surface->dst_rect.x, - surface->dst_rect.y, - surface->dst_rect.width, - surface->dst_rect.height, - surface->clip_rect.x, - surface->clip_rect.y, - surface->clip_rect.width, - surface->clip_rect.height); + "plane_state->src_rect.x = %d;\n" + "plane_state->src_rect.y = %d;\n" + "plane_state->src_rect.width = %d;\n" + "plane_state->src_rect.height = %d;\n" + "plane_state->dst_rect.x = %d;\n" + "plane_state->dst_rect.y = %d;\n" + "plane_state->dst_rect.width = %d;\n" + "plane_state->dst_rect.height = %d;\n" + "plane_state->clip_rect.x = %d;\n" + "plane_state->clip_rect.y = %d;\n" + "plane_state->clip_rect.width = %d;\n" + "plane_state->clip_rect.height = %d;\n", + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height, + plane_state->clip_rect.x, + plane_state->clip_rect.y, + plane_state->clip_rect.width, + plane_state->clip_rect.height); SURFACE_TRACE( - "surface->plane_size.grph.surface_size.x = %d;\n" - "surface->plane_size.grph.surface_size.y = %d;\n" - "surface->plane_size.grph.surface_size.width = %d;\n" - "surface->plane_size.grph.surface_size.height = %d;\n" - "surface->plane_size.grph.surface_pitch = %d;\n", - surface->plane_size.grph.surface_size.x, - surface->plane_size.grph.surface_size.y, - surface->plane_size.grph.surface_size.width, - surface->plane_size.grph.surface_size.height, - surface->plane_size.grph.surface_pitch); + "plane_state->plane_size.grph.surface_size.x = %d;\n" + "plane_state->plane_size.grph.surface_size.y = %d;\n" + "plane_state->plane_size.grph.surface_size.width = %d;\n" + "plane_state->plane_size.grph.surface_size.height = %d;\n" + "plane_state->plane_size.grph.surface_pitch = %d;\n", + plane_state->plane_size.grph.surface_size.x, + plane_state->plane_size.grph.surface_size.y, + plane_state->plane_size.grph.surface_size.width, + plane_state->plane_size.grph.surface_size.height, + plane_state->plane_size.grph.surface_pitch); SURFACE_TRACE( - "surface->tiling_info.gfx8.num_banks = %d;\n" - "surface->tiling_info.gfx8.bank_width = %d;\n" - "surface->tiling_info.gfx8.bank_width_c = %d;\n" - "surface->tiling_info.gfx8.bank_height = %d;\n" - "surface->tiling_info.gfx8.bank_height_c = %d;\n" - "surface->tiling_info.gfx8.tile_aspect = %d;\n" - "surface->tiling_info.gfx8.tile_aspect_c = %d;\n" - "surface->tiling_info.gfx8.tile_split = %d;\n" - "surface->tiling_info.gfx8.tile_split_c = %d;\n" - "surface->tiling_info.gfx8.tile_mode = %d;\n" - "surface->tiling_info.gfx8.tile_mode_c = %d;\n", - surface->tiling_info.gfx8.num_banks, - surface->tiling_info.gfx8.bank_width, - surface->tiling_info.gfx8.bank_width_c, - surface->tiling_info.gfx8.bank_height, - surface->tiling_info.gfx8.bank_height_c, - surface->tiling_info.gfx8.tile_aspect, - surface->tiling_info.gfx8.tile_aspect_c, - surface->tiling_info.gfx8.tile_split, - surface->tiling_info.gfx8.tile_split_c, - surface->tiling_info.gfx8.tile_mode, - surface->tiling_info.gfx8.tile_mode_c); + "plane_state->tiling_info.gfx8.num_banks = %d;\n" + "plane_state->tiling_info.gfx8.bank_width = %d;\n" + "plane_state->tiling_info.gfx8.bank_width_c = %d;\n" + "plane_state->tiling_info.gfx8.bank_height = %d;\n" + "plane_state->tiling_info.gfx8.bank_height_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect = %d;\n" + "plane_state->tiling_info.gfx8.tile_aspect_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_split = %d;\n" + "plane_state->tiling_info.gfx8.tile_split_c = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode = %d;\n" + "plane_state->tiling_info.gfx8.tile_mode_c = %d;\n", + plane_state->tiling_info.gfx8.num_banks, + plane_state->tiling_info.gfx8.bank_width, + plane_state->tiling_info.gfx8.bank_width_c, + plane_state->tiling_info.gfx8.bank_height, + plane_state->tiling_info.gfx8.bank_height_c, + plane_state->tiling_info.gfx8.tile_aspect, + plane_state->tiling_info.gfx8.tile_aspect_c, + plane_state->tiling_info.gfx8.tile_split, + plane_state->tiling_info.gfx8.tile_split_c, + plane_state->tiling_info.gfx8.tile_mode, + plane_state->tiling_info.gfx8.tile_mode_c); SURFACE_TRACE( - "surface->tiling_info.gfx8.pipe_config = %d;\n" - "surface->tiling_info.gfx8.array_mode = %d;\n" - "surface->color_space = %d;\n" - "surface->dcc.enable = %d;\n" - "surface->format = %d;\n" - "surface->rotation = %d;\n" - "surface->stereo_format = %d;\n", - surface->tiling_info.gfx8.pipe_config, - surface->tiling_info.gfx8.array_mode, - surface->color_space, - surface->dcc.enable, - surface->format, - surface->rotation, - surface->stereo_format); - - SURFACE_TRACE("surface->tiling_info.gfx9.swizzle = %d;\n", - surface->tiling_info.gfx9.swizzle); + "plane_state->tiling_info.gfx8.pipe_config = %d;\n" + "plane_state->tiling_info.gfx8.array_mode = %d;\n" + "plane_state->color_space = %d;\n" + "plane_state->dcc.enable = %d;\n" + "plane_state->format = %d;\n" + "plane_state->rotation = %d;\n" + "plane_state->stereo_format = %d;\n", + plane_state->tiling_info.gfx8.pipe_config, + plane_state->tiling_info.gfx8.array_mode, + plane_state->color_space, + plane_state->dcc.enable, + plane_state->format, + plane_state->rotation, + plane_state->stereo_format); + + SURFACE_TRACE("plane_state->tiling_info.gfx9.swizzle = %d;\n", + plane_state->tiling_info.gfx9.swizzle); SURFACE_TRACE("\n"); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ce0415f26600..4eef400cb551 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -430,17 +430,17 @@ static void rect_swap_helper(struct rect *rect) static void calculate_viewport(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; struct scaler_data *data = &pipe_ctx->scl_data; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; struct rect clip = { 0 }; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; bool pri_split = pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface; + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE || stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { @@ -448,41 +448,41 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) sec_split = false; } - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); /* The actual clip is an intersection between stream * source and surface clip */ - clip.x = stream->src.x > surface->clip_rect.x ? - stream->src.x : surface->clip_rect.x; + clip.x = stream->src.x > plane_state->clip_rect.x ? + stream->src.x : plane_state->clip_rect.x; clip.width = stream->src.x + stream->src.width < - surface->clip_rect.x + surface->clip_rect.width ? + plane_state->clip_rect.x + plane_state->clip_rect.width ? stream->src.x + stream->src.width - clip.x : - surface->clip_rect.x + surface->clip_rect.width - clip.x ; + plane_state->clip_rect.x + plane_state->clip_rect.width - clip.x ; - clip.y = stream->src.y > surface->clip_rect.y ? - stream->src.y : surface->clip_rect.y; + clip.y = stream->src.y > plane_state->clip_rect.y ? + stream->src.y : plane_state->clip_rect.y; clip.height = stream->src.y + stream->src.height < - surface->clip_rect.y + surface->clip_rect.height ? + plane_state->clip_rect.y + plane_state->clip_rect.height ? stream->src.y + stream->src.height - clip.y : - surface->clip_rect.y + surface->clip_rect.height - clip.y ; + plane_state->clip_rect.y + plane_state->clip_rect.height - clip.y ; /* offset = surf_src.ofs + (clip.ofs - surface->dst_rect.ofs) * scl_ratio * num_pixels = clip.num_pix * scl_ratio */ - data->viewport.x = surf_src.x + (clip.x - surface->dst_rect.x) * - surf_src.width / surface->dst_rect.width; + data->viewport.x = surf_src.x + (clip.x - plane_state->dst_rect.x) * + surf_src.width / plane_state->dst_rect.width; data->viewport.width = clip.width * - surf_src.width / surface->dst_rect.width; + surf_src.width / plane_state->dst_rect.width; - data->viewport.y = surf_src.y + (clip.y - surface->dst_rect.y) * - surf_src.height / surface->dst_rect.height; + data->viewport.y = surf_src.y + (clip.y - plane_state->dst_rect.y) * + surf_src.height / plane_state->dst_rect.height; data->viewport.height = clip.height * - surf_src.height / surface->dst_rect.height; + surf_src.height / plane_state->dst_rect.height; /* Round down, compensate in init */ data->viewport_c.x = data->viewport.x / vpc_div; @@ -498,13 +498,13 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) /* Handle hsplit */ if (pri_split || sec_split) { /* HMirror XOR Secondary_pipe XOR Rotation_180 */ - bool right_view = (sec_split != surface->horizontal_mirror) != - (surface->rotation == ROTATION_ANGLE_180); + bool right_view = (sec_split != plane_state->horizontal_mirror) != + (plane_state->rotation == ROTATION_ANGLE_180); - if (surface->rotation == ROTATION_ANGLE_90 - || surface->rotation == ROTATION_ANGLE_270) + if (plane_state->rotation == ROTATION_ANGLE_90 + || plane_state->rotation == ROTATION_ANGLE_270) /* Secondary_pipe XOR Rotation_270 */ - right_view = (surface->rotation == ROTATION_ANGLE_270) != sec_split; + right_view = (plane_state->rotation == ROTATION_ANGLE_270) != sec_split; if (right_view) { data->viewport.width /= 2; @@ -520,8 +520,8 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) } } - if (surface->rotation == ROTATION_ANGLE_90 || - surface->rotation == ROTATION_ANGLE_270) { + if (plane_state->rotation == ROTATION_ANGLE_90 || + plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -529,14 +529,14 @@ static void calculate_viewport(struct pipe_ctx *pipe_ctx) static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; - struct rect surf_clip = surface->clip_rect; + struct rect surf_src = plane_state->src_rect; + struct rect surf_clip = plane_state->clip_rect; int recout_full_x, recout_full_y; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.recout.x = stream->dst.x; @@ -568,8 +568,8 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip - pipe_ctx->scl_data.recout.y; /* Handle h & vsplit */ - if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->surface == - pipe_ctx->surface) { + if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == + pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) { pipe_ctx->scl_data.recout.height /= 2; pipe_ctx->scl_data.recout.y += pipe_ctx->scl_data.recout.height; @@ -581,7 +581,7 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip pipe_ctx->scl_data.recout.width += pipe_ctx->scl_data.recout.width % 2; } } else if (pipe_ctx->bottom_pipe && - pipe_ctx->bottom_pipe->surface == pipe_ctx->surface) { + pipe_ctx->bottom_pipe->plane_state == pipe_ctx->plane_state) { if (stream->view_format == VIEW_3D_FORMAT_TOP_AND_BOTTOM) pipe_ctx->scl_data.recout.height /= 2; else @@ -592,13 +592,13 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip * * 1/ stream scaling ratio) - (surf surf_src offset * 1/ full scl * ratio) */ - recout_full_x = stream->dst.x + (surface->dst_rect.x - stream->src.x) + recout_full_x = stream->dst.x + (plane_state->dst_rect.x - stream->src.x) * stream->dst.width / stream->src.width - - surf_src.x * surface->dst_rect.width / surf_src.width + surf_src.x * plane_state->dst_rect.width / surf_src.width * stream->dst.width / stream->src.width; - recout_full_y = stream->dst.y + (surface->dst_rect.y - stream->src.y) + recout_full_y = stream->dst.y + (plane_state->dst_rect.y - stream->src.y) * stream->dst.height / stream->src.height - - surf_src.y * surface->dst_rect.height / surf_src.height + surf_src.y * plane_state->dst_rect.height / surf_src.height * stream->dst.height / stream->src.height; recout_skip->width = pipe_ctx->scl_data.recout.x - recout_full_x; @@ -607,24 +607,24 @@ static void calculate_recout(struct pipe_ctx *pipe_ctx, struct view *recout_skip static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; const struct dc_stream_state *stream = pipe_ctx->stream; - struct rect surf_src = surface->src_rect; + struct rect surf_src = plane_state->src_rect; const int in_w = stream->src.width; const int in_h = stream->src.height; const int out_w = stream->dst.width; const int out_h = stream->dst.height; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) rect_swap_helper(&surf_src); pipe_ctx->scl_data.ratios.horz = dal_fixed31_32_from_fraction( surf_src.width, - surface->dst_rect.width); + plane_state->dst_rect.width); pipe_ctx->scl_data.ratios.vert = dal_fixed31_32_from_fraction( surf_src.height, - surface->dst_rect.height); + plane_state->dst_rect.height); if (stream->view_format == VIEW_3D_FORMAT_SIDE_BY_SIDE) pipe_ctx->scl_data.ratios.horz.value *= 2; @@ -649,13 +649,13 @@ static void calculate_scaling_ratios(struct pipe_ctx *pipe_ctx) static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *recout_skip) { struct scaler_data *data = &pipe_ctx->scl_data; - struct rect src = pipe_ctx->surface->src_rect; + struct rect src = pipe_ctx->plane_state->src_rect; int vpc_div = (data->format == PIXEL_FORMAT_420BPP8 || data->format == PIXEL_FORMAT_420BPP10) ? 2 : 1; - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&src); rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); @@ -805,8 +805,8 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r data->inits.v_bot = dal_fixed31_32_add(data->inits.v, data->ratios.vert); data->inits.v_c_bot = dal_fixed31_32_add(data->inits.v_c, data->ratios.vert_c); - if (pipe_ctx->surface->rotation == ROTATION_ANGLE_90 || - pipe_ctx->surface->rotation == ROTATION_ANGLE_270) { + if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || + pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { rect_swap_helper(&data->viewport_c); rect_swap_helper(&data->viewport); } @@ -814,7 +814,7 @@ static void calculate_inits_and_adj_vp(struct pipe_ctx *pipe_ctx, struct view *r bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) { - const struct dc_plane_state *surface = pipe_ctx->surface; + const struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; struct view recout_skip = { 0 }; bool res = false; @@ -824,7 +824,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) * Inits require viewport, taps, ratios and recout of split pipe */ pipe_ctx->scl_data.format = convert_pixel_format_to_dalsurface( - pipe_ctx->surface->format); + pipe_ctx->plane_state->format); calculate_scaling_ratios(pipe_ctx); @@ -846,14 +846,14 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) /* Taps calculations */ res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); if (!res) { /* Try 24 bpp linebuffer */ pipe_ctx->scl_data.lb_params.depth = LB_PIXEL_DEPTH_24BPP; res = pipe_ctx->xfm->funcs->transform_get_optimal_number_of_taps( - pipe_ctx->xfm, &pipe_ctx->scl_data, &surface->scaling_quality); + pipe_ctx->xfm, &pipe_ctx->scl_data, &plane_state->scaling_quality); } if (res) @@ -869,10 +869,10 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->scl_data.viewport.width, pipe_ctx->scl_data.viewport.x, pipe_ctx->scl_data.viewport.y, - surface->dst_rect.height, - surface->dst_rect.width, - surface->dst_rect.x, - surface->dst_rect.y); + plane_state->dst_rect.height, + plane_state->dst_rect.width, + plane_state->dst_rect.x, + plane_state->dst_rect.y); return res; } @@ -885,7 +885,7 @@ enum dc_status resource_build_scaling_params_for_context( int i; for (i = 0; i < MAX_PIPES; i++) { - if (context->res_ctx.pipe_ctx[i].surface != NULL && + if (context->res_ctx.pipe_ctx[i].plane_state != NULL && context->res_ctx.pipe_ctx[i].stream != NULL) if (!resource_build_scaling_params(&context->res_ctx.pipe_ctx[i])) return DC_FAIL_SCALING; @@ -954,13 +954,13 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( if (!head_pipe) ASSERT(0); - if (!head_pipe->surface) + if (!head_pipe->plane_state) return head_pipe; /* Re-use pipe already acquired for this stream if available*/ for (i = pool->pipe_count - 1; i >= 0; i--) { if (res_ctx->pipe_ctx[i].stream == stream && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { return &res_ctx->pipe_ctx[i]; } } @@ -987,7 +987,7 @@ static void release_free_pipes_for_stream( /* never release the topmost pipe*/ if (res_ctx->pipe_ctx[i].stream == stream && res_ctx->pipe_ctx[i].top_pipe && - !res_ctx->pipe_ctx[i].surface) { + !res_ctx->pipe_ctx[i].plane_state) { memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); } } @@ -1005,7 +1005,7 @@ static int acquire_first_split_pipe( struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; if (pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface) { + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state) { pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; if (pipe_ctx->bottom_pipe) pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; @@ -1028,7 +1028,7 @@ static int acquire_first_split_pipe( #endif bool resource_attach_surfaces_to_context( - struct dc_plane_state * const *surfaces, + struct dc_plane_state * const *plane_states, int surface_count, struct dc_stream_state *stream, struct validate_context *context, @@ -1057,25 +1057,25 @@ bool resource_attach_surfaces_to_context( /* retain new surfaces */ for (i = 0; i < surface_count; i++) - dc_surface_retain(surfaces[i]); + dc_plane_state_retain(plane_states[i]); /* detach surfaces from pipes */ for (i = 0; i < pool->pipe_count; i++) if (context->res_ctx.pipe_ctx[i].stream == stream) { - context->res_ctx.pipe_ctx[i].surface = NULL; + context->res_ctx.pipe_ctx[i].plane_state = NULL; context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; } /* release existing surfaces*/ - for (i = 0; i < stream_status->surface_count; i++) - dc_surface_release(stream_status->surfaces[i]); + for (i = 0; i < stream_status->plane_count; i++) + dc_plane_state_release(stream_status->plane_states[i]); - for (i = surface_count; i < stream_status->surface_count; i++) - stream_status->surfaces[i] = NULL; + for (i = surface_count; i < stream_status->plane_count; i++) + stream_status->plane_states[i] = NULL; tail_pipe = NULL; for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = surfaces[i]; + struct dc_plane_state *plane_state = plane_states[i]; struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( context, pool, stream); @@ -1087,11 +1087,11 @@ bool resource_attach_surfaces_to_context( } #endif if (!free_pipe) { - stream_status->surfaces[i] = NULL; + stream_status->plane_states[i] = NULL; return false; } - free_pipe->surface = surface; + free_pipe->plane_state = plane_state; if (tail_pipe) { free_pipe->tg = tail_pipe->tg; @@ -1110,9 +1110,9 @@ bool resource_attach_surfaces_to_context( /* assign new surfaces*/ for (i = 0; i < surface_count; i++) - stream_status->surfaces[i] = surfaces[i]; + stream_status->plane_states[i] = plane_states[i]; - stream_status->surface_count = surface_count; + stream_status->plane_count = surface_count; return true; } @@ -1180,17 +1180,17 @@ bool resource_validate_attach_surfaces( old_context->streams[j], context->streams[i])) { if (!resource_attach_surfaces_to_context( - old_context->stream_status[j].surfaces, - old_context->stream_status[j].surface_count, + old_context->stream_status[j].plane_states, + old_context->stream_status[j].plane_count, context->streams[i], context, pool)) return false; context->stream_status[i] = old_context->stream_status[j]; } - if (set[i].surface_count != 0) + if (set[i].plane_count != 0) if (!resource_attach_surfaces_to_context( - set[i].surfaces, - set[i].surface_count, + set[i].plane_states, + set[i].plane_count, context->streams[i], context, pool)) return false; @@ -1351,13 +1351,13 @@ bool resource_is_stream_unchanged( static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { - struct dc_plane_state *surface = to_pipe_ctx->surface; + struct dc_plane_state *plane_state = to_pipe_ctx->plane_state; struct dc_stream_state *stream = to_pipe_ctx->stream; *to_pipe_ctx = *from_pipe_ctx; to_pipe_ctx->stream = stream; - if (surface != NULL) - to_pipe_ctx->surface = surface; + if (plane_state != NULL) + to_pipe_ctx->plane_state = plane_state; } static struct dc_stream_state *find_pll_sharable_stream( @@ -2055,7 +2055,7 @@ static void set_spd_info_packet( static void set_hdr_static_info_packet( struct encoder_info_packet *info_packet, - struct dc_plane_state *surface, + struct dc_plane_state *plane_state, struct dc_stream_state *stream) { uint16_t i = 0; @@ -2063,10 +2063,10 @@ static void set_hdr_static_info_packet( struct dc_hdr_static_metadata hdr_metadata; uint32_t data; - if (!surface) + if (!plane_state) return; - hdr_metadata = surface->hdr_static_ctx; + hdr_metadata = plane_state->hdr_static_ctx; if (!hdr_metadata.hdr_supported) return; @@ -2204,11 +2204,11 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) int i, j; for (i = 0; i < context->stream_count; i++) { - for (j = 0; j < context->stream_status[i].surface_count; j++) - dc_surface_release( - context->stream_status[i].surfaces[j]); + for (j = 0; j < context->stream_status[i].plane_count; j++) + dc_plane_state_release( + context->stream_status[i].plane_states[j]); - context->stream_status[i].surface_count = 0; + context->stream_status[i].plane_count = 0; dc_stream_release(context->streams[i]); context->streams[i] = NULL; } @@ -2240,9 +2240,9 @@ void dc_resource_validate_ctx_copy_construct( for (i = 0; i < dst_ctx->stream_count; i++) { dc_stream_retain(dst_ctx->streams[i]); - for (j = 0; j < dst_ctx->stream_status[i].surface_count; j++) - dc_surface_retain( - dst_ctx->stream_status[i].surfaces[j]); + for (j = 0; j < dst_ctx->stream_status[i].plane_count; j++) + dc_plane_state_retain( + dst_ctx->stream_status[i].plane_states[j]); } /* context refcount should not be overridden */ @@ -2288,7 +2288,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } else if (dc_is_dp_signal(signal)) { set_vsc_info_packet(&info->vsc, pipe_ctx->stream); @@ -2296,7 +2296,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) set_spd_info_packet(&info->spd, pipe_ctx->stream); set_hdr_static_info_packet(&info->hdrsmd, - pipe_ctx->surface, pipe_ctx->stream); + pipe_ctx->plane_state, pipe_ctx->stream); } patch_gamut_packet_checksum(&info->gamut); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 7a87f38f2324..2b6506822cca 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -185,7 +185,7 @@ bool dc_stream_set_cursor_attributes( if (pipe_ctx->stream != stream || !pipe_ctx->ipp) continue; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) continue; pipe_ctx->ipp->funcs->ipp_cursor_set_attributes( @@ -229,14 +229,14 @@ bool dc_stream_set_cursor_position( }; if (pipe_ctx->stream != stream || - !pipe_ctx->ipp || !pipe_ctx->surface) + !pipe_ctx->ipp || !pipe_ctx->plane_state) continue; - if (pipe_ctx->surface->address.type + if (pipe_ctx->plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) pos_cpy.enable = false; - if (pipe_ctx->top_pipe && pipe_ctx->surface != pipe_ctx->top_pipe->surface) + if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) pos_cpy.enable = false; ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 941b3671375d..3bcca2d1872b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -34,75 +34,75 @@ /******************************************************************************* * Private functions ******************************************************************************/ -static bool construct(struct dc_context *ctx, struct dc_plane_state *surface) +static bool construct(struct dc_context *ctx, struct dc_plane_state *plane_state) { - surface->ctx = ctx; - memset(&surface->hdr_static_ctx, + plane_state->ctx = ctx; + memset(&plane_state->hdr_static_ctx, 0, sizeof(struct dc_hdr_static_metadata)); return true; } -static void destruct(struct dc_plane_state *surface) +static void destruct(struct dc_plane_state *plane_state) { - if (surface->gamma_correction != NULL) { - dc_gamma_release(&surface->gamma_correction); + if (plane_state->gamma_correction != NULL) { + dc_gamma_release(&plane_state->gamma_correction); } - if (surface->in_transfer_func != NULL) { + if (plane_state->in_transfer_func != NULL) { dc_transfer_func_release( - surface->in_transfer_func); - surface->in_transfer_func = NULL; + plane_state->in_transfer_func); + plane_state->in_transfer_func = NULL; } } /******************************************************************************* * Public functions ******************************************************************************/ -void enable_surface_flip_reporting(struct dc_plane_state *surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id) { - surface->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; + plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; /*register_flip_interrupt(surface);*/ } -struct dc_plane_state *dc_create_surface(const struct dc *dc) +struct dc_plane_state *dc_create_plane_state(const struct dc *dc) { struct core_dc *core_dc = DC_TO_CORE(dc); - struct dc_plane_state *surface = dm_alloc(sizeof(*surface)); + struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); - if (NULL == surface) + if (NULL == plane_state) goto alloc_fail; - if (false == construct(core_dc->ctx, surface)) + if (false == construct(core_dc->ctx, plane_state)) goto construct_fail; - ++surface->ref_count; + ++plane_state->ref_count; - return surface; + return plane_state; construct_fail: - dm_free(surface); + dm_free(plane_state); alloc_fail: return NULL; } -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface) +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state) { - const struct dc_surface_status *surface_status; + const struct dc_plane_status *plane_status; struct core_dc *core_dc; int i; - if (!dc_surface || - !dc_surface->ctx || - !dc_surface->ctx->dc) { + if (!plane_state || + !plane_state->ctx || + !plane_state->ctx->dc) { ASSERT(0); return NULL; /* remove this if above assert never hit */ } - surface_status = &dc_surface->status; - core_dc = DC_TO_CORE(dc_surface->ctx->dc); + plane_status = &plane_state->status; + core_dc = DC_TO_CORE(plane_state->ctx->dc); if (core_dc->current_context == NULL) return NULL; @@ -111,29 +111,29 @@ const struct dc_surface_status *dc_surface_get_status( struct pipe_ctx *pipe_ctx = &core_dc->current_context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != dc_surface) + if (pipe_ctx->plane_state != plane_state) continue; core_dc->hwss.update_pending_status(pipe_ctx); } - return surface_status; + return plane_status; } -void dc_surface_retain(struct dc_plane_state *surface) +void dc_plane_state_retain(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - ++surface->ref_count; + ASSERT(plane_state->ref_count > 0); + ++plane_state->ref_count; } -void dc_surface_release(struct dc_plane_state *surface) +void dc_plane_state_release(struct dc_plane_state *plane_state) { - ASSERT(surface->ref_count > 0); - --surface->ref_count; + ASSERT(plane_state->ref_count > 0); + --plane_state->ref_count; - if (surface->ref_count == 0) { - destruct(surface); - dm_free(surface); + if (plane_state->ref_count == 0) { + destruct(plane_state); + dm_free(plane_state); } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ab805965e321..d1a6398043a3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -47,7 +47,7 @@ struct dc_caps { uint32_t max_links; uint32_t max_audios; uint32_t max_slave_planes; - uint32_t max_surfaces; + uint32_t max_planes; uint32_t max_downscale_ratio; uint32_t i2c_speed_in_khz; @@ -303,7 +303,7 @@ struct dc_transfer_func { * the last requested address and the currently active address so the called * can determine if there are any outstanding flips */ -struct dc_surface_status { +struct dc_plane_status { struct dc_plane_address requested_address; struct dc_plane_address current_address; bool is_flip_pending; @@ -338,7 +338,7 @@ struct dc_plane_state { bool horizontal_mirror; /* private to DC core */ - struct dc_surface_status status; + struct dc_plane_status status; struct dc_context *ctx; /* private to dc_surface.c */ @@ -385,12 +385,12 @@ struct dc_surface_update { /* * Create a new surface with default parameters; */ -struct dc_plane_state *dc_create_surface(const struct dc *dc); -const struct dc_surface_status *dc_surface_get_status( - const struct dc_plane_state *dc_surface); +struct dc_plane_state *dc_create_plane_state(const struct dc *dc); +const struct dc_plane_status *dc_plane_get_status( + const struct dc_plane_state *plane_state); -void dc_surface_retain(struct dc_plane_state *dc_surface); -void dc_surface_release(struct dc_plane_state *dc_surface); +void dc_plane_state_retain(struct dc_plane_state *plane_state); +void dc_plane_state_release(struct dc_plane_state *plane_state); void dc_gamma_retain(struct dc_gamma *dc_gamma); void dc_gamma_release(struct dc_gamma **dc_gamma); @@ -422,10 +422,10 @@ struct dc_flip_addrs { * This does not trigger a flip. No surface address is programmed. */ -bool dc_commit_surfaces_to_stream( +bool dc_commit_planes_to_stream( struct dc *dc, - struct dc_plane_state **dc_surfaces, - uint8_t surface_count, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *stream); bool dc_post_update_surfaces_to_stream( @@ -469,8 +469,8 @@ enum surface_update_type { struct dc_stream_status { int primary_otg_inst; - int surface_count; - struct dc_plane_state *surfaces[MAX_SURFACE_NUM]; + int plane_count; + struct dc_plane_state *plane_states[MAX_SURFACE_NUM]; /* * link this stream passes through @@ -546,7 +546,7 @@ bool dc_is_stream_unchanged( * */ -void dc_update_surfaces_and_stream(struct dc *dc, +void dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *surface_updates, int surface_count, struct dc_stream_state *dc_stream, struct dc_stream_update *stream_update); @@ -582,8 +582,8 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, */ struct dc_validation_set { struct dc_stream_state *stream; - struct dc_plane_state *surfaces[MAX_SURFACES]; - uint8_t surface_count; + struct dc_plane_state *plane_states[MAX_SURFACES]; + uint8_t plane_count; }; bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c index af59ab93796a..8140ff31c3bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c @@ -197,9 +197,9 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, } /* Only use LUT for 8 bit formats */ -bool dce_use_lut(const struct dc_plane_state *surface) +bool dce_use_lut(const struct dc_plane_state *plane_state) { - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: return true; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h index d5cb98a92c53..a0531b3aa6a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h @@ -552,5 +552,5 @@ void dce_crtc_switch_to_clk_src(struct dce_hwseq *hws, struct clock_source *clk_src, unsigned int tg_inst); -bool dce_use_lut(const struct dc_plane_state *surface); +bool dce_use_lut(const struct dc_plane_state *plane_state); #endif /*__DCE_HWSEQ_H__*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 98fb7f02a6fe..46f0c71fbac4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -705,13 +705,13 @@ static bool dce100_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -958,7 +958,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index e4310a376116..ea9ce87d348a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -215,11 +215,11 @@ static bool dce110_enable_display_power_gating( } static void build_prescale_params(struct ipp_prescale_params *prescale_params, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; - switch (surface->format) { + switch (plane_state->format) { case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: prescale_params->scale = 0x2020; @@ -240,7 +240,7 @@ static void build_prescale_params(struct ipp_prescale_params *prescale_params, static bool dce110_set_input_transfer_func( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface) + const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -250,14 +250,14 @@ static bool dce110_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - build_prescale_params(&prescale_params, surface); + build_prescale_params(&prescale_params, plane_state); ipp->funcs->ipp_program_prescale(ipp, &prescale_params); - if (surface->gamma_correction && dce_use_lut(surface)) - ipp->funcs->ipp_program_input_lut(ipp, surface->gamma_correction); + if (plane_state->gamma_correction && dce_use_lut(plane_state)) + ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction); if (tf == NULL) { /* Default case if no input transfer function specified */ @@ -1119,7 +1119,7 @@ static enum dc_status apply_single_controller_ctx_to_hw( if ((!pipe_ctx_old || memcmp(&pipe_ctx_old->scl_data, &pipe_ctx->scl_data, sizeof(struct scaler_data)) != 0) && - pipe_ctx->surface) { + pipe_ctx->plane_state) { program_scaler(dc, pipe_ctx); } @@ -1916,11 +1916,11 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx) struct default_adjustment default_adjust = { 0 }; default_adjust.force_hw_default = false; - if (pipe_ctx->surface == NULL) + if (pipe_ctx->plane_state == NULL) default_adjust.in_color_space = COLOR_SPACE_SRGB; else default_adjust.in_color_space = - pipe_ctx->surface->color_space; + pipe_ctx->plane_state->color_space; if (pipe_ctx->stream == NULL) default_adjust.out_color_space = COLOR_SPACE_SRGB; else @@ -1971,16 +1971,16 @@ static void program_surface_visibility(const struct core_dc *dc, /* For now we are supporting only two pipes */ ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); - if (pipe_ctx->bottom_pipe->surface->visible) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->bottom_pipe->plane_state->visible) { + if (pipe_ctx->plane_state->visible) blender_mode = BLND_MODE_BLENDING; else blender_mode = BLND_MODE_OTHER_PIPE; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; - } else if (!pipe_ctx->surface->visible) + } else if (!pipe_ctx->plane_state->visible) blank_target = true; dce_set_blender_mode(dc->hwseq, pipe_ctx->pipe_idx, blender_mode); @@ -2038,7 +2038,7 @@ static void set_plane_config( struct resource_context *res_ctx) { struct mem_input *mi = pipe_ctx->mi; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2103,57 +2103,57 @@ static void set_plane_config( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); } static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); + &plane_state->address, + plane_state->flip_immediate); - surface->status.requested_address = surface->address; + plane_state->status.requested_address = plane_state->address; } void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); - if (surface->status.is_flip_pending && !surface->visible) + if (plane_state->status.is_flip_pending && !plane_state->visible) pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && pipe_ctx->tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye =\ + plane_state->status.is_right_eye =\ !pipe_ctx->tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } @@ -2490,7 +2490,7 @@ static void dce110_program_front_end_for_pipe( { struct mem_input *mi = pipe_ctx->mi; struct pipe_ctx *old_pipe = NULL; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct xfm_grph_csc_adjustment adjust; struct out_csc_color_matrix tbl_entry; unsigned int i; @@ -2558,21 +2558,21 @@ static void dce110_program_front_end_for_pipe( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, - &surface->plane_size, - surface->rotation, + plane_state->format, + &plane_state->tiling_info, + &plane_state->plane_size, + plane_state->rotation, NULL, false); if (mi->funcs->set_blank) - mi->funcs->set_blank(mi, pipe_ctx->surface->visible); + mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe:%d 0x%x: addr hi:0x%x, " @@ -2581,21 +2581,21 @@ static void dce110_program_front_end_for_pipe( " %d; dst: %d, %d, %d, %d;" "clip: %d, %d, %d, %d\n", pipe_ctx->pipe_idx, - pipe_ctx->surface, - pipe_ctx->surface->address.grph.addr.high_part, - pipe_ctx->surface->address.grph.addr.low_part, - pipe_ctx->surface->src_rect.x, - pipe_ctx->surface->src_rect.y, - pipe_ctx->surface->src_rect.width, - pipe_ctx->surface->src_rect.height, - pipe_ctx->surface->dst_rect.x, - pipe_ctx->surface->dst_rect.y, - pipe_ctx->surface->dst_rect.width, - pipe_ctx->surface->dst_rect.height, - pipe_ctx->surface->clip_rect.x, - pipe_ctx->surface->clip_rect.y, - pipe_ctx->surface->clip_rect.width, - pipe_ctx->surface->clip_rect.height); + pipe_ctx->plane_state, + pipe_ctx->plane_state->address.grph.addr.high_part, + pipe_ctx->plane_state->address.grph.addr.low_part, + pipe_ctx->plane_state->src_rect.x, + pipe_ctx->plane_state->src_rect.y, + pipe_ctx->plane_state->src_rect.width, + pipe_ctx->plane_state->src_rect.height, + pipe_ctx->plane_state->dst_rect.x, + pipe_ctx->plane_state->dst_rect.y, + pipe_ctx->plane_state->dst_rect.width, + pipe_ctx->plane_state->dst_rect.height, + pipe_ctx->plane_state->clip_rect.x, + pipe_ctx->plane_state->clip_rect.y, + pipe_ctx->plane_state->clip_rect.width, + pipe_ctx->plane_state->clip_rect.height); dm_logger_write(dc->ctx->logger, LOG_SURFACE, "Pipe %d: width, height, x, y\n" @@ -2614,19 +2614,18 @@ static void dce110_program_front_end_for_pipe( static void dce110_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i; - /* TODO remove when removing the surface reset workaroud*/ - if (!surface) + if (!plane_state) return; for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; dce110_program_front_end_for_pipe(dc, pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 89b21bd57a35..f580da1b3249 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -764,9 +764,9 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne { if (pipe_ctx->pipe_idx != underlay_idx) return true; - if (!pipe_ctx->surface) + if (!pipe_ctx->plane_state) return false; - if (pipe_ctx->surface->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) + if (pipe_ctx->plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; return true; } @@ -901,22 +901,22 @@ static bool dce110_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 2) + if (set[i].plane_count > 2) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surface_count == 2) { - if (set[i].surfaces[1]->format + if (set[i].plane_count == 2) { + if (set[i].plane_states[1]->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].surfaces[1]->src_rect.width > 1920 - || set[i].surfaces[1]->src_rect.height > 1080) + if (set[i].plane_states[1]->src_rect.width > 1920 + || set[i].plane_states[1]->src_rect.height > 1080) return false; if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) @@ -1351,7 +1351,7 @@ static bool construct( if (!dce110_hw_sequencer_construct(dc)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 68554d6edd94..420434d7283e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -889,13 +889,13 @@ static bool dce112_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -1319,7 +1319,7 @@ static bool construct( &res_create_funcs)) goto res_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; /* Create hardware sequencer */ if (!dce112_hw_sequencer_construct(dc)) diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index 45f5fd63ce14..6448d15c02f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -982,7 +982,7 @@ static bool construct( if (!dce120_hw_sequencer_create(dc)) goto controller_create_fail; - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; bw_calcs_init(&dc->bw_dceip, &dc->bw_vbios, dc->ctx->asic_id); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 734b35eddeed..7473f58584c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -722,13 +722,13 @@ static bool dce80_validate_surface_sets( int i; for (i = 0; i < set_count; i++) { - if (set[i].surface_count == 0) + if (set[i].plane_count == 0) continue; - if (set[i].surface_count > 1) + if (set[i].plane_count > 1) return false; - if (set[i].surfaces[0]->format + if (set[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -959,7 +959,7 @@ static bool construct( } } - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; if (!resource_construct(num_virtual_links, dc, &pool->base, &res_create_funcs)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 866f63d1259d..5922cf8272f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -986,7 +986,7 @@ static void reset_hw_ctx_wrap( struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || - !pipe_ctx->surface || + !pipe_ctx->plane_state || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { plane_atomic_disconnect(dc, i); @@ -1010,13 +1010,13 @@ static void reset_hw_ctx_wrap( /*if (!pipe_ctx_old->stream) continue;*/ - if (pipe_ctx->stream && pipe_ctx->surface + if (pipe_ctx->stream && pipe_ctx->plane_state && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) continue; plane_atomic_disable(dc, i); - if (!pipe_ctx->stream || !pipe_ctx->surface) + if (!pipe_ctx->stream || !pipe_ctx->plane_state) plane_atomic_power_down(dc, i); } @@ -1038,24 +1038,24 @@ static void reset_hw_ctx_wrap( static bool patch_address_for_sbs_tb_stereo( struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; bool sec_split = pipe_ctx->top_pipe && - pipe_ctx->top_pipe->surface == pipe_ctx->surface; - if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO && + pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; + if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO && (pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE || pipe_ctx->stream->timing.timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)) { - *addr = surface->address.grph_stereo.left_addr; - surface->address.grph_stereo.left_addr = - surface->address.grph_stereo.right_addr; + *addr = plane_state->address.grph_stereo.left_addr; + plane_state->address.grph_stereo.left_addr = + plane_state->address.grph_stereo.right_addr; return true; } else { if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE && - surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { - surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO; - surface->address.grph_stereo.right_addr = - surface->address.grph_stereo.left_addr; + plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) { + plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO; + plane_state->address.grph_stereo.right_addr = + plane_state->address.grph_stereo.left_addr; } } return false; @@ -1065,22 +1065,22 @@ static void update_plane_addr(const struct core_dc *dc, struct pipe_ctx *pipe_ct { bool addr_patched = false; PHYSICAL_ADDRESS_LOC addr; - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; - if (surface == NULL) + if (plane_state == NULL) return; addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr); pipe_ctx->mi->funcs->mem_input_program_surface_flip_and_addr( pipe_ctx->mi, - &surface->address, - surface->flip_immediate); - surface->status.requested_address = surface->address; + &plane_state->address, + plane_state->flip_immediate); + plane_state->status.requested_address = plane_state->address; if (addr_patched) - pipe_ctx->surface->address.grph_stereo.left_addr = addr; + pipe_ctx->plane_state->address.grph_stereo.left_addr = addr; } static bool dcn10_set_input_transfer_func( - struct pipe_ctx *pipe_ctx, const struct dc_plane_state *surface) + struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state) { struct input_pixel_processor *ipp = pipe_ctx->ipp; const struct dc_transfer_func *tf = NULL; @@ -1089,12 +1089,12 @@ static bool dcn10_set_input_transfer_func( if (ipp == NULL) return false; - if (surface->in_transfer_func) - tf = surface->in_transfer_func; + if (plane_state->in_transfer_func) + tf = plane_state->in_transfer_func; - if (surface->gamma_correction && dce_use_lut(surface)) + if (plane_state->gamma_correction && dce_use_lut(plane_state)) ipp->funcs->ipp_program_input_lut(ipp, - surface->gamma_correction); + plane_state->gamma_correction); if (tf == NULL) ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); @@ -1689,7 +1689,7 @@ static void dcn10_power_on_fe( struct pipe_ctx *pipe_ctx, struct validate_context *context) { - struct dc_plane_state *dc_surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; power_on_plane(dc->hwseq, @@ -1704,24 +1704,24 @@ static void dcn10_power_on_fe( OPP_PIPE_CLOCK_EN, 1); /*TODO: REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DPPCLK_WDIVIDER, 0x1f);*/ - if (dc_surface) { + if (plane_state) { dm_logger_write(dc->ctx->logger, LOG_DC, "Pipe:%d 0x%x: addr hi:0x%x, " "addr low:0x%x, " "src: %d, %d, %d," " %d; dst: %d, %d, %d, %d;\n", pipe_ctx->pipe_idx, - dc_surface, - dc_surface->address.grph.addr.high_part, - dc_surface->address.grph.addr.low_part, - dc_surface->src_rect.x, - dc_surface->src_rect.y, - dc_surface->src_rect.width, - dc_surface->src_rect.height, - dc_surface->dst_rect.x, - dc_surface->dst_rect.y, - dc_surface->dst_rect.width, - dc_surface->dst_rect.height); + plane_state, + plane_state->address.grph.addr.high_part, + plane_state->address.grph.addr.low_part, + plane_state->src_rect.x, + plane_state->src_rect.y, + plane_state->src_rect.width, + plane_state->src_rect.height, + plane_state->dst_rect.x, + plane_state->dst_rect.y, + plane_state->dst_rect.width, + plane_state->dst_rect.height); dm_logger_write(dc->ctx->logger, LOG_HW_SET_MODE, "Pipe %d: width, height, x, y\n" @@ -1805,7 +1805,7 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx, } static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe)) return true; @@ -1814,7 +1814,7 @@ static bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1823,7 +1823,7 @@ static bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx) static bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx) { - if (pipe_ctx->surface->visible) + if (pipe_ctx->plane_state->visible) return true; if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) return true; @@ -1898,12 +1898,12 @@ static void update_dchubp_dpp( struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->mi; struct input_pixel_processor *ipp = pipe_ctx->ipp; - struct dc_plane_state *surface = pipe_ctx->surface; - union plane_size size = surface->plane_size; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; + union plane_size size = plane_state->plane_size; struct default_adjustment ocsc = {0}; struct mpcc_cfg mpcc_cfg = {0}; struct pipe_ctx *top_pipe; - bool per_pixel_alpha = surface->per_pixel_alpha && pipe_ctx->bottom_pipe; + bool per_pixel_alpha = plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe; /* TODO: proper fix once fpga works */ /* depends on DML calculation, DPP clock value may change dynamically */ @@ -1936,12 +1936,12 @@ static void update_dchubp_dpp( if (dc->public.config.gpu_vm_support) mi->funcs->mem_input_program_pte_vm( pipe_ctx->mi, - surface->format, - &surface->tiling_info, - surface->rotation); + plane_state->format, + &plane_state->tiling_info, + plane_state->rotation); ipp->funcs->ipp_setup(ipp, - surface->format, + plane_state->format, 1, IPP_OUTPUT_FORMAT_12_BIT_FIX); @@ -1982,12 +1982,12 @@ static void update_dchubp_dpp( mi->funcs->mem_input_program_surface_config( mi, - surface->format, - &surface->tiling_info, + plane_state->format, + &plane_state->tiling_info, &size, - surface->rotation, - &surface->dcc, - surface->horizontal_mirror); + plane_state->rotation, + &plane_state->dcc, + plane_state->horizontal_mirror); mi->funcs->set_blank(mi, !is_pipe_tree_visible(pipe_ctx)); } @@ -2025,7 +2025,7 @@ static void program_all_pipe_in_tree( pipe_ctx->tg->funcs->set_blank(pipe_ctx->tg, !is_pipe_tree_visible(pipe_ctx)); } - if (pipe_ctx->surface != NULL) { + if (pipe_ctx->plane_state != NULL) { dcn10_power_on_fe(dc, pipe_ctx, context); update_dchubp_dpp(dc, pipe_ctx, context); } @@ -2068,7 +2068,7 @@ static void dcn10_pplib_apply_display_requirements( static void dcn10_apply_ctx_for_surface( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context) { int i, be_idx; @@ -2076,11 +2076,11 @@ static void dcn10_apply_ctx_for_surface( if (dc->public.debug.sanity_checks) verify_allow_pstate_change_high(dc->hwseq); - if (!surface) + if (!plane_state) return; for (be_idx = 0; be_idx < dc->res_pool->pipe_count; be_idx++) - if (surface == context->res_ctx.pipe_ctx[be_idx].surface) + if (plane_state == context->res_ctx.pipe_ctx[be_idx].plane_state) break; /* reset unused mpcc */ @@ -2089,7 +2089,7 @@ static void dcn10_apply_ctx_for_surface( struct pipe_ctx *old_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; - if (!pipe_ctx->surface && !old_pipe_ctx->surface) + if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; /* @@ -2097,7 +2097,7 @@ static void dcn10_apply_ctx_for_surface( * fairly hacky right now, using opp_id as indicator */ - if (pipe_ctx->surface && !old_pipe_ctx->surface) { + if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) { if (pipe_ctx->mi->opp_id != 0xf && pipe_ctx->tg->inst == be_idx) { dcn10_power_down_fe(dc, pipe_ctx->pipe_idx); /* @@ -2109,7 +2109,7 @@ static void dcn10_apply_ctx_for_surface( } - if ((!pipe_ctx->surface && old_pipe_ctx->surface) + if ((!pipe_ctx->plane_state && old_pipe_ctx->plane_state) || (!pipe_ctx->stream && old_pipe_ctx->stream)) { if (old_pipe_ctx->tg->inst != be_idx) continue; @@ -2135,7 +2135,7 @@ static void dcn10_apply_ctx_for_surface( old_pipe_ctx->top_pipe = NULL; old_pipe_ctx->bottom_pipe = NULL; - old_pipe_ctx->surface = NULL; + old_pipe_ctx->plane_state = NULL; dm_logger_write(dc->ctx->logger, LOG_DC, "Reset mpcc for pipe %d\n", @@ -2146,7 +2146,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; - if (pipe_ctx->surface != surface) + if (pipe_ctx->plane_state != plane_state) continue; /* looking for top pipe to program */ @@ -2468,34 +2468,34 @@ static bool dcn10_dummy_display_power_gating( void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) { - struct dc_plane_state *surface = pipe_ctx->surface; + struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct timing_generator *tg = pipe_ctx->tg; - if (surface->ctx->dc->debug.sanity_checks) { - struct core_dc *dc = DC_TO_CORE(surface->ctx->dc); + if (plane_state->ctx->dc->debug.sanity_checks) { + struct core_dc *dc = DC_TO_CORE(plane_state->ctx->dc); verify_allow_pstate_change_high(dc->hwseq); } - if (surface == NULL) + if (plane_state == NULL) return; - surface->status.is_flip_pending = + plane_state->status.is_flip_pending = pipe_ctx->mi->funcs->mem_input_is_flip_pending( pipe_ctx->mi); /* DCN we read INUSE address in MI, do we still need this wa? */ - if (surface->status.is_flip_pending && - !surface->visible) { + if (plane_state->status.is_flip_pending && + !plane_state->visible) { pipe_ctx->mi->current_address = pipe_ctx->mi->request_address; BREAK_TO_DEBUGGER(); } - surface->status.current_address = pipe_ctx->mi->current_address; + plane_state->status.current_address = pipe_ctx->mi->current_address; if (pipe_ctx->mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && tg->funcs->is_stereo_left_eye) { - surface->status.is_right_eye = + plane_state->status.is_right_eye = !tg->funcs->is_stereo_left_eye(pipe_ctx->tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 5a9fcbc22d04..3fe6df92f91f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1406,7 +1406,7 @@ static bool construct( goto res_create_fail; dcn10_hw_sequencer_construct(dc); - dc->public.caps.max_surfaces = pool->base.pipe_count; + dc->public.caps.max_planes = pool->base.pipe_count; dc->public.cap_funcs = cap_funcs; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d5c0f9e34ce9..3b3330c563e0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -36,7 +36,7 @@ #define MAX_CLOCK_SOURCES 7 -void enable_surface_flip_reporting(struct dc_plane_state *dc_surface, +void enable_surface_flip_reporting(struct dc_plane_state *plane_state, uint32_t controller_id); #include "grph_object_id.h" @@ -153,7 +153,7 @@ struct resource_pool { }; struct pipe_ctx { - struct dc_plane_state *surface; + struct dc_plane_state *plane_state; struct dc_stream_state *stream; struct mem_input *mi; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 7e03f8d45b2b..5d075f93b4b9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -59,7 +59,7 @@ struct hw_sequencer_funcs { void (*apply_ctx_for_surface)( struct core_dc *dc, - const struct dc_plane_state *surface, + const struct dc_plane_state *plane_state, struct validate_context *context); void (*set_plane_config)( @@ -88,7 +88,7 @@ struct hw_sequencer_funcs { bool (*set_input_transfer_func)( struct pipe_ctx *pipe_ctx, - const struct dc_plane_state *surface); + const struct dc_plane_state *plane_state); bool (*set_output_transfer_func)( struct pipe_ctx *pipe_ctx, diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index aef1197cf749..7f30d9937d10 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -119,7 +119,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( struct dc_stream_state *stream); bool resource_attach_surfaces_to_context( - struct dc_plane_state *const *surfaces, + struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, struct validate_context *context, diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 0e978d921fdf..beb790937769 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -77,7 +77,7 @@ void logger_write(struct dal_logger *logger, void pre_surface_trace( const struct dc *dc, - const struct dc_plane_state *const *surfaces, + const struct dc_plane_state *const *plane_states, int surface_count); void update_surface_trace( -- cgit v1.2.3 From 4d128c2f8a0d90f6e693c62423a678af4fc34bf5 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Thu, 27 Jul 2017 15:50:26 -0400 Subject: drm/amd/display: Add surface to dm_plane_state if fb reserve fails Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 08567b3631cf..41731943b4e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4707,6 +4707,11 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dc_plane_state = dc_create_plane_state(dc); + if (dm_plane_state->dc_state) + dc_plane_state_release(dm_plane_state->dc_state); + + dm_plane_state->dc_state = dc_plane_state; + ret = fill_plane_attributes( plane_crtc->dev->dev_private, dc_plane_state, @@ -4716,12 +4721,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - - if (dm_plane_state->dc_state) - dc_plane_state_release(dm_plane_state->dc_state); - - dm_plane_state->dc_state = dc_plane_state; - add_val_sets_plane(set, set_count, new_acrtc_state->stream, -- cgit v1.2.3 From 9a3329b172d26806477d07da7142925c8643ec9b Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 31 Jul 2017 13:15:04 -0400 Subject: drm/amd/display: Fix plane_atomic_check when no dc_state Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 41731943b4e7..0436261243ab 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3160,7 +3160,7 @@ int dm_plane_atomic_check(struct drm_plane *plane, struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); if (!dm_plane_state->dc_state) - return true; + return 0; if (dc_validate_plane(dc, dm_plane_state->dc_state)) return 0; -- cgit v1.2.3 From a7b06724eeb4ecca0c64e8f734e8ef27001670ca Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Mon, 31 Jul 2017 12:09:02 -0400 Subject: drm/amd/display: Fix comment placement for when new_stream is null Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0436261243ab..c89d6089f3c3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4603,6 +4603,13 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, &crtc_state->mode, dm_conn_state); + /* + * we can have no stream on ACTION_SET if a display + * was disconnected during S3, in this case it not and + * error, the OS will be updated after detection, and + * do the right thing on next atomic commit + */ + if (!new_stream) { DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); @@ -4615,14 +4622,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (modeset_required(crtc_state, new_stream, old_acrtc_state->stream)) { - - /* - * we can have no stream on ACTION_SET if a display - * was disconnected during S3, in this case it not and - * error, the OS will be updated after detection, and - * do the right thing on next atomic commit - */ - if (new_acrtc_state->stream) dc_stream_release(new_acrtc_state->stream); -- cgit v1.2.3 From 2a8f6ccb665c6ac53afdcf76b2aaa7fc5e513bfc Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 31 Jul 2017 16:32:18 -0400 Subject: drm/amd/display: Clean up cursor code This will also fix disappearing cursor after resume. With this change we'll set cursor attributes, as well as cursor position on every update. The impact is minor. These are sample logs that show timestamps at beginning and end of atomic_check, commit_tail, handle_cursor_update, and before and after cursor_attribute and cursor_position calls: [ 66.800353] hwhw: begin of check [ 66.800377] hwhw: end of check [ 66.800428] hwhw: begin of commit_tail [ 66.800441] hwhw: begin of cursor [ 66.800449] hwhw: begin of cursor_attr [ 66.800468] hwhw: end of cursor_attr [ 66.800484] hwhw: end of cursor_positionr [ 66.800501] hwhw: end of commit_tail [ 66.807139] hwhw: begin of check [ 66.807160] hwhw: end of check [ 66.807206] hwhw: begin of commit_tail [ 66.807217] hwhw: begin of cursor [ 66.807225] hwhw: begin of cursor_attr [ 66.807357] hwhw: end of cursor_attr [ 66.807374] hwhw: end of cursor_positionr [ 66.807392] hwhw: end of commit_tail Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 283 +++++++--------------- 1 file changed, 92 insertions(+), 191 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c89d6089f3c3..4535942e8a63 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1647,178 +1647,6 @@ static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { .destroy = amdgpu_dm_encoder_destroy, }; -static void dm_set_cursor( - struct amdgpu_crtc *amdgpu_crtc, - uint64_t gpu_addr, - uint32_t width, - uint32_t height) -{ - struct dc_cursor_attributes attributes; - struct dc_cursor_position position; - struct drm_crtc *crtc = &amdgpu_crtc->base; - int x, y; - int xorigin = 0, yorigin = 0; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - amdgpu_crtc->cursor_width = width; - amdgpu_crtc->cursor_height = height; - - attributes.address.high_part = upper_32_bits(gpu_addr); - attributes.address.low_part = lower_32_bits(gpu_addr); - attributes.width = width; - attributes.height = height; - attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; - attributes.rotation_angle = 0; - attributes.attribute_flags.value = 0; - - attributes.pitch = attributes.width; - - x = amdgpu_crtc->cursor_x; - y = amdgpu_crtc->cursor_y; - - /* avivo cursor are offset into the total surface */ - x += crtc->primary->state->src_x >> 16; - y += crtc->primary->state->src_y >> 16; - - if (x < 0) { - xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); - x = 0; - } - if (y < 0) { - yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); - y = 0; - } - - position.enable = true; - position.x = x; - position.y = y; - - position.x_hotspot = xorigin; - position.y_hotspot = yorigin; - - if (!dc_stream_set_cursor_attributes( - acrtc_state->stream, - &attributes)) { - DRM_ERROR("DC failed to set cursor attributes\n"); - } - - if (!dc_stream_set_cursor_position( - acrtc_state->stream, - &position)) { - DRM_ERROR("DC failed to set cursor position\n"); - } -} - -static int dm_crtc_cursor_set( - struct drm_crtc *crtc, - uint64_t address, - uint32_t width, - uint32_t height) -{ - struct dc_cursor_position position; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - int ret; - - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - ret = EINVAL; - - DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d \n", - __func__, - amdgpu_crtc->crtc_id, - width, - height); - - if (!address) { - /* turn off cursor */ - position.enable = false; - position.x = 0; - position.y = 0; - - if (acrtc_state->stream) { - /*set cursor visible false*/ - dc_stream_set_cursor_position( - acrtc_state->stream, - &position); - } - goto release; - - } - - if ((width > amdgpu_crtc->max_cursor_width) || - (height > amdgpu_crtc->max_cursor_height)) { - DRM_ERROR( - "%s: bad cursor width or height %d x %d\n", - __func__, - width, - height); - goto release; - } - - /*program new cursor bo to hardware*/ - dm_set_cursor(amdgpu_crtc, address, width, height); - -release: - return ret; - -} - -static int dm_crtc_cursor_move(struct drm_crtc *crtc, - int x, int y) -{ - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - int xorigin = 0, yorigin = 0; - struct dc_cursor_position position; - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state); - - amdgpu_crtc->cursor_x = x; - amdgpu_crtc->cursor_y = y; - - /* avivo cursor are offset into the total surface */ - x += crtc->primary->state->src_x >> 16; - y += crtc->primary->state->src_y >> 16; - - /* - * TODO: for cursor debugging unguard the following - */ -#if 0 - DRM_DEBUG_KMS( - "%s: x %d y %d c->x %d c->y %d\n", - __func__, - x, - y, - crtc->x, - crtc->y); -#endif - - if (x < 0) { - xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); - x = 0; - } - if (y < 0) { - yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); - y = 0; - } - - position.enable = true; - position.x = x; - position.y = y; - - position.x_hotspot = xorigin; - position.y_hotspot = yorigin; - - if (acrtc_state->stream) { - if (!dc_stream_set_cursor_position( - acrtc_state->stream, - &position)) { - DRM_ERROR("DC failed to set cursor position\n"); - return -EINVAL; - } - } - - return 0; -} - static bool fill_rects_from_plane_state( const struct drm_plane_state *state, struct dc_plane_state *plane_state) @@ -3782,34 +3610,107 @@ static void remove_stream( acrtc->enabled = false; } +int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, + struct dc_cursor_position *position) +{ + struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc); + int x, y; + int xorigin = 0, yorigin = 0; + + if (!crtc || !plane->state->fb) { + position->enable = false; + position->x = 0; + position->y = 0; + return 0; + } + + if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || + (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { + DRM_ERROR("%s: bad cursor width or height %d x %d\n", + __func__, + plane->state->crtc_w, + plane->state->crtc_h); + return -EINVAL; + } + + x = plane->state->crtc_x; + y = plane->state->crtc_y; + /* avivo cursor are offset into the total surface */ + x += crtc->primary->state->src_x >> 16; + y += crtc->primary->state->src_y >> 16; + if (x < 0) { + xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); + x = 0; + } + if (y < 0) { + yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); + y = 0; + } + position->enable = true; + position->x = x; + position->y = y; + position->x_hotspot = xorigin; + position->y_hotspot = yorigin; + + return 0; +} + static void handle_cursor_update( struct drm_plane *plane, struct drm_plane_state *old_plane_state) { + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); + struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; + struct dm_crtc_state *crtc_state = crtc ? to_dm_crtc_state(crtc->state) : NULL; + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + uint64_t address = afb ? afb->address : 0; + struct dc_cursor_position position; + struct dc_cursor_attributes attributes; + int ret; + if (!plane->state->fb && !old_plane_state->fb) return; - /* Check if it's a cursor on/off update or just cursor move*/ - if (plane->state->fb == old_plane_state->fb) - dm_crtc_cursor_move( - plane->state->crtc, - plane->state->crtc_x, - plane->state->crtc_y); - else { - struct amdgpu_framebuffer *afb = - to_amdgpu_framebuffer(plane->state->fb); - dm_crtc_cursor_set( - (!!plane->state->fb) ? - plane->state->crtc : - old_plane_state->crtc, - (!!plane->state->fb) ? - afb->address : - 0, - plane->state->crtc_w, - plane->state->crtc_h); + DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d\n", + __func__, + amdgpu_crtc->crtc_id, + plane->state->crtc_w, + plane->state->crtc_h); + + ret = get_cursor_position(plane, crtc, &position); + if (ret) + return; + + if (!position.enable) { + /* turn off cursor */ + if (crtc_state && crtc_state->stream) + dc_stream_set_cursor_position(crtc_state->stream, + &position); + return; } -} + amdgpu_crtc->cursor_width = plane->state->crtc_w; + amdgpu_crtc->cursor_height = plane->state->crtc_h; + + attributes.address.high_part = upper_32_bits(address); + attributes.address.low_part = lower_32_bits(address); + attributes.width = plane->state->crtc_w; + attributes.height = plane->state->crtc_h; + attributes.color_format = CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA; + attributes.rotation_angle = 0; + attributes.attribute_flags.value = 0; + + attributes.pitch = attributes.width; + + if (!dc_stream_set_cursor_attributes(crtc_state->stream, + &attributes)) + DRM_ERROR("DC failed to set cursor attributes\n"); + + if (crtc_state->stream) + if (!dc_stream_set_cursor_position(crtc_state->stream, + &position)) + DRM_ERROR("DC failed to set cursor position\n"); +} static void prepare_flip_isr(struct amdgpu_crtc *acrtc) { -- cgit v1.2.3 From d66cf5f5013a4268057bcb92d301d010268ea27f Mon Sep 17 00:00:00 2001 From: Anthony Koo Date: Thu, 3 Aug 2017 09:59:23 -0400 Subject: drm/amd/display: implement DXGI Gamma Ramps Support for gamma correction ramp in Floating Point format Signed-off-by: Anthony Koo Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++------- drivers/gpu/drm/amd/display/dc/dc_hw_types.h | 21 ++++++++++++++++----- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 14 ++++++++++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 11 +++++++---- 4 files changed, 40 insertions(+), 20 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4535942e8a63..b0fcfebc04b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1874,15 +1874,14 @@ static int fill_plane_attributes_from_fb( } -#define NUM_OF_RAW_GAMMA_RAMP_RGB_256 256 - static void fill_gamma_from_crtc_state( const struct drm_crtc_state *crtc_state, struct dc_plane_state *plane_state) { int i; struct dc_gamma *gamma; - struct drm_color_lut *lut = (struct drm_color_lut *) crtc_state->gamma_lut->data; + struct drm_color_lut *lut = + (struct drm_color_lut *) crtc_state->gamma_lut->data; gamma = dc_create_gamma(); @@ -1891,10 +1890,11 @@ static void fill_gamma_from_crtc_state( return; } - for (i = 0; i < NUM_OF_RAW_GAMMA_RAMP_RGB_256; i++) { - gamma->red[i] = lut[i].red; - gamma->green[i] = lut[i].green; - gamma->blue[i] = lut[i].blue; + gamma->type = GAMMA_RGB_256_ENTRIES; + for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) { + gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red); + gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green); + gamma->entries.blue[i] = dal_fixed31_32_from_int(lut[i].blue); } plane_state->gamma_correction = gamma; diff --git a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h index 778bd5555c7a..8d1504668ec7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_hw_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_hw_types.h @@ -409,20 +409,31 @@ struct dc_cursor_mi_param { /* IPP related types */ enum { - INPUT_LUT_ENTRIES = 256 + GAMMA_RGB_256_ENTRIES = 256, + GAMMA_RGB_FLOAT_1024_ENTRIES = 1024, + GAMMA_MAX_ENTRIES = 1024 +}; + +enum dc_gamma_type { + GAMMA_RGB_256 = 1, + GAMMA_RGB_FLOAT_1024 = 2 }; struct dc_gamma { - uint16_t red[INPUT_LUT_ENTRIES]; - uint16_t green[INPUT_LUT_ENTRIES]; - uint16_t blue[INPUT_LUT_ENTRIES]; + enum dc_gamma_type type; + unsigned int num_entries; + + struct dc_gamma_entries { + struct fixed31_32 red[GAMMA_MAX_ENTRIES]; + struct fixed31_32 green[GAMMA_MAX_ENTRIES]; + struct fixed31_32 blue[GAMMA_MAX_ENTRIES]; + } entries; /* private to DC core */ struct dc_context *ctx; /* private to dc_surface.c */ int ref_count; - }; /* Used by both ipp amd opp functions*/ diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index 9e8f0a3593a2..e010cf10d605 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -193,10 +193,16 @@ static void dce_ipp_program_input_lut( REG_SET(DC_LUT_RW_INDEX, 0, DC_LUT_RW_INDEX, 0); - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { - REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->red[i]); - REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->green[i]); - REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, gamma->blue[i]); + for (i = 0; i < gamma->num_entries; i++) { + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.red[i])); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.green[i])); + REG_SET(DC_LUT_SEQ_COLOR, 0, DC_LUT_SEQ_COLOR, + dal_fixed31_32_round( + gamma->entries.blue[i])); } /* power off LUT memory */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index ee12f671d8ea..8ee830522148 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -910,13 +910,16 @@ static void ippn10_program_input_lut( CM_IGAM_LUT_FORMAT_B, 3); // Start at index 0 of IGAM LUT REG_UPDATE(CM_IGAM_LUT_RW_INDEX, CM_IGAM_LUT_RW_INDEX, 0); - for (i = 0; i < INPUT_LUT_ENTRIES; i++) { + for (i = 0; i < gamma->num_entries; i++) { REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->red[i]); + dal_fixed31_32_round( + gamma->entries.red[i])); REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->green[i]); + dal_fixed31_32_round( + gamma->entries.green[i])); REG_SET(CM_IGAM_LUT_SEQ_COLOR, 0, CM_IGAM_LUT_SEQ_COLOR, - gamma->blue[i]); + dal_fixed31_32_round( + gamma->entries.blue[i])); } // Power off LUT memory REG_SET(CM_MEM_PWR_CTRL, 0, SHARED_MEM_PWR_DIS, 0); -- cgit v1.2.3 From 0627bbd30f87e06987cb38aee557b06414ae3735 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sat, 5 Aug 2017 10:30:11 -0400 Subject: drm/amd/display: Use public plane destroy helper Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b0fcfebc04b8..3aab3d233a52 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2835,8 +2835,7 @@ void dm_drm_plane_destroy_state(struct drm_plane *plane, if (dm_plane_state->dc_state) dc_plane_state_release(dm_plane_state->dc_state); - __drm_atomic_helper_plane_destroy_state(state); - kfree(dm_plane_state); + drm_atomic_helper_plane_destroy_state(plane, state); } static const struct drm_plane_funcs dm_plane_funcs = { -- cgit v1.2.3 From e1403629d86402ccc25a5c18feb80fc97f671c12 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Sat, 5 Aug 2017 12:43:45 -0400 Subject: drm/amd/display: Couple newline fixes Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dc.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3aab3d233a52..0caf8135084b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1472,7 +1472,6 @@ static const struct amdgpu_display_funcs dm_display_funcs = { }; - #if defined(CONFIG_DEBUG_KERNEL_DC) static ssize_t s3_debug_store( @@ -1594,7 +1593,8 @@ bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) { - /* TODO */ return true; + /* TODO */ + return true; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d1a6398043a3..cac92bf91e4a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -312,7 +312,6 @@ struct dc_plane_status { struct dc_plane_state { struct dc_plane_address address; - struct scaling_taps scaling_quality; struct rect src_rect; struct rect dst_rect; -- cgit v1.2.3 From 7483bed45de728dacc7cfffe641e67abb3513f61 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 8 Aug 2017 12:23:15 -0400 Subject: drm/amd/display: Pass correct number for gamma entries This was broken by "implement DXGI Gamma Ramps" Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0caf8135084b..7a50aeae8ad7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1890,7 +1890,8 @@ static void fill_gamma_from_crtc_state( return; } - gamma->type = GAMMA_RGB_256_ENTRIES; + gamma->type = GAMMA_RGB_256; + gamma->num_entries = GAMMA_RGB_256_ENTRIES; for (i = 0; i < GAMMA_RGB_256_ENTRIES; i++) { gamma->entries.red[i] = dal_fixed31_32_from_int(lut[i].red); gamma->entries.green[i] = dal_fixed31_32_from_int(lut[i].green); -- cgit v1.2.3 From cd4b356f3a8abcd8a96e19b515cf7dc00f41dcbe Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 10 Aug 2017 14:39:47 -0400 Subject: drm/amd/display/dm: add KV, KB, ML (v2) Add DCE8 APUs to display manager. v2: rebase changes Signed-off-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7a50aeae8ad7..d28de04efa42 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1355,6 +1355,9 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_BONAIRE: case CHIP_HAWAII: + case CHIP_KAVERI: + case CHIP_KABINI: + case CHIP_MULLINS: case CHIP_TONGA: case CHIP_FIJI: case CHIP_CARRIZO: @@ -1519,6 +1522,19 @@ static int dm_early_init(void *handle) adev->mode_info.num_dig = 6; adev->mode_info.plane_type = dm_plane_type_default; break; + case CHIP_KAVERI: + adev->mode_info.num_crtc = 4; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 7; + adev->mode_info.plane_type = dm_plane_type_default; + break; + case CHIP_KABINI: + case CHIP_MULLINS: + adev->mode_info.num_crtc = 2; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + adev->mode_info.plane_type = dm_plane_type_default; + break; case CHIP_FIJI: case CHIP_TONGA: adev->mode_info.num_crtc = 6; -- cgit v1.2.3 From 1dc904974eb7deef924650adc5af542878ce2040 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Mon, 31 Jul 2017 11:29:25 -0400 Subject: drm/amd/display: Per stream validate_context build v2. Until now new context would start as empty, then populated with exsisting pipes + new. Now we start with duplication of existing context and then add/delete from the context pipes as needed. This allows to do a per stream resource population, start discarding dc_validation_set and by this brings DC closer to to DRM. v2: Add some fixes and rebase. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 68 ++- drivers/gpu/drm/amd/display/dc/core/dc.c | 108 +---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 468 +++++++++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 32 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 78 +--- .../drm/amd/display/dc/dce110/dce110_resource.c | 86 +--- .../drm/amd/display/dc/dce112/dce112_resource.c | 143 +++---- .../drm/amd/display/dc/dce112/dce112_resource.h | 5 + .../drm/amd/display/dc/dce120/dce120_resource.c | 4 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 79 +--- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 85 ++-- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 19 +- drivers/gpu/drm/amd/display/dc/inc/resource.h | 6 +- 13 files changed, 577 insertions(+), 604 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d28de04efa42..17e9bf7a2ebb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -25,6 +25,7 @@ #include "dm_services_types.h" #include "dc.h" +#include "dc/inc/core_types.h" #include "vid.h" #include "amdgpu.h" @@ -690,13 +691,33 @@ struct drm_atomic_state * dm_atomic_state_alloc(struct drm_device *dev) { struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + struct validate_context *new_ctx; + struct amdgpu_device *adev = dev->dev_private; + struct dc *dc = adev->dm.dc; - if (!state || drm_atomic_state_init(dev, &state->base) < 0) { - kfree(state); + if (!state) return NULL; - } + + if (drm_atomic_state_init(dev, &state->base) < 0) + goto fail; + + /* copy existing configuration */ + new_ctx = dm_alloc(sizeof(*new_ctx)); + + if (!new_ctx) + goto fail; + + atomic_inc(&new_ctx->ref_count); + + dc_resource_validate_ctx_copy_construct_current(dc, new_ctx); + + state->context = new_ctx; return &state->base; + +fail: + kfree(state); + return NULL; } static void @@ -4418,7 +4439,6 @@ static int do_aquire_global_lock( int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { - struct dm_atomic_state *dm_state; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; struct drm_plane *plane; @@ -4432,6 +4452,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, int set_count; struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); /* * This bool will be set for true for any modeset/reset @@ -4446,8 +4467,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, return ret; } - dm_state = to_dm_atomic_state(state); - /* copy existing configuration */ set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -4490,8 +4509,17 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (modereset_required(crtc_state)) { - /* i.e. reset mode */ + /* i.e. reset mode */ if (new_acrtc_state->stream) { + + if (!dc_remove_stream_from_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + set_count = remove_from_val_sets( set, set_count, @@ -4539,8 +4567,19 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (modeset_required(crtc_state, new_stream, old_acrtc_state->stream)) { - if (new_acrtc_state->stream) + if (new_acrtc_state->stream) { + + if (!dc_remove_stream_from_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + + dc_stream_release(new_acrtc_state->stream); + } new_acrtc_state->stream = new_stream; @@ -4551,6 +4590,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_acrtc_state->stream, crtc); + if (!dc_add_stream_to_ctx( + dc, + dm_state->context, + new_acrtc_state->stream)) { + ret = -EINVAL; + goto fail; + } + lock_and_validation_needed = true; } else { /* @@ -4667,9 +4714,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ret = do_aquire_global_lock(dev, state); if (ret) goto fail; - WARN_ON(dm_state->context); - dm_state->context = dc_get_validate_context(dc, set, set_count); - if (!dm_state->context) { + + if (!dc_validate_global_state(dc, set, set_count, dm_state->context)) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 44c7b52e4a00..10126d9a7233 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -669,41 +669,6 @@ void dc_destroy(struct dc **dc) *dc = NULL; } -static bool is_validation_required( - const struct dc *dc, - const struct dc_validation_set set[], - int set_count) -{ - const struct validate_context *context = dc->current_context; - int i, j; - - if (context->stream_count != set_count) - return true; - - for (i = 0; i < set_count; i++) { - - if (set[i].plane_count != context->stream_status[i].plane_count) - return true; - if (!dc_is_stream_unchanged(set[i].stream, context->streams[i])) - return true; - - for (j = 0; j < set[i].plane_count; j++) { - struct dc_plane_state temp_plane; - memset(&temp_plane, 0, sizeof(temp_plane)); - - temp_plane = *context->stream_status[i].plane_states[j]; - temp_plane.clip_rect = set[i].plane_states[j]->clip_rect; - temp_plane.dst_rect.x = set[i].plane_states[j]->dst_rect.x; - temp_plane.dst_rect.y = set[i].plane_states[j]->dst_rect.y; - - if (memcmp(&temp_plane, set[i].plane_states[j], sizeof(temp_plane)) != 0) - return true; - } - } - - return false; -} - static bool validate_streams ( struct dc *dc, const struct dc_validation_set set[], @@ -733,52 +698,12 @@ static bool validate_surfaces( return true; } -struct validate_context *dc_get_validate_context( - struct dc *dc, - const struct dc_validation_set set[], - uint8_t set_count) -{ - struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; - - - context = dm_alloc(sizeof(struct validate_context)); - if (context == NULL) - goto context_alloc_fail; - - atomic_inc(&context->ref_count); - - if (!is_validation_required(core_dc, set, set_count)) { - dc_resource_validate_ctx_copy_construct(core_dc->current_context, context); - return context; - } - - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, set_count, context, core_dc->current_context); - -context_alloc_fail: - if (result != DC_OK) { - dm_logger_write(core_dc->ctx->logger, LOG_WARNING, - "%s:resource validation failed, dc_status:%d\n", - __func__, - result); - - dc_release_validate_context(context); - context = NULL; - } - - return context; - -} - bool dc_validate_resources( struct dc *dc, const struct dc_validation_set set[], uint8_t set_count) { - struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; struct validate_context *context; if (!validate_streams(dc, set, set_count)) @@ -793,21 +718,16 @@ bool dc_validate_resources( atomic_inc(&context->ref_count); - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, set_count, context, NULL); + dc_resource_validate_ctx_copy_construct_current(dc, context); -context_alloc_fail: - if (result != DC_OK) { - dm_logger_write(core_dc->ctx->logger, LOG_WARNING, - "%s:resource validation failed, dc_status:%d\n", - __func__, - result); - } + result = dc_validate_with_context( + dc, set, set_count, context); +context_alloc_fail: dc_release_validate_context(context); context = NULL; - return result == DC_OK; + return result; } bool dc_validate_guaranteed( @@ -1093,7 +1013,7 @@ bool dc_commit_streams( uint8_t stream_count) { struct dc *core_dc = dc; - enum dc_status result = DC_ERROR_UNEXPECTED; + bool result = false; struct validate_context *context; struct dc_validation_set set[MAX_STREAMS] = { {0, {0} } }; int i; @@ -1135,13 +1055,11 @@ bool dc_commit_streams( atomic_inc(&context->ref_count); - result = core_dc->res_pool->funcs->validate_with_context( - core_dc, set, stream_count, context, core_dc->current_context); - if (result != DC_OK){ - dm_logger_write(core_dc->ctx->logger, LOG_ERROR, - "%s: Context validation failed! dc_status:%d\n", - __func__, - result); + dc_resource_validate_ctx_copy_construct_current(dc, context); + + result = dc_validate_with_context( + dc, set, stream_count, context); + if (!result) { BREAK_TO_DEBUGGER(); goto fail; } @@ -1152,7 +1070,7 @@ fail: dc_release_validate_context(context); context_alloc_fail: - return (result == DC_OK); + return result; } bool dc_post_update_surfaces_to_stream(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 2b357318f945..f640986c6fd2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -938,7 +938,7 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( int i; for (i = 0; i < MAX_PIPES; i++) { if (res_ctx->pipe_ctx[i].stream == stream && - res_ctx->pipe_ctx[i].stream_res.stream_enc) { + !res_ctx->pipe_ctx[i].top_pipe) { return &res_ctx->pipe_ctx[i]; break; } @@ -1217,29 +1217,31 @@ bool resource_validate_attach_surfaces( #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 -static void set_stream_engine_in_use( +static void update_stream_engine_usage( struct resource_context *res_ctx, const struct resource_pool *pool, - struct stream_encoder *stream_enc) + struct stream_encoder *stream_enc, + bool acquired) { int i; for (i = 0; i < pool->stream_enc_count; i++) { if (pool->stream_enc[i] == stream_enc) - res_ctx->is_stream_enc_acquired[i] = true; + res_ctx->is_stream_enc_acquired[i] = acquired; } } /* TODO: release audio object */ -static void set_audio_in_use( +static void update_audio_usage( struct resource_context *res_ctx, const struct resource_pool *pool, - struct audio *audio) + struct audio *audio, + bool acquired) { int i; for (i = 0; i < pool->audio_count; i++) { if (pool->audios[i] == audio) - res_ctx->is_audio_acquired[i] = true; + res_ctx->is_audio_acquired[i] = acquired; } } @@ -1361,6 +1363,100 @@ bool resource_is_stream_unchanged( return false; } +bool dc_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream) +{ + struct dc_context *dc_ctx = dc->ctx; + enum dc_status res; + + if (new_ctx->stream_count >= dc->res_pool->pipe_count) { + DC_ERROR("Max streams reached, can add stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + new_ctx->streams[new_ctx->stream_count] = stream; + dc_stream_retain(stream); + new_ctx->stream_count++; + + res = dc->res_pool->funcs->add_stream_to_ctx(dc, new_ctx, stream); + if (res != DC_OK) + DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res); + + return res == DC_OK; +} + +bool dc_remove_stream_from_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream) +{ + int i, j; + struct dc_context *dc_ctx = dc->ctx; + struct pipe_ctx *del_pipe = NULL; + + /*TODO MPO to remove extra pipe or in surface remove ?*/ + + /* Release primary and secondary pipe (if exsist) */ + for (i = 0; i < MAX_PIPES; i++) { + if (new_ctx->res_ctx.pipe_ctx[i].stream == stream) { + del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; + + if (del_pipe->stream_res.stream_enc) + update_stream_engine_usage( + &new_ctx->res_ctx, + dc->res_pool, + del_pipe->stream_res.stream_enc, + false); + + if (del_pipe->stream_res.audio) + update_audio_usage( + &new_ctx->res_ctx, + dc->res_pool, + del_pipe->stream_res.audio, + false); + + memset(del_pipe, 0, sizeof(*del_pipe)); + } + } + + if (!del_pipe) { + DC_ERROR("Pipe not found for stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + for (i = 0; i < new_ctx->stream_count; i++) + if (new_ctx->streams[i] == stream) + break; + + if (new_ctx->streams[i] != stream) { + DC_ERROR("Context doesn't have stream %p !\n", stream); + return DC_ERROR_UNEXPECTED; + } + + dc_stream_release(new_ctx->streams[i]); + new_ctx->stream_count--; + + /*TODO move into dc_remove_surface_from_ctx ?*/ + for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) + dc_plane_state_release(new_ctx->stream_status[i].plane_states[j]); + + /* Trim back arrays */ + for (; i < new_ctx->stream_count; i++) { + new_ctx->streams[i] = new_ctx->streams[i + 1]; + new_ctx->stream_status[i] = new_ctx->stream_status[i + 1]; + } + + new_ctx->streams[new_ctx->stream_count] = NULL; + memset( + &new_ctx->stream_status[new_ctx->stream_count], + 0, + sizeof(new_ctx->stream_status[0])); + + return DC_OK; +} + static void copy_pipe_ctx( const struct pipe_ctx *from_pipe_ctx, struct pipe_ctx *to_pipe_ctx) { @@ -1440,15 +1536,16 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) enum dc_status resource_map_pool_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { const struct resource_pool *pool = dc->res_pool; - int i, j; - - for (i = 0; old_context && i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + int i; + struct dc_context *dc_ctx = dc->ctx; + struct pipe_ctx *pipe_ctx = NULL; + int pipe_idx = -1; - if (!resource_is_stream_unchanged(old_context, stream)) { + /* TODO Check if this is needed */ + /*if (!resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { stream->bit_depth_params = old_context->streams[i]->bit_depth_params; @@ -1456,119 +1553,228 @@ enum dc_status resource_map_pool_resources( continue; } } + */ - /* mark resources used for stream that is already active */ - for (j = 0; j < pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - const struct pipe_ctx *old_pipe_ctx = - &old_context->res_ctx.pipe_ctx[j]; - - if (!are_stream_backends_same(old_pipe_ctx->stream, stream)) - continue; + /* acquire new resources */ + pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); - if (old_pipe_ctx->top_pipe) - continue; +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (pipe_idx < 0) + acquire_first_split_pipe(&context->res_ctx, pool, stream); +#endif + if (pipe_idx < 0) + return DC_NO_CONTROLLER_RESOURCE; + + pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; + + pipe_ctx->stream_res.stream_enc = + find_first_free_match_stream_enc_for_link( + &context->res_ctx, pool, stream); + + if (!pipe_ctx->stream_res.stream_enc) + return DC_NO_STREAM_ENG_RESOURCE; + + update_stream_engine_usage( + &context->res_ctx, pool, + pipe_ctx->stream_res.stream_enc, + true); + + /* TODO: Add check if ASIC support and EDID audio */ + if (!stream->sink->converter_disable_audio && + dc_is_audio_capable_signal(pipe_ctx->stream->signal) && + stream->audio_info.mode_count) { + pipe_ctx->stream_res.audio = find_first_free_audio( + &context->res_ctx, pool); + + /* + * Audio assigned in order first come first get. + * There are asics which has number of audio + * resources less then number of pipes + */ + if (pipe_ctx->stream_res.audio) + update_audio_usage(&context->res_ctx, pool, + pipe_ctx->stream_res.audio, true); + } - pipe_ctx->stream = stream; - copy_pipe_ctx(old_pipe_ctx, pipe_ctx); + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; + return DC_OK; + } - /* Split pipe resource, do not acquire back end */ - if (!pipe_ctx->stream_res.stream_enc) - continue; + DC_ERROR("Stream %p not found in new ctx!\n", stream); + return DC_ERROR_UNEXPECTED; +} - set_stream_engine_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.stream_enc); +/* first stream in the context is used to populate the rest */ +void validate_guaranteed_copy_streams( + struct validate_context *context, + int max_streams) +{ + int i; - /* Switch to dp clock source only if there is - * no non dp stream that shares the same timing - * with the dp stream. - */ - if (dc_is_dp_signal(pipe_ctx->stream->signal) && - !find_pll_sharable_stream(stream, context)) - pipe_ctx->clock_source = pool->dp_clock_source; + for (i = 1; i < max_streams; i++) { + context->streams[i] = context->streams[0]; - resource_reference_clock_source( - &context->res_ctx, pool, - pipe_ctx->clock_source); + copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], + &context->res_ctx.pipe_ctx[i]); + context->res_ctx.pipe_ctx[i].stream = + context->res_ctx.pipe_ctx[0].stream; - set_audio_in_use(&context->res_ctx, pool, - pipe_ctx->stream_res.audio); - } + dc_stream_retain(context->streams[i]); + context->stream_count++; } +} - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - struct pipe_ctx *pipe_ctx = NULL; - int pipe_idx = -1; +void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, + struct validate_context *dst_ctx) +{ + dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); +} - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - /* acquire new resources */ - pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (pipe_idx < 0) - acquire_first_split_pipe(&context->res_ctx, pool, stream); -#endif - if (pipe_idx < 0) - return DC_NO_CONTROLLER_RESOURCE; +bool dc_validate_with_context( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context) +{ + int i, j; + enum dc_status res = DC_ERROR_UNEXPECTED; + bool found = false; + int old_stream_count = context->stream_count; + struct dc_stream_state *del_streams[MAX_PIPES] = { 0 }; + struct dc_stream_state *add_streams[MAX_PIPES] = { 0 }; + int del_streams_count = 0; + int add_streams_count = 0; - pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; - pipe_ctx->stream_res.stream_enc = - find_first_free_match_stream_enc_for_link( - &context->res_ctx, pool, stream); + /* First remove from context all deleted streams */ + for (i = 0; i < old_stream_count; i++) { + struct dc_stream_state *stream = context->streams[i]; + + for (j = 0; j < set_count; j++) { + if (stream == set[j].stream) { + found = true; + break; + } + } - if (!pipe_ctx->stream_res.stream_enc) - return DC_NO_STREAM_ENG_RESOURCE; + if (!found) + del_streams[del_streams_count++] = stream; - set_stream_engine_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.stream_enc); + found = false; + } - /* TODO: Add check if ASIC support and EDID audio */ - if (!stream->sink->converter_disable_audio && - dc_is_audio_capable_signal(pipe_ctx->stream->signal) && - stream->audio_info.mode_count) { - pipe_ctx->stream_res.audio = find_first_free_audio( - &context->res_ctx, pool); + /* Now add new ones */ + for (i = 0; i < set_count; i++) { + struct dc_stream_state *stream = set[i].stream; - /* - * Audio assigned in order first come first get. - * There are asics which has number of audio - * resources less then number of pipes - */ - if (pipe_ctx->stream_res.audio) - set_audio_in_use( - &context->res_ctx, pool, - pipe_ctx->stream_res.audio); + for (j = 0; j < old_stream_count; j++) { + if (stream == context->streams[j]) { + found = true; + break; + } } - context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; + if (!found) + add_streams[add_streams_count++] = stream; + + found = false; } - return DC_OK; + for (i = 0; i < del_streams_count; i++) + if (!dc_remove_stream_from_ctx(dc, context, del_streams[i])) + goto fail; + + for (i = 0; i < add_streams_count; i++) + if (!dc_add_stream_to_ctx(dc, context, add_streams[i])) + goto fail; + + if (!dc_validate_global_state(dc, set, set_count, context)) + goto fail; + + res = DC_OK; + +fail: + if (res != DC_OK) { + dm_logger_write(dc->ctx->logger, LOG_WARNING, + "%s:resource validation failed, dc_status:%d\n", + __func__, + res); +} + return res == DC_OK; } -/* first stream in the context is used to populate the rest */ -void validate_guaranteed_copy_streams( - struct validate_context *context, - int max_streams) +bool dc_validate_global_state( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *new_ctx) { - int i; + enum dc_status result = DC_ERROR_UNEXPECTED; + struct dc_context *dc_ctx = dc->ctx; + struct validate_context *old_context = dc->current_context; + int i, j; - for (i = 1; i < max_streams; i++) { - context->streams[i] = context->streams[0]; + if (dc->res_pool->funcs->validate_global && + dc->res_pool->funcs->validate_global(dc, set, set_count, + old_context, new_ctx) != DC_OK) + return false; - copy_pipe_ctx(&context->res_ctx.pipe_ctx[0], - &context->res_ctx.pipe_ctx[i]); - context->res_ctx.pipe_ctx[i].stream = - context->res_ctx.pipe_ctx[0].stream; + /* TODO without this SWDEV-114774 brakes */ + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i]; - dc_stream_retain(context->streams[i]); - context->stream_count++; + if (pipe_ctx->top_pipe) + memset(pipe_ctx, 0, sizeof(*pipe_ctx)); + } + + for (i = 0; new_ctx && i < new_ctx->stream_count; i++) { + struct dc_stream_state *stream = new_ctx->streams[i]; + + for (j = 0; j < dc->res_pool->pipe_count; j++) { + struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[j]; + + if (pipe_ctx->stream != stream) + continue; + + /* Switch to dp clock source only if there is + * no non dp stream that shares the same timing + * with the dp stream. + */ + if (dc_is_dp_signal(pipe_ctx->stream->signal) && + !find_pll_sharable_stream(stream, new_ctx)) { + + resource_unreference_clock_source( + &new_ctx->res_ctx, + dc->res_pool, + &pipe_ctx->clock_source); + pipe_ctx->clock_source = dc->res_pool->dp_clock_source; + resource_reference_clock_source( + &new_ctx->res_ctx, + dc->res_pool, + pipe_ctx->clock_source); + } + } + } + + /*TODO This should be ok */ + /* Split pipe resource, do not acquire back end */ + + if (!resource_validate_attach_surfaces( + set, set_count, old_context, new_ctx, dc->res_pool)) { + DC_ERROR("Failed to attach surface to stream!\n"); + return DC_FAIL_ATTACH_SURFACES; } + + result = resource_build_scaling_params_for_context(dc, new_ctx); + + if (result == DC_OK) + if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx)) + result = DC_FAIL_BANDWIDTH_VALIDATE; + + return result; } static void patch_gamut_packet_checksum( @@ -2318,54 +2524,40 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { - int i, j; - const struct resource_pool *pool = dc->res_pool; - /* acquire new resources */ - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; + const struct resource_pool *pool = dc->res_pool; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( + &context->res_ctx, stream); - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = pool->dp_clock_source; + else { + pipe_ctx->clock_source = NULL; - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = pool->dp_clock_source; - else { - pipe_ctx->clock_source = NULL; - - if (!dc->config.disable_disp_pll_sharing) - resource_find_used_clk_src_for_sharing( - &context->res_ctx, - pipe_ctx); - - if (pipe_ctx->clock_source == NULL) - pipe_ctx->clock_source = - dc_resource_find_first_free_pll( - &context->res_ctx, - pool); - } + if (!dc->config.disable_disp_pll_sharing) + resource_find_used_clk_src_for_sharing( + &context->res_ctx, + pipe_ctx); - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (pipe_ctx->clock_source == NULL) + pipe_ctx->clock_source = + dc_resource_find_first_free_pll( + &context->res_ctx, + pool); + } - resource_reference_clock_source( - &context->res_ctx, pool, - pipe_ctx->clock_source); + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - /* only one cs per stream regardless of mpo */ - break; - } - } + resource_reference_clock_source( + &context->res_ctx, pool, + pipe_ctx->clock_source); return DC_OK; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 629aa3c323ca..2b4fc6616243 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -618,6 +618,16 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *h_position, uint32_t *v_position); +bool dc_remove_stream_from_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + +bool dc_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + /* * Structure to store surface/stream associations for validation */ @@ -630,16 +640,18 @@ struct dc_validation_set { bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); -/* - * This function takes a set of resources and checks that they are cofunctional. - * - * After this call: - * No hardware is programmed for call. Only validation is done. - */ -struct validate_context *dc_get_validate_context( + +bool dc_validate_with_context( struct dc *dc, const struct dc_validation_set set[], - uint8_t set_count); + int set_count, + struct validate_context *context); + +bool dc_validate_global_state( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *new_ctx); bool dc_validate_resources( struct dc *dc, @@ -662,6 +674,10 @@ void dc_resource_validate_ctx_copy_construct( const struct validate_context *src_ctx, struct validate_context *dst_ctx); +void dc_resource_validate_ctx_copy_construct_current( + const struct dc *dc, + struct validate_context *dst_ctx); + void dc_resource_validate_ctx_destruct(struct validate_context *context); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index b2b03633eb4f..c9dad4e2a7c8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -654,35 +654,20 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; - - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -719,48 +704,17 @@ static bool dce100_validate_surface_sets( return true; } -enum dc_status dce100_validate_with_context( +enum dc_status dce100_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce100_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce100_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - - return result; + return DC_OK; } enum dc_status dce100_validate_guaranteed( @@ -774,13 +728,13 @@ enum dc_status dce100_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -816,10 +770,10 @@ enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state) static const struct resource_funcs dce100_res_pool_funcs = { .destroy = dce100_destroy_resource_pool, .link_enc_create = dce100_link_encoder_create, - .validate_with_context = dce100_validate_with_context, .validate_guaranteed = dce100_validate_guaranteed, .validate_bandwidth = dce100_validate_bandwidth, .validate_plane = dce100_validate_plane, + .validate_global = dce100_validate_global }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 2154c2e567f2..d682180f2eaf 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -774,41 +774,26 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; - - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + if (!is_surface_pixel_format_supported(pipe_ctx, + dc->res_pool->underlay_pipe_index)) + return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; - if (!is_surface_pixel_format_supported(pipe_ctx, - dc->res_pool->underlay_pipe_index)) - return DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED; + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + if (status != DC_OK) + return status; - if (status != DC_OK) - return status; + /* TODO: validate audio ASIC caps, encoder */ - /* TODO: validate audio ASIC caps, encoder */ - - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -927,48 +912,17 @@ static bool dce110_validate_surface_sets( return true; } -static enum dc_status dce110_validate_with_context( +enum dc_status dce110_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce110_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce110_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; - - return result; + return DC_OK; } static enum dc_status dce110_validate_guaranteed( @@ -982,13 +936,13 @@ static enum dc_status dce110_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -1078,10 +1032,10 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce110_res_pool_funcs = { .destroy = dce110_destroy_resource_pool, .link_enc_create = dce110_link_encoder_create, - .validate_with_context = dce110_validate_with_context, .validate_guaranteed = dce110_validate_guaranteed, .validate_bandwidth = dce110_validate_bandwidth, .acquire_idle_pipe_for_layer = dce110_acquire_underlay, + .validate_global = dce110_validate_global }; static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 89a8dfa68c01..85a396ef5aa5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -725,35 +725,20 @@ static struct clock_source *find_matching_pll( static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + if (status != DC_OK) + return status; - if (status != DC_OK) - return status; - - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -839,45 +824,32 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { - uint8_t i, j; /* acquire new resources */ - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( + &context->res_ctx, stream); - if (dc_is_dp_signal(pipe_ctx->stream->signal) - || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) - pipe_ctx->clock_source = - dc->res_pool->dp_clock_source; - else - pipe_ctx->clock_source = find_matching_pll( - &context->res_ctx, dc->res_pool, - stream); + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (pipe_ctx->clock_source == NULL) - return DC_NO_CLOCK_SOURCE_RESOURCE; + if (dc_is_dp_signal(pipe_ctx->stream->signal) + || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL) + pipe_ctx->clock_source = + dc->res_pool->dp_clock_source; + else + pipe_ctx->clock_source = find_matching_pll( + &context->res_ctx, dc->res_pool, + stream); - resource_reference_clock_source( - &context->res_ctx, - dc->res_pool, - pipe_ctx->clock_source); + if (pipe_ctx->clock_source == NULL) + return DC_NO_CLOCK_SOURCE_RESOURCE; - /* only one cs per stream regardless of mpo */ - break; - } - } + resource_reference_clock_source( + &context->res_ctx, + dc->res_pool, + pipe_ctx->clock_source); return DC_OK; } @@ -903,46 +875,21 @@ static bool dce112_validate_surface_sets( return true; } -enum dc_status dce112_validate_with_context( +enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream) { - struct dc_context *dc_ctx = dc->ctx; enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce112_validate_surface_sets(set, set_count)) - return DC_FAIL_SURFACE_VALIDATE; - - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); + result = resource_map_pool_resources(dc, new_ctx, dc_stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } + result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - if (!dce112_validate_bandwidth(dc, context)) - result = DC_FAIL_BANDWIDTH_VALIDATE; + result = build_mapped_resource(dc, new_ctx, dc_stream); return result; } @@ -958,13 +905,13 @@ enum dc_status dce112_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, NULL); + result = resource_map_phy_clock_resources(dc, context, stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -979,6 +926,19 @@ enum dc_status dce112_validate_guaranteed( return result; } +enum dc_status dce112_validate_global( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *old_context, + struct validate_context *context) +{ + if (!dce112_validate_surface_sets(set, set_count)) + return DC_FAIL_SURFACE_VALIDATE; + + return DC_OK; +} + static void dce112_destroy_resource_pool(struct resource_pool **pool) { struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); @@ -991,10 +951,11 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce112_res_pool_funcs = { .destroy = dce112_destroy_resource_pool, .link_enc_create = dce112_link_encoder_create, - .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce112_add_stream_to_ctx, + .validate_global = dce112_validate_global }; static void bw_calcs_data_update_from_pplib(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index 69f8f689196d..f1834bfe3d1e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -51,6 +51,11 @@ bool dce112_validate_bandwidth( struct dc *dc, struct validate_context *context); +enum dc_status dce112_add_stream_to_ctx( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream); + #endif /* __DC_RESOURCE_DCE112_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index b8fcdff40db3..e5d2d98982f7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -698,10 +698,10 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce120_res_pool_funcs = { .destroy = dce120_destroy_resource_pool, .link_enc_create = dce120_link_encoder_create, - .validate_with_context = dce112_validate_with_context, .validate_guaranteed = dce112_validate_guaranteed, .validate_bandwidth = dce112_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .add_stream_to_ctx = dce112_add_stream_to_ctx }; static void bw_calcs_data_update_from_pplib(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 838bfdaee009..ac3f42a44030 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -686,35 +686,20 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (old_context && resource_is_stream_unchanged(old_context, stream)) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; - - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; - - status = dce110_resource_build_pipe_hw_param(pipe_ctx); + status = dce110_resource_build_pipe_hw_param(pipe_ctx); - if (status != DC_OK) - return status; + if (status != DC_OK) + return status; - resource_build_info_frame(pipe_ctx); - - /* do not need to validate non root pipes */ - break; - } - } + resource_build_info_frame(pipe_ctx); return DC_OK; } @@ -751,47 +736,17 @@ static bool dce80_validate_surface_sets( return true; } -enum dc_status dce80_validate_with_context( +enum dc_status dce80_validate_global( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *old_context, + struct validate_context *context) { - struct dc_context *dc_ctx = dc->ctx; - enum dc_status result = DC_ERROR_UNEXPECTED; - int i; - if (!dce80_validate_surface_sets(set, set_count)) return DC_FAIL_SURFACE_VALIDATE; - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - - if (result == DC_OK) - result = resource_map_clock_resources(dc, context, old_context); - - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - - if (result == DC_OK) - result = build_mapped_resource(dc, context, old_context); - - if (result == DC_OK) - result = resource_build_scaling_params_for_context(dc, context); - - if (result == DC_OK) - result = dce80_validate_bandwidth(dc, context); - - return result; + return DC_OK; } enum dc_status dce80_validate_guaranteed( @@ -805,13 +760,13 @@ enum dc_status dce80_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_clock_resources(dc, context, NULL); + result = resource_map_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -837,10 +792,10 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) static const struct resource_funcs dce80_res_pool_funcs = { .destroy = dce80_destroy_resource_pool, .link_enc_create = dce80_link_encoder_create, - .validate_with_context = dce80_validate_with_context, .validate_guaranteed = dce80_validate_guaranteed, .validate_bandwidth = dce80_validate_bandwidth, - .validate_plane = dce100_validate_plane + .validate_plane = dce100_validate_plane, + .validate_global = dce80_validate_global }; static bool dce80_construct( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 954c234090db..ee43cbc70c8a 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -48,6 +48,7 @@ #include "dce/dce_hwseq.h" #include "../virtual/virtual_stream_encoder.h" #include "dce110/dce110_resource.h" +#include "dce112/dce112_resource.h" #include "vega10/soc15ip.h" @@ -840,17 +841,15 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status build_mapped_resource( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context) + struct dc_stream_state *stream) { enum dc_status status = DC_OK; - uint8_t i, j; - - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; + struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); - if (old_context && resource_is_stream_unchanged(old_context, stream)) { + /*TODO Seems unneeded anymore */ + /* if (old_context && resource_is_stream_unchanged(old_context, stream)) { if (stream != NULL && old_context->streams[i] != NULL) { - /* todo: shouldn't have to copy missing parameter here */ + todo: shouldn't have to copy missing parameter here resource_build_bit_depth_reduction_params(stream, &stream->bit_depth_params); stream->clamping.pixel_encoding = @@ -863,68 +862,34 @@ static enum dc_status build_mapped_resource( continue; } } + */ - for (j = 0; j < dc->res_pool->pipe_count ; j++) { - struct pipe_ctx *pipe_ctx = - &context->res_ctx.pipe_ctx[j]; + if (!pipe_ctx) + return DC_ERROR_UNEXPECTED; - if (context->res_ctx.pipe_ctx[j].stream != stream) - continue; + status = build_pipe_hw_param(pipe_ctx); - status = build_pipe_hw_param(pipe_ctx); - - if (status != DC_OK) - return status; - - /* do not need to validate non root pipes */ - break; - } - } + if (status != DC_OK) + return status; return DC_OK; } -enum dc_status dcn10_validate_with_context( +enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context) + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream) { - enum dc_status result = DC_OK; - int i; - - if (set_count == 0) - return result; - - for (i = 0; i < set_count; i++) { - context->streams[i] = set[i].stream; - dc_stream_retain(context->streams[i]); - context->stream_count++; - } - - result = resource_map_pool_resources(dc, context, old_context); - if (result != DC_OK) - return result; - - result = resource_map_phy_clock_resources(dc, context, old_context); - if (result != DC_OK) - return result; + enum dc_status result = DC_ERROR_UNEXPECTED; - result = build_mapped_resource(dc, context, old_context); - if (result != DC_OK) - return result; + result = resource_map_pool_resources(dc, new_ctx, dc_stream); - if (!resource_validate_attach_surfaces(set, set_count, - old_context, context, dc->res_pool)) - return DC_FAIL_ATTACH_SURFACES; + if (result == DC_OK) + result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); - result = resource_build_scaling_params_for_context(dc, context); - if (result != DC_OK) - return result; - if (!dcn_validate_bandwidth(dc, context)) - return DC_FAIL_BANDWIDTH_VALIDATE; + if (result == DC_OK) + result = build_mapped_resource(dc, new_ctx, dc_stream); return result; } @@ -940,13 +905,13 @@ enum dc_status dcn10_validate_guaranteed( dc_stream_retain(context->streams[0]); context->stream_count++; - result = resource_map_pool_resources(dc, context, NULL); + result = resource_map_pool_resources(dc, context, dc_stream); if (result == DC_OK) - result = resource_map_phy_clock_resources(dc, context, NULL); + result = resource_map_phy_clock_resources(dc, context, dc_stream); if (result == DC_OK) - result = build_mapped_resource(dc, context, NULL); + result = build_mapped_resource(dc, context, dc_stream); if (result == DC_OK) { validate_guaranteed_copy_streams( @@ -1226,10 +1191,10 @@ static struct dc_cap_funcs cap_funcs = { static struct resource_funcs dcn10_res_pool_funcs = { .destroy = dcn10_destroy_resource_pool, .link_enc_create = dcn10_link_encoder_create, - .validate_with_context = dcn10_validate_with_context, .validate_guaranteed = dcn10_validate_guaranteed, .validate_bandwidth = dcn_validate_bandwidth, .acquire_idle_pipe_for_layer = dcn10_acquire_idle_pipe_for_layer, + .add_stream_to_ctx = dcn10_add_stream_to_ctx }; static bool construct( diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index a3f0039088ab..9a3239028377 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -87,12 +87,6 @@ struct resource_funcs { void (*destroy)(struct resource_pool **pool); struct link_encoder *(*link_enc_create)( const struct encoder_init_data *init); - enum dc_status (*validate_with_context)( - struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *context, - struct validate_context *old_context); enum dc_status (*validate_guaranteed)( struct dc *dc, @@ -103,11 +97,24 @@ struct resource_funcs { struct dc *dc, struct validate_context *context); + enum dc_status (*validate_global)( + struct dc *dc, + const struct dc_validation_set set[], + int set_count, + struct validate_context *old_context, + struct validate_context *context); + struct pipe_ctx *(*acquire_idle_pipe_for_layer)( struct validate_context *context, const struct resource_pool *pool, struct dc_stream_state *stream); + enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state); + + enum dc_status (*add_stream_to_ctx)( + struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *dc_stream); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 9085ec7ceac7..ebc0f5b02365 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -82,7 +82,7 @@ void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); @@ -150,12 +150,12 @@ void resource_validate_ctx_update_pointer_after_copy( enum dc_status resource_map_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); enum dc_status resource_map_phy_clock_resources( const struct dc *dc, struct validate_context *context, - struct validate_context *old_context); + struct dc_stream_state *stream); bool pipe_need_reprogram( struct pipe_ctx *pipe_ctx_old, -- cgit v1.2.3 From 81c90ec0348002b6f6b0c108e3e60e666cb4b673 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 7 Sep 2017 16:46:34 -0400 Subject: drm/amd/display: Refactor dc_state creation into a function. For less repetition and easy debugging. Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +--- drivers/gpu/drm/amd/display/dc/core/dc.c | 19 +++++++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 1 + 3 files changed, 15 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 17e9bf7a2ebb..776bd4a1fecc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -702,13 +702,11 @@ dm_atomic_state_alloc(struct drm_device *dev) goto fail; /* copy existing configuration */ - new_ctx = dm_alloc(sizeof(*new_ctx)); + new_ctx = dc_create_state(); if (!new_ctx) goto fail; - atomic_inc(&new_ctx->ref_count); - dc_resource_validate_ctx_copy_construct_current(dc, new_ctx); state->context = new_ctx; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 10126d9a7233..8a6bd2917799 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -497,15 +497,13 @@ static bool construct(struct dc *dc, goto fail; } - dc->current_context = dm_alloc(sizeof(*dc->current_context)); + dc->current_context = dc_create_state(); if (!dc->current_context) { dm_error("%s: failed to create validate ctx\n", __func__); goto fail; } - atomic_inc(&dc->current_context->ref_count); - dc_ctx->cgs_device = init_params->cgs_device; dc_ctx->driver_context = init_params->driver; dc_ctx->dc = dc; @@ -1162,6 +1160,17 @@ bool dc_commit_planes_to_stream( return true; } +struct validate_context *dc_create_state(void) +{ + struct validate_context *context = dm_alloc(sizeof(struct validate_context)); + + if (!context) + return NULL; + + atomic_inc(&context->ref_count); + return context; +} + void dc_retain_validate_context(struct validate_context *context) { ASSERT(atomic_read(&context->ref_count) > 0); @@ -1442,12 +1451,10 @@ void dc_update_planes_and_stream(struct dc *dc, new_planes[i] = srf_updates[i].surface; /* initialize scratch memory for building context */ - context = dm_alloc(sizeof(*context)); + context = dc_create_state(); if (context == NULL) goto context_alloc_fail; - atomic_inc(&context->ref_count); - dc_resource_validate_ctx_copy_construct( core_dc->current_context, context); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2b4fc6616243..928d2a0501eb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -732,6 +732,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( const struct dc_stream_status *stream_status); +struct validate_context *dc_create_state(void); void dc_retain_validate_context(struct validate_context *context); void dc_release_validate_context(struct validate_context *context); -- cgit v1.2.3 From d4d4a64574ab546811d29a21366afe6bb6cdb264 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 21 Sep 2017 16:13:00 -0400 Subject: drm/amd/display: Move copy_construct from state_alloc to atomic_check. Previously atomic_check assumed that dc_state is allocated and filled in. This is not the case when we hit EDEADLK and have to backup and retry. We could change atomic_state_clear but that revealed some other problems. For now let's create and construct dc_state in atomic_check. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 776bd4a1fecc..4bb78f76acce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -691,9 +691,6 @@ struct drm_atomic_state * dm_atomic_state_alloc(struct drm_device *dev) { struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); - struct validate_context *new_ctx; - struct amdgpu_device *adev = dev->dev_private; - struct dc *dc = adev->dm.dc; if (!state) return NULL; @@ -701,16 +698,6 @@ dm_atomic_state_alloc(struct drm_device *dev) if (drm_atomic_state_init(dev, &state->base) < 0) goto fail; - /* copy existing configuration */ - new_ctx = dc_create_state(); - - if (!new_ctx) - goto fail; - - dc_resource_validate_ctx_copy_construct_current(dc, new_ctx); - - state->context = new_ctx; - return &state->base; fail: @@ -4465,6 +4452,10 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, return ret; } + dm_state->context = dc_create_state(); + ASSERT(dm_state->context); + dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); + /* copy existing configuration */ set_count = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { -- cgit v1.2.3 From 79c24086570953e10f2c5c08946619a9a0f71ee9 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Thu, 17 Aug 2017 17:00:47 -0400 Subject: drm/amd/display: Disable stutter for Raven Signed-off-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4bb78f76acce..e037ed85a5cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1383,6 +1383,10 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) DRM_ERROR("DM: Failed to initialize IRQ\n"); goto fail_free_encoder; } + /* + * Temporary disable until pplib/smu interaction is implemented + */ + dm->dc->debug.disable_stutter = true; break; #endif default: -- cgit v1.2.3 From 19f89e2392e692208a0a00465d30b2b2bf43e9a9 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 11 Aug 2017 10:43:45 -0400 Subject: drm/amd/display: Per plane validation context build. Introduce add/remove plane to/from context. Make DC wrapper to use them in WIndows/Diags. Use them in dc_update_surface_to_stream. Call add/remove plane from Linux DM. Remove dc_validation_set from dc_validate_global_state interface and by this remove clean Linux DM from using it. Signed-off-by: Andrey Grodzovsky Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 165 ++++------ drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 362 +++++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 37 ++- .../drm/amd/display/dc/dce100/dce100_resource.c | 16 +- .../drm/amd/display/dc/dce110/dce110_resource.c | 26 +- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 16 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 - 9 files changed, 353 insertions(+), 300 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e037ed85a5cc..e8835e751702 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4304,77 +4304,6 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector dm_force_atomic_commit(&aconnector->base); } -static uint32_t add_val_sets_plane( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream_state *stream, - struct dc_plane_state *plane_state) -{ - uint32_t i = 0, j = 0; - - while (i < set_count) { - if (val_sets[i].stream == stream) { - while (val_sets[i].plane_states[j]) - j++; - break; - } - ++i; - } - - val_sets[i].plane_states[j] = plane_state; - val_sets[i].plane_count++; - - return val_sets[i].plane_count; -} - -static uint32_t update_in_val_sets_stream( - struct dc_validation_set *val_sets, - uint32_t set_count, - struct dc_stream_state *old_stream, - struct dc_stream_state *new_stream, - struct drm_crtc *crtc) -{ - uint32_t i = 0; - - while (i < set_count) { - if (val_sets[i].stream == old_stream) - break; - ++i; - } - - val_sets[i].stream = new_stream; - - if (i == set_count) - /* nothing found. add new one to the end */ - return set_count + 1; - - return set_count; -} - -static uint32_t remove_from_val_sets( - struct dc_validation_set *val_sets, - uint32_t set_count, - const struct dc_stream_state *stream) -{ - int i; - - for (i = 0; i < set_count; i++) - if (val_sets[i].stream == stream) - break; - - if (i == set_count) { - /* nothing found */ - return set_count; - } - - set_count--; - - for (; i < set_count; i++) - val_sets[i] = val_sets[i + 1]; - - return set_count; -} - /*` * Grabs all modesetting locks to serialize against any blocking commits, * Waits for completion of all non blocking commits. @@ -4438,10 +4367,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dc *dc = adev->dm.dc; struct drm_connector *connector; struct drm_connector_state *conn_state; - int set_count; - struct dc_validation_set set[MAX_STREAMS] = { { 0 } }; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + bool pflip_needed = !state->allow_modeset; /* * This bool will be set for true for any modeset/reset @@ -4460,16 +4388,44 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, ASSERT(dm_state->context); dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); - /* copy existing configuration */ - set_count = 0; - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + /* Remove exiting planes if they are disabled or their CRTC is updated */ + for_each_crtc_in_state(state, crtc, crtc_state, i) { + new_acrtc_state = to_dm_crtc_state(crtc_state); - old_acrtc_state = to_dm_crtc_state(crtc->state); + if (pflip_needed) + continue; - if (old_acrtc_state->stream) { - dc_stream_retain(old_acrtc_state->stream); - set[set_count].stream = old_acrtc_state->stream; - ++set_count; + for_each_plane_in_state(state, plane, plane_state, j) { + struct drm_crtc *plane_crtc = plane_state->crtc; + struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + + if (plane->type == DRM_PLANE_TYPE_CURSOR) + continue; + + if (crtc != plane_crtc || !dm_plane_state->dc_state) + continue; + + WARN_ON(!new_acrtc_state->stream); + + if (drm_atomic_plane_disabling(plane->state, plane_state) || + drm_atomic_crtc_needs_modeset(crtc_state)) { + if (!dc_remove_plane_from_context( + dc, + new_acrtc_state->stream, + dm_plane_state->dc_state, + dm_state->context)) { + + ret = EINVAL; + goto fail; + } + + } + + dc_plane_state_release(dm_plane_state->dc_state); + dm_plane_state->dc_state = NULL; + + DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n", + plane->base.id, crtc->base.id); } } @@ -4513,11 +4469,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } - set_count = remove_from_val_sets( - set, - set_count, - new_acrtc_state->stream); - dc_stream_release(new_acrtc_state->stream); new_acrtc_state->stream = NULL; @@ -4576,13 +4527,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, new_acrtc_state->stream = new_stream; - set_count = update_in_val_sets_stream( - set, - set_count, - old_acrtc_state->stream, - new_acrtc_state->stream, - crtc); - if (!dc_add_stream_to_ctx( dc, dm_state->context, @@ -4639,32 +4583,32 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } + /* Add new planes */ for_each_crtc_in_state(state, crtc, crtc_state, i) { new_acrtc_state = to_dm_crtc_state(crtc_state); + if (pflip_needed) + continue; + for_each_plane_in_state(state, plane, plane_state, j) { struct drm_crtc *plane_crtc = plane_state->crtc; - struct drm_framebuffer *fb = plane_state->fb; - bool pflip_needed; struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); /*TODO Implement atomic check for cursor plane */ if (plane->type == DRM_PLANE_TYPE_CURSOR) continue; - if (!fb || !plane_crtc || crtc != plane_crtc || !crtc_state->active) + if (crtc != plane_crtc) continue; - WARN_ON(!new_acrtc_state->stream); - - pflip_needed = !state->allow_modeset; - if (!pflip_needed) { + if (!drm_atomic_plane_disabling(plane->state, plane_state)) { struct dc_plane_state *dc_plane_state; + WARN_ON(!new_acrtc_state->stream); + dc_plane_state = dc_create_plane_state(dc); - if (dm_plane_state->dc_state) - dc_plane_state_release(dm_plane_state->dc_state); + WARN_ON(dm_plane_state->dc_state); dm_plane_state->dc_state = dc_plane_state; @@ -4677,10 +4621,17 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - add_val_sets_plane(set, - set_count, - new_acrtc_state->stream, - dc_plane_state); + + if (!dc_add_plane_to_context( + dc, + new_acrtc_state->stream, + dc_plane_state, + dm_state->context)) { + + ret = EINVAL; + goto fail; + } + lock_and_validation_needed = true; } @@ -4708,7 +4659,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - if (!dc_validate_global_state(dc, set, set_count, dm_state->context)) { + if (!dc_validate_global_state(dc, dm_state->context)) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index ab2b8f23b20a..79980cb0900c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1305,10 +1305,16 @@ void dc_update_planes_and_stream(struct dc *dc, dc_resource_validate_ctx_copy_construct( core_dc->current_context, context); + /*remove old surfaces from context */ + if (!dc_rem_all_planes_for_stream(dc, stream, context)) { + + BREAK_TO_DEBUGGER(); + goto fail; + } + /* add surface to context */ - if (!resource_attach_surfaces_to_context( - new_planes, surface_count, stream, - context, core_dc->res_pool)) { + if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { + BREAK_TO_DEBUGGER(); goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index fbfe15f783c0..6eee1b1a563e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -946,6 +946,26 @@ struct pipe_ctx *resource_get_head_pipe_for_stream( return NULL; } +static struct pipe_ctx *resource_get_tail_pipe_for_stream( + struct resource_context *res_ctx, + struct dc_stream_state *stream) +{ + struct pipe_ctx *head_pipe, *tail_pipe; + head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream); + + if (!head_pipe) + return NULL; + + tail_pipe = head_pipe->bottom_pipe; + + while (tail_pipe) { + head_pipe = tail_pipe; + tail_pipe = tail_pipe->bottom_pipe; + } + + return head_pipe; +} + /* * A free_pipe for a stream is defined here as a pipe * that has no surface attached yet @@ -990,22 +1010,6 @@ static struct pipe_ctx *acquire_free_pipe_for_stream( } -static void release_free_pipes_for_stream( - struct resource_context *res_ctx, - struct dc_stream_state *stream) -{ - int i; - - for (i = MAX_PIPES - 1; i >= 0; i--) { - /* never release the topmost pipe*/ - if (res_ctx->pipe_ctx[i].stream == stream && - res_ctx->pipe_ctx[i].top_pipe && - !res_ctx->pipe_ctx[i].plane_state) { - memset(&res_ctx->pipe_ctx[i], 0, sizeof(struct pipe_ctx)); - } - } -} - #if defined(CONFIG_DRM_AMD_DC_DCN1_0) static int acquire_first_split_pipe( struct resource_context *res_ctx, @@ -1040,96 +1044,235 @@ static int acquire_first_split_pipe( } #endif -bool resource_attach_surfaces_to_context( - struct dc_plane_state * const *plane_states, - int surface_count, +bool dc_add_plane_to_context( + const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context, - const struct resource_pool *pool) + struct dc_plane_state *plane_state, + struct validate_context *context) { int i; - struct pipe_ctx *tail_pipe; + struct resource_pool *pool = dc->res_pool; + struct pipe_ctx *head_pipe, *tail_pipe, *free_pipe; struct dc_stream_status *stream_status = NULL; + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + stream_status = &context->stream_status[i]; + break; + } + if (stream_status == NULL) { + dm_error("Existing stream not found; failed to attach surface!\n"); + return false; + } + + + if (stream_status->plane_count == MAX_SURFACE_NUM) { + dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n", + plane_state, MAX_SURFACE_NUM); + return false; + } + + head_pipe = resource_get_head_pipe_for_stream(&context->res_ctx, stream); + + if (!head_pipe) { + dm_error("Head pipe not found for stream_state %p !\n", stream); + return false; + } + + /* retain new surfaces */ + dc_plane_state_retain(plane_state); + + free_pipe = acquire_free_pipe_for_stream(context, pool, stream); - if (surface_count > MAX_SURFACE_NUM) { - dm_error("Surface: can not attach %d surfaces! Maximum is: %d\n", - surface_count, MAX_SURFACE_NUM); +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) + if (!free_pipe) { + int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); + if (pipe_idx >= 0) + free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; + } +#endif + if (!free_pipe) { + stream_status->plane_states[i] = NULL; return false; } + free_pipe->plane_state = plane_state; + + if (head_pipe != free_pipe) { + + tail_pipe = resource_get_tail_pipe_for_stream(&context->res_ctx, stream); + ASSERT(tail_pipe); + + free_pipe->stream_res.tg = tail_pipe->stream_res.tg; + free_pipe->stream_res.opp = tail_pipe->stream_res.opp; + free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; + free_pipe->stream_res.audio = tail_pipe->stream_res.audio; + free_pipe->clock_source = tail_pipe->clock_source; + free_pipe->top_pipe = tail_pipe; + tail_pipe->bottom_pipe = free_pipe; + } + + /* assign new surfaces*/ + stream_status->plane_states[stream_status->plane_count] = plane_state; + + stream_status->plane_count++; + + return true; +} + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context) +{ + int i; + struct dc_stream_status *stream_status = NULL; + struct resource_pool *pool = dc->res_pool; + for (i = 0; i < context->stream_count; i++) if (context->streams[i] == stream) { stream_status = &context->stream_status[i]; break; } + if (stream_status == NULL) { - dm_error("Existing stream not found; failed to attach surfaces\n"); + dm_error("Existing stream not found; failed to remove plane.\n"); return false; } - /* retain new surfaces */ - for (i = 0; i < surface_count; i++) - dc_plane_state_retain(plane_states[i]); - - /* detach surfaces from pipes */ - for (i = 0; i < pool->pipe_count; i++) - if (context->res_ctx.pipe_ctx[i].stream == stream) { - context->res_ctx.pipe_ctx[i].plane_state = NULL; - context->res_ctx.pipe_ctx[i].bottom_pipe = NULL; - } + /* release pipe for plane*/ + for (i = pool->pipe_count - 1; i >= 0; i--) { + struct pipe_ctx *pipe_ctx; - /* release existing surfaces*/ - for (i = 0; i < stream_status->plane_count; i++) - dc_plane_state_release(stream_status->plane_states[i]); + if (context->res_ctx.pipe_ctx[i].plane_state == plane_state) { + pipe_ctx = &context->res_ctx.pipe_ctx[i]; - for (i = surface_count; i < stream_status->plane_count; i++) - stream_status->plane_states[i] = NULL; + if (pipe_ctx->top_pipe) + pipe_ctx->top_pipe->bottom_pipe = pipe_ctx->bottom_pipe; - tail_pipe = NULL; - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *plane_state = plane_states[i]; - struct pipe_ctx *free_pipe = acquire_free_pipe_for_stream( - context, pool, stream); + /* Second condition is to avoid setting NULL to top pipe + * of tail pipe making it look like head pipe in subsequent + * deletes + */ + if (pipe_ctx->bottom_pipe && pipe_ctx->top_pipe) + pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (!free_pipe) { - int pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); - if (pipe_idx >= 0) - free_pipe = &context->res_ctx.pipe_ctx[pipe_idx]; - } -#endif - if (!free_pipe) { - stream_status->plane_states[i] = NULL; - return false; + /* + * For head pipe detach surfaces from pipe for tail + * pipe just zero it out + */ + if (!pipe_ctx->top_pipe) { + pipe_ctx->plane_state = NULL; + pipe_ctx->bottom_pipe = NULL; + } else { + memset(pipe_ctx, 0, sizeof(*pipe_ctx)); + } } + } + - free_pipe->plane_state = plane_state; + for (i = 0; i < stream_status->plane_count; i++) { + if (stream_status->plane_states[i] == plane_state) { - if (tail_pipe) { - free_pipe->stream_res.tg = tail_pipe->stream_res.tg; - free_pipe->stream_res.opp = tail_pipe->stream_res.opp; - free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; - free_pipe->stream_res.audio = tail_pipe->stream_res.audio; - free_pipe->clock_source = tail_pipe->clock_source; - free_pipe->top_pipe = tail_pipe; - tail_pipe->bottom_pipe = free_pipe; + dc_plane_state_release(stream_status->plane_states[i]); + break; } + } - tail_pipe = free_pipe; + if (i == stream_status->plane_count) { + dm_error("Existing plane_state not found; failed to detach it!\n"); + return false; } - release_free_pipes_for_stream(&context->res_ctx, stream); + stream_status->plane_count--; - /* assign new surfaces*/ - for (i = 0; i < surface_count; i++) - stream_status->plane_states[i] = plane_states[i]; + /* Trim back arrays */ + for (i = 0; i < stream_status->plane_count; i++) + stream_status->plane_states[i] = stream_status->plane_states[i + 1]; + + stream_status->plane_states[stream_status->plane_count] = NULL; + + return true; +} + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct validate_context *context) +{ + int i, old_plane_count; + struct dc_stream_status *stream_status = NULL; + struct dc_plane_state *del_planes[MAX_SURFACE_NUM] = { 0 }; + + for (i = 0; i < context->stream_count; i++) + if (context->streams[i] == stream) { + stream_status = &context->stream_status[i]; + break; + } + + if (stream_status == NULL) { + dm_error("Existing stream %p not found!\n", stream); + return false; + } + + old_plane_count = stream_status->plane_count; - stream_status->plane_count = surface_count; + for (i = 0; i < old_plane_count; i++) + del_planes[i] = stream_status->plane_states[i]; + + for (i = 0; i < old_plane_count; i++) + if (!dc_remove_plane_from_context(dc, stream, del_planes[i], context)) + return false; return true; } +static bool add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + const struct dc_validation_set set[], + int set_count, + struct validate_context *context) +{ + int i, j; + + for (i = 0; i < set_count; i++) + if (set[i].stream == stream) + break; + + if (i == set_count) { + dm_error("Stream %p not found in set!\n", stream); + return false; + } + + for (j = 0; j < set[i].plane_count; j++) + if (!dc_add_plane_to_context(dc, stream, set[i].plane_states[j], context)) + return false; + + return true; +} + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct validate_context *context) +{ + struct dc_validation_set set; + int i; + + set.stream = stream; + set.plane_count = plane_count; + + for (i = 0; i < plane_count; i++) + set.plane_states[i] = plane_states[i]; + + return add_all_planes_for_stream(dc, stream, &set, 1, context); +} + + static bool is_timing_changed(struct dc_stream_state *cur_stream, struct dc_stream_state *new_stream) @@ -1178,41 +1321,6 @@ bool dc_is_stream_unchanged( return true; } -bool resource_validate_attach_surfaces( - const struct dc_validation_set set[], - int set_count, - const struct validate_context *old_context, - struct validate_context *context, - const struct resource_pool *pool) -{ - int i, j; - - for (i = 0; i < set_count; i++) { - for (j = 0; old_context && j < old_context->stream_count; j++) - if (dc_is_stream_unchanged( - old_context->streams[j], - context->streams[i])) { - if (!resource_attach_surfaces_to_context( - old_context->stream_status[j].plane_states, - old_context->stream_status[j].plane_count, - context->streams[i], - context, pool)) - return false; - context->stream_status[i] = old_context->stream_status[j]; - } - if (set[i].plane_count != 0) - if (!resource_attach_surfaces_to_context( - set[i].plane_states, - set[i].plane_count, - context->streams[i], - context, pool)) - return false; - - } - - return true; -} - /* Maximum TMDS single link pixel clock 165MHz */ #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ_UPMOST 297000 @@ -1392,23 +1500,22 @@ bool dc_remove_stream_from_ctx( struct validate_context *new_ctx, struct dc_stream_state *stream) { - int i, j; + int i; struct dc_context *dc_ctx = dc->ctx; struct pipe_ctx *del_pipe = NULL; - /*TODO MPO to remove extra pipe or in surface remove ?*/ - - /* Release primary and secondary pipe (if exsist) */ + /* Release primary pipe */ for (i = 0; i < MAX_PIPES; i++) { - if (new_ctx->res_ctx.pipe_ctx[i].stream == stream) { + if (new_ctx->res_ctx.pipe_ctx[i].stream == stream && + !new_ctx->res_ctx.pipe_ctx[i].top_pipe) { del_pipe = &new_ctx->res_ctx.pipe_ctx[i]; - if (del_pipe->stream_res.stream_enc) - update_stream_engine_usage( - &new_ctx->res_ctx, + ASSERT(del_pipe->stream_res.stream_enc); + update_stream_engine_usage( + &new_ctx->res_ctx, dc->res_pool, - del_pipe->stream_res.stream_enc, - false); + del_pipe->stream_res.stream_enc, + false); if (del_pipe->stream_res.audio) update_audio_usage( @@ -1418,6 +1525,8 @@ bool dc_remove_stream_from_ctx( false); memset(del_pipe, 0, sizeof(*del_pipe)); + + break; } } @@ -1438,10 +1547,6 @@ bool dc_remove_stream_from_ctx( dc_stream_release(new_ctx->streams[i]); new_ctx->stream_count--; - /*TODO move into dc_remove_surface_from_ctx ?*/ - for (j = 0; j < new_ctx->stream_status[i].plane_count; j++) - dc_plane_state_release(new_ctx->stream_status[i].plane_states[j]); - /* Trim back arrays */ for (; i < new_ctx->stream_count; i++) { new_ctx->streams[i] = new_ctx->streams[i + 1]; @@ -1636,18 +1741,14 @@ void dc_resource_validate_ctx_copy_construct_current( bool dc_validate_global_state( struct dc *dc, - const struct dc_validation_set set[], - int set_count, struct validate_context *new_ctx) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct dc_context *dc_ctx = dc->ctx; - struct validate_context *old_context = dc->current_context; int i, j; if (dc->res_pool->funcs->validate_global && - dc->res_pool->funcs->validate_global(dc, set, set_count, - old_context, new_ctx) != DC_OK) + dc->res_pool->funcs->validate_global( + dc, new_ctx) != DC_OK) return false; /* TODO without this SWDEV-114774 brakes */ @@ -1687,15 +1788,6 @@ bool dc_validate_global_state( } } - /*TODO This should be ok */ - /* Split pipe resource, do not acquire back end */ - - if (!resource_validate_attach_surfaces( - set, set_count, old_context, new_ctx, dc->res_pool)) { - DC_ERROR("Failed to attach surface to stream!\n"); - return DC_FAIL_ATTACH_SURFACES; - } - result = resource_build_scaling_params_for_context(dc, new_ctx); if (result == DC_OK) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 9cc1c28caa4e..55fc58102515 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -619,15 +619,40 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *h_position, uint32_t *v_position); -bool dc_remove_stream_from_ctx( +bool dc_add_stream_to_ctx( struct dc *dc, + struct validate_context *new_ctx, + struct dc_stream_state *stream); + +bool dc_remove_stream_from_ctx( + struct dc *dc, struct validate_context *new_ctx, struct dc_stream_state *stream); -bool dc_add_stream_to_ctx( - struct dc *dc, - struct validate_context *new_ctx, - struct dc_stream_state *stream); + +bool dc_add_plane_to_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context); + +bool dc_remove_plane_from_context( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state *plane_state, + struct validate_context *context); + +bool dc_rem_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct validate_context *context); + +bool dc_add_all_planes_for_stream( + const struct dc *dc, + struct dc_stream_state *stream, + struct dc_plane_state * const *plane_states, + int plane_count, + struct validate_context *context); /* * Structure to store surface/stream associations for validation @@ -644,8 +669,6 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); bool dc_validate_global_state( struct dc *dc, - const struct dc_validation_set set[], - int set_count, struct validate_context *new_ctx); /* diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c9dad4e2a7c8..c991610315b2 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -684,19 +684,18 @@ bool dce100_validate_bandwidth( } static bool dce100_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -706,12 +705,9 @@ static bool dce100_validate_surface_sets( enum dc_status dce100_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce100_validate_surface_sets(set, set_count)) + if (!dce100_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index d682180f2eaf..18c67f89e9b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -880,31 +880,30 @@ static bool dce110_validate_bandwidth( } static bool dce110_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 2) + if (context->stream_status[i].plane_count > 2) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].plane_count == 2) { - if (set[i].plane_states[1]->format + if (context->stream_status[i].plane_count == 2) { + if (context->stream_status[i].plane_states[1]->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; - if (set[i].plane_states[1]->src_rect.width > 1920 - || set[i].plane_states[1]->src_rect.height > 1080) + if (context->stream_status[i].plane_states[1]->src_rect.width > 1920 + || context->stream_status[i].plane_states[1]->src_rect.height > 1080) return false; - if (set[i].stream->timing.pixel_encoding != PIXEL_ENCODING_RGB) + if (context->streams[i]->timing.pixel_encoding != PIXEL_ENCODING_RGB) return false; } } @@ -914,12 +913,9 @@ static bool dce110_validate_surface_sets( enum dc_status dce110_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce110_validate_surface_sets(set, set_count)) + if (!dce110_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 85a396ef5aa5..d5a8ee69171d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -855,19 +855,18 @@ enum dc_status resource_map_phy_clock_resources( } static bool dce112_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -928,12 +927,9 @@ enum dc_status dce112_validate_guaranteed( enum dc_status dce112_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce112_validate_surface_sets(set, set_count)) + if (!dce112_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index ac3f42a44030..945ff7ee6cd9 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -716,19 +716,18 @@ bool dce80_validate_bandwidth( } static bool dce80_validate_surface_sets( - const struct dc_validation_set set[], - int set_count) + struct validate_context *context) { int i; - for (i = 0; i < set_count; i++) { - if (set[i].plane_count == 0) + for (i = 0; i < context->stream_count; i++) { + if (context->stream_status[i].plane_count == 0) continue; - if (set[i].plane_count > 1) + if (context->stream_status[i].plane_count > 1) return false; - if (set[i].plane_states[0]->format + if (context->stream_status[i].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) return false; } @@ -738,12 +737,9 @@ static bool dce80_validate_surface_sets( enum dc_status dce80_validate_global( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context) { - if (!dce80_validate_surface_sets(set, set_count)) + if (!dce80_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; return DC_OK; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 62bd11d250c5..bd1a6367872f 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -99,9 +99,6 @@ struct resource_funcs { enum dc_status (*validate_global)( struct dc *dc, - const struct dc_validation_set set[], - int set_count, - struct validate_context *old_context, struct validate_context *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( -- cgit v1.2.3 From 62f555377f972c206c69c6acc93d91f2baec9a26 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Fri, 18 Aug 2017 10:52:20 -0400 Subject: drm/amd/display: Refactor atomic check. Split into update crtcs and update plane functions. Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 462 ++++++++++++---------- 1 file changed, 261 insertions(+), 201 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e8835e751702..193a634f46e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1640,12 +1640,6 @@ static bool modeset_required(struct drm_crtc_state *crtc_state, struct dc_stream_state *new_stream, struct dc_stream_state *old_stream) { - if (dc_is_stream_unchanged(new_stream, old_stream)) { - crtc_state->mode_changed = false; - DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d", - crtc_state->mode_changed); - } - if (!drm_atomic_crtc_needs_modeset(crtc_state)) return false; @@ -3875,9 +3869,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, continue; } - if (!fb || !crtc || pcrtc != crtc || !crtc->state->active || - (!crtc->state->planes_changed && - !pcrtc->state->color_mgmt_changed)) + if (!fb || !crtc || pcrtc != crtc || !crtc->state->active) continue; pflip_needed = !state->allow_modeset; @@ -4354,95 +4346,76 @@ static int do_aquire_global_lock( return ret < 0 ? ret : 0; } -int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) +static int dm_update_crtcs_state( + struct dc *dc, + struct drm_atomic_state *state, + bool enable, + bool *lock_and_validation_needed) { struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; - struct drm_plane *plane; - struct drm_plane_state *plane_state; - int i, j; - int ret; - struct amdgpu_device *adev = dev->dev_private; - struct dc *dc = adev->dm.dc; - struct drm_connector *connector; - struct drm_connector_state *conn_state; + int i; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - bool pflip_needed = !state->allow_modeset; - - /* - * This bool will be set for true for any modeset/reset - * or plane update which implies non fast surface update. - */ - bool lock_and_validation_needed = false; - - ret = drm_atomic_helper_check_modeset(dev, state); - - if (ret) { - DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); - return ret; - } - - dm_state->context = dc_create_state(); - ASSERT(dm_state->context); - dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); + int ret = 0; - /* Remove exiting planes if they are disabled or their CRTC is updated */ + /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ + /* update changed items */ for_each_crtc_in_state(state, crtc, crtc_state, i) { - new_acrtc_state = to_dm_crtc_state(crtc_state); + struct amdgpu_crtc *acrtc = NULL; + struct amdgpu_connector *aconnector = NULL; + struct dc_stream_state *new_stream = NULL; + struct drm_connector_state *conn_state = NULL; + struct dm_connector_state *dm_conn_state = NULL; - if (pflip_needed) - continue; + old_acrtc_state = to_dm_crtc_state(crtc->state); + new_acrtc_state = to_dm_crtc_state(crtc_state); + acrtc = to_amdgpu_crtc(crtc); - for_each_plane_in_state(state, plane, plane_state, j) { - struct drm_crtc *plane_crtc = plane_state->crtc; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); - if (plane->type == DRM_PLANE_TYPE_CURSOR) - continue; + /* TODO This hack should go away */ + if (aconnector && aconnector->dc_sink) { + conn_state = drm_atomic_get_connector_state(state, + &aconnector->base); - if (crtc != plane_crtc || !dm_plane_state->dc_state) - continue; + if (IS_ERR(conn_state)) { + ret = PTR_ERR_OR_ZERO(conn_state); + break; + } - WARN_ON(!new_acrtc_state->stream); + dm_conn_state = to_dm_connector_state(conn_state); - if (drm_atomic_plane_disabling(plane->state, plane_state) || - drm_atomic_crtc_needs_modeset(crtc_state)) { - if (!dc_remove_plane_from_context( - dc, - new_acrtc_state->stream, - dm_plane_state->dc_state, - dm_state->context)) { + new_stream = create_stream_for_sink(aconnector, + &crtc_state->mode, + dm_conn_state); - ret = EINVAL; - goto fail; - } + /* + * we can have no stream on ACTION_SET if a display + * was disconnected during S3, in this case it not and + * error, the OS will be updated after detection, and + * do the right thing on next atomic commit + */ + if (!new_stream) { + DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + __func__, acrtc->base.base.id); + break; } + } - dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->dc_state = NULL; + if (dc_is_stream_unchanged(new_stream, + old_acrtc_state->stream)) { - DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n", - plane->base.id, crtc->base.id); - } - } + crtc_state->mode_changed = false; - /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ - /* update changed items */ - for_each_crtc_in_state(state, crtc, crtc_state, i) { - struct amdgpu_crtc *acrtc = NULL; - struct amdgpu_connector *aconnector = NULL; - struct dc_stream_state *new_stream = NULL; - struct drm_connector_state *conn_state = NULL; - struct dm_connector_state *dm_conn_state = NULL; + DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d", + crtc_state->mode_changed); + } - old_acrtc_state = to_dm_crtc_state(crtc->state); - new_acrtc_state = to_dm_crtc_state(crtc_state); - acrtc = to_amdgpu_crtc(crtc); - aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); + if (!drm_atomic_crtc_needs_modeset(crtc_state)) + continue; DRM_DEBUG_KMS( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " @@ -4456,109 +4429,256 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, crtc_state->active_changed, crtc_state->connectors_changed); - if (modereset_required(crtc_state)) { + /* Remove stream for any changed/disabled CRTC */ + if (!enable) { + + if (!old_acrtc_state->stream) + continue; + + DRM_DEBUG_KMS("Disabling DRM crtc: %d\n", + crtc->base.id); /* i.e. reset mode */ - if (new_acrtc_state->stream) { + if (!dc_remove_stream_from_ctx( + dc, + dm_state->context, + old_acrtc_state->stream)) { + ret = -EINVAL; + break; + } + + dc_stream_release(old_acrtc_state->stream); + new_acrtc_state->stream = NULL; + + *lock_and_validation_needed = true; + + } else {/* Add stream for any updated/enabled CRTC */ + + if (modereset_required(crtc_state)) + continue; + + if (modeset_required(crtc_state, new_stream, + old_acrtc_state->stream)) { + + WARN_ON(new_acrtc_state->stream); + + new_acrtc_state->stream = new_stream; + dc_stream_retain(new_stream); + + DRM_DEBUG_KMS("Enabling DRM crtc: %d\n", + crtc->base.id); - if (!dc_remove_stream_from_ctx( + if (!dc_add_stream_to_ctx( dc, dm_state->context, new_acrtc_state->stream)) { ret = -EINVAL; - goto fail; + break; } - dc_stream_release(new_acrtc_state->stream); - new_acrtc_state->stream = NULL; - - lock_and_validation_needed = true; + *lock_and_validation_needed = true; } + } - } else { + /* Release extra reference */ + if (new_stream) + dc_stream_release(new_stream); + } - if (aconnector) { - conn_state = drm_atomic_get_connector_state(state, - &aconnector->base); + return ret; +} - if (IS_ERR(conn_state)) { - ret = PTR_ERR_OR_ZERO(conn_state); - goto fail; - } +static int dm_update_planes_state( + struct dc *dc, + struct drm_atomic_state *state, + bool enable, + bool *lock_and_validation_needed) +{ + struct drm_crtc *new_plane_crtc, *old_plane_crtc; + struct drm_crtc_state *new_crtc_state; + struct drm_plane *plane; + struct drm_plane_state *old_plane_state, *new_plane_state; + struct dm_crtc_state *new_acrtc_state, *old_acrtc_state; + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; + int i ; + /* TODO return page_flip_needed() function */ + bool pflip_needed = !state->allow_modeset; + int ret = 0; - dm_conn_state = to_dm_connector_state(conn_state); + if (pflip_needed) + return ret; - new_stream = create_stream_for_sink(aconnector, - &crtc_state->mode, - dm_conn_state); + /* Add new planes */ + for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { + new_plane_crtc = new_plane_state->crtc; + old_plane_crtc = old_plane_state->crtc; + new_dm_plane_state = to_dm_plane_state(new_plane_state); + old_dm_plane_state = to_dm_plane_state(old_plane_state); + + /*TODO Implement atomic check for cursor plane */ + if (plane->type == DRM_PLANE_TYPE_CURSOR) + continue; - /* - * we can have no stream on ACTION_SET if a display - * was disconnected during S3, in this case it not and - * error, the OS will be updated after detection, and - * do the right thing on next atomic commit - */ + /* Remove any changed/removed planes */ + if (!enable) { - if (!new_stream) { - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", - __func__, acrtc->base.base.id); - break; - } + if (!old_plane_crtc) + continue; + + old_acrtc_state = to_dm_crtc_state( + drm_atomic_get_old_crtc_state( + state, + old_plane_crtc)); + if (!old_acrtc_state->stream) + continue; + + DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n", + plane->base.id, old_plane_crtc->base.id); + if (!dc_remove_plane_from_context( + dc, + old_acrtc_state->stream, + old_dm_plane_state->dc_state, + dm_state->context)) { + + ret = EINVAL; + return ret; } - if (modeset_required(crtc_state, new_stream, - old_acrtc_state->stream)) { - if (new_acrtc_state->stream) { + dc_plane_state_release(old_dm_plane_state->dc_state); + new_dm_plane_state->dc_state = NULL; - if (!dc_remove_stream_from_ctx( - dc, - dm_state->context, - new_acrtc_state->stream)) { - ret = -EINVAL; - goto fail; - } + *lock_and_validation_needed = true; + } else { /* Add new planes */ - dc_stream_release(new_acrtc_state->stream); - } + if (drm_atomic_plane_disabling(plane->state, new_plane_state)) + continue; - new_acrtc_state->stream = new_stream; + if (!new_plane_crtc) + continue; - if (!dc_add_stream_to_ctx( - dc, - dm_state->context, - new_acrtc_state->stream)) { - ret = -EINVAL; - goto fail; - } + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); - lock_and_validation_needed = true; - } else { - /* - * The new stream is unused, so we release it - */ - if (new_stream) - dc_stream_release(new_stream); + if (!new_acrtc_state->stream) + continue; + + + WARN_ON(new_dm_plane_state->dc_state); + new_dm_plane_state->dc_state = dc_create_plane_state(dc); + + DRM_DEBUG_KMS("Enabling DRM plane: %d on DRM crtc %d\n", + plane->base.id, new_plane_crtc->base.id); + + if (!new_dm_plane_state->dc_state) { + ret = -EINVAL; + return ret; + } + + ret = fill_plane_attributes( + new_plane_crtc->dev->dev_private, + new_dm_plane_state->dc_state, + new_plane_state, + new_crtc_state, + false); + if (ret) + return ret; + + + if (!dc_add_plane_to_context( + dc, + new_acrtc_state->stream, + new_dm_plane_state->dc_state, + dm_state->context)) { + + ret = -EINVAL; + return ret; } + + *lock_and_validation_needed = true; } + } - /* - * Hack: Commit needs planes right now, specifically for gamma - * TODO rework commit to check CRTC for gamma change - */ - if (crtc_state->color_mgmt_changed) { + return ret; +} + +int amdgpu_dm_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state) +{ + int i; + int ret; + struct amdgpu_device *adev = dev->dev_private; + struct dc *dc = adev->dm.dc; + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + struct drm_connector *connector; + struct drm_connector_state *conn_state; + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + /* + * This bool will be set for true for any modeset/reset + * or plane update which implies non fast surface update. + */ + bool lock_and_validation_needed = false; + + ret = drm_atomic_helper_check_modeset(dev, state); + + if (ret) { + DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); + return ret; + } + + /* + * Hack: Commit needs planes right now, specifically for gamma + * TODO rework commit to check CRTC for gamma change + */ + for_each_crtc_in_state(state, crtc, crtc_state, i) { + if (crtc_state->color_mgmt_changed) { ret = drm_atomic_add_affected_planes(state, crtc); if (ret) goto fail; } } + dm_state->context = dc_create_state(); + ASSERT(dm_state->context); + dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); + + /* Remove exiting planes if they are modified */ + ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); + if (ret) { + goto fail; + } + + /* Disable all crtcs which require disable */ + ret = dm_update_crtcs_state(dc, state, false, &lock_and_validation_needed); + if (ret) { + goto fail; + } + + /* Enable all crtcs which require enable */ + ret = dm_update_crtcs_state(dc, state, true, &lock_and_validation_needed); + if (ret) { + goto fail; + } + + /* Add new/modified planes */ + ret = dm_update_planes_state(dc, state, true, &lock_and_validation_needed); + if (ret) { + goto fail; + } + + /* Run this here since we want to validate the streams we created */ + ret = drm_atomic_helper_check_planes(dev, state); + if (ret) + goto fail; + /* Check scaling and undersacn changes*/ /*TODO Removed scaling changes validation due to inability to commit * new stream into context w\o causing full reset. Need to @@ -4583,66 +4703,6 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } - /* Add new planes */ - for_each_crtc_in_state(state, crtc, crtc_state, i) { - new_acrtc_state = to_dm_crtc_state(crtc_state); - - if (pflip_needed) - continue; - - for_each_plane_in_state(state, plane, plane_state, j) { - struct drm_crtc *plane_crtc = plane_state->crtc; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); - - /*TODO Implement atomic check for cursor plane */ - if (plane->type == DRM_PLANE_TYPE_CURSOR) - continue; - - if (crtc != plane_crtc) - continue; - - if (!drm_atomic_plane_disabling(plane->state, plane_state)) { - struct dc_plane_state *dc_plane_state; - - WARN_ON(!new_acrtc_state->stream); - - dc_plane_state = dc_create_plane_state(dc); - - WARN_ON(dm_plane_state->dc_state); - - dm_plane_state->dc_state = dc_plane_state; - - ret = fill_plane_attributes( - plane_crtc->dev->dev_private, - dc_plane_state, - plane_state, - crtc_state, - false); - if (ret) - goto fail; - - - if (!dc_add_plane_to_context( - dc, - new_acrtc_state->stream, - dc_plane_state, - dm_state->context)) { - - ret = EINVAL; - goto fail; - } - - - lock_and_validation_needed = true; - } - } - } - - /* Run this here since we want to validate the streams we created */ - ret = drm_atomic_helper_check_planes(dev, state); - if (ret) - goto fail; - /* * For full updates case when * removing/adding/updating streams on once CRTC while flipping @@ -4675,7 +4735,7 @@ fail: else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n"); else - DRM_ERROR("Atomic check failed with err: %d .\n", ret); + DRM_ERROR("Atomic check failed with err: %d \n", ret); return ret; } -- cgit v1.2.3 From 9635b75436e5f536831c810c715f3ae24a5bbbae Mon Sep 17 00:00:00 2001 From: Darren Salt Date: Tue, 12 Sep 2017 17:10:25 +0100 Subject: drm/amd/display: Don't leak dc_stream_state. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Noticed while playing “Valley”, which was causing some 8MB of leakage per second. kmemleak listed many entries looking like this: unreferenced object 0xffff8802c2951800 (size 1024): comm "Xorg", pid 2982, jiffies 4297410155 (age 392.787s) hex dump (first 32 bytes): 00 50 f9 0c 04 88 ff ff 98 08 00 00 00 00 00 00 .P.............. 80 07 00 00 00 00 00 00 58 00 00 00 2c 00 00 00 ........X...,... backtrace: [] create_object+0x13c/0x261 [] kmemleak_alloc+0x20/0x3c [] slab_post_alloc_hook+0x42/0x52 [] kmem_cache_alloc+0x67/0x76 [] dc_create_stream_for_sink+0x24/0x1cf [] create_stream_for_sink+0x6f/0x295 [] dm_update_crtcs_state+0xa6/0x268 [] amdgpu_dm_atomic_check+0x9a/0x314 [] drm_atomic_check_only+0x17a/0x42d [] drm_atomic_commit+0x13/0x4b [] drm_atomic_connector_commit_dpms+0xcb/0xe8 [] drm_mode_obj_set_property_ioctl+0xe6/0x1e3 [] drm_mode_connector_property_set_ioctl+0x2b/0x2d [] drm_ioctl_kernel+0x64/0x9d [] drm_ioctl+0x230/0x316 [] amdgpu_drm_ioctl+0x4b/0x7d v2: also handle break statements. Signed-off-by: Darren Salt Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 193a634f46e6..4f1e31cd4cbe 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4357,6 +4357,7 @@ static int dm_update_crtcs_state( int i; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + struct dc_stream_state *new_stream; int ret = 0; /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ @@ -4364,10 +4365,11 @@ static int dm_update_crtcs_state( for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_connector *aconnector = NULL; - struct dc_stream_state *new_stream = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_conn_state = NULL; + new_stream = NULL; + old_acrtc_state = to_dm_crtc_state(crtc->state); new_acrtc_state = to_dm_crtc_state(crtc_state); acrtc = to_amdgpu_crtc(crtc); @@ -4415,7 +4417,7 @@ static int dm_update_crtcs_state( if (!drm_atomic_crtc_needs_modeset(crtc_state)) - continue; + goto next_crtc; DRM_DEBUG_KMS( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " @@ -4433,7 +4435,7 @@ static int dm_update_crtcs_state( if (!enable) { if (!old_acrtc_state->stream) - continue; + goto next_crtc; DRM_DEBUG_KMS("Disabling DRM crtc: %d\n", crtc->base.id); @@ -4444,7 +4446,7 @@ static int dm_update_crtcs_state( dm_state->context, old_acrtc_state->stream)) { ret = -EINVAL; - break; + goto fail; } dc_stream_release(old_acrtc_state->stream); @@ -4455,7 +4457,7 @@ static int dm_update_crtcs_state( } else {/* Add stream for any updated/enabled CRTC */ if (modereset_required(crtc_state)) - continue; + goto next_crtc; if (modeset_required(crtc_state, new_stream, old_acrtc_state->stream)) { @@ -4473,19 +4475,25 @@ static int dm_update_crtcs_state( dm_state->context, new_acrtc_state->stream)) { ret = -EINVAL; - break; + goto fail; } *lock_and_validation_needed = true; } } +next_crtc: /* Release extra reference */ if (new_stream) dc_stream_release(new_stream); } return ret; + +fail: + if (new_stream) + dc_stream_release(new_stream); + return ret; } static int dm_update_planes_state( -- cgit v1.2.3 From aac6a07e40dea7996851c81f9a5f0e433b806086 Mon Sep 17 00:00:00 2001 From: Andrey Grodzovsky Date: Wed, 23 Aug 2017 16:54:03 -0400 Subject: drm/amd/display: Use DRM provided page flip flag. Starting with 4.12 kernel DRM provides page flip flags so we don't need to have our own copy. Signed-off-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4f1e31cd4cbe..9c44b82036fa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3767,7 +3767,7 @@ static void amdgpu_dm_do_flip( struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); struct amdgpu_bo *abo = gem_to_amdgpu_bo(afb->obj); struct amdgpu_device *adev = crtc->dev->dev_private; - bool async_flip = (acrtc->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + bool async_flip = (crtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; struct dc_flip_addrs addr = { {0} }; /* TODO eliminate or rename surface_update */ struct dc_surface_update surface_updates[1] = { {0} }; @@ -3899,7 +3899,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * TODO Check if it's correct */ *wait_for_vblank = - acrtc_attach->flip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? + pcrtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? false : true; /* TODO: Needs rework for multiplane flip */ @@ -3910,11 +3910,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, crtc, fb, drm_crtc_vblank_count(crtc) + *wait_for_vblank); - - /*TODO BUG remove ASAP in 4.12 to avoid race between worker and flip IOCTL */ - - /*clean up the flags for next usage*/ - acrtc_attach->flip_flags = 0; } } -- cgit v1.2.3 From 608ac7bb3924178d7bfa8b88d79d3d9d72b8f485 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 25 Aug 2017 16:16:10 -0400 Subject: drm/amd/display: Rename dc validate_context and current_context MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename all the dc validate_context to dc_state and dc current_context to current_state. Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 108 ++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 +- drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 40 ++++---- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 15 ++- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 4 +- drivers/gpu/drm/amd/display/dc/dc.h | 38 ++++---- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 4 +- .../amd/display/dc/dce100/dce100_hw_sequencer.c | 8 +- .../amd/display/dc/dce100/dce100_hw_sequencer.h | 4 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 10 +- .../amd/display/dc/dce110/dce110_hw_sequencer.c | 70 ++++++------- .../amd/display/dc/dce110/dce110_hw_sequencer.h | 12 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 16 +-- .../drm/amd/display/dc/dce112/dce112_resource.h | 10 +- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 10 +- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 62 ++++++------ .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 8 +- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h | 2 +- drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h | 4 +- drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h | 14 +-- drivers/gpu/drm/amd/display/dc/inc/resource.h | 22 ++--- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 2 +- .../gpu/drm/amd/display/include/logger_interface.h | 4 +- 32 files changed, 263 insertions(+), 264 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c44b82036fa..9b018115d97e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -711,7 +711,7 @@ dm_atomic_state_clear(struct drm_atomic_state *state) struct dm_atomic_state *dm_state = to_dm_atomic_state(state); if (dm_state->context) { - dc_release_validate_context(dm_state->context); + dc_release_state(dm_state->context); dm_state->context = NULL; } @@ -4098,7 +4098,7 @@ void amdgpu_dm_atomic_commit_tail( } if (dm_state->context) - WARN_ON(!dc_commit_context(dm->dc, dm_state->context)); + WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index e0a5632f00a3..71cbee199016 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -209,7 +209,7 @@ struct dm_crtc_state { struct dm_atomic_state { struct drm_atomic_state base; - struct validate_context *context; + struct dc_state *context; }; #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 6c85a54e47d6..ee1b76c074e6 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -476,7 +476,7 @@ static void dcn_bw_calc_rq_dlg_ttu( static void dcn_dml_wm_override( const struct dcn_bw_internal_vars *v, struct display_mode_lib *dml, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool) { int i, in_idx, active_count; @@ -593,7 +593,7 @@ static void split_stream_across_pipes( } static void calc_wm_sets_and_perf_params( - struct validate_context *context, + struct dc_state *context, struct dcn_bw_internal_vars *v) { /* Calculate set A last to keep internal var state consistent for required config */ @@ -721,7 +721,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc) bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { const struct resource_pool *pool = dc->res_pool; struct dcn_bw_internal_vars *v = &context->dcn_bw_vars; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a20dc24db0d5..53f814dcc24d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -160,7 +160,7 @@ static bool stream_adjust_vmin_vmax(struct dc *dc, bool ret = false; for (i = 0; i < MAX_PIPES; i++) { - struct pipe_ctx *pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.set_drr(&pipe, 1, vmin, vmax); @@ -187,7 +187,7 @@ static bool stream_get_crtc_position(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (pipe->stream == stream && pipe->stream_res.stream_enc) { dc->hwss.get_position(&pipe, 1, &position); @@ -207,8 +207,8 @@ static bool set_gamut_remap(struct dc *dc, const struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_gamut_remap(pipes); ret = true; } @@ -224,10 +224,10 @@ static bool program_csc_matrix(struct dc *dc, struct dc_stream_state *stream) struct pipe_ctx *pipes; for (i = 0; i < MAX_PIPES; i++) { - if (dc->current_context->res_ctx.pipe_ctx[i].stream + if (dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { - pipes = &dc->current_context->res_ctx.pipe_ctx[i]; + pipes = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.program_csc_matrix(pipes, stream->output_color_space, stream->csc_color_matrix.matrix); @@ -252,10 +252,10 @@ static void set_static_screen_events(struct dc *dc, struct dc_stream_state *stream = streams[i]; for (j = 0; j < MAX_PIPES; j++) { - if (dc->current_context->res_ctx.pipe_ctx[j].stream + if (dc->current_state->res_ctx.pipe_ctx[j].stream == stream) { pipes_affected[num_pipes_affected++] = - &dc->current_context->res_ctx.pipe_ctx[j]; + &dc->current_state->res_ctx.pipe_ctx[j]; } } } @@ -334,7 +334,7 @@ void set_dither_option(struct dc_stream_state *stream, { struct bit_depth_reduction_params params; struct dc_link *link = stream->status.link; - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; memset(¶ms, 0, sizeof(params)); if (!stream) @@ -408,8 +408,8 @@ static void allocate_dc_stream_funcs(struct dc *dc) static void destruct(struct dc *dc) { - dc_release_validate_context(dc->current_context); - dc->current_context = NULL; + dc_release_state(dc->current_state); + dc->current_state = NULL; destroy_links(dc); @@ -494,9 +494,9 @@ static bool construct(struct dc *dc, goto fail; } - dc->current_context = dc_create_state(); + dc->current_state = dc_create_state(); - if (!dc->current_context) { + if (!dc->current_state) { dm_error("%s: failed to create validate ctx\n", __func__); goto fail; } @@ -668,12 +668,12 @@ bool dc_validate_guaranteed( struct dc_stream_state *stream) { enum dc_status result = DC_ERROR_UNEXPECTED; - struct validate_context *context; + struct dc_state *context; if (!dc_validate_stream(dc, stream)) return false; - context = dm_alloc(sizeof(struct validate_context)); + context = dm_alloc(sizeof(struct dc_state)); if (context == NULL) goto context_alloc_fail; @@ -682,7 +682,7 @@ bool dc_validate_guaranteed( result = dc->res_pool->funcs->validate_guaranteed( dc, stream, context); - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: if (result != DC_OK) { @@ -697,7 +697,7 @@ context_alloc_fail: static void program_timing_sync( struct dc *dc, - struct validate_context *ctx) + struct dc_state *ctx) { int i, j; int group_index = 0; @@ -771,15 +771,15 @@ static void program_timing_sync( static bool context_changed( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i; - if (context->stream_count != dc->current_context->stream_count) + if (context->stream_count != dc->current_state->stream_count) return true; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (dc->current_context->streams[i] != context->streams[i]) + for (i = 0; i < dc->current_state->stream_count; i++) { + if (dc->current_state->streams[i] != context->streams[i]) return true; } @@ -788,7 +788,7 @@ static bool context_changed( bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count) { @@ -800,7 +800,7 @@ bool dc_enable_stereo( if (context != NULL) pipe = &context->res_ctx.pipe_ctx[i]; else - pipe = &dc->current_context->res_ctx.pipe_ctx[i]; + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; for (j = 0 ; pipe && j < stream_count; j++) { if (streams[j] && streams[j] == pipe->stream && dc->hwss.setup_stereo) @@ -816,7 +816,7 @@ bool dc_enable_stereo( * Applies given context to HW and copy it into current context. * It's up to the user to release the src context afterwards. */ -static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *context) +static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -875,18 +875,18 @@ static bool dc_commit_context_no_check(struct dc *dc, struct validate_context *c dc_enable_stereo(dc, context, dc_streams, context->stream_count); - dc_release_validate_context(dc->current_context); + dc_release_state(dc->current_state); - dc->current_context = context; + dc->current_state = context; - dc_retain_validate_context(dc->current_context); + dc_retain_state(dc->current_state); dc->hwss.optimize_shared_resources(dc); return (result == DC_OK); } -bool dc_commit_context(struct dc *dc, struct validate_context *context) +bool dc_commit_state(struct dc *dc, struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; int i; @@ -905,7 +905,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) LOG_DC); } - result = dc_commit_context_no_check(dc, context); + result = dc_commit_state_no_check(dc, context); return (result == DC_OK); } @@ -914,7 +914,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context) bool dc_post_update_surfaces_to_stream(struct dc *dc) { int i; - struct validate_context *context = dc->current_context; + struct dc_state *context = dc->current_state; post_surface_trace(dc); @@ -999,9 +999,9 @@ bool dc_commit_planes_to_stream( return true; } -struct validate_context *dc_create_state(void) +struct dc_state *dc_create_state(void) { - struct validate_context *context = dm_alloc(sizeof(struct validate_context)); + struct dc_state *context = dm_alloc(sizeof(struct dc_state)); if (!context) return NULL; @@ -1010,13 +1010,13 @@ struct validate_context *dc_create_state(void) return context; } -void dc_retain_validate_context(struct validate_context *context) +void dc_retain_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_inc(&context->ref_count); } -void dc_release_validate_context(struct validate_context *context) +void dc_release_state(struct dc_state *context) { ASSERT(atomic_read(&context->ref_count) > 0); atomic_dec(&context->ref_count); @@ -1028,7 +1028,7 @@ void dc_release_validate_context(struct validate_context *context) } static bool is_surface_in_context( - const struct validate_context *context, + const struct dc_state *context, const struct dc_plane_state *plane_state) { int j; @@ -1145,7 +1145,7 @@ static enum surface_update_type det_surface_update( const struct dc_surface_update *u, int surface_index) { - const struct validate_context *context = dc->current_context; + const struct dc_state *context = dc->current_state; enum surface_update_type type = UPDATE_TYPE_FAST; enum surface_update_type overall_type = UPDATE_TYPE_FAST; @@ -1200,7 +1200,7 @@ enum surface_update_type dc_check_update_surfaces_for_stream( } static struct dc_stream_status *stream_get_status( - struct validate_context *ctx, + struct dc_state *ctx, struct dc_stream_state *stream) { uint8_t i; @@ -1221,7 +1221,7 @@ void dc_update_planes_and_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { - struct validate_context *context; + struct dc_state *context; int i, j; enum surface_update_type update_type; const struct dc_stream_status *stream_status; @@ -1239,7 +1239,7 @@ void dc_update_planes_and_stream(struct dc *dc, ASSERT(0); } #endif - context = dc->current_context; + context = dc->current_state; /* update current stream with the new updates */ if (stream_update) { @@ -1293,7 +1293,7 @@ void dc_update_planes_and_stream(struct dc *dc, goto context_alloc_fail; dc_resource_validate_ctx_copy_construct( - dc->current_context, context); + dc->current_state, context); /*remove old surfaces from context */ if (!dc_rem_all_planes_for_stream(dc, stream, context)) { @@ -1437,7 +1437,7 @@ void dc_update_planes_and_stream(struct dc *dc, /* Full fe update*/ for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[j]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j]; bool is_new_pipe_surface = cur_pipe_ctx->plane_state != pipe_ctx->plane_state; struct dc_cursor_position position = { 0 }; @@ -1524,7 +1524,7 @@ void dc_update_planes_and_stream(struct dc *dc, } } - if (dc->current_context != context) { + if (dc->current_state != context) { /* Since memory free requires elevated IRQL, an interrupt * request is generated by mem free. If this happens @@ -1534,16 +1534,16 @@ void dc_update_planes_and_stream(struct dc *dc, * then free the old context. */ - struct validate_context *old = dc->current_context; + struct dc_state *old = dc->current_state; - dc->current_context = context; - dc_release_validate_context(old); + dc->current_state = context; + dc_release_state(old); } return; fail: - dc_release_validate_context(context); + dc_release_state(context); context_alloc_fail: DC_ERROR("Failed to allocate new validate context!\n"); @@ -1551,13 +1551,13 @@ context_alloc_fail: uint8_t dc_get_current_stream_count(struct dc *dc) { - return dc->current_context->stream_count; + return dc->current_state->stream_count; } struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i) { - if (i < dc->current_context->stream_count) - return dc->current_context->streams[i]; + if (i < dc->current_state->stream_count) + return dc->current_state->streams[i]; return NULL; } @@ -1634,11 +1634,11 @@ void dc_set_power_state( */ /* Preserve refcount */ - ref_count = dc->current_context->ref_count; - dc_resource_validate_ctx_destruct(dc->current_context); - memset(dc->current_context, 0, - sizeof(*dc->current_context)); - dc->current_context->ref_count = ref_count; + ref_count = dc->current_state->ref_count; + dc_resource_validate_ctx_destruct(dc->current_state); + memset(dc->current_state, 0, + sizeof(*dc->current_state)); + dc->current_state->ref_count = ref_count; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index d74eed8f9b96..6acee5426e4b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -329,7 +329,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { #if defined(CONFIG_DRM_AMD_DC_DCN1_0) struct dc *core_dc = dc; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 0bdd41ca8799..65e12614d96c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1819,14 +1819,14 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level, if (dc_is_embedded_signal(link->connector_signal)) { if (stream != NULL) { for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx. + if (core_dc->current_state->res_ctx. pipe_ctx[i].stream == stream) /* DMCU -1 for all controller id values, * therefore +1 here */ controller_id = - core_dc->current_context-> + core_dc->current_state-> res_ctx.pipe_ctx[i].stream_res.tg->inst + 1; } @@ -1926,13 +1926,13 @@ bool dc_link_setup_psr(struct dc_link *link, psr_context->engineId = link->link_enc->preferred_engine; for (i = 0; i < MAX_PIPES; i++) { - if (core_dc->current_context->res_ctx.pipe_ctx[i].stream + if (core_dc->current_state->res_ctx.pipe_ctx[i].stream == stream) { /* dmcu -1 for all controller id values, * therefore +1 here */ psr_context->controllerId = - core_dc->current_context->res_ctx. + core_dc->current_state->res_ctx. pipe_ctx[i].stream_res.tg->inst + 1; break; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 446e2933474c..5f2b52e41427 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2406,7 +2406,7 @@ bool dc_link_dp_set_test_pattern( const unsigned char *p_custom_pattern, unsigned int cust_pattern_size) { - struct pipe_ctx *pipes = link->dc->current_context->res_ctx.pipe_ctx; + struct pipe_ctx *pipes = link->dc->current_state->res_ctx.pipe_ctx; struct pipe_ctx *pipe_ctx = &pipes[0]; unsigned int lane; unsigned int i; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c index 23d8b614e0fd..3427fb5b7e30 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c @@ -62,7 +62,7 @@ void dp_enable_link_phy( struct link_encoder *link_enc = link->link_enc; struct pipe_ctx *pipes = - link->dc->current_context->res_ctx.pipe_ctx; + link->dc->current_state->res_ctx.pipe_ctx; struct clock_source *dp_cs = link->dc->res_pool->dp_clock_source; unsigned int i; @@ -262,7 +262,7 @@ void dp_retrain_link_dp_test(struct dc_link *link, bool skip_video_pattern) { struct pipe_ctx *pipes = - &link->dc->current_context->res_ctx.pipe_ctx[0]; + &link->dc->current_state->res_ctx.pipe_ctx[0]; unsigned int i; for (i = 0; i < MAX_PIPES; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 9eb8d48bc889..727afeaa3830 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -893,7 +893,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -971,7 +971,7 @@ static struct pipe_ctx *resource_get_tail_pipe_for_stream( * that has no surface attached yet */ static struct pipe_ctx *acquire_free_pipe_for_stream( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -1048,7 +1048,7 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct resource_pool *pool = dc->res_pool; @@ -1124,7 +1124,7 @@ bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context) + struct dc_state *context) { int i; struct dc_stream_status *stream_status = NULL; @@ -1199,7 +1199,7 @@ bool dc_remove_plane_from_context( bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { int i, old_plane_count; struct dc_stream_status *stream_status = NULL; @@ -1233,7 +1233,7 @@ static bool add_all_planes_for_stream( struct dc_stream_state *stream, const struct dc_validation_set set[], int set_count, - struct validate_context *context) + struct dc_state *context) { int i, j; @@ -1258,7 +1258,7 @@ bool dc_add_all_planes_for_stream( struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context) + struct dc_state *context) { struct dc_validation_set set; int i; @@ -1434,7 +1434,7 @@ static struct audio *find_first_free_audio( } bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream) + struct dc_state *old_context, struct dc_stream_state *stream) { int i; @@ -1450,7 +1450,7 @@ bool resource_is_stream_unchanged( bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { struct dc_context *dc_ctx = dc->ctx; @@ -1474,7 +1474,7 @@ bool dc_add_stream_to_ctx( bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream) { int i; @@ -1553,7 +1553,7 @@ static void copy_pipe_ctx( static struct dc_stream_state *find_pll_sharable_stream( struct dc_stream_state *stream_needs_pll, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1615,7 +1615,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream) enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { const struct resource_pool *pool = dc->res_pool; @@ -1689,7 +1689,7 @@ enum dc_status resource_map_pool_resources( /* first stream in the context is used to populate the rest */ void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams) { int i; @@ -1709,14 +1709,14 @@ void validate_guaranteed_copy_streams( void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx) + struct dc_state *dst_ctx) { - dc_resource_validate_ctx_copy_construct(dc->current_context, dst_ctx); + dc_resource_validate_ctx_copy_construct(dc->current_state, dst_ctx); } bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx) + struct dc_state *new_ctx) { enum dc_status result = DC_ERROR_UNEXPECTED; int i, j; @@ -2413,7 +2413,7 @@ static void set_vsc_info_packet( /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ } -void dc_resource_validate_ctx_destruct(struct validate_context *context) +void dc_resource_validate_ctx_destruct(struct dc_state *context) { int i, j; @@ -2433,8 +2433,8 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context) * by the src_ctx */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx) + const struct dc_state *src_ctx, + struct dc_state *dst_ctx) { int i, j; atomic_t ref_count = dst_ctx->ref_count; @@ -2518,7 +2518,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx) enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { /* acquire new resources */ diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 0e7cc293184e..a421779093d9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -169,10 +169,9 @@ struct dc_stream_status *dc_stream_get_status( uint8_t i; struct dc *dc = stream->ctx->dc; - for (i = 0; i < dc->current_context->stream_count; i++) { - if (stream == dc->current_context->streams[i]) { - return &dc->current_context->stream_status[i]; - } + for (i = 0; i < dc->current_state->stream_count; i++) { + if (stream == dc->current_state->streams[i]) + return &dc->current_state->stream_status[i]; } return NULL; @@ -199,7 +198,7 @@ bool dc_stream_set_cursor_attributes( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -235,7 +234,7 @@ bool dc_stream_set_cursor_position( } core_dc = stream->ctx->dc; - res_ctx = &core_dc->current_context->res_ctx; + res_ctx = &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx = &res_ctx->pipe_ctx[i]; @@ -271,7 +270,7 @@ uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream) uint8_t i; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; @@ -295,7 +294,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool ret = false; struct dc *core_dc = stream->ctx->dc; struct resource_context *res_ctx = - &core_dc->current_context->res_ctx; + &core_dc->current_state->res_ctx; for (i = 0; i < MAX_PIPES; i++) { struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index 0b6410fb2f3e..e96f63eed070 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -104,12 +104,12 @@ const struct dc_plane_status *dc_plane_get_status( plane_status = &plane_state->status; core_dc = plane_state->ctx->dc; - if (core_dc->current_context == NULL) + if (core_dc->current_state == NULL) return NULL; for (i = 0; i < core_dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = - &core_dc->current_context->res_ctx.pipe_ctx[i]; + &core_dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->plane_state != plane_state) continue; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 55fc58102515..d1d5737398df 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -99,7 +99,7 @@ struct dc_static_screen_events { /* Forward declaration*/ struct dc; struct dc_plane_state; -struct validate_context; +struct dc_state; struct dc_cap_funcs { bool (*get_dcc_compression_cap)(const struct dc *dc, @@ -192,7 +192,7 @@ struct dc_debug { bool disable_psr; bool force_abm_enable; }; -struct validate_context; +struct dc_state; struct resource_pool; struct dce_hwseq; struct dc { @@ -208,7 +208,7 @@ struct dc { uint8_t link_count; struct dc_link *links[MAX_PIPES * 2]; - struct validate_context *current_context; + struct dc_state *current_state; struct resource_pool *res_pool; /* Display Engine Clock levels */ @@ -621,12 +621,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, bool dc_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); bool dc_remove_stream_from_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *stream); @@ -634,25 +634,25 @@ bool dc_add_plane_to_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_remove_plane_from_context( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state *plane_state, - struct validate_context *context); + struct dc_state *context); bool dc_rem_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool dc_add_all_planes_for_stream( const struct dc *dc, struct dc_stream_state *stream, struct dc_plane_state * const *plane_states, int plane_count, - struct validate_context *context); + struct dc_state *context); /* * Structure to store surface/stream associations for validation @@ -669,7 +669,7 @@ bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); bool dc_validate_global_state( struct dc *dc, - struct validate_context *new_ctx); + struct dc_state *new_ctx); /* * This function takes a stream and checks if it is guaranteed to be supported. @@ -680,14 +680,14 @@ bool dc_validate_global_state( */ void dc_resource_validate_ctx_copy_construct( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); void dc_resource_validate_ctx_copy_construct_current( const struct dc *dc, - struct validate_context *dst_ctx); + struct dc_state *dst_ctx); -void dc_resource_validate_ctx_destruct(struct validate_context *context); +void dc_resource_validate_ctx_destruct(struct dc_state *context); /* * TODO update to make it about validation sets @@ -698,7 +698,7 @@ void dc_resource_validate_ctx_destruct(struct validate_context *context); * Phy, Encoder, Timing Generator are programmed and enabled. * New streams are enabled with blank stream; no memory read. */ -bool dc_commit_context(struct dc *dc, struct validate_context *context); +bool dc_commit_state(struct dc *dc, struct dc_state *context); /* * Set up streams and links associated to drive sinks @@ -714,7 +714,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context); */ bool dc_enable_stereo( struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *streams[], uint8_t stream_count); @@ -737,9 +737,9 @@ enum surface_update_type dc_check_update_surfaces_for_stream( const struct dc_stream_status *stream_status); -struct validate_context *dc_create_state(void); -void dc_retain_validate_context(struct validate_context *context); -void dc_release_validate_context(struct validate_context *context); +struct dc_state *dc_create_state(void); +void dc_retain_state(struct dc_state *context); +void dc_release_state(struct dc_state *context); /******************************************************************************* * Link Interfaces diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 0654fe34627c..d3b61b92ebec 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -609,7 +609,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ @@ -624,7 +624,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll( { uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; struct dc *dc_core = cs->ctx->dc; - struct validate_context *context = dc_core->current_context; + struct dc_state *context = dc_core->current_state; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst]; /* This function need separate to different DCE version, before separate, just use pixel clock */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c index b7e51c5ed1b1..492ea6069eb4 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c @@ -107,7 +107,7 @@ static bool dce100_enable_display_power_gating( static void dce100_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -127,14 +127,14 @@ static void dce100_pplib_apply_display_requirements( void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } dce100_pplib_apply_display_requirements(dc, context); } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h index c04aa15cd656..770b5bb1ff40 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h @@ -29,13 +29,13 @@ #include "core_types.h" struct dc; -struct validate_context; +struct dc_state; bool dce100_hw_sequencer_construct(struct dc *dc); void dce100_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); #endif /* __DC_HWSS_DCE100_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index c991610315b2..36d79175354c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -653,7 +653,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -674,7 +674,7 @@ static enum dc_status build_mapped_resource( bool dce100_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -684,7 +684,7 @@ bool dce100_validate_bandwidth( } static bool dce100_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -705,7 +705,7 @@ static bool dce100_validate_surface_sets( enum dc_status dce100_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce100_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -716,7 +716,7 @@ enum dc_status dce100_validate_global( enum dc_status dce100_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c index 3502faa1458f..1c6e2006f2a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c @@ -976,11 +976,11 @@ static void program_scaler(const struct dc *dc, static enum dc_status dce110_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; struct tg_color black_color = {0}; @@ -1032,11 +1032,11 @@ static enum dc_status dce110_prog_pixclk_crtc_otg( static enum dc_status apply_single_controller_ctx_to_hw( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; - struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx. + struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. pipe_ctx[pipe_ctx->pipe_idx]; /* */ @@ -1257,7 +1257,7 @@ static uint32_t compute_pstate_blackout_duration( void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context) + struct dc_state *context) { uint8_t i, num_pipes; unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; @@ -1415,7 +1415,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx, */ static uint32_t get_max_pixel_clock_for_all_paths( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool pre_mode_set) { uint32_t max_pix_clk = 0; @@ -1456,7 +1456,7 @@ static uint32_t get_max_pixel_clock_for_all_paths( */ static void apply_min_clocks( struct dc *dc, - struct validate_context *context, + struct dc_state *context, enum dm_pp_clocks_state *clocks_state, bool pre_mode_set) { @@ -1545,7 +1545,7 @@ static void apply_min_clocks( * Check if FBC can be enabled */ static enum dc_status validate_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[0]; @@ -1575,7 +1575,7 @@ static enum dc_status validate_fbc(struct dc *dc, * Enable FBC */ static enum dc_status enable_fbc(struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = validate_fbc(dc, context); @@ -1604,14 +1604,14 @@ static enum dc_status enable_fbc(struct dc *dc, static enum dc_status apply_ctx_to_hw_fpga( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { enum dc_status status = DC_ERROR_UNEXPECTED; int i; for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -1634,7 +1634,7 @@ static enum dc_status apply_ctx_to_hw_fpga( static void dce110_reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1642,7 +1642,7 @@ static void dce110_reset_hw_ctx_wrap( /* look up the targets that have been removed since last commit */ for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /* Note: We need to disable output if clock sources change, @@ -1664,9 +1664,9 @@ static void dce110_reset_hw_ctx_wrap( } pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); pipe_ctx_old->plane_res.mi->funcs->free_mem_input( - pipe_ctx_old->plane_res.mi, dc->current_context->stream_count); + pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); resource_unreference_clock_source( - &dc->current_context->res_ctx, dc->res_pool, + &dc->current_state->res_ctx, dc->res_pool, &pipe_ctx_old->clock_source); dc->hwss.power_down_front_end(dc, pipe_ctx_old->pipe_idx); @@ -1679,7 +1679,7 @@ static void dce110_reset_hw_ctx_wrap( enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; @@ -1705,7 +1705,7 @@ enum dc_status dce110_apply_ctx_to_hw( /* below is for real asic only */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) @@ -1735,31 +1735,31 @@ enum dc_status dce110_apply_ctx_to_hw( #if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (dc->ctx->dce_version >= DCN_VERSION_1_0) { if (context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_FCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.fclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.fclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { struct dm_pp_clock_for_voltage_req clock; clock.clk_type = DM_PP_CLOCK_TYPE_DCFCLK; clock.clocks_in_khz = context->bw.dcn.calc_clk.dcfclk_khz; dm_pp_apply_clock_for_voltage_request(dc->ctx, &clock); - dc->current_context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; + dc->current_state->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; context->bw.dcn.cur_clk.dcfclk_khz = clock.clocks_in_khz; } if (context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; context->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; @@ -1767,7 +1767,7 @@ enum dc_status dce110_apply_ctx_to_hw( } else #endif if (context->bw.dce.dispclk_khz - > dc->current_context->bw.dce.dispclk_khz) { + > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); @@ -1848,7 +1848,7 @@ enum dc_status dce110_apply_ctx_to_hw( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream == NULL) @@ -2327,7 +2327,7 @@ static void init_hw(struct dc *dc) } void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg) { int j; @@ -2375,7 +2375,7 @@ void dce110_fill_display_configs( pp_display_cfg->display_count = num_cfgs; } -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context) +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) { uint8_t j; uint32_t min_vertical_blank_time = -1; @@ -2427,7 +2427,7 @@ static int determine_sclk_from_bounding_box( static void pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2481,16 +2481,16 @@ static void pplib_apply_display_requirements( static void dce110_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { dce110_set_displaymarks(dc, context); - if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_context->bw.dce.dispclk_khz) { + if (decrease_allowed || context->bw.dce.dispclk_khz > dc->current_state->bw.dce.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dce.dispclk_khz * 115 / 100); - dc->current_context->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; + dc->current_state->bw.dce.dispclk_khz = context->bw.dce.dispclk_khz; } pplib_apply_display_requirements(dc, context); @@ -2508,8 +2508,8 @@ static void dce110_program_front_end_for_pipe( memset(&tbl_entry, 0, sizeof(tbl_entry)); - if (dc->current_context) - old_pipe = &dc->current_context->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; + if (dc->current_state) + old_pipe = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx]; memset(&adjust, 0, sizeof(adjust)); adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -2627,7 +2627,7 @@ static void dce110_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2657,7 +2657,7 @@ static void dce110_apply_ctx_for_surface( static void dce110_power_down_fe(struct dc *dc, int fe_idx) { /* Do not power down fe when stream is active on dce*/ - if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream) + if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) return; dc->hwss.enable_display_power_gating( diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h index ac418fd83894..baa20c1f17ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.h @@ -30,20 +30,20 @@ #define GAMMA_HW_POINTS_NUM 256 struct dc; -struct validate_context; +struct dc_state; struct dm_pp_display_configuration; bool dce110_hw_sequencer_construct(struct dc *dc); enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, - struct validate_context *context); + struct dc_state *context); -void dce110_set_display_clock(struct validate_context *context); +void dce110_set_display_clock(struct dc_state *context); void dce110_set_displaymarks( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void dce110_enable_stream(struct pipe_ctx *pipe_ctx); @@ -62,10 +62,10 @@ void dce110_power_down(struct dc *dc); void dce110_update_pending_status(struct pipe_ctx *pipe_ctx); void dce110_fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); -uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context); +uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context); void dp_receiver_power_ctrl(struct dc_link *link, bool on); #endif /* __DC_HWSS_DCE110_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 18c67f89e9b5..94b6eb83e01e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -773,7 +773,7 @@ static bool is_surface_pixel_format_supported(struct pipe_ctx *pipe_ctx, unsigne static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -800,7 +800,7 @@ static enum dc_status build_mapped_resource( static bool dce110_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -826,7 +826,7 @@ static bool dce110_validate_bandwidth( context->streams[0]->timing.v_addressable, context->streams[0]->timing.pix_clk_khz); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -880,7 +880,7 @@ static bool dce110_validate_bandwidth( } static bool dce110_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -913,7 +913,7 @@ static bool dce110_validate_surface_sets( enum dc_status dce110_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce110_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -924,7 +924,7 @@ enum dc_status dce110_validate_global( static enum dc_status dce110_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -954,7 +954,7 @@ static enum dc_status dce110_validate_guaranteed( } static struct pipe_ctx *dce110_acquire_underlay( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { @@ -976,7 +976,7 @@ static struct pipe_ctx *dce110_acquire_underlay( pipe_ctx->stream = stream; - if (!dc->current_context->res_ctx.pipe_ctx[underlay_idx].stream) { + if (!dc->current_state->res_ctx.pipe_ctx[underlay_idx].stream) { struct tg_color black_color = {0}; struct dc_bios *dcb = dc->ctx->dc_bios; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index d5a8ee69171d..de6f71d8a89b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -724,7 +724,7 @@ static struct clock_source *find_matching_pll( static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -745,7 +745,7 @@ static enum dc_status build_mapped_resource( bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { bool result = false; @@ -768,7 +768,7 @@ bool dce112_validate_bandwidth( "%s: Bandwidth validation failed!", __func__); - if (memcmp(&dc->current_context->bw.dce, + if (memcmp(&dc->current_state->bw.dce, &context->bw.dce, sizeof(context->bw.dce))) { struct log_entry log_entry; dm_logger_open( @@ -823,7 +823,7 @@ bool dce112_validate_bandwidth( enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { @@ -855,7 +855,7 @@ enum dc_status resource_map_phy_clock_resources( } static bool dce112_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -876,7 +876,7 @@ static bool dce112_validate_surface_sets( enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -896,7 +896,7 @@ enum dc_status dce112_add_stream_to_ctx( enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -927,7 +927,7 @@ enum dc_status dce112_validate_guaranteed( enum dc_status dce112_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce112_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h index f1834bfe3d1e..d5c19d34eb0a 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h @@ -39,21 +39,21 @@ enum dc_status dce112_validate_with_context( struct dc *dc, const struct dc_validation_set set[], int set_count, - struct validate_context *context, - struct validate_context *old_context); + struct dc_state *context, + struct dc_state *old_context); enum dc_status dce112_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context); + struct dc_state *context); bool dce112_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status dce112_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 945ff7ee6cd9..316080767a21 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -685,7 +685,7 @@ static void destruct(struct dce110_resource_pool *pool) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -706,7 +706,7 @@ static enum dc_status build_mapped_resource( bool dce80_validate_bandwidth( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { /* TODO implement when needed but for now hardcode max value*/ context->bw.dce.dispclk_khz = 681000; @@ -716,7 +716,7 @@ bool dce80_validate_bandwidth( } static bool dce80_validate_surface_sets( - struct validate_context *context) + struct dc_state *context) { int i; @@ -737,7 +737,7 @@ static bool dce80_validate_surface_sets( enum dc_status dce80_validate_global( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { if (!dce80_validate_surface_sets(context)) return DC_FAIL_SURFACE_VALIDATE; @@ -748,7 +748,7 @@ enum dc_status dce80_validate_global( enum dc_status dce80_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 9c54cae28997..71ff1cedbdf4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -793,7 +793,7 @@ static void undo_DEGVIDCN10_253_wa(struct dc *dc) static void ready_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) undo_DEGVIDCN10_253_wa(dc); } @@ -815,7 +815,7 @@ static void apply_DEGVIDCN10_253_wa(struct dc *dc) static void optimize_shared_resources(struct dc *dc) { - if (dc->current_context->stream_count == 0 && + if (dc->current_state->stream_count == 0 && !dc->debug.disable_stutter) apply_DEGVIDCN10_253_wa(dc); } @@ -918,7 +918,7 @@ static void dcn10_init_hw(struct dc *dc) static enum dc_status dcn10_prog_pixclk_crtc_otg( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1008,7 +1008,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg( static void reset_back_end_for_pipe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { int i; @@ -1040,7 +1040,7 @@ static void reset_back_end_for_pipe( &pipe_ctx->clock_source); for (i = 0; i < dc->res_pool->pipe_count; i++) - if (&dc->current_context->res_ctx.pipe_ctx[i] == pipe_ctx) + if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) break; if (i == dc->res_pool->pipe_count) @@ -1206,14 +1206,14 @@ static void dcn10_power_down_fe(struct dc *dc, int fe_idx) static void reset_hw_ctx_wrap( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { int i; /* Reset Front End*/ /* Lock*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1222,7 +1222,7 @@ static void reset_hw_ctx_wrap( /* Disconnect*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx->stream || @@ -1234,7 +1234,7 @@ static void reset_hw_ctx_wrap( } /* Unlock*/ for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) { - struct pipe_ctx *cur_pipe_ctx = &dc->current_context->res_ctx.pipe_ctx[i]; + struct pipe_ctx *cur_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; struct timing_generator *tg = cur_pipe_ctx->stream_res.tg; if (cur_pipe_ctx->stream) @@ -1244,7 +1244,7 @@ static void reset_hw_ctx_wrap( /* Disable and Powerdown*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; /*if (!pipe_ctx_old->stream) @@ -1263,7 +1263,7 @@ static void reset_hw_ctx_wrap( /* Reset Back End*/ for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *pipe_ctx_old = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; if (!pipe_ctx_old->stream) @@ -1271,7 +1271,7 @@ static void reset_hw_ctx_wrap( if (!pipe_ctx->stream || pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) - reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_context); + reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); } } @@ -1943,7 +1943,7 @@ static void print_rq_dlg_ttu( static void dcn10_power_on_fe( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dce_hwseq *hws = dc->hwseq; @@ -2244,7 +2244,7 @@ static void dcn10_program_pte_vm(struct mem_input *mem_input, static void update_dchubp_dpp( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { struct dce_hwseq *hws = dc->hwseq; struct mem_input *mi = pipe_ctx->plane_res.mi; @@ -2263,7 +2263,7 @@ static void update_dchubp_dpp( pipe_ctx->pipe_idx, pipe_ctx->stream_res.pix_clk_params.requested_pix_clk, context->bw.dcn.calc_clk.dppclk_div); - dc->current_context->bw.dcn.cur_clk.dppclk_div = + dc->current_state->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; @@ -2350,7 +2350,7 @@ static void update_dchubp_dpp( static void program_all_pipe_in_tree( struct dc *dc, struct pipe_ctx *pipe_ctx, - struct validate_context *context) + struct dc_state *context) { unsigned int ref_clk_mhz = dc->res_pool->ref_clock_inKhz/1000; @@ -2408,7 +2408,7 @@ static void program_all_pipe_in_tree( static void dcn10_pplib_apply_display_requirements( struct dc *dc, - struct validate_context *context) + struct dc_state *context) { struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; @@ -2437,7 +2437,7 @@ static void dcn10_apply_ctx_for_surface( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context) + struct dc_state *context) { int i, be_idx; @@ -2457,7 +2457,7 @@ static void dcn10_apply_ctx_for_surface( if (num_planes == 0) { for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (old_pipe_ctx->stream_res.tg && old_pipe_ctx->stream_res.tg->inst == be_idx) { old_pipe_ctx->stream_res.tg->funcs->set_blank(old_pipe_ctx->stream_res.tg, true); @@ -2471,7 +2471,7 @@ static void dcn10_apply_ctx_for_surface( for (i = 0; i < dc->res_pool->pipe_count; i++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; struct pipe_ctx *old_pipe_ctx = - &dc->current_context->res_ctx.pipe_ctx[i]; + &dc->current_state->res_ctx.pipe_ctx[i]; if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) continue; @@ -2591,7 +2591,7 @@ static void dcn10_apply_ctx_for_surface( static void dcn10_set_bandwidth( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed) { struct pp_smu_display_requirement_rv *smu_req_cur = @@ -2607,25 +2607,25 @@ static void dcn10_set_bandwidth( return; if (decrease_allowed || context->bw.dcn.calc_clk.dispclk_khz - > dc->current_context->bw.dcn.cur_clk.dispclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dispclk_khz) { dc->res_pool->display_clock->funcs->set_clock( dc->res_pool->display_clock, context->bw.dcn.calc_clk.dispclk_khz); - dc->current_context->bw.dcn.cur_clk.dispclk_khz = + dc->current_state->bw.dcn.cur_clk.dispclk_khz = context->bw.dcn.calc_clk.dispclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_khz) { + > dc->current_state->bw.dcn.cur_clk.dcfclk_khz) { smu_req.hard_min_dcefclk_khz = context->bw.dcn.calc_clk.dcfclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.fclk_khz - > dc->current_context->bw.dcn.cur_clk.fclk_khz) { + > dc->current_state->bw.dcn.cur_clk.fclk_khz) { smu_req.hard_min_fclk_khz = context->bw.dcn.calc_clk.fclk_khz; } if (decrease_allowed || context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz - > dc->current_context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { - dc->current_context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = + > dc->current_state->bw.dcn.cur_clk.dcfclk_deep_sleep_khz) { + dc->current_state->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; context->bw.dcn.cur_clk.dcfclk_deep_sleep_khz = context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz; @@ -2640,15 +2640,15 @@ static void dcn10_set_bandwidth( /* Decrease in freq is increase in period so opposite comparison for dram_ccm */ if (decrease_allowed || context->bw.dcn.calc_clk.dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; context->bw.dcn.cur_clk.dram_ccm_us = context->bw.dcn.calc_clk.dram_ccm_us; } if (decrease_allowed || context->bw.dcn.calc_clk.min_active_dram_ccm_us - < dc->current_context->bw.dcn.cur_clk.min_active_dram_ccm_us) { - dc->current_context->bw.dcn.calc_clk.min_active_dram_ccm_us = + < dc->current_state->bw.dcn.cur_clk.min_active_dram_ccm_us) { + dc->current_state->bw.dcn.calc_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; context->bw.dcn.cur_clk.min_active_dram_ccm_us = context->bw.dcn.calc_clk.min_active_dram_ccm_us; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h index 8bb09de8dcd7..ca53dc1cc19b 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.h @@ -32,7 +32,7 @@ struct dc; void dcn10_hw_sequencer_construct(struct dc *dc); extern void fill_display_configs( - const struct validate_context *context, + const struct dc_state *context, struct dm_pp_display_configuration *pp_display_cfg); #endif /* __DC_HWSS_DCN10_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index d09ed13fb8ea..fff86ad0c411 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -850,7 +850,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx) static enum dc_status build_mapped_resource( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream) { enum dc_status status = DC_OK; @@ -887,7 +887,7 @@ static enum dc_status build_mapped_resource( enum dc_status dcn10_add_stream_to_ctx( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -907,7 +907,7 @@ enum dc_status dcn10_add_stream_to_ctx( enum dc_status dcn10_validate_guaranteed( struct dc *dc, struct dc_stream_state *dc_stream, - struct validate_context *context) + struct dc_state *context) { enum dc_status result = DC_ERROR_UNEXPECTED; @@ -935,7 +935,7 @@ enum dc_status dcn10_validate_guaranteed( } static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index bd1a6367872f..71eb9859faf2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -80,7 +80,7 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); #include "transform.h" struct resource_pool; -struct validate_context; +struct dc_state; struct resource_context; struct resource_funcs { @@ -91,18 +91,18 @@ struct resource_funcs { enum dc_status (*validate_guaranteed)( struct dc *dc, struct dc_stream_state *stream, - struct validate_context *context); + struct dc_state *context); bool (*validate_bandwidth)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); enum dc_status (*validate_global)( struct dc *dc, - struct validate_context *context); + struct dc_state *context); struct pipe_ctx *(*acquire_idle_pipe_for_layer)( - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool, struct dc_stream_state *stream); @@ -110,7 +110,7 @@ struct resource_funcs { enum dc_status (*add_stream_to_ctx)( struct dc *dc, - struct validate_context *new_ctx, + struct dc_state *new_ctx, struct dc_stream_state *dc_stream); }; @@ -252,7 +252,7 @@ union bw_context { struct dce_bw_output dce; }; -struct validate_context { +struct dc_state { struct dc_stream_state *streams[MAX_PIPES]; struct dc_stream_status stream_status[MAX_PIPES]; uint8_t stream_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h index 6a205b010084..ae2399f16d1c 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dce_calcs.h @@ -34,7 +34,7 @@ struct pipe_ctx; struct dc; -struct validate_context; +struct dc_state; struct dce_bw_output; enum bw_calcs_version { diff --git a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h index 58744fe87ed8..1e231f6de732 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h +++ b/drivers/gpu/drm/amd/display/dc/inc/dcn_calcs.h @@ -35,7 +35,7 @@ #include "../dml/display_mode_lib.h" struct dc; -struct validate_context; +struct dc_state; /******************************************************************************* * DCN data structures. @@ -621,7 +621,7 @@ extern const struct dcn_ip_params dcn10_ip_defaults; bool dcn_validate_bandwidth( struct dc *dc, - struct validate_context *context); + struct dc_state *context); unsigned int dcn_find_dcfclk_suits_all( const struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h index 01e426194163..aae7629b1c08 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h @@ -49,7 +49,7 @@ struct dce_hwseq { }; struct pipe_ctx; -struct validate_context; +struct dc_state; struct dchub_init_data; struct dc_static_screen_events; struct resource_pool; @@ -60,16 +60,16 @@ struct hw_sequencer_funcs { void (*init_hw)(struct dc *dc); enum dc_status (*apply_ctx_to_hw)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*reset_hw_ctx_wrap)( - struct dc *dc, struct validate_context *context); + struct dc *dc, struct dc_state *context); void (*apply_ctx_for_surface)( struct dc *dc, const struct dc_stream_state *stream, int num_planes, - struct validate_context *context); + struct dc_state *context); void (*set_plane_config)( const struct dc *dc, @@ -127,7 +127,7 @@ struct hw_sequencer_funcs { void (*power_on_front_end)(struct dc *dc, struct pipe_ctx *pipe, - struct validate_context *context); + struct dc_state *context); void (*update_info_frame)(struct pipe_ctx *pipe_ctx); @@ -145,7 +145,7 @@ struct hw_sequencer_funcs { void (*set_bandwidth)( struct dc *dc, - struct validate_context *context, + struct dc_state *context, bool decrease_allowed); void (*set_drr)(struct pipe_ctx **pipe_ctx, int num_pipes, @@ -159,7 +159,7 @@ struct hw_sequencer_funcs { enum dc_status (*prog_pixclk_crtc_otg)( struct pipe_ctx *pipe_ctx, - struct validate_context *context, + struct dc_state *context, struct dc *dc); void (*setup_stereo)( diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index ebc0f5b02365..41437da5fb9b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -81,14 +81,14 @@ void dc_destroy_resource_pool(struct dc *dc); enum dc_status resource_map_pool_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx); enum dc_status resource_build_scaling_params_for_context( const struct dc *dc, - struct validate_context *context); + struct dc_state *context); void resource_build_info_frame(struct pipe_ctx *pipe_ctx); @@ -122,7 +122,7 @@ bool resource_attach_surfaces_to_context( struct dc_plane_state *const *plane_state, int surface_count, struct dc_stream_state *dc_stream, - struct validate_context *context, + struct dc_state *context, const struct resource_pool *pool); struct pipe_ctx *find_idle_secondary_pipe( @@ -130,31 +130,31 @@ struct pipe_ctx *find_idle_secondary_pipe( const struct resource_pool *pool); bool resource_is_stream_unchanged( - struct validate_context *old_context, struct dc_stream_state *stream); + struct dc_state *old_context, struct dc_stream_state *stream); bool resource_validate_attach_surfaces( const struct dc_validation_set set[], int set_count, - const struct validate_context *old_context, - struct validate_context *context, + const struct dc_state *old_context, + struct dc_state *context, const struct resource_pool *pool); void validate_guaranteed_copy_streams( - struct validate_context *context, + struct dc_state *context, int max_streams); void resource_validate_ctx_update_pointer_after_copy( - const struct validate_context *src_ctx, - struct validate_context *dst_ctx); + const struct dc_state *src_ctx, + struct dc_state *dst_ctx); enum dc_status resource_map_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); enum dc_status resource_map_phy_clock_resources( const struct dc *dc, - struct validate_context *context, + struct dc_state *context, struct dc_stream_state *stream); bool pipe_need_reprogram( diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index e3a12f3e0642..7cce28489dba 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -214,7 +214,7 @@ bool dce110_vblank_set( uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK; struct timing_generator *tg = - core_dc->current_context->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; + core_dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; if (enable) { if (!tg->funcs->arm_vert_intr(tg, 2)) { diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 93c8556358f0..6641e8001e97 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -32,7 +32,7 @@ struct dc_context; struct dc_link; struct dc_surface_update; struct resource_context; -struct validate_context; +struct dc_state; /* * @@ -93,7 +93,7 @@ void context_timing_trace( void context_clock_trace( struct dc *dc, - struct validate_context *context); + struct dc_state *context); /* Any function which is empty or have incomplete implementation should be * marked by this macro. -- cgit v1.2.3 From f36cc577c3254738e370b553f9f8cedf2df84070 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Mon, 28 Aug 2017 12:04:23 -0400 Subject: drm/amd/display: Rename dc resource_validate_ctx methods Rename dc_resource methods from validate_ctx to state Signed-off-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++--- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 ++++---- drivers/gpu/drm/amd/display/dc/dc.h | 6 +++--- 4 files changed, 11 insertions(+), 11 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9b018115d97e..4c7515d9c811 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4651,7 +4651,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, dm_state->context = dc_create_state(); ASSERT(dm_state->context); - dc_resource_validate_ctx_copy_construct_current(dc, dm_state->context); + dc_resource_state_copy_construct_current(dc, dm_state->context); /* Remove exiting planes if they are modified */ ret = dm_update_planes_state(dc, state, false, &lock_and_validation_needed); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 53f814dcc24d..6bf8af7a592d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1022,7 +1022,7 @@ void dc_release_state(struct dc_state *context) atomic_dec(&context->ref_count); if (atomic_read(&context->ref_count) == 0) { - dc_resource_validate_ctx_destruct(context); + dc_resource_state_destruct(context); dm_free(context); } } @@ -1292,7 +1292,7 @@ void dc_update_planes_and_stream(struct dc *dc, if (context == NULL) goto context_alloc_fail; - dc_resource_validate_ctx_copy_construct( + dc_resource_state_copy_construct( dc->current_state, context); /*remove old surfaces from context */ @@ -1635,7 +1635,7 @@ void dc_set_power_state( /* Preserve refcount */ ref_count = dc->current_state->ref_count; - dc_resource_validate_ctx_destruct(dc->current_state); + dc_resource_state_destruct(dc->current_state); memset(dc->current_state, 0, sizeof(*dc->current_state)); dc->current_state->ref_count = ref_count; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 727afeaa3830..d284d9d40e2b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1707,11 +1707,11 @@ void validate_guaranteed_copy_streams( } } -void dc_resource_validate_ctx_copy_construct_current( +void dc_resource_state_copy_construct_current( const struct dc *dc, struct dc_state *dst_ctx) { - dc_resource_validate_ctx_copy_construct(dc->current_state, dst_ctx); + dc_resource_state_copy_construct(dc->current_state, dst_ctx); } bool dc_validate_global_state( @@ -2413,7 +2413,7 @@ static void set_vsc_info_packet( /*TODO: stereo 3D support and extend pixel encoding colorimetry*/ } -void dc_resource_validate_ctx_destruct(struct dc_state *context) +void dc_resource_state_destruct(struct dc_state *context) { int i, j; @@ -2432,7 +2432,7 @@ void dc_resource_validate_ctx_destruct(struct dc_state *context) * Copy src_ctx into dst_ctx and retain all surfaces and streams referenced * by the src_ctx */ -void dc_resource_validate_ctx_copy_construct( +void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d1d5737398df..f3ccc2043405 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -679,15 +679,15 @@ bool dc_validate_global_state( * No hardware is programmed for call. Only validation is done. */ -void dc_resource_validate_ctx_copy_construct( +void dc_resource_state_copy_construct( const struct dc_state *src_ctx, struct dc_state *dst_ctx); -void dc_resource_validate_ctx_copy_construct_current( +void dc_resource_state_copy_construct_current( const struct dc *dc, struct dc_state *dst_ctx); -void dc_resource_validate_ctx_destruct(struct dc_state *context); +void dc_resource_state_destruct(struct dc_state *context); /* * TODO update to make it about validation sets -- cgit v1.2.3 From 8f38b66c82618854d019f9df8ff4cd8dd796da10 Mon Sep 17 00:00:00 2001 From: Hersen Wu Date: Mon, 11 Sep 2017 16:42:14 -0400 Subject: drm/amd/display: USB-C to HDMI dongle not light RV1 support only USB-C active DP-2-HDMI dongle. HPD short pulse is generated only for DP signal. When processing HPD short pulse, it must be DP active dongle. No need for I2C-Over-AUX detection. v2: Add description Signed-off-by: Hersen Wu Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++--- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 32 +++++++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 8 +++++- 3 files changed, 33 insertions(+), 16 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4c7515d9c811..febfff2225d9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -639,7 +639,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) continue; mutex_lock(&aconnector->hpd_lock); - dc_link_detect(aconnector->dc_link, false); + dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); aconnector->dc_sink = NULL; amdgpu_dm_update_connector_after_detect(aconnector); mutex_unlock(&aconnector->hpd_lock); @@ -855,7 +855,7 @@ static void handle_hpd_irq(void *param) * since (for MST case) MST does this in it's own context. */ mutex_lock(&aconnector->hpd_lock); - if (dc_link_detect(aconnector->dc_link, false)) { + if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { amdgpu_dm_update_connector_after_detect(aconnector); @@ -965,7 +965,7 @@ static void handle_hpd_rx_irq(void *param) if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) && !is_mst_root_connector) { /* Downstream Port status changed. */ - if (dc_link_detect(aconnector->dc_link, false)) { + if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) { amdgpu_dm_update_connector_after_detect(aconnector); @@ -1353,7 +1353,8 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_encoder; } - if (dc_link_detect(dc_get_link_at_index(dm->dc, i), true)) + if (dc_link_detect(dc_get_link_at_index(dm->dc, i), + DETECT_REASON_BOOT)) amdgpu_dm_update_connector_after_detect(aconnector); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index cea8dafd2edc..845ec421d861 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -355,7 +355,9 @@ static bool is_dp_sink_present(struct dc_link *link) * @brief * Detect output sink type */ -static enum signal_type link_detect_sink(struct dc_link *link) +static enum signal_type link_detect_sink( + struct dc_link *link, + enum dc_detect_reason reason) { enum signal_type result = get_basic_signal_type( link->link_enc->id, link->link_id); @@ -388,12 +390,17 @@ static enum signal_type link_detect_sink(struct dc_link *link) } break; case CONNECTOR_ID_DISPLAY_PORT: { - - /* Check whether DP signal detected: if not - - * we assume signal is DVI; it could be corrected - * to HDMI after dongle detection */ - if (!is_dp_sink_present(link)) - result = SIGNAL_TYPE_DVI_SINGLE_LINK; + /* DP HPD short pulse. Passive DP dongle will not + * have short pulse + */ + if (reason != DETECT_REASON_HPDRX) { + /* Check whether DP signal detected: if not - + * we assume signal is DVI; it could be corrected + * to HDMI after dongle detection + */ + if (!is_dp_sink_present(link)) + result = SIGNAL_TYPE_DVI_SINGLE_LINK; + } } break; default: @@ -460,9 +467,10 @@ static void detect_dp( struct display_sink_capability *sink_caps, bool *converter_disable_audio, struct audio_support *audio_support, - bool boot) + enum dc_detect_reason reason) { - sink_caps->signal = link_detect_sink(link); + bool boot = false; + sink_caps->signal = link_detect_sink(link, reason); sink_caps->transaction_type = get_ddc_transaction_type(sink_caps->signal); @@ -513,6 +521,8 @@ static void detect_dp( * Need check ->sink usages in case ->sink = NULL * TODO: s3 resume check */ + if (reason == DETECT_REASON_BOOT) + boot = true; if (dm_helpers_dp_mst_start_top_mgr( link->ctx, @@ -531,7 +541,7 @@ static void detect_dp( } } -bool dc_link_detect(struct dc_link *link, bool boot) +bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason) { struct dc_sink_init_data sink_init_data = { 0 }; struct display_sink_capability sink_caps = { 0 }; @@ -596,7 +606,7 @@ bool dc_link_detect(struct dc_link *link, bool boot) link, &sink_caps, &converter_disable_audio, - aud_support, boot); + aud_support, reason); /* Active dongle downstream unplug */ if (link->type == dc_connection_active_dongle diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2316a6060b2c..1f0521ff4614 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -885,7 +885,13 @@ bool dc_link_setup_psr(struct dc_link *dc_link, * true otherwise. True meaning further action is required (status update * and OS notification). */ -bool dc_link_detect(struct dc_link *dc_link, bool boot); +enum dc_detect_reason { + DETECT_REASON_BOOT, + DETECT_REASON_HPD, + DETECT_REASON_HPDRX, +}; + +bool dc_link_detect(struct dc_link *dc_link, enum dc_detect_reason reason); /* Notify DC about DP RX Interrupt (aka Short Pulse Interrupt). * Return: -- cgit v1.2.3 From c84dec2fe8837facf4ccaffd2afae9b157719327 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 5 Sep 2017 14:16:09 -0400 Subject: drm/amd/display: Break out amdgpu_dm_connector Stop using amdgpu_connector and roll our own. There is no overlap with amdgpu. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 126 ++++++++++----------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 53 ++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 20 ++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 12 +- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 34 +++--- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.h | 4 +- 6 files changed, 146 insertions(+), 103 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index febfff2225d9..c42660520871 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -465,14 +465,14 @@ static int dm_sw_fini(void *handle) static int detect_mst_link_for_all_connectors(struct drm_device *dev) { - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; int ret = 0; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->dc_link->type == dc_connection_mst_branch) { DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", aconnector, aconnector->base.base.id); @@ -500,13 +500,13 @@ static int dm_late_init(void *handle) static void s3_handle_mst(struct drm_device *dev, bool suspend) { - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->dc_link->type == dc_connection_mst_branch && !aconnector->mst_port) { @@ -562,7 +562,7 @@ static int dm_suspend(void *handle) return ret; } -struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( +struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_atomic_state *state, struct drm_crtc *crtc, bool from_state_var) @@ -583,7 +583,7 @@ struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( connector->state->crtc; if (crtc_from_state == crtc) - return to_amdgpu_connector(connector); + return to_amdgpu_dm_connector(connector); } return NULL; @@ -607,7 +607,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) { struct drm_device *ddev = adev->ddev; struct amdgpu_display_manager *dm = &adev->dm; - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -629,7 +629,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev ) /* Do detection*/ list_for_each_entry(connector, &ddev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); /* * this is the case when traversing through already created @@ -741,7 +741,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { }; void amdgpu_dm_update_connector_after_detect( - struct amdgpu_connector *aconnector) + struct amdgpu_dm_connector *aconnector) { struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; @@ -847,7 +847,7 @@ void amdgpu_dm_update_connector_after_detect( static void handle_hpd_irq(void *param) { - struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param; + struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; @@ -870,7 +870,7 @@ static void handle_hpd_irq(void *param) } -static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector) +static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) { uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 }; uint8_t dret; @@ -949,7 +949,7 @@ static void dm_handle_hpd_rx_irq(struct amdgpu_connector *aconnector) static void handle_hpd_rx_irq(void *param) { - struct amdgpu_connector *aconnector = (struct amdgpu_connector *)param; + struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; const struct dc_link *dc_link = aconnector->dc_link; @@ -988,7 +988,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev) { struct drm_device *dev = adev->ddev; struct drm_connector *connector; - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; const struct dc_link *dc_link; struct dc_interrupt_params int_params = {0}; @@ -998,7 +998,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); dc_link = aconnector->dc_link; if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { @@ -1279,7 +1279,7 @@ int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) { struct amdgpu_display_manager *dm = &adev->dm; uint32_t i; - struct amdgpu_connector *aconnector = NULL; + struct amdgpu_dm_connector *aconnector = NULL; struct amdgpu_encoder *aencoder = NULL; struct amdgpu_mode_info *mode_info = &adev->mode_info; uint32_t link_cnt; @@ -1966,18 +1966,18 @@ static int fill_plane_attributes( /*****************************************************************************/ -struct amdgpu_connector *aconnector_from_drm_crtc_id( +struct amdgpu_dm_connector *aconnector_from_drm_crtc_id( const struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_connector *connector; struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->base.state->crtc != &acrtc->base) continue; @@ -2279,7 +2279,7 @@ static void decide_crtc_timing_for_drm_display_mode( } static struct dc_stream_state *create_stream_for_sink( - struct amdgpu_connector *aconnector, + struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, const struct dm_connector_state *dm_state) { @@ -2425,7 +2425,7 @@ static enum drm_connector_status amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) { bool connected; - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); /* Notes: * 1. This interface is NOT called in context of HPD irq. @@ -2538,7 +2538,7 @@ int amdgpu_dm_connector_atomic_get_property( void amdgpu_dm_connector_destroy(struct drm_connector *connector) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); const struct dc_link *link = aconnector->dc_link; struct amdgpu_device *adev = connector->dev->dev_private; struct amdgpu_display_manager *dm = &adev->dm; @@ -2636,7 +2636,7 @@ static int get_modes(struct drm_connector *connector) return amdgpu_dm_connector_get_modes(connector); } -static void create_eml_sink(struct amdgpu_connector *aconnector) +static void create_eml_sink(struct amdgpu_dm_connector *aconnector) { struct dc_sink_init_data init_params = { .link = aconnector->dc_link, @@ -2669,7 +2669,7 @@ static void create_eml_sink(struct amdgpu_connector *aconnector) aconnector->dc_em_sink; } -static void handle_edid_mgmt(struct amdgpu_connector *aconnector) +static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) { struct dc_link *link = (struct dc_link *)aconnector->dc_link; @@ -2695,7 +2695,7 @@ int amdgpu_dm_connector_mode_valid( struct amdgpu_device *adev = connector->dev->dev_private; /* TODO: Unhardcode stream count */ struct dc_stream_state *stream; - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || (mode->flags & DRM_MODE_FLAG_DBLSCAN)) @@ -2708,7 +2708,7 @@ int amdgpu_dm_connector_mode_valid( !aconnector->dc_em_sink) handle_edid_mgmt(aconnector); - dc_sink = to_amdgpu_connector(connector)->dc_sink; + dc_sink = to_amdgpu_dm_connector(connector)->dc_sink; if (dc_sink == NULL) { DRM_ERROR("dc_sink is NULL!\n"); @@ -2968,7 +2968,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, { int result = MODE_ERROR; struct dc_sink *dc_sink = - to_amdgpu_connector(connector)->dc_sink; + to_amdgpu_dm_connector(connector)->dc_sink; /* TODO: Unhardcode stream count */ struct dc_stream_state *stream; @@ -3229,8 +3229,8 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_display_mode *mode = NULL; struct drm_display_mode *native_mode = &amdgpu_encoder->native_mode; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); int i; int n; struct mode_size { @@ -3278,7 +3278,7 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, common_modes[i].name, common_modes[i].w, common_modes[i].h); drm_mode_probed_add(connector, mode); - amdgpu_connector->num_modes++; + amdgpu_dm_connector->num_modes++; } } @@ -3286,41 +3286,41 @@ static void amdgpu_dm_connector_ddc_get_modes( struct drm_connector *connector, struct edid *edid) { - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); if (edid) { /* empty probed_modes */ INIT_LIST_HEAD(&connector->probed_modes); - amdgpu_connector->num_modes = + amdgpu_dm_connector->num_modes = drm_add_edid_modes(connector, edid); drm_edid_to_eld(connector, edid); amdgpu_dm_get_native_mode(connector); } else - amdgpu_connector->num_modes = 0; + amdgpu_dm_connector->num_modes = 0; } int amdgpu_dm_connector_get_modes(struct drm_connector *connector) { const struct drm_connector_helper_funcs *helper = connector->helper_private; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); struct drm_encoder *encoder; - struct edid *edid = amdgpu_connector->edid; + struct edid *edid = amdgpu_dm_connector->edid; encoder = helper->best_encoder(connector); amdgpu_dm_connector_ddc_get_modes(connector, edid); amdgpu_dm_connector_add_common_modes(encoder, connector); - return amdgpu_connector->num_modes; + return amdgpu_dm_connector->num_modes; } void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, + struct amdgpu_dm_connector *aconnector, int connector_type, struct dc_link *link, int link_index) @@ -3440,7 +3440,7 @@ static struct amdgpu_i2c_adapter *create_i2c( */ int amdgpu_dm_connector_init( struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, + struct amdgpu_dm_connector *aconnector, uint32_t link_index, struct amdgpu_encoder *aencoder) { @@ -4076,7 +4076,7 @@ void amdgpu_dm_atomic_commit_tail( */ if (adev->dm.freesync_module) { for (i = 0; i < new_crtcs_count; i++) { - struct amdgpu_connector *aconnector = NULL; + struct amdgpu_dm_connector *aconnector = NULL; new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); @@ -4120,7 +4120,7 @@ void amdgpu_dm_atomic_commit_tail( /* Handle scaling and undersacn changes*/ for_each_connector_in_state(state, connector, old_conn_state, i) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *con_new_state = to_dm_connector_state(aconnector->base.state); struct dm_connector_state *con_old_state = @@ -4270,7 +4270,7 @@ err: */ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct amdgpu_crtc *disconnected_acrtc; struct dm_crtc_state *acrtc_state; @@ -4360,7 +4360,7 @@ static int dm_update_crtcs_state( /* update changed items */ for_each_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; - struct amdgpu_connector *aconnector = NULL; + struct amdgpu_dm_connector *aconnector = NULL; struct drm_connector_state *conn_state = NULL; struct dm_connector_state *dm_conn_state = NULL; @@ -4689,7 +4689,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * decide how to handle. */ for_each_connector_in_state(state, connector, conn_state, i) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *con_old_state = to_dm_connector_state(aconnector->base.state); struct dm_connector_state *con_new_state = @@ -4746,15 +4746,15 @@ fail: static bool is_dp_capable_without_timing_msa( struct dc *dc, - struct amdgpu_connector *amdgpu_connector) + struct amdgpu_dm_connector *amdgpu_dm_connector) { uint8_t dpcd_data; bool capable = false; - if (amdgpu_connector->dc_link && + if (amdgpu_dm_connector->dc_link && dm_helpers_dp_read_dpcd( NULL, - amdgpu_connector->dc_link, + amdgpu_dm_connector->dc_link, DP_DOWN_STREAM_PORT_COUNT, &dpcd_data, sizeof(dpcd_data))) { @@ -4773,14 +4773,14 @@ void amdgpu_dm_add_sink_to_freesync_module( struct detailed_timing *timing; struct detailed_non_pixel *data; struct detailed_data_monitor_range *range; - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; edid_check_required = false; - if (!amdgpu_connector->dc_sink) { + if (!amdgpu_dm_connector->dc_sink) { DRM_ERROR("dc_sink NULL, could not add free_sync module.\n"); return; } @@ -4790,11 +4790,11 @@ void amdgpu_dm_add_sink_to_freesync_module( * if edid non zero restrict freesync only for dp and edp */ if (edid) { - if (amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT - || amdgpu_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { + if (amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT + || amdgpu_dm_connector->dc_sink->sink_signal == SIGNAL_TYPE_EDP) { edid_check_required = is_dp_capable_without_timing_msa( adev->dm.dc, - amdgpu_connector); + amdgpu_dm_connector); } } val_capable = 0; @@ -4819,20 +4819,20 @@ void amdgpu_dm_add_sink_to_freesync_module( if (range->flags != 1) continue; - amdgpu_connector->min_vfreq = range->min_vfreq; - amdgpu_connector->max_vfreq = range->max_vfreq; - amdgpu_connector->pixel_clock_mhz = + amdgpu_dm_connector->min_vfreq = range->min_vfreq; + amdgpu_dm_connector->max_vfreq = range->max_vfreq; + amdgpu_dm_connector->pixel_clock_mhz = range->pixel_clock_mhz * 10; break; } - if (amdgpu_connector->max_vfreq - - amdgpu_connector->min_vfreq > 10) { - amdgpu_connector->caps.supported = true; - amdgpu_connector->caps.min_refresh_in_micro_hz = - amdgpu_connector->min_vfreq * 1000000; - amdgpu_connector->caps.max_refresh_in_micro_hz = - amdgpu_connector->max_vfreq * 1000000; + if (amdgpu_dm_connector->max_vfreq - + amdgpu_dm_connector->min_vfreq > 10) { + amdgpu_dm_connector->caps.supported = true; + amdgpu_dm_connector->caps.min_refresh_in_micro_hz = + amdgpu_dm_connector->min_vfreq * 1000000; + amdgpu_dm_connector->caps.max_refresh_in_micro_hz = + amdgpu_dm_connector->max_vfreq * 1000000; val_capable = 1; } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 71cbee199016..8894613e956c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -147,6 +147,50 @@ struct amdgpu_display_manager { #endif }; +struct amdgpu_dm_connector { + + struct drm_connector base; + uint32_t connector_id; + + /* we need to mind the EDID between detect + and get modes due to analog/digital/tvencoder */ + struct edid *edid; + + /* shared with amdgpu */ + struct amdgpu_hpd hpd; + + /* number of modes generated from EDID at 'dc_sink' */ + int num_modes; + + /* The 'old' sink - before an HPD. + * The 'current' sink is in dc_link->sink. */ + struct dc_sink *dc_sink; + struct dc_link *dc_link; + struct dc_sink *dc_em_sink; + + /* DM only */ + struct drm_dp_mst_topology_mgr mst_mgr; + struct amdgpu_dm_dp_aux dm_dp_aux; + struct drm_dp_mst_port *port; + struct amdgpu_dm_connector *mst_port; + struct amdgpu_encoder *mst_encoder; + + /* TODO see if we can merge with ddc_bus or make a dm_connector */ + struct amdgpu_i2c_adapter *i2c; + + /* Monitor range limits */ + int min_vfreq ; + int max_vfreq ; + int pixel_clock_mhz; + + /*freesync caps*/ + struct mod_freesync_caps caps; + + struct mutex hpd_lock; +}; + +#define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) + /* basic init/fini API */ int amdgpu_dm_init(struct amdgpu_device *adev); @@ -178,9 +222,9 @@ void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm); extern const struct amdgpu_ip_block_version dm_ip_block; void amdgpu_dm_update_connector_after_detect( - struct amdgpu_connector *aconnector); + struct amdgpu_dm_connector *aconnector); -struct amdgpu_connector *amdgpu_dm_find_first_crct_matching_connector( +struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_atomic_state *state, struct drm_crtc *crtc, bool from_state_var); @@ -193,7 +237,6 @@ struct dc_plane_state; /* TODO rename to dc_stream_state */ struct dc_stream; - struct dm_plane_state { struct drm_plane_state base; struct dc_plane_state *dc_state; @@ -223,7 +266,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, uint32_t link_index); int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, - struct amdgpu_connector *amdgpu_connector, + struct amdgpu_dm_connector *amdgpu_dm_connector, uint32_t link_index, struct amdgpu_encoder *amdgpu_encoder); int amdgpu_dm_encoder_init( @@ -267,7 +310,7 @@ int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); void amdgpu_dm_connector_init_helper( struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector, + struct amdgpu_dm_connector *aconnector, int connector_type, struct dc_link *link, int link_index); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 4a124537dc9a..9bd142f65f9b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -133,7 +133,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( } static void get_payload_table( - struct amdgpu_connector *aconnector, + struct amdgpu_dm_connector *aconnector, struct dp_mst_stream_allocation_table *proposed_table) { int i; @@ -178,7 +178,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( struct dp_mst_stream_allocation_table *proposed_table, bool enable) { - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; int slots = 0; @@ -266,7 +266,7 @@ bool dm_helpers_dp_mst_poll_for_allocation_change_trigger( struct dc_context *ctx, const struct dc_stream_state *stream) { - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; int ret; @@ -293,7 +293,7 @@ bool dm_helpers_dp_mst_send_payload_allocation( const struct dc_stream_state *stream, bool enable) { - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; int ret; @@ -341,7 +341,7 @@ bool dm_helpers_dp_mst_start_top_mgr( const struct dc_link *link, bool boot) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; if (!aconnector) { DRM_ERROR("Failed to found connector for link!"); @@ -364,7 +364,7 @@ void dm_helpers_dp_mst_stop_top_mgr( struct dc_context *ctx, const struct dc_link *link) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; if (!aconnector) { DRM_ERROR("Failed to found connector for link!"); @@ -386,7 +386,7 @@ bool dm_helpers_dp_read_dpcd( uint32_t size) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; if (!aconnector) { DRM_ERROR("Failed to found connector for link!"); @@ -404,7 +404,7 @@ bool dm_helpers_dp_write_dpcd( const uint8_t *data, uint32_t size) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; if (!aconnector) { DRM_ERROR("Failed to found connector for link!"); @@ -420,7 +420,7 @@ bool dm_helpers_submit_i2c( const struct dc_link *link, struct i2c_command *cmd) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; struct i2c_msg *msgs; int i = 0; int num = cmd->number_of_payloads; @@ -455,7 +455,7 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_link *link, struct dc_sink *sink) { - struct amdgpu_connector *aconnector = link->priv; + struct amdgpu_dm_connector *aconnector = link->priv; struct i2c_adapter *ddc; int retry = 3; enum dc_edid_status edid_status; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 4aee146a848f..276adf96d5f2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -787,10 +787,10 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) struct drm_connector *connector; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); - const struct dc_link *dc_link = amdgpu_connector->dc_link; + const struct dc_link *dc_link = amdgpu_dm_connector->dc_link; if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) { dc_interrupt_set(adev->dm.dc, @@ -820,9 +820,9 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) struct drm_connector *connector; list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - struct amdgpu_connector *amdgpu_connector = - to_amdgpu_connector(connector); - const struct dc_link *dc_link = amdgpu_connector->dc_link; + struct amdgpu_dm_connector *amdgpu_dm_connector = + to_amdgpu_dm_connector(connector); + const struct dc_link *dc_link = amdgpu_dm_connector->dc_link; dc_interrupt_set(adev->dm.dc, dc_link->irq_source_hpd, false); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 82e4d49fb184..343645e4070b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -137,8 +137,8 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg static enum drm_connector_status dm_dp_mst_detect(struct drm_connector *connector, bool force) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); - struct amdgpu_connector *master = aconnector->mst_port; + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct amdgpu_dm_connector *master = aconnector->mst_port; enum drm_connector_status status = drm_dp_mst_detect_port( @@ -152,13 +152,13 @@ dm_dp_mst_detect(struct drm_connector *connector, bool force) static void dm_dp_mst_connector_destroy(struct drm_connector *connector) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); - struct amdgpu_encoder *amdgpu_encoder = amdgpu_connector->mst_encoder; + struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); + struct amdgpu_encoder *amdgpu_encoder = amdgpu_dm_connector->mst_encoder; drm_encoder_cleanup(&amdgpu_encoder->base); kfree(amdgpu_encoder); drm_connector_cleanup(connector); - kfree(amdgpu_connector); + kfree(amdgpu_dm_connector); } static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { @@ -174,7 +174,7 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { static int dm_dp_mst_get_modes(struct drm_connector *connector) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); int ret = 0; ret = drm_add_edid_modes(&aconnector->base, aconnector->edid); @@ -186,9 +186,9 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder *dm_mst_best_encoder(struct drm_connector *connector) { - struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); - return &amdgpu_connector->mst_encoder->base; + return &amdgpu_dm_connector->mst_encoder->base; } static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { @@ -198,7 +198,7 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs }; static struct amdgpu_encoder * -dm_dp_create_fake_mst_encoder(struct amdgpu_connector *connector) +dm_dp_create_fake_mst_encoder(struct amdgpu_dm_connector *connector) { struct drm_device *dev = connector->base.dev; struct amdgpu_device *adev = dev->dev_private; @@ -233,15 +233,15 @@ static struct drm_connector *dm_dp_add_mst_connector(struct drm_dp_mst_topology_ struct drm_dp_mst_port *port, const char *pathprop) { - struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr); + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); struct drm_device *dev = master->base.dev; struct amdgpu_device *adev = dev->dev_private; - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->mst_port == master && !aconnector->port) { DRM_INFO("DM_MST: reusing connector: %p [id: %d] [master: %p]\n", @@ -315,7 +315,7 @@ static void dm_dp_destroy_mst_connector( struct drm_dp_mst_topology_mgr *mgr, struct drm_connector *connector) { - struct amdgpu_connector *aconnector = to_amdgpu_connector(connector); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", aconnector, connector->base.id, aconnector->mst_port); @@ -339,17 +339,17 @@ static void dm_dp_destroy_mst_connector( static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) { - struct amdgpu_connector *master = container_of(mgr, struct amdgpu_connector, mst_mgr); + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); struct drm_device *dev = master->base.dev; struct amdgpu_device *adev = dev->dev_private; struct drm_connector *connector; - struct amdgpu_connector *aconnector; + struct amdgpu_dm_connector *aconnector; struct edid *edid; struct dc_sink *dc_sink; drm_modeset_lock_all(dev); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->port && aconnector->port->pdt != DP_PEER_DEVICE_NONE && aconnector->port->pdt != DP_PEER_DEVICE_MST_BRANCHING && @@ -440,7 +440,7 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { void amdgpu_dm_initialize_dp_connector( struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector) + struct amdgpu_dm_connector *aconnector) { aconnector->dm_dp_aux.aux.name = "dmdc"; aconnector->dm_dp_aux.aux.dev = dm->adev->dev; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h index 418061f3b46b..ba64a408d79c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h @@ -27,10 +27,10 @@ #define __DAL_AMDGPU_DM_MST_TYPES_H__ struct amdgpu_display_manager; -struct amdgpu_connector; +struct amdgpu_dm_connector; void amdgpu_dm_initialize_dp_connector( struct amdgpu_display_manager *dm, - struct amdgpu_connector *aconnector); + struct amdgpu_dm_connector *aconnector); #endif -- cgit v1.2.3 From 2e0ac3d68838d20a5eace958bdf853a295a7175f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 17 Aug 2017 14:58:07 -0400 Subject: drm/amd/display: Create fake sink if needed when commit stream The problem we're trying to fix is this (and similar): 1) X Desktop with single display 2) VT switch 3) Unplug display 4) VT switch back to X 5) re-plug same display Before this we'd fail at step 4 when trying to create a dc_stream_state because of a missing sink. This change will fake a sink in this case. The same scenario applies to S3 resume. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 ++++++++++++++++++++++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 ++ 2 files changed, 30 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c42660520871..d2ece343b5fa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -855,6 +855,10 @@ static void handle_hpd_irq(void *param) * since (for MST case) MST does this in it's own context. */ mutex_lock(&aconnector->hpd_lock); + + if (aconnector->fake_enable) + aconnector->fake_enable = false; + if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) { amdgpu_dm_update_connector_after_detect(aconnector); @@ -2278,6 +2282,25 @@ static void decide_crtc_timing_for_drm_display_mode( } } +static void create_fake_sink(struct amdgpu_dm_connector *aconnector) +{ + struct dc_sink *sink = NULL; + struct dc_sink_init_data sink_init_data = { 0 }; + + sink_init_data.link = aconnector->dc_link; + sink_init_data.sink_signal = aconnector->dc_link->connector_signal; + + sink = dc_sink_create(&sink_init_data); + if (!sink) + DRM_ERROR("Failed to create sink!\n"); + + sink->sink_signal = SIGNAL_TYPE_VIRTUAL; + aconnector->fake_enable = true; + + aconnector->dc_sink = sink; + aconnector->dc_link->local_sink = sink; +} + static struct dc_stream_state *create_stream_for_sink( struct amdgpu_dm_connector *aconnector, const struct drm_display_mode *drm_mode, @@ -2300,6 +2323,10 @@ static struct dc_stream_state *create_stream_for_sink( } drm_connector = &aconnector->base; + + if (!aconnector->dc_sink) + create_fake_sink(aconnector); + stream = dc_create_stream_for_sink(aconnector->dc_sink); if (stream == NULL) { @@ -4373,7 +4400,7 @@ static int dm_update_crtcs_state( aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); /* TODO This hack should go away */ - if (aconnector && aconnector->dc_sink) { + if (aconnector) { conn_state = drm_atomic_get_connector_state(state, &aconnector->base); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 8894613e956c..630e6cdf84f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -187,6 +187,8 @@ struct amdgpu_dm_connector { struct mod_freesync_caps caps; struct mutex hpd_lock; + + bool fake_enable; }; #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) -- cgit v1.2.3 From 1ecfc3da95428983725d643e80e9a320497d2059 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 8 Sep 2017 10:23:42 -0400 Subject: drm/amd/display: Format changes to bring in line with internal tree Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 4 ++-- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 1 - 3 files changed, 5 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d2ece343b5fa..bb4f415746d5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -603,7 +603,7 @@ static int dm_resume(void *handle) return 0; } -int amdgpu_dm_display_resume(struct amdgpu_device *adev ) +int amdgpu_dm_display_resume(struct amdgpu_device *adev) { struct drm_device *ddev = adev->ddev; struct amdgpu_display_manager *dm = &adev->dm; @@ -1794,7 +1794,7 @@ static int fill_plane_attributes_from_fb( break; default: DRM_ERROR("Unsupported screen format %s\n", - drm_get_format_name(fb->format->format, &format_name)); + drm_get_format_name(fb->format->format, &format_name)); return -EINVAL; } @@ -2618,7 +2618,7 @@ struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( if (new_state) { __drm_atomic_helper_connector_duplicate_state(connector, - &new_state->base); + &new_state->base); return &new_state->base; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 276adf96d5f2..22d41d35249e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -705,8 +705,8 @@ static inline int dm_irq_state( if (!acrtc) { DRM_ERROR( "%s: crtc is NULL at id :%d\n", - func, - crtc_id); + func, + crtc_id); return 0; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index 25f6f9103c44..f7d049c0e62a 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -41,7 +41,6 @@ */ #include "dce80/hw_factory_dce80.h" - #include "dce110/hw_factory_dce110.h" #include "dce120/hw_factory_dce120.h" #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -- cgit v1.2.3 From 01a526f3dee9abe1e2db9e37e4ceb4149f8ae77b Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 19:33:40 -0400 Subject: drm/amd/display: Pass log_mask from DM Linux and Windows often desire different log levels. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/dc/basics/logger.c | 41 +++------------------- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../gpu/drm/amd/display/include/logger_interface.h | 2 +- drivers/gpu/drm/amd/display/include/logger_types.h | 32 +++++++++++++++++ 6 files changed, 42 insertions(+), 38 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb4f415746d5..5f4e7dc92797 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -374,6 +374,8 @@ int amdgpu_dm_init(struct amdgpu_device *adev) init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; + init_data.log_mask = DC_DEFAULT_LOG_MASK; + #ifdef ENABLE_FBC if (adev->family == FAMILY_CZ) amdgpu_dm_initialize_fbc(adev); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 0b17374b1535..5895dd3903a3 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -64,40 +64,9 @@ static const struct dc_log_type_info log_type_info_tbl[] = { }; -#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \ - (1 << LOG_WARNING) | \ - (1 << LOG_EVENT_MODE_SET) | \ - (1 << LOG_EVENT_DETECTION) | \ - (1 << LOG_EVENT_LINK_TRAINING) | \ - (1 << LOG_EVENT_LINK_LOSS) | \ - (1 << LOG_EVENT_UNDERFLOW) | \ - (1 << LOG_RESOURCE) | \ - (1 << LOG_FEATURE_OVERRIDE) | \ - (1 << LOG_DETECTION_EDID_PARSER) | \ - (1 << LOG_DC) | \ - (1 << LOG_HW_HOTPLUG) | \ - (1 << LOG_HW_SET_MODE) | \ - (1 << LOG_HW_RESUME_S3) | \ - (1 << LOG_HW_HPD_IRQ) | \ - (1 << LOG_SYNC) | \ - (1 << LOG_BANDWIDTH_VALIDATION) | \ - (1 << LOG_MST) | \ - (1 << LOG_DETECTION_DP_CAPS) | \ - (1 << LOG_BACKLIGHT)) | \ - (1 << LOG_I2C_AUX) | \ - (1 << LOG_IF_TRACE) | \ - (1 << LOG_DTN) /* | \ - (1 << LOG_DEBUG) | \ - (1 << LOG_BIOS) | \ - (1 << LOG_SURFACE) | \ - (1 << LOG_SCALER) | \ - (1 << LOG_DML) | \ - (1 << LOG_HW_LINK_TRAINING) | \ - (1 << LOG_HW_AUDIO)| \ - (1 << LOG_BANDWIDTH_CALCS)*/ - /* ----------- Object init and destruction ----------- */ -static bool construct(struct dc_context *ctx, struct dal_logger *logger) +static bool construct(struct dc_context *ctx, struct dal_logger *logger, + uint32_t log_mask) { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; @@ -120,7 +89,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger) logger->ctx = ctx; - logger->mask = DC_DEFAULT_LOG_MASK; + logger->mask = log_mask; return true; } @@ -133,14 +102,14 @@ static void destruct(struct dal_logger *logger) } } -struct dal_logger *dal_logger_create(struct dc_context *ctx) +struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask) { /* malloc struct */ struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger)); if (!logger) return NULL; - if (!construct(ctx, logger)) { + if (!construct(ctx, logger, log_mask)) { dm_free(logger); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5579d2167a9a..75a5fa2296d7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -493,7 +493,7 @@ static bool construct(struct dc *dc, dc_ctx->asic_id = init_params->asic_id; /* Create logger */ - logger = dal_logger_create(dc_ctx); + logger = dal_logger_create(dc_ctx, init_params->log_mask); if (!logger) { /* can *not* call logger. call base driver 'print error' */ diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1f0521ff4614..9c0e00050753 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -267,6 +267,7 @@ struct dc_init_data { enum dce_environment dce_environment; struct dc_config flags; + uint32_t log_mask; #ifdef ENABLE_FBC uint64_t fbc_gpu_addr; #endif diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index 6641e8001e97..5aaf2dacfe38 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -40,7 +40,7 @@ struct dc_state; * */ -struct dal_logger *dal_logger_create(struct dc_context *ctx); +struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask); uint32_t dal_logger_destroy(struct dal_logger **logger); diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index 42ffb93e3172..044805ccac25 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -70,6 +70,38 @@ enum dc_log_type { LOG_SECTION_TOTAL_COUNT }; +#define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \ + (1 << LOG_WARNING) | \ + (1 << LOG_EVENT_MODE_SET) | \ + (1 << LOG_EVENT_DETECTION) | \ + (1 << LOG_EVENT_LINK_TRAINING) | \ + (1 << LOG_EVENT_LINK_LOSS) | \ + (1 << LOG_EVENT_UNDERFLOW) | \ + (1 << LOG_RESOURCE) | \ + (1 << LOG_FEATURE_OVERRIDE) | \ + (1 << LOG_DETECTION_EDID_PARSER) | \ + (1 << LOG_DC) | \ + (1 << LOG_HW_HOTPLUG) | \ + (1 << LOG_HW_SET_MODE) | \ + (1 << LOG_HW_RESUME_S3) | \ + (1 << LOG_HW_HPD_IRQ) | \ + (1 << LOG_SYNC) | \ + (1 << LOG_BANDWIDTH_VALIDATION) | \ + (1 << LOG_MST) | \ + (1 << LOG_DETECTION_DP_CAPS) | \ + (1 << LOG_BACKLIGHT)) | \ + (1 << LOG_I2C_AUX) | \ + (1 << LOG_IF_TRACE) | \ + (1 << LOG_DTN) /* | \ + (1 << LOG_DEBUG) | \ + (1 << LOG_BIOS) | \ + (1 << LOG_SURFACE) | \ + (1 << LOG_SCALER) | \ + (1 << LOG_DML) | \ + (1 << LOG_HW_LINK_TRAINING) | \ + (1 << LOG_HW_AUDIO)| \ + (1 << LOG_BANDWIDTH_CALCS)*/ + union logger_flags { struct { uint32_t ENABLE_CONSOLE:1; /* Print to console */ -- cgit v1.2.3 From f1ad2f5efd29dc838222f37281675a2623714538 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 20:04:48 -0400 Subject: drm/amd/display: Reduce DC chattiness Log DC init but default log level to 0 (default for amdgpu_dc_log) otherwise. Bug reporters can still make DC more chatty by using the dc_log module param. amdgpu.dc_log = 1 v2: Only provide runtime option, no compile time config Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 74 ++++++++++++---------- drivers/gpu/drm/amd/display/include/logger_types.h | 3 + 2 files changed, 42 insertions(+), 35 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5f4e7dc92797..36635486b937 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -334,7 +334,6 @@ int amdgpu_dm_init(struct amdgpu_device *adev) adev->dm.ddev = adev->ddev; adev->dm.adev = adev; - DRM_INFO("DAL is enabled\n"); /* Zero all the fields */ memset(&init_data, 0, sizeof(init_data)); @@ -374,7 +373,10 @@ int amdgpu_dm_init(struct amdgpu_device *adev) init_data.dce_environment = DCE_ENV_PRODUCTION_DRV; - init_data.log_mask = DC_DEFAULT_LOG_MASK; + if (amdgpu_dc_log) + init_data.log_mask = DC_DEFAULT_LOG_MASK; + else + init_data.log_mask = DC_MIN_LOG_MASK; #ifdef ENABLE_FBC if (adev->family == FAMILY_CZ) @@ -384,7 +386,9 @@ int amdgpu_dm_init(struct amdgpu_device *adev) /* Display Core create. */ adev->dm.dc = dc_create(&init_data); - if (!adev->dm.dc) + if (adev->dm.dc) + DRM_INFO("Display Core initialized!\n"); + else DRM_INFO("Display Core failed to initialize!\n"); INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func); @@ -394,7 +398,7 @@ int amdgpu_dm_init(struct amdgpu_device *adev) DRM_ERROR( "amdgpu: failed to initialize freesync_module.\n"); } else - DRM_INFO("amdgpu: freesync_module init done %p.\n", + DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n", adev->dm.freesync_module); if (amdgpu_dm_initialize_drm_device(adev)) { @@ -418,7 +422,7 @@ int amdgpu_dm_init(struct amdgpu_device *adev) goto error; } - DRM_INFO("KMS initialized.\n"); + DRM_DEBUG_DRIVER("KMS initialized.\n"); return 0; error: @@ -476,7 +480,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) list_for_each_entry(connector, &dev->mode_config.connector_list, head) { aconnector = to_amdgpu_dm_connector(connector); if (aconnector->dc_link->type == dc_connection_mst_branch) { - DRM_INFO("DM_MST: starting TM on aconnector: %p [id: %d]\n", + DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", aconnector, aconnector->base.base.id); ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); @@ -805,12 +809,12 @@ void amdgpu_dm_update_connector_after_detect( if (aconnector->dc_sink == sink) { /* We got a DP short pulse (Link Loss, DP CTS, etc...). * Do nothing!! */ - DRM_INFO("DCHPD: connector_id=%d: dc_sink didn't change.\n", + DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n", aconnector->connector_id); return; } - DRM_INFO("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", + DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n", aconnector->connector_id, aconnector->dc_sink, sink); mutex_lock(&dev->mode_config.mutex); @@ -912,7 +916,7 @@ static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) process_count++; - DRM_DEBUG_KMS("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); + DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]); /* handle HPD short pulse irq */ if (aconnector->mst_mgr.mst_state) drm_dp_mst_hpd_irq( @@ -950,7 +954,7 @@ static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) } if (process_count == max_process_count) - DRM_DEBUG_KMS("Loop exceeded max iterations\n"); + DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); } static void handle_hpd_rx_irq(void *param) @@ -1269,7 +1273,7 @@ void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) if (NULL == dm->backlight_dev) DRM_ERROR("DM: Backlight registration failed!\n"); else - DRM_INFO("DM: Registered Backlight device: %s\n", bl_name); + DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); } #endif @@ -2045,7 +2049,7 @@ static void update_stream_scaling_settings( stream->src = src; stream->dst = dst; - DRM_DEBUG_KMS("Destination Rectangle x:%d y:%d width:%d height:%d\n", + DRM_DEBUG_DRIVER("Destination Rectangle x:%d y:%d width:%d height:%d\n", dst.x, dst.y, dst.width, dst.height); } @@ -2355,7 +2359,7 @@ static struct dc_stream_state *create_stream_for_sink( * case, we call set mode ourselves to restore the previous mode * and the modelist may not be filled in in time. */ - DRM_INFO("No preferred mode found\n"); + DRM_DEBUG_DRIVER("No preferred mode found\n"); } else { decide_crtc_timing_for_drm_display_mode( &mode, preferred_mode, @@ -2644,7 +2648,7 @@ static struct drm_encoder *best_encoder(struct drm_connector *connector) struct drm_mode_object *obj; struct drm_encoder *encoder; - DRM_DEBUG_KMS("Finding the best encoder\n"); + DRM_DEBUG_DRIVER("Finding the best encoder\n"); /* pick the encoder ids */ if (enc_id) { @@ -2913,7 +2917,7 @@ static int dm_plane_helper_prepare_fb( dm_plane_state_new = to_dm_plane_state(new_state); if (!new_state->fb) { - DRM_DEBUG_KMS("No FB bound\n"); + DRM_DEBUG_DRIVER("No FB bound\n"); return 0; } @@ -3480,7 +3484,7 @@ int amdgpu_dm_connector_init( struct amdgpu_i2c_adapter *i2c; ((struct dc_link *)link)->priv = aconnector; - DRM_DEBUG_KMS("%s()\n", __func__); + DRM_DEBUG_DRIVER("%s()\n", __func__); i2c = create_i2c(link->ddc, link->link_index, &res); aconnector->i2c = i2c; @@ -3721,11 +3725,11 @@ static void handle_cursor_update( if (!plane->state->fb && !old_plane_state->fb) return; - DRM_DEBUG_KMS("%s: crtc_id=%d with size %d to %d\n", - __func__, - amdgpu_crtc->crtc_id, - plane->state->crtc_w, - plane->state->crtc_h); + DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", + __func__, + amdgpu_crtc->crtc_id, + plane->state->crtc_w, + plane->state->crtc_h); ret = get_cursor_position(plane, crtc, &position); if (ret) @@ -4028,7 +4032,7 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(new_state); old_acrtc_state = to_dm_crtc_state(old_crtc_state); - DRM_DEBUG_KMS( + DRM_DEBUG_DRIVER( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n", @@ -4046,7 +4050,7 @@ void amdgpu_dm_atomic_commit_tail( if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) { - DRM_INFO("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); + DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); if (!new_acrtc_state->stream) { /* @@ -4064,7 +4068,7 @@ void amdgpu_dm_atomic_commit_tail( * have a sink to keep the pipe running so that * hw state is consistent with the sw state */ - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); continue; } @@ -4091,7 +4095,7 @@ void amdgpu_dm_atomic_commit_tail( acrtc->hw_mode = crtc->state->mode; crtc->hwmode = crtc->state->mode; } else if (modereset_required(new_state)) { - DRM_INFO("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); + DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); /* i.e. reset mode */ if (old_acrtc_state->stream) @@ -4116,7 +4120,7 @@ void amdgpu_dm_atomic_commit_tail( &new_crtcs[i]->base, false); if (!aconnector) { - DRM_INFO("Atomic commit: Failed to find connector for acrtc id:%d " + DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d " "skipping freesync init\n", new_crtcs[i]->crtc_id); continue; @@ -4425,7 +4429,7 @@ static int dm_update_crtcs_state( */ if (!new_stream) { - DRM_DEBUG_KMS("%s: Failed to create new stream for crtc %d\n", + DRM_DEBUG_DRIVER("%s: Failed to create new stream for crtc %d\n", __func__, acrtc->base.base.id); break; } @@ -4436,7 +4440,7 @@ static int dm_update_crtcs_state( crtc_state->mode_changed = false; - DRM_DEBUG_KMS("Mode change not required, setting mode_changed to %d", + DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", crtc_state->mode_changed); } @@ -4444,7 +4448,7 @@ static int dm_update_crtcs_state( if (!drm_atomic_crtc_needs_modeset(crtc_state)) goto next_crtc; - DRM_DEBUG_KMS( + DRM_DEBUG_DRIVER( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n", @@ -4462,7 +4466,7 @@ static int dm_update_crtcs_state( if (!old_acrtc_state->stream) goto next_crtc; - DRM_DEBUG_KMS("Disabling DRM crtc: %d\n", + DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", crtc->base.id); /* i.e. reset mode */ @@ -4492,7 +4496,7 @@ static int dm_update_crtcs_state( new_acrtc_state->stream = new_stream; dc_stream_retain(new_stream); - DRM_DEBUG_KMS("Enabling DRM crtc: %d\n", + DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", crtc->base.id); if (!dc_add_stream_to_ctx( @@ -4567,7 +4571,7 @@ static int dm_update_planes_state( if (!old_acrtc_state->stream) continue; - DRM_DEBUG_KMS("Disabling DRM plane: %d on DRM crtc %d\n", + DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n", plane->base.id, old_plane_crtc->base.id); if (!dc_remove_plane_from_context( @@ -4605,7 +4609,7 @@ static int dm_update_planes_state( new_dm_plane_state->dc_state = dc_create_plane_state(dc); - DRM_DEBUG_KMS("Enabling DRM plane: %d on DRM crtc %d\n", + DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", plane->base.id, new_plane_crtc->base.id); if (!new_dm_plane_state->dc_state) { @@ -4764,9 +4768,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, fail: if (ret == -EDEADLK) - DRM_DEBUG_KMS("Atomic check stopped due to to deadlock.\n"); + DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n"); else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) - DRM_DEBUG_KMS("Atomic check stopped due to to signal.\n"); + DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n"); else DRM_ERROR("Atomic check failed with err: %d \n", ret); diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index 044805ccac25..1f22e84cedb9 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -70,6 +70,9 @@ enum dc_log_type { LOG_SECTION_TOTAL_COUNT }; +#define DC_MIN_LOG_MASK ((1 << LOG_ERROR) | \ + (1 << LOG_DETECTION_EDID_PARSER)) + #define DC_DEFAULT_LOG_MASK ((1 << LOG_ERROR) | \ (1 << LOG_WARNING) | \ (1 << LOG_EVENT_MODE_SET) | \ -- cgit v1.2.3 From 2004f45ef83f07f43f5da6ede780b08068c7583d Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Wed, 27 Sep 2017 10:53:50 -0400 Subject: drm/amd/display: Use kernel alloc/free Abstractions are frowned upon. cocci script: virtual context virtual patch virtual org virtual report @@ expression ptr; @@ - dm_alloc(ptr) + kzalloc(ptr, GFP_KERNEL) @@ expression ptr, size; @@ - dm_realloc(ptr, size) + krealloc(ptr, size, GFP_KERNEL) @@ expression ptr; @@ - dm_free(ptr) + kfree(ptr) v2: use GFP_KERNEL, not GFP_ATOMIC. add cocci script Reviewed-by: Alex Deucher Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/basics/logger.c | 18 ++++--- drivers/gpu/drm/amd/display/dc/basics/vector.c | 19 +++---- drivers/gpu/drm/amd/display/dc/bios/bios_parser.c | 17 +++--- drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c | 14 ++--- drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c | 5 +- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc.c | 42 ++++++++------- drivers/gpu/drm/amd/display/dc/core/dc_link.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c | 18 +++---- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_sink.c | 11 ++-- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 6 +-- drivers/gpu/drm/amd/display/dc/core/dc_surface.c | 15 +++--- drivers/gpu/drm/amd/display/dc/dce/dce_abm.c | 4 +- drivers/gpu/drm/amd/display/dc/dce/dce_audio.c | 4 +- .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 12 +++-- drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c | 10 ++-- drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c | 6 +-- drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c | 2 +- .../gpu/drm/amd/display/dc/dce/dce_link_encoder.c | 2 +- drivers/gpu/drm/amd/display/dc/dce/dce_opp.c | 2 +- .../drm/amd/display/dc/dce100/dce100_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce110/dce110_compressor.c | 6 +-- .../drm/amd/display/dc/dce110/dce110_resource.c | 61 ++++++++++++---------- .../drm/amd/display/dc/dce112/dce112_compressor.c | 6 +-- .../drm/amd/display/dc/dce112/dce112_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce120/dce120_resource.c | 43 +++++++-------- .../drm/amd/display/dc/dce80/dce80_compressor.c | 6 +-- .../gpu/drm/amd/display/dc/dce80/dce80_resource.c | 47 +++++++++-------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c | 2 +- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 56 ++++++++++---------- drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c | 4 +- drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c | 21 ++++---- drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c | 6 +-- drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c | 2 +- drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c | 6 +-- .../amd/display/dc/i2caux/dce100/i2caux_dce100.c | 4 +- .../display/dc/i2caux/dce110/aux_engine_dce110.c | 6 +-- .../dc/i2caux/dce110/i2c_hw_engine_dce110.c | 7 +-- .../dc/i2caux/dce110/i2c_sw_engine_dce110.c | 7 +-- .../amd/display/dc/i2caux/dce110/i2caux_dce110.c | 6 +-- .../amd/display/dc/i2caux/dce112/i2caux_dce112.c | 4 +- .../amd/display/dc/i2caux/dce120/i2caux_dce120.c | 4 +- .../display/dc/i2caux/dce80/i2c_hw_engine_dce80.c | 6 +-- .../display/dc/i2caux/dce80/i2c_sw_engine_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c | 6 +-- .../drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c | 4 +- .../display/dc/i2caux/diagnostics/i2caux_diag.c | 7 +-- .../gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c | 6 +-- .../amd/display/dc/irq/dce110/irq_service_dce110.c | 5 +- .../amd/display/dc/irq/dce120/irq_service_dce120.c | 5 +- .../amd/display/dc/irq/dce80/irq_service_dce80.c | 5 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 5 +- drivers/gpu/drm/amd/display/dc/irq/irq_service.c | 2 +- .../amd/display/dc/virtual/virtual_link_encoder.c | 2 +- .../display/dc/virtual/virtual_stream_encoder.c | 4 +- .../drm/amd/display/modules/freesync/freesync.c | 14 ++--- 59 files changed, 362 insertions(+), 330 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 36635486b937..dba54c0a7b5f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2429,7 +2429,7 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) if (WARN_ON(!crtc->state)) return NULL; - state = dm_alloc(sizeof(*state)); + state = kzalloc(sizeof(*state), GFP_KERNEL); __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); diff --git a/drivers/gpu/drm/amd/display/dc/basics/logger.c b/drivers/gpu/drm/amd/display/dc/basics/logger.c index 5895dd3903a3..afb6d2d80e0c 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/logger.c +++ b/drivers/gpu/drm/amd/display/dc/basics/logger.c @@ -70,8 +70,8 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, { /* malloc buffer and init offsets */ logger->log_buffer_size = DAL_LOGGER_BUFFER_MAX_SIZE; - logger->log_buffer = (char *)dm_alloc(logger->log_buffer_size * - sizeof(char)); + logger->log_buffer = (char *)kzalloc(logger->log_buffer_size * sizeof(char), + GFP_KERNEL); if (!logger->log_buffer) return false; @@ -97,7 +97,7 @@ static bool construct(struct dc_context *ctx, struct dal_logger *logger, static void destruct(struct dal_logger *logger) { if (logger->log_buffer) { - dm_free(logger->log_buffer); + kfree(logger->log_buffer); logger->log_buffer = NULL; } } @@ -105,12 +105,13 @@ static void destruct(struct dal_logger *logger) struct dal_logger *dal_logger_create(struct dc_context *ctx, uint32_t log_mask) { /* malloc struct */ - struct dal_logger *logger = dm_alloc(sizeof(struct dal_logger)); + struct dal_logger *logger = kzalloc(sizeof(struct dal_logger), + GFP_KERNEL); if (!logger) return NULL; if (!construct(ctx, logger, log_mask)) { - dm_free(logger); + kfree(logger); return NULL; } @@ -122,7 +123,7 @@ uint32_t dal_logger_destroy(struct dal_logger **logger) if (logger == NULL || *logger == NULL) return 1; destruct(*logger); - dm_free(*logger); + kfree(*logger); *logger = NULL; return 0; @@ -390,7 +391,8 @@ void dm_logger_open( entry->type = log_type; entry->logger = logger; - entry->buf = dm_alloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char)); + entry->buf = kzalloc(DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char), + GFP_KERNEL); entry->buf_offset = 0; entry->max_buf_bytes = DAL_LOGGER_BUFFER_MAX_SIZE * sizeof(char); @@ -421,7 +423,7 @@ void dm_logger_close(struct log_entry *entry) cleanup: if (entry->buf) { - dm_free(entry->buf); + kfree(entry->buf); entry->buf = NULL; entry->buf_offset = 0; entry->max_buf_bytes = 0; diff --git a/drivers/gpu/drm/amd/display/dc/basics/vector.c b/drivers/gpu/drm/amd/display/dc/basics/vector.c index bb72a1857160..e00fc4db3ac4 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/vector.c +++ b/drivers/gpu/drm/amd/display/dc/basics/vector.c @@ -40,7 +40,7 @@ bool dal_vector_construct( return false; } - vector->container = dm_alloc(struct_size * capacity); + vector->container = kzalloc(struct_size * capacity, GFP_KERNEL); if (vector->container == NULL) return false; vector->capacity = capacity; @@ -67,7 +67,7 @@ bool dal_vector_presized_costruct( return false; } - vector->container = dm_alloc(struct_size * count); + vector->container = kzalloc(struct_size * count, GFP_KERNEL); if (vector->container == NULL) return false; @@ -95,7 +95,7 @@ struct vector *dal_vector_presized_create( void *initial_value, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -105,7 +105,7 @@ struct vector *dal_vector_presized_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -114,7 +114,7 @@ struct vector *dal_vector_create( uint32_t capacity, uint32_t struct_size) { - struct vector *vector = dm_alloc(sizeof(struct vector)); + struct vector *vector = kzalloc(sizeof(struct vector), GFP_KERNEL); if (vector == NULL) return NULL; @@ -123,7 +123,7 @@ struct vector *dal_vector_create( return vector; BREAK_TO_DEBUGGER(); - dm_free(vector); + kfree(vector); return NULL; } @@ -131,7 +131,7 @@ void dal_vector_destruct( struct vector *vector) { if (vector->container != NULL) - dm_free(vector->container); + kfree(vector->container); vector->count = 0; vector->capacity = 0; } @@ -142,7 +142,7 @@ void dal_vector_destroy( if (vector == NULL || *vector == NULL) return; dal_vector_destruct(*vector); - dm_free(*vector); + kfree(*vector); *vector = NULL; } @@ -290,7 +290,8 @@ bool dal_vector_reserve(struct vector *vector, uint32_t capacity) if (capacity <= vector->capacity) return true; - new_container = dm_realloc(vector->container, capacity * vector->struct_size); + new_container = krealloc(vector->container, + capacity * vector->struct_size, GFP_KERNEL); if (new_container) { vector->container = new_container; diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c index 2c411441771b..47d673a1f688 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c @@ -116,14 +116,14 @@ struct dc_bios *bios_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); BREAK_TO_DEBUGGER(); return NULL; } @@ -131,10 +131,10 @@ struct dc_bios *bios_parser_create( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void bios_parser_destroy(struct dc_bios **dcb) @@ -148,7 +148,7 @@ static void bios_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -3531,7 +3531,8 @@ static void process_ext_display_connection_info(struct bios_parser *bp) uint8_t *original_bios; /* Step 1: Replace bios image with the new copy which will be * patched */ - bp->base.bios_local_image = dm_alloc(bp->base.bios_size); + bp->base.bios_local_image = kzalloc(bp->base.bios_size, + GFP_KERNEL); if (bp->base.bios_local_image == NULL) { BREAK_TO_DEBUGGER(); /* Failed to alloc bp->base.bios_local_image */ @@ -3965,7 +3966,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -3975,7 +3976,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c index 95fe50f62c57..3f8e605efde9 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c @@ -107,10 +107,10 @@ static struct atom_encoder_caps_record *get_encoder_cap_record( static void destruct(struct bios_parser *bp) { if (bp->base.bios_local_image) - dm_free(bp->base.bios_local_image); + kfree(bp->base.bios_local_image); if (bp->base.integrated_info) - dm_free(bp->base.integrated_info); + kfree(bp->base.integrated_info); } static void firmware_parser_destroy(struct dc_bios **dcb) @@ -124,7 +124,7 @@ static void firmware_parser_destroy(struct dc_bios **dcb) destruct(bp); - dm_free(bp); + kfree(bp); *dcb = NULL; } @@ -2030,7 +2030,7 @@ static struct integrated_info *bios_parser_create_integrated_info( struct bios_parser *bp = BP_FROM_DCB(dcb); struct integrated_info *info = NULL; - info = dm_alloc(sizeof(struct integrated_info)); + info = kzalloc(sizeof(struct integrated_info), GFP_KERNEL); if (info == NULL) { ASSERT_CRITICAL(0); @@ -2040,7 +2040,7 @@ static struct integrated_info *bios_parser_create_integrated_info( if (construct_integrated_info(bp, info) == BP_RESULT_OK) return info; - dm_free(info); + kfree(info); return NULL; } @@ -2205,14 +2205,14 @@ struct dc_bios *firmware_parser_create( { struct bios_parser *bp = NULL; - bp = dm_alloc(sizeof(struct bios_parser)); + bp = kzalloc(sizeof(struct bios_parser), GFP_KERNEL); if (!bp) return NULL; if (bios_parser_construct(bp, init, dce_version)) return &bp->base; - dm_free(bp); + kfree(bp); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c index dba25853f7f9..15cbfc400633 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c @@ -2792,7 +2792,8 @@ bool bw_calcs(struct dc_context *ctx, int pipe_count, struct dce_bw_output *calcs_output) { - struct bw_calcs_data *data = dm_alloc(sizeof(struct bw_calcs_data)); + struct bw_calcs_data *data = kzalloc(sizeof(struct bw_calcs_data), + GFP_KERNEL); populate_initial_data(pipe, pipe_count, data); @@ -3248,7 +3249,7 @@ bool bw_calcs(struct dc_context *ctx, calcs_output->sclk_khz = 0; } - dm_free(data); + kfree(data); return is_display_configuration_supported(vbios, calcs_output); } diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index 1b0f64756be6..91f43a1b88ee 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -481,8 +481,8 @@ static void dcn_dml_wm_override( { int i, in_idx, active_count; - struct _vcs_dpi_display_e2e_pipe_params_st *input = dm_alloc(pool->pipe_count * - sizeof(struct _vcs_dpi_display_e2e_pipe_params_st)); + struct _vcs_dpi_display_e2e_pipe_params_st *input = kzalloc(pool->pipe_count * sizeof(struct _vcs_dpi_display_e2e_pipe_params_st), + GFP_KERNEL); struct wm { double urgent; struct _vcs_dpi_cstate_pstate_watermarks_st cpstate; @@ -560,7 +560,7 @@ static void dcn_dml_wm_override( pipe->plane_state->flip_immediate); in_idx++; } - dm_free(input); + kfree(input); } static void split_stream_across_pipes( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 58c5083bef2a..d86d9796e4cc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -113,7 +113,7 @@ static bool create_links( } for (i = 0; i < num_virtual_links; i++) { - struct dc_link *link = dm_alloc(sizeof(*link)); + struct dc_link *link = kzalloc(sizeof(*link), GFP_KERNEL); struct encoder_init_data enc_init = {0}; if (link == NULL) { @@ -127,7 +127,7 @@ static bool create_links( link->link_id.type = OBJECT_TYPE_CONNECTOR; link->link_id.id = CONNECTOR_ID_VIRTUAL; link->link_id.enum_id = ENUM_ID_1; - link->link_enc = dm_alloc(sizeof(*link->link_enc)); + link->link_enc = kzalloc(sizeof(*link->link_enc), GFP_KERNEL); enc_init.ctx = dc->ctx; enc_init.channel = CHANNEL_ID_UNKNOWN; @@ -413,20 +413,20 @@ static void destruct(struct dc *dc) if (dc->ctx->logger) dal_logger_destroy(&dc->ctx->logger); - dm_free(dc->ctx); + kfree(dc->ctx); dc->ctx = NULL; - dm_free(dc->bw_vbios); + kfree(dc->bw_vbios); dc->bw_vbios = NULL; - dm_free(dc->bw_dceip); + kfree(dc->bw_dceip); dc->bw_dceip = NULL; #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - dm_free(dc->dcn_soc); + kfree(dc->dcn_soc); dc->dcn_soc = NULL; - dm_free(dc->dcn_ip); + kfree(dc->dcn_ip); dc->dcn_ip = NULL; #endif @@ -436,12 +436,15 @@ static bool construct(struct dc *dc, const struct dc_init_data *init_params) { struct dal_logger *logger; - struct dc_context *dc_ctx = dm_alloc(sizeof(*dc_ctx)); - struct bw_calcs_dceip *dc_dceip = dm_alloc(sizeof(*dc_dceip)); - struct bw_calcs_vbios *dc_vbios = dm_alloc(sizeof(*dc_vbios)); + struct dc_context *dc_ctx = kzalloc(sizeof(*dc_ctx), GFP_KERNEL); + struct bw_calcs_dceip *dc_dceip = kzalloc(sizeof(*dc_dceip), + GFP_KERNEL); + struct bw_calcs_vbios *dc_vbios = kzalloc(sizeof(*dc_vbios), + GFP_KERNEL); #ifdef CONFIG_DRM_AMD_DC_DCN1_0 - struct dcn_soc_bounding_box *dcn_soc = dm_alloc(sizeof(*dcn_soc)); - struct dcn_ip_params *dcn_ip = dm_alloc(sizeof(*dcn_ip)); + struct dcn_soc_bounding_box *dcn_soc = kzalloc(sizeof(*dcn_soc), + GFP_KERNEL); + struct dcn_ip_params *dcn_ip = kzalloc(sizeof(*dcn_ip), GFP_KERNEL); #endif enum dce_version dc_version = DCE_VERSION_UNKNOWN; @@ -604,7 +607,7 @@ void ProgramPixelDurationV(unsigned int pixelClockInKHz ) struct dc *dc_create(const struct dc_init_data *init_params) { - struct dc *dc = dm_alloc(sizeof(*dc)); + struct dc *dc = kzalloc(sizeof(*dc), GFP_KERNEL); unsigned int full_pipe_count; if (NULL == dc) @@ -638,7 +641,7 @@ struct dc *dc_create(const struct dc_init_data *init_params) return dc; construct_fail: - dm_free(dc); + kfree(dc); alloc_fail: return NULL; @@ -647,7 +650,7 @@ alloc_fail: void dc_destroy(struct dc **dc) { destruct(*dc); - dm_free(*dc); + kfree(*dc); *dc = NULL; } @@ -900,7 +903,7 @@ bool dc_commit_planes_to_stream( struct dc_scaling_info scaling_info[MAX_SURFACES]; int i; struct dc_stream_update *stream_update = - dm_alloc(sizeof(struct dc_stream_update)); + kzalloc(sizeof(struct dc_stream_update), GFP_KERNEL); if (!stream_update) { BREAK_TO_DEBUGGER(); @@ -951,13 +954,14 @@ bool dc_commit_planes_to_stream( dc_post_update_surfaces_to_stream(dc); - dm_free(stream_update); + kfree(stream_update); return true; } struct dc_state *dc_create_state(void) { - struct dc_state *context = dm_alloc(sizeof(struct dc_state)); + struct dc_state *context = kzalloc(sizeof(struct dc_state), + GFP_KERNEL); if (!context) return NULL; @@ -979,7 +983,7 @@ void dc_release_state(struct dc_state *context) if (atomic_read(&context->ref_count) == 0) { dc_resource_state_destruct(context); - dm_free(context); + kfree(context); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c index 845ec421d861..43ebd8941b77 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c @@ -1100,7 +1100,7 @@ create_fail: struct dc_link *link_create(const struct link_init_data *init_params) { struct dc_link *link = - dm_alloc(sizeof(*link)); + kzalloc(sizeof(*link), GFP_KERNEL); if (NULL == link) goto alloc_fail; @@ -1111,7 +1111,7 @@ struct dc_link *link_create(const struct link_init_data *init_params) return link; construct_fail: - dm_free(link); + kfree(link); alloc_fail: return NULL; @@ -1120,7 +1120,7 @@ alloc_fail: void link_destroy(struct dc_link **link) { destruct(*link); - dm_free(*link); + kfree(*link); *link = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c index d09e539397ea..226512c11ab7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c @@ -130,7 +130,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ { struct i2c_payloads *payloads; - payloads = dm_alloc(sizeof(struct i2c_payloads)); + payloads = kzalloc(sizeof(struct i2c_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -139,7 +139,7 @@ struct i2c_payloads *dal_ddc_i2c_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct i2c_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -159,7 +159,7 @@ void dal_ddc_i2c_payloads_destroy(struct i2c_payloads **p) if (!p || !*p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -168,7 +168,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ { struct aux_payloads *payloads; - payloads = dm_alloc(sizeof(struct aux_payloads)); + payloads = kzalloc(sizeof(struct aux_payloads), GFP_KERNEL); if (!payloads) return NULL; @@ -177,7 +177,7 @@ struct aux_payloads *dal_ddc_aux_payloads_create(struct dc_context *ctx, uint32_ &payloads->payloads, ctx, count, sizeof(struct aux_payload))) return payloads; - dm_free(payloads); + kfree(payloads); return NULL; } @@ -197,7 +197,7 @@ void dal_ddc_aux_payloads_destroy(struct aux_payloads **p) return; dal_vector_destruct(&(*p)->payloads); - dm_free(*p); + kfree(*p); *p = NULL; } @@ -290,7 +290,7 @@ struct ddc_service *dal_ddc_service_create( { struct ddc_service *ddc_service; - ddc_service = dm_alloc(sizeof(struct ddc_service)); + ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL); if (!ddc_service) return NULL; @@ -298,7 +298,7 @@ struct ddc_service *dal_ddc_service_create( if (construct(ddc_service, init_data)) return ddc_service; - dm_free(ddc_service); + kfree(ddc_service); return NULL; } @@ -315,7 +315,7 @@ void dal_ddc_service_destroy(struct ddc_service **ddc) return; } destruct(*ddc); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index dcfdfebd5c62..1832f252edab 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -160,7 +160,7 @@ void dc_destroy_resource_pool(struct dc *dc) dc->res_pool->funcs->destroy(&dc->res_pool); if (dc->hwseq) - dm_free(dc->hwseq); + kfree(dc->hwseq); } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c index 7717350297a5..b3bbafc8fd6a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_sink.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_sink.c @@ -34,7 +34,7 @@ static void destruct(struct dc_sink *sink) { if (sink->dc_container_id) { - dm_free(sink->dc_container_id); + kfree(sink->dc_container_id); sink->dc_container_id = NULL; } } @@ -74,13 +74,13 @@ void dc_sink_release(struct dc_sink *sink) if (atomic_read(&sink->ref_count) == 0) { destruct(sink); - dm_free(sink); + kfree(sink); } } struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) { - struct dc_sink *sink = dm_alloc(sizeof(*sink)); + struct dc_sink *sink = kzalloc(sizeof(*sink), GFP_KERNEL); if (NULL == sink) goto alloc_fail; @@ -93,7 +93,7 @@ struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params) return sink; construct_fail: - dm_free(sink); + kfree(sink); alloc_fail: return NULL; @@ -117,7 +117,8 @@ bool dc_sink_set_container_id(struct dc_sink *dc_sink, const struct dc_container { if (dc_sink && container_id) { if (!dc_sink->dc_container_id) - dc_sink->dc_container_id = dm_alloc(sizeof(*dc_sink->dc_container_id)); + dc_sink->dc_container_id = kzalloc(sizeof(*dc_sink->dc_container_id), + GFP_KERNEL); if (dc_sink->dc_container_id) { memmove(&dc_sink->dc_container_id->guid, &container_id->guid, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index a421779093d9..d5da847ffad6 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -131,7 +131,7 @@ void dc_stream_release(struct dc_stream_state *stream) if (atomic_read(&stream->ref_count) == 0) { destruct(stream); - dm_free(stream); + kfree(stream); } } } @@ -144,7 +144,7 @@ struct dc_stream_state *dc_create_stream_for_sink( if (sink == NULL) goto alloc_fail; - stream = dm_alloc(sizeof(struct dc_stream_state)); + stream = kzalloc(sizeof(struct dc_stream_state), GFP_KERNEL); if (NULL == stream) goto alloc_fail; @@ -157,7 +157,7 @@ struct dc_stream_state *dc_create_stream_for_sink( return stream; construct_fail: - dm_free(stream); + kfree(stream); alloc_fail: return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c index e96f63eed070..511ada94530e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c @@ -68,7 +68,8 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) { struct dc *core_dc = dc; - struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state)); + struct dc_plane_state *plane_state = kzalloc(sizeof(*plane_state), + GFP_KERNEL); if (NULL == plane_state) goto alloc_fail; @@ -81,7 +82,7 @@ struct dc_plane_state *dc_create_plane_state(struct dc *dc) return plane_state; construct_fail: - dm_free(plane_state); + kfree(plane_state); alloc_fail: return NULL; @@ -133,7 +134,7 @@ void dc_plane_state_release(struct dc_plane_state *plane_state) if (atomic_read(&plane_state->ref_count) == 0) { destruct(plane_state); - dm_free(plane_state); + kfree(plane_state); } } @@ -149,14 +150,14 @@ void dc_gamma_release(struct dc_gamma **gamma) atomic_dec(&(*gamma)->ref_count); if (atomic_read(&(*gamma)->ref_count) == 0) - dm_free((*gamma)); + kfree((*gamma)); *gamma = NULL; } struct dc_gamma *dc_create_gamma() { - struct dc_gamma *gamma = dm_alloc(sizeof(*gamma)); + struct dc_gamma *gamma = kzalloc(sizeof(*gamma), GFP_KERNEL); if (gamma == NULL) goto alloc_fail; @@ -181,12 +182,12 @@ void dc_transfer_func_release(struct dc_transfer_func *tf) atomic_dec(&tf->ref_count); if (atomic_read(&tf->ref_count) == 0) - dm_free(tf); + kfree(tf); } struct dc_transfer_func *dc_create_transfer_func() { - struct dc_transfer_func *tf = dm_alloc(sizeof(*tf)); + struct dc_transfer_func *tf = kzalloc(sizeof(*tf), GFP_KERNEL); if (tf == NULL) goto alloc_fail; diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c index 0e9d914e1a8f..0e0336c5af4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.c @@ -462,7 +462,7 @@ struct abm *dce_abm_create( const struct dce_abm_shift *abm_shift, const struct dce_abm_mask *abm_mask) { - struct dce_abm *abm_dce = dm_alloc(sizeof(*abm_dce)); + struct dce_abm *abm_dce = kzalloc(sizeof(*abm_dce), GFP_KERNEL); if (abm_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -480,6 +480,6 @@ void dce_abm_destroy(struct abm **abm) { struct dce_abm *abm_dce = TO_DCE_ABM(*abm); - dm_free(abm_dce); + kfree(abm_dce); *abm = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c index b94c1e5d85cb..198f4532e100 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_audio.c @@ -897,7 +897,7 @@ void dce_aud_destroy(struct audio **audio) { struct dce_audio *aud = DCE_AUD(*audio); - dm_free(aud); + kfree(aud); *audio = NULL; } @@ -909,7 +909,7 @@ struct audio *dce_audio_create( const struct dce_aduio_mask *masks ) { - struct dce_audio *audio = dm_alloc(sizeof(*audio)); + struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); if (audio == NULL) { ASSERT_CRITICAL(audio); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index d3b61b92ebec..31280d252753 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1084,12 +1084,14 @@ static void get_ss_info_from_atombios( if (*ss_entries_num == 0) return; - ss_info = dm_alloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num)); + ss_info = kzalloc(sizeof(struct spread_spectrum_info) * (*ss_entries_num), + GFP_KERNEL); ss_info_cur = ss_info; if (ss_info == NULL) return; - ss_data = dm_alloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num)); + ss_data = kzalloc(sizeof(struct spread_spectrum_data) * (*ss_entries_num), + GFP_KERNEL); if (ss_data == NULL) goto out_free_info; @@ -1157,14 +1159,14 @@ static void get_ss_info_from_atombios( } *spread_spectrum_data = ss_data; - dm_free(ss_info); + kfree(ss_info); return; out_free_data: - dm_free(ss_data); + kfree(ss_data); *ss_entries_num = 0; out_free_info: - dm_free(ss_info); + kfree(ss_info); } static void ss_info_from_atombios_create( diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c index 06d9a3e7c8a2..3e9ff2f5472d 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c @@ -719,7 +719,7 @@ struct display_clock *dce_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -742,7 +742,7 @@ struct display_clock *dce110_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -767,7 +767,7 @@ struct display_clock *dce112_disp_clk_create( const struct dce_disp_clk_shift *clk_shift, const struct dce_disp_clk_mask *clk_mask) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); if (clk_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -788,7 +788,7 @@ struct display_clock *dce112_disp_clk_create( struct display_clock *dce120_disp_clk_create(struct dc_context *ctx) { - struct dce_disp_clk *clk_dce = dm_alloc(sizeof(*clk_dce)); + struct dce_disp_clk *clk_dce = kzalloc(sizeof(*clk_dce), GFP_KERNEL); struct dm_pp_clock_levels_with_voltage clk_level_info = {0}; if (clk_dce == NULL) { @@ -822,6 +822,6 @@ void dce_disp_clk_destroy(struct display_clock **disp_clk) { struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(*disp_clk); - dm_free(clk_dce); + kfree(clk_dce); *disp_clk = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c index 313f61bf06e1..f9873cad40e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c @@ -573,7 +573,7 @@ struct dmcu *dce_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -595,7 +595,7 @@ struct dmcu *dcn10_dmcu_create( const struct dce_dmcu_shift *dmcu_shift, const struct dce_dmcu_mask *dmcu_mask) { - struct dce_dmcu *dmcu_dce = dm_alloc(sizeof(*dmcu_dce)); + struct dce_dmcu *dmcu_dce = kzalloc(sizeof(*dmcu_dce), GFP_KERNEL); if (dmcu_dce == NULL) { BREAK_TO_DEBUGGER(); @@ -615,6 +615,6 @@ void dce_dmcu_destroy(struct dmcu **dmcu) { struct dce_dmcu *dmcu_dce = TO_DCE_DMCU(*dmcu); - dm_free(dmcu_dce); + kfree(dmcu_dce); *dmcu = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c index e010cf10d605..fa481d481132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_ipp.c @@ -261,6 +261,6 @@ void dce_ipp_construct( void dce_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCE_IPP(*ipp)); + kfree(TO_DCE_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c index 0ce94ede80bf..2ce730de0dc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c @@ -1108,7 +1108,7 @@ void dce110_link_encoder_hw_init( void dce110_link_encoder_destroy(struct link_encoder **enc) { - dm_free(TO_DCE110_LINK_ENC(*enc)); + kfree(TO_DCE110_LINK_ENC(*enc)); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c index 348e4b7047f1..c0736aeabd85 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_opp.c @@ -563,7 +563,7 @@ bool dce110_opp_construct(struct dce110_opp *opp110, void dce110_opp_destroy(struct output_pixel_processor **opp) { if (*opp) - dm_free(FROM_DCE11_OPP(*opp)); + kfree(FROM_DCE11_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index ca6c7c2a1b4c..9a75bde32611 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -370,7 +370,7 @@ static struct timing_generator *dce100_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -380,7 +380,7 @@ static struct timing_generator *dce100_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -389,7 +389,7 @@ static struct stream_encoder *dce100_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -400,7 +400,7 @@ static struct stream_encoder *dce100_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -422,7 +422,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce100_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -467,7 +467,8 @@ static struct mem_input *dce100_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -481,7 +482,7 @@ static struct mem_input *dce100_mem_input_create( static void dce100_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -490,7 +491,7 @@ static struct transform *dce100_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -501,14 +502,14 @@ static struct transform *dce100_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce100_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -532,7 +533,7 @@ struct link_encoder *dce100_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -549,7 +550,7 @@ struct link_encoder *dce100_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -558,7 +559,7 @@ struct output_pixel_processor *dce100_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -568,7 +569,7 @@ struct output_pixel_processor *dce100_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -580,7 +581,7 @@ struct clock_source *dce100_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -597,7 +598,7 @@ struct clock_source *dce100_clock_source_create( void dce100_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -616,19 +617,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -768,7 +769,7 @@ static void dce100_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -950,7 +951,7 @@ struct resource_pool *dce100_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c index f82c26995609..90770cb2ffcd 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_compressor.c @@ -388,7 +388,7 @@ void dce110_compressor_set_fbc_invalidation_triggers( struct compressor *dce110_compressor_create(struct dc_context *ctx) { struct dce110_compressor *cp110 = - dm_alloc(sizeof(struct dce110_compressor)); + kzalloc(sizeof(struct dce110_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -397,13 +397,13 @@ struct compressor *dce110_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce110_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE110_COMPRESSOR(*compressor)); + kfree(TO_DCE110_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 25eda52c32ef..787e20e15221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -405,7 +405,7 @@ static struct timing_generator *dce110_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -414,7 +414,7 @@ static struct timing_generator *dce110_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -423,7 +423,7 @@ static struct stream_encoder *dce110_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -434,7 +434,7 @@ static struct stream_encoder *dce110_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -460,7 +460,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce110_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -505,7 +505,8 @@ static struct mem_input *dce110_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -519,7 +520,7 @@ static struct mem_input *dce110_mem_input_create( static void dce110_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -528,7 +529,7 @@ static struct transform *dce110_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -538,14 +539,14 @@ static struct transform *dce110_transform_create( return &transform->base; BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } static struct input_pixel_processor *dce110_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -569,7 +570,7 @@ static struct link_encoder *dce110_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -586,7 +587,7 @@ static struct link_encoder *dce110_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -595,7 +596,7 @@ static struct output_pixel_processor *dce110_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ static struct output_pixel_processor *dce110_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce110_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -642,15 +643,15 @@ void dce110_clock_source_destroy(struct clock_source **clk_src) dce110_clk_src = TO_DCE110_CLK_SRC(*clk_src); if (dce110_clk_src->dp_ss_params) - dm_free(dce110_clk_src->dp_ss_params); + kfree(dce110_clk_src->dp_ss_params); if (dce110_clk_src->hdmi_ss_params) - dm_free(dce110_clk_src->hdmi_ss_params); + kfree(dce110_clk_src->hdmi_ss_params); if (dce110_clk_src->dvi_ss_params) - dm_free(dce110_clk_src->dvi_ss_params); + kfree(dce110_clk_src->dvi_ss_params); - dm_free(dce110_clk_src); + kfree(dce110_clk_src); *clk_src = NULL; } @@ -669,19 +670,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -1031,7 +1032,7 @@ static void dce110_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1048,10 +1049,14 @@ static const struct resource_funcs dce110_res_pool_funcs = { static bool underlay_create(struct dc_context *ctx, struct resource_pool *pool) { - struct dce110_timing_generator *dce110_tgv = dm_alloc(sizeof (*dce110_tgv)); - struct dce_transform *dce110_xfmv = dm_alloc(sizeof (*dce110_xfmv)); - struct dce_mem_input *dce110_miv = dm_alloc(sizeof (*dce110_miv)); - struct dce110_opp *dce110_oppv = dm_alloc(sizeof (*dce110_oppv)); + struct dce110_timing_generator *dce110_tgv = kzalloc(sizeof(*dce110_tgv), + GFP_KERNEL); + struct dce_transform *dce110_xfmv = kzalloc(sizeof(*dce110_xfmv), + GFP_KERNEL); + struct dce_mem_input *dce110_miv = kzalloc(sizeof(*dce110_miv), + GFP_KERNEL); + struct dce110_opp *dce110_oppv = kzalloc(sizeof(*dce110_oppv), + GFP_KERNEL); if ((dce110_tgv == NULL) || (dce110_xfmv == NULL) || @@ -1332,7 +1337,7 @@ struct resource_pool *dce110_create_resource_pool( struct hw_asic_id asic_id) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c index 75af2125344b..e75895baa132 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_compressor.c @@ -839,7 +839,7 @@ bool dce112_compressor_construct(struct dce112_compressor *compressor, struct compressor *dce112_compressor_create(struct dc_context *ctx) { struct dce112_compressor *cp110 = - dm_alloc(sizeof(struct dce112_compressor)); + kzalloc(sizeof(struct dce112_compressor), GFP_KERNEL); if (!cp110) return NULL; @@ -848,12 +848,12 @@ struct compressor *dce112_compressor_create(struct dc_context *ctx) return &cp110->base; BREAK_TO_DEBUGGER(); - dm_free(cp110); + kfree(cp110); return NULL; } void dce112_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE112_COMPRESSOR(*compressor)); + kfree(TO_DCE112_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index de6f71d8a89b..4e2ed3429a90 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -410,7 +410,7 @@ static struct timing_generator *dce112_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -419,7 +419,7 @@ static struct timing_generator *dce112_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -428,7 +428,7 @@ static struct stream_encoder *dce112_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -439,7 +439,7 @@ static struct stream_encoder *dce112_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -461,7 +461,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce112_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -501,7 +501,8 @@ static struct mem_input *dce112_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -514,7 +515,7 @@ static struct mem_input *dce112_mem_input_create( static void dce112_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -523,7 +524,7 @@ static struct transform *dce112_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -535,7 +536,7 @@ static struct transform *dce112_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -554,7 +555,7 @@ struct link_encoder *dce112_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -571,14 +572,14 @@ struct link_encoder *dce112_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce112_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -595,7 +596,7 @@ struct output_pixel_processor *dce112_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -605,7 +606,7 @@ struct output_pixel_processor *dce112_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -617,7 +618,7 @@ struct clock_source *dce112_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -634,7 +635,7 @@ struct clock_source *dce112_clock_source_create( void dce112_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -653,19 +654,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -940,7 +941,7 @@ static void dce112_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1298,7 +1299,7 @@ struct resource_pool *dce112_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index e5d2d98982f7..6b5d5948ddb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -351,7 +351,7 @@ struct output_pixel_processor *dce120_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -361,7 +361,7 @@ struct output_pixel_processor *dce120_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -388,7 +388,7 @@ struct clock_source *dce120_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(*clk_src)); + kzalloc(sizeof(*clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -405,7 +405,7 @@ struct clock_source *dce120_clock_source_create( void dce120_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } @@ -428,7 +428,7 @@ static struct timing_generator *dce120_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -437,13 +437,13 @@ static struct timing_generator *dce120_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } static void dce120_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -462,7 +462,7 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -471,7 +471,7 @@ static void destruct(struct dce110_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } @@ -483,7 +483,7 @@ static void destruct(struct dce110_resource_pool *pool) for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -539,7 +539,7 @@ static struct link_encoder *dce120_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -556,14 +556,14 @@ static struct link_encoder *dce120_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } static struct input_pixel_processor *dce120_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -580,7 +580,7 @@ static struct stream_encoder *dce120_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -591,7 +591,7 @@ static struct stream_encoder *dce120_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -614,7 +614,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce120_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -654,7 +654,8 @@ static struct mem_input *dce120_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -670,7 +671,7 @@ static struct transform *dce120_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -682,7 +683,7 @@ static struct transform *dce120_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -691,7 +692,7 @@ static void dce120_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -1006,7 +1007,7 @@ struct resource_pool *dce120_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c index 77626d7624c6..cc1c0d390945 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_compressor.c @@ -819,7 +819,7 @@ bool dce80_compressor_construct(struct dce80_compressor *compressor, struct compressor *dce80_compressor_create(struct dc_context *ctx) { struct dce80_compressor *cp80 = - dm_alloc(sizeof(struct dce80_compressor)); + kzalloc(sizeof(struct dce80_compressor), GFP_KERNEL); if (!cp80) return NULL; @@ -828,12 +828,12 @@ struct compressor *dce80_compressor_create(struct dc_context *ctx) return &cp80->base; BREAK_TO_DEBUGGER(); - dm_free(cp80); + kfree(cp80); return NULL; } void dce80_compressor_destroy(struct compressor **compressor) { - dm_free(TO_DCE80_COMPRESSOR(*compressor)); + kfree(TO_DCE80_COMPRESSOR(*compressor)); *compressor = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 5453f02ea8ca..170509a4a221 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -399,7 +399,7 @@ static struct timing_generator *dce80_timing_generator_create( const struct dce110_timing_generator_offsets *offsets) { struct dce110_timing_generator *tg110 = - dm_alloc(sizeof(struct dce110_timing_generator)); + kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); if (!tg110) return NULL; @@ -408,7 +408,7 @@ static struct timing_generator *dce80_timing_generator_create( return &tg110->base; BREAK_TO_DEBUGGER(); - dm_free(tg110); + kfree(tg110); return NULL; } @@ -417,7 +417,7 @@ static struct output_pixel_processor *dce80_opp_create( uint32_t inst) { struct dce110_opp *opp = - dm_alloc(sizeof(struct dce110_opp)); + kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); if (!opp) return NULL; @@ -427,7 +427,7 @@ static struct output_pixel_processor *dce80_opp_create( return &opp->base; BREAK_TO_DEBUGGER(); - dm_free(opp); + kfree(opp); return NULL; } @@ -436,7 +436,7 @@ static struct stream_encoder *dce80_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -447,7 +447,7 @@ static struct stream_encoder *dce80_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -469,7 +469,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dce80_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -514,7 +514,8 @@ static struct mem_input *dce80_mem_input_create( struct dc_context *ctx, uint32_t inst) { - struct dce_mem_input *dce_mi = dm_alloc(sizeof(struct dce_mem_input)); + struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), + GFP_KERNEL); if (!dce_mi) { BREAK_TO_DEBUGGER(); @@ -528,7 +529,7 @@ static struct mem_input *dce80_mem_input_create( static void dce80_transform_destroy(struct transform **xfm) { - dm_free(TO_DCE_TRANSFORM(*xfm)); + kfree(TO_DCE_TRANSFORM(*xfm)); *xfm = NULL; } @@ -537,7 +538,7 @@ static struct transform *dce80_transform_create( uint32_t inst) { struct dce_transform *transform = - dm_alloc(sizeof(struct dce_transform)); + kzalloc(sizeof(struct dce_transform), GFP_KERNEL); if (!transform) return NULL; @@ -549,7 +550,7 @@ static struct transform *dce80_transform_create( } BREAK_TO_DEBUGGER(); - dm_free(transform); + kfree(transform); return NULL; } @@ -565,7 +566,7 @@ struct link_encoder *dce80_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -582,7 +583,7 @@ struct link_encoder *dce80_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -594,7 +595,7 @@ struct clock_source *dce80_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -611,14 +612,14 @@ struct clock_source *dce80_clock_source_create( void dce80_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct input_pixel_processor *dce80_ipp_create( struct dc_context *ctx, uint32_t inst) { - struct dce_ipp *ipp = dm_alloc(sizeof(struct dce_ipp)); + struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -645,19 +646,19 @@ static void destruct(struct dce110_resource_pool *pool) dce_ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCE_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCE110TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.clk_src_count; i++) { @@ -781,7 +782,7 @@ static void dce80_destroy_resource_pool(struct resource_pool **pool) struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); destruct(dce110_pool); - dm_free(dce110_pool); + kfree(dce110_pool); *pool = NULL; } @@ -948,7 +949,7 @@ struct resource_pool *dce80_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1113,7 +1114,7 @@ struct resource_pool *dce81_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; @@ -1274,7 +1275,7 @@ struct resource_pool *dce83_create_resource_pool( struct dc *dc) { struct dce110_resource_pool *pool = - dm_alloc(sizeof(struct dce110_resource_pool)); + kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c index 5e0e2464eab3..67bd6a738fe9 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.c @@ -225,7 +225,7 @@ static void ippn10_cursor_set_position( static void dcn10_ipp_destroy(struct input_pixel_processor **ipp) { - dm_free(TO_DCN10_IPP(*ipp)); + kfree(TO_DCN10_IPP(*ipp)); *ipp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c index 8048782ac599..a136f70b7a3c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c @@ -314,7 +314,7 @@ static void oppn10_set_stereo_polarity( static void dcn10_opp_destroy(struct output_pixel_processor **opp) { - dm_free(TO_DCN10_OPP(*opp)); + kfree(TO_DCN10_OPP(*opp)); *opp = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 298eb44ad9bf..71adda0e5b59 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -468,7 +468,7 @@ static const struct dc_debug debug_defaults_diags = { static void dcn10_dpp_destroy(struct transform **xfm) { - dm_free(TO_DCN10_DPP(*xfm)); + kfree(TO_DCN10_DPP(*xfm)); *xfm = NULL; } @@ -477,7 +477,7 @@ static struct transform *dcn10_dpp_create( uint32_t inst) { struct dcn10_dpp *dpp = - dm_alloc(sizeof(struct dcn10_dpp)); + kzalloc(sizeof(struct dcn10_dpp), GFP_KERNEL); if (!dpp) return NULL; @@ -487,7 +487,7 @@ static struct transform *dcn10_dpp_create( return &dpp->base; BREAK_TO_DEBUGGER(); - dm_free(dpp); + kfree(dpp); return NULL; } @@ -495,7 +495,7 @@ static struct input_pixel_processor *dcn10_ipp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_ipp *ipp = - dm_alloc(sizeof(struct dcn10_ipp)); + kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL); if (!ipp) { BREAK_TO_DEBUGGER(); @@ -512,7 +512,7 @@ static struct output_pixel_processor *dcn10_opp_create( struct dc_context *ctx, uint32_t inst) { struct dcn10_opp *opp = - dm_alloc(sizeof(struct dcn10_opp)); + kzalloc(sizeof(struct dcn10_opp), GFP_KERNEL); if (!opp) { BREAK_TO_DEBUGGER(); @@ -526,7 +526,8 @@ static struct output_pixel_processor *dcn10_opp_create( static struct mpc *dcn10_mpc_create(struct dc_context *ctx) { - struct dcn10_mpc *mpc10 = dm_alloc(sizeof(struct dcn10_mpc)); + struct dcn10_mpc *mpc10 = kzalloc(sizeof(struct dcn10_mpc), + GFP_KERNEL); if (!mpc10) return NULL; @@ -545,7 +546,7 @@ static struct timing_generator *dcn10_timing_generator_create( uint32_t instance) { struct dcn10_timing_generator *tgn10 = - dm_alloc(sizeof(struct dcn10_timing_generator)); + kzalloc(sizeof(struct dcn10_timing_generator), GFP_KERNEL); if (!tgn10) return NULL; @@ -577,7 +578,7 @@ struct link_encoder *dcn10_link_encoder_create( const struct encoder_init_data *enc_init_data) { struct dce110_link_encoder *enc110 = - dm_alloc(sizeof(struct dce110_link_encoder)); + kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -594,7 +595,7 @@ struct link_encoder *dcn10_link_encoder_create( } BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -606,7 +607,7 @@ struct clock_source *dcn10_clock_source_create( bool dp_clk_src) { struct dce110_clk_src *clk_src = - dm_alloc(sizeof(struct dce110_clk_src)); + kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); if (!clk_src) return NULL; @@ -641,7 +642,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( struct dc_context *ctx) { struct dce110_stream_encoder *enc110 = - dm_alloc(sizeof(struct dce110_stream_encoder)); + kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); if (!enc110) return NULL; @@ -652,7 +653,7 @@ static struct stream_encoder *dcn10_stream_encoder_create( return &enc110->base; BREAK_TO_DEBUGGER(); - dm_free(enc110); + kfree(enc110); return NULL; } @@ -671,7 +672,7 @@ static const struct dce_hwseq_mask hwseq_mask = { static struct dce_hwseq *dcn10_hwseq_create( struct dc_context *ctx) { - struct dce_hwseq *hws = dm_alloc(sizeof(struct dce_hwseq)); + struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); if (hws) { hws->ctx = ctx; @@ -698,13 +699,13 @@ static const struct resource_create_funcs res_create_maximus_funcs = { void dcn10_clock_source_destroy(struct clock_source **clk_src) { - dm_free(TO_DCE110_CLK_SRC(*clk_src)); + kfree(TO_DCE110_CLK_SRC(*clk_src)); *clk_src = NULL; } static struct pp_smu_funcs_rv *dcn10_pp_smu_create(struct dc_context *ctx) { - struct pp_smu_funcs_rv *pp_smu = dm_alloc(sizeof(*pp_smu)); + struct pp_smu_funcs_rv *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL); if (!pp_smu) return pp_smu; @@ -722,13 +723,13 @@ static void destruct(struct dcn10_resource_pool *pool) /* TODO: free dcn version of stream encoder once implemented * rather than using virtual stream encoder */ - dm_free(pool->base.stream_enc[i]); + kfree(pool->base.stream_enc[i]); pool->base.stream_enc[i] = NULL; } } if (pool->base.mpc != NULL) { - dm_free(TO_DCN10_MPC(pool->base.mpc)); + kfree(TO_DCN10_MPC(pool->base.mpc)); pool->base.mpc = NULL; } for (i = 0; i < pool->base.pipe_count; i++) { @@ -742,7 +743,7 @@ static void destruct(struct dcn10_resource_pool *pool) pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]); if (pool->base.mis[i] != NULL) { - dm_free(TO_DCN10_MEM_INPUT(pool->base.mis[i])); + kfree(TO_DCN10_MEM_INPUT(pool->base.mis[i])); pool->base.mis[i] = NULL; } @@ -751,14 +752,14 @@ static void destruct(struct dcn10_resource_pool *pool) } if (pool->base.timing_generators[i] != NULL) { - dm_free(DCN10TG_FROM_TG(pool->base.timing_generators[i])); + kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i])); pool->base.timing_generators[i] = NULL; } } for (i = 0; i < pool->base.stream_enc_count; i++) { if (pool->base.stream_enc[i] != NULL) - dm_free(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); + kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); } for (i = 0; i < pool->base.audio_count; i++) { @@ -767,7 +768,7 @@ static void destruct(struct dcn10_resource_pool *pool) } for (i = 0; i < pool->base.res_cap->num_dwb; i++) { - dm_free(pool->base.dwbc[i]); + kfree(pool->base.dwbc[i]); pool->base.dwbc[i] = NULL; } @@ -792,7 +793,7 @@ static void destruct(struct dcn10_resource_pool *pool) if (pool->base.display_clock != NULL) dce_disp_clk_destroy(&pool->base.display_clock); - dm_free(pool->base.pp_smu); + kfree(pool->base.pp_smu); } static struct mem_input *dcn10_mem_input_create( @@ -800,7 +801,7 @@ static struct mem_input *dcn10_mem_input_create( uint32_t inst) { struct dcn10_mem_input *mem_inputn10 = - dm_alloc(sizeof(struct dcn10_mem_input)); + kzalloc(sizeof(struct dcn10_mem_input), GFP_KERNEL); if (!mem_inputn10) return NULL; @@ -810,7 +811,7 @@ static struct mem_input *dcn10_mem_input_create( return &mem_inputn10->base; BREAK_TO_DEBUGGER(); - dm_free(mem_inputn10); + kfree(mem_inputn10); return NULL; } @@ -1207,7 +1208,7 @@ static void dcn10_destroy_resource_pool(struct resource_pool **pool) struct dcn10_resource_pool *dcn10_pool = TO_DCN10_RES_POOL(*pool); destruct(dcn10_pool); - dm_free(dcn10_pool); + kfree(dcn10_pool); *pool = NULL; } @@ -1239,7 +1240,8 @@ static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool uint32_t dwb_count = pool->res_cap->num_dwb; for (i = 0; i < dwb_count; i++) { - struct dcn10_dwbc *dwbc10 = dm_alloc(sizeof(struct dcn10_dwbc)); + struct dcn10_dwbc *dwbc10 = kzalloc(sizeof(struct dcn10_dwbc), + GFP_KERNEL); if (!dwbc10) { dm_error("DC: failed to create dwbc10!\n"); @@ -1517,7 +1519,7 @@ struct resource_pool *dcn10_create_resource_pool( struct dc *dc) { struct dcn10_resource_pool *pool = - dm_alloc(sizeof(struct dcn10_resource_pool)); + kzalloc(sizeof(struct dcn10_resource_pool), GFP_KERNEL); if (!pool) return NULL; diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c index d42eb3de2ea4..1d1efd72b291 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_base.c @@ -239,7 +239,7 @@ struct gpio *dal_gpio_create( uint32_t en, enum gpio_pin_output_state output_state) { - struct gpio *gpio = dm_alloc(sizeof(struct gpio)); + struct gpio *gpio = kzalloc(sizeof(struct gpio), GFP_KERNEL); if (!gpio) { ASSERT_CRITICAL(false); @@ -266,7 +266,7 @@ void dal_gpio_destroy( dal_gpio_close(*gpio); - dm_free(*gpio); + kfree(*gpio); *gpio = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c index eeb1cd0f75a6..d4e5ef64e489 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/gpio_service.c @@ -59,7 +59,7 @@ struct gpio_service *dal_gpio_service_create( uint32_t index_of_id; - service = dm_alloc(sizeof(struct gpio_service)); + service = kzalloc(sizeof(struct gpio_service), GFP_KERNEL); if (!service) { BREAK_TO_DEBUGGER(); @@ -98,7 +98,8 @@ struct gpio_service *dal_gpio_service_create( if (number_of_bits) { uint32_t index_of_uint = 0; - slot = dm_alloc(number_of_uints * sizeof(uint32_t)); + slot = kzalloc(number_of_uints * sizeof(uint32_t), + GFP_KERNEL); if (!slot) { BREAK_TO_DEBUGGER(); @@ -130,11 +131,11 @@ failure_2: slot = service->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); }; failure_1: - dm_free(service); + kfree(service); return NULL; } @@ -171,13 +172,13 @@ void dal_gpio_service_destroy( uint32_t *slot = (*ptr)->busyness[index_of_id]; if (slot) - dm_free(slot); + kfree(slot); ++index_of_id; } while (index_of_id < GPIO_ID_COUNT); } - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -399,7 +400,7 @@ void dal_gpio_destroy_irq( dal_gpio_close(*irq); dal_gpio_destroy(irq); - dm_free(*irq); + kfree(*irq); *irq = NULL; } @@ -417,7 +418,7 @@ struct ddc *dal_gpio_create_ddc( if (!service->translate.funcs->offset_to_id(offset, mask, &id, &en)) return NULL; - ddc = dm_alloc(sizeof(struct ddc)); + ddc = kzalloc(sizeof(struct ddc), GFP_KERNEL); if (!ddc) { BREAK_TO_DEBUGGER(); @@ -450,7 +451,7 @@ failure_2: dal_gpio_destroy(&ddc->pin_data); failure_1: - dm_free(ddc); + kfree(ddc); return NULL; } @@ -466,7 +467,7 @@ void dal_gpio_destroy_ddc( dal_ddc_close(*ddc); dal_gpio_destroy(&(*ddc)->pin_data); dal_gpio_destroy(&(*ddc)->pin_clock); - dm_free(*ddc); + kfree(*ddc); *ddc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c index 47e0f8f24a86..7b6efa4f2efd 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c @@ -55,7 +55,7 @@ static void destroy( destruct(pin); - dm_free(pin); + kfree(pin); *ptr = NULL; } @@ -225,7 +225,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( enum gpio_id id, uint32_t en) { - struct hw_ddc *pin = dm_alloc(sizeof(struct hw_ddc)); + struct hw_ddc *pin = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); if (!pin) { ASSERT_CRITICAL(false); @@ -237,7 +237,7 @@ struct hw_gpio_pin *dal_hw_ddc_create( ASSERT_CRITICAL(false); - dm_free(pin); + kfree(pin); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c index f7d049c0e62a..87b580fa4bc9 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c @@ -101,7 +101,7 @@ void dal_hw_factory_destroy( return; } - dm_free(*factory); + kfree(*factory); *factory = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c index 9634e8841d90..0c255c02045b 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c +++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c @@ -72,7 +72,7 @@ static void destroy( destruct(hpd); - dm_free(hpd); + kfree(hpd); *ptr = NULL; } @@ -157,7 +157,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( enum gpio_id id, uint32_t en) { - struct hw_hpd *hpd = dm_alloc(sizeof(struct hw_hpd)); + struct hw_hpd *hpd = kzalloc(sizeof(struct hw_hpd), GFP_KERNEL); if (!hpd) { ASSERT_CRITICAL(false); @@ -169,7 +169,7 @@ struct hw_gpio_pin *dal_hw_hpd_create( ASSERT_CRITICAL(false); - dm_free(hpd); + kfree(hpd); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c index 0712cafb4c42..c45a2ee8c336 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce100/i2caux_dce100.c @@ -88,7 +88,7 @@ struct i2caux *dal_i2caux_dce100_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -106,7 +106,7 @@ struct i2caux *dal_i2caux_dce100_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c index d3eaf8977a60..4b673b48bf42 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c @@ -87,7 +87,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *aux_engine = NULL; } @@ -464,7 +464,7 @@ struct aux_engine *dal_aux_engine_dce110_create( return NULL; } - engine = dm_alloc(sizeof(*engine)); + engine = kzalloc(sizeof(*engine), GFP_KERNEL); if (!engine) { ASSERT_CRITICAL(false); @@ -476,7 +476,7 @@ struct aux_engine *dal_aux_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c index 80d06ad78e07..aab77a81008a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_hw_engine_dce110.c @@ -469,7 +469,7 @@ static void destroy( dal_i2c_hw_engine_destruct(&engine_dce110->base); - dm_free(engine_dce110); + kfree(engine_dce110); *i2c_engine = NULL; } @@ -559,7 +559,8 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( return NULL; } - engine_dce10 = dm_alloc(sizeof(struct i2c_hw_engine_dce110)); + engine_dce10 = kzalloc(sizeof(struct i2c_hw_engine_dce110), + GFP_KERNEL); if (!engine_dce10) { ASSERT_CRITICAL(false); @@ -571,7 +572,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce10); + kfree(engine_dce10); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c index 996813d9165f..bf2c4b240b78 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2c_sw_engine_dce110.c @@ -88,7 +88,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -153,7 +153,8 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( return NULL; } - engine_dce110 = dm_alloc(sizeof(struct i2c_sw_engine_dce110)); + engine_dce110 = kzalloc(sizeof(struct i2c_sw_engine_dce110), + GFP_KERNEL); if (!engine_dce110) { ASSERT_CRITICAL(false); @@ -165,7 +166,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce110_create( ASSERT_CRITICAL(false); - dm_free(engine_dce110); + kfree(engine_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c index 1c00ed0010d9..ae9adb389319 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/i2caux_dce110.c @@ -68,7 +68,7 @@ static void destroy( destruct(i2caux_dce110); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); *i2c_engine = NULL; } @@ -299,7 +299,7 @@ struct i2caux *dal_i2caux_dce110_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -317,7 +317,7 @@ struct i2caux *dal_i2caux_dce110_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c index d74f3f15d600..715ba4390957 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce112/i2caux_dce112.c @@ -122,7 +122,7 @@ struct i2caux *dal_i2caux_dce112_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -134,7 +134,7 @@ struct i2caux *dal_i2caux_dce112_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c index 91198295f1a4..d52827ae3f1a 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce120/i2caux_dce120.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dce120_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dce120_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c index 423c38ac880c..d41e37c94214 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_hw_engine_dce80.c @@ -190,7 +190,7 @@ static void destroy( destruct(engine); - dm_free(engine); + kfree(engine); *i2c_engine = NULL; } @@ -867,7 +867,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_hw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_hw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -879,7 +879,7 @@ struct i2c_engine *dal_i2c_hw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c index 804a3266c578..6be77bc931c6 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2c_sw_engine_dce80.c @@ -103,7 +103,7 @@ static void destroy( destruct(sw_engine); - dm_free(sw_engine); + kfree(sw_engine); *engine = NULL; } @@ -165,7 +165,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine_dce80)); + engine = kzalloc(sizeof(struct i2c_sw_engine_dce80), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -177,7 +177,7 @@ struct i2c_engine *dal_i2c_sw_engine_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c index 5e71450c44e0..d3c157e5eccd 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce80/i2caux_dce80.c @@ -101,7 +101,7 @@ static void destroy( destruct(i2caux_dce80); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); *i2c_engine = NULL; } @@ -277,7 +277,7 @@ struct i2caux *dal_i2caux_dce80_create( struct dc_context *ctx) { struct i2caux_dce80 *i2caux_dce80 = - dm_alloc(sizeof(struct i2caux_dce80)); + kzalloc(sizeof(struct i2caux_dce80), GFP_KERNEL); if (!i2caux_dce80) { BREAK_TO_DEBUGGER(); @@ -289,7 +289,7 @@ struct i2caux *dal_i2caux_dce80_create( BREAK_TO_DEBUGGER(); - dm_free(i2caux_dce80); + kfree(i2caux_dce80); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c index 9f17d2e4376b..f8659f1c5f9d 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dcn10/i2caux_dcn10.c @@ -101,7 +101,7 @@ struct i2caux *dal_i2caux_dcn10_create( struct dc_context *ctx) { struct i2caux_dce110 *i2caux_dce110 = - dm_alloc(sizeof(struct i2caux_dce110)); + kzalloc(sizeof(struct i2caux_dce110), GFP_KERNEL); if (!i2caux_dce110) { ASSERT_CRITICAL(false); @@ -119,7 +119,7 @@ struct i2caux *dal_i2caux_dcn10_create( ASSERT_CRITICAL(false); - dm_free(i2caux_dce110); + kfree(i2caux_dce110); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c index 029bf735036c..1fdb3252920b 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/diagnostics/i2caux_diag.c @@ -59,7 +59,7 @@ static void destroy( { destruct(*i2c_engine); - dm_free(*i2c_engine); + kfree(*i2c_engine); *i2c_engine = NULL; } @@ -90,7 +90,8 @@ static bool construct( struct i2caux *dal_i2caux_diag_fpga_create( struct dc_context *ctx) { - struct i2caux *i2caux = dm_alloc(sizeof(struct i2caux)); + struct i2caux *i2caux = kzalloc(sizeof(struct i2caux), + GFP_KERNEL); if (!i2caux) { ASSERT_CRITICAL(false); @@ -102,7 +103,7 @@ struct i2caux *dal_i2caux_diag_fpga_create( ASSERT_CRITICAL(false); - dm_free(i2caux); + kfree(i2caux); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c index 95bc4457d44b..9d0077ade12c 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/i2c_sw_engine.c @@ -541,7 +541,7 @@ static void destroy( { dal_i2c_sw_engine_destruct(FROM_I2C_ENGINE(*ptr)); - dm_free(*ptr); + kfree(*ptr); *ptr = NULL; } @@ -592,7 +592,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( return NULL; } - engine = dm_alloc(sizeof(struct i2c_sw_engine)); + engine = kzalloc(sizeof(struct i2c_sw_engine), GFP_KERNEL); if (!engine) { BREAK_TO_DEBUGGER(); @@ -604,7 +604,7 @@ struct i2c_engine *dal_i2c_sw_engine_create( BREAK_TO_DEBUGGER(); - dm_free(engine); + kfree(engine); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c index 7cce28489dba..a6c3a7229def 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c @@ -422,7 +422,8 @@ bool construct( struct irq_service *dal_irq_service_dce110_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -430,6 +431,6 @@ struct irq_service *dal_irq_service_dce110_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c index 3871633ac635..61d7c286802a 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c @@ -281,7 +281,8 @@ static bool construct( struct irq_service *dal_irq_service_dce120_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -289,6 +290,6 @@ struct irq_service *dal_irq_service_dce120_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c index f458ef8e4c57..d6e1fb665d90 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dce80/irq_service_dce80.c @@ -293,7 +293,8 @@ static bool construct( struct irq_service *dal_irq_service_dce80_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -301,7 +302,7 @@ struct irq_service *dal_irq_service_dce80_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index be59f0a654e2..f6e861162a6e 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -348,7 +348,8 @@ static bool construct( struct irq_service *dal_irq_service_dcn10_create( struct irq_service_init_data *init_data) { - struct irq_service *irq_service = dm_alloc(sizeof(*irq_service)); + struct irq_service *irq_service = kzalloc(sizeof(*irq_service), + GFP_KERNEL); if (!irq_service) return NULL; @@ -356,6 +357,6 @@ struct irq_service *dal_irq_service_dcn10_create( if (construct(irq_service, init_data)) return irq_service; - dm_free(irq_service); + kfree(irq_service); return NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c index 0a1fae4ef83a..ce20622c7c89 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c +++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c @@ -66,7 +66,7 @@ void dal_irq_service_destroy(struct irq_service **irq_service) return; } - dm_free(*irq_service); + kfree(*irq_service); *irq_service = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c index 57b5a3babdf8..db513abd735a 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c @@ -87,7 +87,7 @@ static void virtual_link_encoder_connect_dig_be_to_fe( static void virtual_link_encoder_destroy(struct link_encoder **enc) { - dm_free(*enc); + kfree(*enc); *enc = NULL; } diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 7fe6085e6e37..3dc1733eea20 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -121,7 +121,7 @@ bool virtual_stream_encoder_construct( struct stream_encoder *virtual_stream_encoder_create( struct dc_context *ctx, struct dc_bios *bp) { - struct stream_encoder *enc = dm_alloc(sizeof(*enc)); + struct stream_encoder *enc = kzalloc(sizeof(*enc), GFP_KERNEL); if (!enc) return NULL; @@ -130,7 +130,7 @@ struct stream_encoder *virtual_stream_encoder_create( return enc; BREAK_TO_DEBUGGER(); - dm_free(enc); + kfree(enc); return NULL; } diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index 52350d0e68d0..4d7db4aa28e0 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -143,7 +143,7 @@ static bool check_dc_support(const struct dc *dc) struct mod_freesync *mod_freesync_create(struct dc *dc) { struct core_freesync *core_freesync = - dm_alloc(sizeof(struct core_freesync)); + kzalloc(sizeof(struct core_freesync), GFP_KERNEL); struct persistent_data_flag flag; @@ -153,8 +153,8 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) if (core_freesync == NULL) goto fail_alloc_context; - core_freesync->map = dm_alloc(sizeof(struct freesync_entity) * - MOD_FREESYNC_MAX_CONCURRENT_STREAMS); + core_freesync->map = kzalloc(sizeof(struct freesync_entity) * MOD_FREESYNC_MAX_CONCURRENT_STREAMS, + GFP_KERNEL); if (core_freesync->map == NULL) goto fail_alloc_map; @@ -197,10 +197,10 @@ struct mod_freesync *mod_freesync_create(struct dc *dc) return &core_freesync->public; fail_construct: - dm_free(core_freesync->map); + kfree(core_freesync->map); fail_alloc_map: - dm_free(core_freesync); + kfree(core_freesync); fail_alloc_context: return NULL; @@ -217,9 +217,9 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync) if (core_freesync->map[i].stream) dc_stream_release(core_freesync->map[i].stream); - dm_free(core_freesync->map); + kfree(core_freesync->map); - dm_free(core_freesync); + kfree(core_freesync); } } -- cgit v1.2.3 From 99d1abf8f41ed2c256e8cca7e9da71d751894c7f Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 10:27:41 +1000 Subject: amdgpu/dm: constify yuv_formats. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dba54c0a7b5f..89442cce7373 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3073,7 +3073,7 @@ static uint32_t rgb_formats[] = { DRM_FORMAT_ABGR2101010, }; -static uint32_t yuv_formats[] = { +static const uint32_t yuv_formats[] = { DRM_FORMAT_NV12, DRM_FORMAT_NV21, }; -- cgit v1.2.3 From e04a6123a45abf6836f547e679a8f9aca37ceeb6 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 10:32:23 +1000 Subject: amdgpu/dm: constify plane type. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index b541ade8a03f..59e2e5d59562 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -361,7 +361,7 @@ struct amdgpu_mode_info { int num_dig; /* number of dig blocks */ int disp_priority; const struct amdgpu_display_funcs *funcs; - enum drm_plane_type *plane_type; + const enum drm_plane_type *plane_type; }; #define AMDGPU_MAX_BL_LEVEL 0xFF diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 89442cce7373..ef938521fec8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -71,7 +71,7 @@ #include "i2caux_interface.h" -static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { +static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, @@ -80,14 +80,14 @@ static enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, }; -static enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { +static const enum drm_plane_type dm_plane_type_carizzo[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY,/* YUV Capable Underlay */ }; -static enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { +static const enum drm_plane_type dm_plane_type_stoney[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_PRIMARY, DRM_PLANE_TYPE_OVERLAY, /* YUV Capable Underlay */ -- cgit v1.2.3 From d90371b0f5f3258a808d12a17a942e4d16f8252c Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Fri, 29 Sep 2017 10:32:24 +1000 Subject: amdgpu/dm: constify rgb formats. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ef938521fec8..61ccddd19718 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3062,7 +3062,7 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { * plane capabilities, or initialize this array to all formats, so internal drm * check will succeed, and let DC to implement proper check */ -static uint32_t rgb_formats[] = { +static const uint32_t rgb_formats[] = { DRM_FORMAT_RGB888, DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, -- cgit v1.2.3 From ae3a27d19b59e431aea9f9d5917c1aec710ae4c3 Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Tue, 3 Oct 2017 14:27:15 +1000 Subject: amdgpu/dm: don't use after free. This dereference acrtc after freeing it. Found by the kfree cocci script. Signed-off-by: Dave Airlie Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 61ccddd19718..4f8973182f8a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3174,7 +3174,6 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, fail: kfree(acrtc); kfree(cursor_plane); - acrtc->crtc_id = -1; return res; } -- cgit v1.2.3 From 9ba29fcb76a559078491adffc74f66bf92b9dbea Mon Sep 17 00:00:00 2001 From: Dave Airlie Date: Mon, 9 Oct 2017 10:33:04 +1000 Subject: drm/amd/display: Use DRM new-style object iterators. Use the correct for_each_new/old_* iterators instead of for_each_* The following functions were considered: amdgpu_dm_find_first_crtc_matching_connector: use for_each_new - Old from_state_var flag was always choosing the new state amdgpu_dm_display_resume: use for_each_new - drm_atomic_helper_duplicate_state is called during suspend to cache the state - It sets 'state' within the state triplet to 'new_state' amdgpu_dm_commit_planes: use for_each_old - Called after the state was swapped (via atomic commit tail) amdgpu_dm_atomic_commit: use for_each_new - Called before the state is swapped amdgpu_dm_atomic_commit_tail: use for_each_old - Called after the state was swapped dm_update_crtcs_state: use for_each_new - Called before the state is swapped (via atomic check) amdgpu_dm_atomic_check: use for_each_new - Called before the state is swapped v2: Split out typo fixes to a new patch. v3: Say "functions considered" instead of "affected functions". The latter implies that changes are made to each. [airlied: squashed with my hacks] Reviewed-by: Harry Wentland Reviewed-by: Maarten Lankhorst Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 42 +++++++++-------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 +- 2 files changed, 17 insertions(+), 28 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4f8973182f8a..cc024abb14d5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -570,23 +570,15 @@ static int dm_suspend(void *handle) struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_atomic_state *state, - struct drm_crtc *crtc, - bool from_state_var) + struct drm_crtc *crtc) { uint32_t i; struct drm_connector_state *conn_state; struct drm_connector *connector; struct drm_crtc *crtc_from_state; - for_each_connector_in_state( - state, - connector, - conn_state, - i) { - crtc_from_state = - from_state_var ? - conn_state->crtc : - connector->state->crtc; + for_each_new_connector_in_state(state, connector, conn_state, i) { + crtc_from_state = conn_state->crtc; if (crtc_from_state == crtc) return to_amdgpu_dm_connector(connector); @@ -652,7 +644,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) } /* Force mode set in atomic comit */ - for_each_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i) + for_each_new_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i) crtc_state->active_changed = true; ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); @@ -3890,7 +3882,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, unsigned long flags; /* update planes when needed */ - for_each_plane_in_state(state, plane, old_plane_state, i) { + for_each_old_plane_in_state(state, plane, old_plane_state, i) { struct drm_plane_state *plane_state = plane->state; struct drm_crtc *crtc = plane_state->crtc; struct drm_framebuffer *fb = plane_state->fb; @@ -3987,7 +3979,7 @@ int amdgpu_dm_atomic_commit( * it will update crtc->dm_crtc_state->stream pointer which is used in * the ISRs. */ - for_each_crtc_in_state(state, crtc, new_state, i) { + for_each_new_crtc_in_state(state, crtc, new_state, i) { struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); @@ -4024,7 +4016,7 @@ void amdgpu_dm_atomic_commit_tail( dm_state = to_dm_atomic_state(state); /* update changed items */ - for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); struct drm_crtc_state *new_state = crtc->state; @@ -4113,11 +4105,9 @@ void amdgpu_dm_atomic_commit_tail( new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); new_stream = new_acrtc_state->stream; - aconnector = - amdgpu_dm_find_first_crct_matching_connector( + aconnector = amdgpu_dm_find_first_crct_matching_connector( state, - &new_crtcs[i]->base, - false); + &new_crtcs[i]->base); if (!aconnector) { DRM_DEBUG_DRIVER("Atomic commit: Failed to find connector for acrtc id:%d " "skipping freesync init\n", @@ -4151,7 +4141,7 @@ void amdgpu_dm_atomic_commit_tail( } /* Handle scaling and undersacn changes*/ - for_each_connector_in_state(state, connector, old_conn_state, i) { + for_each_old_connector_in_state(state, connector, old_conn_state, i) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *con_new_state = to_dm_connector_state(aconnector->base.state); @@ -4205,7 +4195,7 @@ void amdgpu_dm_atomic_commit_tail( } /* update planes when needed per crtc*/ - for_each_crtc_in_state(state, pcrtc, old_crtc_state, j) { + for_each_old_crtc_in_state(state, pcrtc, old_crtc_state, j) { new_acrtc_state = to_dm_crtc_state(pcrtc->state); if (new_acrtc_state->stream) @@ -4218,7 +4208,7 @@ void amdgpu_dm_atomic_commit_tail( * mark consumed event for drm_atomic_helper_commit_hw_done */ spin_lock_irqsave(&adev->ddev->event_lock, flags); - for_each_crtc_in_state(state, crtc, old_crtc_state, i) { + for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); if (acrtc->base.state->event) @@ -4390,7 +4380,7 @@ static int dm_update_crtcs_state( /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ /* update changed items */ - for_each_crtc_in_state(state, crtc, crtc_state, i) { + for_each_new_crtc_in_state(state, crtc, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_dm_connector *aconnector = NULL; struct drm_connector_state *conn_state = NULL; @@ -4402,7 +4392,7 @@ static int dm_update_crtcs_state( new_acrtc_state = to_dm_crtc_state(crtc_state); acrtc = to_amdgpu_crtc(crtc); - aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc, true); + aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc); /* TODO This hack should go away */ if (aconnector) { @@ -4674,7 +4664,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * Hack: Commit needs planes right now, specifically for gamma * TODO rework commit to check CRTC for gamma change */ - for_each_crtc_in_state(state, crtc, crtc_state, i) { + for_each_new_crtc_in_state(state, crtc, crtc_state, i) { if (crtc_state->color_mgmt_changed) { ret = drm_atomic_add_affected_planes(state, crtc); if (ret) @@ -4720,7 +4710,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * new stream into context w\o causing full reset. Need to * decide how to handle. */ - for_each_connector_in_state(state, connector, conn_state, i) { + for_each_new_connector_in_state(state, connector, conn_state, i) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct dm_connector_state *con_old_state = to_dm_connector_state(aconnector->base.state); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 630e6cdf84f6..1c55a0b5cd15 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -228,8 +228,7 @@ void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_atomic_state *state, - struct drm_crtc *crtc, - bool from_state_var); + struct drm_crtc *crtc); struct amdgpu_framebuffer; -- cgit v1.2.3 From 0bc9706db3a35b6d674d0642f425d768560736b2 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 12 Oct 2017 17:15:07 -0400 Subject: drm/amd/display: Use new DRM API where possible To conform to DRM's new API, we should not be accessing a DRM object's internal state directly. Rather, the DRM for_each_old/new_* iterators, and drm_atomic_get_old/new_* interface should be used. This is an ongoing process. For now, update the DRM-facing atomic functions, where the atomic state object is given. Reviewed-by: Harry Wentland Reviewed-by: Maarten Lankhorst Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 131 +++++++++++----------- 1 file changed, 66 insertions(+), 65 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cc024abb14d5..d4426b326918 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3873,28 +3873,31 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, { uint32_t i; struct drm_plane *plane; - struct drm_plane_state *old_plane_state; + struct drm_plane_state *old_plane_state, *new_plane_state; struct dc_stream_state *dc_stream_attach; struct dc_plane_state *plane_states_constructed[MAX_SURFACES]; struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc); - struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state); + struct drm_crtc_state *new_pcrtc_state = + drm_atomic_get_new_crtc_state(state, pcrtc); + struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); int planes_count = 0; unsigned long flags; /* update planes when needed */ - for_each_old_plane_in_state(state, plane, old_plane_state, i) { - struct drm_plane_state *plane_state = plane->state; - struct drm_crtc *crtc = plane_state->crtc; - struct drm_framebuffer *fb = plane_state->fb; + for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { + struct drm_crtc *crtc = new_plane_state->crtc; + struct drm_crtc_state *new_crtc_state = + drm_atomic_get_new_crtc_state(state, crtc); + struct drm_framebuffer *fb = new_plane_state->fb; bool pflip_needed; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(plane_state); + struct dm_plane_state *dm_plane_state = to_dm_plane_state(new_plane_state); if (plane->type == DRM_PLANE_TYPE_CURSOR) { handle_cursor_update(plane, old_plane_state); continue; } - if (!fb || !crtc || pcrtc != crtc || !crtc->state->active) + if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active) continue; pflip_needed = !state->allow_modeset; @@ -3918,13 +3921,13 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, dc_stream_attach = acrtc_state->stream; planes_count++; - } else if (crtc->state->planes_changed) { + } else if (new_crtc_state->planes_changed) { /* Assume even ONE crtc with immediate flip means * entire can't wait for VBLANK * TODO Check if it's correct */ *wait_for_vblank = - pcrtc->state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? + new_pcrtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC ? false : true; /* TODO: Needs rework for multiplane flip */ @@ -3942,7 +3945,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (planes_count) { unsigned long flags; - if (pcrtc->state->event) { + if (new_pcrtc_state->event) { drm_crtc_vblank_get(pcrtc); @@ -3968,7 +3971,7 @@ int amdgpu_dm_atomic_commit( bool nonblock) { struct drm_crtc *crtc; - struct drm_crtc_state *new_state; + struct drm_crtc_state *old_crtc_state, *new_state; struct amdgpu_device *adev = dev->dev_private; int i; @@ -3979,8 +3982,8 @@ int amdgpu_dm_atomic_commit( * it will update crtc->dm_crtc_state->stream pointer which is used in * the ISRs. */ - for_each_new_crtc_in_state(state, crtc, new_state, i) { - struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(crtc->state); + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_state, i) { + struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(old_crtc_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream) @@ -4002,13 +4005,13 @@ void amdgpu_dm_atomic_commit_tail( uint32_t i, j; uint32_t new_crtcs_count = 0; struct drm_crtc *crtc, *pcrtc; - struct drm_crtc_state *old_crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; struct dc_stream_state *new_stream = NULL; unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_conn_state; + struct drm_connector_state *old_conn_state, *new_con_state; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -4016,11 +4019,10 @@ void amdgpu_dm_atomic_commit_tail( dm_state = to_dm_atomic_state(state); /* update changed items */ - for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct drm_crtc_state *new_state = crtc->state; - new_acrtc_state = to_dm_crtc_state(new_state); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); old_acrtc_state = to_dm_crtc_state(old_crtc_state); DRM_DEBUG_DRIVER( @@ -4028,18 +4030,18 @@ void amdgpu_dm_atomic_commit_tail( "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n", acrtc->crtc_id, - new_state->enable, - new_state->active, - new_state->planes_changed, - new_state->mode_changed, - new_state->active_changed, - new_state->connectors_changed); + new_crtc_state->enable, + new_crtc_state->active, + new_crtc_state->planes_changed, + new_crtc_state->mode_changed, + new_crtc_state->active_changed, + new_crtc_state->connectors_changed); /* handles headless hotplug case, updating new_state and * aconnector as needed */ - if (modeset_required(new_state, new_acrtc_state->stream, old_acrtc_state->stream)) { + if (modeset_required(new_crtc_state, new_acrtc_state->stream, old_acrtc_state->stream)) { DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); @@ -4082,10 +4084,11 @@ void amdgpu_dm_atomic_commit_tail( new_crtcs[new_crtcs_count] = acrtc; new_crtcs_count++; + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); acrtc->enabled = true; - acrtc->hw_mode = crtc->state->mode; - crtc->hwmode = crtc->state->mode; - } else if (modereset_required(new_state)) { + acrtc->hw_mode = new_crtc_state->mode; + crtc->hwmode = new_crtc_state->mode; + } else if (modereset_required(new_crtc_state)) { DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); /* i.e. reset mode */ @@ -4102,7 +4105,9 @@ void amdgpu_dm_atomic_commit_tail( for (i = 0; i < new_crtcs_count; i++) { struct amdgpu_dm_connector *aconnector = NULL; - new_acrtc_state = to_dm_crtc_state(new_crtcs[i]->base.state); + new_crtc_state = drm_atomic_get_new_crtc_state(state, + &new_crtcs[i]->base); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); new_stream = new_acrtc_state->stream; aconnector = amdgpu_dm_find_first_crct_matching_connector( @@ -4123,11 +4128,10 @@ void amdgpu_dm_atomic_commit_tail( if (dm_state->context) WARN_ON(!dc_commit_state(dm->dc, dm_state->context)); - - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - new_acrtc_state = to_dm_crtc_state(crtc->state); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); if (new_acrtc_state->stream != NULL) { const struct dc_stream_status *status = @@ -4141,24 +4145,24 @@ void amdgpu_dm_atomic_commit_tail( } /* Handle scaling and undersacn changes*/ - for_each_old_connector_in_state(state, connector, old_conn_state, i) { - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct dm_connector_state *con_new_state = - to_dm_connector_state(aconnector->base.state); - struct dm_connector_state *con_old_state = - to_dm_connector_state(old_conn_state); + for_each_oldnew_connector_in_state(state, connector, old_conn_state, new_con_state, i) { + struct dm_connector_state *con_new_state = to_dm_connector_state(new_con_state); + struct dm_connector_state *con_old_state = to_dm_connector_state(old_conn_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); struct dc_stream_status *status = NULL; + if (acrtc) + new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); + /* Skip any modesets/resets */ - if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) + if (!acrtc || drm_atomic_crtc_needs_modeset(new_crtc_state)) continue; /* Skip any thing not scale or underscan changes */ if (!is_scaling_state_different(con_new_state, con_old_state)) continue; - new_acrtc_state = to_dm_crtc_state(acrtc->base.state); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); update_stream_scaling_settings(&con_new_state->base.crtc->mode, con_new_state, (struct dc_stream_state *)new_acrtc_state->stream); @@ -4185,7 +4189,8 @@ void amdgpu_dm_atomic_commit_tail( */ struct amdgpu_crtc *acrtc = new_crtcs[i]; - new_acrtc_state = to_dm_crtc_state(acrtc->base.state); + new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); if (adev->dm.freesync_module) mod_freesync_notify_mode_change( @@ -4195,8 +4200,8 @@ void amdgpu_dm_atomic_commit_tail( } /* update planes when needed per crtc*/ - for_each_old_crtc_in_state(state, pcrtc, old_crtc_state, j) { - new_acrtc_state = to_dm_crtc_state(pcrtc->state); + for_each_new_crtc_in_state(state, pcrtc, new_crtc_state, j) { + new_acrtc_state = to_dm_crtc_state(new_crtc_state); if (new_acrtc_state->stream) amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); @@ -4208,13 +4213,12 @@ void amdgpu_dm_atomic_commit_tail( * mark consumed event for drm_atomic_helper_commit_hw_done */ spin_lock_irqsave(&adev->ddev->event_lock, flags); - for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { - if (acrtc->base.state->event) - drm_send_event_locked(dev, &crtc->state->event->base); + if (new_crtc_state->event) + drm_send_event_locked(dev, &new_crtc_state->event->base); - acrtc->base.state->event = NULL; + new_crtc_state->event = NULL; } spin_unlock_irqrestore(&adev->ddev->event_lock, flags); @@ -4371,7 +4375,7 @@ static int dm_update_crtcs_state( bool *lock_and_validation_needed) { struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; + struct drm_crtc_state *old_crtc_state, *crtc_state; int i; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); @@ -4380,7 +4384,7 @@ static int dm_update_crtcs_state( /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ /* update changed items */ - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_dm_connector *aconnector = NULL; struct drm_connector_state *conn_state = NULL; @@ -4388,7 +4392,7 @@ static int dm_update_crtcs_state( new_stream = NULL; - old_acrtc_state = to_dm_crtc_state(crtc->state); + old_acrtc_state = to_dm_crtc_state(old_crtc_state); new_acrtc_state = to_dm_crtc_state(crtc_state); acrtc = to_amdgpu_crtc(crtc); @@ -4521,7 +4525,7 @@ static int dm_update_planes_state( bool *lock_and_validation_needed) { struct drm_crtc *new_plane_crtc, *old_plane_crtc; - struct drm_crtc_state *new_crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct drm_plane *plane; struct drm_plane_state *old_plane_state, *new_plane_state; struct dm_crtc_state *new_acrtc_state, *old_acrtc_state; @@ -4552,10 +4556,9 @@ static int dm_update_planes_state( if (!old_plane_crtc) continue; - old_acrtc_state = to_dm_crtc_state( - drm_atomic_get_old_crtc_state( - state, - old_plane_crtc)); + old_crtc_state = drm_atomic_get_old_crtc_state( + state, old_plane_crtc); + old_acrtc_state = to_dm_crtc_state(old_crtc_state); if (!old_acrtc_state->stream) continue; @@ -4643,7 +4646,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dc *dc = adev->dm.dc; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); struct drm_connector *connector; - struct drm_connector_state *conn_state; + struct drm_connector_state *old_con_state, *conn_state; struct drm_crtc *crtc; struct drm_crtc_state *crtc_state; @@ -4710,16 +4713,14 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * new stream into context w\o causing full reset. Need to * decide how to handle. */ - for_each_new_connector_in_state(state, connector, conn_state, i) { - struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct dm_connector_state *con_old_state = - to_dm_connector_state(aconnector->base.state); - struct dm_connector_state *con_new_state = - to_dm_connector_state(conn_state); + for_each_oldnew_connector_in_state(state, connector, old_con_state, conn_state, i) { + struct dm_connector_state *con_old_state = to_dm_connector_state(old_con_state); + struct dm_connector_state *con_new_state = to_dm_connector_state(conn_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); /* Skip any modesets/resets */ - if (!acrtc || drm_atomic_crtc_needs_modeset(acrtc->base.state)) + if (!acrtc || drm_atomic_crtc_needs_modeset( + drm_atomic_get_new_crtc_state(state, &acrtc->base))) continue; /* Skip any thing not scale or underscan changes */ -- cgit v1.2.3 From c2cea7063b85fc2bcec92997a808f1d3a16f8052 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 12 Oct 2017 17:15:08 -0400 Subject: drm/amd/display: Unify DRM state variable namings. Use new_*_state and old_*_state for their respective new/old DRM object states. Reviewed-by: Maarten Lankhorst Reviewed-by: Harry Wentland Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 80 +++++++++++------------ 1 file changed, 40 insertions(+), 40 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d4426b326918..fe0b658cf3a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -573,12 +573,12 @@ struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( struct drm_crtc *crtc) { uint32_t i; - struct drm_connector_state *conn_state; + struct drm_connector_state *new_con_state; struct drm_connector *connector; struct drm_crtc *crtc_from_state; - for_each_new_connector_in_state(state, connector, conn_state, i) { - crtc_from_state = conn_state->crtc; + for_each_new_connector_in_state(state, connector, new_con_state, i) { + crtc_from_state = new_con_state->crtc; if (crtc_from_state == crtc) return to_amdgpu_dm_connector(connector); @@ -608,7 +608,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; + struct drm_crtc_state *new_crtc_state; int ret = 0; int i; @@ -644,8 +644,8 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) } /* Force mode set in atomic comit */ - for_each_new_crtc_in_state(adev->dm.cached_state, crtc, crtc_state, i) - crtc_state->active_changed = true; + for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) + new_crtc_state->active_changed = true; ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); @@ -3971,7 +3971,7 @@ int amdgpu_dm_atomic_commit( bool nonblock) { struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state, *new_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct amdgpu_device *adev = dev->dev_private; int i; @@ -3982,11 +3982,11 @@ int amdgpu_dm_atomic_commit( * it will update crtc->dm_crtc_state->stream pointer which is used in * the ISRs. */ - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(old_crtc_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (drm_atomic_crtc_needs_modeset(new_state) && old_acrtc_state->stream) + if (drm_atomic_crtc_needs_modeset(new_crtc_state) && old_acrtc_state->stream) manage_dm_interrupts(adev, acrtc, false); } @@ -4011,7 +4011,7 @@ void amdgpu_dm_atomic_commit_tail( unsigned long flags; bool wait_for_vblank = true; struct drm_connector *connector; - struct drm_connector_state *old_conn_state, *new_con_state; + struct drm_connector_state *old_con_state, *new_con_state; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -4145,9 +4145,9 @@ void amdgpu_dm_atomic_commit_tail( } /* Handle scaling and undersacn changes*/ - for_each_oldnew_connector_in_state(state, connector, old_conn_state, new_con_state, i) { + for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { struct dm_connector_state *con_new_state = to_dm_connector_state(new_con_state); - struct dm_connector_state *con_old_state = to_dm_connector_state(old_conn_state); + struct dm_connector_state *con_old_state = to_dm_connector_state(old_con_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); struct dc_stream_status *status = NULL; @@ -4375,7 +4375,7 @@ static int dm_update_crtcs_state( bool *lock_and_validation_needed) { struct drm_crtc *crtc; - struct drm_crtc_state *old_crtc_state, *crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; int i; struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); @@ -4384,34 +4384,34 @@ static int dm_update_crtcs_state( /*TODO Move this code into dm_crtc_atomic_check once we get rid of dc_validation_set */ /* update changed items */ - for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_dm_connector *aconnector = NULL; - struct drm_connector_state *conn_state = NULL; + struct drm_connector_state *new_con_state = NULL; struct dm_connector_state *dm_conn_state = NULL; new_stream = NULL; old_acrtc_state = to_dm_crtc_state(old_crtc_state); - new_acrtc_state = to_dm_crtc_state(crtc_state); + new_acrtc_state = to_dm_crtc_state(new_crtc_state); acrtc = to_amdgpu_crtc(crtc); aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc); /* TODO This hack should go away */ if (aconnector) { - conn_state = drm_atomic_get_connector_state(state, - &aconnector->base); + new_con_state = drm_atomic_get_connector_state(state, + &aconnector->base); - if (IS_ERR(conn_state)) { - ret = PTR_ERR_OR_ZERO(conn_state); + if (IS_ERR(new_con_state)) { + ret = PTR_ERR_OR_ZERO(new_con_state); break; } - dm_conn_state = to_dm_connector_state(conn_state); + dm_conn_state = to_dm_connector_state(new_con_state); new_stream = create_stream_for_sink(aconnector, - &crtc_state->mode, + &new_crtc_state->mode, dm_conn_state); /* @@ -4431,14 +4431,14 @@ static int dm_update_crtcs_state( if (dc_is_stream_unchanged(new_stream, old_acrtc_state->stream)) { - crtc_state->mode_changed = false; + new_crtc_state->mode_changed = false; - DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", - crtc_state->mode_changed); + DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", + new_crtc_state->mode_changed); } - if (!drm_atomic_crtc_needs_modeset(crtc_state)) + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) goto next_crtc; DRM_DEBUG_DRIVER( @@ -4446,12 +4446,12 @@ static int dm_update_crtcs_state( "planes_changed:%d, mode_changed:%d,active_changed:%d," "connectors_changed:%d\n", acrtc->crtc_id, - crtc_state->enable, - crtc_state->active, - crtc_state->planes_changed, - crtc_state->mode_changed, - crtc_state->active_changed, - crtc_state->connectors_changed); + new_crtc_state->enable, + new_crtc_state->active, + new_crtc_state->planes_changed, + new_crtc_state->mode_changed, + new_crtc_state->active_changed, + new_crtc_state->connectors_changed); /* Remove stream for any changed/disabled CRTC */ if (!enable) { @@ -4478,10 +4478,10 @@ static int dm_update_crtcs_state( } else {/* Add stream for any updated/enabled CRTC */ - if (modereset_required(crtc_state)) + if (modereset_required(new_crtc_state)) goto next_crtc; - if (modeset_required(crtc_state, new_stream, + if (modeset_required(new_crtc_state, new_stream, old_acrtc_state->stream)) { WARN_ON(new_acrtc_state->stream); @@ -4646,9 +4646,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, struct dc *dc = adev->dm.dc; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); struct drm_connector *connector; - struct drm_connector_state *old_con_state, *conn_state; + struct drm_connector_state *old_con_state, *new_con_state; struct drm_crtc *crtc; - struct drm_crtc_state *crtc_state; + struct drm_crtc_state *new_crtc_state; /* * This bool will be set for true for any modeset/reset @@ -4667,8 +4667,8 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * Hack: Commit needs planes right now, specifically for gamma * TODO rework commit to check CRTC for gamma change */ - for_each_new_crtc_in_state(state, crtc, crtc_state, i) { - if (crtc_state->color_mgmt_changed) { + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->color_mgmt_changed) { ret = drm_atomic_add_affected_planes(state, crtc); if (ret) goto fail; @@ -4713,9 +4713,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * new stream into context w\o causing full reset. Need to * decide how to handle. */ - for_each_oldnew_connector_in_state(state, connector, old_con_state, conn_state, i) { + for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { struct dm_connector_state *con_old_state = to_dm_connector_state(old_con_state); - struct dm_connector_state *con_new_state = to_dm_connector_state(conn_state); + struct dm_connector_state *con_new_state = to_dm_connector_state(new_con_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); /* Skip any modesets/resets */ -- cgit v1.2.3 From 54d76575246798f5f42ca56fe5d54d1f195198b2 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 12 Oct 2017 17:15:09 -0400 Subject: drm/amd/display: Unify amdgpu_dm state variable namings. Use dm_new_*_state and dm_old_*_state for their respective amdgpu_dm new and old object states. Helps with readability, and enforces use of new DRM api (choose either new, or old). Reviewed-by: Maarten Lankhorst Reviewed-by: Harry Wentland Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 137 +++++++++++----------- 1 file changed, 68 insertions(+), 69 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fe0b658cf3a6..de88ee1af438 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3890,7 +3890,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, drm_atomic_get_new_crtc_state(state, crtc); struct drm_framebuffer *fb = new_plane_state->fb; bool pflip_needed; - struct dm_plane_state *dm_plane_state = to_dm_plane_state(new_plane_state); + struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); if (plane->type == DRM_PLANE_TYPE_CURSOR) { handle_cursor_update(plane, old_plane_state); @@ -3914,9 +3914,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, spin_unlock_irqrestore(&crtc->dev->event_lock, flags); if (!pflip_needed) { - WARN_ON(!dm_plane_state->dc_state); + WARN_ON(!dm_new_plane_state->dc_state); - plane_states_constructed[planes_count] = dm_plane_state->dc_state; + plane_states_constructed[planes_count] = dm_new_plane_state->dc_state; dc_stream_attach = acrtc_state->stream; planes_count++; @@ -3983,10 +3983,10 @@ int amdgpu_dm_atomic_commit( * the ISRs. */ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { - struct dm_crtc_state *old_acrtc_state = to_dm_crtc_state(old_crtc_state); + struct dm_crtc_state *dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - if (drm_atomic_crtc_needs_modeset(new_crtc_state) && old_acrtc_state->stream) + if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream) manage_dm_interrupts(adev, acrtc, false); } @@ -4012,7 +4012,7 @@ void amdgpu_dm_atomic_commit_tail( bool wait_for_vblank = true; struct drm_connector *connector; struct drm_connector_state *old_con_state, *new_con_state; - struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; drm_atomic_helper_update_legacy_modeset_state(dev, state); @@ -4022,8 +4022,8 @@ void amdgpu_dm_atomic_commit_tail( for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); - old_acrtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); DRM_DEBUG_DRIVER( "amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, " @@ -4041,11 +4041,11 @@ void amdgpu_dm_atomic_commit_tail( * aconnector as needed */ - if (modeset_required(new_crtc_state, new_acrtc_state->stream, old_acrtc_state->stream)) { + if (modeset_required(new_crtc_state, dm_new_crtc_state->stream, dm_old_crtc_state->stream)) { DRM_DEBUG_DRIVER("Atomic commit: SET crtc id %d: [%p]\n", acrtc->crtc_id, acrtc); - if (!new_acrtc_state->stream) { + if (!dm_new_crtc_state->stream) { /* * this could happen because of issues with * userspace notifications delivery. @@ -4067,8 +4067,8 @@ void amdgpu_dm_atomic_commit_tail( } - if (old_acrtc_state->stream) - remove_stream(adev, acrtc, old_acrtc_state->stream); + if (dm_old_crtc_state->stream) + remove_stream(adev, acrtc, dm_old_crtc_state->stream); /* @@ -4092,8 +4092,8 @@ void amdgpu_dm_atomic_commit_tail( DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); /* i.e. reset mode */ - if (old_acrtc_state->stream) - remove_stream(adev, acrtc, old_acrtc_state->stream); + if (dm_old_crtc_state->stream) + remove_stream(adev, acrtc, dm_old_crtc_state->stream); } } /* for_each_crtc_in_state() */ @@ -4107,9 +4107,9 @@ void amdgpu_dm_atomic_commit_tail( new_crtc_state = drm_atomic_get_new_crtc_state(state, &new_crtcs[i]->base); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - new_stream = new_acrtc_state->stream; + new_stream = dm_new_crtc_state->stream; aconnector = amdgpu_dm_find_first_crct_matching_connector( state, &new_crtcs[i]->base); @@ -4131,14 +4131,14 @@ void amdgpu_dm_atomic_commit_tail( for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - if (new_acrtc_state->stream != NULL) { + if (dm_new_crtc_state->stream != NULL) { const struct dc_stream_status *status = - dc_stream_get_status(new_acrtc_state->stream); + dc_stream_get_status(dm_new_crtc_state->stream); if (!status) - DC_ERR("got no status for stream %p on acrtc%p\n", new_acrtc_state->stream, acrtc); + DC_ERR("got no status for stream %p on acrtc%p\n", dm_new_crtc_state->stream, acrtc); else acrtc->otg_inst = status->primary_otg_inst; } @@ -4146,9 +4146,9 @@ void amdgpu_dm_atomic_commit_tail( /* Handle scaling and undersacn changes*/ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { - struct dm_connector_state *con_new_state = to_dm_connector_state(new_con_state); - struct dm_connector_state *con_old_state = to_dm_connector_state(old_con_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); + struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); + struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_stream_status *status = NULL; if (acrtc) @@ -4159,19 +4159,19 @@ void amdgpu_dm_atomic_commit_tail( continue; /* Skip any thing not scale or underscan changes */ - if (!is_scaling_state_different(con_new_state, con_old_state)) + if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) continue; - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - update_stream_scaling_settings(&con_new_state->base.crtc->mode, - con_new_state, (struct dc_stream_state *)new_acrtc_state->stream); + update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, + dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); - status = dc_stream_get_status(new_acrtc_state->stream); + status = dc_stream_get_status(dm_new_crtc_state->stream); WARN_ON(!status); WARN_ON(!status->plane_count); - if (!new_acrtc_state->stream) + if (!dm_new_crtc_state->stream) continue; /*TODO How it works with MPO ?*/ @@ -4179,7 +4179,7 @@ void amdgpu_dm_atomic_commit_tail( dm->dc, status->plane_states, status->plane_count, - new_acrtc_state->stream)) + dm_new_crtc_state->stream)) dm_error("%s: Failed to update stream scaling!\n", __func__); } @@ -4190,20 +4190,20 @@ void amdgpu_dm_atomic_commit_tail( struct amdgpu_crtc *acrtc = new_crtcs[i]; new_crtc_state = drm_atomic_get_new_crtc_state(state, &acrtc->base); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (adev->dm.freesync_module) mod_freesync_notify_mode_change( - adev->dm.freesync_module, &new_acrtc_state->stream, 1); + adev->dm.freesync_module, &dm_new_crtc_state->stream, 1); manage_dm_interrupts(adev, acrtc, true); } /* update planes when needed per crtc*/ for_each_new_crtc_in_state(state, pcrtc, new_crtc_state, j) { - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - if (new_acrtc_state->stream) + if (dm_new_crtc_state->stream) amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); } @@ -4377,7 +4377,7 @@ static int dm_update_crtcs_state( struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; int i; - struct dm_crtc_state *old_acrtc_state, *new_acrtc_state; + struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); struct dc_stream_state *new_stream; int ret = 0; @@ -4392,8 +4392,8 @@ static int dm_update_crtcs_state( new_stream = NULL; - old_acrtc_state = to_dm_crtc_state(old_crtc_state); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); acrtc = to_amdgpu_crtc(crtc); aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc); @@ -4428,8 +4428,7 @@ static int dm_update_crtcs_state( } } - if (dc_is_stream_unchanged(new_stream, - old_acrtc_state->stream)) { + if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream)) { new_crtc_state->mode_changed = false; @@ -4456,7 +4455,7 @@ static int dm_update_crtcs_state( /* Remove stream for any changed/disabled CRTC */ if (!enable) { - if (!old_acrtc_state->stream) + if (!dm_old_crtc_state->stream) goto next_crtc; DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", @@ -4466,13 +4465,13 @@ static int dm_update_crtcs_state( if (!dc_remove_stream_from_ctx( dc, dm_state->context, - old_acrtc_state->stream)) { + dm_old_crtc_state->stream)) { ret = -EINVAL; goto fail; } - dc_stream_release(old_acrtc_state->stream); - new_acrtc_state->stream = NULL; + dc_stream_release(dm_old_crtc_state->stream); + dm_new_crtc_state->stream = NULL; *lock_and_validation_needed = true; @@ -4482,11 +4481,11 @@ static int dm_update_crtcs_state( goto next_crtc; if (modeset_required(new_crtc_state, new_stream, - old_acrtc_state->stream)) { + dm_old_crtc_state->stream)) { - WARN_ON(new_acrtc_state->stream); + WARN_ON(dm_new_crtc_state->stream); - new_acrtc_state->stream = new_stream; + dm_new_crtc_state->stream = new_stream; dc_stream_retain(new_stream); DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", @@ -4495,7 +4494,7 @@ static int dm_update_crtcs_state( if (!dc_add_stream_to_ctx( dc, dm_state->context, - new_acrtc_state->stream)) { + dm_new_crtc_state->stream)) { ret = -EINVAL; goto fail; } @@ -4528,9 +4527,9 @@ static int dm_update_planes_state( struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct drm_plane *plane; struct drm_plane_state *old_plane_state, *new_plane_state; - struct dm_crtc_state *new_acrtc_state, *old_acrtc_state; + struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - struct dm_plane_state *new_dm_plane_state, *old_dm_plane_state; + struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state; int i ; /* TODO return page_flip_needed() function */ bool pflip_needed = !state->allow_modeset; @@ -4543,8 +4542,8 @@ static int dm_update_planes_state( for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { new_plane_crtc = new_plane_state->crtc; old_plane_crtc = old_plane_state->crtc; - new_dm_plane_state = to_dm_plane_state(new_plane_state); - old_dm_plane_state = to_dm_plane_state(old_plane_state); + dm_new_plane_state = to_dm_plane_state(new_plane_state); + dm_old_plane_state = to_dm_plane_state(old_plane_state); /*TODO Implement atomic check for cursor plane */ if (plane->type == DRM_PLANE_TYPE_CURSOR) @@ -4558,9 +4557,9 @@ static int dm_update_planes_state( old_crtc_state = drm_atomic_get_old_crtc_state( state, old_plane_crtc); - old_acrtc_state = to_dm_crtc_state(old_crtc_state); + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!old_acrtc_state->stream) + if (!dm_old_crtc_state->stream) continue; DRM_DEBUG_DRIVER("Disabling DRM plane: %d on DRM crtc %d\n", @@ -4568,8 +4567,8 @@ static int dm_update_planes_state( if (!dc_remove_plane_from_context( dc, - old_acrtc_state->stream, - old_dm_plane_state->dc_state, + dm_old_crtc_state->stream, + dm_old_plane_state->dc_state, dm_state->context)) { ret = EINVAL; @@ -4577,8 +4576,8 @@ static int dm_update_planes_state( } - dc_plane_state_release(old_dm_plane_state->dc_state); - new_dm_plane_state->dc_state = NULL; + dc_plane_state_release(dm_old_plane_state->dc_state); + dm_new_plane_state->dc_state = NULL; *lock_and_validation_needed = true; @@ -4591,27 +4590,27 @@ static int dm_update_planes_state( continue; new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_crtc); - new_acrtc_state = to_dm_crtc_state(new_crtc_state); + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); - if (!new_acrtc_state->stream) + if (!dm_new_crtc_state->stream) continue; - WARN_ON(new_dm_plane_state->dc_state); + WARN_ON(dm_new_plane_state->dc_state); - new_dm_plane_state->dc_state = dc_create_plane_state(dc); + dm_new_plane_state->dc_state = dc_create_plane_state(dc); DRM_DEBUG_DRIVER("Enabling DRM plane: %d on DRM crtc %d\n", plane->base.id, new_plane_crtc->base.id); - if (!new_dm_plane_state->dc_state) { + if (!dm_new_plane_state->dc_state) { ret = -EINVAL; return ret; } ret = fill_plane_attributes( new_plane_crtc->dev->dev_private, - new_dm_plane_state->dc_state, + dm_new_plane_state->dc_state, new_plane_state, new_crtc_state, false); @@ -4621,8 +4620,8 @@ static int dm_update_planes_state( if (!dc_add_plane_to_context( dc, - new_acrtc_state->stream, - new_dm_plane_state->dc_state, + dm_new_crtc_state->stream, + dm_new_plane_state->dc_state, dm_state->context)) { ret = -EINVAL; @@ -4714,9 +4713,9 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, * decide how to handle. */ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { - struct dm_connector_state *con_old_state = to_dm_connector_state(old_con_state); - struct dm_connector_state *con_new_state = to_dm_connector_state(new_con_state); - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(con_new_state->base.crtc); + struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); + struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); + struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); /* Skip any modesets/resets */ if (!acrtc || drm_atomic_crtc_needs_modeset( @@ -4724,7 +4723,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, continue; /* Skip any thing not scale or underscan changes */ - if (!is_scaling_state_different(con_new_state, con_old_state)) + if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state)) continue; lock_and_validation_needed = true; -- cgit v1.2.3 From ebdd27e1a5440cb3f30952d105eb08cadafc431d Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 12 Oct 2017 17:15:10 -0400 Subject: drm/amd/display: Fix typo undersacn -> underscan Reviewed-by: Maarten Lankhorst Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index de88ee1af438..67222ffac96a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4144,7 +4144,7 @@ void amdgpu_dm_atomic_commit_tail( } } - /* Handle scaling and undersacn changes*/ + /* Handle scaling and underscan changes*/ for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { struct dm_connector_state *dm_new_con_state = to_dm_connector_state(new_con_state); struct dm_connector_state *dm_old_con_state = to_dm_connector_state(old_con_state); @@ -4707,7 +4707,7 @@ int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - /* Check scaling and undersacn changes*/ + /* Check scaling and underscan changes*/ /*TODO Removed scaling changes validation due to inability to commit * new stream into context w\o causing full reset. Need to * decide how to handle. -- cgit v1.2.3 From 5cc6dcbd45a60be4800cd5cc9a30bcc2e158e6a1 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 12 Oct 2017 17:15:11 -0400 Subject: drm/amd/display: Remove useless pcrtc pointer in amdgpu_dm_atomic_commit_tail. Just use crtc instead. Reviewed-by: Maarten Lankhorst Reviewed-by: Harry Wentland Reviewed-by: Alex Deucher Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 67222ffac96a..f9b57697be70 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4004,7 +4004,7 @@ void amdgpu_dm_atomic_commit_tail( struct dm_atomic_state *dm_state; uint32_t i, j; uint32_t new_crtcs_count = 0; - struct drm_crtc *crtc, *pcrtc; + struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct amdgpu_crtc *new_crtcs[MAX_STREAMS]; struct dc_stream_state *new_stream = NULL; @@ -4200,11 +4200,11 @@ void amdgpu_dm_atomic_commit_tail( } /* update planes when needed per crtc*/ - for_each_new_crtc_in_state(state, pcrtc, new_crtc_state, j) { + for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) { dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->stream) - amdgpu_dm_commit_planes(state, dev, dm, pcrtc, &wait_for_vblank); + amdgpu_dm_commit_planes(state, dev, dm, crtc, &wait_for_vblank); } -- cgit v1.2.3 From 1daf8c63480b35b967a63a40457c1b0ad866ee81 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 13 Oct 2017 14:04:26 -0400 Subject: drm/amd/display: fix typo in function name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit s/amdgpu_dm_find_first_crct_matching_connector/ amdgpu_dm_find_first_crtc_matching_connector/ And while here, make it static. Reviewed-by: Harry Wentland Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++----- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 5 ----- 2 files changed, 5 insertions(+), 10 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f9b57697be70..c2031eb5833f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -568,9 +568,9 @@ static int dm_suspend(void *handle) return ret; } -struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( - struct drm_atomic_state *state, - struct drm_crtc *crtc) +static struct amdgpu_dm_connector * +amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, + struct drm_crtc *crtc) { uint32_t i; struct drm_connector_state *new_con_state; @@ -4110,7 +4110,7 @@ void amdgpu_dm_atomic_commit_tail( dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); new_stream = dm_new_crtc_state->stream; - aconnector = amdgpu_dm_find_first_crct_matching_connector( + aconnector = amdgpu_dm_find_first_crtc_matching_connector( state, &new_crtcs[i]->base); if (!aconnector) { @@ -4396,7 +4396,7 @@ static int dm_update_crtcs_state( dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); acrtc = to_amdgpu_crtc(crtc); - aconnector = amdgpu_dm_find_first_crct_matching_connector(state, crtc); + aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); /* TODO This hack should go away */ if (aconnector) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1c55a0b5cd15..aca061aa4643 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -226,11 +226,6 @@ extern const struct amdgpu_ip_block_version dm_ip_block; void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *aconnector); -struct amdgpu_dm_connector *amdgpu_dm_find_first_crct_matching_connector( - struct drm_atomic_state *state, - struct drm_crtc *crtc); - - struct amdgpu_framebuffer; struct amdgpu_display_manager; struct dc_validation_set; -- cgit v1.2.3 From 3ee6b26b78e47825032726f807beb70be86ea20a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Oct 2017 17:44:52 -0400 Subject: drm/amd/display: whitespace cleanup in amdgpu_dm.c/h To match kernel standards. No intended functional change. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 330 ++++++++++------------ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 91 +++--- 2 files changed, 192 insertions(+), 229 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c2031eb5833f..f282fe8d5089 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -127,7 +127,7 @@ static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc) } static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, - u32 *vbl, u32 *position) + u32 *vbl, u32 *position) { uint32_t v_blank_start, v_blank_end, h_position, v_position; @@ -184,9 +184,9 @@ static int dm_soft_reset(void *handle) return 0; } -static struct amdgpu_crtc *get_crtc_by_otg_inst( - struct amdgpu_device *adev, - int otg_inst) +static struct amdgpu_crtc * +get_crtc_by_otg_inst(struct amdgpu_device *adev, + int otg_inst) { struct drm_device *dev = adev->ddev; struct drm_crtc *crtc; @@ -738,8 +738,8 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail }; -void amdgpu_dm_update_connector_after_detect( - struct amdgpu_dm_connector *aconnector) +void +amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) { struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; @@ -1490,11 +1490,10 @@ static const struct amdgpu_display_funcs dm_display_funcs = { #if defined(CONFIG_DEBUG_KERNEL_DC) -static ssize_t s3_debug_store( - struct device *device, - struct device_attribute *attr, - const char *buf, - size_t count) +static ssize_t s3_debug_store(struct device *device, + struct device_attribute *attr, + const char *buf, + size_t count) { int ret; int s3_state; @@ -1670,9 +1669,8 @@ static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = { .destroy = amdgpu_dm_encoder_destroy, }; -static bool fill_rects_from_plane_state( - const struct drm_plane_state *state, - struct dc_plane_state *plane_state) +static bool fill_rects_from_plane_state(const struct drm_plane_state *state, + struct dc_plane_state *plane_state) { plane_state->src_rect.x = state->src_x >> 16; plane_state->src_rect.y = state->src_y >> 16; @@ -1721,10 +1719,9 @@ static bool fill_rects_from_plane_state( return true; } -static int get_fb_info( - const struct amdgpu_framebuffer *amdgpu_fb, - uint64_t *tiling_flags, - uint64_t *fb_location) +static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, + uint64_t *tiling_flags, + uint64_t *fb_location) { struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->obj); int r = amdgpu_bo_reserve(rbo, false); @@ -1745,10 +1742,10 @@ static int get_fb_info( return r; } -static int fill_plane_attributes_from_fb( - struct amdgpu_device *adev, - struct dc_plane_state *plane_state, - const struct amdgpu_framebuffer *amdgpu_fb, bool addReq) +static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, + struct dc_plane_state *plane_state, + const struct amdgpu_framebuffer *amdgpu_fb, + bool addReq) { uint64_t tiling_flags; uint64_t fb_location = 0; @@ -1897,9 +1894,8 @@ static int fill_plane_attributes_from_fb( } -static void fill_gamma_from_crtc_state( - const struct drm_crtc_state *crtc_state, - struct dc_plane_state *plane_state) +static void fill_gamma_from_crtc_state(const struct drm_crtc_state *crtc_state, + struct dc_plane_state *plane_state) { int i; struct dc_gamma *gamma; @@ -1924,12 +1920,11 @@ static void fill_gamma_from_crtc_state( plane_state->gamma_correction = gamma; } -static int fill_plane_attributes( - struct amdgpu_device *adev, - struct dc_plane_state *dc_plane_state, - struct drm_plane_state *plane_state, - struct drm_crtc_state *crtc_state, - bool addrReq) +static int fill_plane_attributes(struct amdgpu_device *adev, + struct dc_plane_state *dc_plane_state, + struct drm_plane_state *plane_state, + struct drm_crtc_state *crtc_state, + bool addrReq) { const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); @@ -1968,8 +1963,8 @@ static int fill_plane_attributes( /*****************************************************************************/ -struct amdgpu_dm_connector *aconnector_from_drm_crtc_id( - const struct drm_crtc *crtc) +struct amdgpu_dm_connector * +aconnector_from_drm_crtc_id(const struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; struct drm_connector *connector; @@ -1992,10 +1987,9 @@ struct amdgpu_dm_connector *aconnector_from_drm_crtc_id( return NULL; } -static void update_stream_scaling_settings( - const struct drm_display_mode *mode, - const struct dm_connector_state *dm_state, - struct dc_stream_state *stream) +static void update_stream_scaling_settings(const struct drm_display_mode *mode, + const struct dm_connector_state *dm_state, + struct dc_stream_state *stream) { enum amdgpu_rmx_type rmx_type; @@ -2046,8 +2040,8 @@ static void update_stream_scaling_settings( } -static enum dc_color_depth convert_color_depth_from_display_info( - const struct drm_connector *connector) +static enum dc_color_depth +convert_color_depth_from_display_info(const struct drm_connector *connector) { uint32_t bpc = connector->display_info.bpc; @@ -2081,8 +2075,8 @@ static enum dc_color_depth convert_color_depth_from_display_info( } } -static enum dc_aspect_ratio get_aspect_ratio( - const struct drm_display_mode *mode_in) +static enum dc_aspect_ratio +get_aspect_ratio(const struct drm_display_mode *mode_in) { int32_t width = mode_in->crtc_hdisplay * 9; int32_t height = mode_in->crtc_vdisplay * 16; @@ -2093,8 +2087,8 @@ static enum dc_aspect_ratio get_aspect_ratio( return ASPECT_RATIO_4_3; } -static enum dc_color_space get_output_color_space( - const struct dc_crtc_timing *dc_crtc_timing) +static enum dc_color_space +get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing) { enum dc_color_space color_space = COLOR_SPACE_SRGB; @@ -2138,10 +2132,10 @@ static enum dc_color_space get_output_color_space( /*****************************************************************************/ -static void fill_stream_properties_from_drm_display_mode( - struct dc_stream_state *stream, - const struct drm_display_mode *mode_in, - const struct drm_connector *connector) +static void +fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, + const struct drm_display_mode *mode_in, + const struct drm_connector *connector) { struct dc_crtc_timing *timing_out = &stream->timing; @@ -2196,10 +2190,9 @@ static void fill_stream_properties_from_drm_display_mode( } } -static void fill_audio_info( - struct audio_info *audio_info, - const struct drm_connector *drm_connector, - const struct dc_sink *dc_sink) +static void fill_audio_info(struct audio_info *audio_info, + const struct drm_connector *drm_connector, + const struct dc_sink *dc_sink) { int i = 0; int cea_revision = 0; @@ -2244,9 +2237,9 @@ static void fill_audio_info( } -static void copy_crtc_timing_for_drm_display_mode( - const struct drm_display_mode *src_mode, - struct drm_display_mode *dst_mode) +static void +copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode, + struct drm_display_mode *dst_mode) { dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay; dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay; @@ -2264,10 +2257,10 @@ static void copy_crtc_timing_for_drm_display_mode( dst_mode->crtc_vtotal = src_mode->crtc_vtotal; } -static void decide_crtc_timing_for_drm_display_mode( - struct drm_display_mode *drm_mode, - const struct drm_display_mode *native_mode, - bool scale_enabled) +static void +decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, + const struct drm_display_mode *native_mode, + bool scale_enabled) { if (scale_enabled) { copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode); @@ -2299,10 +2292,10 @@ static void create_fake_sink(struct amdgpu_dm_connector *aconnector) aconnector->dc_link->local_sink = sink; } -static struct dc_stream_state *create_stream_for_sink( - struct amdgpu_dm_connector *aconnector, - const struct drm_display_mode *drm_mode, - const struct dm_connector_state *dm_state) +static struct dc_stream_state * +create_stream_for_sink(struct amdgpu_dm_connector *aconnector, + const struct drm_display_mode *drm_mode, + const struct dm_connector_state *dm_state) { struct drm_display_mode *preferred_mode = NULL; const struct drm_connector *drm_connector; @@ -2380,7 +2373,7 @@ void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) } static void dm_crtc_destroy_state(struct drm_crtc *crtc, - struct drm_crtc_state *state) + struct drm_crtc_state *state) { struct dm_crtc_state *cur = to_dm_crtc_state(state); @@ -2466,11 +2459,10 @@ amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) connector_status_disconnected); } -int amdgpu_dm_connector_atomic_set_property( - struct drm_connector *connector, - struct drm_connector_state *connector_state, - struct drm_property *property, - uint64_t val) +int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, + struct drm_connector_state *connector_state, + struct drm_property *property, + uint64_t val) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; @@ -2519,11 +2511,10 @@ int amdgpu_dm_connector_atomic_set_property( return ret; } -int amdgpu_dm_connector_atomic_get_property( - struct drm_connector *connector, - const struct drm_connector_state *state, - struct drm_property *property, - uint64_t *val) +int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; @@ -2605,8 +2596,8 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) } } -struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( - struct drm_connector *connector) +struct drm_connector_state * +amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) { struct dm_connector_state *state = to_dm_connector_state(connector->state); @@ -2711,9 +2702,8 @@ static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector) create_eml_sink(aconnector); } -int amdgpu_dm_connector_mode_valid( - struct drm_connector *connector, - struct drm_display_mode *mode) +int amdgpu_dm_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) { int result = MODE_ERROR; struct dc_sink *dc_sink; @@ -2780,9 +2770,8 @@ static void dm_crtc_helper_disable(struct drm_crtc *crtc) { } -static int dm_crtc_helper_atomic_check( - struct drm_crtc *crtc, - struct drm_crtc_state *state) +static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, + struct drm_crtc_state *state) { struct amdgpu_device *adev = crtc->dev->dev_private; struct dc *dc = adev->dm.dc; @@ -2805,10 +2794,9 @@ static int dm_crtc_helper_atomic_check( return ret; } -static bool dm_crtc_helper_mode_fixup( - struct drm_crtc *crtc, - const struct drm_display_mode *mode, - struct drm_display_mode *adjusted_mode) +static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, + const struct drm_display_mode *mode, + struct drm_display_mode *adjusted_mode) { return true; } @@ -2824,10 +2812,9 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } -static int dm_encoder_helper_atomic_check( - struct drm_encoder *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) { return 0; } @@ -2875,7 +2862,7 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) } void dm_drm_plane_destroy_state(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_plane_state *state) { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); @@ -2894,9 +2881,8 @@ static const struct drm_plane_funcs dm_plane_funcs = { .atomic_destroy_state = dm_drm_plane_destroy_state, }; -static int dm_plane_helper_prepare_fb( - struct drm_plane *plane, - struct drm_plane_state *new_state) +static int dm_plane_helper_prepare_fb(struct drm_plane *plane, + struct drm_plane_state *new_state) { struct amdgpu_framebuffer *afb; struct drm_gem_object *obj; @@ -2964,9 +2950,8 @@ static int dm_plane_helper_prepare_fb( return 0; } -static void dm_plane_helper_cleanup_fb( - struct drm_plane *plane, - struct drm_plane_state *old_state) +static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, + struct drm_plane_state *old_state) { struct amdgpu_bo *rbo; struct amdgpu_framebuffer *afb; @@ -2989,7 +2974,8 @@ static void dm_plane_helper_cleanup_fb( } int dm_create_validation_set_for_connector(struct drm_connector *connector, - struct drm_display_mode *mode, struct dc_validation_set *val_set) + struct drm_display_mode *mode, + struct dc_validation_set *val_set) { int result = MODE_ERROR; struct dc_sink *dc_sink = @@ -3027,7 +3013,7 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, } int dm_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) + struct drm_plane_state *state) { struct amdgpu_device *adev = plane->dev->dev_private; struct dc *dc = adev->dm.dc; @@ -3075,8 +3061,8 @@ static const u32 cursor_formats[] = { }; int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs) + struct amdgpu_plane *aplane, + unsigned long possible_crtcs) { int res = -EPERM; @@ -3224,9 +3210,10 @@ static void amdgpu_dm_get_native_mode(struct drm_connector *connector) } } -static struct drm_display_mode *amdgpu_dm_create_common_mode( - struct drm_encoder *encoder, char *name, - int hdisplay, int vdisplay) +static struct drm_display_mode * +amdgpu_dm_create_common_mode(struct drm_encoder *encoder, + char *name, + int hdisplay, int vdisplay) { struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -3248,7 +3235,7 @@ static struct drm_display_mode *amdgpu_dm_create_common_mode( } static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, - struct drm_connector *connector) + struct drm_connector *connector) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_display_mode *mode = NULL; @@ -3306,9 +3293,8 @@ static void amdgpu_dm_connector_add_common_modes(struct drm_encoder *encoder, } } -static void amdgpu_dm_connector_ddc_get_modes( - struct drm_connector *connector, - struct edid *edid) +static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, + struct edid *edid) { struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); @@ -3342,12 +3328,11 @@ int amdgpu_dm_connector_get_modes(struct drm_connector *connector) return amdgpu_dm_connector->num_modes; } -void amdgpu_dm_connector_init_helper( - struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *aconnector, - int connector_type, - struct dc_link *link, - int link_index) +void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, + struct amdgpu_dm_connector *aconnector, + int connector_type, + struct dc_link *link, + int link_index) { struct amdgpu_device *adev = dm->ddev->dev_private; @@ -3395,7 +3380,7 @@ void amdgpu_dm_connector_init_helper( } int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg *msgs, int num) + struct i2c_msg *msgs, int num) { struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); struct ddc_service *ddc_service = i2c->ddc_service; @@ -3439,10 +3424,10 @@ static const struct i2c_algorithm amdgpu_dm_i2c_algo = { .functionality = amdgpu_dm_i2c_func, }; -static struct amdgpu_i2c_adapter *create_i2c( - struct ddc_service *ddc_service, - int link_index, - int *res) +static struct amdgpu_i2c_adapter * +create_i2c(struct ddc_service *ddc_service, + int link_index, + int *res) { struct amdgpu_device *adev = ddc_service->ctx->driver_context; struct amdgpu_i2c_adapter *i2c; @@ -3462,11 +3447,10 @@ static struct amdgpu_i2c_adapter *create_i2c( /* Note: this function assumes that dc_link_detect() was called for the * dc_link which will be represented by this aconnector. */ -int amdgpu_dm_connector_init( - struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *aconnector, - uint32_t link_index, - struct amdgpu_encoder *aencoder) +int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, + struct amdgpu_dm_connector *aconnector, + uint32_t link_index, + struct amdgpu_encoder *aencoder) { int res = 0; int connector_type; @@ -3569,10 +3553,9 @@ int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) } } -int amdgpu_dm_encoder_init( - struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index) +int amdgpu_dm_encoder_init(struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index) { struct amdgpu_device *adev = dev->dev_private; @@ -3594,10 +3577,9 @@ int amdgpu_dm_encoder_init( return res; } -static void manage_dm_interrupts( - struct amdgpu_device *adev, - struct amdgpu_crtc *acrtc, - bool enable) +static void manage_dm_interrupts(struct amdgpu_device *adev, + struct amdgpu_crtc *acrtc, + bool enable) { /* * this is not correct translation but will work as soon as VBLANK @@ -3624,9 +3606,9 @@ static void manage_dm_interrupts( } } -static bool is_scaling_state_different( - const struct dm_connector_state *dm_state, - const struct dm_connector_state *old_dm_state) +static bool +is_scaling_state_different(const struct dm_connector_state *dm_state, + const struct dm_connector_state *old_dm_state) { if (dm_state->scaling != old_dm_state->scaling) return true; @@ -3642,10 +3624,9 @@ static bool is_scaling_state_different( return false; } -static void remove_stream( - struct amdgpu_device *adev, - struct amdgpu_crtc *acrtc, - struct dc_stream_state *stream) +static void remove_stream(struct amdgpu_device *adev, + struct amdgpu_crtc *acrtc, + struct dc_stream_state *stream) { /* this is the update mode case */ if (adev->dm.freesync_module) @@ -3656,7 +3637,7 @@ static void remove_stream( } int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, - struct dc_cursor_position *position) + struct dc_cursor_position *position) { struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc); int x, y; @@ -3700,9 +3681,8 @@ int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, return 0; } -static void handle_cursor_update( - struct drm_plane *plane, - struct drm_plane_state *old_plane_state) +static void handle_cursor_update(struct drm_plane *plane, + struct drm_plane_state *old_plane_state) { struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(plane->state->fb); struct drm_crtc *crtc = afb ? plane->state->crtc : old_plane_state->crtc; @@ -3780,10 +3760,9 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc) * * Waits on all BO's fences and for proper vblank count */ -static void amdgpu_dm_do_flip( - struct drm_crtc *crtc, - struct drm_framebuffer *fb, - uint32_t target) +static void amdgpu_dm_do_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + uint32_t target) { unsigned long flags; uint32_t target_vblank; @@ -3866,10 +3845,10 @@ static void amdgpu_dm_do_flip( } static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, - struct drm_device *dev, - struct amdgpu_display_manager *dm, - struct drm_crtc *pcrtc, - bool *wait_for_vblank) + struct drm_device *dev, + struct amdgpu_display_manager *dm, + struct drm_crtc *pcrtc, + bool *wait_for_vblank) { uint32_t i; struct drm_plane *plane; @@ -3965,10 +3944,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock) +int amdgpu_dm_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -3995,8 +3973,7 @@ int amdgpu_dm_atomic_commit( /*TODO Handle EINTR, reenable IRQ*/ } -void amdgpu_dm_atomic_commit_tail( - struct drm_atomic_state *state) +void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = dev->dev_private; @@ -4294,7 +4271,8 @@ err: * This include when the same display is unplugged then plugged back into the * same port and when we are running without usermode desktop manager supprot */ -void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector) +void dm_restore_drm_connector_state(struct drm_device *dev, + struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct amdgpu_crtc *disconnected_acrtc; @@ -4322,9 +4300,8 @@ void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector * Grabs all modesetting locks to serialize against any blocking commits, * Waits for completion of all non blocking commits. */ -static int do_aquire_global_lock( - struct drm_device *dev, - struct drm_atomic_state *state) +static int do_aquire_global_lock(struct drm_device *dev, + struct drm_atomic_state *state) { struct drm_crtc *crtc; struct drm_crtc_commit *commit; @@ -4368,11 +4345,10 @@ static int do_aquire_global_lock( return ret < 0 ? ret : 0; } -static int dm_update_crtcs_state( - struct dc *dc, - struct drm_atomic_state *state, - bool enable, - bool *lock_and_validation_needed) +static int dm_update_crtcs_state(struct dc *dc, + struct drm_atomic_state *state, + bool enable, + bool *lock_and_validation_needed) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -4517,11 +4493,10 @@ fail: return ret; } -static int dm_update_planes_state( - struct dc *dc, - struct drm_atomic_state *state, - bool enable, - bool *lock_and_validation_needed) +static int dm_update_planes_state(struct dc *dc, + struct drm_atomic_state *state, + bool enable, + bool *lock_and_validation_needed) { struct drm_crtc *new_plane_crtc, *old_plane_crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -4637,7 +4612,7 @@ static int dm_update_planes_state( } int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) + struct drm_atomic_state *state) { int i; int ret; @@ -4766,9 +4741,8 @@ fail: return ret; } -static bool is_dp_capable_without_timing_msa( - struct dc *dc, - struct amdgpu_dm_connector *amdgpu_dm_connector) +static bool is_dp_capable_without_timing_msa(struct dc *dc, + struct amdgpu_dm_connector *amdgpu_dm_connector) { uint8_t dpcd_data; bool capable = false; @@ -4785,9 +4759,8 @@ static bool is_dp_capable_without_timing_msa( return capable; } -void amdgpu_dm_add_sink_to_freesync_module( - struct drm_connector *connector, - struct edid *edid) +void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, + struct edid *edid) { int i; uint64_t val_capable; @@ -4867,8 +4840,7 @@ void amdgpu_dm_add_sink_to_freesync_module( } -void amdgpu_dm_remove_sink_from_freesync_module( - struct drm_connector *connector) +void amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector) { /* * TODO fill in once we figure out how to deal with freesync in diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index aca061aa4643..eb20642403ae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -206,12 +206,10 @@ void amdgpu_dm_destroy(void); * * Returns 0 on success */ -int amdgpu_dm_initialize_drm_device( - struct amdgpu_device *adev); +int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); /* removes and deallocates the drm structures, created by the above function */ -void amdgpu_dm_destroy_drm_device( - struct amdgpu_display_manager *dm); +void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); /* Locking/Mutex */ bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm); @@ -223,8 +221,8 @@ void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm); extern const struct amdgpu_ip_block_version dm_ip_block; -void amdgpu_dm_update_connector_after_detect( - struct amdgpu_dm_connector *aconnector); +void +amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); struct amdgpu_framebuffer; struct amdgpu_display_manager; @@ -256,19 +254,18 @@ struct dm_atomic_state { /*TODO Jodan Hersen use the one in amdgpu_dm*/ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs); + struct amdgpu_plane *aplane, + unsigned long possible_crtcs); int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, struct drm_plane *plane, uint32_t link_index); int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *amdgpu_dm_connector, - uint32_t link_index, - struct amdgpu_encoder *amdgpu_encoder); -int amdgpu_dm_encoder_init( - struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index); + struct amdgpu_dm_connector *amdgpu_dm_connector, + uint32_t link_index, + struct amdgpu_encoder *amdgpu_encoder); +int amdgpu_dm_encoder_init(struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index); void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc); void amdgpu_dm_connector_destroy(struct drm_connector *connector); @@ -276,53 +273,47 @@ void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); int amdgpu_dm_connector_get_modes(struct drm_connector *connector); -int amdgpu_dm_atomic_commit( - struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); +int amdgpu_dm_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock); -void amdgpu_dm_atomic_commit_tail( - struct drm_atomic_state *state); +void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); + struct drm_atomic_state *state); void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); -struct drm_connector_state *amdgpu_dm_connector_atomic_duplicate_state( - struct drm_connector *connector); -int amdgpu_dm_connector_atomic_set_property( - struct drm_connector *connector, - struct drm_connector_state *state, - struct drm_property *property, - uint64_t val); - -int amdgpu_dm_connector_atomic_get_property( - struct drm_connector *connector, - const struct drm_connector_state *state, - struct drm_property *property, - uint64_t *val); +struct drm_connector_state * +amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); +int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, + struct drm_connector_state *state, + struct drm_property *property, + uint64_t val); + +int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, + const struct drm_connector_state *state, + struct drm_property *property, + uint64_t *val); int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); -void amdgpu_dm_connector_init_helper( - struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *aconnector, - int connector_type, - struct dc_link *link, - int link_index); +void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, + struct amdgpu_dm_connector *aconnector, + int connector_type, + struct dc_link *link, + int link_index); -int amdgpu_dm_connector_mode_valid( - struct drm_connector *connector, - struct drm_display_mode *mode); +int amdgpu_dm_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode); -void dm_restore_drm_connector_state(struct drm_device *dev, struct drm_connector *connector); +void dm_restore_drm_connector_state(struct drm_device *dev, + struct drm_connector *connector); -void amdgpu_dm_add_sink_to_freesync_module( - struct drm_connector *connector, - struct edid *edid); +void amdgpu_dm_add_sink_to_freesync_module(struct drm_connector *connector, + struct edid *edid); -void amdgpu_dm_remove_sink_from_freesync_module( - struct drm_connector *connector); +void +amdgpu_dm_remove_sink_from_freesync_module(struct drm_connector *connector); extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; -- cgit v1.2.3 From 7578ecda14d521f39e74166103270c62b15af96d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Oct 2017 17:51:02 -0400 Subject: drm/amd/display: make a bunch of stuff in amdgpu_dm.c static Not used outside of that file. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 136 +++++++++++++++------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 59 ---------- 2 files changed, 91 insertions(+), 104 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f282fe8d5089..051cb371e88b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -70,6 +70,50 @@ #include "i2caux_interface.h" +/* basic init/fini API */ +static int amdgpu_dm_init(struct amdgpu_device *adev); +static void amdgpu_dm_fini(struct amdgpu_device *adev); + +/* initializes drm_device display related structures, based on the information + * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, + * drm_encoder, drm_mode_config + * + * Returns 0 on success + */ +static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); +/* removes and deallocates the drm structures, created by the above function */ +static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); + +static void +amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); + +static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs); +static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t link_index); +static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, + struct amdgpu_dm_connector *amdgpu_dm_connector, + uint32_t link_index, + struct amdgpu_encoder *amdgpu_encoder); +static int amdgpu_dm_encoder_init(struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index); + +static int amdgpu_dm_connector_get_modes(struct drm_connector *connector); + +static int amdgpu_dm_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock); + +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); + +static int amdgpu_dm_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state); + + + static const enum drm_plane_type dm_plane_type_default[AMDGPU_MAX_PLANES] = { DRM_PLANE_TYPE_PRIMARY, @@ -306,7 +350,7 @@ static void hotplug_notify_work_func(struct work_struct *work) /* TODO: Dynamic allocation */ #define AMDGPU_FBC_SIZE (3840 * 2160 * 4) -void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev) +static void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev) { int r; struct dm_comressor_info *compressor = &adev->dm.compressor; @@ -328,7 +372,7 @@ void amdgpu_dm_initialize_fbc(struct amdgpu_device *adev) * * Returns 0 on success */ -int amdgpu_dm_init(struct amdgpu_device *adev) +static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; adev->dm.ddev = adev->ddev; @@ -431,7 +475,7 @@ error: return -1; } -void amdgpu_dm_fini(struct amdgpu_device *adev) +static void amdgpu_dm_fini(struct amdgpu_device *adev) { amdgpu_dm_destroy_drm_device(&adev->dm); /* @@ -455,7 +499,7 @@ void amdgpu_dm_fini(struct amdgpu_device *adev) } /* moved from amdgpu_dm_kms.c */ -void amdgpu_dm_destroy() +static void amdgpu_dm_destroy(void) { } @@ -685,7 +729,7 @@ const struct amdgpu_ip_block_version dm_ip_block = }; -struct drm_atomic_state * +static struct drm_atomic_state * dm_atomic_state_alloc(struct drm_device *dev) { struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); @@ -738,7 +782,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail }; -void +static void amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) { struct drm_connector *connector = &aconnector->base; @@ -1245,7 +1289,8 @@ static const struct backlight_ops amdgpu_dm_backlight_ops = { .update_status = amdgpu_dm_backlight_update_status, }; -void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) +static void +amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) { char bl_name[16]; struct backlight_properties props = { 0 }; @@ -1277,7 +1322,7 @@ void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) * * Returns 0 on success */ -int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) +static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) { struct amdgpu_display_manager *dm = &adev->dm; uint32_t i; @@ -1410,7 +1455,7 @@ fail_free_planes: return -1; } -void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) +static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { drm_mode_config_cleanup(dm->ddev); return; @@ -1613,13 +1658,13 @@ static int dm_early_init(void *handle) return 0; } -bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) +static bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) { /* TODO */ return true; } -bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) +static bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) { /* TODO */ return true; @@ -1659,7 +1704,7 @@ static bool modereset_required(struct drm_crtc_state *crtc_state) return !crtc_state->enable || !crtc_state->active; } -void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) +static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) { drm_encoder_cleanup(encoder); kfree(encoder); @@ -1963,7 +2008,7 @@ static int fill_plane_attributes(struct amdgpu_device *adev, /*****************************************************************************/ -struct amdgpu_dm_connector * +static struct amdgpu_dm_connector * aconnector_from_drm_crtc_id(const struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; @@ -2366,7 +2411,7 @@ drm_connector_null: return stream; } -void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) +static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc) { drm_crtc_cleanup(crtc); kfree(crtc); @@ -2552,7 +2597,7 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, return ret; } -void amdgpu_dm_connector_destroy(struct drm_connector *connector) +static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); const struct dc_link *link = aconnector->dc_link; @@ -2973,9 +3018,10 @@ static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, amdgpu_bo_unref(&rbo); } -int dm_create_validation_set_for_connector(struct drm_connector *connector, - struct drm_display_mode *mode, - struct dc_validation_set *val_set) +static int +dm_create_validation_set_for_connector(struct drm_connector *connector, + struct drm_display_mode *mode, + struct dc_validation_set *val_set) { int result = MODE_ERROR; struct dc_sink *dc_sink = @@ -3012,8 +3058,8 @@ int dm_create_validation_set_for_connector(struct drm_connector *connector, return MODE_OK; } -int dm_plane_atomic_check(struct drm_plane *plane, - struct drm_plane_state *state) +static int dm_plane_atomic_check(struct drm_plane *plane, + struct drm_plane_state *state) { struct amdgpu_device *adev = plane->dev->dev_private; struct dc *dc = adev->dm.dc; @@ -3060,9 +3106,9 @@ static const u32 cursor_formats[] = { DRM_FORMAT_ARGB8888 }; -int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs) +static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + struct amdgpu_plane *aplane, + unsigned long possible_crtcs) { int res = -EPERM; @@ -3106,9 +3152,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, return res; } -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct drm_plane *plane, - uint32_t crtc_index) +static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + struct drm_plane *plane, + uint32_t crtc_index) { struct amdgpu_crtc *acrtc = NULL; struct amdgpu_plane *cursor_plane; @@ -3312,7 +3358,7 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, amdgpu_dm_connector->num_modes = 0; } -int amdgpu_dm_connector_get_modes(struct drm_connector *connector) +static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) { const struct drm_connector_helper_funcs *helper = connector->helper_private; @@ -3379,8 +3425,8 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, } -int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, - struct i2c_msg *msgs, int num) +static int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, + struct i2c_msg *msgs, int num) { struct amdgpu_i2c_adapter *i2c = i2c_get_adapdata(i2c_adap); struct ddc_service *ddc_service = i2c->ddc_service; @@ -3414,7 +3460,7 @@ int amdgpu_dm_i2c_xfer(struct i2c_adapter *i2c_adap, return result; } -u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) +static u32 amdgpu_dm_i2c_func(struct i2c_adapter *adap) { return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; } @@ -3447,10 +3493,10 @@ create_i2c(struct ddc_service *ddc_service, /* Note: this function assumes that dc_link_detect() was called for the * dc_link which will be represented by this aconnector. */ -int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *aconnector, - uint32_t link_index, - struct amdgpu_encoder *aencoder) +static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, + struct amdgpu_dm_connector *aconnector, + uint32_t link_index, + struct amdgpu_encoder *aencoder) { int res = 0; int connector_type; @@ -3553,9 +3599,9 @@ int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev) } } -int amdgpu_dm_encoder_init(struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index) +static int amdgpu_dm_encoder_init(struct drm_device *dev, + struct amdgpu_encoder *aencoder, + uint32_t link_index) { struct amdgpu_device *adev = dev->dev_private; @@ -3636,8 +3682,8 @@ static void remove_stream(struct amdgpu_device *adev, acrtc->enabled = false; } -int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, - struct dc_cursor_position *position) +static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, + struct dc_cursor_position *position) { struct amdgpu_crtc *amdgpu_crtc = amdgpu_crtc = to_amdgpu_crtc(crtc); int x, y; @@ -3944,9 +3990,9 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } -int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock) +static int amdgpu_dm_atomic_commit(struct drm_device *dev, + struct drm_atomic_state *state, + bool nonblock) { struct drm_crtc *crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; @@ -3973,7 +4019,7 @@ int amdgpu_dm_atomic_commit(struct drm_device *dev, /*TODO Handle EINTR, reenable IRQ*/ } -void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) +static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) { struct drm_device *dev = state->dev; struct amdgpu_device *adev = dev->dev_private; @@ -4611,8 +4657,8 @@ static int dm_update_planes_state(struct dc *dc, return ret; } -int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state) +static int amdgpu_dm_atomic_check(struct drm_device *dev, + struct drm_atomic_state *state) { int i; int ret; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index eb20642403ae..be3b70d683e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -193,37 +193,8 @@ struct amdgpu_dm_connector { #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) -/* basic init/fini API */ -int amdgpu_dm_init(struct amdgpu_device *adev); - -void amdgpu_dm_fini(struct amdgpu_device *adev); - -void amdgpu_dm_destroy(void); - -/* initializes drm_device display related structures, based on the information - * provided by DAL. The drm strcutures are: drm_crtc, drm_connector, - * drm_encoder, drm_mode_config - * - * Returns 0 on success - */ -int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev); - -/* removes and deallocates the drm structures, created by the above function */ -void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm); - -/* Locking/Mutex */ -bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm); - -bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm); - -/* Register "Backlight device" accessible by user-mode. */ -void amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm); - extern const struct amdgpu_ip_block_version dm_ip_block; -void -amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector); - struct amdgpu_framebuffer; struct amdgpu_display_manager; struct dc_validation_set; @@ -252,36 +223,6 @@ struct dm_atomic_state { #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) -/*TODO Jodan Hersen use the one in amdgpu_dm*/ -int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - struct amdgpu_plane *aplane, - unsigned long possible_crtcs); -int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - struct drm_plane *plane, - uint32_t link_index); -int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, - struct amdgpu_dm_connector *amdgpu_dm_connector, - uint32_t link_index, - struct amdgpu_encoder *amdgpu_encoder); -int amdgpu_dm_encoder_init(struct drm_device *dev, - struct amdgpu_encoder *aencoder, - uint32_t link_index); - -void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc); -void amdgpu_dm_connector_destroy(struct drm_connector *connector); -void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder); - -int amdgpu_dm_connector_get_modes(struct drm_connector *connector); - -int amdgpu_dm_atomic_commit(struct drm_device *dev, - struct drm_atomic_state *state, - bool nonblock); - -void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); - -int amdgpu_dm_atomic_check(struct drm_device *dev, - struct drm_atomic_state *state); - void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); struct drm_connector_state * amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); -- cgit v1.2.3 From b4133c09e47afe4c2a5485eb33c7cf456ce0241f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Oct 2017 17:53:24 -0400 Subject: drm/amd/display: drop unused functions in amdgpu_dm.c Not used anywhere. Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 82 ----------------------- 1 file changed, 82 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 051cb371e88b..e98bb639268d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -498,11 +498,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) return; } -/* moved from amdgpu_dm_kms.c */ -static void amdgpu_dm_destroy(void) -{ -} - static int dm_sw_init(void *handle) { return 0; @@ -1658,19 +1653,6 @@ static int dm_early_init(void *handle) return 0; } -static bool amdgpu_dm_acquire_dal_lock(struct amdgpu_display_manager *dm) -{ - /* TODO */ - return true; -} - -static bool amdgpu_dm_release_dal_lock(struct amdgpu_display_manager *dm) -{ - /* TODO */ - return true; -} - - struct dm_connector_state { struct drm_connector_state base; @@ -2008,30 +1990,6 @@ static int fill_plane_attributes(struct amdgpu_device *adev, /*****************************************************************************/ -static struct amdgpu_dm_connector * -aconnector_from_drm_crtc_id(const struct drm_crtc *crtc) -{ - struct drm_device *dev = crtc->dev; - struct drm_connector *connector; - struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); - struct amdgpu_dm_connector *aconnector; - - list_for_each_entry(connector, - &dev->mode_config.connector_list, head) { - - aconnector = to_amdgpu_dm_connector(connector); - - if (aconnector->base.state->crtc != &acrtc->base) - continue; - - /* Found the connector */ - return aconnector; - } - - /* If we get here, not found. */ - return NULL; -} - static void update_stream_scaling_settings(const struct drm_display_mode *mode, const struct dm_connector_state *dm_state, struct dc_stream_state *stream) @@ -3018,46 +2976,6 @@ static void dm_plane_helper_cleanup_fb(struct drm_plane *plane, amdgpu_bo_unref(&rbo); } -static int -dm_create_validation_set_for_connector(struct drm_connector *connector, - struct drm_display_mode *mode, - struct dc_validation_set *val_set) -{ - int result = MODE_ERROR; - struct dc_sink *dc_sink = - to_amdgpu_dm_connector(connector)->dc_sink; - /* TODO: Unhardcode stream count */ - struct dc_stream_state *stream; - - if ((mode->flags & DRM_MODE_FLAG_INTERLACE) || - (mode->flags & DRM_MODE_FLAG_DBLSCAN)) - return result; - - if (dc_sink == NULL) { - DRM_ERROR("dc_sink is NULL!\n"); - return result; - } - - stream = dc_create_stream_for_sink(dc_sink); - - if (stream == NULL) { - DRM_ERROR("Failed to create stream for sink!\n"); - return result; - } - - drm_mode_set_crtcinfo(mode, 0); - - fill_stream_properties_from_drm_display_mode(stream, mode, connector); - - val_set->stream = stream; - - stream->src.width = mode->hdisplay; - stream->src.height = mode->vdisplay; - stream->dst = stream->src; - - return MODE_OK; -} - static int dm_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { -- cgit v1.2.3 From 8580d60baed5c8c9f08a5c3b239e563c8966a9dc Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 17 Aug 2017 14:58:07 -0400 Subject: drm/amd/display: Don't report fake sink as connected This was missed in the previous fake sink change. The fake sink allows us to enable a pipe with a disconnected display. We shouldn't report it as connected. Signed-off-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8cc228ebdc9a..75212f74f027 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2453,7 +2453,8 @@ amdgpu_dm_connector_detect(struct drm_connector *connector, bool force) * 2. This interface *is called* in context of user-mode ioctl. Which * makes it a bad place for *any* MST-related activit. */ - if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) + if (aconnector->base.force == DRM_FORCE_UNSPECIFIED && + !aconnector->fake_enable) connected = (aconnector->dc_sink != NULL); else connected = (aconnector->base.force == DRM_FORCE_ON); -- cgit v1.2.3 From 4f346e655d24140fb40b46f814506ba17ac34ea1 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Thu, 7 Sep 2017 17:05:38 -0400 Subject: drm/amd/display: Match actual state during S3 resume. During system suspend, we: 1. Cache a duplicate of the current DRM atomic state, which calls hooks to duplicate our internal states. 2. Call hooks to disable all functionalities. 3. System suspended. During resume, we attempt to restore the cached state. However, our interal states are now stale, since step 1 was done before step 2. i.e. our cached state does not reflect the disabled nature of things. This change resolves that by destroying all relevant states to reflect the actual state during resume. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 36 +++++++++++++++++++++++ 1 file changed, 36 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 75212f74f027..ecca2862407f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -648,6 +648,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) struct drm_connector *connector; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + struct dm_crtc_state *dm_crtc_state; + struct drm_plane *plane; + struct drm_plane_state *plane_state; + struct dm_plane_state *dm_plane_state; + struct dm_atomic_state *cached_state; int ret = 0; int i; @@ -686,6 +691,37 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) new_crtc_state->active_changed = true; + cached_state = to_dm_atomic_state(adev->dm.cached_state); + + /* + * During suspend, the cached state is saved before all streams are + * disabled. Refresh cached state to match actual current state before + * restoring it. + */ + WARN_ON(kref_read(&cached_state->context->refcount) > 1); + dc_release_state(cached_state->context); + + cached_state->context = dc_create_state(); + dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context); + + for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { + dm_crtc_state = to_dm_crtc_state(new_crtc_state); + if (dm_crtc_state->stream) { + WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1); + dc_stream_release(dm_crtc_state->stream); + dm_crtc_state->stream = NULL; + } + } + + for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) { + dm_plane_state = to_dm_plane_state(plane_state); + if (dm_plane_state->dc_state) { + WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1); + dc_plane_state_release(dm_plane_state->dc_state); + dm_plane_state->dc_state = NULL; + } + } + ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); drm_atomic_state_put(adev->dm.cached_state); -- cgit v1.2.3 From f4ac176e62fdc74e52ee58461fb7c8912322fc1c Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 8 Sep 2017 11:52:45 -0400 Subject: drm/amd/display: Exclude MST from fake sink Needs effort to take care of the fake sink scenario in downstream daisy chain device. Exclude MST from fake sink feature for now. Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ecca2862407f..dfea04fed695 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2354,8 +2354,16 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, drm_connector = &aconnector->base; - if (!aconnector->dc_sink) + if (!aconnector->dc_sink) { + /* + * Exclude MST from creating fake_sink + * TODO: need to enable MST into fake_sink feature + */ + if (aconnector->mst_port) + goto stream_create_fail; + create_fake_sink(aconnector); + } stream = dc_create_stream_for_sink(aconnector->dc_sink); @@ -4376,7 +4384,8 @@ static int dm_update_crtcs_state(struct dc *dc, aconnector = amdgpu_dm_find_first_crtc_matching_connector(state, crtc); /* TODO This hack should go away */ - if (aconnector) { + if (aconnector && enable) { + // Make sure fake sink is created in plug-in scenario new_con_state = drm_atomic_get_connector_state(state, &aconnector->base); -- cgit v1.2.3 From fc17235fe65b0179969e0793a086cba93afcc078 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 8 Sep 2017 16:40:34 -0400 Subject: drm/amd/display: Fix NULL pointer on MST chained mode Prevent NULL pointer on new_stream being added to ctx when added MST connectors cannot be found in existing crtc_state in the chained mode Signed-off-by: Jerry Zuo Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dfea04fed695..f2724713ddd0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4462,6 +4462,13 @@ static int dm_update_crtcs_state(struct dc *dc, *lock_and_validation_needed = true; } else {/* Add stream for any updated/enabled CRTC */ + /* + * Quick fix to prevent NULL pointer on new_stream when + * added MST connectors not found in existing crtc_state in the chained mode + * TODO: need to dig out the root cause of that + */ + if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) + continue; if (modereset_required(new_crtc_state)) goto next_crtc; -- cgit v1.2.3 From bc6828e0e6b6c5bcafbb093f9fe475f63dbe47e5 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Tue, 12 Sep 2017 13:56:57 -0400 Subject: drm/amd/display: Refactor dc_update_planes_and_stream. Split update_planes_and_stream_state (split Software and Hardware programming) as the state is already build, so we only need to program the hardware Signed-off-by: Andrey Grodzovsky Signed-off-by: Bhawanpreet Lakha Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 256 +++++----------------- drivers/gpu/drm/amd/display/dc/dc.h | 36 +-- 3 files changed, 87 insertions(+), 226 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f2724713ddd0..6c04ad1b5859 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3771,7 +3771,8 @@ static void prepare_flip_isr(struct amdgpu_crtc *acrtc) */ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, - uint32_t target) + uint32_t target, + struct dc_state *state) { unsigned long flags; uint32_t target_vblank; @@ -3842,7 +3843,13 @@ static void amdgpu_dm_do_flip(struct drm_crtc *crtc, surface_updates->flip_addr = &addr; - dc_update_planes_and_stream(adev->dm.dc, surface_updates, 1, acrtc_state->stream, NULL); + dc_commit_updates_for_stream(adev->dm.dc, + surface_updates, + 1, + acrtc_state->stream, + NULL, + &surface_updates->surface, + state); DRM_DEBUG_DRIVER("%s Flipping to hi: 0x%x, low: 0x%x \n", __func__, @@ -3868,6 +3875,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, struct drm_crtc_state *new_pcrtc_state = drm_atomic_get_new_crtc_state(state, pcrtc); struct dm_crtc_state *acrtc_state = to_dm_crtc_state(new_pcrtc_state); + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); int planes_count = 0; unsigned long flags; @@ -3925,7 +3933,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, amdgpu_dm_do_flip( crtc, fb, - drm_crtc_vblank_count(crtc) + *wait_for_vblank); + drm_crtc_vblank_count(crtc) + *wait_for_vblank, + dm_state->context); } } @@ -3945,7 +3954,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (false == dc_commit_planes_to_stream(dm->dc, plane_states_constructed, planes_count, - dc_stream_attach)) + dc_stream_attach, + dm_state->context)) dm_error("%s: Failed to attach plane!\n", __func__); } else { /*TODO BUG Here should go disable planes on CRTC. */ @@ -4165,7 +4175,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) dm->dc, status->plane_states, status->plane_count, - dm_new_crtc_state->stream)) + dm_new_crtc_state->stream, + dm_state->context)) dm_error("%s: Failed to update stream scaling!\n", __func__); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 47f16a4b9f27..1ec6df9870da 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -869,7 +869,8 @@ bool dc_commit_planes_to_stream( struct dc *dc, struct dc_plane_state **plane_states, uint8_t new_plane_count, - struct dc_stream_state *dc_stream) + struct dc_stream_state *dc_stream, + struct dc_state *state) { struct dc_surface_update updates[MAX_SURFACES]; struct dc_flip_addrs flip_addr[MAX_SURFACES]; @@ -920,11 +921,11 @@ bool dc_commit_planes_to_stream( updates[i].scaling_info = &scaling_info[i]; } - dc_update_planes_and_stream( + dc_commit_updates_for_stream( dc, updates, new_plane_count, - dc_stream, stream_update); + dc_stream, stream_update, plane_states, state); dc_post_update_surfaces_to_stream(dc); @@ -1150,192 +1151,20 @@ static struct dc_stream_status *stream_get_status( static const enum surface_update_type update_surface_trace_level = UPDATE_TYPE_FULL; -void dc_update_planes_and_stream(struct dc *dc, - struct dc_surface_update *srf_updates, int surface_count, + +static void commit_planes_for_stream(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, struct dc_stream_state *stream, - struct dc_stream_update *stream_update) + struct dc_stream_update *stream_update, + enum surface_update_type update_type, + struct dc_state *context) { - struct dc_state *context; int i, j; - enum surface_update_type update_type; - const struct dc_stream_status *stream_status; - struct dc_context *dc_ctx = dc->ctx; - - stream_status = dc_stream_get_status(stream); - - ASSERT(stream_status); - if (!stream_status) - return; /* Cannot commit surface to stream that is not committed */ - -#ifdef ENABLE_FBC - if (srf_updates->flip_addr) { - if (srf_updates->flip_addr->address.grph.addr.low_part == 0) - ASSERT(0); - } -#endif - context = dc->current_state; - - /* update current stream with the new updates */ - if (stream_update) { - if ((stream_update->src.height != 0) && - (stream_update->src.width != 0)) - stream->src = stream_update->src; - - if ((stream_update->dst.height != 0) && - (stream_update->dst.width != 0)) - stream->dst = stream_update->dst; - - if (stream_update->out_transfer_func && - stream_update->out_transfer_func != - stream->out_transfer_func) { - if (stream->out_transfer_func != NULL) - dc_transfer_func_release(stream->out_transfer_func); - dc_transfer_func_retain(stream_update->out_transfer_func); - stream->out_transfer_func = - stream_update->out_transfer_func; - } - } - - /* do not perform surface update if surface has invalid dimensions - * (all zero) and no scaling_info is provided - */ - if (surface_count > 0 && - srf_updates->surface->src_rect.width == 0 && - srf_updates->surface->src_rect.height == 0 && - srf_updates->surface->dst_rect.width == 0 && - srf_updates->surface->dst_rect.height == 0 && - !srf_updates->scaling_info) { - ASSERT(false); - return; - } - - update_type = dc_check_update_surfaces_for_stream( - dc, srf_updates, surface_count, stream_update, stream_status); - - if (update_type >= update_surface_trace_level) - update_surface_trace(dc, srf_updates, surface_count); - - if (update_type >= UPDATE_TYPE_FULL) { - struct dc_plane_state *new_planes[MAX_SURFACES] = {0}; - - for (i = 0; i < surface_count; i++) - new_planes[i] = srf_updates[i].surface; - - /* initialize scratch memory for building context */ - context = dc_create_state(); - if (context == NULL) { - DC_ERROR("Failed to allocate new validate context!\n"); - return; - } - - dc_resource_state_copy_construct( - dc->current_state, context); - - /*remove old surfaces from context */ - if (!dc_rem_all_planes_for_stream(dc, stream, context)) { - - BREAK_TO_DEBUGGER(); - goto fail; - } - - /* add surface to context */ - if (!dc_add_all_planes_for_stream(dc, stream, new_planes, surface_count, context)) { - - BREAK_TO_DEBUGGER(); - goto fail; - } - } - - /* save update parameters into surface */ - for (i = 0; i < surface_count; i++) { - struct dc_plane_state *surface = srf_updates[i].surface; - - if (srf_updates[i].flip_addr) { - surface->address = srf_updates[i].flip_addr->address; - surface->flip_immediate = - srf_updates[i].flip_addr->flip_immediate; - } - - if (srf_updates[i].scaling_info) { - surface->scaling_quality = - srf_updates[i].scaling_info->scaling_quality; - surface->dst_rect = - srf_updates[i].scaling_info->dst_rect; - surface->src_rect = - srf_updates[i].scaling_info->src_rect; - surface->clip_rect = - srf_updates[i].scaling_info->clip_rect; - } - - if (srf_updates[i].plane_info) { - surface->color_space = - srf_updates[i].plane_info->color_space; - surface->format = - srf_updates[i].plane_info->format; - surface->plane_size = - srf_updates[i].plane_info->plane_size; - surface->rotation = - srf_updates[i].plane_info->rotation; - surface->horizontal_mirror = - srf_updates[i].plane_info->horizontal_mirror; - surface->stereo_format = - srf_updates[i].plane_info->stereo_format; - surface->tiling_info = - srf_updates[i].plane_info->tiling_info; - surface->visible = - srf_updates[i].plane_info->visible; - surface->per_pixel_alpha = - srf_updates[i].plane_info->per_pixel_alpha; - surface->dcc = - srf_updates[i].plane_info->dcc; - } - - if (update_type >= UPDATE_TYPE_MED) { - for (j = 0; j < dc->res_pool->pipe_count; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (pipe_ctx->plane_state != surface) - continue; - - resource_build_scaling_params(pipe_ctx); - } - } - - if (srf_updates[i].gamma && - srf_updates[i].gamma != surface->gamma_correction) { - if (surface->gamma_correction != NULL) - dc_gamma_release(&surface->gamma_correction); - - dc_gamma_retain(srf_updates[i].gamma); - surface->gamma_correction = srf_updates[i].gamma; - } - - if (srf_updates[i].in_transfer_func && - srf_updates[i].in_transfer_func != surface->in_transfer_func) { - if (surface->in_transfer_func != NULL) - dc_transfer_func_release( - surface-> - in_transfer_func); - - dc_transfer_func_retain( - srf_updates[i].in_transfer_func); - surface->in_transfer_func = - srf_updates[i].in_transfer_func; - } - - if (srf_updates[i].hdr_static_metadata) - surface->hdr_static_ctx = - *(srf_updates[i].hdr_static_metadata); - } if (update_type == UPDATE_TYPE_FULL) { - if (!dc->res_pool->funcs->validate_bandwidth(dc, context)) { - BREAK_TO_DEBUGGER(); - goto fail; - } else { - dc->hwss.set_bandwidth(dc, context, false); - context_clock_trace(dc, context); - } + dc->hwss.set_bandwidth(dc, context, false); + context_clock_trace(dc, context); } if (update_type > UPDATE_TYPE_FAST) { @@ -1459,27 +1288,60 @@ void dc_update_planes_and_stream(struct dc *dc, break; } } +} + +void dc_commit_updates_for_stream(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_plane_state **plane_states, + struct dc_state *state) +{ + const struct dc_stream_status *stream_status; + enum surface_update_type update_type; + struct dc_state *context; + int i; - if (dc->current_state != context) { + stream_status = dc_stream_get_status(stream); + context = dc->current_state; + + update_type = dc_check_update_surfaces_for_stream( + dc, srf_updates, surface_count, stream_update, stream_status); + + if (update_type >= update_surface_trace_level) + update_surface_trace(dc, srf_updates, surface_count); - /* Since memory free requires elevated IRQL, an interrupt - * request is generated by mem free. If this happens - * between freeing and reassigning the context, our vsync - * interrupt will call into dc and cause a memory - * corruption BSOD. Hence, we first reassign the context, - * then free the old context. - */ - struct dc_state *old = dc->current_state; + if (update_type >= UPDATE_TYPE_FULL) + dc_resource_state_copy_construct(state, context); - dc->current_state = context; - dc_release_state(old); + + for (i = 0; i < surface_count; i++) { + struct dc_plane_state *surface = srf_updates[i].surface; + + /* TODO: On flip we don't build the state, so it still has the + * old address. Which is why we are updating the address here + */ + if (srf_updates[i].flip_addr) + surface->address = srf_updates[i].flip_addr->address; } + + + commit_planes_for_stream( + dc, + srf_updates, + surface_count, + stream, + stream_update, + update_type, + context); + + dc_post_update_surfaces_to_stream(dc); + return; -fail: - dc_release_state(context); } uint8_t dc_get_current_stream_count(struct dc *dc) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 4ff543826476..50440731f83c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -449,23 +449,6 @@ struct dc_flip_addrs { /* TODO: add flip duration for FreeSync */ }; -/* - * Set up surface attributes and associate to a stream - * The surfaces parameter is an absolute set of all surface active for the stream. - * If no surfaces are provided, the stream will be blanked; no memory read. - * Any flip related attribute changes must be done through this interface. - * - * After this call: - * Surfaces attributes are programmed and configured to be composed into stream. - * This does not trigger a flip. No surface address is programmed. - */ - -bool dc_commit_planes_to_stream( - struct dc *dc, - struct dc_plane_state **plane_states, - uint8_t new_plane_count, - struct dc_stream_state *stream); - bool dc_post_update_surfaces_to_stream( struct dc *dc); @@ -571,9 +554,6 @@ bool dc_is_stream_unchanged( struct dc_stream_state *old_stream, struct dc_stream_state *stream); /* - * Setup stream attributes if no stream updates are provided - * there will be no impact on the stream parameters - * * Set up surface attributes and associate to a stream * The surfaces parameter is an absolute set of all surface active for the stream. * If no surfaces are provided, the stream will be blanked; no memory read. @@ -582,14 +562,22 @@ bool dc_is_stream_unchanged( * After this call: * Surfaces attributes are programmed and configured to be composed into stream. * This does not trigger a flip. No surface address is programmed. - * */ -void dc_update_planes_and_stream(struct dc *dc, - struct dc_surface_update *surface_updates, int surface_count, +bool dc_commit_planes_to_stream( + struct dc *dc, + struct dc_plane_state **plane_states, + uint8_t new_plane_count, struct dc_stream_state *dc_stream, - struct dc_stream_update *stream_update); + struct dc_state *state); +void dc_commit_updates_for_stream(struct dc *dc, + struct dc_surface_update *srf_updates, + int surface_count, + struct dc_stream_state *stream, + struct dc_stream_update *stream_update, + struct dc_plane_state **plane_states, + struct dc_state *state); /* * Log the current stream state. */ -- cgit v1.2.3 From e750d56d2c62875c81f52344afab44220300388d Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Wed, 20 Sep 2017 17:06:18 -0400 Subject: drm/amd/display: Fixed validation return wrong result. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6c04ad1b5859..0707bec111a5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4748,7 +4748,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (ret) goto fail; - if (!dc_validate_global_state(dc, dm_state->context)) { + if (dc_validate_global_state(dc, dm_state->context) != DC_OK) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 77b3474a7c9e..d9a2d09a1f4f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1716,7 +1716,7 @@ void dc_resource_state_construct( dst_ctx->dis_clk = dc->res_pool->display_clock; } -bool dc_validate_global_state( +enum dc_status dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2e77885fc1ea..1e49b8f9c66e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -654,7 +654,7 @@ bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); -bool dc_validate_global_state( +enum dc_status dc_validate_global_state( struct dc *dc, struct dc_state *new_ctx); -- cgit v1.2.3 From 13ab1b44151195823fa0e2ceace1cf4687266dba Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Thu, 28 Sep 2017 17:18:27 -0400 Subject: drm/amd/display: Fixed extend to second screen mode hang 1. Fixed acquire free split pipe bug. 2. Change return value for dc_add_stream_to_ctx from bool to enum. 4. Remove redundant apply_ctx_for_surface calling 5. Unlock pipe after back end programming. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 48 ++++++++++++----------- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++--- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 4 files changed, 32 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0707bec111a5..8653453566b8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4495,10 +4495,10 @@ static int dm_update_crtcs_state(struct dc *dc, DRM_DEBUG_DRIVER("Enabling DRM crtc: %d\n", crtc->base.id); - if (!dc_add_stream_to_ctx( + if (dc_add_stream_to_ctx( dc, dm_state->context, - dm_new_crtc_state->stream)) { + dm_new_crtc_state->stream) != DC_OK) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f9bac11d3950..33a63c7d7a8e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -766,34 +766,27 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) for (i = 0; i < context->stream_count; i++) { const struct dc_sink *sink = context->streams[i]->sink; - for (j = 0; j < context->stream_status[i].plane_count; j++) { - dc->hwss.apply_ctx_for_surface( - dc, context->streams[i], - context->stream_status[i].plane_count, - context); + dc->hwss.apply_ctx_for_surface( + dc, context->streams[i], + context->stream_status[i].plane_count, + context); - /* - * enable stereo - * TODO rework dc_enable_stereo call to work with validation sets? - */ - for (k = 0; k < MAX_PIPES; k++) { - pipe = &context->res_ctx.pipe_ctx[k]; - - for (l = 0 ; pipe && l < context->stream_count; l++) { - if (context->streams[l] && - context->streams[l] == pipe->stream && - dc->hwss.setup_stereo) - dc->hwss.setup_stereo(pipe, dc); - } + /* + * enable stereo + * TODO rework dc_enable_stereo call to work with validation sets? + */ + for (k = 0; k < MAX_PIPES; k++) { + pipe = &context->res_ctx.pipe_ctx[k]; + + for (l = 0 ; pipe && l < context->stream_count; l++) { + if (context->streams[l] && + context->streams[l] == pipe->stream && + dc->hwss.setup_stereo) + dc->hwss.setup_stereo(pipe, dc); } } - for (j = 0; j < MAX_PIPES; j++) { - pipe = &context->res_ctx.pipe_ctx[j]; - if (!pipe->top_pipe && pipe->stream == context->streams[i]) - dc->hwss.pipe_control_lock(dc, pipe, false); - } CONN_MSG_MODE(sink->link, "{%dx%d, %dx%d@%dKhz}", context->streams[i]->timing.h_addressable, @@ -815,6 +808,15 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) dc_enable_stereo(dc, context, dc_streams, context->stream_count); + for (i = 0; i < context->stream_count; i++) { + for (j = 0; j < MAX_PIPES; j++) { + pipe = &context->res_ctx.pipe_ctx[j]; + + if (!pipe->top_pipe && pipe->stream == context->streams[i]) + dc->hwss.pipe_control_lock(dc, pipe, false); + } + } + dc_release_state(dc->current_state); dc->current_state = context; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c31dccdc3d2e..c60f53069708 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1446,7 +1446,7 @@ bool resource_is_stream_unchanged( return false; } -bool dc_add_stream_to_ctx( +enum dc_status dc_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream) @@ -1467,7 +1467,7 @@ bool dc_add_stream_to_ctx( if (res != DC_OK) DC_ERROR("Adding stream %p to context failed with err %d!\n", stream, res); - return res == DC_OK; + return res; } bool dc_remove_stream_from_ctx( @@ -1640,10 +1640,9 @@ enum dc_status resource_map_pool_resources( /* acquire new resources */ pipe_idx = acquire_first_free_pipe(&context->res_ctx, pool, stream); -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) if (pipe_idx < 0) - acquire_first_split_pipe(&context->res_ctx, pool, stream); -#endif + pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream); + if (pipe_idx < 0) return DC_NO_CONTROLLER_RESOURCE; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 172050ad845d..eeb8ee5acdc1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -631,7 +631,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream, uint32_t *h_position, uint32_t *v_position); -bool dc_add_stream_to_ctx( +enum dc_status dc_add_stream_to_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream); -- cgit v1.2.3 From 886daac91d4c794fa76a0e5cf1101bdb329f3fe3 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Thu, 5 Oct 2017 15:37:46 -0400 Subject: drm/amd/display: Fix a logic defect in cursor move Regression caused by: Ib98354194d7 Need to check crtc->stream before updating cursor attributes and position. Signed-off-by: Jerry Zuo Reviewed-by: Roman Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8653453566b8..17fb636648f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3736,14 +3736,15 @@ static void handle_cursor_update(struct drm_plane *plane, attributes.pitch = attributes.width; - if (!dc_stream_set_cursor_attributes(crtc_state->stream, - &attributes)) - DRM_ERROR("DC failed to set cursor attributes\n"); + if (crtc_state->stream) { + if (!dc_stream_set_cursor_attributes(crtc_state->stream, + &attributes)) + DRM_ERROR("DC failed to set cursor attributes\n"); - if (crtc_state->stream) if (!dc_stream_set_cursor_position(crtc_state->stream, &position)) DRM_ERROR("DC failed to set cursor position\n"); + } } static void prepare_flip_isr(struct amdgpu_crtc *acrtc) -- cgit v1.2.3 From 9bbc30310f240c9400e31c7ab7b7edd2b76b3589 Mon Sep 17 00:00:00 2001 From: Jerry Zuo Date: Fri, 6 Oct 2017 15:08:07 -0400 Subject: drm/amd/display: Remove a false-positive error message To avoid confusion, need to suppress the error message when get -ERESTARTSYS error code. It is normal when getting interrupted by signals in the process of a wait for the buffer to become unreserved. Only propagate to user-mode for further action, no need to pop up error message. Signed-off-by: Jerry Zuo Reviewed-by: Sun peng Li Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 17fb636648f4..09163d8d9332 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1790,7 +1790,9 @@ static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, int r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { - DRM_ERROR("Unable to reserve buffer\n"); + // Don't show error msg. when return -ERESTARTSYS + if (r != -ERESTARTSYS) + DRM_ERROR("Unable to reserve buffer: %d\n", r); return r; } -- cgit v1.2.3 From 9a5d9c48d883db4f7f3e5409062bef7d25165a95 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Fri, 6 Oct 2017 11:57:40 -0400 Subject: drm/amd/display: Report stream as different on scaling change When scaling is enabled, our preference is to scale up to the prefered (native) mode. This means that hardware timings will be the same across a modeset. Therefore, also report mode as changed if source or destination rectangle is different. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 2 ++ 3 files changed, 27 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 09163d8d9332..fad40da8422e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4428,12 +4428,13 @@ static int dm_update_crtcs_state(struct dc *dc, } } - if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream)) { + if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && + dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { new_crtc_state->mode_changed = false; DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", - new_crtc_state->mode_changed); + new_crtc_state->mode_changed); } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 454a521a268d..2a5c91772473 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1335,6 +1335,28 @@ bool dc_is_stream_unchanged( return true; } +bool dc_is_stream_scaling_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream) +{ + if (old_stream == stream) + return true; + + if (old_stream == NULL || stream == NULL) + return false; + + if (memcmp(&old_stream->src, + &stream->src, + sizeof(struct rect)) != 0) + return false; + + if (memcmp(&old_stream->dst, + &stream->dst, + sizeof(struct rect)) != 0) + return false; + + return true; +} + /* Maximum TMDS single link pixel clock 165MHz */ #define TMDS_MAX_PIXEL_CLOCK_IN_KHZ 165000 diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index ace17d13683a..f60191d9c7e5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -627,6 +627,8 @@ struct dc_stream_update { bool dc_is_stream_unchanged( struct dc_stream_state *old_stream, struct dc_stream_state *stream); +bool dc_is_stream_scaling_unchanged( + struct dc_stream_state *old_stream, struct dc_stream_state *stream); /* * Set up surface attributes and associate to a stream -- cgit v1.2.3 From 5771ec8fe8cb99c0db3115e81b4f69b1543c6982 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Fri, 6 Oct 2017 15:11:41 -0400 Subject: drm/amd/display: ASSERT on dc_create_state failing. dc_create_state() returns NULL on allocation failure. Raise warning when that happens. Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fad40da8422e..e439363ed54b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -702,6 +702,7 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) dc_release_state(cached_state->context); cached_state->context = dc_create_state(); + ASSERT(cached_state->context); dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context); for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { -- cgit v1.2.3 From c12a7ba543d16c1770fb44670e5eb42ae524c502 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 20:04:48 -0400 Subject: drm/amd/display: Fix up some whitespace in handle_cursor_update Use combo of tabs and spaces Signed-off-by: Harry Wentland Acked-by: Alex Deucher Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e439363ed54b..60587d6f81d7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3709,10 +3709,10 @@ static void handle_cursor_update(struct drm_plane *plane, return; DRM_DEBUG_DRIVER("%s: crtc_id=%d with size %d to %d\n", - __func__, - amdgpu_crtc->crtc_id, - plane->state->crtc_w, - plane->state->crtc_h); + __func__, + amdgpu_crtc->crtc_id, + plane->state->crtc_w, + plane->state->crtc_h); ret = get_cursor_position(plane, crtc, &position); if (ret) -- cgit v1.2.3 From 62c933f9c6bf287b5b911a1eb838bc942eaa7202 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 10 Oct 2017 14:01:33 -0400 Subject: drm/amd/display: WA for 3 display play video hot plug. Three monitor connected and playing a video will occupy all 4 pipes, if hot plug forth display, commit streams will be failed due to no free pipe can be found. Work around: When forth monitor connected, mark video plane as a fake plane, remove it in dc, keep it in dm and report address to OS, until OS turn off MPO. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++----- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 14 ++++++++------ drivers/gpu/drm/amd/display/dc/dc.h | 6 +++--- drivers/gpu/drm/amd/display/dc/inc/core_status.h | 15 ++++++++------- 5 files changed, 26 insertions(+), 23 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 60587d6f81d7..0d1b41298990 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2794,7 +2794,7 @@ int amdgpu_dm_connector_mode_valid(struct drm_connector *connector, stream->src.height = mode->vdisplay; stream->dst = stream->src; - if (dc_validate_stream(adev->dm.dc, stream)) + if (dc_validate_stream(adev->dm.dc, stream) == DC_OK) result = MODE_OK; dc_stream_release(stream); @@ -2839,7 +2839,7 @@ static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc, if (!dm_crtc_state->stream) return 0; - if (dc_validate_stream(dc, dm_crtc_state->stream)) + if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK) return 0; return ret; @@ -3034,7 +3034,7 @@ static int dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - if (dc_validate_plane(dc, dm_plane_state->dc_state)) + if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK) return 0; return -EINVAL; @@ -4464,10 +4464,10 @@ static int dm_update_crtcs_state(struct dc *dc, crtc->base.id); /* i.e. reset mode */ - if (!dc_remove_stream_from_ctx( + if (dc_remove_stream_from_ctx( dc, dm_state->context, - dm_old_crtc_state->stream)) { + dm_old_crtc_state->stream) != DC_OK) { ret = -EINVAL; goto fail; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 9d750fa29a87..ff6bd384aece 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -793,7 +793,7 @@ bool dc_enable_stereo( * Applies given context to HW and copy it into current context. * It's up to the user to release the src context afterwards. */ -static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) +static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *context) { struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status result = DC_ERROR_UNEXPECTED; @@ -869,7 +869,7 @@ static bool dc_commit_state_no_check(struct dc *dc, struct dc_state *context) dc->hwss.optimize_shared_resources(dc); - return (result == DC_OK); + return result; } bool dc_commit_state(struct dc *dc, struct dc_state *context) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 0aca7a3d3dd6..d1cdf9f8853d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1503,7 +1503,7 @@ enum dc_status dc_add_stream_to_ctx( return res; } -bool dc_remove_stream_from_ctx( +enum dc_status dc_remove_stream_from_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream) @@ -2756,7 +2756,7 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream, fmt_bit_depth->pixel_encoding = pixel_encoding; } -bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) +enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) { struct dc *core_dc = dc; struct dc_link *link = stream->sink->link; @@ -2780,14 +2780,16 @@ bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream) link, &stream->timing); - return res == DC_OK; + return res; } -bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) +enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state) { + enum dc_status res = DC_OK; + /* TODO For now validates pixel format only */ if (dc->res_pool->funcs->validate_plane) - return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps) == DC_OK; + return dc->res_pool->funcs->validate_plane(plane_state, &dc->caps); - return true; + return res; } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f60191d9c7e5..6c0de093a59e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -686,7 +686,7 @@ enum dc_status dc_add_stream_to_ctx( struct dc_state *new_ctx, struct dc_stream_state *stream); -bool dc_remove_stream_from_ctx( +enum dc_status dc_remove_stream_from_ctx( struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream); @@ -725,9 +725,9 @@ struct dc_validation_set { uint8_t plane_count; }; -bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); +enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream); -bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); +enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); enum dc_status dc_validate_global_state( struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_status.h b/drivers/gpu/drm/amd/display/dc/inc/core_status.h index b5759c0e5a2f..01df85641684 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_status.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_status.h @@ -35,13 +35,14 @@ enum dc_status { DC_FAIL_CONTROLLER_VALIDATE = 5, DC_FAIL_ENC_VALIDATE = 6, DC_FAIL_ATTACH_SURFACES = 7, - DC_FAIL_SURFACE_VALIDATE = 8, - DC_NO_DP_LINK_BANDWIDTH = 9, - DC_EXCEED_DONGLE_MAX_CLK = 10, - DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 11, - DC_FAIL_BANDWIDTH_VALIDATE = 12, /* BW and Watermark validation */ - DC_FAIL_SCALING = 13, - DC_FAIL_DP_LINK_TRAINING = 14, + DC_FAIL_DETACH_SURFACES = 8, + DC_FAIL_SURFACE_VALIDATE = 9, + DC_NO_DP_LINK_BANDWIDTH = 10, + DC_EXCEED_DONGLE_MAX_CLK = 11, + DC_SURFACE_PIXEL_FORMAT_UNSUPPORTED = 12, + DC_FAIL_BANDWIDTH_VALIDATE = 13, /* BW and Watermark validation */ + DC_FAIL_SCALING = 14, + DC_FAIL_DP_LINK_TRAINING = 15, DC_ERROR_UNEXPECTED = -1 }; -- cgit v1.2.3 From 1bed4d09a4cc5a7d4449da86832d9bd816ae44ff Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 12 Sep 2017 17:10:25 +0100 Subject: drm/amd/display: Fix one more place for dc_stream_state leak One more thing that happened due to uneven applying of patches. This mirrors what Darren Salt fixed. Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0d1b41298990..58143fe49e4a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4484,7 +4484,7 @@ static int dm_update_crtcs_state(struct dc *dc, * TODO: need to dig out the root cause of that */ if (!aconnector || (!aconnector->dc_sink && aconnector->mst_port)) - continue; + goto next_crtc; if (modereset_required(new_crtc_state)) goto next_crtc; -- cgit v1.2.3 From 33be2785477e470087ea1c5b203881d644cdb0f3 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 08:47:25 -0400 Subject: drm/amd/display: Simplify dm_late_init() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 58143fe49e4a..d8fcf24a041e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -538,9 +538,8 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) static int dm_late_init(void *handle) { struct drm_device *dev = ((struct amdgpu_device *)handle)->ddev; - int r = detect_mst_link_for_all_connectors(dev); - return r; + return detect_mst_link_for_all_connectors(dev); } static void s3_handle_mst(struct drm_device *dev, bool suspend) -- cgit v1.2.3 From 32f5062d1c7dc2a4d974bb10cf67a98043d9c901 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 08:48:44 -0400 Subject: drm/amd/display: Fix indentation in dm_suspend() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d8fcf24a041e..893213b9c11e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -598,10 +598,7 @@ static int dm_suspend(void *handle) WARN_ON(adev->dm.cached_state); adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev); - dc_set_power_state( - dm->dc, - DC_ACPI_CM_POWER_STATE_D3 - ); + dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3); return ret; } -- cgit v1.2.3 From 1fb0c9ccb311cdf16f6ec617fb30c249888c5f97 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 08:49:13 -0400 Subject: drm/amd/display: Fix indentation in dm_resume() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 893213b9c11e..a7bbd22e8f12 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -628,10 +628,7 @@ static int dm_resume(void *handle) struct amdgpu_display_manager *dm = &adev->dm; /* power on hardware */ - dc_set_power_state( - dm->dc, - DC_ACPI_CM_POWER_STATE_D0 - ); + dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0); return 0; } -- cgit v1.2.3 From 900b3cb1833883de9be62e48ff748663c7b6ef96 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 08:59:18 -0400 Subject: drm/amd/display: Fix brace style in amdgpu_dm_update_connector_after_detect() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a7bbd22e8f12..7999eadddd75 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -890,9 +890,9 @@ amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector) connector); aconnector->dc_sink = sink; - if (sink->dc_edid.length == 0) + if (sink->dc_edid.length == 0) { aconnector->edid = NULL; - else { + } else { aconnector->edid = (struct edid *) sink->dc_edid.raw_edid; -- cgit v1.2.3 From d4a6e8a90ffa281918d9ba75a08f1f917c7eb183 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 09:00:33 -0400 Subject: drm/amd/display: Fix brace style in dm_handle_hpd_rx_irq() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7999eadddd75..2b57bfc8ec40 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1010,8 +1010,9 @@ static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector) dpcd_bytes_to_read); new_irq_handled = false; - } else + } else { break; + } } if (process_count == max_process_count) -- cgit v1.2.3 From 53cbf65c145450e35fbca50a33c56f5a066e3fe8 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 09:04:25 -0400 Subject: drm/amd/display: Simplify handle_hpd_rx_irq() There is a local reference to the dc_link that wasn't being used so we shorten references throughout the function. Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2b57bfc8ec40..bb83da6fd31b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1024,20 +1024,20 @@ static void handle_hpd_rx_irq(void *param) struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param; struct drm_connector *connector = &aconnector->base; struct drm_device *dev = connector->dev; - const struct dc_link *dc_link = aconnector->dc_link; + struct dc_link *dc_link = aconnector->dc_link; bool is_mst_root_connector = aconnector->mst_mgr.mst_state; /* TODO:Temporary add mutex to protect hpd interrupt not have a gpio * conflict, after implement i2c helper, this mutex should be * retired. */ - if (aconnector->dc_link->type != dc_connection_mst_branch) + if (dc_link->type != dc_connection_mst_branch) mutex_lock(&aconnector->hpd_lock); - if (dc_link_handle_hpd_rx_irq(aconnector->dc_link, NULL) && + if (dc_link_handle_hpd_rx_irq(dc_link, NULL) && !is_mst_root_connector) { /* Downstream Port status changed. */ - if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPDRX)) { + if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) { amdgpu_dm_update_connector_after_detect(aconnector); @@ -1049,10 +1049,10 @@ static void handle_hpd_rx_irq(void *param) } } if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || - (dc_link->type == dc_connection_mst_branch)) + (dc_link->type == dc_connection_mst_branch)) dm_handle_hpd_rx_irq(aconnector); - if (aconnector->dc_link->type != dc_connection_mst_branch) + if (dc_link->type != dc_connection_mst_branch) mutex_unlock(&aconnector->hpd_lock); } -- cgit v1.2.3 From 8440c30463f3c6d312a5a65be634e6c6c1b6a5b3 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 09:09:42 -0400 Subject: drm/amd/display: Fix brace style in amdgpu_dm_initialize_drm_device() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb83da6fd31b..fb24ba69b2a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1412,9 +1412,8 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail_free_planes; aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); - if (!aencoder) { + if (!aencoder) goto fail_free_connector; - } if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { DRM_ERROR("KMS: Failed to initialize encoder\n"); -- cgit v1.2.3 From d2b2562c23e5e2a122a73627b0c658c5cfedb01a Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 09:46:54 -0400 Subject: drm/amd/display: Replace block with strncpy() in fill_audio_info() Replace inlined strncpy with library call. Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fb24ba69b2a6..3f405976f882 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2238,11 +2238,9 @@ static void fill_audio_info(struct audio_info *audio_info, cea_revision = drm_connector->display_info.cea_rev; - while (i < AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS && - edid_caps->display_name[i]) { - audio_info->display_name[i] = edid_caps->display_name[i]; - i++; - } + strncpy(audio_info->display_name, + edid_caps->display_name, + AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; -- cgit v1.2.3 From a68d90e7aed55e274cb117bbca34913d5fb8afd2 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 10:15:12 -0400 Subject: drm/amd/display: Fix indentation in create_eml_sink() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3f405976f882..ce975aef27a7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2720,8 +2720,7 @@ static void create_eml_sink(struct amdgpu_dm_connector *aconnector) (edid->extensions + 1) * EDID_LENGTH, &init_params); - if (aconnector->base.force - == DRM_FORCE_ON) + if (aconnector->base.force == DRM_FORCE_ON) aconnector->dc_sink = aconnector->dc_link->local_sink ? aconnector->dc_link->local_sink : aconnector->dc_em_sink; -- cgit v1.2.3 From f922237daa7f2de4a8eae0ecdc99e944333fffc2 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 10:16:39 -0400 Subject: drm/amd/display: Tidy up dm_drm_plane_reset() Move WARN_ON higher up and in doing so fix brace style. Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ce975aef27a7..46fac2bccc57 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2873,13 +2873,13 @@ static void dm_drm_plane_reset(struct drm_plane *plane) plane->funcs->atomic_destroy_state(plane, plane->state); amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); - + WARN_ON(amdgpu_state == NULL); + if (amdgpu_state) { plane->state = &amdgpu_state->base; plane->state->plane = plane; plane->state->rotation = DRM_MODE_ROTATE_0; - } else - WARN_ON(1); + } } static struct drm_plane_state * -- cgit v1.2.3 From a8d8d3dc9ad8dc4ba6155bdd88f01e23bfc7dfbc Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 10:38:27 -0400 Subject: drm/amd/display: Fix brace style in amdgpu_dm_connector_ddc_get_modes() Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 46fac2bccc57..d7fc237851c5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3310,8 +3310,9 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, drm_edid_to_eld(connector, edid); amdgpu_dm_get_native_mode(connector); - } else + } else { amdgpu_dm_connector->num_modes = 0; + } } static int amdgpu_dm_connector_get_modes(struct drm_connector *connector) -- cgit v1.2.3 From 9a227d263d44572583be5dd9e9f215cceb4297a1 Mon Sep 17 00:00:00 2001 From: Tom St Denis Date: Tue, 17 Oct 2017 10:40:08 -0400 Subject: drm/amd/display: Remove needless cast in amdgpu_dm_connector_init() The cast of dc_link is redundant. Signed-off-by: Tom St Denis Acked-by: Andrey Grodzovsky Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d7fc237851c5..6ef71e192845 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3460,7 +3460,8 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, struct dc *dc = dm->dc; struct dc_link *link = dc_get_link_at_index(dc, link_index); struct amdgpu_i2c_adapter *i2c; - ((struct dc_link *)link)->priv = aconnector; + + link->priv = aconnector; DRM_DEBUG_DRIVER("%s()\n", __func__); -- cgit v1.2.3 From fc9e9920b1d3a7a6af7eb993d531c36beb985570 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Wed, 27 Sep 2017 15:15:38 +0530 Subject: drm/amd/display: add hardware_planes_only to list of affected planes For SoC's having software designed cursor plane, should be treated differently than hardware cursor planes. The DRM core initializes cursor plane by default with legacy_cursor_update set. Hence legacy_cursor_update can be use effectively to handle software cursor planes' update and atomicity functionalities. This patch uses this variable to decide in the atomic_check to whether add a requested plane to the list of affected planes or not, hence fixing the issue of co-existence of MPO, i.e, setting of available hardware planes like underlay and updation of cursor planes as well. Without this patch when underlay is set from user space, only blank screen with backlight is visible. Signed-off-by: Shirish S Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 30 ++++++++++++++++++----- 1 file changed, 24 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6ef71e192845..51258d045167 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3982,6 +3982,8 @@ static int amdgpu_dm_atomic_commit(struct drm_device *dev, if (drm_atomic_crtc_needs_modeset(new_crtc_state) && dm_old_crtc_state->stream) manage_dm_interrupts(adev, acrtc, false); } + /* Add check here for SoC's that support hardware cursor plane, to + * unset legacy_cursor_update */ return drm_atomic_helper_commit(dev, state, nonblock); @@ -4647,7 +4649,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector *connector; struct drm_connector_state *old_con_state, *new_con_state; struct drm_crtc *crtc; - struct drm_crtc_state *new_crtc_state; + struct drm_crtc_state *old_crtc_state, *new_crtc_state; /* * This bool will be set for true for any modeset/reset @@ -4656,18 +4658,34 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; ret = drm_atomic_helper_check_modeset(dev, state); - if (ret) { DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); return ret; } /* - * Hack: Commit needs planes right now, specifically for gamma - * TODO rework commit to check CRTC for gamma change + * legacy_cursor_update should be made false for SoC's having + * a dedicated hardware plane for cursor in amdgpu_dm_atomic_commit(), + * otherwise for software cursor plane, + * we should not add it to list of affected planes. */ - for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { - if (new_crtc_state->color_mgmt_changed) { + if (state->legacy_cursor_update) { + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { + if (new_crtc_state->color_mgmt_changed) { + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + goto fail; + } + } + } else { + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (!new_crtc_state->enable) + continue; + + ret = drm_atomic_add_affected_connectors(state, crtc); + if (ret) + return ret; + ret = drm_atomic_add_affected_planes(state, crtc); if (ret) goto fail; -- cgit v1.2.3 From af09e48aa52377eb807709e2a1cdc33e9fd1ac94 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Fri, 20 Oct 2017 13:59:53 -0400 Subject: drm/amd/display: Fix memoryleak during S3 resume. Do not create dc_state within display_resume, since it's being constructed within atomic check. Reviewed-by: Harry Wentland Signed-off-by: Leo (Sunpeng) Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 51258d045167..d0ee1b3b8b5c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -694,10 +694,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) WARN_ON(kref_read(&cached_state->context->refcount) > 1); dc_release_state(cached_state->context); - cached_state->context = dc_create_state(); - ASSERT(cached_state->context); - dc_resource_state_copy_construct_current(adev->dm.dc, cached_state->context); - for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { dm_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_crtc_state->stream) { -- cgit v1.2.3 From 9a68db7220d05fb28de139a7db93bd6866cc86fa Mon Sep 17 00:00:00 2001 From: Rex Zhu Date: Thu, 26 Oct 2017 00:03:27 -0400 Subject: Revert "drm/amd/display: Match actual state during S3 resume." This reverts commit 4f346e655d24140fb40b46f814506ba17ac34ea1. fix s3 hang issue. Acked-by: Alex Deucher Signed-off-by: Rex Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 33 ----------------------- 1 file changed, 33 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d0ee1b3b8b5c..bb134a6320bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -641,11 +641,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) struct drm_connector *connector; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; - struct dm_crtc_state *dm_crtc_state; - struct drm_plane *plane; - struct drm_plane_state *plane_state; - struct dm_plane_state *dm_plane_state; - struct dm_atomic_state *cached_state; int ret = 0; int i; @@ -684,34 +679,6 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) new_crtc_state->active_changed = true; - cached_state = to_dm_atomic_state(adev->dm.cached_state); - - /* - * During suspend, the cached state is saved before all streams are - * disabled. Refresh cached state to match actual current state before - * restoring it. - */ - WARN_ON(kref_read(&cached_state->context->refcount) > 1); - dc_release_state(cached_state->context); - - for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { - dm_crtc_state = to_dm_crtc_state(new_crtc_state); - if (dm_crtc_state->stream) { - WARN_ON(kref_read(&dm_crtc_state->stream->refcount) > 1); - dc_stream_release(dm_crtc_state->stream); - dm_crtc_state->stream = NULL; - } - } - - for_each_new_plane_in_state(adev->dm.cached_state, plane, plane_state, i) { - dm_plane_state = to_dm_plane_state(plane_state); - if (dm_plane_state->dc_state) { - WARN_ON(kref_read(&dm_plane_state->dc_state->refcount) > 1); - dc_plane_state_release(dm_plane_state->dc_state); - dm_plane_state->dc_state = NULL; - } - } - ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); drm_atomic_state_put(adev->dm.cached_state); -- cgit v1.2.3 From 4d3e00dad80a2c317d542358620facd8ca698428 Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 19 Oct 2017 22:34:15 +0530 Subject: drm/amd/display : add high part address calculation for underlay Currently the high part of the address structure is not populated in case of luma and chroma. This patch adds this calculation. Signed-off-by: Shirish S Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index bb134a6320bf..635a8a3df369 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1771,6 +1771,7 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, { uint64_t tiling_flags; uint64_t fb_location = 0; + uint64_t chroma_addr = 0; unsigned int awidth; const struct drm_framebuffer *fb = &amdgpu_fb->base; int ret = 0; @@ -1833,9 +1834,13 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(fb_location); + plane_state->address.video_progressive.luma_addr.high_part + = upper_32_bits(fb_location); + chroma_addr = fb_location + (u64)(awidth * fb->height); plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(fb_location) + - (awidth * fb->height); + = lower_32_bits(chroma_addr); + plane_state->address.video_progressive.chroma_addr.high_part + = upper_32_bits(chroma_addr); plane_state->plane_size.video.luma_size.x = 0; plane_state->plane_size.video.luma_size.y = 0; plane_state->plane_size.video.luma_size.width = awidth; -- cgit v1.2.3 From 56087b31f4b2861c773185ec45d313b55dbbb69d Mon Sep 17 00:00:00 2001 From: Shirish S Date: Thu, 26 Oct 2017 16:15:01 +0530 Subject: drm/amd/display: fix high part address in dm_plane_helper_prepare_fb() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The high part calculation of luma and chroma address' was missing in dm_plane_helper_prepare_fb(). This fix brings uniformity in the address' at atomic_check and atomic_commit for both RGB & YUV planes. Signed-off-by: Shirish S Reviewed-by: Michel Dänzer Reviewed-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 635a8a3df369..c2fefd3e657e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2896,6 +2896,7 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, struct amdgpu_framebuffer *afb; struct drm_gem_object *obj; struct amdgpu_bo *rbo; + uint64_t chroma_addr = 0; int r; struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; unsigned int awidth; @@ -2937,11 +2938,16 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, plane_state->address.grph.addr.high_part = upper_32_bits(afb->address); } else { awidth = ALIGN(new_state->fb->width, 64); + plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address); + plane_state->address.video_progressive.luma_addr.high_part + = upper_32_bits(afb->address); + chroma_addr = afb->address + (u64)(awidth * new_state->fb->height); plane_state->address.video_progressive.chroma_addr.low_part - = lower_32_bits(afb->address) + - (awidth * new_state->fb->height); + = lower_32_bits(chroma_addr); + plane_state->address.video_progressive.chroma_addr.high_part + = upper_32_bits(chroma_addr); } } -- cgit v1.2.3 From 7bef1af3b9c2a5690a41298b5986dbde82fbedbc Mon Sep 17 00:00:00 2001 From: Shirish S Date: Fri, 27 Oct 2017 03:25:55 +0000 Subject: drm/amd/display: check if modeset is required before adding plane Adding affected planes without checking if modeset is requested from the user space causes performance regression in video p/b scenarios when full screen p/b is not composited. Hence add a check before adding a plane as affected. bug: https://bugs.freedesktop.org/show_bug.cgi?id=103408 Acked-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Shirish S Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c2fefd3e657e..fd3e995fc426 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4653,6 +4653,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } else { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + if (!new_crtc_state->enable) continue; -- cgit v1.2.3 From 30b7c6147d18d77c6120a8f689d04d2518d3f5e4 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Thu, 26 Oct 2017 15:35:14 -0400 Subject: drm/amd/display: Don't print error when bo_pin is interrupted MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: Also don't print for ERESTARTSYS or EAGAIN v3: Best practice is to only ignore ERESTARTSYS Signed-off-by: Harry Wentland Reviewed-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fd3e995fc426..b94987bb6af9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2923,7 +2923,8 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, amdgpu_bo_unreserve(rbo); if (unlikely(r != 0)) { - DRM_ERROR("Failed to pin framebuffer\n"); + if (r != -ERESTARTSYS) + DRM_ERROR("Failed to pin framebuffer with error %d\n", r); return r; } -- cgit v1.2.3 From f5ba60fefa00ca789c4eb35df38b171d532b3155 Mon Sep 17 00:00:00 2001 From: Drew Davenport Date: Fri, 27 Oct 2017 12:34:46 -0600 Subject: amdgpu/dc: Avoid dereferencing NULL pointer crtc is dereferenced from within drm_atomic_get_new_crtc_state, so check for NULL before initializing new_crtc_state. Signed-off-by: Drew Davenport Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b94987bb6af9..84591781fca1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3853,8 +3853,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, /* update planes when needed */ for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) { struct drm_crtc *crtc = new_plane_state->crtc; - struct drm_crtc_state *new_crtc_state = - drm_atomic_get_new_crtc_state(state, crtc); + struct drm_crtc_state *new_crtc_state; struct drm_framebuffer *fb = new_plane_state->fb; bool pflip_needed; struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state); @@ -3864,7 +3863,11 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, continue; } - if (!fb || !crtc || pcrtc != crtc || !new_crtc_state->active) + if (!fb || !crtc || pcrtc != crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc); + if (!new_crtc_state->active) continue; pflip_needed = !state->allow_modeset; -- cgit v1.2.3 From efa6a8b7ca0f1c6073a2ac7f5a02f8ea333daf92 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:42:41 -0400 Subject: drm/amd/display: Use plane pointer to avoid line breaks Signed-off-by: Harry Wentland Reviewed-by: Mikita Lipski Reviewed-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 84591781fca1..2df9f951b7e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1328,13 +1328,16 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) } for (i = 0; i < dm->dc->caps.max_planes; i++) { - mode_info->planes[i] = kzalloc(sizeof(struct amdgpu_plane), - GFP_KERNEL); - if (!mode_info->planes[i]) { + struct amdgpu_plane *plane; + + plane = kzalloc(sizeof(struct amdgpu_plane), GFP_KERNEL); + mode_info->planes[i] = plane; + + if (!plane) { DRM_ERROR("KMS: Failed to allocate plane\n"); goto fail_free_planes; } - mode_info->planes[i]->base.type = mode_info->plane_type[i]; + plane->base.type = mode_info->plane_type[i]; /* * HACK: IGT tests expect that each plane can only have one -- cgit v1.2.3 From cd8a2ae8dc08a92d4804a7adda645f1f8d1f7586 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:28:59 -0400 Subject: drm/amd/display: Use single fail label in init_drm_dev No need for multiple labels as kfree will always do a NULL check before freeing the memory. Signed-off-by: Harry Wentland Reviewed-by: Bhawanpreet Lakha Reviewed-by: Tony Cheng Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 +++++++++++------------ 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2df9f951b7e7..6eb7b32fb763 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1335,7 +1335,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (!plane) { DRM_ERROR("KMS: Failed to allocate plane\n"); - goto fail_free_planes; + goto fail; } plane->base.type = mode_info->plane_type[i]; @@ -1351,14 +1351,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (amdgpu_dm_plane_init(dm, mode_info->planes[i], possible_crtcs)) { DRM_ERROR("KMS: Failed to initialize plane\n"); - goto fail_free_planes; + goto fail; } } for (i = 0; i < dm->dc->caps.max_streams; i++) if (amdgpu_dm_crtc_init(dm, &mode_info->planes[i]->base, i)) { DRM_ERROR("KMS: Failed to initialize crtc\n"); - goto fail_free_planes; + goto fail; } dm->display_indexes_num = dm->dc->caps.max_streams; @@ -1375,20 +1375,20 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL); if (!aconnector) - goto fail_free_planes; + goto fail; aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL); if (!aencoder) - goto fail_free_connector; + goto fail; if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) { DRM_ERROR("KMS: Failed to initialize encoder\n"); - goto fail_free_encoder; + goto fail; } if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) { DRM_ERROR("KMS: Failed to initialize connector\n"); - goto fail_free_encoder; + goto fail; } if (dc_link_detect(dc_get_link_at_index(dm->dc, i), @@ -1413,14 +1413,14 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) case CHIP_VEGA10: if (dce110_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - goto fail_free_encoder; + goto fail; } break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); - goto fail_free_encoder; + goto fail; } /* * Temporary disable until pplib/smu interaction is implemented @@ -1430,17 +1430,15 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) #endif default: DRM_ERROR("Usupported ASIC type: 0x%X\n", adev->asic_type); - goto fail_free_encoder; + goto fail; } drm_mode_config_reset(dm->ddev); return 0; -fail_free_encoder: +fail: kfree(aencoder); -fail_free_connector: kfree(aconnector); -fail_free_planes: for (i = 0; i < dm->dc->caps.max_planes; i++) kfree(mode_info->planes[i]); return -1; -- cgit v1.2.3 From 96719c5439b4d75bfd6b3c5cb24f1a8e537125bb Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 20 Oct 2017 08:43:40 -0400 Subject: drm/amd/display: Explicitly call ->reset for each object We need to avoid calling reset after detection because the next commit adds freesync properties on the atomic_state which are set during detection. Calling reset after this clears them. The easiest way to accomplish this right now is to call ->reset on the connector right after creation but before detection. To stay consistent call ->reset on every other object as well after creation. v2: Provide better reason for this change in commit msg. Signed-off-by: Harry Wentland Reviewed-by: Roman Li Acked-by: Harry Wentland Reviewed-by: Andrey Grodzovsky Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6eb7b32fb763..33a15a1d818c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1433,8 +1433,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) goto fail; } - drm_mode_config_reset(dm->ddev); - return 0; fail: kfree(aencoder); @@ -3081,6 +3079,11 @@ static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(&aplane->base, &dm_plane_helper_funcs); + /* Create (reset) the plane state */ + if (aplane->base.funcs->reset) + aplane->base.funcs->reset(&aplane->base); + + return res; } @@ -3116,6 +3119,10 @@ static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_crtc_helper_add(&acrtc->base, &amdgpu_dm_crtc_helper_funcs); + /* Create (reset) the plane state */ + if (acrtc->base.funcs->reset) + acrtc->base.funcs->reset(&acrtc->base); + acrtc->max_cursor_width = dm->adev->dm.dc->caps.max_cursor_size; acrtc->max_cursor_height = dm->adev->dm.dc->caps.max_cursor_size; @@ -3468,6 +3475,9 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, &aconnector->base, &amdgpu_dm_connector_helper_funcs); + if (aconnector->base.funcs->reset) + aconnector->base.funcs->reset(&aconnector->base); + amdgpu_dm_connector_init_helper( dm, aconnector, -- cgit v1.2.3 From 74baea4275ee130c67400b33c532da8999b530af Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Mon, 6 Nov 2017 14:43:41 +0300 Subject: drm/amd/display: checking for NULL instead of IS_ERR() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit backlight_device_register() never returns NULL, it returns error pointers on error so the check here is wrong. Acked-by: Christian König Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 33a15a1d818c..75f9383f5b9b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1296,7 +1296,7 @@ amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm) &amdgpu_dm_backlight_ops, &props); - if (NULL == dm->backlight_dev) + if (IS_ERR(dm->backlight_dev)) DRM_ERROR("DM: Backlight registration failed!\n"); else DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name); -- cgit v1.2.3 From b349f76ece33be50943c1e6f78ccffd1b3e9627e Mon Sep 17 00:00:00 2001 From: Ernst Sjöstrand Date: Tue, 7 Nov 2017 21:06:57 +0100 Subject: amdgpu/dc: fix more indentation warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit More "warn: inconsistent indenting" fixes from smatch. Acked-by: Christian König Reviewed-by: Harry Wentland Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++----- .../gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 75f9383f5b9b..ad98885222e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -517,7 +517,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); list_for_each_entry(connector, &dev->mode_config.connector_list, head) { - aconnector = to_amdgpu_dm_connector(connector); + aconnector = to_amdgpu_dm_connector(connector); if (aconnector->dc_link->type == dc_connection_mst_branch) { DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n", aconnector, aconnector->base.base.id); @@ -4712,10 +4712,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } - /* Run this here since we want to validate the streams we created */ - ret = drm_atomic_helper_check_planes(dev, state); - if (ret) - goto fail; + /* Run this here since we want to validate the streams we created */ + ret = drm_atomic_helper_check_planes(dev, state); + if (ret) + goto fail; /* Check scaling and underscan changes*/ /*TODO Removed scaling changes validation due to inability to commit diff --git a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c index 0c4bbc10510d..81f9f3e34c10 100644 --- a/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c +++ b/drivers/gpu/drm/amd/display/dc/i2caux/dce110/aux_engine_dce110.c @@ -318,7 +318,7 @@ static void process_channel_reply( REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); - reply->data[i] = aux_sw_data_val; + reply->data[i] = aux_sw_data_val; ++i; } -- cgit v1.2.3 From 2a55f09643acf51ec0f1c72d92fdd4515e9a8aa7 Mon Sep 17 00:00:00 2001 From: Ernst Sjöstrand Date: Tue, 7 Nov 2017 21:06:58 +0100 Subject: amdgpu/dc: Fix potential null dereferences in amdgpu_dm.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Acked-by: Christian König Reviewed-by: Harry Wentland Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ad98885222e6..8ee1bff09a6c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2423,6 +2423,8 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) return NULL; state = kzalloc(sizeof(*state), GFP_KERNEL); + if (!state) + return NULL; __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base); @@ -3419,6 +3421,8 @@ create_i2c(struct ddc_service *ddc_service, struct amdgpu_i2c_adapter *i2c; i2c = kzalloc(sizeof(struct amdgpu_i2c_adapter), GFP_KERNEL); + if (!i2c) + return NULL; i2c->base.owner = THIS_MODULE; i2c->base.class = I2C_CLASS_DDC; i2c->base.dev.parent = &adev->pdev->dev; @@ -3449,6 +3453,11 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, DRM_DEBUG_DRIVER("%s()\n", __func__); i2c = create_i2c(link->ddc, link->link_index, &res); + if (!i2c) { + DRM_ERROR("Failed to create i2c adapter data\n"); + return -ENOMEM; + } + aconnector->i2c = i2c; res = i2c_add_adapter(&i2c->base); -- cgit v1.2.3 From 423788c7a866cb7f5265af9b96952e8a4bf48fd5 Mon Sep 17 00:00:00 2001 From: Ernst Sjöstrand Date: Tue, 7 Nov 2017 21:06:59 +0100 Subject: amdgpu/dc: Fix missing null checks in amdgpu_dm.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From smatch: error: we previously assumed X could be null Acked-by: Christian König Reviewed-by: Harry Wentland Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8ee1bff09a6c..cb45a3dc5a65 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -430,10 +430,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) /* Display Core create. */ adev->dm.dc = dc_create(&init_data); - if (adev->dm.dc) + if (adev->dm.dc) { DRM_INFO("Display Core initialized!\n"); - else + } else { DRM_INFO("Display Core failed to initialize!\n"); + goto error; + } INIT_WORK(&adev->dm.mst_hotplug_work, hotplug_notify_work_func); @@ -2273,7 +2275,7 @@ decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode, } } -static void create_fake_sink(struct amdgpu_dm_connector *aconnector) +static int create_fake_sink(struct amdgpu_dm_connector *aconnector) { struct dc_sink *sink = NULL; struct dc_sink_init_data sink_init_data = { 0 }; @@ -2282,14 +2284,18 @@ static void create_fake_sink(struct amdgpu_dm_connector *aconnector) sink_init_data.sink_signal = aconnector->dc_link->connector_signal; sink = dc_sink_create(&sink_init_data); - if (!sink) + if (!sink) { DRM_ERROR("Failed to create sink!\n"); + return -ENOMEM; + } sink->sink_signal = SIGNAL_TYPE_VIRTUAL; aconnector->fake_enable = true; aconnector->dc_sink = sink; aconnector->dc_link->local_sink = sink; + + return 0; } static struct dc_stream_state * @@ -2323,7 +2329,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, if (aconnector->mst_port) goto stream_create_fail; - create_fake_sink(aconnector); + if (create_fake_sink(aconnector)) + goto stream_create_fail; } stream = dc_create_stream_for_sink(aconnector->dc_sink); -- cgit v1.2.3 From 53a23207f2a17fd990c85bd84c45d243463e21bb Mon Sep 17 00:00:00 2001 From: Ernst Sjöstrand Date: Tue, 7 Nov 2017 21:18:06 +0100 Subject: amdgpu/dc: Fix double unlock in amdgpu_dm_commit_planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by smartch: amdgpu_dm_commit_planes() error: double unlock 'spin_lock:&crtc->dev->event_lock' amdgpu_dm_commit_planes() error: double unlock 'irqsave:flags' The error path doesn't return so we only need a single unlock. Reviewed-by: Harry Wentland Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cb45a3dc5a65..8ed6767b4616 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3904,7 +3904,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, DRM_ERROR("%s: acrtc %d, already busy\n", __func__, acrtc_attach->crtc_id); - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); /* In commit tail framework this cannot happen */ WARN_ON(1); } -- cgit v1.2.3 From 01e28f9c03aa88edfda313e6d309c816690d4b10 Mon Sep 17 00:00:00 2001 From: Michel Dänzer Date: Thu, 9 Nov 2017 18:38:09 +0100 Subject: amdgpu/dm: Don't use DRM_ERROR in amdgpu_dm_atomic_check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The atomic_check hook is expected to fail in some cases, e.g. if the modeset operation requested by userspace cannot be performed, so it must not spam dmesg on failure. Fixes spurious [drm:amdgpu_dm_atomic_check [amdgpu]] *ERROR* Atomic state validation failed with error :-35 ! error messages on DPMS off with CONFIG_DEBUG_WW_MUTEX_SLOWPATH enabled. While we're at it, fix up the existing DRM_DEBUG_DRIVER strings. Signed-off-by: Michel Dänzer Reviewed-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8ed6767b4616..6db8840c12a3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4662,10 +4662,8 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; ret = drm_atomic_helper_check_modeset(dev, state); - if (ret) { - DRM_ERROR("Atomic state validation failed with error :%d !\n", ret); - return ret; - } + if (ret) + goto fail; /* * legacy_cursor_update should be made false for SoC's having @@ -4782,11 +4780,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, fail: if (ret == -EDEADLK) - DRM_DEBUG_DRIVER("Atomic check stopped due to to deadlock.\n"); + DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) - DRM_DEBUG_DRIVER("Atomic check stopped due to to signal.\n"); + DRM_DEBUG_DRIVER("Atomic check stopped due to signal.\n"); else - DRM_ERROR("Atomic check failed with err: %d \n", ret); + DRM_DEBUG_DRIVER("Atomic check failed with err: %d \n", ret); return ret; } -- cgit v1.2.3 From 6ef39a6224e0f18222a9b75f00d24cdd0c755612 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 26 Oct 2017 18:43:58 -0400 Subject: drm/amd/display: use configurable FBC option in dm Replace ENABLE_FBC macro with config option CONFIG_DRM_AMD_DC_FBC in dm. DC code has been already updated the same way. Signed-off-by: Roman Li Reviewed-by: Shirish Shankarappa Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6db8840c12a3..cd19db28a845 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -344,7 +344,7 @@ static void hotplug_notify_work_func(struct work_struct *work) drm_kms_helper_hotplug_event(dev); } -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) #include "dal_asic_id.h" /* Allocate memory for FBC compressed data */ /* TODO: Dynamic allocation */ @@ -422,7 +422,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) else init_data.log_mask = DC_MIN_LOG_MASK; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) if (adev->family == FAMILY_CZ) amdgpu_dm_initialize_fbc(adev); init_data.fbc_gpu_addr = adev->dm.compressor.gpu_addr; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index f42f8357b676..117521c6a6ed 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -72,7 +72,7 @@ struct irq_list_head { struct work_struct work; }; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) struct dm_comressor_info { void *cpu_addr; struct amdgpu_bo *bo_ptr; @@ -142,7 +142,7 @@ struct amdgpu_display_manager { * Caches device atomic state for suspend/resume */ struct drm_atomic_state *cached_state; -#ifdef ENABLE_FBC +#if defined(CONFIG_DRM_AMD_DC_FBC) struct dm_comressor_info compressor; #endif }; -- cgit v1.2.3 From fcb4019e090b959dbcbfc7bbbc1ebd99c924fa11 Mon Sep 17 00:00:00 2001 From: "Leo (Sunpeng) Li" Date: Wed, 1 Nov 2017 16:49:14 -0400 Subject: drm/amd/display: Fix warnings on S3 resume This is a followup to the following revert: Rex Zhu Revert "drm/amd/display: Match actual state during S3 resume." Three things needed to be addressed: 1. Potential memory leak on dc_state creation in atomic_check during s3 resume 2. Warnings are now seen in dmesg during S3 resume 3. Since dc_state is now created in atomic_check, what the reverted patch was addressing needs to be reevaluated. This change addresses the above: 1. Since the suspend procedure calls drm_atomic_state_clear, our hook for releasing the dc_state is called. This frees it before atomic_check creates it during resume. The leak does not occur. 2. The dc_crtc/plane_state references kept by the atomic states need to be released before calling atomic_check, which warns if they are non-null. This is because atomic_check is responsible for creating the dc_*_states. This is a special case for S3 resume, since the atomic state duplication that occurs during suspend also copies a reference to the dc_*_states. 3. See 2. comments are also updated to reflect this. Reviewed-by: Andrey Grodzovsky Signed-off-by: Leo (Sunpeng) Li Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 28 +++++++++++++++++++++++ 1 file changed, 28 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cd19db28a845..889ed24084e8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -643,6 +643,11 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) struct drm_connector *connector; struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; + struct dm_crtc_state *dm_new_crtc_state; + struct drm_plane *plane; + struct drm_plane_state *new_plane_state; + struct dm_plane_state *dm_new_plane_state; + int ret = 0; int i; @@ -681,6 +686,29 @@ int amdgpu_dm_display_resume(struct amdgpu_device *adev) for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) new_crtc_state->active_changed = true; + /* + * atomic_check is expected to create the dc states. We need to release + * them here, since they were duplicated as part of the suspend + * procedure. + */ + for_each_new_crtc_in_state(adev->dm.cached_state, crtc, new_crtc_state, i) { + dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); + if (dm_new_crtc_state->stream) { + WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1); + dc_stream_release(dm_new_crtc_state->stream); + dm_new_crtc_state->stream = NULL; + } + } + + for_each_new_plane_in_state(adev->dm.cached_state, plane, new_plane_state, i) { + dm_new_plane_state = to_dm_plane_state(new_plane_state); + if (dm_new_plane_state->dc_state) { + WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1); + dc_plane_state_release(dm_new_plane_state->dc_state); + dm_new_plane_state->dc_state = NULL; + } + } + ret = drm_atomic_helper_resume(ddev, adev->dm.cached_state); drm_atomic_state_put(adev->dm.cached_state); -- cgit v1.2.3