From 24ab1df3665e52eda64508a2bf7c2cc688285ccc Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:43:59 +0300 Subject: drm: omapdrm: dss: Use supported outputs instead of display types The dss driver uses the supported display types to check whether the DSS has SDI, VENC or HDMI outputs. We can instead use the supported outputs the provide the same information. This removes the last use of the supported display types, that we can then remove as well. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dss_features.h | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index c36436d27ff5..56936d972cd3 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -99,7 +99,6 @@ bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); void dss_features_init(enum omapdss_version version); -enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel); enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); int dss_feat_get_num_mgrs(void); -- cgit v1.2.3 From 28550474747853d701173ead5722c2215112a84e Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:03 +0300 Subject: drm: omapdrm: Move size unit features to dispc_features structure The buffer_size_unit and burst_size_unit are dispc features. Move them from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 25 +++++++++++++++++------- drivers/gpu/drm/omapdrm/dss/dss_features.c | 31 ------------------------------ drivers/gpu/drm/omapdrm/dss/dss_features.h | 3 --- 3 files changed, 18 insertions(+), 41 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 7053e3fdc9e2..99a308446283 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -88,6 +88,8 @@ struct dispc_features { u16 width, u16 height, u16 out_width, u16 out_height, bool mem_to_mem); u8 num_fifos; + unsigned int buffer_size_unit; + unsigned int burst_size_unit; /* swap GFX & WB fifos */ bool gfx_fifo_workaround:1; @@ -1138,9 +1140,8 @@ static void dispc_configure_burst_sizes(void) static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) { - unsigned unit = dss_feat_get_burst_size_unit(); /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ - return unit * 8; + return dispc.feat->burst_size_unit * 8; } static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) @@ -1225,7 +1226,7 @@ static void dispc_init_fifos(void) u32 unit; int i; - unit = dss_feat_get_buffer_size_unit(); + unit = dispc.feat->buffer_size_unit; dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); @@ -1309,7 +1310,7 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, u8 hi_start, hi_end, lo_start, lo_end; u32 unit; - unit = dss_feat_get_buffer_size_unit(); + unit = dispc.feat->buffer_size_unit; WARN_ON(low % unit != 0); WARN_ON(high % unit != 0); @@ -1362,7 +1363,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, * buffer_units, and the fifo thresholds must be buffer_unit aligned. */ - unsigned buf_unit = dss_feat_get_buffer_size_unit(); + unsigned buf_unit = dispc.feat->buffer_size_unit; unsigned ovl_fifo_size, total_fifo_size, burst_size; int i; @@ -1439,7 +1440,7 @@ static void dispc_init_mflag(void) for (i = 0; i < dss_feat_get_num_ovls(); ++i) { u32 size = dispc_ovl_get_fifo_size(i); - u32 unit = dss_feat_get_buffer_size_unit(); + u32 unit = dispc.feat->buffer_size_unit; u32 low, high; dispc_ovl_set_mflag(i, true); @@ -1458,7 +1459,7 @@ static void dispc_init_mflag(void) if (dispc.feat->has_writeback) { u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB); - u32 unit = dss_feat_get_buffer_size_unit(); + u32 unit = dispc.feat->buffer_size_unit; u32 low, high; dispc_ovl_set_mflag(OMAP_DSS_WB, true); @@ -3706,6 +3707,8 @@ static const struct dispc_features omap24xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_24xx, .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -3727,6 +3730,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -3748,6 +3753,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, .no_framedone_tv = true, .set_max_preload = false, .last_pixel_inc_missing = true, @@ -3769,6 +3776,8 @@ static const struct dispc_features omap44xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .buffer_size_unit = 16, + .burst_size_unit = 16, .gfx_fifo_workaround = true, .set_max_preload = true, .supports_sync_align = true, @@ -3795,6 +3804,8 @@ static const struct dispc_features omap54xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .buffer_size_unit = 16, + .burst_size_unit = 16, .gfx_fifo_workaround = true, .mstandby_workaround = true, .set_max_preload = true, diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index 4172fb3bf106..7393f3fde169 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -50,9 +50,6 @@ struct omap_dss_features { const u32 **supported_color_modes; const enum omap_overlay_caps *overlay_caps; const struct dss_param_range *dss_params; - - const u32 buffer_size_unit; - const u32 burst_size_unit; }; /* This struct is assigned to one of the below during initialization */ @@ -551,8 +548,6 @@ static const struct omap_dss_features omap2_dss_features = { .supported_color_modes = omap2_dss_supported_color_modes, .overlay_caps = omap2_dss_overlay_caps, .dss_params = omap2_dss_param_range, - .buffer_size_unit = 1, - .burst_size_unit = 8, }; /* OMAP3 DSS Features */ @@ -569,8 +564,6 @@ static const struct omap_dss_features omap3430_dss_features = { .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, - .buffer_size_unit = 1, - .burst_size_unit = 8, }; /* @@ -590,8 +583,6 @@ static const struct omap_dss_features am35xx_dss_features = { .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, - .buffer_size_unit = 1, - .burst_size_unit = 8, }; static const struct omap_dss_features am43xx_dss_features = { @@ -607,8 +598,6 @@ static const struct omap_dss_features am43xx_dss_features = { .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = am43xx_dss_param_range, - .buffer_size_unit = 1, - .burst_size_unit = 8, }; static const struct omap_dss_features omap3630_dss_features = { @@ -624,8 +613,6 @@ static const struct omap_dss_features omap3630_dss_features = { .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3630_dss_overlay_caps, .dss_params = omap3_dss_param_range, - .buffer_size_unit = 1, - .burst_size_unit = 8, }; /* OMAP4 DSS Features */ @@ -643,8 +630,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, - .buffer_size_unit = 16, - .burst_size_unit = 16, }; /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */ @@ -661,8 +646,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, - .buffer_size_unit = 16, - .burst_size_unit = 16, }; /* For all the other OMAP4 versions */ @@ -679,8 +662,6 @@ static const struct omap_dss_features omap4_dss_features = { .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, - .buffer_size_unit = 16, - .burst_size_unit = 16, }; /* OMAP5 DSS Features */ @@ -697,8 +678,6 @@ static const struct omap_dss_features omap5_dss_features = { .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap5_dss_param_range, - .buffer_size_unit = 16, - .burst_size_unit = 16, }; /* Functions returning values related to a DSS feature */ @@ -752,16 +731,6 @@ bool dss_feat_color_mode_supported(enum omap_plane_id plane, u32 fourcc) return false; } -u32 dss_feat_get_buffer_size_unit(void) -{ - return omap_current_dss_features->buffer_size_unit; -} - -u32 dss_feat_get_burst_size_unit(void) -{ - return omap_current_dss_features->burst_size_unit; -} - /* DSS has_feature check */ bool dss_has_feature(enum dss_feat_id id) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 56936d972cd3..3fb56d68962b 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -92,9 +92,6 @@ enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane); bool dss_feat_color_mode_supported(enum omap_plane_id plane, u32 fourcc); -u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ -u32 dss_feat_get_burst_size_unit(void); /* in bytes */ - bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); void dss_features_init(enum omapdss_version version); -- cgit v1.2.3 From 94f96ad7c7372dcba74d296de7251f8c6079a2e0 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:04 +0300 Subject: drm: omapdrm: Move color modes feature to dispc_features structure The supported_color_modes is a dispc feature. Move it from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 127 +++++++++++++++++++++++++++- drivers/gpu/drm/omapdrm/dss/dss_features.c | 130 ----------------------------- drivers/gpu/drm/omapdrm/dss/dss_features.h | 3 - 3 files changed, 124 insertions(+), 136 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 99a308446283..f3ae7f16e65c 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -88,6 +88,7 @@ struct dispc_features { u16 width, u16 height, u16 out_width, u16 out_height, bool mem_to_mem); u8 num_fifos; + const u32 **supported_color_modes; unsigned int buffer_size_unit; unsigned int burst_size_unit; @@ -1144,9 +1145,24 @@ static u32 dispc_ovl_get_burst_size(enum omap_plane_id plane) return dispc.feat->burst_size_unit * 8; } +static bool dispc_ovl_color_mode_supported(enum omap_plane_id plane, u32 fourcc) +{ + const u32 *modes; + unsigned int i; + + modes = dispc.feat->supported_color_modes[plane]; + + for (i = 0; modes[i]; ++i) { + if (modes[i] == fourcc) + return true; + } + + return false; +} + static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) { - return dss_feat_get_supported_color_modes(plane); + return dispc.feat->supported_color_modes[plane]; } static int dispc_get_num_ovls(void) @@ -1867,7 +1883,7 @@ static void dispc_ovl_set_rotation_attrs(enum omap_plane_id plane, u8 rotation, REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), row_repeat ? 1 : 0, 18, 18); - if (dss_feat_color_mode_supported(plane, DRM_FORMAT_NV12)) { + if (dispc_ovl_color_mode_supported(plane, DRM_FORMAT_NV12)) { bool doublestride = fourcc == DRM_FORMAT_NV12 && rotation_type == OMAP_DSS_ROT_TILER && @@ -2431,7 +2447,7 @@ static int dispc_ovl_setup_common(enum omap_plane_id plane, out_height); } - if (!dss_feat_color_mode_supported(plane, fourcc)) + if (!dispc_ovl_color_mode_supported(plane, fourcc)) return -EINVAL; r = dispc_ovl_calc_scaling(pclk, lclk, caps, vm, in_width, @@ -3692,6 +3708,106 @@ static void _omap_dispc_initial_config(void) dispc_init_mflag(); } +#define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } + +static const u32 *omap2_dispc_supported_color_modes[] = { + + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, + DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY), +}; + +static const u32 *omap3_dispc_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, + DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, + DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), +}; + +static const u32 *omap4_dispc_supported_color_modes[] = { + /* OMAP_DSS_GFX */ + COLOR_ARRAY( + DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, + DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, + DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, + DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), + + /* OMAP_DSS_VIDEO1 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO2 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_VIDEO3 */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), + + /* OMAP_DSS_WB */ + COLOR_ARRAY( + DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, + DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, + DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, + DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, + DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, + DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, + DRM_FORMAT_RGBX8888), +}; + static const struct dispc_features omap24xx_dispc_feats = { .sw_start = 5, .fp_start = 15, @@ -3707,6 +3823,7 @@ static const struct dispc_features omap24xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_24xx, .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, + .supported_color_modes = omap2_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3730,6 +3847,7 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .supported_color_modes = omap3_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3753,6 +3871,7 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .supported_color_modes = omap3_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3776,6 +3895,7 @@ static const struct dispc_features omap44xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .supported_color_modes = omap4_dispc_supported_color_modes, .buffer_size_unit = 16, .burst_size_unit = 16, .gfx_fifo_workaround = true, @@ -3804,6 +3924,7 @@ static const struct dispc_features omap54xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .supported_color_modes = omap4_dispc_supported_color_modes, .buffer_size_unit = 16, .burst_size_unit = 16, .gfx_fifo_workaround = true, diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index 7393f3fde169..cb099f43a8a2 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -47,7 +47,6 @@ struct omap_dss_features { const int num_mgrs; const int num_ovls; const enum omap_dss_output_id *supported_outputs; - const u32 **supported_color_modes; const enum omap_overlay_caps *overlay_caps; const struct dss_param_range *dss_params; }; @@ -170,106 +169,6 @@ static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { OMAP_DSS_OUTPUT_DSI2, }; -#define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } - -static const u32 *omap2_dss_supported_color_modes[] = { - - /* OMAP_DSS_GFX */ - COLOR_ARRAY( - DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, - DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888), - - /* OMAP_DSS_VIDEO1 */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, - DRM_FORMAT_UYVY), - - /* OMAP_DSS_VIDEO2 */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, - DRM_FORMAT_UYVY), -}; - -static const u32 *omap3_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - COLOR_ARRAY( - DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, - DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), - - /* OMAP_DSS_VIDEO1 */ - COLOR_ARRAY( - DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, - DRM_FORMAT_RGBX4444, DRM_FORMAT_RGB565, - DRM_FORMAT_YUYV, DRM_FORMAT_UYVY), - - /* OMAP_DSS_VIDEO2 */ - COLOR_ARRAY( - DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, - DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_YUYV, - DRM_FORMAT_UYVY, DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888), -}; - -static const u32 *omap4_dss_supported_color_modes[] = { - /* OMAP_DSS_GFX */ - COLOR_ARRAY( - DRM_FORMAT_RGBX4444, DRM_FORMAT_ARGB4444, - DRM_FORMAT_RGB565, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_ARGB8888, - DRM_FORMAT_RGBA8888, DRM_FORMAT_RGBX8888, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XRGB4444, - DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB1555), - - /* OMAP_DSS_VIDEO1 */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, - DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, - DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, - DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, - DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, - DRM_FORMAT_RGBX8888), - - /* OMAP_DSS_VIDEO2 */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, - DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, - DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, - DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, - DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, - DRM_FORMAT_RGBX8888), - - /* OMAP_DSS_VIDEO3 */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, - DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, - DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, - DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, - DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, - DRM_FORMAT_RGBX8888), - - /* OMAP_DSS_WB */ - COLOR_ARRAY( - DRM_FORMAT_RGB565, DRM_FORMAT_RGBX4444, - DRM_FORMAT_YUYV, DRM_FORMAT_ARGB1555, - DRM_FORMAT_RGBA8888, DRM_FORMAT_NV12, - DRM_FORMAT_RGBA4444, DRM_FORMAT_XRGB8888, - DRM_FORMAT_RGB888, DRM_FORMAT_UYVY, - DRM_FORMAT_ARGB4444, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB4444, - DRM_FORMAT_RGBX8888), -}; - static const enum omap_overlay_caps omap2_dss_overlay_caps[] = { /* OMAP_DSS_GFX */ OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, @@ -545,7 +444,6 @@ static const struct omap_dss_features omap2_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap2_dss_supported_outputs, - .supported_color_modes = omap2_dss_supported_color_modes, .overlay_caps = omap2_dss_overlay_caps, .dss_params = omap2_dss_param_range, }; @@ -561,7 +459,6 @@ static const struct omap_dss_features omap3430_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -580,7 +477,6 @@ static const struct omap_dss_features am35xx_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -595,7 +491,6 @@ static const struct omap_dss_features am43xx_dss_features = { .num_mgrs = 1, .num_ovls = 3, .supported_outputs = am43xx_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3430_dss_overlay_caps, .dss_params = am43xx_dss_param_range, }; @@ -610,7 +505,6 @@ static const struct omap_dss_features omap3630_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3630_dss_supported_outputs, - .supported_color_modes = omap3_dss_supported_color_modes, .overlay_caps = omap3630_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -627,7 +521,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -643,7 +536,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -659,7 +551,6 @@ static const struct omap_dss_features omap4_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -675,7 +566,6 @@ static const struct omap_dss_features omap5_dss_features = { .num_mgrs = 4, .num_ovls = 4, .supported_outputs = omap5_dss_supported_outputs, - .supported_color_modes = omap4_dss_supported_color_modes, .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap5_dss_param_range, }; @@ -706,31 +596,11 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel return omap_current_dss_features->supported_outputs[channel]; } -const u32 *dss_feat_get_supported_color_modes(enum omap_plane_id plane) -{ - return omap_current_dss_features->supported_color_modes[plane]; -} - enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane) { return omap_current_dss_features->overlay_caps[plane]; } -bool dss_feat_color_mode_supported(enum omap_plane_id plane, u32 fourcc) -{ - const u32 *modes; - unsigned int i; - - modes = omap_current_dss_features->supported_color_modes[plane]; - - for (i = 0; modes[i]; ++i) { - if (modes[i] == fourcc) - return true; - } - - return false; -} - /* DSS has_feature check */ bool dss_has_feature(enum dss_feat_id id) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 3fb56d68962b..06ddfc406b13 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -89,8 +89,6 @@ enum dss_range_param { unsigned long dss_feat_get_param_min(enum dss_range_param param); unsigned long dss_feat_get_param_max(enum dss_range_param param); enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane); -bool dss_feat_color_mode_supported(enum omap_plane_id plane, - u32 fourcc); bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); @@ -100,6 +98,5 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel int dss_feat_get_num_mgrs(void); int dss_feat_get_num_ovls(void); -const u32 *dss_feat_get_supported_color_modes(enum omap_plane_id plane); #endif -- cgit v1.2.3 From fcd4188894dab2f08d74174edd214d7a82521167 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:05 +0300 Subject: drm: omapdrm: Move overlay caps features to dispc_features structure The overlay_caps is a dispc feature. Move it from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 106 +++++++++++++++++++++++++++-- drivers/gpu/drm/omapdrm/dss/dss_features.c | 79 --------------------- drivers/gpu/drm/omapdrm/dss/dss_features.h | 1 - 3 files changed, 102 insertions(+), 84 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index f3ae7f16e65c..c013bfd66865 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -88,6 +88,7 @@ struct dispc_features { u16 width, u16 height, u16 out_width, u16 out_height, bool mem_to_mem); u8 num_fifos; + const enum omap_overlay_caps *overlay_caps; const u32 **supported_color_modes; unsigned int buffer_size_unit; unsigned int burst_size_unit; @@ -2568,7 +2569,7 @@ static int dispc_ovl_setup(enum omap_plane_id plane, enum omap_channel channel) { int r; - enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane); + enum omap_overlay_caps caps = dispc.feat->overlay_caps[plane]; const bool replication = true; DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->" @@ -3708,6 +3709,70 @@ static void _omap_dispc_initial_config(void) dispc_init_mflag(); } +static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap3430_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap3630_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, +}; + +static const enum omap_overlay_caps omap4_dispc_overlay_caps[] = { + /* OMAP_DSS_GFX */ + OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | + OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | + OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO1 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO2 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, + + /* OMAP_DSS_VIDEO3 */ + OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | + OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | + OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, +}; + #define COLOR_ARRAY(arr...) (const u32[]) { arr, 0 } static const u32 *omap2_dispc_supported_color_modes[] = { @@ -3823,6 +3888,7 @@ static const struct dispc_features omap24xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_24xx, .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, + .overlay_caps = omap2_dispc_overlay_caps, .supported_color_modes = omap2_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, @@ -3847,6 +3913,7 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, @@ -3871,6 +3938,32 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .overlay_caps = omap3430_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .buffer_size_unit = 1, + .burst_size_unit = 8, + .no_framedone_tv = true, + .set_max_preload = false, + .last_pixel_inc_missing = true, +}; + +static const struct dispc_features omap36xx_dispc_feats = { + .sw_start = 7, + .fp_start = 19, + .bp_start = 31, + .sw_max = 256, + .vp_max = 4095, + .hp_max = 4096, + .mgr_width_start = 10, + .mgr_height_start = 26, + .mgr_width_max = 2048, + .mgr_height_max = 2048, + .max_lcd_pclk = 173000000, + .max_tv_pclk = 59000000, + .calc_scaling = dispc_ovl_calc_scaling_34xx, + .calc_core_clk = calc_core_clk_34xx, + .num_fifos = 3, + .overlay_caps = omap3630_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .buffer_size_unit = 1, .burst_size_unit = 8, @@ -3895,6 +3988,7 @@ static const struct dispc_features omap44xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, .buffer_size_unit = 16, .burst_size_unit = 16, @@ -3924,6 +4018,7 @@ static const struct dispc_features omap54xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, .buffer_size_unit = 16, .burst_size_unit = 16, @@ -4171,7 +4266,7 @@ static const struct dispc_ops dispc_ops = { /* DISPC HW IP initialisation */ static const struct of_device_id dispc_of_match[] = { { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats }, - { .compatible = "ti,omap3-dispc", .data = &omap34xx_rev3_0_dispc_feats }, + { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats }, { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats }, { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats }, { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats }, @@ -4181,6 +4276,9 @@ static const struct of_device_id dispc_of_match[] = { static const struct soc_device_attribute dispc_soc_devices[] = { { .machine = "OMAP3[45]*", .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, + { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, + { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, + { .machine = "AM43*", .data = &omap34xx_rev3_0_dispc_feats }, { /* sentinel */ } }; @@ -4198,8 +4296,8 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) spin_lock_init(&dispc.control_lock); /* - * The OMAP34xx ES1.x and ES2.x can't be identified through the - * compatible string, use SoC device matching. + * The OMAP34xx and OMAP36xx can't be told apart using the compatible + * string, use SoC device matching. */ soc = soc_device_match(dispc_soc_devices); if (soc) diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index cb099f43a8a2..e272fe9bd2dd 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -47,7 +47,6 @@ struct omap_dss_features { const int num_mgrs; const int num_ovls; const enum omap_dss_output_id *supported_outputs; - const enum omap_overlay_caps *overlay_caps; const struct dss_param_range *dss_params; }; @@ -169,70 +168,6 @@ static const enum omap_dss_output_id omap5_dss_supported_outputs[] = { OMAP_DSS_OUTPUT_DSI2, }; -static const enum omap_overlay_caps omap2_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap3430_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap3630_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, -}; - -static const enum omap_overlay_caps omap4_dss_overlay_caps[] = { - /* OMAP_DSS_GFX */ - OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | - OMAP_DSS_OVL_CAP_ZORDER | OMAP_DSS_OVL_CAP_POS | - OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO1 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO2 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, - - /* OMAP_DSS_VIDEO3 */ - OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_GLOBAL_ALPHA | - OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA | OMAP_DSS_OVL_CAP_ZORDER | - OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, -}; - static const struct dss_param_range omap2_dss_param_range[] = { [FEAT_PARAM_DSS_FCK] = { 0, 133000000 }, [FEAT_PARAM_DSS_PCD] = { 2, 255 }, @@ -444,7 +379,6 @@ static const struct omap_dss_features omap2_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap2_dss_supported_outputs, - .overlay_caps = omap2_dss_overlay_caps, .dss_params = omap2_dss_param_range, }; @@ -459,7 +393,6 @@ static const struct omap_dss_features omap3430_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, - .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -477,7 +410,6 @@ static const struct omap_dss_features am35xx_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, - .overlay_caps = omap3430_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -491,7 +423,6 @@ static const struct omap_dss_features am43xx_dss_features = { .num_mgrs = 1, .num_ovls = 3, .supported_outputs = am43xx_dss_supported_outputs, - .overlay_caps = omap3430_dss_overlay_caps, .dss_params = am43xx_dss_param_range, }; @@ -505,7 +436,6 @@ static const struct omap_dss_features omap3630_dss_features = { .num_mgrs = 2, .num_ovls = 3, .supported_outputs = omap3630_dss_supported_outputs, - .overlay_caps = omap3630_dss_overlay_caps, .dss_params = omap3_dss_param_range, }; @@ -521,7 +451,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -536,7 +465,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -551,7 +479,6 @@ static const struct omap_dss_features omap4_dss_features = { .num_mgrs = 3, .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, - .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap4_dss_param_range, }; @@ -566,7 +493,6 @@ static const struct omap_dss_features omap5_dss_features = { .num_mgrs = 4, .num_ovls = 4, .supported_outputs = omap5_dss_supported_outputs, - .overlay_caps = omap4_dss_overlay_caps, .dss_params = omap5_dss_param_range, }; @@ -596,11 +522,6 @@ enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel return omap_current_dss_features->supported_outputs[channel]; } -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane) -{ - return omap_current_dss_features->overlay_caps[plane]; -} - /* DSS has_feature check */ bool dss_has_feature(enum dss_feat_id id) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 06ddfc406b13..8c2275d8f047 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -88,7 +88,6 @@ enum dss_range_param { /* DSS Feature Functions */ unsigned long dss_feat_get_param_min(enum dss_range_param param); unsigned long dss_feat_get_param_max(enum dss_range_param param); -enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane_id plane); bool dss_has_feature(enum dss_feat_id id); void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); -- cgit v1.2.3 From acf591c6aa1ef27b80da36e9f707b0efe003a03f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:06 +0300 Subject: drm: omapdrm: Move num_ovls and num_mgrs to dispc_features structure The num_ovls and num_mgrs are dispc features. Move them from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 91 ++++++++++++++++++++++-------- drivers/gpu/drm/omapdrm/dss/dss_features.c | 30 ---------- drivers/gpu/drm/omapdrm/dss/dss_features.h | 3 - 3 files changed, 66 insertions(+), 58 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index c013bfd66865..839425ad8a75 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -90,6 +90,8 @@ struct dispc_features { u8 num_fifos; const enum omap_overlay_caps *overlay_caps; const u32 **supported_color_modes; + unsigned int num_mgrs; + unsigned int num_ovls; unsigned int buffer_size_unit; unsigned int burst_size_unit; @@ -349,6 +351,16 @@ static void mgr_fld_write(enum omap_channel channel, spin_unlock_irqrestore(&dispc.control_lock, flags); } +static int dispc_get_num_ovls(void) +{ + return dispc.feat->num_ovls; +} + +static int dispc_get_num_mgrs(void) +{ + return dispc.feat->num_mgrs; +} + #define SR(reg) \ dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) #define RR(reg) \ @@ -376,7 +388,7 @@ static void dispc_save_context(void) SR(CONFIG3); } - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { SR(DEFAULT_COLOR(i)); SR(TRANS_COLOR(i)); SR(SIZE_MGR(i)); @@ -398,7 +410,7 @@ static void dispc_save_context(void) } } - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { SR(OVL_BA0(i)); SR(OVL_BA1(i)); SR(OVL_POSITION(i)); @@ -482,7 +494,7 @@ static void dispc_restore_context(void) if (dss_has_feature(FEAT_MGR_LCD3)) RR(CONFIG3); - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { RR(DEFAULT_COLOR(i)); RR(TRANS_COLOR(i)); RR(SIZE_MGR(i)); @@ -504,7 +516,7 @@ static void dispc_restore_context(void) } } - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { RR(OVL_BA0(i)); RR(OVL_BA1(i)); RR(OVL_POSITION(i)); @@ -785,7 +797,7 @@ static void dispc_ovl_write_color_conv_coef(enum omap_plane_id plane, static void dispc_setup_color_conv_coef(void) { int i; - int num_ovl = dss_feat_get_num_ovls(); + int num_ovl = dispc_get_num_ovls(); const struct color_conv_coef ctbl_bt601_5_ovl = { /* YUV -> RGB */ 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, @@ -877,7 +889,7 @@ static void dispc_ovl_enable_zorder_planes(void) if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) return; - for (i = 0; i < dss_feat_get_num_ovls(); i++) + for (i = 0; i < dispc_get_num_ovls(); i++) REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); } @@ -1134,7 +1146,7 @@ static void dispc_configure_burst_sizes(void) const int burst_size = BURST_SIZE_X8; /* Configure burst size always to maximum size */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) + for (i = 0; i < dispc_get_num_ovls(); ++i) dispc_ovl_set_burst_size(i, burst_size); if (dispc.feat->has_writeback) dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size); @@ -1166,11 +1178,6 @@ static const u32 *dispc_ovl_get_color_modes(enum omap_plane_id plane) return dispc.feat->supported_color_modes[plane]; } -static int dispc_get_num_ovls(void) -{ - return dss_feat_get_num_ovls(); -} - static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) { if (channel == OMAP_DSS_CHANNEL_DIGIT) @@ -1285,7 +1292,7 @@ static void dispc_init_fifos(void) /* * Setup default fifo thresholds. */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + for (i = 0; i < dispc_get_num_ovls(); ++i) { u32 low, high; const bool use_fifomerge = false; const bool manual_update = false; @@ -1389,7 +1396,7 @@ void dispc_ovl_compute_fifo_thresholds(enum omap_plane_id plane, if (use_fifomerge) { total_fifo_size = 0; - for (i = 0; i < dss_feat_get_num_ovls(); ++i) + for (i = 0; i < dispc_get_num_ovls(); ++i) total_fifo_size += dispc_ovl_get_fifo_size(i); } else { total_fifo_size = ovl_fifo_size; @@ -1455,7 +1462,7 @@ static void dispc_init_mflag(void) (1 << 0) | /* MFLAG_CTRL = force always on */ (0 << 2)); /* MFLAG_START = disable */ - for (i = 0; i < dss_feat_get_num_ovls(); ++i) { + for (i = 0; i < dispc_get_num_ovls(); ++i) { u32 size = dispc_ovl_get_fifo_size(i); u32 unit = dispc.feat->buffer_size_unit; u32 low, high; @@ -2694,11 +2701,6 @@ void dispc_pck_free_enable(bool enable) REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); } -static int dispc_get_num_mgrs(void) -{ - return dss_feat_get_num_mgrs(); -} - static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) { mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); @@ -3265,7 +3267,7 @@ static void dispc_dump_regs(struct seq_file *s) p_names = mgr_names; /* DISPC channel specific registers */ - for (i = 0; i < dss_feat_get_num_mgrs(); i++) { + for (i = 0; i < dispc_get_num_mgrs(); i++) { DUMPREG(i, DISPC_DEFAULT_COLOR); DUMPREG(i, DISPC_TRANS_COLOR); DUMPREG(i, DISPC_SIZE_MGR); @@ -3291,7 +3293,7 @@ static void dispc_dump_regs(struct seq_file *s) p_names = ovl_names; - for (i = 0; i < dss_feat_get_num_ovls(); i++) { + for (i = 0; i < dispc_get_num_ovls(); i++) { DUMPREG(i, DISPC_OVL_BA0); DUMPREG(i, DISPC_OVL_BA1); DUMPREG(i, DISPC_OVL_POSITION); @@ -3369,7 +3371,7 @@ static void dispc_dump_regs(struct seq_file *s) /* Video pipeline coefficient registers */ /* start from OMAP_DSS_VIDEO1 */ - for (i = 1; i < dss_feat_get_num_ovls(); i++) { + for (i = 1; i < dispc_get_num_ovls(); i++) { for (j = 0; j < 8; j++) DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); @@ -3890,6 +3892,8 @@ static const struct dispc_features omap24xx_dispc_feats = { .num_fifos = 3, .overlay_caps = omap2_dispc_overlay_caps, .supported_color_modes = omap2_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3915,6 +3919,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .num_fifos = 3, .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3940,6 +3946,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .num_fifos = 3, .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3965,6 +3973,35 @@ static const struct dispc_features omap36xx_dispc_feats = { .num_fifos = 3, .overlay_caps = omap3630_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 2, + .num_ovls = 3, + .buffer_size_unit = 1, + .burst_size_unit = 8, + .no_framedone_tv = true, + .set_max_preload = false, + .last_pixel_inc_missing = true, +}; + +static const struct dispc_features am43xx_dispc_feats = { + .sw_start = 7, + .fp_start = 19, + .bp_start = 31, + .sw_max = 256, + .vp_max = 4095, + .hp_max = 4096, + .mgr_width_start = 10, + .mgr_height_start = 26, + .mgr_width_max = 2048, + .mgr_height_max = 2048, + .max_lcd_pclk = 173000000, + .max_tv_pclk = 59000000, + .calc_scaling = dispc_ovl_calc_scaling_34xx, + .calc_core_clk = calc_core_clk_34xx, + .num_fifos = 3, + .overlay_caps = omap3430_dispc_overlay_caps, + .supported_color_modes = omap3_dispc_supported_color_modes, + .num_mgrs = 1, + .num_ovls = 3, .buffer_size_unit = 1, .burst_size_unit = 8, .no_framedone_tv = true, @@ -3990,6 +4027,8 @@ static const struct dispc_features omap44xx_dispc_feats = { .num_fifos = 5, .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, + .num_mgrs = 3, + .num_ovls = 4, .buffer_size_unit = 16, .burst_size_unit = 16, .gfx_fifo_workaround = true, @@ -4020,6 +4059,8 @@ static const struct dispc_features omap54xx_dispc_feats = { .num_fifos = 5, .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, + .num_mgrs = 4, + .num_ovls = 4, .buffer_size_unit = 16, .burst_size_unit = 16, .gfx_fifo_workaround = true, @@ -4278,7 +4319,7 @@ static const struct soc_device_attribute dispc_soc_devices[] = { .revision = "ES[12].?", .data = &omap34xx_rev1_0_dispc_feats }, { .machine = "OMAP3[45]*", .data = &omap34xx_rev3_0_dispc_feats }, { .machine = "AM35*", .data = &omap34xx_rev3_0_dispc_feats }, - { .machine = "AM43*", .data = &omap34xx_rev3_0_dispc_feats }, + { .machine = "AM43*", .data = &am43xx_dispc_feats }, { /* sentinel */ } }; @@ -4296,7 +4337,7 @@ static int dispc_bind(struct device *dev, struct device *master, void *data) spin_lock_init(&dispc.control_lock); /* - * The OMAP34xx and OMAP36xx can't be told apart using the compatible + * The OMAP3-based models can't be told apart using the compatible * string, use SoC device matching. */ soc = soc_device_match(dispc_soc_devices); diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index e272fe9bd2dd..faa9bc3c03b2 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -44,8 +44,6 @@ struct omap_dss_features { const enum dss_feat_id *features; const int num_features; - const int num_mgrs; - const int num_ovls; const enum omap_dss_output_id *supported_outputs; const struct dss_param_range *dss_params; }; @@ -376,8 +374,6 @@ static const struct omap_dss_features omap2_dss_features = { .features = omap2_dss_feat_list, .num_features = ARRAY_SIZE(omap2_dss_feat_list), - .num_mgrs = 2, - .num_ovls = 3, .supported_outputs = omap2_dss_supported_outputs, .dss_params = omap2_dss_param_range, }; @@ -390,8 +386,6 @@ static const struct omap_dss_features omap3430_dss_features = { .features = omap3430_dss_feat_list, .num_features = ARRAY_SIZE(omap3430_dss_feat_list), - .num_mgrs = 2, - .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, .dss_params = omap3_dss_param_range, }; @@ -407,8 +401,6 @@ static const struct omap_dss_features am35xx_dss_features = { .features = am35xx_dss_feat_list, .num_features = ARRAY_SIZE(am35xx_dss_feat_list), - .num_mgrs = 2, - .num_ovls = 3, .supported_outputs = omap3430_dss_supported_outputs, .dss_params = omap3_dss_param_range, }; @@ -420,8 +412,6 @@ static const struct omap_dss_features am43xx_dss_features = { .features = am43xx_dss_feat_list, .num_features = ARRAY_SIZE(am43xx_dss_feat_list), - .num_mgrs = 1, - .num_ovls = 3, .supported_outputs = am43xx_dss_supported_outputs, .dss_params = am43xx_dss_param_range, }; @@ -433,8 +423,6 @@ static const struct omap_dss_features omap3630_dss_features = { .features = omap3630_dss_feat_list, .num_features = ARRAY_SIZE(omap3630_dss_feat_list), - .num_mgrs = 2, - .num_ovls = 3, .supported_outputs = omap3630_dss_supported_outputs, .dss_params = omap3_dss_param_range, }; @@ -448,8 +436,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { .features = omap4430_es1_0_dss_feat_list, .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list), - .num_mgrs = 3, - .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, .dss_params = omap4_dss_param_range, }; @@ -462,8 +448,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { .features = omap4430_es2_0_1_2_dss_feat_list, .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list), - .num_mgrs = 3, - .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, .dss_params = omap4_dss_param_range, }; @@ -476,8 +460,6 @@ static const struct omap_dss_features omap4_dss_features = { .features = omap4_dss_feat_list, .num_features = ARRAY_SIZE(omap4_dss_feat_list), - .num_mgrs = 3, - .num_ovls = 4, .supported_outputs = omap4_dss_supported_outputs, .dss_params = omap4_dss_param_range, }; @@ -490,23 +472,11 @@ static const struct omap_dss_features omap5_dss_features = { .features = omap5_dss_feat_list, .num_features = ARRAY_SIZE(omap5_dss_feat_list), - .num_mgrs = 4, - .num_ovls = 4, .supported_outputs = omap5_dss_supported_outputs, .dss_params = omap5_dss_param_range, }; /* Functions returning values related to a DSS feature */ -int dss_feat_get_num_mgrs(void) -{ - return omap_current_dss_features->num_mgrs; -} - -int dss_feat_get_num_ovls(void) -{ - return omap_current_dss_features->num_ovls; -} - unsigned long dss_feat_get_param_min(enum dss_range_param param) { return omap_current_dss_features->dss_params[param].min; diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 8c2275d8f047..89a36d2b57a7 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -95,7 +95,4 @@ void dss_features_init(enum omapdss_version version); enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); -int dss_feat_get_num_mgrs(void); -int dss_feat_get_num_ovls(void); - #endif -- cgit v1.2.3 From 6d85d4adb645e5474594c0dc5fafa36c173ecec1 Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:07 +0300 Subject: drm: omapdrm: Move DISPC_CLK_SWITCH reg feature to struct dss_features The register belongs to the DSS, move the feature to the dss_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dss.c | 15 +++++++++++---- drivers/gpu/drm/omapdrm/dss/dss.h | 5 +++++ drivers/gpu/drm/omapdrm/dss/dss_features.c | 10 ---------- drivers/gpu/drm/omapdrm/dss/dss_features.h | 1 - 4 files changed, 16 insertions(+), 15 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c index 3d6b1e8ec0c0..d145d9eedfa7 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.c +++ b/drivers/gpu/drm/omapdrm/dss/dss.c @@ -86,6 +86,7 @@ struct dss_features { const enum omap_display_type *ports; int num_ports; const struct dss_ops *ops; + struct dss_reg_field dispc_clk_switch; }; static struct { @@ -427,7 +428,6 @@ static int dss_get_channel_index(enum omap_channel channel) static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) { int b; - u8 start, end; /* * We always use PRCM clock as the DISPC func clock, except on DSS3, @@ -452,9 +452,9 @@ static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) return; } - dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end); - - REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ + REG_FLD_MOD(DSS_CONTROL, b, /* DISPC_CLK_SWITCH */ + dss.feat->dispc_clk_switch.start, + dss.feat->dispc_clk_switch.end); dss.dispc_clk_source = clk_src; } @@ -1010,6 +1010,7 @@ static const struct dss_features omap24xx_dss_feats = { .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, }; static const struct dss_features omap34xx_dss_feats = { @@ -1020,6 +1021,7 @@ static const struct dss_features omap34xx_dss_feats = { .ports = omap34xx_ports, .num_ports = ARRAY_SIZE(omap34xx_ports), .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, }; static const struct dss_features omap3630_dss_feats = { @@ -1030,6 +1032,7 @@ static const struct dss_features omap3630_dss_feats = { .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, }; static const struct dss_features omap44xx_dss_feats = { @@ -1040,6 +1043,7 @@ static const struct dss_features omap44xx_dss_feats = { .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), .ops = &dss_ops_omap4, + .dispc_clk_switch = { 9, 8 }, }; static const struct dss_features omap54xx_dss_feats = { @@ -1050,6 +1054,7 @@ static const struct dss_features omap54xx_dss_feats = { .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), .ops = &dss_ops_omap5, + .dispc_clk_switch = { 9, 7 }, }; static const struct dss_features am43xx_dss_feats = { @@ -1060,6 +1065,7 @@ static const struct dss_features am43xx_dss_feats = { .ports = omap2plus_ports, .num_ports = ARRAY_SIZE(omap2plus_ports), .ops = &dss_ops_omap2_omap3, + .dispc_clk_switch = { 0, 0 }, }; static const struct dss_features dra7xx_dss_feats = { @@ -1070,6 +1076,7 @@ static const struct dss_features dra7xx_dss_feats = { .ports = dra7xx_ports, .num_ports = ARRAY_SIZE(dra7xx_ports), .ops = &dss_ops_dra7, + .dispc_clk_switch = { 9, 7 }, }; static int dss_init_ports(struct platform_device *pdev) diff --git a/drivers/gpu/drm/omapdrm/dss/dss.h b/drivers/gpu/drm/omapdrm/dss/dss.h index b7ce0eacdd0e..ac642607321e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss.h +++ b/drivers/gpu/drm/omapdrm/dss/dss.h @@ -200,6 +200,11 @@ struct dss_pll { struct dss_pll_clock_info cinfo; }; +/* Defines a generic omap register field */ +struct dss_reg_field { + u8 start, end; +}; + struct dispc_clock_info { /* rates that we get with dividers below */ unsigned long lck; diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index faa9bc3c03b2..04848196780e 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -28,11 +28,6 @@ #include "dss.h" #include "dss_features.h" -/* Defines a generic omap register field */ -struct dss_reg_field { - u8 start, end; -}; - struct dss_param_range { int min, max; }; @@ -59,7 +54,6 @@ static const struct dss_reg_field omap2_dss_reg_fields[] = { [FEAT_REG_FIFOSIZE] = { 8, 0 }, [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, }; static const struct dss_reg_field omap3_dss_reg_fields[] = { @@ -70,7 +64,6 @@ static const struct dss_reg_field omap3_dss_reg_fields[] = { [FEAT_REG_FIFOSIZE] = { 10, 0 }, [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, }; static const struct dss_reg_field am43xx_dss_reg_fields[] = { @@ -81,7 +74,6 @@ static const struct dss_reg_field am43xx_dss_reg_fields[] = { [FEAT_REG_FIFOSIZE] = { 10, 0 }, [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, [FEAT_REG_VERTICALACCU] = { 25, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 0, 0 }, }; static const struct dss_reg_field omap4_dss_reg_fields[] = { @@ -92,7 +84,6 @@ static const struct dss_reg_field omap4_dss_reg_fields[] = { [FEAT_REG_FIFOSIZE] = { 15, 0 }, [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, [FEAT_REG_VERTICALACCU] = { 26, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 8 }, }; static const struct dss_reg_field omap5_dss_reg_fields[] = { @@ -103,7 +94,6 @@ static const struct dss_reg_field omap5_dss_reg_fields[] = { [FEAT_REG_FIFOSIZE] = { 15, 0 }, [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, [FEAT_REG_VERTICALACCU] = { 26, 16 }, - [FEAT_REG_DISPC_CLK_SWITCH] = { 9, 7 }, }; static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 89a36d2b57a7..e0e825db4b0a 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -73,7 +73,6 @@ enum dss_feat_reg_field { FEAT_REG_FIFOSIZE, FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU, - FEAT_REG_DISPC_CLK_SWITCH, }; enum dss_range_param { -- cgit v1.2.3 From 38dc07039c8bc4bf5f61a127143c2cfec2d7c36a Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:08 +0300 Subject: drm: omapdrm: Move reg_fields to dispc_features structure The reg_fields feature describes DISPC registers only. Move it from the omap_dss_features structure to the dispc_features structure. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dispc.c | 87 +++++++++++++++++++++++++---- drivers/gpu/drm/omapdrm/dss/dss_features.c | 89 ------------------------------ drivers/gpu/drm/omapdrm/dss/dss_features.h | 12 ---- 3 files changed, 76 insertions(+), 112 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index 839425ad8a75..3ad52c04a299 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -88,6 +88,8 @@ struct dispc_features { u16 width, u16 height, u16 out_width, u16 out_height, bool mem_to_mem); u8 num_fifos; + const struct dss_reg_field *reg_fields; + const unsigned int num_reg_fields; const enum omap_overlay_caps *overlay_caps; const u32 **supported_color_modes; unsigned int num_mgrs; @@ -188,6 +190,17 @@ enum mgr_reg_fields { DISPC_MGR_FLD_NUM, }; +/* DISPC register field id */ +enum dispc_feat_reg_field { + FEAT_REG_FIRHINC, + FEAT_REG_FIRVINC, + FEAT_REG_FIFOHIGHTHRESHOLD, + FEAT_REG_FIFOLOWTHRESHOLD, + FEAT_REG_FIFOSIZE, + FEAT_REG_HORIZONTALACCU, + FEAT_REG_VERTICALACCU, +}; + struct dispc_reg_field { u16 reg; u8 high; @@ -361,6 +374,16 @@ static int dispc_get_num_mgrs(void) return dispc.feat->num_mgrs; } +static void dispc_get_reg_field(enum dispc_feat_reg_field id, + u8 *start, u8 *end) +{ + if (id >= dispc.feat->num_reg_fields) + BUG(); + + *start = dispc.feat->reg_fields[id].start; + *end = dispc.feat->reg_fields[id].end; +} + #define SR(reg) \ dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) #define RR(reg) \ @@ -1252,7 +1275,7 @@ static void dispc_init_fifos(void) unit = dispc.feat->buffer_size_unit; - dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); + dispc_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); @@ -1342,8 +1365,8 @@ void dispc_ovl_set_fifo_threshold(enum omap_plane_id plane, u32 low, low /= unit; high /= unit; - dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); - dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); + dispc_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); + dispc_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", plane, @@ -1510,10 +1533,8 @@ static void dispc_ovl_set_fir(enum omap_plane_id plane, if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { u8 hinc_start, hinc_end, vinc_start, vinc_end; - dss_feat_get_reg_field(FEAT_REG_FIRHINC, - &hinc_start, &hinc_end); - dss_feat_get_reg_field(FEAT_REG_FIRVINC, - &vinc_start, &vinc_end); + dispc_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end); + dispc_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end); val = FLD_VAL(vinc, vinc_start, vinc_end) | FLD_VAL(hinc, hinc_start, hinc_end); @@ -1530,8 +1551,8 @@ static void dispc_ovl_set_vid_accu0(enum omap_plane_id plane, int haccu, u32 val; u8 hor_start, hor_end, vert_start, vert_end; - dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); - dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); val = FLD_VAL(vaccu, vert_start, vert_end) | FLD_VAL(haccu, hor_start, hor_end); @@ -1545,8 +1566,8 @@ static void dispc_ovl_set_vid_accu1(enum omap_plane_id plane, int haccu, u32 val; u8 hor_start, hor_end, vert_start, vert_end; - dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); - dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); + dispc_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); + dispc_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); val = FLD_VAL(vaccu, vert_start, vert_end) | FLD_VAL(haccu, hor_start, hor_end); @@ -3711,6 +3732,36 @@ static void _omap_dispc_initial_config(void) dispc_init_mflag(); } +static const struct dss_reg_field omap2_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 11, 0 }, + [FEAT_REG_FIRVINC] = { 27, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, + [FEAT_REG_FIFOSIZE] = { 8, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, +}; + +static const struct dss_reg_field omap3_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, + [FEAT_REG_FIFOSIZE] = { 10, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, + [FEAT_REG_VERTICALACCU] = { 25, 16 }, +}; + +static const struct dss_reg_field omap4_dispc_reg_fields[] = { + [FEAT_REG_FIRHINC] = { 12, 0 }, + [FEAT_REG_FIRVINC] = { 28, 16 }, + [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, + [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, + [FEAT_REG_FIFOSIZE] = { 15, 0 }, + [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, + [FEAT_REG_VERTICALACCU] = { 26, 16 }, +}; + static const enum omap_overlay_caps omap2_dispc_overlay_caps[] = { /* OMAP_DSS_GFX */ OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, @@ -3890,6 +3941,8 @@ static const struct dispc_features omap24xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_24xx, .calc_core_clk = calc_core_clk_24xx, .num_fifos = 3, + .reg_fields = omap2_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap2_dispc_reg_fields), .overlay_caps = omap2_dispc_overlay_caps, .supported_color_modes = omap2_dispc_supported_color_modes, .num_mgrs = 2, @@ -3917,6 +3970,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .num_mgrs = 2, @@ -3944,6 +3999,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .num_mgrs = 2, @@ -3971,6 +4028,8 @@ static const struct dispc_features omap36xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), .overlay_caps = omap3630_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .num_mgrs = 2, @@ -3998,6 +4057,8 @@ static const struct dispc_features am43xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_34xx, .calc_core_clk = calc_core_clk_34xx, .num_fifos = 3, + .reg_fields = omap3_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap3_dispc_reg_fields), .overlay_caps = omap3430_dispc_overlay_caps, .supported_color_modes = omap3_dispc_supported_color_modes, .num_mgrs = 1, @@ -4025,6 +4086,8 @@ static const struct dispc_features omap44xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .reg_fields = omap4_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, .num_mgrs = 3, @@ -4057,6 +4120,8 @@ static const struct dispc_features omap54xx_dispc_feats = { .calc_scaling = dispc_ovl_calc_scaling_44xx, .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, + .reg_fields = omap4_dispc_reg_fields, + .num_reg_fields = ARRAY_SIZE(omap4_dispc_reg_fields), .overlay_caps = omap4_dispc_overlay_caps, .supported_color_modes = omap4_dispc_supported_color_modes, .num_mgrs = 4, diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index 04848196780e..b0a07c6558cd 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -33,9 +33,6 @@ struct dss_param_range { }; struct omap_dss_features { - const struct dss_reg_field *reg_fields; - const int num_reg_fields; - const enum dss_feat_id *features; const int num_features; @@ -46,56 +43,6 @@ struct omap_dss_features { /* This struct is assigned to one of the below during initialization */ static const struct omap_dss_features *omap_current_dss_features; -static const struct dss_reg_field omap2_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 11, 0 }, - [FEAT_REG_FIRVINC] = { 27, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 8, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 24, 16 }, - [FEAT_REG_FIFOSIZE] = { 8, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, -}; - -static const struct dss_reg_field omap3_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, - [FEAT_REG_FIFOSIZE] = { 10, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, -}; - -static const struct dss_reg_field am43xx_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 11, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 27, 16 }, - [FEAT_REG_FIFOSIZE] = { 10, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 9, 0 }, - [FEAT_REG_VERTICALACCU] = { 25, 16 }, -}; - -static const struct dss_reg_field omap4_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, - [FEAT_REG_FIFOSIZE] = { 15, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, - [FEAT_REG_VERTICALACCU] = { 26, 16 }, -}; - -static const struct dss_reg_field omap5_dss_reg_fields[] = { - [FEAT_REG_FIRHINC] = { 12, 0 }, - [FEAT_REG_FIRVINC] = { 28, 16 }, - [FEAT_REG_FIFOLOWTHRESHOLD] = { 15, 0 }, - [FEAT_REG_FIFOHIGHTHRESHOLD] = { 31, 16 }, - [FEAT_REG_FIFOSIZE] = { 15, 0 }, - [FEAT_REG_HORIZONTALACCU] = { 10, 0 }, - [FEAT_REG_VERTICALACCU] = { 26, 16 }, -}; - static const enum omap_dss_output_id omap2_dss_supported_outputs[] = { /* OMAP_DSS_CHANNEL_LCD */ OMAP_DSS_OUTPUT_DPI | OMAP_DSS_OUTPUT_DBI, @@ -358,9 +305,6 @@ static const enum dss_feat_id omap5_dss_feat_list[] = { /* OMAP2 DSS Features */ static const struct omap_dss_features omap2_dss_features = { - .reg_fields = omap2_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields), - .features = omap2_dss_feat_list, .num_features = ARRAY_SIZE(omap2_dss_feat_list), @@ -370,9 +314,6 @@ static const struct omap_dss_features omap2_dss_features = { /* OMAP3 DSS Features */ static const struct omap_dss_features omap3430_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - .features = omap3430_dss_feat_list, .num_features = ARRAY_SIZE(omap3430_dss_feat_list), @@ -385,9 +326,6 @@ static const struct omap_dss_features omap3430_dss_features = { * vdds_dsi regulator. */ static const struct omap_dss_features am35xx_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - .features = am35xx_dss_feat_list, .num_features = ARRAY_SIZE(am35xx_dss_feat_list), @@ -396,9 +334,6 @@ static const struct omap_dss_features am35xx_dss_features = { }; static const struct omap_dss_features am43xx_dss_features = { - .reg_fields = am43xx_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(am43xx_dss_reg_fields), - .features = am43xx_dss_feat_list, .num_features = ARRAY_SIZE(am43xx_dss_feat_list), @@ -407,9 +342,6 @@ static const struct omap_dss_features am43xx_dss_features = { }; static const struct omap_dss_features omap3630_dss_features = { - .reg_fields = omap3_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields), - .features = omap3630_dss_feat_list, .num_features = ARRAY_SIZE(omap3630_dss_feat_list), @@ -420,9 +352,6 @@ static const struct omap_dss_features omap3630_dss_features = { /* OMAP4 DSS Features */ /* For OMAP4430 ES 1.0 revision */ static const struct omap_dss_features omap4430_es1_0_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - .features = omap4430_es1_0_dss_feat_list, .num_features = ARRAY_SIZE(omap4430_es1_0_dss_feat_list), @@ -432,9 +361,6 @@ static const struct omap_dss_features omap4430_es1_0_dss_features = { /* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - .features = omap4430_es2_0_1_2_dss_feat_list, .num_features = ARRAY_SIZE(omap4430_es2_0_1_2_dss_feat_list), @@ -444,9 +370,6 @@ static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = { /* For all the other OMAP4 versions */ static const struct omap_dss_features omap4_dss_features = { - .reg_fields = omap4_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields), - .features = omap4_dss_feat_list, .num_features = ARRAY_SIZE(omap4_dss_feat_list), @@ -456,9 +379,6 @@ static const struct omap_dss_features omap4_dss_features = { /* OMAP5 DSS Features */ static const struct omap_dss_features omap5_dss_features = { - .reg_fields = omap5_dss_reg_fields, - .num_reg_fields = ARRAY_SIZE(omap5_dss_reg_fields), - .features = omap5_dss_feat_list, .num_features = ARRAY_SIZE(omap5_dss_feat_list), @@ -497,15 +417,6 @@ bool dss_has_feature(enum dss_feat_id id) return false; } -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end) -{ - if (id >= omap_current_dss_features->num_reg_fields) - BUG(); - - *start = omap_current_dss_features->reg_fields[id].start; - *end = omap_current_dss_features->reg_fields[id].end; -} - void dss_features_init(enum omapdss_version version) { switch (version) { diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index e0e825db4b0a..24c57c55e785 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -64,17 +64,6 @@ enum dss_feat_id { FEAT_MFLAG, }; -/* DSS register field id */ -enum dss_feat_reg_field { - FEAT_REG_FIRHINC, - FEAT_REG_FIRVINC, - FEAT_REG_FIFOHIGHTHRESHOLD, - FEAT_REG_FIFOLOWTHRESHOLD, - FEAT_REG_FIFOSIZE, - FEAT_REG_HORIZONTALACCU, - FEAT_REG_VERTICALACCU, -}; - enum dss_range_param { FEAT_PARAM_DSS_FCK, FEAT_PARAM_DSS_PCD, @@ -89,7 +78,6 @@ unsigned long dss_feat_get_param_min(enum dss_range_param param); unsigned long dss_feat_get_param_max(enum dss_range_param param); bool dss_has_feature(enum dss_feat_id id); -void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end); void dss_features_init(enum omapdss_version version); enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel); -- cgit v1.2.3 From 34dfb85f03957f5f396058e2f3c15686e77c28ba Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:09 +0300 Subject: drm: omapdrm: Move FEAT_VENC_REQUIRES_TV_DAC_CLK to venc driver The FEAT_VENC_REQUIRES_TV_DAC_CLK is specific to the VENC, move it from the omap_dss_features structure to the venc driver. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dss_features.c | 2 -- drivers/gpu/drm/omapdrm/dss/dss_features.h | 1 - drivers/gpu/drm/omapdrm/dss/venc.c | 14 +++++++++++++- 3 files changed, 13 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.c b/drivers/gpu/drm/omapdrm/dss/dss_features.c index b0a07c6558cd..dcdc66be28de 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.c +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.c @@ -166,7 +166,6 @@ static const enum dss_feat_id omap3430_dss_feat_list[] = { FEAT_ROWREPEATENABLE, FEAT_RESIZECONF, FEAT_DSI_REVERSE_TXCLKESC, - FEAT_VENC_REQUIRES_TV_DAC_CLK, FEAT_CPR, FEAT_PRELOAD, FEAT_FIR_COEF_V, @@ -185,7 +184,6 @@ static const enum dss_feat_id am35xx_dss_feat_list[] = { FEAT_ROWREPEATENABLE, FEAT_RESIZECONF, FEAT_DSI_REVERSE_TXCLKESC, - FEAT_VENC_REQUIRES_TV_DAC_CLK, FEAT_CPR, FEAT_PRELOAD, FEAT_FIR_COEF_V, diff --git a/drivers/gpu/drm/omapdrm/dss/dss_features.h b/drivers/gpu/drm/omapdrm/dss/dss_features.h index 24c57c55e785..f296bc77f220 100644 --- a/drivers/gpu/drm/omapdrm/dss/dss_features.h +++ b/drivers/gpu/drm/omapdrm/dss/dss_features.h @@ -50,7 +50,6 @@ enum dss_feat_id { FEAT_HDMI_AUDIO_USE_MCLK, FEAT_HANDLE_UV_SEPARATE, FEAT_ATTR2, - FEAT_VENC_REQUIRES_TV_DAC_CLK, FEAT_CPR, FEAT_PRELOAD, FEAT_FIR_COEF_V, diff --git a/drivers/gpu/drm/omapdrm/dss/venc.c b/drivers/gpu/drm/omapdrm/dss/venc.c index 9e4fc000e961..b0a85b10fa38 100644 --- a/drivers/gpu/drm/omapdrm/dss/venc.c +++ b/drivers/gpu/drm/omapdrm/dss/venc.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "omapdss.h" #include "dss.h" @@ -309,6 +310,7 @@ static struct { struct videomode vm; enum omap_dss_venc_type type; bool invert_polarity; + bool requires_tv_dac_clk; struct omap_dss_device output; } venc; @@ -691,7 +693,7 @@ static int venc_get_clocks(struct platform_device *pdev) { struct clk *clk; - if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) { + if (venc.requires_tv_dac_clk) { clk = devm_clk_get(&pdev->dev, "tv_dac_clk"); if (IS_ERR(clk)) { DSSERR("can't get tv_dac_clk\n"); @@ -826,6 +828,12 @@ err: } /* VENC HW IP initialisation */ +static const struct soc_device_attribute venc_soc_devices[] = { + { .machine = "OMAP3[45]*" }, + { .machine = "AM35*" }, + { /* sentinel */ } +}; + static int venc_bind(struct device *dev, struct device *master, void *data) { struct platform_device *pdev = to_platform_device(dev); @@ -835,6 +843,10 @@ static int venc_bind(struct device *dev, struct device *master, void *data) venc.pdev = pdev; + /* The OMAP34xx, OMAP35xx and AM35xx VENC require the TV DAC clock. */ + if (soc_device_match(venc_soc_devices)) + venc.requires_tv_dac_clk = true; + mutex_init(&venc.venc_lock); venc.wss_data = 0; -- cgit v1.2.3 From 44d8ca10789759f73bee50e7bb1695e7b8b8d22f Mon Sep 17 00:00:00 2001 From: Laurent Pinchart Date: Sat, 5 Aug 2017 01:44:10 +0300 Subject: drm: omapdrm: Move FEAT_DSI_* features to dsi driver The FEAT_DSI_* features are specific to the DSI, move them from the omap_dss_features structure to the dsi driver. Signed-off-by: Laurent Pinchart Signed-off-by: Tomi Valkeinen --- drivers/gpu/drm/omapdrm/dss/dsi.c | 137 ++++++++++++++++++----------- drivers/gpu/drm/omapdrm/dss/dss_features.c | 16 ---- drivers/gpu/drm/omapdrm/dss/dss_features.h | 7 -- 3 files changed, 88 insertions(+), 72 deletions(-) (limited to 'drivers/gpu/drm/omapdrm/dss/dss_features.h') diff --git a/drivers/gpu/drm/omapdrm/dss/dsi.c b/drivers/gpu/drm/omapdrm/dss/dsi.c index 3d98e9ce9a43..1af2c5329c99 100644 --- a/drivers/gpu/drm/omapdrm/dss/dsi.c +++ b/drivers/gpu/drm/omapdrm/dss/dsi.c @@ -44,6 +44,7 @@ #include #include #include +#include #include