From 6b43538f0698695fba9aa0c0b29a80c555cf1b63 Mon Sep 17 00:00:00 2001 From: Tinghan Shen Date: Tue, 10 Jan 2023 16:43:11 +0800 Subject: ASoC: SOF: mediatek: Support mt8188 platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add support of SOF on MediaTek MT8188 SoC. MT8188 ADSP integrates with a single core Cadence HiFi-5 DSP. The IPC communication between AP and DSP is based on shared DRAM and mailbox interrupt. The change in the mt8186.h is compatible on both mt8186 and mt8188. The register controls booting the DSP core with the default address or the user specified address. Both mt8186 and mt8188 should boot with the user specified boot in the driver. The usage of the register is the same on both SoC, but the control bit is different on mt8186 and mt8188, which is bit 1 on mt8186 and bit 0 on mt8188. Configure the redundant bit has noside effect on both SoCs. Signed-off-by: Tinghan Shen Reviewed-by: Péter Ujfalusi Reviewed-by: Pierre-Louis Bossart Reviewed-by: Ranjani Sridharan Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230110084312.12953-3-tinghan.shen@mediatek.com Signed-off-by: Mark Brown --- sound/soc/sof/mediatek/mt8186/mt8186.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'sound/soc/sof/mediatek/mt8186/mt8186.h') diff --git a/sound/soc/sof/mediatek/mt8186/mt8186.h b/sound/soc/sof/mediatek/mt8186/mt8186.h index 98b2965e5ba6..5b521c60b4e3 100644 --- a/sound/soc/sof/mediatek/mt8186/mt8186.h +++ b/sound/soc/sof/mediatek/mt8186/mt8186.h @@ -52,7 +52,15 @@ struct snd_sof_dev; #define ADSP_PRID 0x0 #define ADSP_ALTVEC_C0 0x04 #define ADSP_ALTVECSEL 0x0C -#define ADSP_ALTVECSEL_C0 BIT(1) +#define MT8188_ADSP_ALTVECSEL_C0 BIT(0) +#define MT8186_ADSP_ALTVECSEL_C0 BIT(1) + +/* + * On MT8188, BIT(1) is not evaluated and on MT8186 BIT(0) is not evaluated: + * We can simplify the driver by safely setting both bits regardless of the SoC. + */ +#define ADSP_ALTVECSEL_C0 (MT8188_ADSP_ALTVECSEL_C0 | \ + MT8186_ADSP_ALTVECSEL_C0) /* dsp bus */ #define ADSP_SRAM_POOL_CON 0x190 -- cgit v1.2.3