path: root/arch/arm/mach-omap2/prm.h

#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H
#define __ARCH_ARM_MACH_OMAP2_PRM_H

/*
 * OMAP2/3 Power/Reset Management (PRM) register definitions
 *
 * Copyright (C) 2007-2009 Texas Instruments, Inc.
 * Copyright (C) 2007 Nokia Corporation
 *
 * Written by Paul Walmsley
 * Updated for OMAP4 by Rajendra Nayak (rnayak@ti.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "prcm-common.h"

#define OMAP2420_PRM_REGADDR(module, reg)				\
			IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
#define OMAP2430_PRM_REGADDR(module, reg)				\
			IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
#define OMAP34XX_PRM_REGADDR(module, reg)				\
			IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
#define OMAP44XX_PRM_REGADDR(module, reg)				\
			IO_ADDRESS(OMAP4430_PRM_BASE + (module) + (reg))

/*
 * Architecture-specific global PRM registers
 * Use __raw_{read,write}l() with these registers.
 *
 * With a few exceptions, these are the register names beginning with
 * PRCM_* on 24xx, and PRM_* on 34xx and 44xx.  (The exceptions are the
 * IRQSTATUS and IRQENABLE bits.)
 *
 */

#define OMAP2_PRCM_REVISION_OFFSET	0x0000
#define OMAP2420_PRCM_REVISION		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
#define OMAP2_PRCM_SYSCONFIG_OFFSET	0x0010
#define OMAP2420_PRCM_SYSCONFIG		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)

#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET	0x0018
#define OMAP2420_PRCM_IRQSTATUS_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET	0x001c
#define OMAP2420_PRCM_IRQENABLE_MPU	OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)

#define OMAP2_PRCM_VOLTCTRL_OFFSET	0x0050
#define OMAP2420_PRCM_VOLTCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
#define OMAP2_PRCM_VOLTST_OFFSET	0x0054
#define OMAP2420_PRCM_VOLTST		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET	0x0060
#define OMAP2420_PRCM_CLKSRC_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET	0x0070
#define OMAP2420_PRCM_CLKOUT_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET	0x0078
#define OMAP2420_PRCM_CLKEMUL_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET	0x0080
#define OMAP2420_PRCM_CLKCFG_CTRL	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET	0x0084
#define OMAP2420_PRCM_CLKCFG_STATUS	OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
#define OMAP2_PRCM_VOLTSETUP_OFFSET	0x0090
#define OMAP2420_PRCM_VOLTSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
#define OMAP2_PRCM_CLKSSETUP_OFFSET	0x0094
#define OMAP2420_PRCM_CLKSSETUP		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
#define OMAP2_PRCM_POLCTRL_OFFSET	0x0098
#define OMAP2420_PRCM_POLCTRL		OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)

#define OMAP2430_PRCM_REVISION		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
#define OMAP2430_PRCM_SYSCONFIG		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)

#define OMAP2430_PRCM_IRQSTATUS_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
#define OMAP2430_PRCM_IRQENABLE_MPU	OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)

#define OMAP2430_PRCM_VOLTCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
#define OMAP2430_PRCM_VOLTST		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
#define OMAP2430_PRCM_CLKSRC_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
#define OMAP2430_PRCM_CLKOUT_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
#define OMAP2430_PRCM_CLKEMUL_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
#define OMAP2430_PRCM_CLKCFG_CTRL	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
#define OMAP2430_PRCM_CLKCFG_STATUS	OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
#define OMAP2430_PRCM_VOLTSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
#define OMAP2430_PRCM_CLKSSETUP		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
#define OMAP2430_PRCM_POLCTRL		OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)

#define OMAP3_PRM_REVISION_OFFSET	0x0004
#define OMAP3430_PRM_REVISION		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
#define OMAP3_PRM_SYSCONFIG_OFFSET	0x0014
#define OMAP3430_PRM_SYSCONFIG		OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)

#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET	0x0018
#define OMAP3430_PRM_IRQSTATUS_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
#define OMAP3_PRM_IRQENABLE_MPU_OFFSET	0x001c
#define OMAP3430_PRM_IRQENABLE_MPU	OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)


#define OMAP3_PRM_VC_SMPS_SA_OFFSET	0x0020
#define OMAP3430_PRM_VC_SMPS_SA		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET	0x0024
#define OMAP3430_PRM_VC_SMPS_VOL_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET	0x0028
#define OMAP3430_PRM_VC_SMPS_CMD_RA	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET	0x002c
#define OMAP3430_PRM_VC_CMD_VAL_0	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET	0x0030
#define OMAP3430_PRM_VC_CMD_VAL_1	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
#define OMAP3_PRM_VC_CH_CONF_OFFSET	0x0034
#define OMAP3430_PRM_VC_CH_CONF		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
#define OMAP3_PRM_VC_I2C_CFG_OFFSET	0x0038
#define OMAP3430_PRM_VC_I2C_CFG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET	0x003c
#define OMAP3430_PRM_VC_BYPASS_VAL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
#define OMAP3_PRM_RSTCTRL_OFFSET	0x0050
#define OMAP3430_PRM_RSTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
#define OMAP3_PRM_RSTTIME_OFFSET	0x0054
#define OMAP3430_PRM_RSTTIME		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
#define OMAP3_PRM_RSTST_OFFSET	0x0058
#define OMAP3430_PRM_RSTST		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
#define OMAP3_PRM_VOLTCTRL_OFFSET	0x0060
#define OMAP3430_PRM_VOLTCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
#define OMAP3_PRM_SRAM_PCHARGE_OFFSET	0x0064
#define OMAP3430_PRM_SRAM_PCHARGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
#define OMAP3_PRM_CLKSRC_CTRL_OFFSET	0x0070
#define OMAP3430_PRM_CLKSRC_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
#define OMAP3_PRM_VOLTSETUP1_OFFSET	0x0090
#define OMAP3430_PRM_VOLTSETUP1		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
#define OMAP3_PRM_VOLTOFFSET_OFFSET	0x0094
#define OMAP3430_PRM_VOLTOFFSET		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
#define OMAP3_PRM_CLKSETUP_OFFSET	0x0098
#define OMAP3430_PRM_CLKSETUP		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
#define OMAP3_PRM_POLCTRL_OFFSET	0x009c
#define OMAP3430_PRM_POLCTRL		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
#define OMAP3_PRM_VOLTSETUP2_OFFSET	0x00a0
#define OMAP3430_PRM_VOLTSETUP2		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
#define OMAP3_PRM_VP1_CONFIG_OFFSET	0x00b0
#define OMAP3430_PRM_VP1_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET	0x00b4
#define OMAP3430_PRM_VP1_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET	0x00b8
#define OMAP3430_PRM_VP1_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
#define OMAP3_PRM_VP1_VLIMITTO_OFFSET	0x00bc
#define OMAP3430_PRM_VP1_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
#define OMAP3_PRM_VP1_VOLTAGE_OFFSET	0x00c0
#define OMAP3430_PRM_VP1_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
#define OMAP3_PRM_VP1_STATUS_OFFSET	0x00c4
#define OMAP3430_PRM_VP1_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
#define OMAP3_PRM_VP2_CONFIG_OFFSET	0x00d0
#define OMAP3430_PRM_VP2_CONFIG		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET	0x00d4
#define OMAP3430_PRM_VP2_VSTEPMIN	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET	0x00d8
#define OMAP3430_PRM_VP2_VSTEPMAX	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
#define OMAP3_PRM_VP2_VLIMITTO_OFFSET	0x00dc
#define OMAP3430_PRM_VP2_VLIMITTO	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
#define OMAP3_PRM_VP2_VOLTAGE_OFFSET	0x00e0
#define OMAP3430_PRM_VP2_VOLTAGE	OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
#define OMAP3_PRM_VP2_STATUS_OFFSET	0x00e4
#define OMAP3430_PRM_VP2_STATUS		OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)

#define OMAP3_PRM_CLKSEL_OFFSET	0x0040
#define OMAP3430_PRM_CLKSEL		OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
#define OMAP3_PRM_CLKOUT_CTRL_OFFSET	0x0070
#define OMAP3430_PRM_CLKOUT_CTRL	OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)

#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL	OMAP44XX_PRM_REGADDR(OMAP4430_CKGEN_MOD, 0x0)
#define OMAP4430_CM_DPLL_SYS_REF_CLKSEL	OMAP44XX_PRM_REGADDR(OMAP4430_CKGEN_MOD, 0x4)
#define OMAP4430_CM_L4_WKUP_CLKSEL	OMAP44XX_PRM_REGADDR(OMAP4430_CKGEN_MOD, 0x8)
#define OMAP4430_CM_ABE_PLL_REF_CLKSEL	OMAP44XX_PRM_REGADDR(OMAP4430_CKGEN_MOD, 0xC)
#define OMAP4430_CM_SYS_CLKSEL		OMAP44XX_PRM_REGADDR(OMAP4430_CKGEN_MOD, 0x10)
#define OMAP4430_PM_ABE_PWRSTCTRL	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x0)
#define OMAP4430_PM_ABE_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x4)
#define OMAP4430_RM_ABE_AESS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x2C)
#define OMAP4430_PM_ABE_PDM_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x30)
#define OMAP4430_RM_ABE_PDM_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x34)
#define OMAP4430_PM_ABE_DMIC_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x38)
#define OMAP4430_RM_ABE_DMIC_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x3C)
#define OMAP4430_PM_ABE_MCASP_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x40)
#define OMAP4430_RM_ABE_MCASP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x44)
#define OMAP4430_PM_ABE_MCBSP1_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x48)
#define OMAP4430_RM_ABE_MCBSP1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x4C)
#define OMAP4430_PM_ABE_MCBSP2_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x50)
#define OMAP4430_RM_ABE_MCBSP2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x54)
#define OMAP4430_PM_ABE_MCBSP3_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x58)
#define OMAP4430_RM_ABE_MCBSP3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x5C)
#define OMAP4430_PM_ABE_SLIMBUS_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x60)
#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x64)
#define OMAP4430_PM_ABE_TIMER5_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x68)
#define OMAP4430_RM_ABE_TIMER5_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x6C)
#define OMAP4430_PM_ABE_TIMER6_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x70)
#define OMAP4430_RM_ABE_TIMER6_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x74)
#define OMAP4430_PM_ABE_TIMER7_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x78)
#define OMAP4430_RM_ABE_TIMER7_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x7C)
#define OMAP4430_PM_ABE_TIMER8_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x80)
#define OMAP4430_RM_ABE_TIMER8_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x84)
#define OMAP4430_PM_ABE_WDT3_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x88)
#define OMAP4430_RM_ABE_WDT3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ABE_MOD, 0x8C)
#define OMAP4430_PM_DSS_PWRSTCTRL	OMAP44XX_PRM_REGADDR(OMAP4430_DSS_MOD, 0x0)
#define OMAP4430_PM_DSS_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_DSS_MOD, 0x4)
#define OMAP4430_PM_DSS_DSS_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_DSS_MOD, 0x20)
#define OMAP4430_RM_DSS_DSS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_DSS_MOD, 0x24)
#define OMAP4430_RM_DSS_DEISS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_DSS_MOD, 0x2C)
#define OMAP4430_PM_L3INIT_PWRSTCTRL	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x0)
#define OMAP4430_PM_L3INIT_PWRSTST	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x4)
#define OMAP4430_PM_L3INIT_MMC1_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x28)
#define OMAP4430_RM_L3INIT_MMC1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x2C)
#define OMAP4430_PM_L3INIT_MMC2_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x30)
#define OMAP4430_RM_L3INIT_MMC2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x34)
#define OMAP4430_PM_L3INIT_HSI_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x38)
#define OMAP4430_RM_L3INIT_HSI_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x3C)
#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x40)
#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x44)
#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x58)
#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x5C)
#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x60)
#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x64)
#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x68)
#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x6C)
#define OMAP4430_RM_L3INIT_P1500_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x7C)
#define OMAP4430_RM_L3INIT_EMAC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x84)
#define OMAP4430_PM_L3INIT_SATA_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x88)
#define OMAP4430_RM_L3INIT_SATA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x8C)
#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x94)
#define OMAP4430_PM_L3INIT_PCIESS_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x98)
#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0x9C)
#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xAC)
#define OMAP4430_PM_L3INIT_XHPI_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xC0)
#define OMAP4430_RM_L3INIT_XHPI_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xC4)
#define OMAP4430_PM_L3INIT_MMC6_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xC8)
#define OMAP4430_RM_L3INIT_MMC6_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xCC)
#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xD0)
#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xD4)
#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L3INIT_MOD, 0xE4)
#define OMAP4430_PM_L4PER_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x0)
#define OMAP4430_PM_L4PER_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x4)
#define OMAP4430_RM_L4PER_ADC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x24)
#define OMAP4430_PM_L4PER_GPTIMER10_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x28)
#define OMAP4430_RM_L4PER_GPTIMER10_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x2C)
#define OMAP4430_PM_L4PER_GPTIMER11_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x30)
#define OMAP4430_RM_L4PER_GPTIMER11_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x34)
#define OMAP4430_PM_L4PER_GPTIMER2_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x38)
#define OMAP4430_RM_L4PER_GPTIMER2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x3C)
#define OMAP4430_PM_L4PER_GPTIMER3_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x40)
#define OMAP4430_RM_L4PER_GPTIMER3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x44)
#define OMAP4430_PM_L4PER_GPTIMER4_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x48)
#define OMAP4430_RM_L4PER_GPTIMER4_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x4C)
#define OMAP4430_PM_L4PER_GPTIMER9_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x50)
#define OMAP4430_RM_L4PER_GPTIMER9_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x54)
#define OMAP4430_RM_L4PER_ELM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x5C)
#define OMAP4430_PM_L4PER_GPIO2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x60)
#define OMAP4430_RM_L4PER_GPIO2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x64)
#define OMAP4430_PM_L4PER_GPIO3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x68)
#define OMAP4430_RM_L4PER_GPIO3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x6C)
#define OMAP4430_PM_L4PER_GPIO4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x70)
#define OMAP4430_RM_L4PER_GPIO4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x74)
#define OMAP4430_PM_L4PER_GPIO5_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x78)
#define OMAP4430_RM_L4PER_GPIO5_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x7C)
#define OMAP4430_PM_L4PER_GPIO6_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x80)
#define OMAP4430_RM_L4PER_GPIO6_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x84)
#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x8C)
#define OMAP4430_PM_L4PER_HECC1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x90)
#define OMAP4430_RM_L4PER_HECC1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x94)
#define OMAP4430_PM_L4PER_HECC2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x98)
#define OMAP4430_RM_L4PER_HECC2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x9C)
#define OMAP4430_PM_L4PER_I2C1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xA0)
#define OMAP4430_RM_L4PER_I2C1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xA4)
#define OMAP4430_PM_L4PER_I2C2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xA8)
#define OMAP4430_RM_L4PER_I2C2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xAC)
#define OMAP4430_PM_L4PER_I2C3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xB0)
#define OMAP4430_RM_L4PER_I2C3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xB4)
#define OMAP4430_PM_L4PER_I2C4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xB8)
#define OMAP4430_RM_L4PER_I2C4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xBC)
#define OMAP4430_RM_L4PER_L4_PER_CONTEXT 	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xC0)
#define OMAP4430_PM_L4PER_MCASP2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xD0)
#define OMAP4430_RM_L4PER_MCASP2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xD4)
#define OMAP4430_PM_L4PER_MCASP3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xD8)
#define OMAP4430_RM_L4PER_MCASP3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xDC)
#define OMAP4430_PM_L4PER_MCBSP4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xE0)
#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xE4)
#define OMAP4430_RM_L4PER_MGATE_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xEC)
#define OMAP4430_PM_L4PER_MCSPI1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xF0)
#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xF4)
#define OMAP4430_PM_L4PER_MCSPI2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xF8)
#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0xFC)
#define OMAP4430_PM_L4PER_MCSPI3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x100)
#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x104)
#define OMAP4430_PM_L4PER_MCSPI4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x108)
#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x10C)
#define OMAP4430_PM_L4PER_MMCSD3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x120)
#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x124)
#define OMAP4430_PM_L4PER_MMCSD4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x128)
#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x12C)
#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x134)
#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x138)
#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x13C)
#define OMAP4430_PM_L4PER_UART1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x140)
#define OMAP4430_RM_L4PER_UART1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x144)
#define OMAP4430_PM_L4PER_UART2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x148)
#define OMAP4430_RM_L4PER_UART2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x14C)
#define OMAP4430_PM_L4PER_UART3_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x150)
#define OMAP4430_RM_L4PER_UART3_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x154)
#define OMAP4430_PM_L4PER_UART4_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x158)
#define OMAP4430_RM_L4PER_UART4_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x15C)
#define OMAP4430_PM_L4PER_MMCSD5_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x160)
#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x164)
#define OMAP4430_RM_L4SEC_AES1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1A4)
#define OMAP4430_RM_L4SEC_AES2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1AC)
#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1B4)
#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1BC)
#define OMAP4430_RM_L4SEC_RNG_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1C4)
#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1CC)
#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_L4PER_MOD, 0x1DC)
#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x24)
#define OMAP4430_RM_WKUP_WDT1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x2C)
#define OMAP4430_PM_WKUP_WDT2_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x30)
#define OMAP4430_RM_WKUP_WDT2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x34)
#define OMAP4430_PM_WKUP_GPIO1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x38)
#define OMAP4430_RM_WKUP_GPIO1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x3C)
#define OMAP4430_PM_WKUP_TIMER1_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x40)
#define OMAP4430_RM_WKUP_TIMER1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x44)
#define OMAP4430_PM_WKUP_TIMER12_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x48)
#define OMAP4430_RM_WKUP_TIMER12_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x4C)
#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x54)
#define OMAP4430_PM_WKUP_USIM_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x58)
#define OMAP4430_RM_WKUP_USIM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x5C)
#define OMAP4430_RM_WKUP_SARRAM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x64)
#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x78)
#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x7C)
#define OMAP4430_PM_WKUP_RTC_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x80)
#define OMAP4430_RM_WKUP_RTC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_MOD, 0x84)
#define OMAP4430_PM_MPU_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_MPU_MOD, 0x0)
#define OMAP4430_PM_MPU_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_MPU_MOD, 0x4)
#define OMAP4430_RM_MPU_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_MPU_MOD, 0x14)
#define OMAP4430_RM_MPU_MPU_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_MPU_MOD, 0x24)
#define OMAP4430_PM_TESLA_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DSP_MOD, 0x0)
#define OMAP4430_PM_TESLA_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_DSP_MOD, 0x4)
#define OMAP4430_RM_TESLA_RSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DSP_MOD, 0x10)
#define OMAP4430_RM_TESLA_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_DSP_MOD, 0x14)
#define OMAP4430_RM_TESLA_TESLA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_DSP_MOD, 0x24)
#define OMAP4430_PM_IVAHD_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x0)
#define OMAP4430_PM_IVAHD_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x4)
#define OMAP4430_RM_IVAHD_RSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x10)
#define OMAP4430_RM_IVAHD_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x14)
#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x24)
#define OMAP4430_RM_IVAHD_SL2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x2C)
#define OMAP4430_PM_CORE_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_CORE_MOD, 0x0)
#define OMAP4430_PM_CORE_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_CORE_MOD, 0x4)
#define OMAP4430_RM_L3_1_L3_1_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x24)
#define OMAP4430_RM_L3_2_L3_2_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x124)
#define OMAP4430_RM_L3_2_GPMC_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x12C)
#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x134)
#define OMAP4430_RM_DUCATI_RSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x210)
#define OMAP4430_RM_DUCATI_RSTST		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x214)
#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x224)
#define OMAP4430_RM_SDMA_SDMA_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x324)
#define OMAP4430_RM_MEMIF_DMM_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x424)
#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x42C)
#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x434)
#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x43C)
#define OMAP4430_RM_MEMIF_DLL_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x444)
#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x454)
#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x45C)
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x464)
#define OMAP4430_RM_D2D_SAD2D_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x524)
#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x52C)
#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x624)
#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x62C)
#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x634)
#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x63C)
#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x724)
#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x72C)
#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_IVAHD_MOD, 0x744)
#define OMAP4430_REVISION_PRM			OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x0)
#define OMAP4430_PRM_IRQSTATUS_MPU		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x10)
#define OMAP4430_PRM_IRQENABLE_MPU		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x18)
#define OMAP4430_PRM_IRQSTATUS_DUCATI		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x20)
#define OMAP4430_PRM_IRQENABLE_DUCATI		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x28)
#define OMAP4430_PRM_IRQSTATUS_TESLA		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x30)
#define OMAP4430_PRM_IRQENABLE_TESLA		OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x38)
#define OMAP4430_PRM_PRM_PROFILING_CLKCTRL	OMAP44XX_PRM_REGADDR(OMAP4430_OCP_SOCKET_MOD, 0x40)
#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x24)
#define OMAP4430_PM_ALWON_SR_MPU_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x28)
#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x2C)
#define OMAP4430_PM_ALWON_SR_IVA_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x30)
#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x34)
#define OMAP4430_PM_ALWON_SR_CORE_WKDEP		OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x38)
#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_ALWAYS_ON_MOD, 0x3C)
#define OMAP4430_PM_CAM_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_CAM_MOD, 0x0)
#define OMAP4430_PM_CAM_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_CAM_MOD, 0x4)
#define OMAP4430_RM_CAM_ISS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_CAM_MOD, 0x24)
#define OMAP4430_RM_CAM_FDIF_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_CAM_MOD, 0x2C)
#define OMAP4430_PM_GFX_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_GFX_MOD, 0x0)
#define OMAP4430_PM_GFX_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_GFX_MOD, 0x4)
#define OMAP4430_RM_GFX_GFX_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_GFX_MOD, 0x24)
#define OMAP4430_PM_EMU_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_EMU_MOD, 0x0)
#define OMAP4430_PM_EMU_PWRSTST			OMAP44XX_PRM_REGADDR(OMAP4430_EMU_MOD, 0x4)
#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT		OMAP44XX_PRM_REGADDR(OMAP4430_EMU_MOD, 0x24)
#define OMAP4430_PM_CEFUSE_PWRSTCTRL		OMAP44XX_PRM_REGADDR(OMAP4430_CEFUSE_MOD, 0x0)
#define OMAP4430_PM_CEFUSE_PWRSTST		OMAP44XX_PRM_REGADDR(OMAP4430_CEFUSE_MOD, 0x4)
#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT	OMAP44XX_PRM_REGADDR(OMAP4430_CEFUSE_MOD, 0x24)
#define OMAP4430_PRM_RSTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x0)
#define OMAP4430_PRM_RSTST			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x4)
#define OMAP4430_PRM_RSTTIME			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x8)
#define OMAP4430_PRM_CLKREQCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xC)
#define OMAP4430_PRM_VOLTCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x10)
#define OMAP4430_PRM_PWRREQCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x14)
#define OMAP4430_PRM_PSCON_COUNT		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x18)
#define OMAP4430_PRM_IO_COUNT			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x1C)
#define OMAP4430_PRM_IO_PMCTRL			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x20)
#define OMAP4430_PRM_VOLTSETUP_CORE_OFF		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x24)
#define OMAP4430_PRM_VOLTSETUP_MPU_OFF		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x28)
#define OMAP4430_PRM_VOLTSETUP_IVA_OFF		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x2C)
#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x30)
#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x34)
#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x38)
#define OMAP4430_PRM_VP_CORE_CONFIG		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x3C)
#define OMAP4430_PRM_VP_CORE_STATUS		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x40)
#define OMAP4430_PRM_VP_CORE_VLIMITTO		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x44)
#define OMAP4430_PRM_VP_CORE_VOLTAGE		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x48)
#define OMAP4430_PRM_VP_CORE_VSTEPMAX		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x4C)
#define OMAP4430_PRM_VP_CORE_VSTEPMIN		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x50)
#define OMAP4430_PRM_VP_MPU_CONFIG		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x54)
#define OMAP4430_PRM_VP_MPU_STATUS		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x58)
#define OMAP4430_PRM_VP_MPU_VLIMITTO		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x5C)
#define OMAP4430_PRM_VP_MPU_VOLTAGE		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x60)
#define OMAP4430_PRM_VP_MPU_VSTEPMAX		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x64)
#define OMAP4430_PRM_VP_MPU_VSTEPMIN		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x68)
#define OMAP4430_PRM_VP_IVA_CONFIG		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x6C)
#define OMAP4430_PRM_VP_IVA_STATUS		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x70)
#define OMAP4430_PRM_VP_IVA_VLIMITTO		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x74)
#define OMAP4430_PRM_VP_IVA_VOLTAGE		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x78)
#define OMAP4430_PRM_VP_IVA_VSTEPMAX		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x7C)
#define OMAP4430_PRM_VP_IVA_VSTEPMIN		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x80)
#define OMAP4430_PRM_VC_SMPS_SA			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x84)
#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x88)
#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x8C)
#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x90)
#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x94)
#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x98)
#define OMAP4430_PRM_VC_VAL_BYPASS		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0x9C)
#define OMAP4430_PRM_VC_CFG_CHANNEL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xA0)
#define OMAP4430_PRM_VC_CFG_I2C_MODE		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xA4)
#define OMAP4430_PRM_VC_CFG_I2C_CLK		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xA8)
#define OMAP4430_PRM_SRAM_COUNT 		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xAC)
#define OMAP4430_PRM_SRAM_WKUP_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xB0)
#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP	OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xB4)
#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xB8)
#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xBC)
#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xC0)
#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xC4)
#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xC8)
#define OMAP4430_PRM_LDO_ABB_MPU_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xCC)
#define OMAP4430_PRM_LDO_ABB_MPU_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xD0)
#define OMAP4430_PRM_LDO_ABB_IVA_SETUP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xD4)
#define OMAP4430_PRM_LDO_ABB_IVA_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xD8)
#define OMAP4430_PRM_LDO_BANDGAP_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xDC)
#define OMAP4430_PRM_DEVICE_OFF_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xE0)
#define OMAP4430_PRM_RESTORE_ST			OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xE4)
#define OMAP4430_PRM_PHASE1_CNDP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xE8)
#define OMAP4430_PRM_PHASE2A_CNDP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xEC)
#define OMAP4430_PRM_PHASE2B_CNDP		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xF0)
#define OMAP4430_PRM_MODEM_IF_CTRL		OMAP44XX_PRM_REGADDR(OMAP4430_DEVICE_MOD, 0xF4)
#define OMAP4430_CM_WKUP_GPTIMER1_CLKCTRL	OMAP44XX_PRM_REGADDR(OMAP4430_WKUP_CM_MOD, 0x40)

/*
 * Module specific PRM registers from PRM_BASE + domain offset
 *
 * Use prm_{read,write}_mod_reg() with these registers.
 *
 * With a few exceptions, these are the register names beginning with
 * {PM,RM}_* on both architectures.  (The exceptions are the IRQSTATUS
 * and IRQENABLE bits.)
 *
 */

/* Registers appearing on both 24xx and 34xx */

#define RM_RSTCTRL					0x0050
#define RM_RSTTIME					0x0054
#define RM_RSTST					0x0058

#define PM_WKEN						0x00a0
#define PM_WKEN1					PM_WKEN
#define PM_WKST						0x00b0
#define PM_WKST1					PM_WKST
#define PM_WKDEP					0x00c8
#define PM_EVGENCTRL					0x00d4
#define PM_EVGENONTIM					0x00d8
#define PM_EVGENOFFTIM					0x00dc
#define PM_PWSTCTRL					0x00e0
#define PM_PWSTST					0x00e4

/* Omap2 specific registers */
#define OMAP24XX_PM_WKEN2				0x00a4
#define OMAP24XX_PM_WKST2				0x00b4

#define OMAP24XX_PRCM_IRQSTATUS_DSP			0x00f0	/* IVA mod */
#define OMAP24XX_PRCM_IRQENABLE_DSP			0x00f4	/* IVA mod */
#define OMAP24XX_PRCM_IRQSTATUS_IVA			0x00f8
#define OMAP24XX_PRCM_IRQENABLE_IVA			0x00fc

/* Omap3 specific registers */
#define OMAP3430ES2_PM_WKEN3				0x00f0
#define OMAP3430ES2_PM_WKST3				0x00b8

#define OMAP3430_PM_MPUGRPSEL				0x00a4
#define OMAP3430_PM_MPUGRPSEL1				OMAP3430_PM_MPUGRPSEL
#define OMAP3430ES2_PM_MPUGRPSEL3			0x00f8

#define OMAP3430_PM_IVAGRPSEL				0x00a8
#define OMAP3430_PM_IVAGRPSEL1				OMAP3430_PM_IVAGRPSEL
#define OMAP3430ES2_PM_IVAGRPSEL3			0x00f4

#define OMAP3430_PM_PREPWSTST				0x00e8

#define OMAP3430_PRM_IRQSTATUS_IVA2			0x00f8
#define OMAP3430_PRM_IRQENABLE_IVA2			0x00fc


#ifndef __ASSEMBLER__

/* Power/reset management domain register get/set */
extern u32 prm_read_mod_reg(s16 module, u16 idx);
extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);

/* Read-modify-write bits in a PRM register (by domain) */
static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return prm_rmw_mod_reg_bits(bits, bits, module, idx);
}

static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
{
	return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
}

#endif

/*
 * Bits common to specific registers
 *
 * The 3430 register and bit names are generally used,
 * since they tend to make more sense
 */

/* PM_EVGENONTIM_MPU */
/* Named PM_EVEGENONTIM_MPU on the 24XX */
#define OMAP_ONTIMEVAL_SHIFT				0
#define OMAP_ONTIMEVAL_MASK				(0xffffffff << 0)

/* PM_EVGENOFFTIM_MPU */
/* Named PM_EVEGENOFFTIM_MPU on the 24XX */
#define OMAP_OFFTIMEVAL_SHIFT				0
#define OMAP_OFFTIMEVAL_MASK				(0xffffffff << 0)

/* PRM_CLKSETUP and PRCM_VOLTSETUP */
/* Named PRCM_CLKSSETUP on the 24XX */
#define OMAP_SETUP_TIME_SHIFT				0
#define OMAP_SETUP_TIME_MASK				(0xffff << 0)

/* PRM_CLKSRC_CTRL */
/* Named PRCM_CLKSRC_CTRL on the 24XX */
#define OMAP_SYSCLKDIV_SHIFT				6
#define OMAP_SYSCLKDIV_MASK				(0x3 << 6)
#define OMAP_AUTOEXTCLKMODE_SHIFT			3
#define OMAP_AUTOEXTCLKMODE_MASK			(0x3 << 3)
#define OMAP_SYSCLKSEL_SHIFT				0
#define OMAP_SYSCLKSEL_MASK				(0x3 << 0)

/* PM_EVGENCTRL_MPU */
#define OMAP_OFFLOADMODE_SHIFT				3
#define OMAP_OFFLOADMODE_MASK				(0x3 << 3)
#define OMAP_ONLOADMODE_SHIFT				1
#define OMAP_ONLOADMODE_MASK				(0x3 << 1)
#define OMAP_ENABLE					(1 << 0)

/* PRM_RSTTIME */
/* Named RM_RSTTIME_WKUP on the 24xx */
#define OMAP_RSTTIME2_SHIFT				8
#define OMAP_RSTTIME2_MASK				(0x1f << 8)
#define OMAP_RSTTIME1_SHIFT				0
#define OMAP_RSTTIME1_MASK				(0xff << 0)

/* PRM_RSTCTRL */
/* Named RM_RSTCTRL_WKUP on the 24xx */
/* 2420 calls RST_DPLL3 'RST_DPLL' */
#define OMAP_RST_DPLL3					(1 << 2)
#define OMAP_RST_GS					(1 << 1)


/*
 * Bits common to module-shared registers
 *
 * Not all registers of a particular type support all of these bits -
 * check TRM if you are unsure
 */

/*
 * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP
 *
 * 2430: PM_PWSTST_MDM
 *
 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 *	 PM_PWSTST_NEON
 */
#define OMAP_INTRANSITION				(1 << 20)


/*
 * 24XX: PM_PWSTST_GFX, PM_PWSTST_DSP
 *
 * 2430: PM_PWSTST_MDM
 *
 * 3430: PM_PWSTST_IVA2, PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_GFX,
 *	 PM_PWSTST_DSS, PM_PWSTST_CAM, PM_PWSTST_PER, PM_PWSTST_EMU,
 *	 PM_PWSTST_NEON
 */
#define OMAP_POWERSTATEST_SHIFT				0
#define OMAP_POWERSTATEST_MASK				(0x3 << 0)

/*
 * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is
 *	 called 'COREWKUP_RST'
 *
 * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS,
 *	 RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON
 */
#define OMAP_COREDOMAINWKUP_RST				(1 << 3)

/*
 * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP
 *
 * 2430: RM_RSTST_MDM
 *
 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 */
#define OMAP_DOMAINWKUP_RST				(1 << 2)

/*
 * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP
 *	 On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'.
 *
 * 2430: RM_RSTST_MDM
 *
 * 3430: RM_RSTST_CORE, RM_RSTST_EMU
 */
#define OMAP_GLOBALWARM_RST				(1 << 1)
#define OMAP_GLOBALCOLD_RST				(1 << 0)

/*
 * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP
 *	 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP"
 *
 * 2430: PM_WKDEP_MDM
 *
 * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM,
 *	 PM_WKDEP_PER
 */
#define OMAP_EN_WKUP_SHIFT				4
#define OMAP_EN_WKUP_MASK				(1 << 4)

/*
 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 *	 PM_PWSTCTRL_DSP
 *
 * 2430: PM_PWSTCTRL_MDM
 *
 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 *	 PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 *	 PM_PWSTCTRL_NEON
 */
#define OMAP_LOGICRETSTATE				(1 << 2)

/*
 * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX,
 *       PM_PWSTCTRL_DSP, PM_PWSTST_MPU
 *
 * 2430: PM_PWSTCTRL_MDM shared bits
 *
 * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE,
 *	 PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER,
 *	 PM_PWSTCTRL_NEON shared bits
 */
#define OMAP_POWERSTATE_SHIFT				0
#define OMAP_POWERSTATE_MASK				(0x3 << 0)


#endif