summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts
blob: 8956a46788fac2d4c94cb0410d1bcb1249868630 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)

/*
 * Copyright 2019-2021 MNT Research GmbH
 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
 */

/dts-v1/;

#include "imx8mq-nitrogen-som.dtsi"

/ {
	model = "MNT Reform 2";
	compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
	chassis-type = "laptop";

	backlight: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_backlight>;
		pwms = <&pwm2 0 10000 0>;
		power-supply = <&reg_main_usb>;
		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
		brightness-levels = <0 32 64 128 160 200 255>;
		default-brightness-level = <6>;
	};

	panel {
		compatible = "innolux,n125hce-gn1", "simple-panel";
		power-supply = <&reg_main_3v3>;
		backlight = <&backlight>;
		no-hpd;

		port {
			panel_in: endpoint {
				remote-endpoint = <&edp_bridge_out>;
			};
		};
	};

	pcie1_refclk: clock-pcie1-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

	reg_main_5v: regulator-main-5v {
		compatible = "regulator-fixed";
		regulator-name = "5V";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
	};

	reg_main_3v3: regulator-main-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "3V3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	reg_main_usb: regulator-main-usb {
		compatible = "regulator-fixed";
		regulator-name = "USB_PWR";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_main_5v>;
	};

	reg_main_1v8: regulator-main-1v8 {
		compatible = "regulator-fixed";
		regulator-name = "1V8";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		vin-supply = <&reg_main_3v3>;
	};

	reg_main_1v2: regulator-main-1v2 {
		compatible = "regulator-fixed";
		regulator-name = "1V2";
		regulator-min-microvolt = <1200000>;
		regulator-max-microvolt = <1200000>;
		vin-supply = <&reg_main_5v>;
	};

	sound {
		compatible = "fsl,imx-audio-wm8960";
		audio-cpu = <&sai2>;
		audio-codec = <&wm8960>;
		audio-routing =
			"Headphone Jack", "HP_L",
			"Headphone Jack", "HP_R",
			"Ext Spk", "SPK_LP",
			"Ext Spk", "SPK_LN",
			"Ext Spk", "SPK_RP",
			"Ext Spk", "SPK_RN",
			"LINPUT1", "Mic Jack",
			"Mic Jack", "MICB",
			"LINPUT2", "Line In Jack",
			"RINPUT2", "Line In Jack";
		model = "wm8960-audio";
	};
};

&dphy {
	assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
	assigned-clock-rates = <25000000>;
	status = "okay";
};

&fec1 {
	status = "okay";
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";

	wm8960: codec@1a {
		compatible = "wlf,wm8960";
		reg = <0x1a>;
		clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
		clock-names = "mclk";
		#sound-dai-cells = <0>;
	};

	rtc@68 {
		compatible = "nxp,pcf8523";
		reg = <0x68>;
	};
};

&i2c4 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c4>;
	clock-frequency = <400000>;
	status = "okay";

	edp_bridge: bridge@2c {
		compatible = "ti,sn65dsi86";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_edp_bridge>;
		reg = <0x2c>;
		enable-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
		vccio-supply = <&reg_main_1v8>;
		vpll-supply = <&reg_main_1v8>;
		vcca-supply = <&reg_main_1v2>;
		vcc-supply = <&reg_main_1v2>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				edp_bridge_in: endpoint {
					remote-endpoint = <&mipi_dsi_out>;
				};
			};

			port@1 {
				reg = <1>;

				edp_bridge_out: endpoint {
					remote-endpoint = <&panel_in>;
				};
			};
		};
	};
};

&lcdif {
	assigned-clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
	assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>;
	/delete-property/assigned-clock-rates;
	status = "okay";
};

&mipi_dsi {
	status = "okay";

	ports {
		port@1 {
			reg = <1>;

			mipi_dsi_out: endpoint {
				remote-endpoint = <&edp_bridge_in>;
			};
		};
	};
};

&pcie1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pcie1>;
	reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>;
	clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
		 <&clk IMX8MQ_CLK_PCIE2_AUX>,
		 <&clk IMX8MQ_CLK_PCIE2_PHY>,
		 <&pcie1_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	status = "okay";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "okay";
};


&reg_1p8v {
	vin-supply = <&reg_main_5v>;
};

&reg_snvs {
	vin-supply = <&reg_main_5v>;
};

&reg_arm_dram {
	vin-supply = <&reg_main_5v>;
};

&reg_dram_1p1v {
	vin-supply = <&reg_main_5v>;
};

&reg_soc_gpu_vpu {
	vin-supply = <&reg_main_5v>;
};

&sai2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	assigned-clocks = <&clk IMX8MQ_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
	assigned-clock-rates = <25000000>;
	fsl,sai-mclk-direction-output;
	fsl,sai-asynchronous;
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&usb3_phy0 {
	vbus-supply = <&reg_main_usb>;
	status = "okay";
};

&usb3_phy1 {
	vbus-supply = <&reg_main_usb>;
	status = "okay";
};

&usb_dwc3_0 {
	dr_mode = "host";
	status = "okay";
};

&usb_dwc3_1 {
	dr_mode = "host";
	status = "okay";
};

&usdhc2 {
	assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
	assigned-clock-rates = <200000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	vqmmc-supply = <&reg_main_3v3>;
	vmmc-supply = <&reg_main_3v3>;
	bus-width = <4>;
	status = "okay";
};

&iomuxc {
	pinctrl_backlight: backlightgrp {
		fsl,pins = <
			MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x3
		>;
	};

	pinctrl_edp_bridge: edpbridgegrp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20		0x1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL			0x40000022
			MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA			0x40000022
		>;
	};

	pinctrl_i2c4: i2c4grp {
		fsl,pins = <
			MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL			0x40000022
			MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA			0x40000022
		>;
	};

	pinctrl_pcie1: pcie1grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23		0x16
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT			0x3
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0		0xd6
			MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC		0xd6
			MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK		0xd6
			MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK		0xd6
			MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0		0xd6
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX		0x45
			MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX		0x45
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B		0x0
			MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK			0x83
			MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD			0xc3
			MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0		0xc3
			MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1		0xc3
			MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2		0xc3
			MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3		0xc3
		>;
	};
};