summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/renesas/r8a77960.dtsi
blob: 12476e354d746d0eb867c7e2d97a355ce1a76660 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285
2286
2287
2288
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417
2418
2419
2420
2421
2422
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435
2436
2437
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469
2470
2471
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499
2500
2501
2502
2503
2504
2505
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704
2705
2706
2707
2708
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055
3056
3057
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
 *
 * Copyright (C) 2016-2017 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/r8a7796-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7796-sysc.h>

#define CPG_AUDIO_CLK_I		R8A7796_CLK_S0D4

/ {
	compatible = "renesas,r8a7796";
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		i2c6 = &i2c6;
		i2c7 = &i2c_dvfs;
	};

	/*
	 * The external audio clocks are configured as 0 Hz fixed frequency
	 * clocks by default.
	 * Boards that provide audio clocks should override them.
	 */
	audio_clk_a: audio_clk_a {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	audio_clk_b: audio_clk_b {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	audio_clk_c: audio_clk_c {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	cluster0_opp: opp_table0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1500000000 {
			opp-hz = /bits/ 64 <1500000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1600000000 {
			opp-hz = /bits/ 64 <1600000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
			turbo-mode;
		};
		opp-1700000000 {
			opp-hz = /bits/ 64 <1700000000>;
			opp-microvolt = <900000>;
			clock-latency-ns = <300000>;
			turbo-mode;
		};
		opp-1800000000 {
			opp-hz = /bits/ 64 <1800000000>;
			opp-microvolt = <960000>;
			clock-latency-ns = <300000>;
			turbo-mode;
		};
	};

	cluster1_opp: opp_table1 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1200000000 {
			opp-hz = /bits/ 64 <1200000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
		};
		opp-1300000000 {
			opp-hz = /bits/ 64 <1300000000>;
			opp-microvolt = <820000>;
			clock-latency-ns = <300000>;
			turbo-mode;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&a57_0>;
				};
				core1 {
					cpu = <&a57_1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&a53_0>;
				};
				core1 {
					cpu = <&a53_1>;
				};
				core2 {
					cpu = <&a53_2>;
				};
				core3 {
					cpu = <&a53_3>;
				};
			};
		};

		a57_0: cpu@0 {
			compatible = "arm,cortex-a57";
			reg = <0x0>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
			next-level-cache = <&L2_CA57>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			dynamic-power-coefficient = <854>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
			operating-points-v2 = <&cluster0_opp>;
			capacity-dmips-mhz = <1024>;
			#cooling-cells = <2>;
		};

		a57_1: cpu@1 {
			compatible = "arm,cortex-a57";
			reg = <0x1>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
			next-level-cache = <&L2_CA57>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z>;
			operating-points-v2 = <&cluster0_opp>;
			capacity-dmips-mhz = <1024>;
			#cooling-cells = <2>;
		};

		a53_0: cpu@100 {
			compatible = "arm,cortex-a53";
			reg = <0x100>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_1>;
			#cooling-cells = <2>;
			dynamic-power-coefficient = <277>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <535>;
		};

		a53_1: cpu@101 {
			compatible = "arm,cortex-a53";
			reg = <0x101>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_1>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <535>;
		};

		a53_2: cpu@102 {
			compatible = "arm,cortex-a53";
			reg = <0x102>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_1>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <535>;
		};

		a53_3: cpu@103 {
			compatible = "arm,cortex-a53";
			reg = <0x103>;
			device_type = "cpu";
			power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
			next-level-cache = <&L2_CA53>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_1>;
			clocks = <&cpg CPG_CORE R8A7796_CLK_Z2>;
			operating-points-v2 = <&cluster1_opp>;
			capacity-dmips-mhz = <535>;
		};

		L2_CA57: cache-controller-0 {
			compatible = "cache";
			power-domains = <&sysc R8A7796_PD_CA57_SCU>;
			cache-unified;
			cache-level = <2>;
		};

		L2_CA53: cache-controller-1 {
			compatible = "cache";
			power-domains = <&sysc R8A7796_PD_CA53_SCU>;
			cache-unified;
			cache-level = <2>;
		};

		idle-states {
			entry-method = "psci";

			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <400>;
				exit-latency-us = <500>;
				min-residency-us = <4000>;
			};

			CPU_SLEEP_1: cpu-sleep-1 {
				compatible = "arm,idle-state";
				arm,psci-suspend-param = <0x0010000>;
				local-timer-stop;
				entry-latency-us = <700>;
				exit-latency-us = <700>;
				min-residency-us = <5000>;
			};
		};
	};

	extal_clk: extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	extalr_clk: extalr {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	/* External PCIe clock - can be overridden by the board */
	pcie_bus_clk: pcie_bus {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	pmu_a53 {
		compatible = "arm,cortex-a53-pmu";
		interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
	};

	pmu_a57 {
		compatible = "arm,cortex-a57-pmu";
		interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
				      <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&a57_0>, <&a57_1>;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	/* External SCIF clock - to be overridden by boards that provide it */
	scif_clk: scif {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	soc {
		compatible = "simple-bus";
		interrupt-parent = <&gic>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rwdt: watchdog@e6020000 {
			compatible = "renesas,r8a7796-wdt",
				     "renesas,rcar-gen3-wdt";
			reg = <0 0xe6020000 0 0x0c>;
			clocks = <&cpg CPG_MOD 402>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 402>;
			status = "disabled";
		};

		gpio0: gpio@e6050000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6050000 0 0x50>;
			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 0 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 912>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 912>;
		};

		gpio1: gpio@e6051000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6051000 0 0x50>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 32 29>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 911>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 911>;
		};

		gpio2: gpio@e6052000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6052000 0 0x50>;
			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 64 15>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 910>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 910>;
		};

		gpio3: gpio@e6053000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6053000 0 0x50>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 96 16>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 909>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 909>;
		};

		gpio4: gpio@e6054000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6054000 0 0x50>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 128 18>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 908>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 908>;
		};

		gpio5: gpio@e6055000 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055000 0 0x50>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 160 26>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 907>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 907>;
		};

		gpio6: gpio@e6055400 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055400 0 0x50>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 192 32>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 906>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 906>;
		};

		gpio7: gpio@e6055800 {
			compatible = "renesas,gpio-r8a7796",
				     "renesas,rcar-gen3-gpio";
			reg = <0 0xe6055800 0 0x50>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			#gpio-cells = <2>;
			gpio-controller;
			gpio-ranges = <&pfc 0 224 4>;
			#interrupt-cells = <2>;
			interrupt-controller;
			clocks = <&cpg CPG_MOD 905>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 905>;
		};

		pfc: pinctrl@e6060000 {
			compatible = "renesas,pfc-r8a7796";
			reg = <0 0xe6060000 0 0x50c>;
		};

		cmt0: timer@e60f0000 {
			compatible = "renesas,r8a7796-cmt0",
				     "renesas,rcar-gen3-cmt0";
			reg = <0 0xe60f0000 0 0x1004>;
			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 303>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 303>;
			status = "disabled";
		};

		cmt1: timer@e6130000 {
			compatible = "renesas,r8a7796-cmt1",
				     "renesas,rcar-gen3-cmt1";
			reg = <0 0xe6130000 0 0x1004>;
			interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 302>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 302>;
			status = "disabled";
		};

		cmt2: timer@e6140000 {
			compatible = "renesas,r8a7796-cmt1",
				     "renesas,rcar-gen3-cmt1";
			reg = <0 0xe6140000 0 0x1004>;
			interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 301>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 301>;
			status = "disabled";
		};

		cmt3: timer@e6148000 {
			compatible = "renesas,r8a7796-cmt1",
				     "renesas,rcar-gen3-cmt1";
			reg = <0 0xe6148000 0 0x1004>;
			interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 300>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 300>;
			status = "disabled";
		};

		cpg: clock-controller@e6150000 {
			compatible = "renesas,r8a7796-cpg-mssr";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>, <&extalr_clk>;
			clock-names = "extal", "extalr";
			#clock-cells = <2>;
			#power-domain-cells = <0>;
			#reset-cells = <1>;
		};

		rst: reset-controller@e6160000 {
			compatible = "renesas,r8a7796-rst";
			reg = <0 0xe6160000 0 0x0200>;
		};

		sysc: system-controller@e6180000 {
			compatible = "renesas,r8a7796-sysc";
			reg = <0 0xe6180000 0 0x0400>;
			#power-domain-cells = <1>;
		};

		tsc: thermal@e6198000 {
			compatible = "renesas,r8a7796-thermal";
			reg = <0 0xe6198000 0 0x100>,
			      <0 0xe61a0000 0 0x100>,
			      <0 0xe61a8000 0 0x100>;
			interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 522>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 522>;
			#thermal-sensor-cells = <1>;
		};

		intc_ex: interrupt-controller@e61c0000 {
			compatible = "renesas,intc-ex-r8a7796", "renesas,irqc";
			#interrupt-cells = <2>;
			interrupt-controller;
			reg = <0 0xe61c0000 0 0x200>;
			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 407>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 407>;
		};

		tmu0: timer@e61e0000 {
			compatible = "renesas,tmu-r8a7796", "renesas,tmu";
			reg = <0 0xe61e0000 0 0x30>;
			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 125>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 125>;
			status = "disabled";
		};

		tmu1: timer@e6fc0000 {
			compatible = "renesas,tmu-r8a7796", "renesas,tmu";
			reg = <0 0xe6fc0000 0 0x30>;
			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 124>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 124>;
			status = "disabled";
		};

		tmu2: timer@e6fd0000 {
			compatible = "renesas,tmu-r8a7796", "renesas,tmu";
			reg = <0 0xe6fd0000 0 0x30>;
			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 123>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 123>;
			status = "disabled";
		};

		tmu3: timer@e6fe0000 {
			compatible = "renesas,tmu-r8a7796", "renesas,tmu";
			reg = <0 0xe6fe0000 0 0x30>;
			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 122>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 122>;
			status = "disabled";
		};

		tmu4: timer@ffc00000 {
			compatible = "renesas,tmu-r8a7796", "renesas,tmu";
			reg = <0 0xffc00000 0 0x30>;
			interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 121>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 121>;
			status = "disabled";
		};

		i2c0: i2c@e6500000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6500000 0 0x40>;
			interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 931>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 931>;
			dmas = <&dmac1 0x91>, <&dmac1 0x90>,
			       <&dmac2 0x91>, <&dmac2 0x90>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		i2c1: i2c@e6508000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6508000 0 0x40>;
			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 930>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 930>;
			dmas = <&dmac1 0x93>, <&dmac1 0x92>,
			       <&dmac2 0x93>, <&dmac2 0x92>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c2: i2c@e6510000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe6510000 0 0x40>;
			interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 929>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 929>;
			dmas = <&dmac1 0x95>, <&dmac1 0x94>,
			       <&dmac2 0x95>, <&dmac2 0x94>;
			dma-names = "tx", "rx", "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c3: i2c@e66d0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe66d0000 0 0x40>;
			interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 928>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 928>;
			dmas = <&dmac0 0x97>, <&dmac0 0x96>;
			dma-names = "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		i2c4: i2c@e66d8000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe66d8000 0 0x40>;
			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 927>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 927>;
			dmas = <&dmac0 0x99>, <&dmac0 0x98>;
			dma-names = "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		i2c5: i2c@e66e0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe66e0000 0 0x40>;
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 919>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 919>;
			dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
			dma-names = "tx", "rx";
			i2c-scl-internal-delay-ns = <110>;
			status = "disabled";
		};

		i2c6: i2c@e66e8000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,i2c-r8a7796",
				     "renesas,rcar-gen3-i2c";
			reg = <0 0xe66e8000 0 0x40>;
			interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 918>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 918>;
			dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
			dma-names = "tx", "rx";
			i2c-scl-internal-delay-ns = <6>;
			status = "disabled";
		};

		i2c_dvfs: i2c@e60b0000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,iic-r8a7796",
				     "renesas,rcar-gen3-iic",
				     "renesas,rmobile-iic";
			reg = <0 0xe60b0000 0 0x425>;
			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 926>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 926>;
			dmas = <&dmac0 0x11>, <&dmac0 0x10>;
			dma-names = "tx", "rx";
			status = "disabled";
		};

		hscif0: serial@e6540000 {
			compatible = "renesas,hscif-r8a7796",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6540000 0 0x60>;
			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 520>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x31>, <&dmac1 0x30>,
			       <&dmac2 0x31>, <&dmac2 0x30>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 520>;
			status = "disabled";
		};

		hscif1: serial@e6550000 {
			compatible = "renesas,hscif-r8a7796",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6550000 0 0x60>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 519>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x33>, <&dmac1 0x32>,
			       <&dmac2 0x33>, <&dmac2 0x32>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 519>;
			status = "disabled";
		};

		hscif2: serial@e6560000 {
			compatible = "renesas,hscif-r8a7796",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe6560000 0 0x60>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 518>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x35>, <&dmac1 0x34>,
			       <&dmac2 0x35>, <&dmac2 0x34>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 518>;
			status = "disabled";
		};

		hscif3: serial@e66a0000 {
			compatible = "renesas,hscif-r8a7796",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe66a0000 0 0x60>;
			interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 517>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x37>, <&dmac0 0x36>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 517>;
			status = "disabled";
		};

		hscif4: serial@e66b0000 {
			compatible = "renesas,hscif-r8a7796",
				     "renesas,rcar-gen3-hscif",
				     "renesas,hscif";
			reg = <0 0xe66b0000 0 0x60>;
			interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 516>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x39>, <&dmac0 0x38>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 516>;
			status = "disabled";
		};

		hsusb: usb@e6590000 {
			compatible = "renesas,usbhs-r8a7796",
				     "renesas,rcar-gen3-usbhs";
			reg = <0 0xe6590000 0 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
			dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
			       <&usb_dmac1 0>, <&usb_dmac1 1>;
			dma-names = "ch0", "ch1", "ch2", "ch3";
			renesas,buswait = <11>;
			phys = <&usb2_phy0 3>;
			phy-names = "usb";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 704>, <&cpg 703>;
			status = "disabled";
		};

		usb_dmac0: dma-controller@e65a0000 {
			compatible = "renesas,r8a7796-usb-dmac",
				     "renesas,usb-dmac";
			reg = <0 0xe65a0000 0 0x100>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1";
			clocks = <&cpg CPG_MOD 330>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 330>;
			#dma-cells = <1>;
			dma-channels = <2>;
		};

		usb_dmac1: dma-controller@e65b0000 {
			compatible = "renesas,r8a7796-usb-dmac",
				     "renesas,usb-dmac";
			reg = <0 0xe65b0000 0 0x100>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1";
			clocks = <&cpg CPG_MOD 331>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 331>;
			#dma-cells = <1>;
			dma-channels = <2>;
		};

		usb3_phy0: usb-phy@e65ee000 {
			compatible = "renesas,r8a7796-usb3-phy",
				     "renesas,rcar-gen3-usb3-phy";
			reg = <0 0xe65ee000 0 0x90>;
			clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>,
				 <&usb_extal_clk>;
			clock-names = "usb3-if", "usb3s_clk", "usb_extal";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 328>;
			#phy-cells = <0>;
			status = "disabled";
		};

		arm_cc630p: crypto@e6601000 {
			compatible = "arm,cryptocell-630p-ree";
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x0 0xe6601000 0 0x1000>;
			clocks = <&cpg CPG_MOD 229>;
			resets = <&cpg 229>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
		};

		dmac0: dma-controller@e6700000 {
			compatible = "renesas,dmac-r8a7796",
				     "renesas,rcar-dmac";
			reg = <0 0xe6700000 0 0x10000>;
			interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 219>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 219>;
			#dma-cells = <1>;
			dma-channels = <16>;
			iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
			       <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
			       <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
			       <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
			       <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
			       <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
			       <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
			       <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
		};

		dmac1: dma-controller@e7300000 {
			compatible = "renesas,dmac-r8a7796",
				     "renesas,rcar-dmac";
			reg = <0 0xe7300000 0 0x10000>;
			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 218>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 218>;
			#dma-cells = <1>;
			dma-channels = <16>;
			iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
			       <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
			       <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
			       <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
			       <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
			       <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
			       <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
			       <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
		};

		dmac2: dma-controller@e7310000 {
			compatible = "renesas,dmac-r8a7796",
				     "renesas,rcar-dmac";
			reg = <0 0xe7310000 0 0x10000>;
			interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 217>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 217>;
			#dma-cells = <1>;
			dma-channels = <16>;
			iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
			       <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
			       <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
			       <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
			       <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
			       <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
			       <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
			       <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
		};

		ipmmu_ds0: iommu@e6740000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xe6740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 0>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_ds1: iommu@e7740000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xe7740000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 1>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_hc: iommu@e6570000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xe6570000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 2>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_ir: iommu@ff8b0000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xff8b0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 3>;
			power-domains = <&sysc R8A7796_PD_A3IR>;
			#iommu-cells = <1>;
		};

		ipmmu_mm: iommu@e67b0000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xe67b0000 0 0x1000>;
			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_mp: iommu@ec670000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xec670000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 4>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_pv0: iommu@fd800000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xfd800000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 5>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_pv1: iommu@fd950000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xfd950000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 6>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_rt: iommu@ffc80000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xffc80000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 7>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		ipmmu_vc0: iommu@fe6b0000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xfe6b0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 8>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			#iommu-cells = <1>;
		};

		ipmmu_vi0: iommu@febd0000 {
			compatible = "renesas,ipmmu-r8a7796";
			reg = <0 0xfebd0000 0 0x1000>;
			renesas,ipmmu-main = <&ipmmu_mm 9>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			#iommu-cells = <1>;
		};

		avb: ethernet@e6800000 {
			compatible = "renesas,etheravb-r8a7796",
				     "renesas,etheravb-rcar-gen3";
			reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15",
					  "ch16", "ch17", "ch18", "ch19",
					  "ch20", "ch21", "ch22", "ch23",
					  "ch24";
			clocks = <&cpg CPG_MOD 812>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 812>;
			phy-mode = "rgmii";
			rx-internal-delay-ps = <0>;
			tx-internal-delay-ps = <0>;
			iommus = <&ipmmu_ds0 16>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		can0: can@e6c30000 {
			compatible = "renesas,can-r8a7796",
				     "renesas,rcar-gen3-can";
			reg = <0 0xe6c30000 0 0x1000>;
			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 916>,
			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 916>;
			status = "disabled";
		};

		can1: can@e6c38000 {
			compatible = "renesas,can-r8a7796",
				     "renesas,rcar-gen3-can";
			reg = <0 0xe6c38000 0 0x1000>;
			interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 915>,
			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "clkp1", "clkp2", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 915>;
			status = "disabled";
		};

		canfd: can@e66c0000 {
			compatible = "renesas,r8a7796-canfd",
				     "renesas,rcar-gen3-canfd";
			reg = <0 0xe66c0000 0 0x8000>;
			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
				   <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 914>,
			       <&cpg CPG_CORE R8A7796_CLK_CANFD>,
			       <&can_clk>;
			clock-names = "fck", "canfd", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;
			assigned-clock-rates = <40000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 914>;
			status = "disabled";

			channel0 {
				status = "disabled";
			};

			channel1 {
				status = "disabled";
			};
		};

		pwm0: pwm@e6e30000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e30000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm1: pwm@e6e31000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e31000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm2: pwm@e6e32000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e32000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm3: pwm@e6e33000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e33000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm4: pwm@e6e34000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e34000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm5: pwm@e6e35000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e35000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		pwm6: pwm@e6e36000 {
			compatible = "renesas,pwm-r8a7796", "renesas,pwm-rcar";
			reg = <0 0xe6e36000 0 8>;
			#pwm-cells = <2>;
			clocks = <&cpg CPG_MOD 523>;
			resets = <&cpg 523>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			status = "disabled";
		};

		scif0: serial@e6e60000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e60000 0 64>;
			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 207>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x51>, <&dmac1 0x50>,
			       <&dmac2 0x51>, <&dmac2 0x50>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 207>;
			status = "disabled";
		};

		scif1: serial@e6e68000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e68000 0 64>;
			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 206>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x53>, <&dmac1 0x52>,
			       <&dmac2 0x53>, <&dmac2 0x52>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 206>;
			status = "disabled";
		};

		scif2: serial@e6e88000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6e88000 0 64>;
			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 310>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x13>, <&dmac1 0x12>,
			       <&dmac2 0x13>, <&dmac2 0x12>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 310>;
			status = "disabled";
		};

		scif3: serial@e6c50000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6c50000 0 64>;
			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 204>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x57>, <&dmac0 0x56>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 204>;
			status = "disabled";
		};

		scif4: serial@e6c40000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6c40000 0 64>;
			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 203>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac0 0x59>, <&dmac0 0x58>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 203>;
			status = "disabled";
		};

		scif5: serial@e6f30000 {
			compatible = "renesas,scif-r8a7796",
				     "renesas,rcar-gen3-scif", "renesas,scif";
			reg = <0 0xe6f30000 0 64>;
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 202>,
				 <&cpg CPG_CORE R8A7796_CLK_S3D1>,
				 <&scif_clk>;
			clock-names = "fck", "brg_int", "scif_clk";
			dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
			       <&dmac2 0x5b>, <&dmac2 0x5a>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 202>;
			status = "disabled";
		};

		tpu: pwm@e6e80000 {
			compatible = "renesas,tpu-r8a7796", "renesas,tpu";
			reg = <0 0xe6e80000 0 0x148>;
			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 304>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 304>;
			#pwm-cells = <3>;
			status = "disabled";
		};

		msiof0: spi@e6e90000 {
			compatible = "renesas,msiof-r8a7796",
				     "renesas,rcar-gen3-msiof";
			reg = <0 0xe6e90000 0 0x0064>;
			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 211>;
			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
			       <&dmac2 0x41>, <&dmac2 0x40>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 211>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof1: spi@e6ea0000 {
			compatible = "renesas,msiof-r8a7796",
				     "renesas,rcar-gen3-msiof";
			reg = <0 0xe6ea0000 0 0x0064>;
			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 210>;
			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
			       <&dmac2 0x43>, <&dmac2 0x42>;
			dma-names = "tx", "rx", "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 210>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof2: spi@e6c00000 {
			compatible = "renesas,msiof-r8a7796",
				     "renesas,rcar-gen3-msiof";
			reg = <0 0xe6c00000 0 0x0064>;
			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 209>;
			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 209>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		msiof3: spi@e6c10000 {
			compatible = "renesas,msiof-r8a7796",
				     "renesas,rcar-gen3-msiof";
			reg = <0 0xe6c10000 0 0x0064>;
			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 208>;
			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
			dma-names = "tx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 208>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		vin0: video@e6ef0000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef0000 0 0x1000>;
			interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 811>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 811>;
			renesas,id = <0>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin0csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin0>;
					};
					vin0csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin0>;
					};
				};
			};
		};

		vin1: video@e6ef1000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef1000 0 0x1000>;
			interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 810>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 810>;
			renesas,id = <1>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin1csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin1>;
					};
					vin1csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin1>;
					};
				};
			};
		};

		vin2: video@e6ef2000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef2000 0 0x1000>;
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 809>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 809>;
			renesas,id = <2>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin2csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin2>;
					};
					vin2csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin2>;
					};
				};
			};
		};

		vin3: video@e6ef3000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef3000 0 0x1000>;
			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 808>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 808>;
			renesas,id = <3>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin3csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin3>;
					};
					vin3csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin3>;
					};
				};
			};
		};

		vin4: video@e6ef4000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef4000 0 0x1000>;
			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 807>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 807>;
			renesas,id = <4>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin4csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin4>;
					};
					vin4csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin4>;
					};
				};
			};
		};

		vin5: video@e6ef5000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef5000 0 0x1000>;
			interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 806>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 806>;
			renesas,id = <5>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin5csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin5>;
					};
					vin5csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin5>;
					};
				};
			};
		};

		vin6: video@e6ef6000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef6000 0 0x1000>;
			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 805>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 805>;
			renesas,id = <6>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin6csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin6>;
					};
					vin6csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin6>;
					};
				};
			};
		};

		vin7: video@e6ef7000 {
			compatible = "renesas,vin-r8a7796";
			reg = <0 0xe6ef7000 0 0x1000>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 804>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 804>;
			renesas,id = <7>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					vin7csi20: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&csi20vin7>;
					};
					vin7csi40: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&csi40vin7>;
					};
				};
			};
		};

		drif00: rif@e6f40000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f40000 0 0x64>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 515>;
			clock-names = "fck";
			dmas = <&dmac1 0x20>, <&dmac2 0x20>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 515>;
			renesas,bonding = <&drif01>;
			status = "disabled";
		};

		drif01: rif@e6f50000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f50000 0 0x64>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 514>;
			clock-names = "fck";
			dmas = <&dmac1 0x22>, <&dmac2 0x22>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 514>;
			renesas,bonding = <&drif00>;
			status = "disabled";
		};

		drif10: rif@e6f60000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f60000 0 0x64>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 513>;
			clock-names = "fck";
			dmas = <&dmac1 0x24>, <&dmac2 0x24>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 513>;
			renesas,bonding = <&drif11>;
			status = "disabled";
		};

		drif11: rif@e6f70000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f70000 0 0x64>;
			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 512>;
			clock-names = "fck";
			dmas = <&dmac1 0x26>, <&dmac2 0x26>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 512>;
			renesas,bonding = <&drif10>;
			status = "disabled";
		};

		drif20: rif@e6f80000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f80000 0 0x64>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 511>;
			clock-names = "fck";
			dmas = <&dmac1 0x28>, <&dmac2 0x28>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 511>;
			renesas,bonding = <&drif21>;
			status = "disabled";
		};

		drif21: rif@e6f90000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6f90000 0 0x64>;
			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 510>;
			clock-names = "fck";
			dmas = <&dmac1 0x2a>, <&dmac2 0x2a>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 510>;
			renesas,bonding = <&drif20>;
			status = "disabled";
		};

		drif30: rif@e6fa0000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6fa0000 0 0x64>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 509>;
			clock-names = "fck";
			dmas = <&dmac1 0x2c>, <&dmac2 0x2c>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 509>;
			renesas,bonding = <&drif31>;
			status = "disabled";
		};

		drif31: rif@e6fb0000 {
			compatible = "renesas,r8a7796-drif",
				     "renesas,rcar-gen3-drif";
			reg = <0 0xe6fb0000 0 0x64>;
			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 508>;
			clock-names = "fck";
			dmas = <&dmac1 0x2e>, <&dmac2 0x2e>;
			dma-names = "rx", "rx";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 508>;
			renesas,bonding = <&drif30>;
			status = "disabled";
		};

		rcar_sound: sound@ec500000 {
			/*
			 * #sound-dai-cells is required
			 *
			 * Single DAI : #sound-dai-cells = <0>;	<&rcar_sound>;
			 * Multi  DAI : #sound-dai-cells = <1>;	<&rcar_sound N>;
			 */
			/*
			 * #clock-cells is required for audio_clkout0/1/2/3
			 *
			 * clkout	: #clock-cells = <0>;	<&rcar_sound>;
			 * clkout0/1/2/3: #clock-cells = <1>;	<&rcar_sound N>;
			 */
			compatible =  "renesas,rcar_sound-r8a7796", "renesas,rcar_sound-gen3";
			reg =	<0 0xec500000 0 0x1000>, /* SCU */
				<0 0xec5a0000 0 0x100>,  /* ADG */
				<0 0xec540000 0 0x1000>, /* SSIU */
				<0 0xec541000 0 0x280>,  /* SSI */
				<0 0xec760000 0 0x200>;  /* Audio DMAC peri peri*/
			reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";

			clocks = <&cpg CPG_MOD 1005>,
				 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
				 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
				 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
				 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
				 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
				 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
				 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
				 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
				 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
				 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
				 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
				 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
				 <&audio_clk_a>, <&audio_clk_b>,
				 <&audio_clk_c>,
				 <&cpg CPG_CORE R8A7796_CLK_S0D4>;
			clock-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0",
				      "src.9", "src.8", "src.7", "src.6",
				      "src.5", "src.4", "src.3", "src.2",
				      "src.1", "src.0",
				      "mix.1", "mix.0",
				      "ctu.1", "ctu.0",
				      "dvc.0", "dvc.1",
				      "clk_a", "clk_b", "clk_c", "clk_i";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 1005>,
				 <&cpg 1006>, <&cpg 1007>,
				 <&cpg 1008>, <&cpg 1009>,
				 <&cpg 1010>, <&cpg 1011>,
				 <&cpg 1012>, <&cpg 1013>,
				 <&cpg 1014>, <&cpg 1015>;
			reset-names = "ssi-all",
				      "ssi.9", "ssi.8", "ssi.7", "ssi.6",
				      "ssi.5", "ssi.4", "ssi.3", "ssi.2",
				      "ssi.1", "ssi.0";
			status = "disabled";

			rcar_sound,ctu {
				ctu00: ctu-0 { };
				ctu01: ctu-1 { };
				ctu02: ctu-2 { };
				ctu03: ctu-3 { };
				ctu10: ctu-4 { };
				ctu11: ctu-5 { };
				ctu12: ctu-6 { };
				ctu13: ctu-7 { };
			};

			rcar_sound,dvc {
				dvc0: dvc-0 {
					dmas = <&audma1 0xbc>;
					dma-names = "tx";
				};
				dvc1: dvc-1 {
					dmas = <&audma1 0xbe>;
					dma-names = "tx";
				};
			};

			rcar_sound,mix {
				mix0: mix-0 { };
				mix1: mix-1 { };
			};

			rcar_sound,src {
				src0: src-0 {
					interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x85>, <&audma1 0x9a>;
					dma-names = "rx", "tx";
				};
				src1: src-1 {
					interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x87>, <&audma1 0x9c>;
					dma-names = "rx", "tx";
				};
				src2: src-2 {
					interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x89>, <&audma1 0x9e>;
					dma-names = "rx", "tx";
				};
				src3: src-3 {
					interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8b>, <&audma1 0xa0>;
					dma-names = "rx", "tx";
				};
				src4: src-4 {
					interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8d>, <&audma1 0xb0>;
					dma-names = "rx", "tx";
				};
				src5: src-5 {
					interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x8f>, <&audma1 0xb2>;
					dma-names = "rx", "tx";
				};
				src6: src-6 {
					interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x91>, <&audma1 0xb4>;
					dma-names = "rx", "tx";
				};
				src7: src-7 {
					interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x93>, <&audma1 0xb6>;
					dma-names = "rx", "tx";
				};
				src8: src-8 {
					interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x95>, <&audma1 0xb8>;
					dma-names = "rx", "tx";
				};
				src9: src-9 {
					interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x97>, <&audma1 0xba>;
					dma-names = "rx", "tx";
				};
			};

			rcar_sound,ssi {
				ssi0: ssi-0 {
					interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x01>, <&audma1 0x02>;
					dma-names = "rx", "tx";
				};
				ssi1: ssi-1 {
					interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x03>, <&audma1 0x04>;
					dma-names = "rx", "tx";
				};
				ssi2: ssi-2 {
					interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x05>, <&audma1 0x06>;
					dma-names = "rx", "tx";
				};
				ssi3: ssi-3 {
					interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x07>, <&audma1 0x08>;
					dma-names = "rx", "tx";
				};
				ssi4: ssi-4 {
					interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x09>, <&audma1 0x0a>;
					dma-names = "rx", "tx";
				};
				ssi5: ssi-5 {
					interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0b>, <&audma1 0x0c>;
					dma-names = "rx", "tx";
				};
				ssi6: ssi-6 {
					interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0d>, <&audma1 0x0e>;
					dma-names = "rx", "tx";
				};
				ssi7: ssi-7 {
					interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x0f>, <&audma1 0x10>;
					dma-names = "rx", "tx";
				};
				ssi8: ssi-8 {
					interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x11>, <&audma1 0x12>;
					dma-names = "rx", "tx";
				};
				ssi9: ssi-9 {
					interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
					dmas = <&audma0 0x13>, <&audma1 0x14>;
					dma-names = "rx", "tx";
				};
			};

			rcar_sound,ssiu {
				ssiu00: ssiu-0 {
					dmas = <&audma0 0x15>, <&audma1 0x16>;
					dma-names = "rx", "tx";
				};
				ssiu01: ssiu-1 {
					dmas = <&audma0 0x35>, <&audma1 0x36>;
					dma-names = "rx", "tx";
				};
				ssiu02: ssiu-2 {
					dmas = <&audma0 0x37>, <&audma1 0x38>;
					dma-names = "rx", "tx";
				};
				ssiu03: ssiu-3 {
					dmas = <&audma0 0x47>, <&audma1 0x48>;
					dma-names = "rx", "tx";
				};
				ssiu04: ssiu-4 {
					dmas = <&audma0 0x3F>, <&audma1 0x40>;
					dma-names = "rx", "tx";
				};
				ssiu05: ssiu-5 {
					dmas = <&audma0 0x43>, <&audma1 0x44>;
					dma-names = "rx", "tx";
				};
				ssiu06: ssiu-6 {
					dmas = <&audma0 0x4F>, <&audma1 0x50>;
					dma-names = "rx", "tx";
				};
				ssiu07: ssiu-7 {
					dmas = <&audma0 0x53>, <&audma1 0x54>;
					dma-names = "rx", "tx";
				};
				ssiu10: ssiu-8 {
					dmas = <&audma0 0x49>, <&audma1 0x4a>;
					dma-names = "rx", "tx";
				};
				ssiu11: ssiu-9 {
					dmas = <&audma0 0x4B>, <&audma1 0x4C>;
					dma-names = "rx", "tx";
				};
				ssiu12: ssiu-10 {
					dmas = <&audma0 0x57>, <&audma1 0x58>;
					dma-names = "rx", "tx";
				};
				ssiu13: ssiu-11 {
					dmas = <&audma0 0x59>, <&audma1 0x5A>;
					dma-names = "rx", "tx";
				};
				ssiu14: ssiu-12 {
					dmas = <&audma0 0x5F>, <&audma1 0x60>;
					dma-names = "rx", "tx";
				};
				ssiu15: ssiu-13 {
					dmas = <&audma0 0xC3>, <&audma1 0xC4>;
					dma-names = "rx", "tx";
				};
				ssiu16: ssiu-14 {
					dmas = <&audma0 0xC7>, <&audma1 0xC8>;
					dma-names = "rx", "tx";
				};
				ssiu17: ssiu-15 {
					dmas = <&audma0 0xCB>, <&audma1 0xCC>;
					dma-names = "rx", "tx";
				};
				ssiu20: ssiu-16 {
					dmas = <&audma0 0x63>, <&audma1 0x64>;
					dma-names = "rx", "tx";
				};
				ssiu21: ssiu-17 {
					dmas = <&audma0 0x67>, <&audma1 0x68>;
					dma-names = "rx", "tx";
				};
				ssiu22: ssiu-18 {
					dmas = <&audma0 0x6B>, <&audma1 0x6C>;
					dma-names = "rx", "tx";
				};
				ssiu23: ssiu-19 {
					dmas = <&audma0 0x6D>, <&audma1 0x6E>;
					dma-names = "rx", "tx";
				};
				ssiu24: ssiu-20 {
					dmas = <&audma0 0xCF>, <&audma1 0xCE>;
					dma-names = "rx", "tx";
				};
				ssiu25: ssiu-21 {
					dmas = <&audma0 0xEB>, <&audma1 0xEC>;
					dma-names = "rx", "tx";
				};
				ssiu26: ssiu-22 {
					dmas = <&audma0 0xED>, <&audma1 0xEE>;
					dma-names = "rx", "tx";
				};
				ssiu27: ssiu-23 {
					dmas = <&audma0 0xEF>, <&audma1 0xF0>;
					dma-names = "rx", "tx";
				};
				ssiu30: ssiu-24 {
					dmas = <&audma0 0x6f>, <&audma1 0x70>;
					dma-names = "rx", "tx";
				};
				ssiu31: ssiu-25 {
					dmas = <&audma0 0x21>, <&audma1 0x22>;
					dma-names = "rx", "tx";
				};
				ssiu32: ssiu-26 {
					dmas = <&audma0 0x23>, <&audma1 0x24>;
					dma-names = "rx", "tx";
				};
				ssiu33: ssiu-27 {
					dmas = <&audma0 0x25>, <&audma1 0x26>;
					dma-names = "rx", "tx";
				};
				ssiu34: ssiu-28 {
					dmas = <&audma0 0x27>, <&audma1 0x28>;
					dma-names = "rx", "tx";
				};
				ssiu35: ssiu-29 {
					dmas = <&audma0 0x29>, <&audma1 0x2A>;
					dma-names = "rx", "tx";
				};
				ssiu36: ssiu-30 {
					dmas = <&audma0 0x2B>, <&audma1 0x2C>;
					dma-names = "rx", "tx";
				};
				ssiu37: ssiu-31 {
					dmas = <&audma0 0x2D>, <&audma1 0x2E>;
					dma-names = "rx", "tx";
				};
				ssiu40: ssiu-32 {
					dmas =	<&audma0 0x71>, <&audma1 0x72>;
					dma-names = "rx", "tx";
				};
				ssiu41: ssiu-33 {
					dmas = <&audma0 0x17>, <&audma1 0x18>;
					dma-names = "rx", "tx";
				};
				ssiu42: ssiu-34 {
					dmas = <&audma0 0x19>, <&audma1 0x1A>;
					dma-names = "rx", "tx";
				};
				ssiu43: ssiu-35 {
					dmas = <&audma0 0x1B>, <&audma1 0x1C>;
					dma-names = "rx", "tx";
				};
				ssiu44: ssiu-36 {
					dmas = <&audma0 0x1D>, <&audma1 0x1E>;
					dma-names = "rx", "tx";
				};
				ssiu45: ssiu-37 {
					dmas = <&audma0 0x1F>, <&audma1 0x20>;
					dma-names = "rx", "tx";
				};
				ssiu46: ssiu-38 {
					dmas = <&audma0 0x31>, <&audma1 0x32>;
					dma-names = "rx", "tx";
				};
				ssiu47: ssiu-39 {
					dmas = <&audma0 0x33>, <&audma1 0x34>;
					dma-names = "rx", "tx";
				};
				ssiu50: ssiu-40 {
					dmas = <&audma0 0x73>, <&audma1 0x74>;
					dma-names = "rx", "tx";
				};
				ssiu60: ssiu-41 {
					dmas = <&audma0 0x75>, <&audma1 0x76>;
					dma-names = "rx", "tx";
				};
				ssiu70: ssiu-42 {
					dmas = <&audma0 0x79>, <&audma1 0x7a>;
					dma-names = "rx", "tx";
				};
				ssiu80: ssiu-43 {
					dmas = <&audma0 0x7b>, <&audma1 0x7c>;
					dma-names = "rx", "tx";
				};
				ssiu90: ssiu-44 {
					dmas = <&audma0 0x7d>, <&audma1 0x7e>;
					dma-names = "rx", "tx";
				};
				ssiu91: ssiu-45 {
					dmas = <&audma0 0x7F>, <&audma1 0x80>;
					dma-names = "rx", "tx";
				};
				ssiu92: ssiu-46 {
					dmas = <&audma0 0x81>, <&audma1 0x82>;
					dma-names = "rx", "tx";
				};
				ssiu93: ssiu-47 {
					dmas = <&audma0 0x83>, <&audma1 0x84>;
					dma-names = "rx", "tx";
				};
				ssiu94: ssiu-48 {
					dmas = <&audma0 0xA3>, <&audma1 0xA4>;
					dma-names = "rx", "tx";
				};
				ssiu95: ssiu-49 {
					dmas = <&audma0 0xA5>, <&audma1 0xA6>;
					dma-names = "rx", "tx";
				};
				ssiu96: ssiu-50 {
					dmas = <&audma0 0xA7>, <&audma1 0xA8>;
					dma-names = "rx", "tx";
				};
				ssiu97: ssiu-51 {
					dmas = <&audma0 0xA9>, <&audma1 0xAA>;
					dma-names = "rx", "tx";
				};
			};
		};

		audma0: dma-controller@ec700000 {
			compatible = "renesas,dmac-r8a7796",
				     "renesas,rcar-dmac";
			reg = <0 0xec700000 0 0x10000>;
			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 502>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 502>;
			#dma-cells = <1>;
			dma-channels = <16>;
			iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
			       <&ipmmu_mp 2>, <&ipmmu_mp 3>,
			       <&ipmmu_mp 4>, <&ipmmu_mp 5>,
			       <&ipmmu_mp 6>, <&ipmmu_mp 7>,
			       <&ipmmu_mp 8>, <&ipmmu_mp 9>,
			       <&ipmmu_mp 10>, <&ipmmu_mp 11>,
			       <&ipmmu_mp 12>, <&ipmmu_mp 13>,
			       <&ipmmu_mp 14>, <&ipmmu_mp 15>;
		};

		audma1: dma-controller@ec720000 {
			compatible = "renesas,dmac-r8a7796",
				     "renesas,rcar-dmac";
			reg = <0 0xec720000 0 0x10000>;
			interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error",
					"ch0", "ch1", "ch2", "ch3",
					"ch4", "ch5", "ch6", "ch7",
					"ch8", "ch9", "ch10", "ch11",
					"ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD 501>;
			clock-names = "fck";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 501>;
			#dma-cells = <1>;
			dma-channels = <16>;
			iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>,
			       <&ipmmu_mp 18>, <&ipmmu_mp 19>,
			       <&ipmmu_mp 20>, <&ipmmu_mp 21>,
			       <&ipmmu_mp 22>, <&ipmmu_mp 23>,
			       <&ipmmu_mp 24>, <&ipmmu_mp 25>,
			       <&ipmmu_mp 26>, <&ipmmu_mp 27>,
			       <&ipmmu_mp 28>, <&ipmmu_mp 29>,
			       <&ipmmu_mp 30>, <&ipmmu_mp 31>;
		};

		xhci0: usb@ee000000 {
			compatible = "renesas,xhci-r8a7796",
				     "renesas,rcar-gen3-xhci";
			reg = <0 0xee000000 0 0xc00>;
			interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 328>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 328>;
			status = "disabled";
		};

		usb3_peri0: usb@ee020000 {
			compatible = "renesas,r8a7796-usb3-peri",
				     "renesas,rcar-gen3-usb3-peri";
			reg = <0 0xee020000 0 0x400>;
			interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 328>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 328>;
			status = "disabled";
		};

		ohci0: usb@ee080000 {
			compatible = "generic-ohci";
			reg = <0 0xee080000 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
			phys = <&usb2_phy0 1>;
			phy-names = "usb";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 703>, <&cpg 704>;
			status = "disabled";
		};

		ohci1: usb@ee0a0000 {
			compatible = "generic-ohci";
			reg = <0 0xee0a0000 0 0x100>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 702>;
			phys = <&usb2_phy1 1>;
			phy-names = "usb";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 702>;
			status = "disabled";
		};

		ehci0: usb@ee080100 {
			compatible = "generic-ehci";
			reg = <0 0xee080100 0 0x100>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
			phys = <&usb2_phy0 2>;
			phy-names = "usb";
			companion = <&ohci0>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 703>, <&cpg 704>;
			status = "disabled";
		};

		ehci1: usb@ee0a0100 {
			compatible = "generic-ehci";
			reg = <0 0xee0a0100 0 0x100>;
			interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 702>;
			phys = <&usb2_phy1 2>;
			phy-names = "usb";
			companion = <&ohci1>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 702>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@ee080200 {
			compatible = "renesas,usb2-phy-r8a7796",
				     "renesas,rcar-gen3-usb2-phy";
			reg = <0 0xee080200 0 0x700>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 703>, <&cpg 704>;
			#phy-cells = <1>;
			status = "disabled";
		};

		usb2_phy1: usb-phy@ee0a0200 {
			compatible = "renesas,usb2-phy-r8a7796",
				     "renesas,rcar-gen3-usb2-phy";
			reg = <0 0xee0a0200 0 0x700>;
			clocks = <&cpg CPG_MOD 702>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 702>;
			#phy-cells = <1>;
			status = "disabled";
		};

		sdhi0: mmc@ee100000 {
			compatible = "renesas,sdhi-r8a7796",
				     "renesas,rcar-gen3-sdhi";
			reg = <0 0xee100000 0 0x2000>;
			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 314>;
			max-frequency = <200000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 314>;
			iommus = <&ipmmu_ds1 32>;
			status = "disabled";
		};

		sdhi1: mmc@ee120000 {
			compatible = "renesas,sdhi-r8a7796",
				     "renesas,rcar-gen3-sdhi";
			reg = <0 0xee120000 0 0x2000>;
			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 313>;
			max-frequency = <200000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 313>;
			iommus = <&ipmmu_ds1 33>;
			status = "disabled";
		};

		sdhi2: mmc@ee140000 {
			compatible = "renesas,sdhi-r8a7796",
				     "renesas,rcar-gen3-sdhi";
			reg = <0 0xee140000 0 0x2000>;
			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 312>;
			max-frequency = <200000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 312>;
			iommus = <&ipmmu_ds1 34>;
			status = "disabled";
		};

		sdhi3: mmc@ee160000 {
			compatible = "renesas,sdhi-r8a7796",
				     "renesas,rcar-gen3-sdhi";
			reg = <0 0xee160000 0 0x2000>;
			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 311>;
			max-frequency = <200000000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 311>;
			iommus = <&ipmmu_ds1 35>;
			status = "disabled";
		};

		gic: interrupt-controller@f1010000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			#address-cells = <0>;
			interrupt-controller;
			reg = <0x0 0xf1010000 0 0x1000>,
			      <0x0 0xf1020000 0 0x20000>,
			      <0x0 0xf1040000 0 0x20000>,
			      <0x0 0xf1060000 0 0x20000>;
			interrupts = <GIC_PPI 9
					(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
			clocks = <&cpg CPG_MOD 408>;
			clock-names = "clk";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 408>;
		};

		pciec0: pcie@fe000000 {
			compatible = "renesas,pcie-r8a7796",
				     "renesas,pcie-rcar-gen3";
			reg = <0 0xfe000000 0 0x80000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			device_type = "pci";
			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
				 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
				 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
				 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
			/* Map all possible DDR as inbound ranges */
			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
			clock-names = "pcie", "pcie_bus";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 319>;
			status = "disabled";
		};

		pciec1: pcie@ee800000 {
			compatible = "renesas,pcie-r8a7796",
				     "renesas,pcie-rcar-gen3";
			reg = <0 0xee800000 0 0x80000>;
			#address-cells = <3>;
			#size-cells = <2>;
			bus-range = <0x00 0xff>;
			device_type = "pci";
			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>,
				 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
				 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
				 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
			/* Map all possible DDR as inbound ranges */
			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
			#interrupt-cells = <1>;
			interrupt-map-mask = <0 0 0 0>;
			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
			clock-names = "pcie", "pcie_bus";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 318>;
			status = "disabled";
		};

		imr-lx4@fe860000 {
			compatible = "renesas,r8a7796-imr-lx4",
				     "renesas,imr-lx4";
			reg = <0 0xfe860000 0 0x2000>;
			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 823>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 823>;
		};

		imr-lx4@fe870000 {
			compatible = "renesas,r8a7796-imr-lx4",
				     "renesas,imr-lx4";
			reg = <0 0xfe870000 0 0x2000>;
			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 822>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 822>;
		};

		fdp1@fe940000 {
			compatible = "renesas,fdp1";
			reg = <0 0xfe940000 0 0x2400>;
			interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 119>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 119>;
			renesas,fcp = <&fcpf0>;
		};

		fcpf0: fcp@fe950000 {
			compatible = "renesas,fcpf";
			reg = <0 0xfe950000 0 0x200>;
			clocks = <&cpg CPG_MOD 615>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 615>;
		};

		fcpvb0: fcp@fe96f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe96f000 0 0x200>;
			clocks = <&cpg CPG_MOD 607>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 607>;
		};

		fcpvi0: fcp@fe9af000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfe9af000 0 0x200>;
			clocks = <&cpg CPG_MOD 611>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 611>;
			iommus = <&ipmmu_vc0 19>;
		};

		fcpvd0: fcp@fea27000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea27000 0 0x200>;
			clocks = <&cpg CPG_MOD 603>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 603>;
			iommus = <&ipmmu_vi0 8>;
		};

		fcpvd1: fcp@fea2f000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea2f000 0 0x200>;
			clocks = <&cpg CPG_MOD 602>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 602>;
			iommus = <&ipmmu_vi0 9>;
		};

		fcpvd2: fcp@fea37000 {
			compatible = "renesas,fcpv";
			reg = <0 0xfea37000 0 0x200>;
			clocks = <&cpg CPG_MOD 601>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 601>;
			iommus = <&ipmmu_vi0 10>;
		};

		vspb: vsp@fe960000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfe960000 0 0x8000>;
			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 626>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 626>;

			renesas,fcp = <&fcpvb0>;
		};

		vspd0: vsp@fea20000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea20000 0 0x5000>;
			interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 623>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 623>;

			renesas,fcp = <&fcpvd0>;
		};

		vspd1: vsp@fea28000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea28000 0 0x5000>;
			interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 622>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 622>;

			renesas,fcp = <&fcpvd1>;
		};

		vspd2: vsp@fea30000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfea30000 0 0x5000>;
			interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 621>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 621>;

			renesas,fcp = <&fcpvd2>;
		};

		vspi0: vsp@fe9a0000 {
			compatible = "renesas,vsp2";
			reg = <0 0xfe9a0000 0 0x8000>;
			interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 631>;
			power-domains = <&sysc R8A7796_PD_A3VC>;
			resets = <&cpg 631>;

			renesas,fcp = <&fcpvi0>;
		};

		cmm0: cmm@fea40000 {
			compatible = "renesas,r8a7796-cmm",
				     "renesas,rcar-gen3-cmm";
			reg = <0 0xfea40000 0 0x1000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			clocks = <&cpg CPG_MOD 711>;
			resets = <&cpg 711>;
		};

		cmm1: cmm@fea50000 {
			compatible = "renesas,r8a7796-cmm",
				     "renesas,rcar-gen3-cmm";
			reg = <0 0xfea50000 0 0x1000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			clocks = <&cpg CPG_MOD 710>;
			resets = <&cpg 710>;
		};

		cmm2: cmm@fea60000 {
			compatible = "renesas,r8a7796-cmm",
				     "renesas,rcar-gen3-cmm";
			reg = <0 0xfea60000 0 0x1000>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			clocks = <&cpg CPG_MOD 709>;
			resets = <&cpg 709>;
		};

		csi20: csi2@fea80000 {
			compatible = "renesas,r8a7796-csi2";
			reg = <0 0xfea80000 0 0x10000>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 714>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 714>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
				};

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					csi20vin0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vin0csi20>;
					};
					csi20vin1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vin1csi20>;
					};
					csi20vin2: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&vin2csi20>;
					};
					csi20vin3: endpoint@3 {
						reg = <3>;
						remote-endpoint = <&vin3csi20>;
					};
					csi20vin4: endpoint@4 {
						reg = <4>;
						remote-endpoint = <&vin4csi20>;
					};
					csi20vin5: endpoint@5 {
						reg = <5>;
						remote-endpoint = <&vin5csi20>;
					};
					csi20vin6: endpoint@6 {
						reg = <6>;
						remote-endpoint = <&vin6csi20>;
					};
					csi20vin7: endpoint@7 {
						reg = <7>;
						remote-endpoint = <&vin7csi20>;
					};
				};
			};
		};

		csi40: csi2@feaa0000 {
			compatible = "renesas,r8a7796-csi2";
			reg = <0 0xfeaa0000 0 0x10000>;
			interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 716>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 716>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
				};

				port@1 {
					#address-cells = <1>;
					#size-cells = <0>;

					reg = <1>;

					csi40vin0: endpoint@0 {
						reg = <0>;
						remote-endpoint = <&vin0csi40>;
					};
					csi40vin1: endpoint@1 {
						reg = <1>;
						remote-endpoint = <&vin1csi40>;
					};
					csi40vin2: endpoint@2 {
						reg = <2>;
						remote-endpoint = <&vin2csi40>;
					};
					csi40vin3: endpoint@3 {
						reg = <3>;
						remote-endpoint = <&vin3csi40>;
					};
					csi40vin4: endpoint@4 {
						reg = <4>;
						remote-endpoint = <&vin4csi40>;
					};
					csi40vin5: endpoint@5 {
						reg = <5>;
						remote-endpoint = <&vin5csi40>;
					};
					csi40vin6: endpoint@6 {
						reg = <6>;
						remote-endpoint = <&vin6csi40>;
					};
					csi40vin7: endpoint@7 {
						reg = <7>;
						remote-endpoint = <&vin7csi40>;
					};
				};

			};
		};

		hdmi0: hdmi@fead0000 {
			compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
			reg = <0 0xfead0000 0 0x10000>;
			interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7796_CLK_HDMI>;
			clock-names = "iahb", "isfr";
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 729>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;
				port@0 {
					reg = <0>;
					dw_hdmi0_in: endpoint {
						remote-endpoint = <&du_out_hdmi0>;
					};
				};
				port@1 {
					reg = <1>;
				};
				port@2 {
					/* HDMI sound */
					reg = <2>;
				};
			};
		};

		du: display@feb00000 {
			compatible = "renesas,du-r8a7796";
			reg = <0 0xfeb00000 0 0x70000>;
			interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
				 <&cpg CPG_MOD 722>;
			clock-names = "du.0", "du.1", "du.2";
			resets = <&cpg 724>, <&cpg 722>;
			reset-names = "du.0", "du.2";

			renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>;
			renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					du_out_rgb: endpoint {
					};
				};
				port@1 {
					reg = <1>;
					du_out_hdmi0: endpoint {
						remote-endpoint = <&dw_hdmi0_in>;
					};
				};
				port@2 {
					reg = <2>;
					du_out_lvds0: endpoint {
						remote-endpoint = <&lvds0_in>;
					};
				};
			};
		};

		lvds0: lvds@feb90000 {
			compatible = "renesas,r8a7796-lvds";
			reg = <0 0xfeb90000 0 0x14>;
			clocks = <&cpg CPG_MOD 727>;
			power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
			resets = <&cpg 727>;
			status = "disabled";

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					lvds0_in: endpoint {
						remote-endpoint = <&du_out_lvds0>;
					};
				};
				port@1 {
					reg = <1>;
					lvds0_out: endpoint {
					};
				};
			};
		};

		prr: chipid@fff00044 {
			compatible = "renesas,prr";
			reg = <0 0xfff00044 0 4>;
		};
	};

	thermal-zones {
		sensor_thermal1: sensor-thermal1 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&tsc 0>;
			sustainable-power = <3874>;

			trips {
				sensor1_crit: sensor1-crit {
					temperature = <120000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		sensor_thermal2: sensor-thermal2 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&tsc 1>;
			sustainable-power = <3874>;

			trips {
				sensor2_crit: sensor2-crit {
					temperature = <120000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};

		sensor_thermal3: sensor-thermal3 {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&tsc 2>;
			sustainable-power = <3874>;

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&a57_0 2 4>;
					contribution = <1024>;
				};
				map1 {
					trip = <&target>;
					cooling-device = <&a53_0 0 2>;
					contribution = <1024>;
				};
			};
			trips {
				target: trip-point1 {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "passive";
				};

				sensor3_crit: sensor3-crit {
					temperature = <120000>;
					hysteresis = <1000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
	};

	/* External USB clocks - can be overridden by the board */
	usb3s0_clk: usb3s0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	usb_extal_clk: usb_extal {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};
};