path: root/sound/soc/codecs/abe/abe_cm_addr.h

/*
 * ==========================================================================
 *               Texas Instruments OMAP(TM) Platform Firmware
 * (c) Copyright 2009, Texas Instruments Incorporated.  All Rights Reserved.
 *
 *  Use of this firmware is controlled by the terms and conditions found
 *  in the license agreement under which this firmware has been supplied.
 * ==========================================================================
 */

#ifndef _ABE_CM_ADDR_H_
#define _ABE_CM_ADDR_H_

#define init_CM_ADDR			0
#define init_CM_ADDR_END		284
#define init_CM_sizeof			285

#define C_Data_LSB_2_ADDR		285
#define C_Data_LSB_2_ADDR_END		285
#define C_Data_LSB_2_sizeof		1

#define C_1_Alpha_ADDR			286
#define C_1_Alpha_ADDR_END		303
#define C_1_Alpha_sizeof		18

#define C_Alpha_ADDR			304
#define C_Alpha_ADDR_END		321
#define C_Alpha_sizeof			18

#define C_GainsWRamp_ADDR		322
#define C_GainsWRamp_ADDR_END		335
#define C_GainsWRamp_sizeof		14

#define C_Gains_DL1M_ADDR		336
#define C_Gains_DL1M_ADDR_END		339
#define C_Gains_DL1M_sizeof		4

#define C_Gains_DL2M_ADDR		340
#define C_Gains_DL2M_ADDR_END		343
#define C_Gains_DL2M_sizeof		4

#define C_Gains_EchoM_ADDR		344
#define C_Gains_EchoM_ADDR_END		345
#define C_Gains_EchoM_sizeof		2

#define C_Gains_SDTM_ADDR		346
#define C_Gains_SDTM_ADDR_END		347
#define C_Gains_SDTM_sizeof		2

#define C_Gains_VxRecM_ADDR		348
#define C_Gains_VxRecM_ADDR_END		351
#define C_Gains_VxRecM_sizeof		4

#define C_Gains_ULM_ADDR		352
#define C_Gains_ULM_ADDR_END		355
#define C_Gains_ULM_sizeof		4

#define C_Gains_unused_ADDR		356
#define C_Gains_unused_ADDR_END		357
#define C_Gains_unused_sizeof		2

#define C_SDT_Coefs_ADDR		358
#define C_SDT_Coefs_ADDR_END		366
#define C_SDT_Coefs_sizeof		9

#define C_CoefASRC1_VX_ADDR		367
#define C_CoefASRC1_VX_ADDR_END		385
#define C_CoefASRC1_VX_sizeof		19

#define C_CoefASRC2_VX_ADDR		386
#define C_CoefASRC2_VX_ADDR_END		404
#define C_CoefASRC2_VX_sizeof		19

#define C_CoefASRC3_VX_ADDR		405
#define C_CoefASRC3_VX_ADDR_END		423
#define C_CoefASRC3_VX_sizeof		19

#define C_CoefASRC4_VX_ADDR		424
#define C_CoefASRC4_VX_ADDR_END		442
#define C_CoefASRC4_VX_sizeof		19

#define C_CoefASRC5_VX_ADDR		443
#define C_CoefASRC5_VX_ADDR_END		461
#define C_CoefASRC5_VX_sizeof		19

#define C_CoefASRC6_VX_ADDR		462
#define C_CoefASRC6_VX_ADDR_END		480
#define C_CoefASRC6_VX_sizeof		19

#define C_CoefASRC7_VX_ADDR		481
#define C_CoefASRC7_VX_ADDR_END		499
#define C_CoefASRC7_VX_sizeof		19

#define C_CoefASRC8_VX_ADDR		500
#define C_CoefASRC8_VX_ADDR_END		518
#define C_CoefASRC8_VX_sizeof		19

#define C_CoefASRC9_VX_ADDR		519
#define C_CoefASRC9_VX_ADDR_END		537
#define C_CoefASRC9_VX_sizeof		19

#define C_CoefASRC10_VX_ADDR		538
#define C_CoefASRC10_VX_ADDR_END	556
#define C_CoefASRC10_VX_sizeof		19

#define C_CoefASRC11_VX_ADDR		557
#define C_CoefASRC11_VX_ADDR_END	575
#define C_CoefASRC11_VX_sizeof		19

#define C_CoefASRC12_VX_ADDR		576
#define C_CoefASRC12_VX_ADDR_END	594
#define C_CoefASRC12_VX_sizeof		19

#define C_CoefASRC13_VX_ADDR		595
#define C_CoefASRC13_VX_ADDR_END	613
#define C_CoefASRC13_VX_sizeof		19

#define C_CoefASRC14_VX_ADDR		614
#define C_CoefASRC14_VX_ADDR_END	632
#define C_CoefASRC14_VX_sizeof		19

#define C_CoefASRC15_VX_ADDR		633
#define C_CoefASRC15_VX_ADDR_END	651
#define C_CoefASRC15_VX_sizeof		19

#define C_CoefASRC16_VX_ADDR		652
#define C_CoefASRC16_VX_ADDR_END	670
#define C_CoefASRC16_VX_sizeof		19

#define C_AlphaCurrent_UL_VX_ADDR	671
#define C_AlphaCurrent_UL_VX_ADDR_END	671
#define C_AlphaCurrent_UL_VX_sizeof	1

#define C_BetaCurrent_UL_VX_ADDR	672
#define C_BetaCurrent_UL_VX_ADDR_END	672
#define C_BetaCurrent_UL_VX_sizeof	1

#define C_AlphaCurrent_DL_VX_ADDR	673
#define C_AlphaCurrent_DL_VX_ADDR_END	673
#define C_AlphaCurrent_DL_VX_sizeof	1

#define C_BetaCurrent_DL_VX_ADDR	674
#define C_BetaCurrent_DL_VX_ADDR_END	674
#define C_BetaCurrent_DL_VX_sizeof	1

#define C_CoefASRC1_DL_MM_ADDR		675
#define C_CoefASRC1_DL_MM_ADDR_END	692
#define C_CoefASRC1_DL_MM_sizeof	18

#define C_CoefASRC2_DL_MM_ADDR		693
#define C_CoefASRC2_DL_MM_ADDR_END	710
#define C_CoefASRC2_DL_MM_sizeof	18

#define C_CoefASRC3_DL_MM_ADDR		711
#define C_CoefASRC3_DL_MM_ADDR_END	728
#define C_CoefASRC3_DL_MM_sizeof	18

#define C_CoefASRC4_DL_MM_ADDR		729
#define C_CoefASRC4_DL_MM_ADDR_END	746
#define C_CoefASRC4_DL_MM_sizeof	18

#define C_CoefASRC5_DL_MM_ADDR		747
#define C_CoefASRC5_DL_MM_ADDR_END	764
#define C_CoefASRC5_DL_MM_sizeof	18

#define C_CoefASRC6_DL_MM_ADDR		765
#define C_CoefASRC6_DL_MM_ADDR_END	782
#define C_CoefASRC6_DL_MM_sizeof	18

#define C_CoefASRC7_DL_MM_ADDR		783
#define C_CoefASRC7_DL_MM_ADDR_END	800
#define C_CoefASRC7_DL_MM_sizeof	18

#define C_CoefASRC8_DL_MM_ADDR		801
#define C_CoefASRC8_DL_MM_ADDR_END	818
#define C_CoefASRC8_DL_MM_sizeof	18

#define C_CoefASRC9_DL_MM_ADDR		819
#define C_CoefASRC9_DL_MM_ADDR_END	836
#define C_CoefASRC9_DL_MM_sizeof	18

#define C_CoefASRC10_DL_MM_ADDR		837
#define C_CoefASRC10_DL_MM_ADDR_END	854
#define C_CoefASRC10_DL_MM_sizeof	18

#define C_CoefASRC11_DL_MM_ADDR		855
#define C_CoefASRC11_DL_MM_ADDR_END	872
#define C_CoefASRC11_DL_MM_sizeof	18

#define C_CoefASRC12_DL_MM_ADDR		873
#define C_CoefASRC12_DL_MM_ADDR_END	890
#define C_CoefASRC12_DL_MM_sizeof	18

#define C_CoefASRC13_DL_MM_ADDR		891
#define C_CoefASRC13_DL_MM_ADDR_END	908
#define C_CoefASRC13_DL_MM_sizeof	18

#define C_CoefASRC14_DL_MM_ADDR		909
#define C_CoefASRC14_DL_MM_ADDR_END	926
#define C_CoefASRC14_DL_MM_sizeof	18

#define C_CoefASRC15_DL_MM_ADDR		927
#define C_CoefASRC15_DL_MM_ADDR_END	944
#define C_CoefASRC15_DL_MM_sizeof	18

#define C_CoefASRC16_DL_MM_ADDR		945
#define C_CoefASRC16_DL_MM_ADDR_END	962
#define C_CoefASRC16_DL_MM_sizeof	18

#define C_AlphaCurrent_DL_MM_ADDR	963
#define C_AlphaCurrent_DL_MM_ADDR_END	963
#define C_AlphaCurrent_DL_MM_sizeof	1

#define C_BetaCurrent_DL_MM_ADDR	964
#define C_BetaCurrent_DL_MM_ADDR_END	964
#define C_BetaCurrent_DL_MM_sizeof	1

#define C_DL2_L_Coefs_ADDR		965
#define C_DL2_L_Coefs_ADDR_END		989
#define C_DL2_L_Coefs_sizeof		25

#define C_DL2_R_Coefs_ADDR		990
#define C_DL2_R_Coefs_ADDR_END		1014
#define C_DL2_R_Coefs_sizeof		25

#define C_DL1_Coefs_ADDR		1015
#define C_DL1_Coefs_ADDR_END		1039
#define C_DL1_Coefs_sizeof		25

#define C_VX_8_48_BP_Coefs_ADDR		1040
#define C_VX_8_48_BP_Coefs_ADDR_END	1052
#define C_VX_8_48_BP_Coefs_sizeof	13

#define C_VX_8_48_LP_Coefs_ADDR		1053
#define C_VX_8_48_LP_Coefs_ADDR_END	1065
#define C_VX_8_48_LP_Coefs_sizeof	13

#define C_VX_48_8_LP_Coefs_ADDR		1066
#define C_VX_48_8_LP_Coefs_ADDR_END	1078
#define C_VX_48_8_LP_Coefs_sizeof	13

#define C_VX_16_48_HP_Coefs_ADDR	1079
#define C_VX_16_48_HP_Coefs_ADDR_END	1085
#define C_VX_16_48_HP_Coefs_sizeof	7

#define C_VX_16_48_LP_Coefs_ADDR	1086
#define C_VX_16_48_LP_Coefs_ADDR_END	1098
#define C_VX_16_48_LP_Coefs_sizeof	13

#define C_VX_48_16_LP_Coefs_ADDR	1099
#define C_VX_48_16_LP_Coefs_ADDR_END	1111
#define C_VX_48_16_LP_Coefs_sizeof	13

#define C_EANC_WarpCoeffs_ADDR		1112
#define C_EANC_WarpCoeffs_ADDR_END	1113
#define C_EANC_WarpCoeffs_sizeof	2

#define C_EANC_FIRcoeffs_ADDR		1114
#define C_EANC_FIRcoeffs_ADDR_END	1134
#define C_EANC_FIRcoeffs_sizeof		21

#define C_EANC_IIRcoeffs_ADDR		1135
#define C_EANC_IIRcoeffs_ADDR_END	1151
#define C_EANC_IIRcoeffs_sizeof		17

#define C_EANC_FIRcoeffs_2nd_ADDR	1152
#define C_EANC_FIRcoeffs_2nd_ADDR_END	1172
#define C_EANC_FIRcoeffs_2nd_sizeof	21

#define C_EANC_IIRcoeffs_2nd_ADDR	1173
#define C_EANC_IIRcoeffs_2nd_ADDR_END	1189
#define C_EANC_IIRcoeffs_2nd_sizeof	17

#define C_APS_DL1_coeffs1_ADDR		1190
#define C_APS_DL1_coeffs1_ADDR_END	1198
#define C_APS_DL1_coeffs1_sizeof	9

#define C_APS_DL1_M_coeffs2_ADDR	1199
#define C_APS_DL1_M_coeffs2_ADDR_END	1201
#define C_APS_DL1_M_coeffs2_sizeof	3

#define C_APS_DL1_C_coeffs2_ADDR	1202
#define C_APS_DL1_C_coeffs2_ADDR_END	1204
#define C_APS_DL1_C_coeffs2_sizeof	3

#define C_APS_DL2_L_coeffs1_ADDR	1205
#define C_APS_DL2_L_coeffs1_ADDR_END	1213
#define C_APS_DL2_L_coeffs1_sizeof	9

#define C_APS_DL2_R_coeffs1_ADDR	1214
#define C_APS_DL2_R_coeffs1_ADDR_END	1222
#define C_APS_DL2_R_coeffs1_sizeof	9

#define C_APS_DL2_L_M_coeffs2_ADDR		1223
#define C_APS_DL2_L_M_coeffs2_ADDR_END		1225
#define C_APS_DL2_L_M_coeffs2_sizeof		3

#define C_APS_DL2_R_M_coeffs2_ADDR		1226
#define C_APS_DL2_R_M_coeffs2_ADDR_END		1228
#define C_APS_DL2_R_M_coeffs2_sizeof		3

#define C_APS_DL2_L_C_coeffs2_ADDR		1229
#define C_APS_DL2_L_C_coeffs2_ADDR_END		1231
#define C_APS_DL2_L_C_coeffs2_sizeof		3

#define C_APS_DL2_R_C_coeffs2_ADDR		1232
#define C_APS_DL2_R_C_coeffs2_ADDR_END		1234
#define C_APS_DL2_R_C_coeffs2_sizeof		3

#define C_AlphaCurrent_ECHO_REF_ADDR		1235
#define C_AlphaCurrent_ECHO_REF_ADDR_END	1235
#define C_AlphaCurrent_ECHO_REF_sizeof		1

#define C_BetaCurrent_ECHO_REF_ADDR		1236
#define C_BetaCurrent_ECHO_REF_ADDR_END		1236
#define C_BetaCurrent_ECHO_REF_sizeof		1

#define C_APS_DL1_EQ_ADDR			1237
#define C_APS_DL1_EQ_ADDR_END			1245
#define C_APS_DL1_EQ_sizeof			9

#define C_APS_DL2_L_EQ_ADDR			1246
#define C_APS_DL2_L_EQ_ADDR_END			1254
#define C_APS_DL2_L_EQ_sizeof			9

#define C_APS_DL2_R_EQ_ADDR			1255
#define C_APS_DL2_R_EQ_ADDR_END			1263
#define C_APS_DL2_R_EQ_sizeof			9

#define C_Vibra2_consts_ADDR			1264
#define C_Vibra2_consts_ADDR_END		1267
#define C_Vibra2_consts_sizeof			4

#define C_Vibra1_coeffs_ADDR			1268
#define C_Vibra1_coeffs_ADDR_END		1278
#define C_Vibra1_coeffs_sizeof			11

#define C_48_96_LP_Coefs_ADDR			1279
#define C_48_96_LP_Coefs_ADDR_END		1293
#define C_48_96_LP_Coefs_sizeof			15

#define C_98_48_LP_Coefs_ADDR			1294
#define C_98_48_LP_Coefs_ADDR_END		1308
#define C_98_48_LP_Coefs_sizeof			15

#endif /* _ABECM_ADDR_H_ */