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/*
* Texas Instruments OMAP(TM) Platform Firmware
* (c) Copyright 2009, Texas Instruments Incorporated. All Rights Reserved.
*
* Use of this firmware is controlled by the terms and conditions found
* in the license agreement under which this firmware has been supplied.
*/
#ifndef __ABE_CM_ADDR_H_
#define __ABE_CM_ADDR_H_
#define init_CM_ADDR 0
#define init_CM_ADDR_END 241
#define init_CM_sizeof 242
#define C_Coef1_ADDR 242
#define C_Coef1_ADDR_END 242
#define C_Coef1_sizeof 1
#define C_CoefM1_ADDR 243
#define C_CoefM1_ADDR_END 243
#define C_CoefM1_sizeof 1
#define C_1_Alpha_ADDR 244
#define C_1_Alpha_ADDR_END 252
#define C_1_Alpha_sizeof 9
#define C_Alpha_ADDR 253
#define C_Alpha_ADDR_END 261
#define C_Alpha_sizeof 9
#define C_GainsWRamp_ADDR 262
#define C_GainsWRamp_ADDR_END 279
#define C_GainsWRamp_sizeof 18
#define C_Gains_ADDR 280
#define C_Gains_ADDR_END 291
#define C_Gains_sizeof 12
#define C_Gains_DL1M_ADDR 292
#define C_Gains_DL1M_ADDR_END 295
#define C_Gains_DL1M_sizeof 4
#define C_Gains_DL2M_ADDR 296
#define C_Gains_DL2M_ADDR_END 299
#define C_Gains_DL2M_sizeof 4
#define C_Gains_EchoM_ADDR 300
#define C_Gains_EchoM_ADDR_END 301
#define C_Gains_EchoM_sizeof 2
#define C_Gains_SDTM_ADDR 302
#define C_Gains_SDTM_ADDR_END 303
#define C_Gains_SDTM_sizeof 2
#define C_Gains_VxRecM_ADDR 304
#define C_Gains_VxRecM_ADDR_END 307
#define C_Gains_VxRecM_sizeof 4
#define C_Gains_ULM_ADDR 308
#define C_Gains_ULM_ADDR_END 311
#define C_Gains_ULM_sizeof 4
#define C_SDT_Coefs_ADDR 312
#define C_SDT_Coefs_ADDR_END 328
#define C_SDT_Coefs_sizeof 17
#define C_MM96_F_Coefs_ADDR 329
#define C_MM96_F_Coefs_ADDR_END 345
#define C_MM96_F_Coefs_sizeof 17
#define C_DMIC0_96F_Coefs_ADDR 346
#define C_DMIC0_96F_Coefs_ADDR_END 362
#define C_DMIC0_96F_Coefs_sizeof 17
#define C_DMIC_96_48_Coefs_ADDR 363
#define C_DMIC_96_48_Coefs_ADDR_END 379
#define C_DMIC_96_48_Coefs_sizeof 17
#define C_AMIC_96_48_Coefs_ADDR 380
#define C_AMIC_96_48_Coefs_ADDR_END 396
#define C_AMIC_96_48_Coefs_sizeof 17
#define C_AMIC_EQ_Coefs_ADDR 397
#define C_AMIC_EQ_Coefs_ADDR_END 413
#define C_AMIC_EQ_Coefs_sizeof 17
#define C_DMIC1_EQ_Coefs_ADDR 414
#define C_DMIC1_EQ_Coefs_ADDR_END 430
#define C_DMIC1_EQ_Coefs_sizeof 17
#define C_DMIC2_EQ_Coefs_ADDR 431
#define C_DMIC2_EQ_Coefs_ADDR_END 447
#define C_DMIC2_EQ_Coefs_sizeof 17
#define C_DMIC3_EQ_Coefs_ADDR 448
#define C_DMIC3_EQ_Coefs_ADDR_END 464
#define C_DMIC3_EQ_Coefs_sizeof 17
#define C_Voice_F_Coefs_ADDR 465
#define C_Voice_F_Coefs_ADDR_END 481
#define C_Voice_F_Coefs_sizeof 17
#define C_CoefASRC1_UL_VX_ADDR 482
#define C_CoefASRC1_UL_VX_ADDR_END 500
#define C_CoefASRC1_UL_VX_sizeof 19
#define C_CoefASRC2_UL_VX_ADDR 501
#define C_CoefASRC2_UL_VX_ADDR_END 519
#define C_CoefASRC2_UL_VX_sizeof 19
#define C_CoefASRC3_UL_VX_ADDR 520
#define C_CoefASRC3_UL_VX_ADDR_END 538
#define C_CoefASRC3_UL_VX_sizeof 19
#define C_CoefASRC4_UL_VX_ADDR 539
#define C_CoefASRC4_UL_VX_ADDR_END 557
#define C_CoefASRC4_UL_VX_sizeof 19
#define C_CoefASRC5_UL_VX_ADDR 558
#define C_CoefASRC5_UL_VX_ADDR_END 576
#define C_CoefASRC5_UL_VX_sizeof 19
#define C_CoefASRC6_UL_VX_ADDR 577
#define C_CoefASRC6_UL_VX_ADDR_END 595
#define C_CoefASRC6_UL_VX_sizeof 19
#define C_CoefASRC7_UL_VX_ADDR 596
#define C_CoefASRC7_UL_VX_ADDR_END 614
#define C_CoefASRC7_UL_VX_sizeof 19
#define C_CoefASRC8_UL_VX_ADDR 615
#define C_CoefASRC8_UL_VX_ADDR_END 633
#define C_CoefASRC8_UL_VX_sizeof 19
#define C_CoefASRC9_UL_VX_ADDR 634
#define C_CoefASRC9_UL_VX_ADDR_END 652
#define C_CoefASRC9_UL_VX_sizeof 19
#define C_CoefASRC10_UL_VX_ADDR 653
#define C_CoefASRC10_UL_VX_ADDR_END 671
#define C_CoefASRC10_UL_VX_sizeof 19
#define C_CoefASRC11_UL_VX_ADDR 672
#define C_CoefASRC11_UL_VX_ADDR_END 690
#define C_CoefASRC11_UL_VX_sizeof 19
#define C_CoefASRC12_UL_VX_ADDR 691
#define C_CoefASRC12_UL_VX_ADDR_END 709
#define C_CoefASRC12_UL_VX_sizeof 19
#define C_CoefASRC13_UL_VX_ADDR 710
#define C_CoefASRC13_UL_VX_ADDR_END 728
#define C_CoefASRC13_UL_VX_sizeof 19
#define C_CoefASRC14_UL_VX_ADDR 729
#define C_CoefASRC14_UL_VX_ADDR_END 747
#define C_CoefASRC14_UL_VX_sizeof 19
#define C_CoefASRC15_UL_VX_ADDR 748
#define C_CoefASRC15_UL_VX_ADDR_END 766
#define C_CoefASRC15_UL_VX_sizeof 19
#define C_CoefASRC16_UL_VX_ADDR 767
#define C_CoefASRC16_UL_VX_ADDR_END 785
#define C_CoefASRC16_UL_VX_sizeof 19
#define C_AlphaCurrent_UL_VX_ADDR 786
#define C_AlphaCurrent_UL_VX_ADDR_END 786
#define C_AlphaCurrent_UL_VX_sizeof 1
#define C_BetaCurrent_UL_VX_ADDR 787
#define C_BetaCurrent_UL_VX_ADDR_END 787
#define C_BetaCurrent_UL_VX_sizeof 1
#define C_CoefASRC1_DL_VX_ADDR 788
#define C_CoefASRC1_DL_VX_ADDR_END 806
#define C_CoefASRC1_DL_VX_sizeof 19
#define C_CoefASRC2_DL_VX_ADDR 807
#define C_CoefASRC2_DL_VX_ADDR_END 825
#define C_CoefASRC2_DL_VX_sizeof 19
#define C_CoefASRC3_DL_VX_ADDR 826
#define C_CoefASRC3_DL_VX_ADDR_END 844
#define C_CoefASRC3_DL_VX_sizeof 19
#define C_CoefASRC4_DL_VX_ADDR 845
#define C_CoefASRC4_DL_VX_ADDR_END 863
#define C_CoefASRC4_DL_VX_sizeof 19
#define C_CoefASRC5_DL_VX_ADDR 864
#define C_CoefASRC5_DL_VX_ADDR_END 882
#define C_CoefASRC5_DL_VX_sizeof 19
#define C_CoefASRC6_DL_VX_ADDR 883
#define C_CoefASRC6_DL_VX_ADDR_END 901
#define C_CoefASRC6_DL_VX_sizeof 19
#define C_CoefASRC7_DL_VX_ADDR 902
#define C_CoefASRC7_DL_VX_ADDR_END 920
#define C_CoefASRC7_DL_VX_sizeof 19
#define C_CoefASRC8_DL_VX_ADDR 921
#define C_CoefASRC8_DL_VX_ADDR_END 939
#define C_CoefASRC8_DL_VX_sizeof 19
#define C_CoefASRC9_DL_VX_ADDR 940
#define C_CoefASRC9_DL_VX_ADDR_END 958
#define C_CoefASRC9_DL_VX_sizeof 19
#define C_CoefASRC10_DL_VX_ADDR 959
#define C_CoefASRC10_DL_VX_ADDR_END 977
#define C_CoefASRC10_DL_VX_sizeof 19
#define C_CoefASRC11_DL_VX_ADDR 978
#define C_CoefASRC11_DL_VX_ADDR_END 996
#define C_CoefASRC11_DL_VX_sizeof 19
#define C_CoefASRC12_DL_VX_ADDR 997
#define C_CoefASRC12_DL_VX_ADDR_END 1015
#define C_CoefASRC12_DL_VX_sizeof 19
#define C_CoefASRC13_DL_VX_ADDR 1016
#define C_CoefASRC13_DL_VX_ADDR_END 1034
#define C_CoefASRC13_DL_VX_sizeof 19
#define C_CoefASRC14_DL_VX_ADDR 1035
#define C_CoefASRC14_DL_VX_ADDR_END 1053
#define C_CoefASRC14_DL_VX_sizeof 19
#define C_CoefASRC15_DL_VX_ADDR 1054
#define C_CoefASRC15_DL_VX_ADDR_END 1072
#define C_CoefASRC15_DL_VX_sizeof 19
#define C_CoefASRC16_DL_VX_ADDR 1073
#define C_CoefASRC16_DL_VX_ADDR_END 1091
#define C_CoefASRC16_DL_VX_sizeof 19
#define C_AlphaCurrent_DL_VX_ADDR 1092
#define C_AlphaCurrent_DL_VX_ADDR_END 1092
#define C_AlphaCurrent_DL_VX_sizeof 1
#define C_BetaCurrent_DL_VX_ADDR 1093
#define C_BetaCurrent_DL_VX_ADDR_END 1093
#define C_BetaCurrent_DL_VX_sizeof 1
#define C_CoefASRC1_DL_MM_ADDR 1094
#define C_CoefASRC1_DL_MM_ADDR_END 1111
#define C_CoefASRC1_DL_MM_sizeof 18
#define C_CoefASRC2_DL_MM_ADDR 1112
#define C_CoefASRC2_DL_MM_ADDR_END 1129
#define C_CoefASRC2_DL_MM_sizeof 18
#define C_CoefASRC3_DL_MM_ADDR 1130
#define C_CoefASRC3_DL_MM_ADDR_END 1147
#define C_CoefASRC3_DL_MM_sizeof 18
#define C_CoefASRC4_DL_MM_ADDR 1148
#define C_CoefASRC4_DL_MM_ADDR_END 1165
#define C_CoefASRC4_DL_MM_sizeof 18
#define C_CoefASRC5_DL_MM_ADDR 1166
#define C_CoefASRC5_DL_MM_ADDR_END 1183
#define C_CoefASRC5_DL_MM_sizeof 18
#define C_CoefASRC6_DL_MM_ADDR 1184
#define C_CoefASRC6_DL_MM_ADDR_END 1201
#define C_CoefASRC6_DL_MM_sizeof 18
#define C_CoefASRC7_DL_MM_ADDR 1202
#define C_CoefASRC7_DL_MM_ADDR_END 1219
#define C_CoefASRC7_DL_MM_sizeof 18
#define C_CoefASRC8_DL_MM_ADDR 1220
#define C_CoefASRC8_DL_MM_ADDR_END 1237
#define C_CoefASRC8_DL_MM_sizeof 18
#define C_CoefASRC9_DL_MM_ADDR 1238
#define C_CoefASRC9_DL_MM_ADDR_END 1255
#define C_CoefASRC9_DL_MM_sizeof 18
#define C_CoefASRC10_DL_MM_ADDR 1256
#define C_CoefASRC10_DL_MM_ADDR_END 1273
#define C_CoefASRC10_DL_MM_sizeof 18
#define C_CoefASRC11_DL_MM_ADDR 1274
#define C_CoefASRC11_DL_MM_ADDR_END 1291
#define C_CoefASRC11_DL_MM_sizeof 18
#define C_CoefASRC12_DL_MM_ADDR 1292
#define C_CoefASRC12_DL_MM_ADDR_END 1309
#define C_CoefASRC12_DL_MM_sizeof 18
#define C_CoefASRC13_DL_MM_ADDR 1310
#define C_CoefASRC13_DL_MM_ADDR_END 1327
#define C_CoefASRC13_DL_MM_sizeof 18
#define C_CoefASRC14_DL_MM_ADDR 1328
#define C_CoefASRC14_DL_MM_ADDR_END 1345
#define C_CoefASRC14_DL_MM_sizeof 18
#define C_CoefASRC15_DL_MM_ADDR 1346
#define C_CoefASRC15_DL_MM_ADDR_END 1363
#define C_CoefASRC15_DL_MM_sizeof 18
#define C_CoefASRC16_DL_MM_ADDR 1364
#define C_CoefASRC16_DL_MM_ADDR_END 1381
#define C_CoefASRC16_DL_MM_sizeof 18
#define C_AlphaCurrent_DL_MM_ADDR 1382
#define C_AlphaCurrent_DL_MM_ADDR_END 1382
#define C_AlphaCurrent_DL_MM_sizeof 1
#define C_BetaCurrent_DL_MM_ADDR 1383
#define C_BetaCurrent_DL_MM_ADDR_END 1383
#define C_BetaCurrent_DL_MM_sizeof 1
#define C_DL2_L_Coefs_ADDR 1384
#define C_DL2_L_Coefs_ADDR_END 1408
#define C_DL2_L_Coefs_sizeof 25
#define C_DL2_R_Coefs_ADDR 1409
#define C_DL2_R_Coefs_ADDR_END 1433
#define C_DL2_R_Coefs_sizeof 25
#define C_DL1_Coefs_ADDR 1434
#define C_DL1_Coefs_ADDR_END 1458
#define C_DL1_Coefs_sizeof 25
#define C_48_96_LP0_Coefs_ADDR 1459
#define C_48_96_LP0_Coefs_ADDR_END 1471
#define C_48_96_LP0_Coefs_sizeof 13
#define C_48_96_LP1_Coefs_ADDR 1472
#define C_48_96_LP1_Coefs_ADDR_END 1486
#define C_48_96_LP1_Coefs_sizeof 15
#define C_VX_8_48_BP_Coefs_ADDR 1487
#define C_VX_8_48_BP_Coefs_ADDR_END 1499
#define C_VX_8_48_BP_Coefs_sizeof 13
#define C_VX_8_48_LP_Coefs_ADDR 1500
#define C_VX_8_48_LP_Coefs_ADDR_END 1512
#define C_VX_8_48_LP_Coefs_sizeof 13
#define C_VX_48_8_LP_Coefs_ADDR 1513
#define C_VX_48_8_LP_Coefs_ADDR_END 1525
#define C_VX_48_8_LP_Coefs_sizeof 13
#define C_VX_16_48_HP_Coefs_ADDR 1526
#define C_VX_16_48_HP_Coefs_ADDR_END 1532
#define C_VX_16_48_HP_Coefs_sizeof 7
#define C_VX_16_48_LP_Coefs_ADDR 1533
#define C_VX_16_48_LP_Coefs_ADDR_END 1545
#define C_VX_16_48_LP_Coefs_sizeof 13
#define C_VX_48_16_LP_Coefs_ADDR 1546
#define C_VX_48_16_LP_Coefs_ADDR_END 1558
#define C_VX_48_16_LP_Coefs_sizeof 13
#define C_EANC_WarpCoeffs_ADDR 1559
#define C_EANC_WarpCoeffs_ADDR_END 1560
#define C_EANC_WarpCoeffs_sizeof 2
#define C_EANC_FIRcoeffs_ADDR 1561
#define C_EANC_FIRcoeffs_ADDR_END 1581
#define C_EANC_FIRcoeffs_sizeof 21
#define C_EANC_IIRcoeffs_ADDR 1582
#define C_EANC_IIRcoeffs_ADDR_END 1598
#define C_EANC_IIRcoeffs_sizeof 17
#define C_APS_coeffs1_ADDR 1599
#define C_APS_coeffs1_ADDR_END 1607
#define C_APS_coeffs1_sizeof 9
#define C_APS_coeffs2_ADDR 1608
#define C_APS_coeffs2_ADDR_END 1610
#define C_APS_coeffs2_sizeof 3
#define C_APS_DL2_L_coeffs1_ADDR 1611
#define C_APS_DL2_L_coeffs1_ADDR_END 1619
#define C_APS_DL2_L_coeffs1_sizeof 9
#define C_APS_DL2_R_coeffs1_ADDR 1620
#define C_APS_DL2_R_coeffs1_ADDR_END 1628
#define C_APS_DL2_R_coeffs1_sizeof 9
#define C_APS_DL2_L_coeffs2_ADDR 1629
#define C_APS_DL2_L_coeffs2_ADDR_END 1631
#define C_APS_DL2_L_coeffs2_sizeof 3
#define C_APS_DL2_R_coeffs2_ADDR 1632
#define C_APS_DL2_R_coeffs2_ADDR_END 1634
#define C_APS_DL2_R_coeffs2_sizeof 3
#define C_AlphaCurrent_ECHO_REF_ADDR 1635
#define C_AlphaCurrent_ECHO_REF_ADDR_END 1635
#define C_AlphaCurrent_ECHO_REF_sizeof 1
#define C_BetaCurrent_ECHO_REF_ADDR 1636
#define C_BetaCurrent_ECHO_REF_ADDR_END 1636
#define C_BetaCurrent_ECHO_REF_sizeof 1
#define C_APS_DL1_EQ_ADDR 1637
#define C_APS_DL1_EQ_ADDR_END 1645
#define C_APS_DL1_EQ_sizeof 9
#define C_APS_DL2_L_EQ_ADDR 1646
#define C_APS_DL2_L_EQ_ADDR_END 1654
#define C_APS_DL2_L_EQ_sizeof 9
#define C_APS_DL2_R_EQ_ADDR 1655
#define C_APS_DL2_R_EQ_ADDR_END 1663
#define C_APS_DL2_R_EQ_sizeof 9
#endif /* _ABECM_ADDR_H_ */
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