1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
|
[
{
"MetricExpr": "BR_MIS_PRED / BR_PRED",
"BriefDescription": "Branch predictor misprediction rate. May not count branches that are never resolved because they are in the misprediction shadow of an earlier branch",
"MetricGroup": "Branch Prediction",
"MetricName": "Misprediction"
},
{
"MetricExpr": "BR_MIS_PRED_RETIRED / BR_RETIRED",
"BriefDescription": "Branch predictor misprediction rate",
"MetricGroup": "Branch Prediction",
"MetricName": "Misprediction (retired)"
},
{
"MetricExpr": "BUS_ACCESS / ( BUS_CYCLES * 1)",
"BriefDescription": "Core-to-uncore bus utilization",
"MetricGroup": "Bus",
"MetricName": "Bus utilization"
},
{
"MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
"BriefDescription": "L1D cache miss rate",
"MetricGroup": "Cache",
"MetricName": "L1D cache miss"
},
{
"MetricExpr": "L1D_CACHE_LMISS_RD / L1D_CACHE_RD",
"BriefDescription": "L1D cache read miss rate",
"MetricGroup": "Cache",
"MetricName": "L1D cache read miss"
},
{
"MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
"BriefDescription": "L1I cache miss rate",
"MetricGroup": "Cache",
"MetricName": "L1I cache miss"
},
{
"MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
"BriefDescription": "L2 cache miss rate",
"MetricGroup": "Cache",
"MetricName": "L2 cache miss"
},
{
"MetricExpr": "L1I_CACHE_LMISS / L1I_CACHE",
"BriefDescription": "L1I cache read miss rate",
"MetricGroup": "Cache",
"MetricName": "L1I cache read miss"
},
{
"MetricExpr": "L2D_CACHE_LMISS_RD / L2D_CACHE_RD",
"BriefDescription": "L2 cache read miss rate",
"MetricGroup": "Cache",
"MetricName": "L2 cache read miss"
},
{
"MetricExpr": "(L1D_CACHE_LMISS_RD * 1000) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (data)",
"MetricGroup": "Cache",
"MetricName": "MPKI data"
},
{
"MetricExpr": "(L1I_CACHE_LMISS * 1000) / INST_RETIRED",
"BriefDescription": "Misses per thousand instructions (instruction)",
"MetricGroup": "Cache",
"MetricName": "MPKI instruction"
},
{
"MetricExpr": "ASE_SPEC / OP_SPEC",
"BriefDescription": "Proportion of advanced SIMD data processing operations (excluding DP_SPEC/LD_SPEC) operations",
"MetricGroup": "Instruction",
"MetricName": "ASE mix"
},
{
"MetricExpr": "CRYPTO_SPEC / OP_SPEC",
"BriefDescription": "Proportion of crypto data processing operations",
"MetricGroup": "Instruction",
"MetricName": "Crypto mix"
},
{
"MetricExpr": "VFP_SPEC / (duration_time *1000000000)",
"BriefDescription": "Giga-floating point operations per second",
"MetricGroup": "Instruction",
"MetricName": "GFLOPS_ISSUED"
},
{
"MetricExpr": "DP_SPEC / OP_SPEC",
"BriefDescription": "Proportion of integer data processing operations",
"MetricGroup": "Instruction",
"MetricName": "Integer mix"
},
{
"MetricExpr": "INST_RETIRED / CPU_CYCLES",
"BriefDescription": "Instructions per cycle",
"MetricGroup": "Instruction",
"MetricName": "IPC"
},
{
"MetricExpr": "LD_SPEC / OP_SPEC",
"BriefDescription": "Proportion of load operations",
"MetricGroup": "Instruction",
"MetricName": "Load mix"
},
{
"MetricExpr": "LDST_SPEC/ OP_SPEC",
"BriefDescription": "Proportion of load & store operations",
"MetricGroup": "Instruction",
"MetricName": "Load-store mix"
},
{
"MetricExpr": "INST_RETIRED / (duration_time * 1000000)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "Instruction",
"MetricName": "MIPS_RETIRED"
},
{
"MetricExpr": "INST_SPEC / (duration_time * 1000000)",
"BriefDescription": "Millions of instructions per second",
"MetricGroup": "Instruction",
"MetricName": "MIPS_UTILIZATION"
},
{
"MetricExpr": "PC_WRITE_SPEC / OP_SPEC",
"BriefDescription": "Proportion of software change of PC operations",
"MetricGroup": "Instruction",
"MetricName": "PC write mix"
},
{
"MetricExpr": "ST_SPEC / OP_SPEC",
"BriefDescription": "Proportion of store operations",
"MetricGroup": "Instruction",
"MetricName": "Store mix"
},
{
"MetricExpr": "VFP_SPEC / OP_SPEC",
"BriefDescription": "Proportion of FP operations",
"MetricGroup": "Instruction",
"MetricName": "VFP mix"
},
{
"MetricExpr": "1 - (OP_RETIRED/ (CPU_CYCLES * 4))",
"BriefDescription": "Proportion of slots lost",
"MetricGroup": "Speculation / TDA",
"MetricName": "CPU lost"
},
{
"MetricExpr": "OP_RETIRED/ (CPU_CYCLES * 4)",
"BriefDescription": "Proportion of slots retiring",
"MetricGroup": "Speculation / TDA",
"MetricName": "CPU utilization"
},
{
"MetricExpr": "OP_RETIRED - OP_SPEC",
"BriefDescription": "Operations lost due to misspeculation",
"MetricGroup": "Speculation / TDA",
"MetricName": "Operations lost"
},
{
"MetricExpr": "1 - (OP_RETIRED / OP_SPEC)",
"BriefDescription": "Proportion of operations lost",
"MetricGroup": "Speculation / TDA",
"MetricName": "Operations lost (ratio)"
},
{
"MetricExpr": "OP_RETIRED / OP_SPEC",
"BriefDescription": "Proportion of operations retired",
"MetricGroup": "Speculation / TDA",
"MetricName": "Operations retired"
},
{
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and cache miss",
"MetricGroup": "Stall",
"MetricName": "Stall backend cache cycles"
},
{
"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and resource full",
"MetricGroup": "Stall",
"MetricName": "Stall backend resource cycles"
},
{
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no operations issued to backend and TLB miss",
"MetricGroup": "Stall",
"MetricName": "Stall backend tlb cycles"
},
{
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and cache miss",
"MetricGroup": "Stall",
"MetricName": "Stall frontend cache cycles"
},
{
"MetricExpr": "STALL_FRONTEND_TLB / CPU_CYCLES",
"BriefDescription": "Proportion of cycles stalled and no ops delivered from frontend and TLB miss",
"MetricGroup": "Stall",
"MetricName": "Stall frontend tlb cycles"
},
{
"MetricExpr": "DTLB_WALK / L1D_TLB",
"BriefDescription": "D-side walk per d-side translation request",
"MetricGroup": "TLB",
"MetricName": "DTLB walks"
},
{
"MetricExpr": "ITLB_WALK / L1I_TLB",
"BriefDescription": "I-side walk per i-side translation request",
"MetricGroup": "TLB",
"MetricName": "ITLB walks"
},
{
"MetricExpr": "STALL_SLOT_BACKEND / (CPU_CYCLES * 4)",
"BriefDescription": "Fraction of slots backend bound",
"MetricGroup": "TopDownL1",
"MetricName": "backend"
},
{
"MetricExpr": "1 - (retiring + lost + backend)",
"BriefDescription": "Fraction of slots frontend bound",
"MetricGroup": "TopDownL1",
"MetricName": "frontend"
},
{
"MetricExpr": "((OP_SPEC - OP_RETIRED) / (CPU_CYCLES * 4))",
"BriefDescription": "Fraction of slots lost due to misspeculation",
"MetricGroup": "TopDownL1",
"MetricName": "lost"
},
{
"MetricExpr": "(OP_RETIRED / (CPU_CYCLES * 4))",
"BriefDescription": "Fraction of slots retiring, useful work",
"MetricGroup": "TopDownL1",
"MetricName": "retiring"
},
{
"MetricExpr": "backend - backend_memory",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend non-memory subsystem issues",
"MetricGroup": "TopDownL2",
"MetricName": "backend_core"
},
{
"MetricExpr": "(STALL_BACKEND_TLB + STALL_BACKEND_CACHE + STALL_BACKEND_MEM) / CPU_CYCLES ",
"BriefDescription": "Fraction of slots the CPU was stalled due to backend memory subsystem issues (cache/tlb miss)",
"MetricGroup": "TopDownL2",
"MetricName": "backend_memory"
},
{
"MetricExpr": " (BR_MIS_PRED_RETIRED / GPC_FLUSH) * lost",
"BriefDescription": "Fraction of slots lost due to branch misprediciton",
"MetricGroup": "TopDownL2",
"MetricName": "branch_mispredict"
},
{
"MetricExpr": "frontend - frontend_latency",
"BriefDescription": "Fraction of slots the CPU did not dispatch at full bandwidth - able to dispatch partial slots only (1, 2, or 3 uops)",
"MetricGroup": "TopDownL2",
"MetricName": "frontend_bandwidth"
},
{
"MetricExpr": "(STALL_FRONTEND - ((STALL_SLOT_FRONTEND - (frontend * CPU_CYCLES * 4)) / 4)) / CPU_CYCLES",
"BriefDescription": "Fraction of slots the CPU was stalled due to frontend latency issues (cache/tlb miss); nothing to dispatch",
"MetricGroup": "TopDownL2",
"MetricName": "frontend_latency"
},
{
"MetricExpr": "lost - branch_mispredict",
"BriefDescription": "Fraction of slots lost due to other/non-branch misprediction misspeculation",
"MetricGroup": "TopDownL2",
"MetricName": "other_clears"
},
{
"MetricExpr": "(IXU_NUM_UOPS_ISSUED + FSU_ISSUED) / (CPU_CYCLES * 6)",
"BriefDescription": "Fraction of execute slots utilized",
"MetricGroup": "TopDownL2",
"MetricName": "pipe_utilization"
},
{
"MetricExpr": "STALL_BACKEND_MEM / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data L2 cache miss",
"MetricGroup": "TopDownL3",
"MetricName": "d_cache_l2_miss"
},
{
"MetricExpr": "STALL_BACKEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data cache miss",
"MetricGroup": "TopDownL3",
"MetricName": "d_cache_miss"
},
{
"MetricExpr": "STALL_BACKEND_TLB / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to data TLB miss",
"MetricGroup": "TopDownL3",
"MetricName": "d_tlb_miss"
},
{
"MetricExpr": "FSU_ISSUED / (CPU_CYCLES * 2)",
"BriefDescription": "Fraction of FSU execute slots utilized",
"MetricGroup": "TopDownL3",
"MetricName": "fsu_pipe_utilization"
},
{
"MetricExpr": "STALL_FRONTEND_CACHE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction cache miss",
"MetricGroup": "TopDownL3",
"MetricName": "i_cache_miss"
},
{
"MetricExpr": " STALL_FRONTEND_TLB / CPU_CYCLES ",
"BriefDescription": "Fraction of cycles the CPU was stalled due to instruction TLB miss",
"MetricGroup": "TopDownL3",
"MetricName": "i_tlb_miss"
},
{
"MetricExpr": "IXU_NUM_UOPS_ISSUED / (CPU_CYCLES / 4)",
"BriefDescription": "Fraction of IXU execute slots utilized",
"MetricGroup": "TopDownL3",
"MetricName": "ixu_pipe_utilization"
},
{
"MetricExpr": "IDR_STALL_FLUSH / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to flush recovery",
"MetricGroup": "TopDownL3",
"MetricName": "recovery"
},
{
"MetricExpr": "STALL_BACKEND_RESOURCE / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled due to core resource shortage",
"MetricGroup": "TopDownL3",
"MetricName": "resource"
},
{
"MetricExpr": "IDR_STALL_FSU_SCHED / CPU_CYCLES ",
"BriefDescription": "Fraction of cycles the CPU was stalled and FSU was full",
"MetricGroup": "TopDownL4",
"MetricName": "stall_fsu_sched"
},
{
"MetricExpr": "IDR_STALL_IXU_SCHED / CPU_CYCLES ",
"BriefDescription": "Fraction of cycles the CPU was stalled and IXU was full",
"MetricGroup": "TopDownL4",
"MetricName": "stall_ixu_sched"
},
{
"MetricExpr": "IDR_STALL_LOB_ID / CPU_CYCLES ",
"BriefDescription": "Fraction of cycles the CPU was stalled and LOB was full",
"MetricGroup": "TopDownL4",
"MetricName": "stall_lob_id"
},
{
"MetricExpr": "IDR_STALL_ROB_ID / CPU_CYCLES",
"BriefDescription": "Fraction of cycles the CPU was stalled and ROB was full",
"MetricGroup": "TopDownL4",
"MetricName": "stall_rob_id"
},
{
"MetricExpr": "IDR_STALL_SOB_ID / CPU_CYCLES ",
"BriefDescription": "Fraction of cycles the CPU was stalled and SOB was full",
"MetricGroup": "TopDownL4",
"MetricName": "stall_sob_id"
}
]
|
