diff options
Diffstat (limited to 'arch/arm/mach-omap2')
70 files changed, 6618 insertions, 11525 deletions
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 3eed0006d189..b5fb5f7992df 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -37,9 +37,8 @@ config ARCH_OMAP4 select CACHE_L2X0 select CPU_V7 select HAVE_ARM_SCU if SMP - select HAVE_ARM_TWD if LOCAL_TIMERS + select HAVE_ARM_TWD if SMP select HAVE_SMP - select LOCAL_TIMERS if SMP select OMAP_INTERCONNECT select PL310_ERRATA_588369 select PL310_ERRATA_727915 @@ -65,7 +64,7 @@ config SOC_OMAP5 select ARM_ERRATA_798181 if SMP config SOC_AM33XX - bool "AM33XX support" + bool "TI AM33XX" depends on ARCH_MULTI_V7 select ARCH_OMAP2PLUS select ARM_CPU_SUSPEND if PM @@ -118,7 +117,7 @@ config ARCH_OMAP2PLUS_TYPICAL select I2C select I2C_OMAP select MENELAUS if ARCH_OMAP2 - select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 + select NEON if CPU_V7 select PM_RUNTIME select REGULATOR select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 @@ -132,9 +131,17 @@ config SOC_HAS_OMAP2_SDRC config SOC_HAS_REALTIME_COUNTER bool "Real time free running counter" - depends on SOC_OMAP5 + depends on SOC_OMAP5 || SOC_DRA7XX default y +config SOC_DRA7XX + bool "TI DRA7XX" + select ARM_ARCH_TIMER + select CPU_V7 + select ARM_GIC + select HAVE_SMP + select COMMON_CLK + comment "OMAP Core Type" depends on ARCH_OMAP2 diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index d4f671547c37..afb457c3135b 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) +obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common) ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) obj-y += mcbsp.o @@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y) plus_sec := $(call as-instr,.arch_extension sec,+sec) AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) @@ -61,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o +obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o # Pin multiplexing obj-$(CONFIG_SOC_OMAP2420) += mux2420.o @@ -87,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o +obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o obj-$(CONFIG_PM_DEBUG) += pm-debug.o obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o @@ -114,6 +118,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ vc44xx_data.o vp44xx_data.o obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) +obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common) # OMAP voltage domains voltagedomain-common := voltage.o vc.o vp.o @@ -143,6 +148,8 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) +obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o # PRCM clockdomain control clockdomain-common += clockdomain.o @@ -160,6 +167,8 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) +obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o # Clock framework obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o @@ -203,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o +obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o # EMU peripherals obj-$(CONFIG_OMAP3_EMU) += emu.o diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c index 1eae96212315..c88d8df753c2 100644 --- a/arch/arm/mach-omap2/am33xx-restart.c +++ b/arch/arm/mach-omap2/am33xx-restart.c @@ -24,8 +24,8 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd) { /* TODO: Handle mode and cmd if necessary */ - am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK, - AM33XX_GLOBAL_WARM_SW_RST_MASK, + am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK, + AM33XX_RST_GLOBAL_WARM_SW_MASK, AM33XX_PRM_DEVICE_MOD, AM33XX_PRM_RSTCTRL_OFFSET); diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index 244d8a5aa54b..c711ad6ac067 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -100,39 +100,52 @@ static struct platform_device sdp2430_flash_device = { .resource = &sdp2430_flash_resource, }; -static struct platform_device *sdp2430_devices[] __initdata = { - &sdp2430_flash_device, -}; - /* LCD */ #define SDP2430_LCD_PANEL_BACKLIGHT_GPIO 91 #define SDP2430_LCD_PANEL_ENABLE_GPIO 154 -static struct panel_generic_dpi_data sdp2430_panel_data = { - .name = "nec_nl2432dr22-11b", - .num_gpios = 2, - .gpios = { - SDP2430_LCD_PANEL_ENABLE_GPIO, - SDP2430_LCD_PANEL_BACKLIGHT_GPIO, - }, +static const struct display_timing sdp2430_lcd_videomode = { + .pixelclock = { 0, 5400000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 39, 0 }, + .hsync_len = { 0, 3, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 2, 0 }, + .vback_porch = { 0, 7, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device sdp2430_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &sdp2430_panel_data, +static struct panel_dpi_platform_data sdp2430_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &sdp2430_lcd_videomode, + + .enable_gpio = SDP2430_LCD_PANEL_ENABLE_GPIO, + .backlight_gpio = SDP2430_LCD_PANEL_BACKLIGHT_GPIO, }; -static struct omap_dss_device *sdp2430_dss_devices[] = { - &sdp2430_lcd_device, +static struct platform_device sdp2430_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &sdp2430_lcd_pdata, }; static struct omap_dss_board_info sdp2430_dss_data = { - .num_devices = ARRAY_SIZE(sdp2430_dss_devices), - .devices = sdp2430_dss_devices, - .default_device = &sdp2430_lcd_device, + .default_display_name = "lcd", +}; + +static struct platform_device *sdp2430_devices[] __initdata = { + &sdp2430_flash_device, + &sdp2430_lcd_device, }; #if IS_ENABLED(CONFIG_SMC91X) diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index 23b004afa3f8..d95d0ef1354a 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -126,53 +126,65 @@ static void __init sdp3430_display_init(void) } -static struct panel_sharp_ls037v7dw01_data sdp3430_lcd_data = { - .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO, - .ini_gpio = -1, - .mo_gpio = -1, - .lr_gpio = -1, - .ud_gpio = -1, +static struct panel_sharp_ls037v7dw01_platform_data sdp3430_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO, + .ini_gpio = -1, + .mo_gpio = -1, + .lr_gpio = -1, + .ud_gpio = -1, +}; + +static struct platform_device sdp3430_lcd_device = { + .name = "panel-sharp-ls037v7dw01", + .id = 0, + .dev.platform_data = &sdp3430_lcd_pdata, }; -static struct omap_dss_device sdp3430_lcd_device = { - .name = "lcd", - .driver_name = "sharp_ls_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &sdp3430_lcd_data, +static struct connector_dvi_platform_data sdp3430_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = -1, +static struct platform_device sdp3430_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &sdp3430_dvi_connector_pdata, }; -static struct omap_dss_device sdp3430_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct encoder_tfp410_platform_data sdp3430_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, }; -static struct omap_dss_device sdp3430_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device sdp3430_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &sdp3430_tfp410_pdata, }; +static struct connector_atv_platform_data sdp3430_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; -static struct omap_dss_device *sdp3430_dss_devices[] = { - &sdp3430_lcd_device, - &sdp3430_dvi_device, - &sdp3430_tv_device, +static struct platform_device sdp3430_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &sdp3430_tv_pdata, }; static struct omap_dss_board_info sdp3430_dss_data = { - .num_devices = ARRAY_SIZE(sdp3430_dss_devices), - .devices = sdp3430_dss_devices, - .default_device = &sdp3430_lcd_device, + .default_display_name = "lcd", }; static struct omap2_hsmmc_info mmc[] = { @@ -583,6 +595,11 @@ static void __init omap_3430sdp_init(void) omap_hsmmc_init(mmc); omap3430_i2c_init(); omap_display_init(&sdp3430_dss_data); + platform_device_register(&sdp3430_lcd_device); + platform_device_register(&sdp3430_tfp410_device); + platform_device_register(&sdp3430_dvi_connector_device); + platform_device_register(&sdp3430_tv_connector_device); + if (omap_rev() > OMAP3430_REV_ES1_0) gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2; else diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c index fc53911d0d13..0d499a1878f6 100644 --- a/arch/arm/mach-omap2/board-am3517crane.c +++ b/arch/arm/mach-omap2/board-am3517crane.c @@ -110,8 +110,6 @@ static void __init am3517_crane_i2c_init(void) static void __init am3517_crane_init(void) { - int ret; - omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); omap_serial_init(); omap_sdrc_init(NULL, NULL); diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c index d63f14b534b5..543d9a882de3 100644 --- a/arch/arm/mach-omap2/board-am3517evm.c +++ b/arch/arm/mach-omap2/board-am3517evm.c @@ -21,7 +21,7 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/gpio.h> -#include <linux/i2c/pca953x.h> +#include <linux/platform_data/pca953x.h> #include <linux/can/platform/ti_hecc.h> #include <linux/davinci_emac.h> #include <linux/mmc/host.h> @@ -120,56 +120,95 @@ static int __init am3517_evm_i2c_init(void) return 0; } -static struct panel_generic_dpi_data lcd_panel = { - .name = "sharp_lq", - .num_gpios = 3, - .gpios = { - LCD_PANEL_PWR, - LCD_PANEL_BKLIGHT_PWR, - LCD_PANEL_PWM, - }, +static const struct display_timing am3517_evm_lcd_videomode = { + .pixelclock = { 0, 9000000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 2, 0 }, + .hsync_len = { 0, 42, 0 }, + + .vactive = { 0, 272, 0 }, + .vfront_porch = { 0, 3, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 11, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_LOW | DISPLAY_FLAGS_PIXDATA_POSEDGE, +}; + +static struct panel_dpi_platform_data am3517_evm_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &am3517_evm_lcd_videomode, + + .enable_gpio = LCD_PANEL_PWR, + .backlight_gpio = LCD_PANEL_BKLIGHT_PWR, +}; + +static struct platform_device am3517_evm_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &am3517_evm_lcd_pdata, }; -static struct omap_dss_device am3517_evm_lcd_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "lcd", - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 16, +static struct connector_dvi_platform_data am3517_evm_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct omap_dss_device am3517_evm_tv_device = { - .type = OMAP_DISPLAY_TYPE_VENC, - .name = "tv", - .driver_name = "venc", - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device am3517_evm_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &am3517_evm_dvi_connector_pdata, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = -1, +static struct encoder_tfp410_platform_data am3517_evm_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, }; -static struct omap_dss_device am3517_evm_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device am3517_evm_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &am3517_evm_tfp410_pdata, }; -static struct omap_dss_device *am3517_evm_dss_devices[] = { - &am3517_evm_lcd_device, - &am3517_evm_tv_device, - &am3517_evm_dvi_device, +static struct connector_atv_platform_data am3517_evm_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device am3517_evm_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &am3517_evm_tv_pdata, }; static struct omap_dss_board_info am3517_evm_dss_data = { - .num_devices = ARRAY_SIZE(am3517_evm_dss_devices), - .devices = am3517_evm_dss_devices, - .default_device = &am3517_evm_lcd_device, + .default_display_name = "lcd", }; +static void __init am3517_evm_display_init(void) +{ + gpio_request_one(LCD_PANEL_PWM, GPIOF_OUT_INIT_HIGH, "lcd panel pwm"); + + omap_display_init(&am3517_evm_dss_data); + + platform_device_register(&am3517_evm_tfp410_device); + platform_device_register(&am3517_evm_dvi_connector_device); + platform_device_register(&am3517_evm_lcd_device); + platform_device_register(&am3517_evm_tv_connector_device); +} + /* * Board initialization */ @@ -295,7 +334,9 @@ static void __init am3517_evm_init(void) omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); am3517_evm_i2c_init(); - omap_display_init(&am3517_evm_dss_data); + + am3517_evm_display_init(); + omap_serial_init(); omap_sdrc_init(NULL, NULL); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index d4622ed26252..33d159e2386e 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -190,52 +190,81 @@ static inline void cm_t35_init_nand(void) {} #define CM_T35_LCD_BL_GPIO 58 #define CM_T35_DVI_EN_GPIO 54 -static struct panel_generic_dpi_data lcd_panel = { - .name = "toppoly_tdo35s", - .num_gpios = 1, - .gpios = { - CM_T35_LCD_BL_GPIO, - }, +static const struct display_timing cm_t35_lcd_videomode = { + .pixelclock = { 0, 26000000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 104, 0 }, + .hback_porch = { 0, 8, 0 }, + .hsync_len = { 0, 8, 0 }, + + .vactive = { 0, 640, 0 }, + .vfront_porch = { 0, 4, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 2, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE, +}; + +static struct panel_dpi_platform_data cm_t35_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .display_timing = &cm_t35_lcd_videomode, + + .enable_gpio = -1, + .backlight_gpio = CM_T35_LCD_BL_GPIO, +}; + +static struct platform_device cm_t35_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &cm_t35_lcd_pdata, }; -static struct omap_dss_device cm_t35_lcd_device = { - .name = "lcd", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 18, +static struct connector_dvi_platform_data cm_t35_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = CM_T35_DVI_EN_GPIO, - .i2c_bus_num = -1, +static struct platform_device cm_t35_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &cm_t35_dvi_connector_pdata, }; -static struct omap_dss_device cm_t35_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct encoder_tfp410_platform_data cm_t35_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = CM_T35_DVI_EN_GPIO, }; -static struct omap_dss_device cm_t35_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device cm_t35_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &cm_t35_tfp410_pdata, }; -static struct omap_dss_device *cm_t35_dss_devices[] = { - &cm_t35_lcd_device, - &cm_t35_dvi_device, - &cm_t35_tv_device, +static struct connector_atv_platform_data cm_t35_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device cm_t35_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &cm_t35_tv_pdata, }; static struct omap_dss_board_info cm_t35_dss_data = { - .num_devices = ARRAY_SIZE(cm_t35_dss_devices), - .devices = cm_t35_dss_devices, - .default_device = &cm_t35_dvi_device, + .default_display_name = "dvi", }; static struct omap2_mcspi_device_config tdo24m_mcspi_config = { @@ -280,6 +309,11 @@ static void __init cm_t35_init_display(void) pr_err("CM-T35: failed to register DSS device\n"); gpio_free(CM_T35_LCD_EN_GPIO); } + + platform_device_register(&cm_t35_tfp410_device); + platform_device_register(&cm_t35_dvi_connector_device); + platform_device_register(&cm_t35_lcd_device); + platform_device_register(&cm_t35_tv_connector_device); } static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = { diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index f1d91ba5d1ac..cdc4fb9960a9 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -112,50 +112,81 @@ static struct regulator_consumer_supply devkit8000_vio_supply[] = { REGULATOR_SUPPLY("vcc", "spi2.0"), }; -static struct panel_generic_dpi_data lcd_panel = { - .name = "innolux_at070tn83", - /* gpios filled in code */ +static const struct display_timing devkit8000_lcd_videomode = { + .pixelclock = { 0, 40000000, 0 }, + + .hactive = { 0, 800, 0 }, + .hfront_porch = { 0, 1, 0 }, + .hback_porch = { 0, 1, 0 }, + .hsync_len = { 0, 48, 0 }, + + .vactive = { 0, 480, 0 }, + .vfront_porch = { 0, 12, 0 }, + .vback_porch = { 0, 25, 0 }, + .vsync_len = { 0, 3, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device devkit8000_lcd_device = { +static struct panel_dpi_platform_data devkit8000_lcd_pdata = { .name = "lcd", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd_panel, - .phy.dpi.data_lines = 24, + .source = "dpi.0", + + .data_lines = 24, + + .display_timing = &devkit8000_lcd_videomode, + + .enable_gpio = -1, /* filled in code */ + .backlight_gpio = -1, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = -1, - .i2c_bus_num = 1, +static struct platform_device devkit8000_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &devkit8000_lcd_pdata, }; -static struct omap_dss_device devkit8000_dvi_device = { +static struct connector_dvi_platform_data devkit8000_dvi_connector_pdata = { .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, + .source = "tfp410.0", + .i2c_bus_num = 1, }; -static struct omap_dss_device devkit8000_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct platform_device devkit8000_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &devkit8000_dvi_connector_pdata, }; +static struct encoder_tfp410_platform_data devkit8000_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, /* filled in code */ +}; -static struct omap_dss_device *devkit8000_dss_devices[] = { - &devkit8000_lcd_device, - &devkit8000_dvi_device, - &devkit8000_tv_device, +static struct platform_device devkit8000_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &devkit8000_tfp410_pdata, +}; + +static struct connector_atv_platform_data devkit8000_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, +}; + +static struct platform_device devkit8000_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &devkit8000_tv_pdata, }; static struct omap_dss_board_info devkit8000_dss_data = { - .num_devices = ARRAY_SIZE(devkit8000_dss_devices), - .devices = devkit8000_dss_devices, - .default_device = &devkit8000_lcd_device, + .default_display_name = "lcd", }; static uint32_t board_keymap[] = { @@ -204,11 +235,10 @@ static int devkit8000_twl_gpio_setup(struct device *dev, gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1; /* TWL4030_GPIO_MAX + 0 is "LCD_PWREN" (out, active high) */ - lcd_panel.num_gpios = 1; - lcd_panel.gpios[0] = gpio + TWL4030_GPIO_MAX + 0; + devkit8000_lcd_pdata.enable_gpio = gpio + TWL4030_GPIO_MAX + 0; /* gpio + 7 is "DVI_PD" (out, active low) */ - dvi_panel.power_down_gpio = gpio + 7; + devkit8000_tfp410_pdata.power_down_gpio = gpio + 7; return 0; } @@ -413,6 +443,10 @@ static struct platform_device *devkit8000_devices[] __initdata = { &leds_gpio, &keys_gpio, &omap_dm9000_dev, + &devkit8000_lcd_device, + &devkit8000_tfp410_device, + &devkit8000_dvi_connector_device, + &devkit8000_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c index be5d005ebad2..39c78387ddec 100644 --- a/arch/arm/mach-omap2/board-generic.c +++ b/arch/arm/mach-omap2/board-generic.c @@ -222,3 +222,22 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)") .dt_compat = am43_boards_compat, MACHINE_END #endif + +#ifdef CONFIG_SOC_DRA7XX +static const char *dra7xx_boards_compat[] __initdata = { + "ti,dra7", + NULL, +}; + +DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)") + .reserve = omap_reserve, + .smp = smp_ops(omap4_smp_ops), + .map_io = omap5_map_io, + .init_early = dra7xx_init_early, + .init_irq = omap_gic_of_init, + .init_machine = omap_generic_init, + .init_time = omap5_realtime_timer_init, + .dt_compat = dra7xx_boards_compat, + .restart = omap44xx_restart, +MACHINE_END +#endif diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c index 69c0acf5aa63..87e41a8b8d46 100644 --- a/arch/arm/mach-omap2/board-h4.c +++ b/arch/arm/mach-omap2/board-h4.c @@ -194,30 +194,48 @@ static struct platform_device h4_flash_device = { .resource = &h4_flash_resource, }; -static struct platform_device *h4_devices[] __initdata = { - &h4_flash_device, +static const struct display_timing cm_t35_lcd_videomode = { + .pixelclock = { 0, 6250000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 15, 0 }, + .hback_porch = { 0, 60, 0 }, + .hsync_len = { 0, 15, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 1, 0 }, + .vback_porch = { 0, 1, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct panel_generic_dpi_data h4_panel_data = { - .name = "h4", +static struct panel_dpi_platform_data cm_t35_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 16, + + .display_timing = &cm_t35_lcd_videomode, + + .enable_gpio = -1, + .backlight_gpio = -1, }; -static struct omap_dss_device h4_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 16, - .data = &h4_panel_data, +static struct platform_device cm_t35_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &cm_t35_lcd_pdata, }; -static struct omap_dss_device *h4_dss_devices[] = { - &h4_lcd_device, +static struct platform_device *h4_devices[] __initdata = { + &h4_flash_device, + &cm_t35_lcd_device, }; static struct omap_dss_board_info h4_dss_data = { - .num_devices = ARRAY_SIZE(h4_dss_devices), - .devices = h4_dss_devices, - .default_device = &h4_lcd_device, + .default_display_name = "lcd", }; /* 2420 Sysboot setup (2430 is different) */ diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c index 87e65dde8e13..06dbb2d3d38b 100644 --- a/arch/arm/mach-omap2/board-igep0020.c +++ b/arch/arm/mach-omap2/board-igep0020.c @@ -429,31 +429,39 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = { .setup = igep_twl_gpio_setup, }; -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = IGEP2_GPIO_DVI_PUP, +static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device igep2_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device omap3stalker_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3stalker_dvi_connector_pdata, }; -static struct omap_dss_device *igep2_dss_devices[] = { - &igep2_dvi_device +static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = IGEP2_GPIO_DVI_PUP, +}; + +static struct platform_device omap3stalker_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3stalker_tfp410_pdata, }; static struct omap_dss_board_info igep2_dss_data = { - .num_devices = ARRAY_SIZE(igep2_dss_devices), - .devices = igep2_dss_devices, - .default_device = &igep2_dvi_device, + .default_display_name = "dvi", }; static struct platform_device *igep_devices[] __initdata = { &igep_vwlan_device, + &omap3stalker_tfp410_device, + &omap3stalker_dvi_connector_device, }; static int igep2_keymap[] = { diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 62e4f701b63b..dd8da2c5399f 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -184,45 +184,70 @@ static inline void __init ldp_init_smsc911x(void) #define LCD_PANEL_RESET_GPIO 55 #define LCD_PANEL_QVGA_GPIO 56 -static struct panel_generic_dpi_data ldp_panel_data = { - .name = "nec_nl2432dr22-11b", - .num_gpios = 4, - /* gpios filled in code */ +static const struct display_timing ldp_lcd_videomode = { + .pixelclock = { 0, 5400000, 0 }, + + .hactive = { 0, 240, 0 }, + .hfront_porch = { 0, 3, 0 }, + .hback_porch = { 0, 39, 0 }, + .hsync_len = { 0, 3, 0 }, + + .vactive = { 0, 320, 0 }, + .vfront_porch = { 0, 2, 0 }, + .vback_porch = { 0, 7, 0 }, + .vsync_len = { 0, 1, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct omap_dss_device ldp_lcd_device = { - .name = "lcd", - .driver_name = "generic_dpi_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 18, - .data = &ldp_panel_data, +static struct panel_dpi_platform_data ldp_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .display_timing = &ldp_lcd_videomode, + + .enable_gpio = -1, /* filled in code */ + .backlight_gpio = -1, /* filled in code */ }; -static struct omap_dss_device *ldp_dss_devices[] = { - &ldp_lcd_device, +static struct platform_device ldp_lcd_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &ldp_lcd_pdata, }; static struct omap_dss_board_info ldp_dss_data = { - .num_devices = ARRAY_SIZE(ldp_dss_devices), - .devices = ldp_dss_devices, - .default_device = &ldp_lcd_device, + .default_display_name = "lcd", }; static void __init ldp_display_init(void) { - ldp_panel_data.gpios[2] = LCD_PANEL_RESET_GPIO; - ldp_panel_data.gpios[3] = LCD_PANEL_QVGA_GPIO; + int r; + + static struct gpio gpios[] __initdata = { + {LCD_PANEL_RESET_GPIO, GPIOF_OUT_INIT_HIGH, "LCD RESET"}, + {LCD_PANEL_QVGA_GPIO, GPIOF_OUT_INIT_HIGH, "LCD QVGA"}, + }; + + r = gpio_request_array(gpios, ARRAY_SIZE(gpios)); + if (r) { + pr_err("Cannot request LCD GPIOs, error %d\n", r); + return; + } omap_display_init(&ldp_dss_data); } static int ldp_twl_gpio_setup(struct device *dev, unsigned gpio, unsigned ngpio) { - ldp_panel_data.gpios[0] = gpio + 7; - ldp_panel_data.gpio_invert[0] = true; + /* LCD enable GPIO */ + ldp_lcd_pdata.enable_gpio = gpio + 7; - ldp_panel_data.gpios[1] = gpio + 15; - ldp_panel_data.gpio_invert[1] = true; + /* Backlight enable GPIO */ + ldp_lcd_pdata.backlight_gpio = gpio + 15; return 0; } @@ -322,6 +347,7 @@ static struct omap2_hsmmc_info mmc[] __initdata = { static struct platform_device *ldp_devices[] __initdata = { &ldp_gpio_keys_device, + &ldp_lcd_device, }; #ifdef CONFIG_OMAP_MUX diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index 04c116555412..f26918467efc 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -33,7 +33,7 @@ #include <linux/mtd/nand.h> #include <linux/mmc/host.h> #include <linux/usb/phy.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include <linux/regulator/machine.h> #include <linux/i2c/twl.h> @@ -225,35 +225,46 @@ static struct mtd_partition omap3beagle_nand_partitions[] = { /* DSS */ -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = -1, +static struct connector_dvi_platform_data beagle_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device beagle_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device beagle_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &beagle_dvi_connector_pdata, }; -static struct omap_dss_device beagle_tv_device = { +static struct encoder_tfp410_platform_data beagle_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, +}; + +static struct platform_device beagle_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &beagle_tfp410_pdata, +}; + +static struct connector_atv_platform_data beagle_tv_pdata = { .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *beagle_dss_devices[] = { - &beagle_dvi_device, - &beagle_tv_device, +static struct platform_device beagle_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &beagle_tv_pdata, }; static struct omap_dss_board_info beagle_dss_data = { - .num_devices = ARRAY_SIZE(beagle_dss_devices), - .devices = beagle_dss_devices, - .default_device = &beagle_dvi_device, + .default_display_name = "dvi", }; #include "sdram-micron-mt46h32m32lf-6.h" @@ -279,7 +290,7 @@ static struct regulator_consumer_supply beagle_vsim_supply[] = { static struct gpio_led gpio_leds[]; /* PHY's VCC regulator might be added later, so flag that we need it */ -static struct nop_usb_xceiv_platform_data hsusb2_phy_data = { +static struct usb_phy_gen_xceiv_platform_data hsusb2_phy_data = { .needs_vcc = true, }; @@ -332,7 +343,11 @@ static int beagle_twl_gpio_setup(struct device *dev, if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC")) pr_err("%s: unable to configure EHCI_nOC\n", __func__); } - dvi_panel.power_down_gpio = beagle_config.dvi_pd_gpio; + beagle_tfp410_pdata.power_down_gpio = beagle_config.dvi_pd_gpio; + + platform_device_register(&beagle_tfp410_device); + platform_device_register(&beagle_dvi_connector_device); + platform_device_register(&beagle_tv_connector_device); /* TWL4030_GPIO_MAX i.e. LED_GPO controls HS USB Port 2 power */ phy_data[0].vcc_gpio = gpio + TWL4030_GPIO_MAX; @@ -547,6 +562,7 @@ static void __init omap3_beagle_init(void) if (gpio_is_valid(beagle_config.dvi_pd_gpio)) omap_mux_init_gpio(beagle_config.dvi_pd_gpio, OMAP_PIN_OUTPUT); omap_display_init(&beagle_dss_data); + omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c index 8c026269baca..18143873346c 100644 --- a/arch/arm/mach-omap2/board-omap3evm.c +++ b/arch/arm/mach-omap2/board-omap3evm.c @@ -33,7 +33,7 @@ #include <linux/i2c/twl.h> #include <linux/usb/otg.h> #include <linux/usb/musb.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include <linux/smsc911x.h> #include <linux/wl12xx.h> @@ -166,14 +166,6 @@ static inline void __init omap3evm_init_smsc911x(void) { return; } */ #define OMAP3EVM_DVI_PANEL_EN_GPIO 199 -static struct panel_sharp_ls037v7dw01_data omap3_evm_lcd_data = { - .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, - .ini_gpio = OMAP3EVM_LCD_PANEL_INI, - .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, - .lr_gpio = OMAP3EVM_LCD_PANEL_LR, - .ud_gpio = OMAP3EVM_LCD_PANEL_UD, -}; - #ifdef CONFIG_BROKEN static void __init omap3_evm_display_init(void) { @@ -196,44 +188,65 @@ static void __init omap3_evm_display_init(void) } #endif -static struct omap_dss_device omap3_evm_lcd_device = { - .name = "lcd", - .driver_name = "sharp_ls_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 18, - .data = &omap3_evm_lcd_data, +static struct panel_sharp_ls037v7dw01_platform_data omap3_evm_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 18, + + .resb_gpio = OMAP3EVM_LCD_PANEL_RESB, + .ini_gpio = OMAP3EVM_LCD_PANEL_INI, + .mo_gpio = OMAP3EVM_LCD_PANEL_QVGA, + .lr_gpio = OMAP3EVM_LCD_PANEL_LR, + .ud_gpio = OMAP3EVM_LCD_PANEL_UD, +}; + +static struct platform_device omap3_evm_lcd_device = { + .name = "panel-sharp-ls037v7dw01", + .id = 0, + .dev.platform_data = &omap3_evm_lcd_pdata, +}; + +static struct connector_dvi_platform_data omap3_evm_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, +}; + +static struct platform_device omap3_evm_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3_evm_dvi_connector_pdata, }; -static struct omap_dss_device omap3_evm_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct encoder_tfp410_platform_data omap3_evm_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = OMAP3EVM_DVI_PANEL_EN_GPIO, - .i2c_bus_num = -1, +static struct platform_device omap3_evm_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3_evm_tfp410_pdata, }; -static struct omap_dss_device omap3_evm_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct connector_atv_platform_data omap3_evm_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *omap3_evm_dss_devices[] = { - &omap3_evm_lcd_device, - &omap3_evm_tv_device, - &omap3_evm_dvi_device, +static struct platform_device omap3_evm_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &omap3_evm_tv_pdata, }; static struct omap_dss_board_info omap3_evm_dss_data = { - .num_devices = ARRAY_SIZE(omap3_evm_dss_devices), - .devices = omap3_evm_dss_devices, - .default_device = &omap3_evm_lcd_device, + .default_display_name = "lcd", }; static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = { @@ -468,7 +481,7 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = { static struct regulator_consumer_supply omap3evm_vaux2_supplies[] = { REGULATOR_SUPPLY("VDD_CSIPHY1", "omap3isp"), /* OMAP ISP */ REGULATOR_SUPPLY("VDD_CSIPHY2", "omap3isp"), /* OMAP ISP */ - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ REGULATOR_SUPPLY("vaux2", NULL), }; @@ -678,6 +691,10 @@ static void __init omap3_evm_init(void) omap3_evm_i2c_init(); omap_display_init(&omap3_evm_dss_data); + platform_device_register(&omap3_evm_lcd_device); + platform_device_register(&omap3_evm_tfp410_device); + platform_device_register(&omap3_evm_dvi_connector_device); + platform_device_register(&omap3_evm_tv_connector_device); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, NULL); diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c index b1547a0edfcd..de1bc6bbe585 100644 --- a/arch/arm/mach-omap2/board-omap3pandora.c +++ b/arch/arm/mach-omap2/board-omap3pandora.c @@ -231,34 +231,21 @@ static struct twl4030_keypad_data pandora_kp_data = { .rep = 1, }; -static struct panel_tpo_td043_data lcd_data = { - .nreset_gpio = 157, -}; - -static struct omap_dss_device pandora_lcd_device = { - .name = "lcd", - .driver_name = "tpo_td043mtea1_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .data = &lcd_data, -}; - -static struct omap_dss_device pandora_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static struct connector_atv_platform_data pandora_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device *pandora_dss_devices[] = { - &pandora_lcd_device, - &pandora_tv_device, +static struct platform_device pandora_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &pandora_tv_pdata, }; static struct omap_dss_board_info pandora_dss_data = { - .num_devices = ARRAY_SIZE(pandora_dss_devices), - .devices = pandora_dss_devices, - .default_device = &pandora_lcd_device, + .default_display_name = "lcd", }; static void pandora_wl1251_init_card(struct mmc_card *card) @@ -348,11 +335,11 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = { }; static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = { - REGULATOR_SUPPLY("vcc", "display0"), + REGULATOR_SUPPLY("vcc", "spi1.1"), }; static struct regulator_consumer_supply pandora_usb_phy_supply[] = { - REGULATOR_SUPPLY("vcc", "nop_usb_xceiv.2"), /* hsusb port 2 */ + REGULATOR_SUPPLY("vcc", "usb_phy_gen_xceiv.2"), /* hsusb port 2 */ }; /* ads7846 on SPI and 2 nub controllers on I2C */ @@ -529,13 +516,21 @@ static int __init omap3pandora_i2c_init(void) return 0; } +static struct panel_tpo_td043mtea1_platform_data pandora_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", + + .data_lines = 24, + .nreset_gpio = 157, +}; + static struct spi_board_info omap3pandora_spi_board_info[] __initdata = { { - .modalias = "tpo_td043mtea1_panel_spi", + .modalias = "panel-tpo-td043mtea1", .bus_num = 1, .chip_select = 1, .max_speed_hz = 375000, - .platform_data = &pandora_lcd_device, + .platform_data = &pandora_lcd_pdata, } }; @@ -580,6 +575,7 @@ static struct platform_device *omap3pandora_devices[] __initdata = { &pandora_keys_gpio, &pandora_vwlan_device, &pandora_backlight, + &pandora_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c index d37e6b187ae4..ba8342fef799 100644 --- a/arch/arm/mach-omap2/board-omap3stalker.c +++ b/arch/arm/mach-omap2/board-omap3stalker.c @@ -93,40 +93,50 @@ static void __init omap3_stalker_display_init(void) { return; } +static struct connector_dvi_platform_data omap3stalker_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = -1, +}; -static struct omap_dss_device omap3_stalker_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, -#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, -#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) - .u.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -#endif +static struct platform_device omap3stalker_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap3stalker_dvi_connector_pdata, }; -static struct tfp410_platform_data dvi_panel = { - .power_down_gpio = DSS_ENABLE_GPIO, - .i2c_bus_num = -1, +static struct encoder_tfp410_platform_data omap3stalker_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = DSS_ENABLE_GPIO, }; -static struct omap_dss_device omap3_stalker_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device omap3stalker_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap3stalker_tfp410_pdata, +}; + +static struct connector_atv_platform_data omap3stalker_tv_pdata = { + .name = "tv", + .source = "venc.0", +#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO) + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, +#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE) + .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, +#endif + .invert_polarity = false, }; -static struct omap_dss_device *omap3_stalker_dss_devices[] = { - &omap3_stalker_tv_device, - &omap3_stalker_dvi_device, +static struct platform_device omap3stalker_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &omap3stalker_tv_pdata, }; static struct omap_dss_board_info omap3_stalker_dss_data = { - .num_devices = ARRAY_SIZE(omap3_stalker_dss_devices), - .devices = omap3_stalker_dss_devices, - .default_device = &omap3_stalker_dvi_device, + .default_display_name = "dvi", }; static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = { @@ -356,6 +366,9 @@ static struct usbhs_phy_data phy_data[] __initdata = { static struct platform_device *omap3_stalker_devices[] __initdata = { &keys_gpio, + &omap3stalker_tfp410_device, + &omap3stalker_dvi_connector_device, + &omap3stalker_tv_connector_device, }; static struct usbhs_omap_platform_data usbhs_bdata __initdata = { diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c index 5748b5d06c23..f6d384111911 100644 --- a/arch/arm/mach-omap2/board-overo.c +++ b/arch/arm/mach-omap2/board-overo.c @@ -72,6 +72,9 @@ #define OVERO_SMSC911X2_CS 4 #define OVERO_SMSC911X2_GPIO 65 +/* whether to register LCD35 instead of LCD43 */ +static bool overo_use_lcd35; + #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) @@ -149,78 +152,94 @@ static inline void __init overo_init_smsc911x(void) { return; } #define OVERO_GPIO_LCD_EN 144 #define OVERO_GPIO_LCD_BL 145 -static struct tfp410_platform_data dvi_panel = { - .i2c_bus_num = 3, - .power_down_gpio = -1, +static struct connector_atv_platform_data overo_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO, + .invert_polarity = false, }; -static struct omap_dss_device overo_dvi_device = { - .name = "dvi", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "tfp410", - .data = &dvi_panel, - .phy.dpi.data_lines = 24, +static struct platform_device overo_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &overo_tv_pdata, }; -static struct omap_dss_device overo_tv_device = { - .name = "tv", - .driver_name = "venc", - .type = OMAP_DISPLAY_TYPE_VENC, - .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, +static const struct display_timing overo_lcd43_videomode = { + .pixelclock = { 0, 9200000, 0 }, + + .hactive = { 0, 480, 0 }, + .hfront_porch = { 0, 8, 0 }, + .hback_porch = { 0, 4, 0 }, + .hsync_len = { 0, 41, 0 }, + + .vactive = { 0, 272, 0 }, + .vfront_porch = { 0, 4, 0 }, + .vback_porch = { 0, 2, 0 }, + .vsync_len = { 0, 10, 0 }, + + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE, }; -static struct panel_generic_dpi_data lcd43_panel = { - .name = "samsung_lte430wq_f0c", - .num_gpios = 2, - .gpios = { - OVERO_GPIO_LCD_EN, - OVERO_GPIO_LCD_BL - }, +static struct panel_dpi_platform_data overo_lcd43_pdata = { + .name = "lcd43", + .source = "dpi.0", + + .data_lines = 24, + + .display_timing = &overo_lcd43_videomode, + + .enable_gpio = OVERO_GPIO_LCD_EN, + .backlight_gpio = OVERO_GPIO_LCD_BL, }; -static struct omap_dss_device overo_lcd43_device = { - .name = "lcd43", - .type = OMAP_DISPLAY_TYPE_DPI, - .driver_name = "generic_dpi_panel", - .data = &lcd43_panel, - .phy.dpi.data_lines = 24, +static struct platform_device overo_lcd43_device = { + .name = "panel-dpi", + .id = 0, + .dev.platform_data = &overo_lcd43_pdata, }; -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) -static struct panel_generic_dpi_data lcd35_panel = { - .num_gpios = 2, - .gpios = { - OVERO_GPIO_LCD_EN, - OVERO_GPIO_LCD_BL - }, +static struct connector_dvi_platform_data overo_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 3, }; -static struct omap_dss_device overo_lcd35_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "lcd35", - .driver_name = "lgphilips_lb035q02_panel", - .phy.dpi.data_lines = 24, - .data = &lcd35_panel, +static struct platform_device overo_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &overo_dvi_connector_pdata, }; -#endif -static struct omap_dss_device *overo_dss_devices[] = { - &overo_dvi_device, - &overo_tv_device, -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) - &overo_lcd35_device, -#endif - &overo_lcd43_device, +static struct encoder_tfp410_platform_data overo_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = -1, +}; + +static struct platform_device overo_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &overo_tfp410_pdata, }; static struct omap_dss_board_info overo_dss_data = { - .num_devices = ARRAY_SIZE(overo_dss_devices), - .devices = overo_dss_devices, - .default_device = &overo_dvi_device, + .default_display_name = "lcd43", }; +static void __init overo_display_init(void) +{ + omap_display_init(&overo_dss_data); + + if (!overo_use_lcd35) + platform_device_register(&overo_lcd43_device); + platform_device_register(&overo_tfp410_device); + platform_device_register(&overo_dvi_connector_device); + platform_device_register(&overo_tv_connector_device); +} + static struct mtd_partition overo_nand_partitions[] = { { .name = "xloader", @@ -408,24 +427,41 @@ static int __init overo_i2c_init(void) return 0; } +static struct panel_lb035q02_platform_data overo_lcd35_pdata = { + .name = "lcd35", + .source = "dpi.0", + + .data_lines = 24, + + .enable_gpio = OVERO_GPIO_LCD_EN, + .backlight_gpio = OVERO_GPIO_LCD_BL, +}; + +/* + * NOTE: We need to add either the lgphilips panel, or the lcd43 panel. The + * selection is done based on the overo_use_lcd35 field. If new SPI + * devices are added here, extra work is needed to make only the lgphilips panel + * affected by the overo_use_lcd35 field. + */ static struct spi_board_info overo_spi_board_info[] __initdata = { -#if defined(CONFIG_PANEL_LGPHILIPS_LB035Q02) || \ - defined(CONFIG_PANEL_LGPHILIPS_LB035Q02_MODULE) { - .modalias = "lgphilips_lb035q02_panel-spi", + .modalias = "panel_lgphilips_lb035q02", .bus_num = 1, .chip_select = 1, .max_speed_hz = 500000, .mode = SPI_MODE_3, + .platform_data = &overo_lcd35_pdata, }, -#endif }; static int __init overo_spi_init(void) { overo_ads7846_init(); - spi_register_board_info(overo_spi_board_info, - ARRAY_SIZE(overo_spi_board_info)); + + if (overo_use_lcd35) { + spi_register_board_info(overo_spi_board_info, + ARRAY_SIZE(overo_spi_board_info)); + } return 0; } @@ -463,11 +499,13 @@ static void __init overo_init(void) { int ret; + if (strstr(boot_command_line, "omapdss.def_disp=lcd35")) + overo_use_lcd35 = true; + regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies)); omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); overo_i2c_init(); omap_hsmmc_init(mmc); - omap_display_init(&overo_dss_data); omap_serial_init(); omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); @@ -484,6 +522,8 @@ static void __init overo_init(void) overo_init_keys(); omap_twl4030_audio_init("overo", NULL); + overo_display_init(); + /* Ensure SDRC pins are mux'd for self-refresh */ omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT); omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT); diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c index 9c2dd102fbbb..c3270c0f1fce 100644 --- a/arch/arm/mach-omap2/board-rx51-peripherals.c +++ b/arch/arm/mach-omap2/board-rx51-peripherals.c @@ -45,6 +45,8 @@ #include <linux/platform_data/tsl2563.h> #include <linux/lis3lv02d.h> +#include <video/omap-panel-data.h> + #if defined(CONFIG_IR_RX51) || defined(CONFIG_IR_RX51_MODULE) #include <media/ir-rx51.h> #endif @@ -226,6 +228,15 @@ static struct lp55xx_platform_data rx51_lp5523_platform_data = { }; #endif +#define RX51_LCD_RESET_GPIO 90 + +static struct panel_acx565akm_platform_data acx_pdata = { + .name = "lcd", + .source = "sdi.0", + .reset_gpio = RX51_LCD_RESET_GPIO, + .datapairs = 2, +}; + static struct omap2_mcspi_device_config wl1251_mcspi_config = { .turbo_mode = 0, }; @@ -254,6 +265,7 @@ static struct spi_board_info rx51_peripherals_spi_board_info[] __initdata = { .chip_select = 2, .max_speed_hz = 6000000, .controller_data = &mipid_mcspi_config, + .platform_data = &acx_pdata, }, [RX51_SPI_TSC2005] = { .modalias = "tsc2005", diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c index bdd1e3a179e1..43a90c8d6837 100644 --- a/arch/arm/mach-omap2/board-rx51-video.c +++ b/arch/arm/mach-omap2/board-rx51-video.c @@ -29,34 +29,21 @@ #if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE) -static struct panel_acx565akm_data lcd_data = { - .reset_gpio = RX51_LCD_RESET_GPIO, +static struct connector_atv_platform_data rx51_tv_pdata = { + .name = "tv", + .source = "venc.0", + .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE, + .invert_polarity = false, }; -static struct omap_dss_device rx51_lcd_device = { - .name = "lcd", - .driver_name = "panel-acx565akm", - .type = OMAP_DISPLAY_TYPE_SDI, - .phy.sdi.datapairs = 2, - .data = &lcd_data, -}; - -static struct omap_dss_device rx51_tv_device = { - .name = "tv", - .type = OMAP_DISPLAY_TYPE_VENC, - .driver_name = "venc", - .phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE, -}; - -static struct omap_dss_device *rx51_dss_devices[] = { - &rx51_lcd_device, - &rx51_tv_device, +static struct platform_device rx51_tv_connector_device = { + .name = "connector-analog-tv", + .id = 0, + .dev.platform_data = &rx51_tv_pdata, }; static struct omap_dss_board_info rx51_dss_board_info = { - .num_devices = ARRAY_SIZE(rx51_dss_devices), - .devices = rx51_dss_devices, - .default_device = &rx51_lcd_device, + .default_display_name = "lcd", }; static int __init rx51_video_init(void) @@ -71,6 +58,8 @@ static int __init rx51_video_init(void) omap_display_init(&rx51_dss_board_info); + platform_device_register(&rx51_tv_connector_device); + return 0; } diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c index c2a079cb76fc..3d8ecc1e05bd 100644 --- a/arch/arm/mach-omap2/board-zoom-display.c +++ b/arch/arm/mach-omap2/board-zoom-display.c @@ -25,32 +25,23 @@ #define LCD_PANEL_RESET_GPIO_PILOT 55 #define LCD_PANEL_QVGA_GPIO 56 -static struct panel_nec_nl8048_data zoom_lcd_data = { - /* res_gpio filled in code */ - .qvga_gpio = LCD_PANEL_QVGA_GPIO, -}; +static struct panel_nec_nl8048hl11_platform_data zoom_lcd_pdata = { + .name = "lcd", + .source = "dpi.0", -static struct omap_dss_device zoom_lcd_device = { - .name = "lcd", - .driver_name = "NEC_8048_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .data = &zoom_lcd_data, -}; + .data_lines = 24, -static struct omap_dss_device *zoom_dss_devices[] = { - &zoom_lcd_device, + .res_gpio = -1, /* filled in code */ + .qvga_gpio = LCD_PANEL_QVGA_GPIO, }; static struct omap_dss_board_info zoom_dss_data = { - .num_devices = ARRAY_SIZE(zoom_dss_devices), - .devices = zoom_dss_devices, - .default_device = &zoom_lcd_device, + .default_display_name = "lcd", }; static void __init zoom_lcd_panel_init(void) { - zoom_lcd_data.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? + zoom_lcd_pdata.res_gpio = (omap_rev() > OMAP3430_REV_ES3_0) ? LCD_PANEL_RESET_GPIO_PROD : LCD_PANEL_RESET_GPIO_PILOT; } @@ -61,19 +52,20 @@ static struct omap2_mcspi_device_config dss_lcd_mcspi_config = { static struct spi_board_info nec_8048_spi_board_info[] __initdata = { [0] = { - .modalias = "nec_8048_spi", + .modalias = "panel-nec-nl8048hl11", .bus_num = 1, .chip_select = 2, .max_speed_hz = 375000, .controller_data = &dss_lcd_mcspi_config, + .platform_data = &zoom_lcd_pdata, }, }; void __init zoom_display_init(void) { omap_display_init(&zoom_dss_data); + zoom_lcd_panel_init(); spi_register_board_info(nec_8048_spi_board_info, ARRAY_SIZE(nec_8048_spi_board_info)); - zoom_lcd_panel_init(); } diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c index ba6534d7f155..865d30ee812f 100644 --- a/arch/arm/mach-omap2/cclock33xx_data.c +++ b/arch/arm/mach-omap2/cclock33xx_data.c @@ -421,6 +421,10 @@ static struct clk aes0_fck; DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); +static struct clk rng_fck; +DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL); +DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null); + /* * Modules clock nodes * @@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = { CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), CLK(NULL, "sha0_fck", &sha0_fck), CLK(NULL, "aes0_fck", &aes0_fck), + CLK(NULL, "rng_fck", &rng_fck), CLK(NULL, "timer1_fck", &timer1_fck), CLK(NULL, "timer2_fck", &timer2_fck), CLK(NULL, "timer3_fck", &timer3_fck), diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c index 88e37a474334..b237950eb8a3 100644 --- a/arch/arm/mach-omap2/cclock44xx_data.c +++ b/arch/arm/mach-omap2/cclock44xx_data.c @@ -1632,7 +1632,7 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck), CLK(NULL, "auxclk5_ck", &auxclk5_ck), CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck), - CLK("omap-gpmc", "fck", &dummy_ck), + CLK("50000000.gpmc", "fck", &dummy_ck), CLK("omap_i2c.1", "ick", &dummy_ck), CLK("omap_i2c.2", "ick", &dummy_ck), CLK("omap_i2c.3", "ick", &dummy_ck), @@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void) omap2_clk_disable_autoidle_all(); /* + * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL + * when its in bypass. So always lock USB before ABE DPLL. + */ + /* + * Lock USB DPLL on OMAP4 devices so that the L3INIT power + * domain can transition to retention state when not in use. + */ + rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); + if (rc) + pr_err("%s: failed to configure USB DPLL!\n", __func__); + + /* * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power * state when turning the ABE clock domain. Workaround this by * locking the ABE DPLL on boot. @@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void) if (rc) pr_err("%s: failed to configure ABE DPLL!\n", __func__); - /* - * Lock USB DPLL on OMAP4 devices so that the L3INIT power - * domain can transition to retention state when not in use. - */ - rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ); - if (rc) - pr_err("%s: failed to configure USB DPLL!\n", __func__); - return 0; } diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index daeecf1b89fa..4b03394fa0c5 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void); extern void __init am33xx_clockdomains_init(void); extern void __init omap44xx_clockdomains_init(void); extern void __init omap54xx_clockdomains_init(void); +extern void __init dra7xx_clockdomains_init(void); extern void clkdm_add_autodeps(struct clockdomain *clkdm); extern void clkdm_del_autodeps(struct clockdomain *clkdm); diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c new file mode 100644 index 000000000000..57d5df0c1fbd --- /dev/null +++ b/arch/arm/mach-omap2/clockdomains7xx_data.c @@ -0,0 +1,740 @@ +/* + * DRA7xx Clock domains framework + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Nokia Corporation + * + * Generated by code originally written by: + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/io.h> + +#include "clockdomain.h" +#include "cm1_7xx.h" +#include "cm2_7xx.h" + +#include "cm-regbits-7xx.h" +#include "prm7xx.h" +#include "prcm44xx.h" +#include "prcm_mpu7xx.h" + +/* Static Dependencies for DRA7xx Clock Domains */ + +static struct clkdm_dep cam_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dma_wkup_sleep_deps[] = { + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dsp1_wkup_sleep_deps[] = { + { .clkdm_name = "atl_clkdm" }, + { .clkdm_name = "cam_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dsp2_wkup_sleep_deps[] = { + { .clkdm_name = "atl_clkdm" }, + { .clkdm_name = "cam_clkdm" }, + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep dss_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep eve1_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep eve2_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep eve3_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep eve4_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep gmac_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep gpu_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep ipu1_wkup_sleep_deps[] = { + { .clkdm_name = "atl_clkdm" }, + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep ipu2_wkup_sleep_deps[] = { + { .clkdm_name = "atl_clkdm" }, + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep iva_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l3init_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l4per2_wkup_sleep_deps[] = { + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep l4sec_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep mpu_wkup_sleep_deps[] = { + { .clkdm_name = "cam_clkdm" }, + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "ipu2_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l3main1_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "pcie_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { .clkdm_name = "wkupaon_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep pcie_wkup_sleep_deps[] = { + { .clkdm_name = "atl_clkdm" }, + { .clkdm_name = "cam_clkdm" }, + { .clkdm_name = "dsp1_clkdm" }, + { .clkdm_name = "dsp2_clkdm" }, + { .clkdm_name = "dss_clkdm" }, + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "eve1_clkdm" }, + { .clkdm_name = "eve2_clkdm" }, + { .clkdm_name = "eve3_clkdm" }, + { .clkdm_name = "eve4_clkdm" }, + { .clkdm_name = "gmac_clkdm" }, + { .clkdm_name = "gpu_clkdm" }, + { .clkdm_name = "ipu_clkdm" }, + { .clkdm_name = "ipu1_clkdm" }, + { .clkdm_name = "iva_clkdm" }, + { .clkdm_name = "l3init_clkdm" }, + { .clkdm_name = "l4cfg_clkdm" }, + { .clkdm_name = "l4per_clkdm" }, + { .clkdm_name = "l4per2_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { .clkdm_name = "l4sec_clkdm" }, + { .clkdm_name = "vpe_clkdm" }, + { NULL }, +}; + +static struct clkdm_dep vpe_wkup_sleep_deps[] = { + { .clkdm_name = "emif_clkdm" }, + { .clkdm_name = "l4per3_clkdm" }, + { NULL }, +}; + +static struct clockdomain l4per3_7xx_clkdm = { + .name = "l4per3_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L4PER_INST, + .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS, + .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4per2_7xx_clkdm = { + .name = "l4per2_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L4PER_INST, + .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS, + .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT, + .wkdep_srcs = l4per2_wkup_sleep_deps, + .sleepdep_srcs = l4per2_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain mpu0_7xx_clkdm = { + .name = "mpu0_clkdm", + .pwrdm = { .name = "cpu0_pwrdm" }, + .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, + .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST, + .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain iva_7xx_clkdm = { + .name = "iva_clkdm", + .pwrdm = { .name = "iva_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_IVA_INST, + .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS, + .dep_bit = DRA7XX_IVA_STATDEP_SHIFT, + .wkdep_srcs = iva_wkup_sleep_deps, + .sleepdep_srcs = iva_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain coreaon_7xx_clkdm = { + .name = "coreaon_clkdm", + .pwrdm = { .name = "coreaon_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_COREAON_INST, + .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain ipu1_7xx_clkdm = { + .name = "ipu1_clkdm", + .pwrdm = { .name = "ipu_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS, + .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT, + .wkdep_srcs = ipu1_wkup_sleep_deps, + .sleepdep_srcs = ipu1_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain ipu2_7xx_clkdm = { + .name = "ipu2_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS, + .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT, + .wkdep_srcs = ipu2_wkup_sleep_deps, + .sleepdep_srcs = ipu2_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l3init_7xx_clkdm = { + .name = "l3init_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, + .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS, + .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT, + .wkdep_srcs = l3init_wkup_sleep_deps, + .sleepdep_srcs = l3init_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4sec_7xx_clkdm = { + .name = "l4sec_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L4PER_INST, + .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS, + .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT, + .wkdep_srcs = l4sec_wkup_sleep_deps, + .sleepdep_srcs = l4sec_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l3main1_7xx_clkdm = { + .name = "l3main1_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS, + .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain vpe_7xx_clkdm = { + .name = "vpe_clkdm", + .pwrdm = { .name = "vpe_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS, + .dep_bit = DRA7XX_VPE_STATDEP_SHIFT, + .wkdep_srcs = vpe_wkup_sleep_deps, + .sleepdep_srcs = vpe_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain mpu_7xx_clkdm = { + .name = "mpu_clkdm", + .pwrdm = { .name = "mpu_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS, + .wkdep_srcs = mpu_wkup_sleep_deps, + .sleepdep_srcs = mpu_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain custefuse_7xx_clkdm = { + .name = "custefuse_clkdm", + .pwrdm = { .name = "custefuse_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain ipu_7xx_clkdm = { + .name = "ipu_clkdm", + .pwrdm = { .name = "ipu_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS, + .dep_bit = DRA7XX_IPU_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain mpu1_7xx_clkdm = { + .name = "mpu1_clkdm", + .pwrdm = { .name = "cpu1_pwrdm" }, + .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, + .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST, + .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain gmac_7xx_clkdm = { + .name = "gmac_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, + .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS, + .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT, + .wkdep_srcs = gmac_wkup_sleep_deps, + .sleepdep_srcs = gmac_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4cfg_7xx_clkdm = { + .name = "l4cfg_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS, + .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP, +}; + +static struct clockdomain dma_7xx_clkdm = { + .name = "dma_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS, + .wkdep_srcs = dma_wkup_sleep_deps, + .sleepdep_srcs = dma_wkup_sleep_deps, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain rtc_7xx_clkdm = { + .name = "rtc_clkdm", + .pwrdm = { .name = "rtc_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain pcie_7xx_clkdm = { + .name = "pcie_clkdm", + .pwrdm = { .name = "l3init_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L3INIT_INST, + .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS, + .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT, + .wkdep_srcs = pcie_wkup_sleep_deps, + .sleepdep_srcs = pcie_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain atl_7xx_clkdm = { + .name = "atl_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS, + .dep_bit = DRA7XX_ATL_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain l3instr_7xx_clkdm = { + .name = "l3instr_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS, +}; + +static struct clockdomain dss_7xx_clkdm = { + .name = "dss_clkdm", + .pwrdm = { .name = "dss_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_DSS_INST, + .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS, + .dep_bit = DRA7XX_DSS_STATDEP_SHIFT, + .wkdep_srcs = dss_wkup_sleep_deps, + .sleepdep_srcs = dss_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain emif_7xx_clkdm = { + .name = "emif_clkdm", + .pwrdm = { .name = "core_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CORE_INST, + .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS, + .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain emu_7xx_clkdm = { + .name = "emu_clkdm", + .pwrdm = { .name = "emu_pwrdm" }, + .prcm_partition = DRA7XX_PRM_PARTITION, + .cm_inst = DRA7XX_PRM_EMU_CM_INST, + .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain dsp2_7xx_clkdm = { + .name = "dsp2_clkdm", + .pwrdm = { .name = "dsp2_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS, + .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT, + .wkdep_srcs = dsp2_wkup_sleep_deps, + .sleepdep_srcs = dsp2_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain dsp1_7xx_clkdm = { + .name = "dsp1_clkdm", + .pwrdm = { .name = "dsp1_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS, + .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT, + .wkdep_srcs = dsp1_wkup_sleep_deps, + .sleepdep_srcs = dsp1_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain cam_7xx_clkdm = { + .name = "cam_clkdm", + .pwrdm = { .name = "cam_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_CAM_INST, + .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS, + .dep_bit = DRA7XX_CAM_STATDEP_SHIFT, + .wkdep_srcs = cam_wkup_sleep_deps, + .sleepdep_srcs = cam_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain l4per_7xx_clkdm = { + .name = "l4per_clkdm", + .pwrdm = { .name = "l4per_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_L4PER_INST, + .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS, + .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain gpu_7xx_clkdm = { + .name = "gpu_clkdm", + .pwrdm = { .name = "gpu_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_PARTITION, + .cm_inst = DRA7XX_CM_CORE_GPU_INST, + .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS, + .dep_bit = DRA7XX_GPU_STATDEP_SHIFT, + .wkdep_srcs = gpu_wkup_sleep_deps, + .sleepdep_srcs = gpu_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain eve4_7xx_clkdm = { + .name = "eve4_clkdm", + .pwrdm = { .name = "eve4_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS, + .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT, + .wkdep_srcs = eve4_wkup_sleep_deps, + .sleepdep_srcs = eve4_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain eve2_7xx_clkdm = { + .name = "eve2_clkdm", + .pwrdm = { .name = "eve2_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS, + .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT, + .wkdep_srcs = eve2_wkup_sleep_deps, + .sleepdep_srcs = eve2_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain eve3_7xx_clkdm = { + .name = "eve3_clkdm", + .pwrdm = { .name = "eve3_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS, + .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT, + .wkdep_srcs = eve3_wkup_sleep_deps, + .sleepdep_srcs = eve3_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +static struct clockdomain wkupaon_7xx_clkdm = { + .name = "wkupaon_clkdm", + .pwrdm = { .name = "wkupaon_pwrdm" }, + .prcm_partition = DRA7XX_PRM_PARTITION, + .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST, + .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS, + .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT, + .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP, +}; + +static struct clockdomain eve1_7xx_clkdm = { + .name = "eve1_clkdm", + .pwrdm = { .name = "eve1_pwrdm" }, + .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION, + .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST, + .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS, + .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT, + .wkdep_srcs = eve1_wkup_sleep_deps, + .sleepdep_srcs = eve1_wkup_sleep_deps, + .flags = CLKDM_CAN_HWSUP_SWSUP, +}; + +/* As clockdomains are added or removed above, this list must also be changed */ +static struct clockdomain *clockdomains_dra7xx[] __initdata = { + &l4per3_7xx_clkdm, + &l4per2_7xx_clkdm, + &mpu0_7xx_clkdm, + &iva_7xx_clkdm, + &coreaon_7xx_clkdm, + &ipu1_7xx_clkdm, + &ipu2_7xx_clkdm, + &l3init_7xx_clkdm, + &l4sec_7xx_clkdm, + &l3main1_7xx_clkdm, + &vpe_7xx_clkdm, + &mpu_7xx_clkdm, + &custefuse_7xx_clkdm, + &ipu_7xx_clkdm, + &mpu1_7xx_clkdm, + &gmac_7xx_clkdm, + &l4cfg_7xx_clkdm, + &dma_7xx_clkdm, + &rtc_7xx_clkdm, + &pcie_7xx_clkdm, + &atl_7xx_clkdm, + &l3instr_7xx_clkdm, + &dss_7xx_clkdm, + &emif_7xx_clkdm, + &emu_7xx_clkdm, + &dsp2_7xx_clkdm, + &dsp1_7xx_clkdm, + &cam_7xx_clkdm, + &l4per_7xx_clkdm, + &gpu_7xx_clkdm, + &eve4_7xx_clkdm, + &eve2_7xx_clkdm, + &eve3_7xx_clkdm, + &wkupaon_7xx_clkdm, + &eve1_7xx_clkdm, + NULL +}; + +void __init dra7xx_clockdomains_init(void) +{ + clkdm_register_platform_funcs(&omap4_clkdm_operations); + clkdm_register_clkdms(clockdomains_dra7xx); + clkdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 669ef51b17a8..8538669cc2ad 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -14,439 +14,121 @@ * published by the Free Software Foundation. */ -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ #define OMAP24XX_EN_CAM_SHIFT 31 -#define OMAP24XX_EN_CAM_MASK (1 << 31) #define OMAP24XX_EN_WDT4_SHIFT 29 -#define OMAP24XX_EN_WDT4_MASK (1 << 29) #define OMAP2420_EN_WDT3_SHIFT 28 -#define OMAP2420_EN_WDT3_MASK (1 << 28) #define OMAP24XX_EN_MSPRO_SHIFT 27 -#define OMAP24XX_EN_MSPRO_MASK (1 << 27) #define OMAP24XX_EN_FAC_SHIFT 25 -#define OMAP24XX_EN_FAC_MASK (1 << 25) #define OMAP2420_EN_EAC_SHIFT 24 -#define OMAP2420_EN_EAC_MASK (1 << 24) #define OMAP24XX_EN_HDQ_SHIFT 23 -#define OMAP24XX_EN_HDQ_MASK (1 << 23) #define OMAP2420_EN_I2C2_SHIFT 20 -#define OMAP2420_EN_I2C2_MASK (1 << 20) #define OMAP2420_EN_I2C1_SHIFT 19 -#define OMAP2420_EN_I2C1_MASK (1 << 19) - -/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ #define OMAP2430_EN_MCBSP5_SHIFT 5 -#define OMAP2430_EN_MCBSP5_MASK (1 << 5) #define OMAP2430_EN_MCBSP4_SHIFT 4 -#define OMAP2430_EN_MCBSP4_MASK (1 << 4) #define OMAP2430_EN_MCBSP3_SHIFT 3 -#define OMAP2430_EN_MCBSP3_MASK (1 << 3) #define OMAP24XX_EN_SSI_SHIFT 1 -#define OMAP24XX_EN_SSI_MASK (1 << 1) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ #define OMAP24XX_EN_MPU_WDT_SHIFT 3 -#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3) - -/* Bits specific to each register */ - -/* CM_IDLEST_MPU */ -/* 2430 only */ -#define OMAP2430_ST_MPU_MASK (1 << 0) - -/* CM_CLKSEL_MPU */ #define OMAP24XX_CLKSEL_MPU_SHIFT 0 -#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_MPU_WIDTH 5 - -/* CM_CLKSTCTRL_MPU */ -#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0 #define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits*/ #define OMAP24XX_EN_TV_SHIFT 2 -#define OMAP24XX_EN_TV_MASK (1 << 2) #define OMAP24XX_EN_DSS2_SHIFT 1 -#define OMAP24XX_EN_DSS2_MASK (1 << 1) #define OMAP24XX_EN_DSS1_SHIFT 0 #define OMAP24XX_EN_DSS1_MASK (1 << 0) - -/* CM_FCLKEN2_CORE specific bits */ #define OMAP2430_EN_I2CHS2_SHIFT 20 -#define OMAP2430_EN_I2CHS2_MASK (1 << 20) #define OMAP2430_EN_I2CHS1_SHIFT 19 -#define OMAP2430_EN_I2CHS1_MASK (1 << 19) #define OMAP2430_EN_MMCHSDB2_SHIFT 17 -#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17) #define OMAP2430_EN_MMCHSDB1_SHIFT 16 -#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16) - -/* CM_ICLKEN1_CORE specific bits */ #define OMAP24XX_EN_MAILBOXES_SHIFT 30 -#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_EN_DSS_SHIFT 0 -#define OMAP24XX_EN_DSS_MASK (1 << 0) - -/* CM_ICLKEN2_CORE specific bits */ - -/* CM_ICLKEN3_CORE */ -/* 2430 only */ #define OMAP2430_EN_SDRC_SHIFT 2 -#define OMAP2430_EN_SDRC_MASK (1 << 2) - -/* CM_ICLKEN4_CORE */ #define OMAP24XX_EN_PKA_SHIFT 4 -#define OMAP24XX_EN_PKA_MASK (1 << 4) #define OMAP24XX_EN_AES_SHIFT 3 -#define OMAP24XX_EN_AES_MASK (1 << 3) #define OMAP24XX_EN_RNG_SHIFT 2 -#define OMAP24XX_EN_RNG_MASK (1 << 2) #define OMAP24XX_EN_SHA_SHIFT 1 -#define OMAP24XX_EN_SHA_MASK (1 << 1) #define OMAP24XX_EN_DES_SHIFT 0 -#define OMAP24XX_EN_DES_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ #define OMAP24XX_ST_MAILBOXES_SHIFT 30 -#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_ST_WDT4_SHIFT 29 -#define OMAP24XX_ST_WDT4_MASK (1 << 29) -#define OMAP2420_ST_WDT3_SHIFT 28 -#define OMAP2420_ST_WDT3_MASK (1 << 28) -#define OMAP24XX_ST_MSPRO_SHIFT 27 -#define OMAP24XX_ST_MSPRO_MASK (1 << 27) -#define OMAP24XX_ST_FAC_SHIFT 25 -#define OMAP24XX_ST_FAC_MASK (1 << 25) -#define OMAP2420_ST_EAC_SHIFT 24 -#define OMAP2420_ST_EAC_MASK (1 << 24) #define OMAP24XX_ST_HDQ_SHIFT 23 -#define OMAP24XX_ST_HDQ_MASK (1 << 23) #define OMAP2420_ST_I2C2_SHIFT 20 -#define OMAP2420_ST_I2C2_MASK (1 << 20) #define OMAP2430_ST_I2CHS1_SHIFT 19 -#define OMAP2430_ST_I2CHS1_MASK (1 << 19) #define OMAP2420_ST_I2C1_SHIFT 19 -#define OMAP2420_ST_I2C1_MASK (1 << 19) #define OMAP2430_ST_I2CHS2_SHIFT 20 -#define OMAP2430_ST_I2CHS2_MASK (1 << 20) #define OMAP24XX_ST_MCBSP2_SHIFT 16 -#define OMAP24XX_ST_MCBSP2_MASK (1 << 16) #define OMAP24XX_ST_MCBSP1_SHIFT 15 -#define OMAP24XX_ST_MCBSP1_MASK (1 << 15) #define OMAP24XX_ST_DSS_SHIFT 0 -#define OMAP24XX_ST_DSS_MASK (1 << 0) - -/* CM_IDLEST2_CORE */ #define OMAP2430_ST_MCBSP5_SHIFT 5 -#define OMAP2430_ST_MCBSP5_MASK (1 << 5) #define OMAP2430_ST_MCBSP4_SHIFT 4 -#define OMAP2430_ST_MCBSP4_MASK (1 << 4) #define OMAP2430_ST_MCBSP3_SHIFT 3 -#define OMAP2430_ST_MCBSP3_MASK (1 << 3) -#define OMAP24XX_ST_SSI_SHIFT 1 -#define OMAP24XX_ST_SSI_MASK (1 << 1) - -/* CM_IDLEST3_CORE */ -/* 2430 only */ -#define OMAP2430_ST_SDRC_MASK (1 << 2) - -/* CM_IDLEST4_CORE */ -#define OMAP24XX_ST_PKA_SHIFT 4 -#define OMAP24XX_ST_PKA_MASK (1 << 4) #define OMAP24XX_ST_AES_SHIFT 3 -#define OMAP24XX_ST_AES_MASK (1 << 3) #define OMAP24XX_ST_RNG_SHIFT 2 -#define OMAP24XX_ST_RNG_MASK (1 << 2) #define OMAP24XX_ST_SHA_SHIFT 1 -#define OMAP24XX_ST_SHA_MASK (1 << 1) -#define OMAP24XX_ST_DES_SHIFT 0 -#define OMAP24XX_ST_DES_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP24XX_AUTO_CAM_MASK (1 << 31) -#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30) -#define OMAP24XX_AUTO_WDT4_MASK (1 << 29) -#define OMAP2420_AUTO_WDT3_MASK (1 << 28) -#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27) -#define OMAP2420_AUTO_MMC_MASK (1 << 26) -#define OMAP24XX_AUTO_FAC_MASK (1 << 25) -#define OMAP2420_AUTO_EAC_MASK (1 << 24) -#define OMAP24XX_AUTO_HDQ_MASK (1 << 23) -#define OMAP24XX_AUTO_UART2_MASK (1 << 22) -#define OMAP24XX_AUTO_UART1_MASK (1 << 21) -#define OMAP24XX_AUTO_I2C2_MASK (1 << 20) -#define OMAP24XX_AUTO_I2C1_MASK (1 << 19) -#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18) -#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17) -#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16) -#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15) -#define OMAP24XX_AUTO_GPT12_MASK (1 << 14) -#define OMAP24XX_AUTO_GPT11_MASK (1 << 13) -#define OMAP24XX_AUTO_GPT10_MASK (1 << 12) -#define OMAP24XX_AUTO_GPT9_MASK (1 << 11) -#define OMAP24XX_AUTO_GPT8_MASK (1 << 10) -#define OMAP24XX_AUTO_GPT7_MASK (1 << 9) -#define OMAP24XX_AUTO_GPT6_MASK (1 << 8) -#define OMAP24XX_AUTO_GPT5_MASK (1 << 7) -#define OMAP24XX_AUTO_GPT4_MASK (1 << 6) -#define OMAP24XX_AUTO_GPT3_MASK (1 << 5) -#define OMAP24XX_AUTO_GPT2_MASK (1 << 4) -#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3) -#define OMAP24XX_AUTO_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE2_CORE */ -#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11) -#define OMAP2430_AUTO_GPIO5_MASK (1 << 10) -#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9) -#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8) -#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7) -#define OMAP2430_AUTO_USBHS_MASK (1 << 6) -#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5) -#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4) -#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3) -#define OMAP24XX_AUTO_UART3_MASK (1 << 2) -#define OMAP24XX_AUTO_SSI_MASK (1 << 1) -#define OMAP24XX_AUTO_USB_MASK (1 << 0) - -/* CM_AUTOIDLE3_CORE */ #define OMAP24XX_AUTO_SDRC_SHIFT 2 -#define OMAP24XX_AUTO_SDRC_MASK (1 << 2) #define OMAP24XX_AUTO_GPMC_SHIFT 1 -#define OMAP24XX_AUTO_GPMC_MASK (1 << 1) #define OMAP24XX_AUTO_SDMA_SHIFT 0 -#define OMAP24XX_AUTO_SDMA_MASK (1 << 0) - -/* CM_AUTOIDLE4_CORE */ -#define OMAP24XX_AUTO_PKA_MASK (1 << 4) -#define OMAP24XX_AUTO_AES_MASK (1 << 3) -#define OMAP24XX_AUTO_RNG_MASK (1 << 2) -#define OMAP24XX_AUTO_SHA_MASK (1 << 1) -#define OMAP24XX_AUTO_DES_MASK (1 << 0) - -/* CM_CLKSEL1_CORE */ -#define OMAP24XX_CLKSEL_USB_SHIFT 25 #define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) -#define OMAP24XX_CLKSEL_SSI_SHIFT 20 #define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) -#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 #define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) -#define OMAP24XX_CLKSEL_DSS2_SHIFT 13 #define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) -#define OMAP24XX_CLKSEL_DSS1_SHIFT 8 #define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) #define OMAP24XX_CLKSEL_L4_SHIFT 5 -#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) #define OMAP24XX_CLKSEL_L4_WIDTH 2 #define OMAP24XX_CLKSEL_L3_SHIFT 0 -#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) #define OMAP24XX_CLKSEL_L3_WIDTH 5 - -/* CM_CLKSEL2_CORE */ -#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 #define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) -#define OMAP24XX_CLKSEL_GPT11_SHIFT 20 #define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) -#define OMAP24XX_CLKSEL_GPT10_SHIFT 18 #define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) -#define OMAP24XX_CLKSEL_GPT9_SHIFT 16 #define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) -#define OMAP24XX_CLKSEL_GPT8_SHIFT 14 #define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) -#define OMAP24XX_CLKSEL_GPT7_SHIFT 12 #define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) -#define OMAP24XX_CLKSEL_GPT6_SHIFT 10 #define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) -#define OMAP24XX_CLKSEL_GPT5_SHIFT 8 #define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) -#define OMAP24XX_CLKSEL_GPT4_SHIFT 6 #define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) -#define OMAP24XX_CLKSEL_GPT3_SHIFT 4 #define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) -#define OMAP24XX_CLKSEL_GPT2_SHIFT 2 #define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) - -/* CM_CLKSTCTRL_CORE */ -#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2 #define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) -#define OMAP24XX_AUTOSTATE_L4_SHIFT 1 #define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) -#define OMAP24XX_AUTOSTATE_L3_SHIFT 0 #define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ #define OMAP24XX_EN_3D_SHIFT 2 -#define OMAP24XX_EN_3D_MASK (1 << 2) #define OMAP24XX_EN_2D_SHIFT 1 -#define OMAP24XX_EN_2D_MASK (1 << 1) - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0 #define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ - -/* CM_ICLKEN_WKUP specific bits */ #define OMAP2430_EN_ICR_SHIFT 6 -#define OMAP2430_EN_ICR_MASK (1 << 6) #define OMAP24XX_EN_OMAPCTRL_SHIFT 5 -#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5) #define OMAP24XX_EN_WDT1_SHIFT 4 -#define OMAP24XX_EN_WDT1_MASK (1 << 4) #define OMAP24XX_EN_32KSYNC_SHIFT 1 -#define OMAP24XX_EN_32KSYNC_MASK (1 << 1) - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP2430_ST_ICR_SHIFT 6 -#define OMAP2430_ST_ICR_MASK (1 << 6) -#define OMAP24XX_ST_OMAPCTRL_SHIFT 5 -#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_ST_WDT1_SHIFT 4 -#define OMAP24XX_ST_WDT1_MASK (1 << 4) #define OMAP24XX_ST_MPU_WDT_SHIFT 3 -#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3) #define OMAP24XX_ST_32KSYNC_SHIFT 1 -#define OMAP24XX_ST_32KSYNC_MASK (1 << 1) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5) -#define OMAP24XX_AUTO_WDT1_MASK (1 << 4) -#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3) -#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2) -#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1) -#define OMAP24XX_AUTO_GPT1_MASK (1 << 0) - -/* CM_CLKSEL_WKUP */ -#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 #define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) - -/* CM_CLKEN_PLL */ #define OMAP24XX_EN_54M_PLL_SHIFT 6 -#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) #define OMAP24XX_EN_96M_PLL_SHIFT 2 -#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) -#define OMAP24XX_EN_DPLL_SHIFT 0 #define OMAP24XX_EN_DPLL_MASK (0x3 << 0) - -/* CM_IDLEST_CKGEN */ #define OMAP24XX_ST_54M_APLL_SHIFT 9 -#define OMAP24XX_ST_54M_APLL_MASK (1 << 9) #define OMAP24XX_ST_96M_APLL_SHIFT 8 -#define OMAP24XX_ST_96M_APLL_MASK (1 << 8) -#define OMAP24XX_ST_54M_CLK_MASK (1 << 6) -#define OMAP24XX_ST_12M_CLK_MASK (1 << 5) -#define OMAP24XX_ST_48M_CLK_MASK (1 << 4) -#define OMAP24XX_ST_96M_CLK_MASK (1 << 2) -#define OMAP24XX_ST_CORE_CLK_SHIFT 0 -#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP24XX_AUTO_54M_SHIFT 6 #define OMAP24XX_AUTO_54M_MASK (0x3 << 6) -#define OMAP24XX_AUTO_96M_SHIFT 2 #define OMAP24XX_AUTO_96M_MASK (0x3 << 2) #define OMAP24XX_AUTO_DPLL_SHIFT 0 #define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) - -/* CM_CLKSEL1_PLL */ -#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 -#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) #define OMAP24XX_APLLS_CLKIN_SHIFT 23 #define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) -#define OMAP24XX_DPLL_MULT_SHIFT 12 #define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) -#define OMAP24XX_DPLL_DIV_SHIFT 8 #define OMAP24XX_DPLL_DIV_MASK (0xf << 8) #define OMAP24XX_54M_SOURCE_SHIFT 5 -#define OMAP24XX_54M_SOURCE_MASK (1 << 5) #define OMAP24XX_54M_SOURCE_WIDTH 1 #define OMAP2430_96M_SOURCE_SHIFT 4 -#define OMAP2430_96M_SOURCE_MASK (1 << 4) #define OMAP2430_96M_SOURCE_WIDTH 1 -#define OMAP24XX_48M_SOURCE_SHIFT 3 #define OMAP24XX_48M_SOURCE_MASK (1 << 3) -#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 -#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) - -/* CM_CLKSEL2_PLL */ -#define OMAP24XX_CORE_CLK_SRC_SHIFT 0 #define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) - -/* CM_FCLKEN_DSP */ #define OMAP2420_EN_IVA_COP_SHIFT 10 -#define OMAP2420_EN_IVA_COP_MASK (1 << 10) #define OMAP2420_EN_IVA_MPU_SHIFT 8 -#define OMAP2420_EN_IVA_MPU_MASK (1 << 8) #define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 -#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0) - -/* CM_ICLKEN_DSP */ #define OMAP2420_EN_DSP_IPI_SHIFT 1 -#define OMAP2420_EN_DSP_IPI_MASK (1 << 1) - -/* CM_IDLEST_DSP */ -#define OMAP2420_ST_IVA_MASK (1 << 8) -#define OMAP2420_ST_IPI_MASK (1 << 1) -#define OMAP24XX_ST_DSP_MASK (1 << 0) - -/* CM_AUTOIDLE_DSP */ -#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1) - -/* CM_CLKSEL_DSP */ -#define OMAP2420_SYNC_IVA_MASK (1 << 13) -#define OMAP2420_CLKSEL_IVA_SHIFT 8 #define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) -#define OMAP24XX_SYNC_DSP_MASK (1 << 7) -#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 #define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) -#define OMAP24XX_CLKSEL_DSP_SHIFT 0 #define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) - -/* CM_CLKSTCTRL_DSP */ -#define OMAP2420_AUTOSTATE_IVA_SHIFT 8 #define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) -#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0 #define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) - -/* CM_FCLKEN_MDM */ -/* 2430 only */ #define OMAP2430_EN_OSC_SHIFT 1 -#define OMAP2430_EN_OSC_MASK (1 << 1) - -/* CM_ICLKEN_MDM */ -/* 2430 only */ #define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 -#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0) - -/* CM_IDLEST_MDM specific bits */ -/* 2430 only */ - -/* CM_AUTOIDLE_MDM */ -/* 2430 only */ -#define OMAP2430_AUTO_OSC_MASK (1 << 1) -#define OMAP2430_AUTO_MDM_MASK (1 << 0) - -/* CM_CLKSEL_MDM */ -/* 2430 only */ -#define OMAP2430_SYNC_MDM_MASK (1 << 4) -#define OMAP2430_CLKSEL_MDM_SHIFT 0 #define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) - -/* CM_CLKSTCTRL_MDM */ -/* 2430 only */ -#define OMAP2430_AUTOSTATE_MDM_SHIFT 0 #define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) - -/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */ #define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 - - #endif diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h index adf7bb79b18f..c0823fd6d5e0 100644 --- a/arch/arm/mach-omap2/cm-regbits-33xx.h +++ b/arch/arm/mach-omap2/cm-regbits-33xx.h @@ -20,798 +20,49 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H -/* - * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP, - * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER - */ -#define AM33XX_AUTO_DPLL_MODE_SHIFT 0 -#define AM33XX_AUTO_DPLL_MODE_WIDTH 3 -#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11) - -/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_CPSW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1 -#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9) - -/* Used by CM_GFX_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24 -#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_PRUSS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6) - -/* Used by CM_PER_L3S_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3) - -/* Used by CM_L3_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_L4FW_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8) - -/* Used by CM_PER_L4HS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8) - -/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */ -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8) - -/* Used by CM_L4_WKUP_AON_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4) - -/* Used by CM_PER_LCDC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7) - -/* Used by CM_PER_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3) - -/* Used by CM_MPU_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2 -#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4) - -/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5) - -/* Used by CM_RTC_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25 -#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12) - -/* Used by CM_PER_L4LS_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10 -#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1 -#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1 -#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2DIV_SHIFT 3 #define AM33XX_CLKOUT2DIV_WIDTH 3 -#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3) - -/* Used by CM_CLKOUT_CTRL */ #define AM33XX_CLKOUT2EN_SHIFT 7 -#define AM33XX_CLKOUT2EN_WIDTH 1 -#define AM33XX_CLKOUT2EN_MASK (1 << 7) - -/* Used by CM_CLKOUT_CTRL */ -#define AM33XX_CLKOUT2SOURCE_SHIFT 0 -#define AM33XX_CLKOUT2SOURCE_WIDTH 3 #define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) - -/* - * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK, - * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK, - * CLKSEL_TIMER7_CLK - */ -#define AM33XX_CLKSEL_SHIFT 0 -#define AM33XX_CLKSEL_WIDTH 1 -#define AM33XX_CLKSEL_MASK (0x01 << 0) - -/* - * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK, - * CM_CPTS_RFT_CLKSEL - */ #define AM33XX_CLKSEL_0_0_SHIFT 0 #define AM33XX_CLKSEL_0_0_WIDTH 1 #define AM33XX_CLKSEL_0_0_MASK (1 << 0) - -#define AM33XX_CLKSEL_0_1_SHIFT 0 -#define AM33XX_CLKSEL_0_1_WIDTH 2 #define AM33XX_CLKSEL_0_1_MASK (3 << 0) - -/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */ -#define AM33XX_CLKSEL_0_2_SHIFT 0 -#define AM33XX_CLKSEL_0_2_WIDTH 3 #define AM33XX_CLKSEL_0_2_MASK (7 << 0) - -/* Used by CLKSEL_GFX_FCLK */ -#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1 -#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1 #define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) - -/* - * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL, - * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL, - * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL, - * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL, - * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL, - * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL - */ #define AM33XX_CLKTRCTRL_SHIFT 0 -#define AM33XX_CLKTRCTRL_WIDTH 2 #define AM33XX_CLKTRCTRL_MASK (0x3 << 0) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR, - * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER - */ -#define AM33XX_DELTAMSTEP_SHIFT 0 -#define AM33XX_DELTAMSTEP_WIDTH 20 -#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0) - -/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */ -#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1 -#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ -#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1 -#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ #define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 #define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 -#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7 -#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) - -/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */ -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1 -#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_DIV_SHIFT 0 -#define AM33XX_DPLL_DIV_WIDTH 7 #define AM33XX_DPLL_DIV_MASK (0x7f << 0) - #define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_DIV_0_7_SHIFT 0 -#define AM33XX_DPLL_DIV_0_7_WIDTH 8 -#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1 -#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_EN_SHIFT 0 -#define AM33XX_DPLL_EN_WIDTH 3 #define AM33XX_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_LPMODE_EN_SHIFT 10 -#define AM33XX_DPLL_LPMODE_EN_WIDTH 1 -#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, - * CM_CLKSEL_DPLL_MPU - */ -#define AM33XX_DPLL_MULT_SHIFT 8 -#define AM33XX_DPLL_MULT_WIDTH 11 #define AM33XX_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8 -#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12 #define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU - */ -#define AM33XX_DPLL_REGM4XEN_SHIFT 11 -#define AM33XX_DPLL_REGM4XEN_WIDTH 1 -#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_PERIPH */ -#define AM33XX_DPLL_SD_DIV_SHIFT 24 -#define AM33XX_DPLL_SD_DIV_WIDTH 8 -#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_ACK_SHIFT 13 -#define AM33XX_DPLL_SSC_ACK_WIDTH 1 -#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1 -#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define AM33XX_DPLL_SSC_EN_SHIFT 12 -#define AM33XX_DPLL_SSC_EN_WIDTH 1 -#define AM33XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_DIV_M4_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M5_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE */ #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1 -#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL, - * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL - */ #define AM33XX_IDLEST_SHIFT 16 -#define AM33XX_IDLEST_WIDTH 2 #define AM33XX_IDLEST_MASK (0x3 << 16) - -/* Used by CM_MAC_CLKSEL */ -#define AM33XX_MII_CLK_SEL_SHIFT 2 -#define AM33XX_MII_CLK_SEL_WIDTH 1 -#define AM33XX_MII_CLK_SEL_MASK (1 << 2) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3 -#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR, - * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER - */ -#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7 -#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL, - * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, - * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL, - * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL, - * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL, - * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL, - * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL, - * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL, - * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL, - * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL, - * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL, - * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL, - * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL, - * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL, - * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL, - * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL, - * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL, - * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL, - * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL, - * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL, - * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL, - * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL, - * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL, - * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL, - * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, - * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, - * CM_CEFUSE_CEFUSE_CLKCTRL - */ #define AM33XX_MODULEMODE_SHIFT 0 -#define AM33XX_MODULEMODE_WIDTH 2 #define AM33XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 -#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1 -#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19) - -/* Used by CM_WKUP_GPIO0_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO1_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO2_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO3_CLKCTRL */ #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO4_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO5_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18) - -/* Used by CM_PER_GPIO6_CLKCTRL */ -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1 -#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18) - -/* - * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL, - * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL, - * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL, - * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL, - * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL, - * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL - */ -#define AM33XX_STBYST_SHIFT 18 -#define AM33XX_STBYST_WIDTH 1 -#define AM33XX_STBYST_MASK (1 << 18) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 #define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_STM_PMD_CLKSEL_SHIFT 22 #define AM33XX_STM_PMD_CLKSEL_WIDTH 2 -#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLK_SHIFT 0 -#define AM33XX_ST_DPLL_CLK_WIDTH 1 #define AM33XX_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_PER */ #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 -#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1 -#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8) - -/* - * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU, - * CM_DIV_M2_DPLL_PER - */ -#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9 -#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1 -#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M4_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* Used by CM_DIV_M5_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE */ -#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1 -#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER - */ -#define AM33XX_ST_MN_BYPASS_SHIFT 8 -#define AM33XX_ST_MN_BYPASS_WIDTH 1 -#define AM33XX_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 #define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 -#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24) - -/* Used by CM_WKUP_DEBUGSS_CLKCTRL */ #define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 #define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 -#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20) - -/* Used by CONTROL_SEC_CLK_CTRL */ -#define AM33XX_TIMER0_CLKSEL_WIDTH 2 -#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index adf78d325804..04dab2fcf862 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -14,833 +14,201 @@ * published by the Free Software Foundation. */ -/* Bits shared between registers */ - -/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ -#define OMAP3430ES2_EN_MMC3_MASK (1 << 30) #define OMAP3430ES2_EN_MMC3_SHIFT 30 -#define OMAP3430_EN_MSPRO_MASK (1 << 23) #define OMAP3430_EN_MSPRO_SHIFT 23 -#define OMAP3430_EN_HDQ_MASK (1 << 22) #define OMAP3430_EN_HDQ_SHIFT 22 -#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5) #define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 -#define OMAP3430ES1_EN_D2D_MASK (1 << 3) #define OMAP3430ES1_EN_D2D_SHIFT 3 -#define OMAP3430_EN_SSI_MASK (1 << 0) #define OMAP3430_EN_SSI_SHIFT 0 - -/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */ #define OMAP3430ES2_EN_USBTLL_SHIFT 2 -#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2) - -/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ -#define OMAP3430_EN_WDT2_MASK (1 << 5) #define OMAP3430_EN_WDT2_SHIFT 5 - -/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */ -#define OMAP3430_EN_CAM_MASK (1 << 0) #define OMAP3430_EN_CAM_SHIFT 0 - -/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */ -#define OMAP3430_EN_WDT3_MASK (1 << 12) #define OMAP3430_EN_WDT3_SHIFT 12 - -/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */ -#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19) - - -/* Bits specific to each register */ - -/* CM_FCLKEN_IVA2 */ #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) #define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 - -/* CM_CLKEN_PLL_IVA2 */ -#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_IVA2_DPLL_SHIFT 0 #define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_IVA2 */ #define OMAP3430_ST_IVA2_SHIFT 0 -#define OMAP3430_ST_IVA2_MASK (1 << 0) - -/* CM_IDLEST_PLL_IVA2 */ -#define OMAP3430_ST_IVA2_CLK_SHIFT 0 #define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL_IVA2 */ -#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 #define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_IVA2 */ #define OMAP3430_IVA2_CLK_SRC_SHIFT 19 -#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_IVA2_CLK_SRC_WIDTH 3 -#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8 #define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0 #define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_IVA2 */ #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0) #define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 - -/* CM_CLKSTCTRL_IVA2 */ -#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0 #define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) - -/* CM_CLKSTST_IVA2 */ -#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0 #define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) - -/* CM_REVISION specific bits */ - -/* CM_SYSCONFIG specific bits */ - -/* CM_CLKEN_PLL_MPU */ -#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_MPU_DPLL_SHIFT 0 #define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_MPU */ -#define OMAP3430_ST_MPU_MASK (1 << 0) - -/* CM_IDLEST_PLL_MPU */ #define OMAP3430_ST_MPU_CLK_SHIFT 0 #define OMAP3430_ST_MPU_CLK_MASK (1 << 0) #define OMAP3430_ST_MPU_CLK_WIDTH 1 - -/* CM_AUTOIDLE_PLL_MPU */ -#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0 #define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL_MPU */ #define OMAP3430_MPU_CLK_SRC_SHIFT 19 -#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19) #define OMAP3430_MPU_CLK_SRC_WIDTH 3 -#define OMAP3430_MPU_DPLL_MULT_SHIFT 8 #define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430_MPU_DPLL_DIV_SHIFT 0 #define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL2_PLL_MPU */ #define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0) #define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 - -/* CM_CLKSTCTRL_MPU */ -#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0 #define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) - -/* CM_CLKSTST_MPU */ -#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0) - -/* CM_FCLKEN1_CORE specific bits */ -#define OMAP3430_EN_MODEM_MASK (1 << 31) #define OMAP3430_EN_MODEM_SHIFT 31 - -/* CM_ICLKEN1_CORE specific bits */ -#define OMAP3430_EN_ICR_MASK (1 << 29) #define OMAP3430_EN_ICR_SHIFT 29 -#define OMAP3430_EN_AES2_MASK (1 << 28) #define OMAP3430_EN_AES2_SHIFT 28 -#define OMAP3430_EN_SHA12_MASK (1 << 27) #define OMAP3430_EN_SHA12_SHIFT 27 -#define OMAP3430_EN_DES2_MASK (1 << 26) #define OMAP3430_EN_DES2_SHIFT 26 -#define OMAP3430ES1_EN_FAC_MASK (1 << 8) #define OMAP3430ES1_EN_FAC_SHIFT 8 -#define OMAP3430_EN_MAILBOXES_MASK (1 << 7) #define OMAP3430_EN_MAILBOXES_SHIFT 7 -#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6) #define OMAP3430_EN_OMAPCTRL_SHIFT 6 -#define OMAP3430_EN_SAD2D_MASK (1 << 3) #define OMAP3430_EN_SAD2D_SHIFT 3 -#define OMAP3430_EN_SDRC_MASK (1 << 1) #define OMAP3430_EN_SDRC_SHIFT 1 - -/* AM35XX specific CM_ICLKEN1_CORE bits */ -#define AM35XX_EN_IPSS_MASK (1 << 4) #define AM35XX_EN_IPSS_SHIFT 4 - -/* CM_ICLKEN2_CORE */ -#define OMAP3430_EN_PKA_MASK (1 << 4) #define OMAP3430_EN_PKA_SHIFT 4 -#define OMAP3430_EN_AES1_MASK (1 << 3) #define OMAP3430_EN_AES1_SHIFT 3 -#define OMAP3430_EN_RNG_MASK (1 << 2) #define OMAP3430_EN_RNG_SHIFT 2 -#define OMAP3430_EN_SHA11_MASK (1 << 1) #define OMAP3430_EN_SHA11_SHIFT 1 -#define OMAP3430_EN_DES1_MASK (1 << 0) #define OMAP3430_EN_DES1_SHIFT 0 - -/* CM_ICLKEN3_CORE */ #define OMAP3430_EN_MAD2D_SHIFT 3 -#define OMAP3430_EN_MAD2D_MASK (1 << 3) - -/* CM_FCLKEN3_CORE specific bits */ #define OMAP3430ES2_EN_TS_SHIFT 1 -#define OMAP3430ES2_EN_TS_MASK (1 << 1) #define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) - -/* CM_IDLEST1_CORE specific bits */ -#define OMAP3430ES2_ST_MMC3_SHIFT 30 -#define OMAP3430ES2_ST_MMC3_MASK (1 << 30) -#define OMAP3430_ST_ICR_SHIFT 29 -#define OMAP3430_ST_ICR_MASK (1 << 29) #define OMAP3430_ST_AES2_SHIFT 28 -#define OMAP3430_ST_AES2_MASK (1 << 28) #define OMAP3430_ST_SHA12_SHIFT 27 -#define OMAP3430_ST_SHA12_MASK (1 << 27) -#define OMAP3430_ST_DES2_SHIFT 26 -#define OMAP3430_ST_DES2_MASK (1 << 26) -#define OMAP3430_ST_MSPRO_SHIFT 23 -#define OMAP3430_ST_MSPRO_MASK (1 << 23) #define AM35XX_ST_UART4_SHIFT 23 -#define AM35XX_ST_UART4_MASK (1 << 23) #define OMAP3430_ST_HDQ_SHIFT 22 -#define OMAP3430_ST_HDQ_MASK (1 << 22) -#define OMAP3430ES1_ST_FAC_SHIFT 8 -#define OMAP3430ES1_ST_FAC_MASK (1 << 8) #define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 -#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) #define OMAP3430_ST_MAILBOXES_SHIFT 7 -#define OMAP3430_ST_MAILBOXES_MASK (1 << 7) -#define OMAP3430_ST_OMAPCTRL_SHIFT 6 -#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) #define OMAP3430_ST_SAD2D_SHIFT 3 -#define OMAP3430_ST_SAD2D_MASK (1 << 3) #define OMAP3430_ST_SDMA_SHIFT 2 -#define OMAP3430_ST_SDMA_MASK (1 << 2) -#define OMAP3430_ST_SDRC_SHIFT 1 -#define OMAP3430_ST_SDRC_MASK (1 << 1) -#define OMAP3430_ST_SSI_STDBY_SHIFT 0 -#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) - -/* AM35xx specific CM_IDLEST1_CORE bits */ #define AM35XX_ST_IPSS_SHIFT 5 -#define AM35XX_ST_IPSS_MASK (1 << 5) - -/* CM_IDLEST2_CORE */ -#define OMAP3430_ST_PKA_SHIFT 4 -#define OMAP3430_ST_PKA_MASK (1 << 4) -#define OMAP3430_ST_AES1_SHIFT 3 -#define OMAP3430_ST_AES1_MASK (1 << 3) -#define OMAP3430_ST_RNG_SHIFT 2 -#define OMAP3430_ST_RNG_MASK (1 << 2) -#define OMAP3430_ST_SHA11_SHIFT 1 -#define OMAP3430_ST_SHA11_MASK (1 << 1) -#define OMAP3430_ST_DES1_SHIFT 0 -#define OMAP3430_ST_DES1_MASK (1 << 0) - -/* CM_IDLEST3_CORE */ #define OMAP3430ES2_ST_USBTLL_SHIFT 2 -#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) -#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 -#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) - -/* CM_AUTOIDLE1_CORE */ -#define OMAP3430_AUTO_MODEM_MASK (1 << 31) -#define OMAP3430_AUTO_MODEM_SHIFT 31 -#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30) -#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 -#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29) -#define OMAP3430ES2_AUTO_ICR_SHIFT 29 -#define OMAP3430_AUTO_AES2_MASK (1 << 28) -#define OMAP3430_AUTO_AES2_SHIFT 28 -#define OMAP3430_AUTO_SHA12_MASK (1 << 27) -#define OMAP3430_AUTO_SHA12_SHIFT 27 -#define OMAP3430_AUTO_DES2_MASK (1 << 26) -#define OMAP3430_AUTO_DES2_SHIFT 26 -#define OMAP3430_AUTO_MMC2_MASK (1 << 25) -#define OMAP3430_AUTO_MMC2_SHIFT 25 -#define OMAP3430_AUTO_MMC1_MASK (1 << 24) -#define OMAP3430_AUTO_MMC1_SHIFT 24 -#define OMAP3430_AUTO_MSPRO_MASK (1 << 23) -#define OMAP3430_AUTO_MSPRO_SHIFT 23 -#define OMAP3430_AUTO_HDQ_MASK (1 << 22) -#define OMAP3430_AUTO_HDQ_SHIFT 22 -#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21) -#define OMAP3430_AUTO_MCSPI4_SHIFT 21 -#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20) -#define OMAP3430_AUTO_MCSPI3_SHIFT 20 -#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19) -#define OMAP3430_AUTO_MCSPI2_SHIFT 19 -#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18) -#define OMAP3430_AUTO_MCSPI1_SHIFT 18 -#define OMAP3430_AUTO_I2C3_MASK (1 << 17) -#define OMAP3430_AUTO_I2C3_SHIFT 17 -#define OMAP3430_AUTO_I2C2_MASK (1 << 16) -#define OMAP3430_AUTO_I2C2_SHIFT 16 -#define OMAP3430_AUTO_I2C1_MASK (1 << 15) -#define OMAP3430_AUTO_I2C1_SHIFT 15 -#define OMAP3430_AUTO_UART2_MASK (1 << 14) -#define OMAP3430_AUTO_UART2_SHIFT 14 -#define OMAP3430_AUTO_UART1_MASK (1 << 13) -#define OMAP3430_AUTO_UART1_SHIFT 13 -#define OMAP3430_AUTO_GPT11_MASK (1 << 12) -#define OMAP3430_AUTO_GPT11_SHIFT 12 -#define OMAP3430_AUTO_GPT10_MASK (1 << 11) -#define OMAP3430_AUTO_GPT10_SHIFT 11 -#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10) -#define OMAP3430_AUTO_MCBSP5_SHIFT 10 -#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9) -#define OMAP3430_AUTO_MCBSP1_SHIFT 9 -#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8) -#define OMAP3430ES1_AUTO_FAC_SHIFT 8 -#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7) -#define OMAP3430_AUTO_MAILBOXES_SHIFT 7 -#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6) -#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6 -#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5) -#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5 -#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4) -#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4 -#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3) -#define OMAP3430ES1_AUTO_D2D_SHIFT 3 -#define OMAP3430_AUTO_SAD2D_MASK (1 << 3) -#define OMAP3430_AUTO_SAD2D_SHIFT 3 -#define OMAP3430_AUTO_SSI_MASK (1 << 0) -#define OMAP3430_AUTO_SSI_SHIFT 0 - -/* CM_AUTOIDLE2_CORE */ -#define OMAP3430_AUTO_PKA_MASK (1 << 4) -#define OMAP3430_AUTO_PKA_SHIFT 4 -#define OMAP3430_AUTO_AES1_MASK (1 << 3) -#define OMAP3430_AUTO_AES1_SHIFT 3 -#define OMAP3430_AUTO_RNG_MASK (1 << 2) -#define OMAP3430_AUTO_RNG_SHIFT 2 -#define OMAP3430_AUTO_SHA11_MASK (1 << 1) -#define OMAP3430_AUTO_SHA11_SHIFT 1 -#define OMAP3430_AUTO_DES1_MASK (1 << 0) -#define OMAP3430_AUTO_DES1_SHIFT 0 - -/* CM_AUTOIDLE3_CORE */ -#define OMAP3430ES2_AUTO_USBHOST (1 << 0) -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBTLL (1 << 2) -#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 -#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) -#define OMAP3430_AUTO_MAD2D_SHIFT 3 -#define OMAP3430_AUTO_MAD2D_MASK (1 << 3) - -/* CM_CLKSEL_CORE */ -#define OMAP3430_CLKSEL_SSI_SHIFT 8 #define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) #define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT11_SHIFT 7 #define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT10_SHIFT 6 -#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4 #define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) #define OMAP3430_CLKSEL_L4_SHIFT 2 -#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2) #define OMAP3430_CLKSEL_L4_WIDTH 2 #define OMAP3430_CLKSEL_L3_SHIFT 0 -#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0) #define OMAP3430_CLKSEL_L3_WIDTH 2 -#define OMAP3630_CLKSEL_96M_SHIFT 12 #define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) -#define OMAP3630_CLKSEL_96M_WIDTH 2 - -/* CM_CLKSTCTRL_CORE */ -#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4 #define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) -#define OMAP3430_CLKTRCTRL_L4_SHIFT 2 #define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) -#define OMAP3430_CLKTRCTRL_L3_SHIFT 0 #define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) - -/* CM_CLKSTST_CORE */ -#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2 -#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2) -#define OMAP3430_CLKACTIVITY_L4_SHIFT 1 -#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1) -#define OMAP3430_CLKACTIVITY_L3_SHIFT 0 -#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0) - -/* CM_FCLKEN_GFX */ -#define OMAP3430ES1_EN_3D_MASK (1 << 2) #define OMAP3430ES1_EN_3D_SHIFT 2 -#define OMAP3430ES1_EN_2D_MASK (1 << 1) #define OMAP3430ES1_EN_2D_SHIFT 1 - -/* CM_ICLKEN_GFX specific bits */ - -/* CM_IDLEST_GFX specific bits */ - -/* CM_CLKSEL_GFX specific bits */ - -/* CM_SLEEPDEP_GFX specific bits */ - -/* CM_CLKSTCTRL_GFX */ -#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0 #define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) - -/* CM_CLKSTST_GFX */ -#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0 -#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) - -/* CM_FCLKEN_SGX */ #define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 -#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) - -/* CM_IDLEST_SGX */ -#define OMAP3430ES2_ST_SGX_SHIFT 1 -#define OMAP3430ES2_ST_SGX_MASK (1 << 1) - -/* CM_ICLKEN_SGX */ #define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 -#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) - -/* CM_CLKSEL_SGX */ -#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 #define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) - -/* CM_CLKSTCTRL_SGX */ -#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) - -/* CM_CLKSTST_SGX */ -#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0) - -/* CM_FCLKEN_WKUP specific bits */ #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 -#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) - -/* CM_ICLKEN_WKUP specific bits */ -#define OMAP3430_EN_WDT1_MASK (1 << 4) #define OMAP3430_EN_WDT1_SHIFT 4 -#define OMAP3430_EN_32KSYNC_MASK (1 << 2) #define OMAP3430_EN_32KSYNC_SHIFT 2 - -/* CM_IDLEST_WKUP specific bits */ -#define OMAP3430ES2_ST_USIMOCP_SHIFT 9 -#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) #define OMAP3430_ST_WDT2_SHIFT 5 -#define OMAP3430_ST_WDT2_MASK (1 << 5) -#define OMAP3430_ST_WDT1_SHIFT 4 -#define OMAP3430_ST_WDT1_MASK (1 << 4) #define OMAP3430_ST_32KSYNC_SHIFT 2 -#define OMAP3430_ST_32KSYNC_MASK (1 << 2) - -/* CM_AUTOIDLE_WKUP */ -#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9) -#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 -#define OMAP3430_AUTO_WDT2_MASK (1 << 5) -#define OMAP3430_AUTO_WDT2_SHIFT 5 -#define OMAP3430_AUTO_WDT1_MASK (1 << 4) -#define OMAP3430_AUTO_WDT1_SHIFT 4 -#define OMAP3430_AUTO_GPIO1_MASK (1 << 3) -#define OMAP3430_AUTO_GPIO1_SHIFT 3 -#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2) -#define OMAP3430_AUTO_32KSYNC_SHIFT 2 -#define OMAP3430_AUTO_GPT12_MASK (1 << 1) -#define OMAP3430_AUTO_GPT12_SHIFT 1 -#define OMAP3430_AUTO_GPT1_MASK (1 << 0) -#define OMAP3430_AUTO_GPT1_SHIFT 0 - -/* CM_CLKSEL_WKUP */ #define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) #define OMAP3430_CLKSEL_RM_SHIFT 1 -#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1) #define OMAP3430_CLKSEL_RM_WIDTH 2 -#define OMAP3430_CLKSEL_GPT1_SHIFT 0 #define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) - -/* CM_CLKEN_PLL */ #define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 #define OMAP3430_PWRDN_CAM_SHIFT 30 #define OMAP3430_PWRDN_DSS1_SHIFT 29 #define OMAP3430_PWRDN_TV_SHIFT 28 #define OMAP3430_PWRDN_96M_SHIFT 27 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24 -#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24) -#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20 #define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) #define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 -#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19) -#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16 #define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) #define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 -#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8 -#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4 #define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3) -#define OMAP3430_EN_CORE_DPLL_SHIFT 0 #define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) - -/* CM_CLKEN2_PLL */ -#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10 -#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8) -#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4 #define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) #define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 -#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0 #define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_IDLEST_CKGEN */ -#define OMAP3430_ST_54M_CLK_MASK (1 << 5) -#define OMAP3430_ST_12M_CLK_MASK (1 << 4) -#define OMAP3430_ST_48M_CLK_MASK (1 << 3) -#define OMAP3430_ST_96M_CLK_MASK (1 << 2) -#define OMAP3430_ST_PERIPH_CLK_SHIFT 1 #define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) -#define OMAP3430_ST_CORE_CLK_SHIFT 0 #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) - -/* CM_IDLEST2_CKGEN */ -#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 -#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) -#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 -#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) -#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 #define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) - -/* CM_AUTOIDLE_PLL */ -#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3 #define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) -#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 #define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) - -/* CM_AUTOIDLE2_PLL */ -#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0 #define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) - -/* CM_CLKSEL1_PLL */ -/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ #define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 -#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27) #define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 -#define OMAP3430_CORE_DPLL_MULT_SHIFT 16 #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) -#define OMAP3430_CORE_DPLL_DIV_SHIFT 8 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) #define OMAP3430_SOURCE_96M_SHIFT 6 -#define OMAP3430_SOURCE_96M_MASK (1 << 6) #define OMAP3430_SOURCE_96M_WIDTH 1 #define OMAP3430_SOURCE_54M_SHIFT 5 -#define OMAP3430_SOURCE_54M_MASK (1 << 5) #define OMAP3430_SOURCE_54M_WIDTH 1 -#define OMAP3430_SOURCE_48M_SHIFT 3 #define OMAP3430_SOURCE_48M_MASK (1 << 3) - -/* CM_CLKSEL2_PLL */ -#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 #define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) #define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) -#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0 #define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) -#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21 #define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) -#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24 #define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) - -/* CM_CLKSEL3_PLL */ #define OMAP3430_DIV_96M_SHIFT 0 -#define OMAP3430_DIV_96M_MASK (0x1f << 0) -#define OMAP3430_DIV_96M_WIDTH 5 -#define OMAP3630_DIV_96M_MASK (0x3f << 0) #define OMAP3630_DIV_96M_WIDTH 6 - -/* CM_CLKSEL4_PLL */ -#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8 #define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0 #define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL5_PLL */ #define OMAP3430ES2_DIV_120M_SHIFT 0 -#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0) #define OMAP3430ES2_DIV_120M_WIDTH 5 - -/* CM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT2_EN_SHIFT 7 -#define OMAP3430_CLKOUT2_EN_MASK (1 << 7) #define OMAP3430_CLKOUT2_DIV_SHIFT 3 -#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3) #define OMAP3430_CLKOUT2_DIV_WIDTH 3 -#define OMAP3430_CLKOUT2SOURCE_SHIFT 0 #define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) - -/* CM_FCLKEN_DSS */ -#define OMAP3430_EN_TV_MASK (1 << 2) #define OMAP3430_EN_TV_SHIFT 2 -#define OMAP3430_EN_DSS2_MASK (1 << 1) #define OMAP3430_EN_DSS2_SHIFT 1 -#define OMAP3430_EN_DSS1_MASK (1 << 0) #define OMAP3430_EN_DSS1_SHIFT 0 - -/* CM_ICLKEN_DSS */ -#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0) #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 - -/* CM_IDLEST_DSS */ #define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) #define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) #define OMAP3430ES1_ST_DSS_SHIFT 0 -#define OMAP3430ES1_ST_DSS_MASK (1 << 0) - -/* CM_AUTOIDLE_DSS */ -#define OMAP3430_AUTO_DSS_MASK (1 << 0) -#define OMAP3430_AUTO_DSS_SHIFT 0 - -/* CM_CLKSEL_DSS */ #define OMAP3430_CLKSEL_TV_SHIFT 8 -#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8) -#define OMAP3430_CLKSEL_TV_WIDTH 5 -#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8) #define OMAP3630_CLKSEL_TV_WIDTH 6 #define OMAP3430_CLKSEL_DSS1_SHIFT 0 -#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0) -#define OMAP3430_CLKSEL_DSS1_WIDTH 5 -#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0) #define OMAP3630_CLKSEL_DSS1_WIDTH 6 - -/* CM_SLEEPDEP_DSS specific bits */ - -/* CM_CLKSTCTRL_DSS */ -#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0 #define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) - -/* CM_CLKSTST_DSS */ -#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0 -#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) - -/* CM_FCLKEN_CAM specific bits */ -#define OMAP3430_EN_CSI2_MASK (1 << 1) #define OMAP3430_EN_CSI2_SHIFT 1 - -/* CM_ICLKEN_CAM specific bits */ - -/* CM_IDLEST_CAM */ -#define OMAP3430_ST_CAM_MASK (1 << 0) - -/* CM_AUTOIDLE_CAM */ -#define OMAP3430_AUTO_CAM_MASK (1 << 0) -#define OMAP3430_AUTO_CAM_SHIFT 0 - -/* CM_CLKSEL_CAM */ #define OMAP3430_CLKSEL_CAM_SHIFT 0 -#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0) -#define OMAP3430_CLKSEL_CAM_WIDTH 5 -#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0) #define OMAP3630_CLKSEL_CAM_WIDTH 6 - -/* CM_SLEEPDEP_CAM specific bits */ - -/* CM_CLKSTCTRL_CAM */ -#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0 #define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) - -/* CM_CLKSTST_CAM */ -#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0 -#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0) - -/* CM_FCLKEN_PER specific bits */ - -/* CM_ICLKEN_PER specific bits */ - -/* CM_IDLEST_PER */ -#define OMAP3430_ST_WDT3_SHIFT 12 -#define OMAP3430_ST_WDT3_MASK (1 << 12) #define OMAP3430_ST_MCBSP4_SHIFT 2 -#define OMAP3430_ST_MCBSP4_MASK (1 << 2) #define OMAP3430_ST_MCBSP3_SHIFT 1 -#define OMAP3430_ST_MCBSP3_MASK (1 << 1) #define OMAP3430_ST_MCBSP2_SHIFT 0 -#define OMAP3430_ST_MCBSP2_MASK (1 << 0) - -/* CM_AUTOIDLE_PER */ -#define OMAP3630_AUTO_UART4_MASK (1 << 18) -#define OMAP3630_AUTO_UART4_SHIFT 18 -#define OMAP3430_AUTO_GPIO6_MASK (1 << 17) -#define OMAP3430_AUTO_GPIO6_SHIFT 17 -#define OMAP3430_AUTO_GPIO5_MASK (1 << 16) -#define OMAP3430_AUTO_GPIO5_SHIFT 16 -#define OMAP3430_AUTO_GPIO4_MASK (1 << 15) -#define OMAP3430_AUTO_GPIO4_SHIFT 15 -#define OMAP3430_AUTO_GPIO3_MASK (1 << 14) -#define OMAP3430_AUTO_GPIO3_SHIFT 14 -#define OMAP3430_AUTO_GPIO2_MASK (1 << 13) -#define OMAP3430_AUTO_GPIO2_SHIFT 13 -#define OMAP3430_AUTO_WDT3_MASK (1 << 12) -#define OMAP3430_AUTO_WDT3_SHIFT 12 -#define OMAP3430_AUTO_UART3_MASK (1 << 11) -#define OMAP3430_AUTO_UART3_SHIFT 11 -#define OMAP3430_AUTO_GPT9_MASK (1 << 10) -#define OMAP3430_AUTO_GPT9_SHIFT 10 -#define OMAP3430_AUTO_GPT8_MASK (1 << 9) -#define OMAP3430_AUTO_GPT8_SHIFT 9 -#define OMAP3430_AUTO_GPT7_MASK (1 << 8) -#define OMAP3430_AUTO_GPT7_SHIFT 8 -#define OMAP3430_AUTO_GPT6_MASK (1 << 7) -#define OMAP3430_AUTO_GPT6_SHIFT 7 -#define OMAP3430_AUTO_GPT5_MASK (1 << 6) -#define OMAP3430_AUTO_GPT5_SHIFT 6 -#define OMAP3430_AUTO_GPT4_MASK (1 << 5) -#define OMAP3430_AUTO_GPT4_SHIFT 5 -#define OMAP3430_AUTO_GPT3_MASK (1 << 4) -#define OMAP3430_AUTO_GPT3_SHIFT 4 -#define OMAP3430_AUTO_GPT2_MASK (1 << 3) -#define OMAP3430_AUTO_GPT2_SHIFT 3 -#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2) -#define OMAP3430_AUTO_MCBSP4_SHIFT 2 -#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1) -#define OMAP3430_AUTO_MCBSP3_SHIFT 1 -#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0) -#define OMAP3430_AUTO_MCBSP2_SHIFT 0 - -/* CM_CLKSEL_PER */ #define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) -#define OMAP3430_CLKSEL_GPT9_SHIFT 7 #define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) -#define OMAP3430_CLKSEL_GPT8_SHIFT 6 #define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) -#define OMAP3430_CLKSEL_GPT7_SHIFT 5 #define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) -#define OMAP3430_CLKSEL_GPT6_SHIFT 4 #define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) -#define OMAP3430_CLKSEL_GPT5_SHIFT 3 #define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) -#define OMAP3430_CLKSEL_GPT4_SHIFT 2 #define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) -#define OMAP3430_CLKSEL_GPT3_SHIFT 1 #define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) -#define OMAP3430_CLKSEL_GPT2_SHIFT 0 - -/* CM_SLEEPDEP_PER specific bits */ -#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_PER */ -#define OMAP3430_CLKTRCTRL_PER_SHIFT 0 #define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) - -/* CM_CLKSTST_PER */ -#define OMAP3430_CLKACTIVITY_PER_SHIFT 0 -#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0) - -/* CM_CLKSEL1_EMU */ #define OMAP3430_DIV_DPLL4_SHIFT 24 -#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24) -#define OMAP3430_DIV_DPLL4_WIDTH 5 -#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24) #define OMAP3630_DIV_DPLL4_WIDTH 6 #define OMAP3430_DIV_DPLL3_SHIFT 16 -#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16) #define OMAP3430_DIV_DPLL3_WIDTH 5 #define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 -#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11) #define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLK_SHIFT 8 -#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8) #define OMAP3430_CLKSEL_PCLK_WIDTH 3 #define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 -#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6) #define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 #define OMAP3430_CLKSEL_ATCLK_SHIFT 4 -#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4) #define OMAP3430_CLKSEL_ATCLK_WIDTH 2 #define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 -#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2) #define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 -#define OMAP3430_MUX_CTRL_SHIFT 0 #define OMAP3430_MUX_CTRL_MASK (0x3 << 0) -#define OMAP3430_MUX_CTRL_WIDTH 2 - -/* CM_CLKSTCTRL_EMU */ -#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0 #define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) - -/* CM_CLKSTST_EMU */ -#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0 -#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0) - -/* CM_CLKSEL2_EMU specific bits */ -#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_CLKSEL3_EMU specific bits */ -#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8 -#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8) -#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0 -#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* CM_POLCTRL */ -#define OMAP3430_CLKOUT2_POL_MASK (1 << 0) - -/* CM_IDLEST_NEON */ -#define OMAP3430_ST_NEON_MASK (1 << 0) - -/* CM_CLKSTCTRL_NEON */ -#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0 #define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) - -/* CM_FCLKEN_USBHOST */ #define OMAP3430ES2_EN_USBHOST2_SHIFT 1 -#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1) #define OMAP3430ES2_EN_USBHOST1_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0) - -/* CM_ICLKEN_USBHOST */ #define OMAP3430ES2_EN_USBHOST_SHIFT 0 -#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) - -/* CM_IDLEST_USBHOST */ #define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 -#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) #define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 -#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) - -/* CM_AUTOIDLE_USBHOST */ -#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 -#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0) - -/* CM_SLEEPDEP_USBHOST */ -#define OMAP3430ES2_EN_MPU_SHIFT 1 -#define OMAP3430ES2_EN_MPU_MASK (1 << 1) -#define OMAP3430ES2_EN_IVA2_SHIFT 2 -#define OMAP3430ES2_EN_IVA2_MASK (1 << 2) - -/* CM_CLKSTCTRL_USBHOST */ -#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0 #define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) - -/* CM_CLKSTST_USBHOST */ -#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0 -#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0) - -/* - * - */ - -/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */ #define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 #define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 #define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 #define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 - - #endif diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 4c6c2f7de65b..4dbbd99b6e1e 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -22,1683 +22,125 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H -/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_ABE_DYNDEP_SHIFT 3 -#define OMAP4430_ABE_DYNDEP_WIDTH 0x1 -#define OMAP4430_ABE_DYNDEP_MASK (1 << 3) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_ABE_STATDEP_WIDTH 0x1 -#define OMAP4430_ABE_STATDEP_MASK (1 << 3) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1 -#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16 -#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1 -#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16) - -/* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, - * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, - * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB - */ -#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17 -#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1 -#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */ -#define OMAP4430_CEFUSE_STATDEP_SHIFT 17 -#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1 -#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9 -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1 -#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9) - -/* Used by CM_DUCATI_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8) - -/* Used by CM_IVAHD_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10) - -/* Used by CM_L3_1_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8) - -/* Used by CM_L3_2_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8) - -/* Used by CM_SDMA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8) - -/* Used by CM_CEFUSE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8) - -/* Used by CM_D2D_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12) - -/* Used by CM_MPU_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8) - -/* Used by CM1_ABE_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21 -#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24) - -/* Used by CM_MEMIF_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10) - -/* Used by CM_GFX_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10) - -/* Used by CM_ALWON_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8) - -/* Used by CM_TESLA_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1 -#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11) - -/* Used by CM_WKUP_CLKSTCTRL */ -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13 -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1 -#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13) - -/* - * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, - * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL, - * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL, - * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL, - * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL - */ #define OMAP4430_CLKSEL_SHIFT 24 #define OMAP4430_CLKSEL_WIDTH 0x1 #define OMAP4430_CLKSEL_MASK (1 << 24) - -/* - * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL, - * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL - */ #define OMAP4430_CLKSEL_0_0_SHIFT 0 #define OMAP4430_CLKSEL_0_0_WIDTH 0x1 -#define OMAP4430_CLKSEL_0_0_MASK (1 << 0) - -/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ #define OMAP4430_CLKSEL_0_1_SHIFT 0 #define OMAP4430_CLKSEL_0_1_WIDTH 0x2 -#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0) - -/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */ #define OMAP4430_CLKSEL_24_25_SHIFT 24 #define OMAP4430_CLKSEL_24_25_WIDTH 0x2 -#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_CLKSEL_60M_SHIFT 24 #define OMAP4430_CLKSEL_60M_WIDTH 0x1 -#define OMAP4430_CLKSEL_60M_MASK (1 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25 -#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 -#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25) - -/* Used by CM1_ABE_AESS_CLKCTRL */ #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_CORE_SHIFT 0 #define OMAP4430_CLKSEL_CORE_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_MASK (1 << 0) - -/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1 -#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1) - -/* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_CLKSEL_DIV_SHIFT 24 #define OMAP4430_CLKSEL_DIV_WIDTH 0x1 -#define OMAP4430_CLKSEL_DIV_MASK (1 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1 -#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24) - -/* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP4430_CLKSEL_FCLK_SHIFT 24 #define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 -#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24) - -/* Used by CM_L4PER_MCBSP4_CLKCTRL */ #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25) - -/* - * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L3_SHIFT 4 #define OMAP4430_CLKSEL_L3_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_MASK (1 << 4) - -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2 -#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2) - -/* Used by CM_CLKSEL_CORE */ #define OMAP4430_CLKSEL_L4_SHIFT 8 #define OMAP4430_CLKSEL_L4_WIDTH 0x1 -#define OMAP4430_CLKSEL_L4_MASK (1 << 8) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_CLKSEL_OPP_SHIFT 0 #define OMAP4430_CLKSEL_OPP_WIDTH 0x2 -#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 #define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 -#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) - -/* Used by CM_GFX_GFX_CLKCTRL */ -#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1 #define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) - -/* - * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, - * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL - */ -#define OMAP4430_CLKSEL_SOURCE_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2 #define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) - -/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */ -#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24 -#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25) - -/* - * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL, - * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL, - * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL, - * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, - * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL, - * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL - */ #define OMAP4430_CLKTRCTRL_SHIFT 0 -#define OMAP4430_CLKTRCTRL_WIDTH 0x2 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0 -#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7 -#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8 -#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb -#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_WIDTH 0x2 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_D2D_DYNDEP_SHIFT 18 -#define OMAP4430_D2D_DYNDEP_WIDTH 0x1 -#define OMAP4430_D2D_DYNDEP_MASK (1 << 18) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP4430_D2D_STATDEP_SHIFT 18 -#define OMAP4430_D2D_STATDEP_WIDTH 0x1 -#define OMAP4430_D2D_STATDEP_MASK (1 << 18) - -/* Used by CM_CLKSEL_DPLL_MPU */ -#define OMAP4460_DCC_COUNT_MAX_SHIFT 24 -#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8 -#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24) - -/* Used by CM_CLKSEL_DPLL_MPU */ -#define OMAP4460_DCC_EN_SHIFT 22 -#define OMAP4460_DCC_EN_MASK (1 << 22) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA, - * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER, - * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB - */ -#define OMAP4430_DELTAMSTEP_SHIFT 0 -#define OMAP4430_DELTAMSTEP_WIDTH 0x14 -#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0) - -/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */ -#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0 -#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15 -#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0) - -/* Used by CM_DLL_CTRL */ -#define OMAP4430_DLL_OVERRIDE_SHIFT 0 -#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1 -#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0) - -/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2 -#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1 -#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DLL_RESET_SHIFT 3 -#define OMAP4430_DLL_RESET_WIDTH 0x1 -#define OMAP4430_DLL_RESET_MASK (1 << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB - */ #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 #define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_CLKSEL_DPLL_CORE */ -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO - */ #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 #define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 #define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) - -/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5) - -/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */ -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB - */ -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3 -#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3 -#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_DIV_SHIFT 0 -#define OMAP4430_DPLL_DIV_WIDTH 0x7 #define OMAP4430_DPLL_DIV_MASK (0x7f << 0) - -/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_DIV_0_7_SHIFT 0 -#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8 #define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1 -#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */ -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1 -#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_EN_SHIFT 0 -#define OMAP4430_DPLL_EN_WIDTH 0x3 #define OMAP4430_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY, - * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, - * CM_CLKSEL_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_MULT_SHIFT 8 -#define OMAP4430_DPLL_MULT_WIDTH 0xb #define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) - -/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_MULT_USB_SHIFT 8 -#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc #define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO - */ -#define OMAP4430_DPLL_REGM4XEN_SHIFT 11 -#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_USB */ -#define OMAP4430_DPLL_SD_DIV_SHIFT 24 -#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8 #define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_ACK_SHIFT 13 -#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY, - * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, - * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB - */ -#define OMAP4430_DPLL_SSC_EN_SHIFT 12 -#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1 -#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_DSS_DYNDEP_SHIFT 8 -#define OMAP4430_DSS_DYNDEP_WIDTH 0x1 -#define OMAP4430_DSS_DYNDEP_MASK (1 << 8) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DSS_STATDEP_SHIFT 8 -#define OMAP4430_DSS_STATDEP_WIDTH 0x1 -#define OMAP4430_DSS_STATDEP_MASK (1 << 8) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_DUCATI_DYNDEP_SHIFT 0 -#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1 -#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0) - -/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */ #define OMAP4430_DUCATI_STATDEP_SHIFT 0 -#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1 -#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP4430_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_FREQ_UPDATE_WIDTH 0x1 -#define OMAP4430_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_WIDTH 0xc -#define OMAP4430_FUNC_MASK (0xfff << 16) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_GFX_DYNDEP_SHIFT 10 -#define OMAP4430_GFX_DYNDEP_WIDTH 0x1 -#define OMAP4430_GFX_DYNDEP_MASK (1 << 10) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_GFX_STATDEP_WIDTH 0x1 -#define OMAP4430_GFX_STATDEP_MASK (1 << 10) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1 -#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1 -#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, - * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, - * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, - * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, - * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, - * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL - */ #define OMAP4430_IDLEST_SHIFT 16 -#define OMAP4430_IDLEST_WIDTH 0x2 #define OMAP4430_IDLEST_MASK (0x3 << 16) - -/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_ISS_DYNDEP_SHIFT 9 -#define OMAP4430_ISS_DYNDEP_WIDTH 0x1 -#define OMAP4430_ISS_DYNDEP_MASK (1 << 9) - -/* - * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, - * CM_TESLA_STATICDEP - */ -#define OMAP4430_ISS_STATDEP_SHIFT 9 -#define OMAP4430_ISS_STATDEP_WIDTH 0x1 -#define OMAP4430_ISS_STATDEP_MASK (1 << 9) - -/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */ -#define OMAP4430_IVAHD_DYNDEP_SHIFT 2 -#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1 -#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_IVAHD_STATDEP_SHIFT 2 -#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1 -#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L3INIT_DYNDEP_SHIFT 7 -#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3INIT_STATDEP_SHIFT 7 -#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1 -#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7) - -/* - * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_L3_1_DYNDEP_SHIFT 5 -#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3_1_STATDEP_SHIFT 5 -#define OMAP4430_L3_1_STATDEP_WIDTH 0x1 -#define OMAP4430_L3_1_STATDEP_MASK (1 << 5) - -/* - * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, - * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP, - * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP - */ -#define OMAP4430_L3_2_DYNDEP_SHIFT 6 -#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1 -#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L3_2_STATDEP_SHIFT 6 -#define OMAP4430_L3_2_STATDEP_WIDTH 0x1 -#define OMAP4430_L3_2_STATDEP_MASK (1 << 6) - -/* Used by CM_L3_1_DYNAMICDEP */ -#define OMAP4430_L4CFG_DYNDEP_SHIFT 12 -#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4CFG_STATDEP_SHIFT 12 -#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1 -#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12) - -/* Used by CM_L3_2_DYNAMICDEP */ -#define OMAP4430_L4PER_DYNDEP_SHIFT 13 -#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13) - -/* - * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, - * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4PER_STATDEP_SHIFT 13 -#define OMAP4430_L4PER_STATDEP_WIDTH 0x1 -#define OMAP4430_L4PER_STATDEP_MASK (1 << 13) - -/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP4430_L4SEC_DYNDEP_SHIFT 14 -#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14) - -/* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP - */ #define OMAP4430_L4SEC_STATDEP_SHIFT 14 -#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1 -#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15 -#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1 -#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15) - -/* - * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_L4WKUP_STATDEP_SHIFT 15 -#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1 -#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15) - -/* - * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MPU_DYNAMICDEP - */ -#define OMAP4430_MEMIF_DYNDEP_SHIFT 4 -#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1 -#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4) - -/* - * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP, - * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP, - * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, - * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP - */ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 -#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1 -#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3 -#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA, - * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7 -#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL, - * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL, - * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL, - * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL, - * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL, - * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL, - * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, - * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL, - * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, - * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL, - * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL, - * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL, - * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, - * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL, - * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, - * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, - * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, - * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL, - * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, - * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL, - * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL, - * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL, - * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL, - * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL, - * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL, - * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL, - * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL - */ #define OMAP4430_MODULEMODE_SHIFT 0 -#define OMAP4430_MODULEMODE_WIDTH 0x2 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4460_MPU_DYNDEP_SHIFT 19 -#define OMAP4460_MPU_DYNDEP_WIDTH 0x1 -#define OMAP4460_MPU_DYNDEP_MASK (1 << 19) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) - -/* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8) - -/* Used by CM_ALWON_USBPHY_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8) - -/* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8) - -/* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, - * CM_WKUP_GPIO1_CLKCTRL - */ #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8) - -/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_WKUP_USIM_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9) - -/* Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */ #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8) - -/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10) - -/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10) - -/* Used by CM_WKUP_BANDGAP_CLKCTRL */ #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 -#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1 -#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */ -#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_CLKCTRL */ #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL */ #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_OTG_CLKCTRL */ #define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1 -#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8) - -/* Used by CM_EMU_OVERRIDE_DPLL_CORE */ -#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19 -#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1 -#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1 -#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8) - -/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */ -#define OMAP4430_PERF_CURRENT_SHIFT 0 -#define OMAP4430_PERF_CURRENT_WIDTH 0x8 -#define OMAP4430_PERF_CURRENT_MASK (0xff << 0) - -/* - * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3, - * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD, - * CM_IVA_DVFS_PERF_TESLA - */ -#define OMAP4430_PERF_REQ_SHIFT 0 -#define OMAP4430_PERF_REQ_WIDTH 0x8 -#define OMAP4430_PERF_REQ_MASK (0xff << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE1_COMPLETED_SHIFT 0 -#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1) - -/* Used by CM_RESTORE_ST */ -#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1 -#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 #define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20) - -/* Used by CM_EMU_DEBUGSS_CLKCTRL */ #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 #define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22) - -/* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP4430_PRESCAL_SHIFT 0 -#define OMAP4430_PRESCAL_WIDTH 0x6 -#define OMAP4430_PRESCAL_MASK (0x3f << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_WIDTH 0x5 -#define OMAP4430_R_RTL_MASK (0x1f << 11) - -/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */ -#define OMAP4430_SAR_MODE_SHIFT 4 -#define OMAP4430_SAR_MODE_WIDTH 0x1 -#define OMAP4430_SAR_MODE_MASK (1 << 4) - -/* Used by CM_SCALE_FCLK */ #define OMAP4430_SCALE_FCLK_SHIFT 0 #define OMAP4430_SCALE_FCLK_WIDTH 0x1 -#define OMAP4430_SCALE_FCLK_MASK (1 << 0) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_WIDTH 0x2 -#define OMAP4430_SCHEME_MASK (0x3 << 30) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_SDMA_DYNDEP_SHIFT 11 -#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1 -#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP4430_SDMA_STATDEP_SHIFT 11 -#define OMAP4430_SDMA_STATDEP_WIDTH 0x1 -#define OMAP4430_SDMA_STATDEP_MASK (1 << 11) - -/* Used by CM_CLKSEL_ABE */ #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1 -#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10) - -/* - * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, - * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL, - * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, - * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL, - * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL - */ -#define OMAP4430_STBYST_SHIFT 18 -#define OMAP4430_STBYST_WIDTH 0x1 -#define OMAP4430_STBYST_MASK (1 << 18) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_DPLL_CLK_SHIFT 0 -#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1 #define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) - -/* Used by CM_CLKDCOLDO_DPLL_USB */ -#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9) - -/* - * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB - */ -#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9) - -/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */ -#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9 -#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */ -#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11 -#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1 -#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11) - -/* - * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, - * CM_DIV_M4_DPLL_PER - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9) - -/* - * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, - * CM_DIV_M5_DPLL_PER - */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9) - -/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9) - -/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */ -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1 -#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY, - * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, - * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB - */ -#define OMAP4430_ST_MN_BYPASS_SHIFT 8 -#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1 -#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8) - -/* Used by CM_SYS_CLKSEL */ #define OMAP4430_SYS_CLKSEL_SHIFT 0 #define OMAP4430_SYS_CLKSEL_WIDTH 0x3 -#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP4430_TESLA_DYNDEP_SHIFT 1 -#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1 -#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1) - -/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */ #define OMAP4430_TESLA_STATDEP_SHIFT 1 -#define OMAP4430_TESLA_STATDEP_WIDTH 0x1 -#define OMAP4430_TESLA_STATDEP_MASK (1 << 1) - -/* - * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, - * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP - */ -#define OMAP4430_WINDOWSIZE_SHIFT 24 -#define OMAP4430_WINDOWSIZE_WIDTH 0x4 -#define OMAP4430_WINDOWSIZE_MASK (0xf << 24) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_WIDTH 0x3 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM1, REVISION_CM2 */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_WIDTH 0x6 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h index e83b8e352b6e..896ae9fc4cfb 100644 --- a/arch/arm/mach-omap2/cm-regbits-54xx.h +++ b/arch/arm/mach-omap2/cm-regbits-54xx.h @@ -21,1717 +21,84 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H -/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */ -#define OMAP54XX_ABE_DYNDEP_SHIFT 3 -#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1 -#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_ABE_STATDEP_SHIFT 3 -#define OMAP54XX_ABE_STATDEP_WIDTH 0x1 -#define OMAP54XX_ABE_STATDEP_MASK (1 << 3) - -/* - * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA, - * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1, - * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB - */ -#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0 -#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3 #define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_C2C_DYNDEP_SHIFT 18 -#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1 -#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP54XX_C2C_STATDEP_SHIFT 18 -#define OMAP54XX_C2C_STATDEP_WIDTH 0x1 -#define OMAP54XX_C2C_STATDEP_MASK (1 << 18) - -/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_CAM_DYNDEP_SHIFT 9 -#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1 -#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9) - -/* - * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, - * CM_MPU_STATICDEP - */ -#define OMAP54XX_CAM_STATDEP_SHIFT 9 -#define OMAP54XX_CAM_STATDEP_WIDTH 0x1 -#define OMAP54XX_CAM_STATDEP_MASK (1 << 9) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10) - -/* Used by CM_C2C_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9) - -/* Used by CM_CUSTEFUSE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8) - -/* Used by CM_CUSTEFUSE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9) - -/* Used by CM_DMA_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8) - -/* Used by CM_DSP_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11) - -/* Used by CM_EMIF_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10) - -/* Used by CM_EMU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8) - -/* Used by CM_CAM_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10) - -/* Used by CM_GPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12) - -/* Used by CM_DSS_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16 -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16) - -/* Used by CM_IPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8) - -/* Used by CM_IVA_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3INSTR_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10) - -/* Used by CM_L3MAIN1_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L3MAIN2_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L4CFG_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8) - -/* Used by CM_L4SEC_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2 -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17 -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18 -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18) - -/* Used by CM_MPU_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14) - -/* Used by CM_ABE_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17 -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18 -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19 -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19 -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10) - -/* Used by CM_COREAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9 -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13) - -/* Used by CM_L4PER_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22 -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23 -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24 -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13) - -/* Used by CM_MIPIEXT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31 -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30 -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30) - -/* Used by CM_L3INIT_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25 -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11 -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12 -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12) - -/* Used by CM_WKUPAON_CLKSTCTRL */ -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13 -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1 -#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13) - -/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */ -#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8 -#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8) - -/* - * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL - */ #define OMAP54XX_CLKSEL_SHIFT 24 #define OMAP54XX_CLKSEL_WIDTH 0x1 -#define OMAP54XX_CLKSEL_MASK (1 << 24) - -/* - * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF, - * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON - */ #define OMAP54XX_CLKSEL_0_0_SHIFT 0 #define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 -#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0) - -/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */ -#define OMAP54XX_CLKSEL_0_1_SHIFT 0 -#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2 -#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0) - -/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */ -#define OMAP54XX_CLKSEL_24_25_SHIFT 24 -#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2 -#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26 -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1 -#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26) - -/* Used by CM_ABE_AESS_CLKCTRL */ #define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 #define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24) - -/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */ #define OMAP54XX_CLKSEL_DIV_SHIFT 25 #define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 -#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25) - -/* Used by CM_MPU_MPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24 -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24) - -/* Used by CM_CAM_FDIF_CLKCTRL */ #define OMAP54XX_CLKSEL_FCLK_SHIFT 24 #define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24) - -/* Used by CM_GPU_GPU_CLKCTRL */ #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 #define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24) - -/* Used by CM_GPU_GPU_CLKCTRL */ #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 #define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25) - -/* Used by CM_GPU_GPU_CLKCTRL */ -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26 -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26) - -/* - * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, - * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL - */ #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 #define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26) - -/* Used by CM_CLKSEL_CORE */ -#define OMAP54XX_CLKSEL_L3_SHIFT 4 -#define OMAP54XX_CLKSEL_L3_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L3_MASK (1 << 4) - -/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1 -#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1) - -/* Used by CM_CLKSEL_CORE */ -#define OMAP54XX_CLKSEL_L4_SHIFT 8 -#define OMAP54XX_CLKSEL_L4_WIDTH 0x1 -#define OMAP54XX_CLKSEL_L4_MASK (1 << 8) - -/* Used by CM_EMIF_EMIF1_CLKCTRL */ -#define OMAP54XX_CLKSEL_LL_SHIFT 24 -#define OMAP54XX_CLKSEL_LL_WIDTH 0x1 -#define OMAP54XX_CLKSEL_LL_MASK (1 << 24) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_CLKSEL_OPP_SHIFT 0 #define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 -#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0) - -/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */ -#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24 -#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1 -#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24) - -/* - * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, - * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL - */ #define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 #define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 -#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24) - -/* - * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL - */ #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 #define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 #define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 #define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 -#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25) - -/* - * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, - * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, - * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, - * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, - * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE, - * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, - * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB, - * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER - */ -#define OMAP54XX_CLKST_SHIFT 9 -#define OMAP54XX_CLKST_WIDTH 0x1 -#define OMAP54XX_CLKST_MASK (1 << 9) - -/* - * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL, - * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL, - * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL, - * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL, - * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL, - * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL, - * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL - */ -#define OMAP54XX_CLKTRCTRL_SHIFT 0 -#define OMAP54XX_CLKTRCTRL_WIDTH 0x2 -#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0) - -/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */ -#define OMAP54XX_CLKX2ST_SHIFT 11 -#define OMAP54XX_CLKX2ST_WIDTH 0x1 -#define OMAP54XX_CLKX2ST_MASK (1 << 11) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_COREAON_DYNDEP_SHIFT 16 -#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1 -#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16) - -/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_COREAON_STATDEP_SHIFT 16 -#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1 -#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17 -#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1 -#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17) - -/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17 -#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1 -#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_CUSTOM_SHIFT 6 -#define OMAP54XX_CUSTOM_WIDTH 0x2 -#define OMAP54XX_CUSTOM_MASK (0x3 << 6) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DCC_EN_SHIFT 22 -#define OMAP54XX_DCC_EN_WIDTH 0x1 -#define OMAP54XX_DCC_EN_MASK (1 << 22) - -/* - * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS, - * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS, - * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS - */ -#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0 -#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd -#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS, - * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 -#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS, - * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9 -#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS, - * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5 -#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS, - * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6 -#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS, - * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb -#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0) - -/* - * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS, - * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS - */ -#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 -#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14 -#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa -#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b -#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe -#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0) - -/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */ -#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16 -#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0) - -/* - * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE, - * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU, - * CM_SSC_DELTAMSTEP_DPLL_PER - */ -#define OMAP54XX_DELTAMSTEP_SHIFT 0 -#define OMAP54XX_DELTAMSTEP_WIDTH 0x14 -#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0) - -/* - * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1, - * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB - */ -#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0 -#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15 -#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0) - -/* - * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER, - * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER, - * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE, - * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE, - * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE - */ -#define OMAP54XX_DIVHS_SHIFT 0 -#define OMAP54XX_DIVHS_WIDTH 0x6 #define OMAP54XX_DIVHS_MASK (0x3f << 0) - -/* - * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, - * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE, - * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER - */ -#define OMAP54XX_DIVHS_0_4_SHIFT 0 -#define OMAP54XX_DIVHS_0_4_WIDTH 0x5 #define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) - -/* - * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, - * CM_DIV_M2_DPLL_USB - */ -#define OMAP54XX_DIVHS_0_6_SHIFT 0 -#define OMAP54XX_DIVHS_0_6_WIDTH 0x7 #define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) - -/* Used by CM_DLL_CTRL */ -#define OMAP54XX_DLL_OVERRIDE_SHIFT 0 -#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1 -#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0) - -/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2 -#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1 -#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DLL_RESET_SHIFT 3 -#define OMAP54XX_DLL_RESET_WIDTH 0x1 -#define OMAP54XX_DLL_RESET_MASK (1 << 3) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23) - -/* Used by CM_CLKSEL_DPLL_CORE */ -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20 -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1 -#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8 -#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3 -#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2 -#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6 -#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11 -#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5 -#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER - */ -#define OMAP54XX_DPLL_DIV_SHIFT 0 -#define OMAP54XX_DPLL_DIV_WIDTH 0x7 #define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) - -/* - * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0 -#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8 -#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8 -#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_EN_SHIFT 0 -#define OMAP54XX_DPLL_EN_WIDTH 0x3 #define OMAP54XX_DPLL_EN_MASK (0x7 << 0) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10 -#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1 #define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) - -/* - * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA, - * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER - */ -#define OMAP54XX_DPLL_MULT_SHIFT 8 -#define OMAP54XX_DPLL_MULT_WIDTH 0xb #define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) - -/* - * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1, - * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB - */ -#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8 -#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc -#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER - */ -#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11 -#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1 #define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) - -/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ -#define OMAP54XX_DPLL_SD_DIV_SHIFT 24 -#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8 #define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) - -/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */ -#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21 -#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1 -#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13 -#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14 -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14) - -/* - * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA, - * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1, - * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB - */ -#define OMAP54XX_DPLL_SSC_EN_SHIFT 12 -#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_DSP_DYNDEP_SHIFT 1 -#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1 -#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_DSP_STATDEP_SHIFT 1 -#define OMAP54XX_DSP_STATDEP_WIDTH 0x1 -#define OMAP54XX_DSP_STATDEP_MASK (1 << 1) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_DSS_DYNDEP_SHIFT 8 -#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1 -#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8) - -/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_DSS_STATDEP_SHIFT 8 -#define OMAP54XX_DSS_STATDEP_WIDTH 0x1 -#define OMAP54XX_DSS_STATDEP_MASK (1 << 8) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, - * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_EMIF_DYNDEP_SHIFT 4 -#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1 -#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_EMIF_STATDEP_SHIFT 4 -#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1 -#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4) - -/* Used by CM_SHADOW_FREQ_CONFIG1 */ -#define OMAP54XX_FREQ_UPDATE_SHIFT 0 -#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1 -#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_FUNC_SHIFT 16 -#define OMAP54XX_FUNC_WIDTH 0xc -#define OMAP54XX_FUNC_MASK (0xfff << 16) - -/* Used by CM_SHADOW_FREQ_CONFIG2 */ -#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0 -#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1 -#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_GPU_DYNDEP_SHIFT 10 -#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_GPU_STATDEP_SHIFT 10 -#define OMAP54XX_GPU_STATDEP_WIDTH 0x1 -#define OMAP54XX_GPU_STATDEP_MASK (1 << 10) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, - * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, - * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, - * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, - * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, - * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, - * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, - * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, - * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, - * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, - * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, - * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, - * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, - * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, - * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, - * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, - * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, - * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, - * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, - * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, - * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, - * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, - * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, - * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, - * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL - */ -#define OMAP54XX_IDLEST_SHIFT 16 -#define OMAP54XX_IDLEST_WIDTH 0x2 -#define OMAP54XX_IDLEST_MASK (0x3 << 16) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_IPU_DYNDEP_SHIFT 0 -#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0) - -/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */ #define OMAP54XX_IPU_STATDEP_SHIFT 0 -#define OMAP54XX_IPU_STATDEP_WIDTH 0x1 -#define OMAP54XX_IPU_STATDEP_MASK (1 << 0) - -/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_IVA_DYNDEP_SHIFT 2 -#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1 -#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_IVA_STATDEP_SHIFT 2 -#define OMAP54XX_IVA_STATDEP_WIDTH 0x1 -#define OMAP54XX_IVA_STATDEP_MASK (1 << 2) - -/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7 -#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3INIT_STATDEP_SHIFT 7 -#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7) - -/* - * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, - * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5 -#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 -#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP, - * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP, - * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP - */ -#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6 -#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6) - -/* - * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP, - * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP, - * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 -#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1 -#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6) - -/* Used by CM_L3MAIN1_DYNAMICDEP */ -#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12 -#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L4CFG_STATDEP_SHIFT 12 -#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12) - -/* Used by CM_L3MAIN2_DYNAMICDEP */ -#define OMAP54XX_L4PER_DYNDEP_SHIFT 13 -#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13) - -/* - * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP, - * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, - * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_L4PER_STATDEP_SHIFT 13 -#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */ -#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14 -#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1 -#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14) - -/* - * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, - * CM_MPU_STATICDEP - */ #define OMAP54XX_L4SEC_STATDEP_SHIFT 14 -#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1 -#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14) - -/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21 -#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1 -#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21) - -/* Used by CM_MPU_STATICDEP */ -#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21 -#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1 -#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8 -#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3 -#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8) - -/* - * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE, - * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU, - * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1, - * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB - */ -#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0 -#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7 -#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL, - * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL, - * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL, - * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL, - * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL, - * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL, - * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL, - * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL, - * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL, - * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, - * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, - * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL, - * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, - * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, - * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, - * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL, - * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL, - * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL, - * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL, - * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL, - * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL, - * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL, - * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL, - * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL, - * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, - * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, - * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL, - * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, - * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, - * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, - * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, - * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, - * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL, - * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL, - * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL, - * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL, - * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, - * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, - * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL, - * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, - * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL, - * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL, - * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL, - * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL, - * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL, - * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL, - * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL - */ -#define OMAP54XX_MODULEMODE_SHIFT 0 -#define OMAP54XX_MODULEMODE_WIDTH 0x2 -#define OMAP54XX_MODULEMODE_MASK (0x3 << 0) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_MPU_DYNDEP_SHIFT 19 -#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1 -#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11) - -/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9) - -/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8) - -/* Used by CM_CAM_ISS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8) - -/* - * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, - * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, - * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL - */ #define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8) - -/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15 -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6) - -/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8) - -/* Used by CM_L3INIT_SATA_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8) - -/* Used by CM_WKUPAON_SCRM_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8) - -/* Used by CM_WKUPAON_SCRM_CLKCTRL */ -#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9) - -/* Used by CM_ABE_SLIMBUS1_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 -#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11) - -/* Used by CM_DSS_DSS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10) - -/* Used by CM_MIPIEXT_LLI_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8) - -/* Used by CM_MIPIEXT_LLI_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */ #define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1 -#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10) - -/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */ -#define OMAP54XX_OUTPUT_SHIFT 0 -#define OMAP54XX_OUTPUT_WIDTH 0x20 -#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 -#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1 -#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0 -#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1 -#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1) - -/* Used by CM_RESTORE_ST */ -#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2 -#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1 -#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2) - -/* Used by CM_DYN_DEP_PRESCAL */ -#define OMAP54XX_PRESCAL_SHIFT 0 -#define OMAP54XX_PRESCAL_WIDTH 0x6 -#define OMAP54XX_PRESCAL_MASK (0x3f << 0) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_R_RTL_SHIFT 11 -#define OMAP54XX_R_RTL_WIDTH 0x5 -#define OMAP54XX_R_RTL_MASK (0x1f << 11) - -/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */ -#define OMAP54XX_SAR_MODE_SHIFT 4 -#define OMAP54XX_SAR_MODE_WIDTH 0x1 -#define OMAP54XX_SAR_MODE_MASK (1 << 4) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_SCHEME_SHIFT 30 -#define OMAP54XX_SCHEME_WIDTH 0x2 -#define OMAP54XX_SCHEME_MASK (0x3 << 30) - -/* Used by CM_L4CFG_DYNAMICDEP */ -#define OMAP54XX_SDMA_DYNDEP_SHIFT 11 -#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1 -#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11) - -/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */ -#define OMAP54XX_SDMA_STATDEP_SHIFT 11 -#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1 -#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL0_SHIFT 0 -#define OMAP54XX_SEL0_WIDTH 0x7 -#define OMAP54XX_SEL0_MASK (0x7f << 0) - -/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL0_0_7_SHIFT 0 -#define OMAP54XX_SEL0_0_7_WIDTH 0x8 -#define OMAP54XX_SEL0_0_7_MASK (0xff << 0) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL1_SHIFT 8 -#define OMAP54XX_SEL1_WIDTH 0x7 -#define OMAP54XX_SEL1_MASK (0x7f << 8) - -/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8 -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL2_SHIFT 16 -#define OMAP54XX_SEL2_WIDTH 0x7 -#define OMAP54XX_SEL2_MASK (0x7f << 16) - -/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16 -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16) - -/* Used by CM_CORE_AON_DEBUG_CFG */ -#define OMAP54XX_SEL3_SHIFT 24 -#define OMAP54XX_SEL3_WIDTH 0x7 -#define OMAP54XX_SEL3_MASK (0x7f << 24) - -/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */ -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24 -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8 -#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24) - -/* Used by CM_CLKSEL_ABE */ #define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 -#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1 -#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10) - -/* - * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL, - * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL, - * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, - * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL, - * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, - * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL, - * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL, - * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL, - * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL - */ -#define OMAP54XX_STBYST_SHIFT 18 -#define OMAP54XX_STBYST_WIDTH 0x1 -#define OMAP54XX_STBYST_MASK (1 << 18) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_CLK_SHIFT 0 -#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1 #define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) - -/* - * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2, - * CM_CLKDCOLDO_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9 -#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1 -#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_INIT_SHIFT 4 -#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1 -#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4) - -/* - * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA, - * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1, - * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB - */ -#define OMAP54XX_ST_DPLL_MODE_SHIFT 1 -#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3 -#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1) - -/* Used by CM_CLKSEL_SYS */ #define OMAP54XX_SYS_CLKSEL_SHIFT 0 #define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 -#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0) - -/* - * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP, - * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, - * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP, - * CM_MPU_DYNAMICDEP - */ -#define OMAP54XX_WINDOWSIZE_SHIFT 24 -#define OMAP54XX_WINDOWSIZE_WIDTH 0x4 -#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24) - -/* Used by CM_L3MAIN1_DYNAMICDEP */ -#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15 -#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1 -#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15) - -/* - * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP, - * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP - */ #define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 -#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1 -#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_X_MAJOR_SHIFT 8 -#define OMAP54XX_X_MAJOR_WIDTH 0x3 -#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */ -#define OMAP54XX_Y_MINOR_SHIFT 0 -#define OMAP54XX_Y_MINOR_WIDTH 0x6 -#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h new file mode 100644 index 000000000000..ad8f81ce9b16 --- /dev/null +++ b/arch/arm/mach-omap2/cm-regbits-7xx.h @@ -0,0 +1,51 @@ +/* + * DRA7xx Clock Management register bits + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Generated by code originally written by: + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H +#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H + +#define DRA7XX_ATL_STATDEP_SHIFT 30 +#define DRA7XX_CAM_STATDEP_SHIFT 9 +#define DRA7XX_DSP1_STATDEP_SHIFT 1 +#define DRA7XX_DSP2_STATDEP_SHIFT 18 +#define DRA7XX_DSS_STATDEP_SHIFT 8 +#define DRA7XX_EMIF_STATDEP_SHIFT 4 +#define DRA7XX_EVE1_STATDEP_SHIFT 19 +#define DRA7XX_EVE2_STATDEP_SHIFT 20 +#define DRA7XX_EVE3_STATDEP_SHIFT 21 +#define DRA7XX_EVE4_STATDEP_SHIFT 22 +#define DRA7XX_GMAC_STATDEP_SHIFT 25 +#define DRA7XX_GPU_STATDEP_SHIFT 10 +#define DRA7XX_IPU1_STATDEP_SHIFT 23 +#define DRA7XX_IPU2_STATDEP_SHIFT 0 +#define DRA7XX_IPU_STATDEP_SHIFT 24 +#define DRA7XX_IVA_STATDEP_SHIFT 2 +#define DRA7XX_L3INIT_STATDEP_SHIFT 7 +#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5 +#define DRA7XX_L4CFG_STATDEP_SHIFT 12 +#define DRA7XX_L4PER2_STATDEP_SHIFT 26 +#define DRA7XX_L4PER3_STATDEP_SHIFT 27 +#define DRA7XX_L4PER_STATDEP_SHIFT 13 +#define DRA7XX_L4SEC_STATDEP_SHIFT 14 +#define DRA7XX_PCIE_STATDEP_SHIFT 29 +#define DRA7XX_VPE_STATDEP_SHIFT 28 +#define DRA7XX_WKUPAON_STATDEP_SHIFT 15 +#endif diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h new file mode 100644 index 000000000000..ca6fa1febaac --- /dev/null +++ b/arch/arm/mach-omap2/cm1_7xx.h @@ -0,0 +1,324 @@ +/* + * DRA7xx CM1 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Generated by code originally written by: + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H +#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H + +#include "cm_44xx_54xx.h" + +/* CM1 base address */ +#define DRA7XX_CM_CORE_AON_BASE 0x4a005000 + +#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg)) + +/* CM_CORE_AON instances */ +#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000 +#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100 +#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300 +#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400 +#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500 +#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600 +#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640 +#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680 +#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0 +#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700 +#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740 +#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760 +#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00 +#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00 + +/* CM_CORE_AON clockdomain register offsets (from instance start) */ +#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040 +#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000 + +/* CM_CORE_AON */ + +/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ +#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000 +#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) +#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec +#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0 +#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4 +#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8 +#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc + +/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ +#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000 +#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) +#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008 +#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) +#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010 +#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 +#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) +#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 +#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) +#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 +#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) +#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c +#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) +#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 +#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) +#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 +#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) +#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 +#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) +#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c +#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) +#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 +#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) +#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 +#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c +#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 +#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) +#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 +#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) +#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 +#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) +#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c +#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) +#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 +#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) +#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 +#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) +#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 +#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) +#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c +#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) +#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 +#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c +#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c +#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) +#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 +#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) +#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 +#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) +#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 +#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) +#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac +#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) +#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0 +#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) +#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4 +#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc +#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc +#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) +#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 +#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) +#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 +#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) +#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 +#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) +#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec +#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) +#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 +#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) +#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 +#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c +#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110 +#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) +#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114 +#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) +#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118 +#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) +#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c +#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) +#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120 +#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) +#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124 +#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) +#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128 +#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130 +#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134 +#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) +#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138 +#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) +#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c +#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) +#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140 +#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) +#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144 +#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) +#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148 +#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150 +#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154 +#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) +#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 +#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 +#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 +#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180 +#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184 +#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) +#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188 +#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) +#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c +#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) +#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190 +#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) +#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194 +#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) +#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198 +#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0 +#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4 +#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) +#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8 +#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) +#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac +#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) +#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0 +#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) +#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4 +#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) +#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8 +#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) +#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc +#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) +#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0 +#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) +#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4 +#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) +#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8 +#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) +#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc +#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4 +#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8 +#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) +#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc +#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) +#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0 +#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) +#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4 +#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) +#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8 +#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) +#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec +#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4 + +/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ +#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020) +#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028) + +/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */ +#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020) + +/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */ +#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020) +#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040 +#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050) +#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058 +#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058) +#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060 +#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060) +#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068 +#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068) +#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070 +#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070) +#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078) +#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080 +#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080) + +/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */ +#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020) + +/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */ +#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020) + +/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */ +#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020) + +/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */ +#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020) + +/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */ +#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020) + +/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */ +#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004 +#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004) + +/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */ +#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004 +#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004) +#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008 + +#endif diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h new file mode 100644 index 000000000000..9ad7594e7622 --- /dev/null +++ b/arch/arm/mach-omap2/cm2_7xx.h @@ -0,0 +1,513 @@ +/* + * DRA7xx CM2 instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Generated by code originally written by: + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H +#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H + +#include "cm_44xx_54xx.h" + +/* CM2 base address */ +#define DRA7XX_CM_CORE_BASE 0x4a008000 + +#define DRA7XX_CM_CORE_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg)) + +/* CM_CORE instances */ +#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000 +#define DRA7XX_CM_CORE_CKGEN_INST 0x0104 +#define DRA7XX_CM_CORE_COREAON_INST 0x0600 +#define DRA7XX_CM_CORE_CORE_INST 0x0700 +#define DRA7XX_CM_CORE_IVA_INST 0x0f00 +#define DRA7XX_CM_CORE_CAM_INST 0x1000 +#define DRA7XX_CM_CORE_DSS_INST 0x1100 +#define DRA7XX_CM_CORE_GPU_INST 0x1200 +#define DRA7XX_CM_CORE_L3INIT_INST 0x1300 +#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 +#define DRA7XX_CM_CORE_L4PER_INST 0x1700 +#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 + +/* CM_CORE clockdomain register offsets (from instance start) */ +#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200 +#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300 +#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400 +#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520 +#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600 +#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700 +#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0 +#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0 +#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000 +#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180 +#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc +#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 + +/* CM_CORE */ + +/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ +#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 +#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) +#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 + +/* CM_CORE.CKGEN_CM_CORE register offsets */ +#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 +#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) +#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c +#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) +#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 +#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) +#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 +#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) +#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 +#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) +#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c +#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) +#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 +#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) +#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 +#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) +#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 +#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) +#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c +#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) +#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 +#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 +#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c +#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) +#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 +#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) +#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 +#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) +#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 +#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) +#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c +#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 +#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 +#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) +#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc +#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) +#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 +#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) +#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 +#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) +#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 +#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) +#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c +#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) +#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 +#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 +#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 +#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) +#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c +#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) +#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 +#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) +#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 +#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) + +/* CM_CORE.COREAON_CM_CORE register offsets */ +#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) +#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 +#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) +#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) +#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) +#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 +#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) +#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 +#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) +#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) +#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 +#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) +#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 +#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) +#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 +#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) +#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) +#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 +#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) +#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 +#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) + +/* CM_CORE.CORE_CM_CORE register offsets */ +#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) +#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) +#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) +#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) +#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 +#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) +#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 +#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) +#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 +#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) +#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 +#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) +#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) +#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 +#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) +#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 +#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) +#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 +#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) +#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 +#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) +#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 +#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) +#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 +#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) +#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) +#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 +#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 +#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 +#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) +#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 +#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 +#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 +#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 +#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) +#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 +#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 +#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 +#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 +#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) +#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 +#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 +#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) +#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 +#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) +#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 +#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) +#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 +#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) +#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 +#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) +#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 +#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) +#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 +#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 +#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 +#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 +#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) +#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 +#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) +#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 +#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) +#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 +#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) +#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 +#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) +#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 +#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) +#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 +#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) +#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 +#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) +#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 +#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) +#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 +#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) +#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 +#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) +#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 +#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) +#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 +#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) +#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 +#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) +#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 +#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) +#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 +#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) +#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 +#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 +#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) +#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 +#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) +#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 +#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 +#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) +#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 +#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) +#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 +#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) +#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 +#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) +#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 +#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) + +/* CM_CORE.IVA_CM_CORE register offsets */ +#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) +#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) + +/* CM_CORE.CAM_CM_CORE register offsets */ +#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) +#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) +#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) +#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 +#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) +#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) +#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 +#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) + +/* CM_CORE.DSS_CM_CORE register offsets */ +#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) +#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) +#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c +#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) + +/* CM_CORE.GPU_CM_CORE register offsets */ +#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) + +/* CM_CORE.L3INIT_CM_CORE register offsets */ +#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 +#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) +#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) +#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) +#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 +#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) +#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) +#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 +#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) +#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) +#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 +#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) +#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 +#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 +#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 +#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 +#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 +#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 +#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) +#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 +#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) +#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 +#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) +#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 +#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) + +/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ +#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) + +/* CM_CORE.L4PER_CM_CORE register offsets */ +#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c +#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) +#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 +#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) +#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 +#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) +#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) +#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) +#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) +#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 +#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) +#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) +#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 +#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) +#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) +#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 +#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) +#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 +#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) +#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 +#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) +#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 +#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) +#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) +#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 +#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) +#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 +#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) +#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 +#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) +#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 +#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) +#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 +#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) +#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 +#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) +#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) +#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 +#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) +#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 +#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) +#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 +#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) +#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 +#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) +#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 +#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) +#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 +#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) +#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 +#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) +#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 +#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) +#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 +#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) +#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 +#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) +#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 +#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) +#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 +#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) +#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 +#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) +#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 +#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) +#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 +#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) +#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 +#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) +#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 +#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) +#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 +#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) +#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 +#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) +#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 +#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) +#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 +#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) +#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 +#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) +#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 +#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) +#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 +#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) +#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 +#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 +#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 +#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 +#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) +#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 +#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) +#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 +#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) +#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 +#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) +#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 +#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) +#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 +#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) +#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 +#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) +#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 +#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) +#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 +#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) +#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 +#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) +#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 +#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) +#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 +#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) +#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 +#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) +#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 +#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) +#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc +#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 +#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 +#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) +#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 +#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) +#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c +#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 +#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 + +#endif diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h index dfcc182ecff9..4a5684b96492 100644 --- a/arch/arm/mach-omap2/common.h +++ b/arch/arm/mach-omap2/common.h @@ -110,6 +110,7 @@ void omap3630_init_late(void); void am35xx_init_late(void); void ti81xx_init_late(void); int omap2_common_pm_late_init(void); +void dra7xx_init_early(void); #ifdef CONFIG_SOC_BUS void omap_soc_device_init(void); diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c index c443f2e97e10..4c8982ae9529 100644 --- a/arch/arm/mach-omap2/cpuidle44xx.c +++ b/arch/arm/mach-omap2/cpuidle44xx.c @@ -143,7 +143,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev, * Call idle CPU cluster PM exit notifier chain * to restore GIC and wakeupgen context. */ - if ((cx->mpu_state == PWRDM_POWER_RET) && + if (dev->cpu == 0 && (cx->mpu_state == PWRDM_POWER_RET) && (cx->mpu_logic_state == PWRDM_POWER_OFF)) cpu_cluster_pm_exit(); diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c index 3c1279f27d1f..5c5315ba129b 100644 --- a/arch/arm/mach-omap2/devices.c +++ b/arch/arm/mach-omap2/devices.c @@ -327,44 +327,6 @@ static void omap_init_audio(void) static inline void omap_init_audio(void) {} #endif -#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \ - defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE) - -static void __init omap_init_mcpdm(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("mcpdm"); - if (!oh) - return; - - pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n"); -} -#else -static inline void omap_init_mcpdm(void) {} -#endif - -#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \ - defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE) - -static void __init omap_init_dmic(void) -{ - struct omap_hwmod *oh; - struct platform_device *pdev; - - oh = omap_hwmod_lookup("dmic"); - if (!oh) - return; - - pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0); - WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n"); -} -#else -static inline void omap_init_dmic(void) {} -#endif - #if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \ defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE) @@ -565,17 +527,15 @@ static int __init omap2_init_devices(void) omap_init_mbox(); /* If dtb is there, the devices will be created dynamically */ if (!of_have_populated_dt()) { - omap_init_dmic(); - omap_init_mcpdm(); omap_init_mcspi(); omap_init_sham(); omap_init_aes(); + omap_init_rng(); } else { /* These can be removed when bindings are done */ omap_init_wl12xx_of(); } omap_init_sti(); - omap_init_rng(); omap_init_vout(); return 0; diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c index ff37be1f6f93..03a0516c7f67 100644 --- a/arch/arm/mach-omap2/display.c +++ b/arch/arm/mach-omap2/display.c @@ -400,7 +400,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) /* Create devices for DPI and SDI */ - pdev = create_simple_dss_pdev("omapdss_dpi", -1, + pdev = create_simple_dss_pdev("omapdss_dpi", 0, board_data, sizeof(*board_data), dss_pdev); if (IS_ERR(pdev)) { pr_err("Could not build platform_device for omapdss_dpi\n"); @@ -408,7 +408,7 @@ int __init omap_display_init(struct omap_dss_board_info *board_data) } if (cpu_is_omap34xx()) { - pdev = create_simple_dss_pdev("omapdss_sdi", -1, + pdev = create_simple_dss_pdev("omapdss_sdi", 0, board_data, sizeof(*board_data), dss_pdev); if (IS_ERR(pdev)) { pr_err("Could not build platform_device for omapdss_sdi\n"); diff --git a/arch/arm/mach-omap2/dss-common.c b/arch/arm/mach-omap2/dss-common.c index 043e5705f2a6..bf89effa4c99 100644 --- a/arch/arm/mach-omap2/dss-common.c +++ b/arch/arm/mach-omap2/dss-common.c @@ -25,6 +25,7 @@ #include <linux/kernel.h> #include <linux/gpio.h> +#include <linux/platform_device.h> #include <video/omapdss.h> #include <video/omap-panel-data.h> @@ -37,70 +38,76 @@ #define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */ #define HDMI_GPIO_HPD 63 /* Hotplug detect */ -/* Display DVI */ #define PANDA_DVI_TFP410_POWER_DOWN_GPIO 0 -/* Using generic display panel */ -static struct tfp410_platform_data omap4_dvi_panel = { - .i2c_bus_num = 2, - .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, +/* DVI Connector */ +static struct connector_dvi_platform_data omap4_panda_dvi_connector_pdata = { + .name = "dvi", + .source = "tfp410.0", + .i2c_bus_num = 2, }; -static struct omap_dss_device omap4_panda_dvi_device = { - .type = OMAP_DISPLAY_TYPE_DPI, - .name = "dvi", - .driver_name = "tfp410", - .data = &omap4_dvi_panel, - .phy.dpi.data_lines = 24, - .channel = OMAP_DSS_CHANNEL_LCD2, +static struct platform_device omap4_panda_dvi_connector_device = { + .name = "connector-dvi", + .id = 0, + .dev.platform_data = &omap4_panda_dvi_connector_pdata, }; -static struct omap_dss_hdmi_data omap4_panda_hdmi_data = { +/* TFP410 DPI-to-DVI chip */ +static struct encoder_tfp410_platform_data omap4_panda_tfp410_pdata = { + .name = "tfp410.0", + .source = "dpi.0", + .data_lines = 24, + .power_down_gpio = PANDA_DVI_TFP410_POWER_DOWN_GPIO, +}; + +static struct platform_device omap4_panda_tfp410_device = { + .name = "tfp410", + .id = 0, + .dev.platform_data = &omap4_panda_tfp410_pdata, +}; + +/* HDMI Connector */ +static struct connector_hdmi_platform_data omap4_panda_hdmi_connector_pdata = { + .name = "hdmi", + .source = "tpd12s015.0", +}; + +static struct platform_device omap4_panda_hdmi_connector_device = { + .name = "connector-hdmi", + .id = 0, + .dev.platform_data = &omap4_panda_hdmi_connector_pdata, +}; + +/* TPD12S015 HDMI ESD protection & level shifter chip */ +static struct encoder_tpd12s015_platform_data omap4_panda_tpd_pdata = { + .name = "tpd12s015.0", + .source = "hdmi.0", + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, .ls_oe_gpio = HDMI_GPIO_LS_OE, .hpd_gpio = HDMI_GPIO_HPD, }; -static struct omap_dss_device omap4_panda_hdmi_device = { - .name = "hdmi", - .driver_name = "hdmi_panel", - .type = OMAP_DISPLAY_TYPE_HDMI, - .channel = OMAP_DSS_CHANNEL_DIGIT, - .data = &omap4_panda_hdmi_data, -}; - -static struct omap_dss_device *omap4_panda_dss_devices[] = { - &omap4_panda_dvi_device, - &omap4_panda_hdmi_device, +static struct platform_device omap4_panda_tpd_device = { + .name = "tpd12s015", + .id = 0, + .dev.platform_data = &omap4_panda_tpd_pdata, }; static struct omap_dss_board_info omap4_panda_dss_data = { - .num_devices = ARRAY_SIZE(omap4_panda_dss_devices), - .devices = omap4_panda_dss_devices, - .default_device = &omap4_panda_dvi_device, + .default_display_name = "dvi", }; -void __init omap4_panda_display_init(void) +void __init omap4_panda_display_init_of(void) { omap_display_init(&omap4_panda_dss_data); - /* - * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and - * later have external pull up on the HDMI I2C lines - */ - if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2) - omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); - else - omap_hdmi_init(0); - - omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); -} + platform_device_register(&omap4_panda_tfp410_device); + platform_device_register(&omap4_panda_dvi_connector_device); -void __init omap4_panda_display_init_of(void) -{ - omap_display_init(&omap4_panda_dss_data); + platform_device_register(&omap4_panda_tpd_device); + platform_device_register(&omap4_panda_hdmi_connector_device); } @@ -109,93 +116,73 @@ void __init omap4_panda_display_init_of(void) #define DISPLAY_SEL_GPIO 59 /* LCD2/PicoDLP switch */ #define DLP_POWER_ON_GPIO 40 -static struct nokia_dsi_panel_data dsi1_panel = { - .name = "taal", - .reset_gpio = 102, - .use_ext_te = false, - .ext_te_gpio = 101, - .esd_interval = 0, - .pin_config = { - .num_pins = 6, - .pins = { 0, 1, 2, 3, 4, 5 }, - }, -}; - -static struct omap_dss_device sdp4430_lcd_device = { - .name = "lcd", - .driver_name = "taal", - .type = OMAP_DISPLAY_TYPE_DSI, - .data = &dsi1_panel, - .phy.dsi = { - .module = 0, +static struct panel_dsicm_platform_data dsi1_panel = { + .name = "lcd", + .source = "dsi.0", + .reset_gpio = 102, + .use_ext_te = false, + .ext_te_gpio = 101, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, }, - .channel = OMAP_DSS_CHANNEL_LCD, }; -static struct nokia_dsi_panel_data dsi2_panel = { - .name = "taal", - .reset_gpio = 104, - .use_ext_te = false, - .ext_te_gpio = 103, - .esd_interval = 0, - .pin_config = { - .num_pins = 6, - .pins = { 0, 1, 2, 3, 4, 5 }, - }, +static struct platform_device sdp4430_lcd_device = { + .name = "panel-dsi-cm", + .id = 0, + .dev.platform_data = &dsi1_panel, }; -static struct omap_dss_device sdp4430_lcd2_device = { - .name = "lcd2", - .driver_name = "taal", - .type = OMAP_DISPLAY_TYPE_DSI, - .data = &dsi2_panel, - .phy.dsi = { - - .module = 1, +static struct panel_dsicm_platform_data dsi2_panel = { + .name = "lcd2", + .source = "dsi.1", + .reset_gpio = 104, + .use_ext_te = false, + .ext_te_gpio = 103, + .pin_config = { + .num_pins = 6, + .pins = { 0, 1, 2, 3, 4, 5 }, }, - .channel = OMAP_DSS_CHANNEL_LCD2, }; -static struct omap_dss_hdmi_data sdp4430_hdmi_data = { - .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, - .ls_oe_gpio = HDMI_GPIO_LS_OE, - .hpd_gpio = HDMI_GPIO_HPD, +static struct platform_device sdp4430_lcd2_device = { + .name = "panel-dsi-cm", + .id = 1, + .dev.platform_data = &dsi2_panel, }; -static struct omap_dss_device sdp4430_hdmi_device = { - .name = "hdmi", - .driver_name = "hdmi_panel", - .type = OMAP_DISPLAY_TYPE_HDMI, - .channel = OMAP_DSS_CHANNEL_DIGIT, - .data = &sdp4430_hdmi_data, +/* HDMI Connector */ +static struct connector_hdmi_platform_data sdp4430_hdmi_connector_pdata = { + .name = "hdmi", + .source = "tpd12s015.0", }; -static struct picodlp_panel_data sdp4430_picodlp_pdata = { - .picodlp_adapter_id = 2, - .emu_done_gpio = 44, - .pwrgood_gpio = 45, +static struct platform_device sdp4430_hdmi_connector_device = { + .name = "connector-hdmi", + .id = 0, + .dev.platform_data = &sdp4430_hdmi_connector_pdata, }; -static struct omap_dss_device sdp4430_picodlp_device = { - .name = "picodlp", - .driver_name = "picodlp_panel", - .type = OMAP_DISPLAY_TYPE_DPI, - .phy.dpi.data_lines = 24, - .channel = OMAP_DSS_CHANNEL_LCD2, - .data = &sdp4430_picodlp_pdata, +/* TPD12S015 HDMI ESD protection & level shifter chip */ +static struct encoder_tpd12s015_platform_data sdp4430_tpd_pdata = { + .name = "tpd12s015.0", + .source = "hdmi.0", + + .ct_cp_hpd_gpio = HDMI_GPIO_CT_CP_HPD, + .ls_oe_gpio = HDMI_GPIO_LS_OE, + .hpd_gpio = HDMI_GPIO_HPD, }; -static struct omap_dss_device *sdp4430_dss_devices[] = { - &sdp4430_lcd_device, - &sdp4430_lcd2_device, - &sdp4430_hdmi_device, - &sdp4430_picodlp_device, +static struct platform_device sdp4430_tpd_device = { + .name = "tpd12s015", + .id = 0, + .dev.platform_data = &sdp4430_tpd_pdata, }; + static struct omap_dss_board_info sdp4430_dss_data = { - .num_devices = ARRAY_SIZE(sdp4430_dss_devices), - .devices = sdp4430_dss_devices, - .default_device = &sdp4430_lcd_device, + .default_display_name = "lcd", }; /* @@ -204,7 +191,7 @@ static struct omap_dss_board_info sdp4430_dss_data = { * used by picodlp on the 4430sdp platform. Keep this gpio disabled as LCD2 is * selected by default */ -void __init omap_4430sdp_display_init(void) +void __init omap_4430sdp_display_init_of(void) { int r; @@ -219,33 +206,10 @@ void __init omap_4430sdp_display_init(void) pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); omap_display_init(&sdp4430_dss_data); - /* - * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and - * later have external pull up on the HDMI I2C lines - */ - if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2) - omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP); - else - omap_hdmi_init(0); - - omap_mux_init_gpio(HDMI_GPIO_LS_OE, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_CT_CP_HPD, OMAP_PIN_OUTPUT); - omap_mux_init_gpio(HDMI_GPIO_HPD, OMAP_PIN_INPUT_PULLDOWN); -} - -void __init omap_4430sdp_display_init_of(void) -{ - int r; - r = gpio_request_one(DISPLAY_SEL_GPIO, GPIOF_OUT_INIT_HIGH, - "display_sel"); - if (r) - pr_err("%s: Could not get display_sel GPIO\n", __func__); - - r = gpio_request_one(DLP_POWER_ON_GPIO, GPIOF_OUT_INIT_LOW, - "DLP POWER ON"); - if (r) - pr_err("%s: Could not get DLP POWER ON GPIO\n", __func__); + platform_device_register(&sdp4430_lcd_device); + platform_device_register(&sdp4430_lcd2_device); - omap_display_init(&sdp4430_dss_data); + platform_device_register(&sdp4430_tpd_device); + platform_device_register(&sdp4430_hdmi_connector_device); } diff --git a/arch/arm/mach-omap2/dss-common.h b/arch/arm/mach-omap2/dss-common.h index 915f6fff5106..c28fe3c03588 100644 --- a/arch/arm/mach-omap2/dss-common.h +++ b/arch/arm/mach-omap2/dss-common.h @@ -6,9 +6,7 @@ * This file will be removed when DSS supports DT. */ -void __init omap4_panda_display_init(void); void __init omap4_panda_display_init_of(void); -void __init omap_4430sdp_display_init(void); void __init omap_4430sdp_display_init_of(void); #endif diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c index f3fdd6afa213..579697adaae7 100644 --- a/arch/arm/mach-omap2/gpmc.c +++ b/arch/arm/mach-omap2/gpmc.c @@ -149,7 +149,7 @@ struct omap3_gpmc_regs { static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; static struct irq_chip gpmc_irq_chip; -static unsigned gpmc_irq_start; +static int gpmc_irq_start; static struct resource gpmc_mem_root; static struct resource gpmc_cs_mem[GPMC_CS_NUM]; @@ -1491,8 +1491,8 @@ static int gpmc_probe_generic_child(struct platform_device *pdev, */ ret = gpmc_cs_remap(cs, res.start); if (ret < 0) { - dev_err(&pdev->dev, "cannot remap GPMC CS %d to 0x%x\n", - cs, res.start); + dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", + cs, &res.start); goto err; } diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c index d940e53dd9f2..b456b4471f35 100644 --- a/arch/arm/mach-omap2/i2c.c +++ b/arch/arm/mach-omap2/i2c.c @@ -181,7 +181,7 @@ int __init omap_i2c_add_bus(struct omap_i2c_bus_platform_data *i2c_pdata, sizeof(struct omap_i2c_bus_platform_data)); WARN(IS_ERR(pdev), "Could not build omap_device for %s\n", name); - return PTR_RET(pdev); + return PTR_ERR_OR_ZERO(pdev); } static int __init omap_i2c_cmdline(void) diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c index 2dc62a25f2c3..0289adcb6efb 100644 --- a/arch/arm/mach-omap2/id.c +++ b/arch/arm/mach-omap2/id.c @@ -61,7 +61,7 @@ int omap_type(void) val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); } else if (cpu_is_omap44xx()) { val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); - } else if (soc_is_omap54xx()) { + } else if (soc_is_omap54xx() || soc_is_dra7xx()) { val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); val &= OMAP5_DEVICETYPE_MASK; val >>= 6; @@ -116,7 +116,7 @@ static u16 tap_prod_id; void omap_get_die_id(struct omap_die_id *odi) { - if (cpu_is_omap44xx() || soc_is_omap54xx()) { + if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 4a3f06f02859..ff2113ce4014 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = { }; #endif -#ifdef CONFIG_SOC_OMAP5 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) static struct map_desc omap54xx_io_desc[] __initdata = { { .virtual = L3_54XX_VIRT, @@ -333,7 +333,7 @@ void __init omap4_map_io(void) } #endif -#ifdef CONFIG_SOC_OMAP5 +#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX) void __init omap5_map_io(void) { iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); @@ -653,6 +653,27 @@ void __init omap5_init_early(void) } #endif +#ifdef CONFIG_SOC_DRA7XX +void __init dra7xx_init_early(void) +{ + omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), + OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE), + OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE)); + omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap_prm_base_init(); + omap_cm_base_init(); + omap44xx_prm_init(); + dra7xx_powerdomains_init(); + dra7xx_clockdomains_init(); + dra7xx_hwmod_init(); + omap_hwmod_init_postsetup(); +} +#endif + + void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c index c53609f46294..be271f1d585b 100644 --- a/arch/arm/mach-omap2/mux34xx.c +++ b/arch/arm/mach-omap2/mux34xx.c @@ -620,7 +620,7 @@ static struct omap_mux __initdata omap3_muxmodes[] = { "uart1_rts", "ssi1_flag_tx", NULL, NULL, "gpio_149", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_RX, 151, - "uart1_rx", "ss1_wake_tx", "mcbsp1_clkr", "mcspi4_clk", + "uart1_rx", "ssi1_wake_tx", "mcbsp1_clkr", "mcspi4_clk", "gpio_151", NULL, NULL, "safe_mode"), _OMAP3_MUXENTRY(UART1_TX, 148, "uart1_tx", "ssi1_dat_tx", NULL, NULL, diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index 8708b2a9da45..891211093295 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c @@ -1,5 +1,5 @@ /* - * OMAP4 SMP source file. It contains platform specific fucntions + * OMAP4 SMP source file. It contains platform specific functions * needed for the linux smp kernel. * * Copyright (C) 2009 Texas Instruments, Inc. diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h index a086ba15868b..2d35c5709408 100644 --- a/arch/arm/mach-omap2/omap54xx.h +++ b/arch/arm/mach-omap2/omap54xx.h @@ -30,4 +30,8 @@ #define OMAP54XX_CTRL_BASE 0x4a002800 #define OMAP54XX_SAR_RAM_BASE 0x4ae26000 +#define DRA7XX_CM_CORE_AON_BASE 0x4a005000 +#define DRA7XX_CTRL_BASE 0x4a003400 +#define DRA7XX_TAP_BASE 0x4ae0c000 + #endif /* __ASM_SOC_OMAP555554XX_H */ diff --git a/arch/arm/mach-omap2/omap_device.c b/arch/arm/mach-omap2/omap_device.c index f99f68e1e85b..b69dd9abb50a 100644 --- a/arch/arm/mach-omap2/omap_device.c +++ b/arch/arm/mach-omap2/omap_device.c @@ -158,7 +158,7 @@ static int omap_device_build_from_dt(struct platform_device *pdev) } od = omap_device_alloc(pdev, hwmods, oh_cnt); - if (!od) { + if (IS_ERR(od)) { dev_err(&pdev->dev, "Cannot allocate omap_device for :%s\n", oh_name); ret = PTR_ERR(od); diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 7f4db12b1459..d9ee0ff094d4 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -1405,7 +1405,9 @@ static void _enable_sysc(struct omap_hwmod *oh) (sf & SYSC_HAS_CLOCKACTIVITY)) _set_clockactivity(oh, oh->class->sysc->clockact, &v); - _write_sysconfig(v, oh); + /* If the cached value is the same as the new value, skip the write */ + if (oh->_sysc_cache != v) + _write_sysconfig(v, oh); /* * Set the autoidle bit only after setting the smartidle bit @@ -4113,7 +4115,7 @@ void __init omap_hwmod_init(void) soc_ops.assert_hardreset = _omap2_assert_hardreset; soc_ops.deassert_hardreset = _omap2_deassert_hardreset; soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; - } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { + } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) { soc_ops.enable_module = _omap4_enable_module; soc_ops.disable_module = _omap4_disable_module; soc_ops.wait_target_ready = _omap4_wait_target_ready; diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h index e1482a9b3bc2..d02acf9308d3 100644 --- a/arch/arm/mach-omap2/omap_hwmod.h +++ b/arch/arm/mach-omap2/omap_hwmod.h @@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void); extern int omap44xx_hwmod_init(void); extern int omap54xx_hwmod_init(void); extern int am33xx_hwmod_init(void); +extern int dra7xx_hwmod_init(void); extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c index eb2f3b93b51c..215894f8910d 100644 --- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c @@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = { * * - cEFUSE (doesn't fall under any ocp_if) * - clkdiv32k - * - debugss * - ocp watch point */ #if 0 @@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = { }, }; -/* - * 'debugss' class - * debug sub system - */ -static struct omap_hwmod_class am33xx_debugss_hwmod_class = { - .name = "debugss", -}; - -static struct omap_hwmod am33xx_debugss_hwmod = { - .name = "debugss", - .class = &am33xx_debugss_hwmod_class, - .clkdm_name = "l3_aon_clkdm", - .main_clk = "debugss_ick", - .prcm = { - .omap4 = { - .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, - .modulemode = MODULEMODE_SWCTRL, - }, - }, -}; - /* ocpwp */ static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { .name = "ocpwp", @@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = { }, }; +/* + * 'debugss' class + * debug sub system + */ +static struct omap_hwmod_opt_clk debugss_opt_clks[] = { + { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" }, + { .role = "dbg_clka", .clk = "dbg_clka_ck" }, +}; + +static struct omap_hwmod_class am33xx_debugss_hwmod_class = { + .name = "debugss", +}; + +static struct omap_hwmod am33xx_debugss_hwmod = { + .name = "debugss", + .class = &am33xx_debugss_hwmod_class, + .clkdm_name = "l3_aon_clkdm", + .main_clk = "trace_clk_div_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = debugss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks), +}; + /* 'smartreflex' class */ static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { .name = "smartreflex", @@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l3_main -> debugss */ +static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = { + { + .pa_start = 0x4b000000, + .pa_end = 0x4b000000 + SZ_16M - 1, + .flags = ADDR_TYPE_RT + }, + { } +}; + +static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = { + .master = &am33xx_l3_main_hwmod, + .slave = &am33xx_debugss_hwmod, + .clk = "dpll_core_m4_ck", + .addr = am33xx_debugss_addrs, + .user = OCP_USER_MPU, +}; + /* l4 wkup -> smartreflex0 */ static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { .master = &am33xx_l4_wkup_hwmod, @@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { &am33xx_pruss__l3_main, &am33xx_wkup_m3__l4_wkup, &am33xx_gfx__l3_main, + &am33xx_l3_main__debugss, &am33xx_l4_wkup__wkup_m3, &am33xx_l4_wkup__control, &am33xx_l4_wkup__smartreflex0, diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c index 3c70f5c1860f..cde415570e04 100644 --- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c @@ -32,7 +32,6 @@ #include "cm1_54xx.h" #include "cm2_54xx.h" #include "prm54xx.h" -#include "prm-regbits-54xx.h" #include "i2c.h" #include "mmc.h" #include "wd_timer.h" @@ -741,6 +740,39 @@ static struct omap_hwmod omap54xx_kbd_hwmod = { }; /* + * 'mailbox' class + * mailbox module allowing communication between the on-chip processors using a + * queued mailbox-interrupt mechanism. + */ + +static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = { + .name = "mailbox", + .sysc = &omap54xx_mailbox_sysc, +}; + +/* mailbox */ +static struct omap_hwmod omap54xx_mailbox_hwmod = { + .name = "mailbox", + .class = &omap54xx_mailbox_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, + .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, + }, + }, +}; + +/* * 'mcbsp' class * multi channel buffered serial port controller */ @@ -1808,6 +1840,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = { .user = OCP_USER_MPU | OCP_USER_SDMA, }; +/* l4_cfg -> mailbox */ +static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = { + .master = &omap54xx_l4_cfg_hwmod, + .slave = &omap54xx_mailbox_hwmod, + .clk = "l4_root_clk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + /* l4_abe -> mcbsp1 */ static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { .master = &omap54xx_l4_abe_hwmod, @@ -2108,6 +2148,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = { &omap54xx_l4_per__i2c4, &omap54xx_l4_per__i2c5, &omap54xx_l4_wkup__kbd, + &omap54xx_l4_cfg__mailbox, &omap54xx_l4_abe__mcbsp1, &omap54xx_l4_abe__mcbsp2, &omap54xx_l4_abe__mcbsp3, diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c new file mode 100644 index 000000000000..db32d5380b11 --- /dev/null +++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c @@ -0,0 +1,2724 @@ +/* + * Hardware modules present on the DRA7xx chips + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Paul Walmsley + * Benoit Cousson + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/io.h> +#include <linux/platform_data/gpio-omap.h> +#include <linux/power/smartreflex.h> +#include <linux/i2c-omap.h> + +#include <linux/omap-dma.h> +#include <linux/platform_data/spi-omap2-mcspi.h> +#include <linux/platform_data/asoc-ti-mcbsp.h> +#include <plat/dmtimer.h> + +#include "omap_hwmod.h" +#include "omap_hwmod_common_data.h" +#include "cm1_7xx.h" +#include "cm2_7xx.h" +#include "prm7xx.h" +#include "i2c.h" +#include "mmc.h" +#include "wd_timer.h" + +/* Base offset for all DRA7XX interrupts external to MPUSS */ +#define DRA7XX_IRQ_GIC_START 32 + +/* Base offset for all DRA7XX dma requests */ +#define DRA7XX_DMA_REQ_START 1 + + +/* + * IP blocks + */ + +/* + * 'l3' class + * instance(s): l3_instr, l3_main_1, l3_main_2 + */ +static struct omap_hwmod_class dra7xx_l3_hwmod_class = { + .name = "l3", +}; + +/* l3_instr */ +static struct omap_hwmod dra7xx_l3_instr_hwmod = { + .name = "l3_instr", + .class = &dra7xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* l3_main_1 */ +static struct omap_hwmod dra7xx_l3_main_1_hwmod = { + .name = "l3_main_1", + .class = &dra7xx_l3_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET, + }, + }, +}; + +/* l3_main_2 */ +static struct omap_hwmod dra7xx_l3_main_2_hwmod = { + .name = "l3_main_2", + .class = &dra7xx_l3_hwmod_class, + .clkdm_name = "l3instr_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'l4' class + * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup + */ +static struct omap_hwmod_class dra7xx_l4_hwmod_class = { + .name = "l4", +}; + +/* l4_cfg */ +static struct omap_hwmod dra7xx_l4_cfg_hwmod = { + .name = "l4_cfg", + .class = &dra7xx_l4_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, + }, + }, +}; + +/* l4_per1 */ +static struct omap_hwmod dra7xx_l4_per1_hwmod = { + .name = "l4_per1", + .class = &dra7xx_l4_hwmod_class, + .clkdm_name = "l4per_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* l4_per2 */ +static struct omap_hwmod dra7xx_l4_per2_hwmod = { + .name = "l4_per2", + .class = &dra7xx_l4_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* l4_per3 */ +static struct omap_hwmod dra7xx_l4_per3_hwmod = { + .name = "l4_per3", + .class = &dra7xx_l4_hwmod_class, + .clkdm_name = "l4per3_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* l4_wkup */ +static struct omap_hwmod dra7xx_l4_wkup_hwmod = { + .name = "l4_wkup", + .class = &dra7xx_l4_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'atl' class + * + */ + +static struct omap_hwmod_class dra7xx_atl_hwmod_class = { + .name = "atl", +}; + +/* atl */ +static struct omap_hwmod dra7xx_atl_hwmod = { + .name = "atl", + .class = &dra7xx_atl_hwmod_class, + .clkdm_name = "atl_clkdm", + .main_clk = "atl_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'bb2d' class + * + */ + +static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = { + .name = "bb2d", +}; + +/* bb2d */ +static struct omap_hwmod dra7xx_bb2d_hwmod = { + .name = "bb2d", + .class = &dra7xx_bb2d_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dpll_core_h24x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'counter' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_counter_hwmod_class = { + .name = "counter", + .sysc = &dra7xx_counter_sysc, +}; + +/* counter_32k */ +static struct omap_hwmod dra7xx_counter_32k_hwmod = { + .name = "counter_32k", + .class = &dra7xx_counter_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .flags = HWMOD_SWSUP_SIDLE, + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'ctrl_module' class + * + */ + +static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = { + .name = "ctrl_module", +}; + +/* ctrl_module_wkup */ +static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = { + .name = "ctrl_module_wkup", + .class = &dra7xx_ctrl_module_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .prcm = { + .omap4 = { + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, +}; + +/* + * 'dcan' class + * + */ + +static struct omap_hwmod_class dra7xx_dcan_hwmod_class = { + .name = "dcan", +}; + +/* dcan1 */ +static struct omap_hwmod dra7xx_dcan1_hwmod = { + .name = "dcan1", + .class = &dra7xx_dcan_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "dcan1_sys_clk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* dcan2 */ +static struct omap_hwmod dra7xx_dcan2_hwmod = { + .name = "dcan2", + .class = &dra7xx_dcan_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "sys_clkin1", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'dma' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x002c, + .syss_offs = 0x0028, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_dma_hwmod_class = { + .name = "dma", + .sysc = &dra7xx_dma_sysc, +}; + +/* dma dev_attr */ +static struct omap_dma_dev_attr dma_dev_attr = { + .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | + IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, + .lch_count = 32, +}; + +/* dma_system */ +static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = { + { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START }, + { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START }, + { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START }, + { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START }, + { .irq = -1 } +}; + +static struct omap_hwmod dra7xx_dma_system_hwmod = { + .name = "dma_system", + .class = &dra7xx_dma_hwmod_class, + .clkdm_name = "dma_clkdm", + .mpu_irqs = dra7xx_dma_system_irqs, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET, + }, + }, + .dev_attr = &dma_dev_attr, +}; + +/* + * 'dss' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = { + .rev_offs = 0x0000, + .syss_offs = 0x0014, + .sysc_flags = SYSS_HAS_RESET_STATUS, +}; + +static struct omap_hwmod_class dra7xx_dss_hwmod_class = { + .name = "dss", + .sysc = &dra7xx_dss_sysc, + .reset = omap_dss_reset, +}; + +/* dss */ +static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = { + { .dma_req = 75 + DRA7XX_DMA_REQ_START }, + { .dma_req = -1 } +}; + +static struct omap_hwmod_opt_clk dss_opt_clks[] = { + { .role = "dss_clk", .clk = "dss_dss_clk" }, + { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" }, + { .role = "32khz_clk", .clk = "dss_32khz_clk" }, + { .role = "video2_clk", .clk = "dss_video2_clk" }, + { .role = "video1_clk", .clk = "dss_video1_clk" }, + { .role = "hdmi_clk", .clk = "dss_hdmi_clk" }, +}; + +static struct omap_hwmod dra7xx_dss_hwmod = { + .name = "dss_core", + .class = &dra7xx_dss_hwmod_class, + .clkdm_name = "dss_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .sdma_reqs = dra7xx_dss_sdma_reqs, + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = dss_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), +}; + +/* + * 'dispc' class + * display controller + */ + +static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_dispc_hwmod_class = { + .name = "dispc", + .sysc = &dra7xx_dispc_sysc, +}; + +/* dss_dispc */ +/* dss_dispc dev_attr */ +static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = { + .has_framedonetv_irq = 1, + .manager_count = 4, +}; + +static struct omap_hwmod dra7xx_dss_dispc_hwmod = { + .name = "dss_dispc", + .class = &dra7xx_dispc_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_dss_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .dev_attr = &dss_dispc_dev_attr, +}; + +/* + * 'hdmi' class + * hdmi controller + */ + +static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = { + .name = "hdmi", + .sysc = &dra7xx_hdmi_sysc, +}; + +/* dss_hdmi */ + +static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { + { .role = "sys_clk", .clk = "dss_hdmi_clk" }, +}; + +static struct omap_hwmod dra7xx_dss_hdmi_hwmod = { + .name = "dss_hdmi", + .class = &dra7xx_hdmi_hwmod_class, + .clkdm_name = "dss_clkdm", + .main_clk = "dss_48mhz_clk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET, + .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT, + }, + }, + .opt_clks = dss_hdmi_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), +}; + +/* + * 'elm' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_elm_hwmod_class = { + .name = "elm", + .sysc = &dra7xx_elm_sysc, +}; + +/* elm */ + +static struct omap_hwmod dra7xx_elm_hwmod = { + .name = "elm", + .class = &dra7xx_elm_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'gpio' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0114, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_gpio_hwmod_class = { + .name = "gpio", + .sysc = &dra7xx_gpio_sysc, + .rev = 2, +}; + +/* gpio dev_attr */ +static struct omap_gpio_dev_attr gpio_dev_attr = { + .bank_width = 32, + .dbck_flag = true, +}; + +/* gpio1 */ +static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { + { .role = "dbclk", .clk = "gpio1_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio1_hwmod = { + .name = "gpio1", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio2 */ +static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { + { .role = "dbclk", .clk = "gpio2_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio2_hwmod = { + .name = "gpio2", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio3 */ +static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { + { .role = "dbclk", .clk = "gpio3_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio3_hwmod = { + .name = "gpio3", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio4 */ +static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { + { .role = "dbclk", .clk = "gpio4_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio4_hwmod = { + .name = "gpio4", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio5 */ +static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { + { .role = "dbclk", .clk = "gpio5_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio5_hwmod = { + .name = "gpio5", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio5_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio6 */ +static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { + { .role = "dbclk", .clk = "gpio6_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio6_hwmod = { + .name = "gpio6", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio6_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio7 */ +static struct omap_hwmod_opt_clk gpio7_opt_clks[] = { + { .role = "dbclk", .clk = "gpio7_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio7_hwmod = { + .name = "gpio7", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio7_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* gpio8 */ +static struct omap_hwmod_opt_clk gpio8_opt_clks[] = { + { .role = "dbclk", .clk = "gpio8_dbclk" }, +}; + +static struct omap_hwmod dra7xx_gpio8_hwmod = { + .name = "gpio8", + .class = &dra7xx_gpio_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = gpio8_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks), + .dev_attr = &gpio_dev_attr, +}; + +/* + * 'gpmc' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = { + .name = "gpmc", + .sysc = &dra7xx_gpmc_sysc, +}; + +/* gpmc */ + +static struct omap_hwmod dra7xx_gpmc_hwmod = { + .name = "gpmc", + .class = &dra7xx_gpmc_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'hdq1w' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0014, + .syss_offs = 0x0018, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = { + .name = "hdq1w", + .sysc = &dra7xx_hdq1w_sysc, +}; + +/* hdq1w */ + +static struct omap_hwmod dra7xx_hdq1w_hwmod = { + .name = "hdq1w", + .class = &dra7xx_hdq1w_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_INIT_NO_RESET, + .main_clk = "func_12m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'i2c' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = { + .sysc_offs = 0x0010, + .syss_offs = 0x0090, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .clockact = CLOCKACT_TEST_ICLK, + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_i2c_hwmod_class = { + .name = "i2c", + .sysc = &dra7xx_i2c_sysc, + .reset = &omap_i2c_reset, + .rev = OMAP_I2C_IP_VERSION_2, +}; + +/* i2c dev_attr */ +static struct omap_i2c_dev_attr i2c_dev_attr = { + .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, +}; + +/* i2c1 */ +static struct omap_hwmod dra7xx_i2c1_hwmod = { + .name = "i2c1", + .class = &dra7xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c2 */ +static struct omap_hwmod dra7xx_i2c2_hwmod = { + .name = "i2c2", + .class = &dra7xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c3 */ +static struct omap_hwmod dra7xx_i2c3_hwmod = { + .name = "i2c3", + .class = &dra7xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c4 */ +static struct omap_hwmod dra7xx_i2c4_hwmod = { + .name = "i2c4", + .class = &dra7xx_i2c_hwmod_class, + .clkdm_name = "l4per_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* i2c5 */ +static struct omap_hwmod dra7xx_i2c5_hwmod = { + .name = "i2c5", + .class = &dra7xx_i2c_hwmod_class, + .clkdm_name = "ipu_clkdm", + .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, + .main_clk = "func_96m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &i2c_dev_attr, +}; + +/* + * 'mcspi' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = { + .name = "mcspi", + .sysc = &dra7xx_mcspi_sysc, + .rev = OMAP4_MCSPI_REV, +}; + +/* mcspi1 */ +/* mcspi1 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { + .num_chipselect = 4, +}; + +static struct omap_hwmod dra7xx_mcspi1_hwmod = { + .name = "mcspi1", + .class = &dra7xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi1_dev_attr, +}; + +/* mcspi2 */ +/* mcspi2 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod dra7xx_mcspi2_hwmod = { + .name = "mcspi2", + .class = &dra7xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi2_dev_attr, +}; + +/* mcspi3 */ +/* mcspi3 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { + .num_chipselect = 2, +}; + +static struct omap_hwmod dra7xx_mcspi3_hwmod = { + .name = "mcspi3", + .class = &dra7xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi3_dev_attr, +}; + +/* mcspi4 */ +/* mcspi4 dev_attr */ +static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { + .num_chipselect = 1, +}; + +static struct omap_hwmod dra7xx_mcspi4_hwmod = { + .name = "mcspi4", + .class = &dra7xx_mcspi_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &mcspi4_dev_attr, +}; + +/* + * 'mmc' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | + SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_mmc_hwmod_class = { + .name = "mmc", + .sysc = &dra7xx_mmc_sysc, +}; + +/* mmc1 */ +static struct omap_hwmod_opt_clk mmc1_opt_clks[] = { + { .role = "clk32k", .clk = "mmc1_clk32k" }, +}; + +/* mmc1 dev_attr */ +static struct omap_mmc_dev_attr mmc1_dev_attr = { + .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, +}; + +static struct omap_hwmod dra7xx_mmc1_hwmod = { + .name = "mmc1", + .class = &dra7xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc1_fclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks), + .dev_attr = &mmc1_dev_attr, +}; + +/* mmc2 */ +static struct omap_hwmod_opt_clk mmc2_opt_clks[] = { + { .role = "clk32k", .clk = "mmc2_clk32k" }, +}; + +static struct omap_hwmod dra7xx_mmc2_hwmod = { + .name = "mmc2", + .class = &dra7xx_mmc_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "mmc2_fclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks), +}; + +/* mmc3 */ +static struct omap_hwmod_opt_clk mmc3_opt_clks[] = { + { .role = "clk32k", .clk = "mmc3_clk32k" }, +}; + +static struct omap_hwmod dra7xx_mmc3_hwmod = { + .name = "mmc3", + .class = &dra7xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "mmc3_gfclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc3_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks), +}; + +/* mmc4 */ +static struct omap_hwmod_opt_clk mmc4_opt_clks[] = { + { .role = "clk32k", .clk = "mmc4_clk32k" }, +}; + +static struct omap_hwmod dra7xx_mmc4_hwmod = { + .name = "mmc4", + .class = &dra7xx_mmc_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "mmc4_gfclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = mmc4_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks), +}; + +/* + * 'mpu' class + * + */ + +static struct omap_hwmod_class dra7xx_mpu_hwmod_class = { + .name = "mpu", +}; + +/* mpu */ +static struct omap_hwmod dra7xx_mpu_hwmod = { + .name = "mpu", + .class = &dra7xx_mpu_hwmod_class, + .clkdm_name = "mpu_clkdm", + .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, + .main_clk = "dpll_mpu_m2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'ocp2scp' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = { + .name = "ocp2scp", + .sysc = &dra7xx_ocp2scp_sysc, +}; + +/* ocp2scp1 */ +static struct omap_hwmod dra7xx_ocp2scp1_hwmod = { + .name = "ocp2scp1", + .class = &dra7xx_ocp2scp_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "l4_root_clk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'qspi' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = { + .sysc_offs = 0x0010, + .sysc_flags = SYSC_HAS_SIDLEMODE, + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_qspi_hwmod_class = { + .name = "qspi", + .sysc = &dra7xx_qspi_sysc, +}; + +/* qspi */ +static struct omap_hwmod dra7xx_qspi_hwmod = { + .name = "qspi", + .class = &dra7xx_qspi_hwmod_class, + .clkdm_name = "l4per2_clkdm", + .main_clk = "qspi_gfclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'sata' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = { + .sysc_offs = 0x0000, + .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | + MSTANDBY_SMART | MSTANDBY_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_sata_hwmod_class = { + .name = "sata", + .sysc = &dra7xx_sata_sysc, +}; + +/* sata */ +static struct omap_hwmod_opt_clk sata_opt_clks[] = { + { .role = "ref_clk", .clk = "sata_ref_clk" }, +}; + +static struct omap_hwmod dra7xx_sata_hwmod = { + .name = "sata", + .class = &dra7xx_sata_hwmod_class, + .clkdm_name = "l3init_clkdm", + .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, + .main_clk = "func_48m_fclk", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .opt_clks = sata_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks), +}; + +/* + * 'smartreflex' class + * + */ + +/* The IP is not compliant to type1 / type2 scheme */ +static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { + .sidle_shift = 24, + .enwkup_shift = 26, +}; + +static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = { + .sysc_offs = 0x0038, + .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type_smartreflex, +}; + +static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = { + .name = "smartreflex", + .sysc = &dra7xx_smartreflex_sysc, + .rev = 2, +}; + +/* smartreflex_core */ +/* smartreflex_core dev_attr */ +static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { + .sensor_voltdm_name = "core", +}; + +static struct omap_hwmod dra7xx_smartreflex_core_hwmod = { + .name = "smartreflex_core", + .class = &dra7xx_smartreflex_hwmod_class, + .clkdm_name = "coreaon_clkdm", + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &smartreflex_core_dev_attr, +}; + +/* smartreflex_mpu */ +/* smartreflex_mpu dev_attr */ +static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { + .sensor_voltdm_name = "mpu", +}; + +static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = { + .name = "smartreflex_mpu", + .class = &dra7xx_smartreflex_hwmod_class, + .clkdm_name = "coreaon_clkdm", + .main_clk = "wkupaon_iclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, + .dev_attr = &smartreflex_mpu_dev_attr, +}; + +/* + * 'spinlock' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | + SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = { + .name = "spinlock", + .sysc = &dra7xx_spinlock_sysc, +}; + +/* spinlock */ +static struct omap_hwmod dra7xx_spinlock_hwmod = { + .name = "spinlock", + .class = &dra7xx_spinlock_hwmod_class, + .clkdm_name = "l4cfg_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'timer' class + * + * This class contains several variants: ['timer_1ms', 'timer_secure', + * 'timer'] + */ + +static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = { + .name = "timer", + .sysc = &dra7xx_timer_1ms_sysc, +}; + +static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = { + .name = "timer", + .sysc = &dra7xx_timer_secure_sysc, +}; + +static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type2, +}; + +static struct omap_hwmod_class dra7xx_timer_hwmod_class = { + .name = "timer", + .sysc = &dra7xx_timer_sysc, +}; + +/* timer1 */ +static struct omap_hwmod dra7xx_timer1_hwmod = { + .name = "timer1", + .class = &dra7xx_timer_1ms_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "timer1_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer2 */ +static struct omap_hwmod dra7xx_timer2_hwmod = { + .name = "timer2", + .class = &dra7xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer2_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer3 */ +static struct omap_hwmod dra7xx_timer3_hwmod = { + .name = "timer3", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer3_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer4 */ +static struct omap_hwmod dra7xx_timer4_hwmod = { + .name = "timer4", + .class = &dra7xx_timer_secure_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer4_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer5 */ +static struct omap_hwmod dra7xx_timer5_hwmod = { + .name = "timer5", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "timer5_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer6 */ +static struct omap_hwmod dra7xx_timer6_hwmod = { + .name = "timer6", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "timer6_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer7 */ +static struct omap_hwmod dra7xx_timer7_hwmod = { + .name = "timer7", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "timer7_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer8 */ +static struct omap_hwmod dra7xx_timer8_hwmod = { + .name = "timer8", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "timer8_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer9 */ +static struct omap_hwmod dra7xx_timer9_hwmod = { + .name = "timer9", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer9_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer10 */ +static struct omap_hwmod dra7xx_timer10_hwmod = { + .name = "timer10", + .class = &dra7xx_timer_1ms_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer10_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* timer11 */ +static struct omap_hwmod dra7xx_timer11_hwmod = { + .name = "timer11", + .class = &dra7xx_timer_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "timer11_gfclk_mux", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'uart' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = { + .rev_offs = 0x0050, + .sysc_offs = 0x0054, + .syss_offs = 0x0058, + .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | + SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | + SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_uart_hwmod_class = { + .name = "uart", + .sysc = &dra7xx_uart_sysc, +}; + +/* uart1 */ +static struct omap_hwmod dra7xx_uart1_hwmod = { + .name = "uart1", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "uart1_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart2 */ +static struct omap_hwmod dra7xx_uart2_hwmod = { + .name = "uart2", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "uart2_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart3 */ +static struct omap_hwmod dra7xx_uart3_hwmod = { + .name = "uart3", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "uart3_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart4 */ +static struct omap_hwmod dra7xx_uart4_hwmod = { + .name = "uart4", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "uart4_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart5 */ +static struct omap_hwmod dra7xx_uart5_hwmod = { + .name = "uart5", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "l4per_clkdm", + .main_clk = "uart5_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* uart6 */ +static struct omap_hwmod dra7xx_uart6_hwmod = { + .name = "uart6", + .class = &dra7xx_uart_hwmod_class, + .clkdm_name = "ipu_clkdm", + .main_clk = "uart6_gfclk_mux", + .flags = HWMOD_SWSUP_SIDLE_ACT, + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + +/* + * 'usb_otg_ss' class + * + */ + +static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = { + .name = "usb_otg_ss", +}; + +/* usb_otg_ss1 */ +static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = { + { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" }, +}; + +static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = { + .name = "usb_otg_ss1", + .class = &dra7xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = usb_otg_ss1_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks), +}; + +/* usb_otg_ss2 */ +static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = { + { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" }, +}; + +static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = { + .name = "usb_otg_ss2", + .class = &dra7xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, + .opt_clks = usb_otg_ss2_opt_clks, + .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks), +}; + +/* usb_otg_ss3 */ +static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = { + .name = "usb_otg_ss3", + .class = &dra7xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* usb_otg_ss4 */ +static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = { + .name = "usb_otg_ss4", + .class = &dra7xx_usb_otg_ss_hwmod_class, + .clkdm_name = "l3init_clkdm", + .main_clk = "dpll_core_h13x2_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET, + .modulemode = MODULEMODE_HWCTRL, + }, + }, +}; + +/* + * 'vcp' class + * + */ + +static struct omap_hwmod_class dra7xx_vcp_hwmod_class = { + .name = "vcp", +}; + +/* vcp1 */ +static struct omap_hwmod dra7xx_vcp1_hwmod = { + .name = "vcp1", + .class = &dra7xx_vcp_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET, + }, + }, +}; + +/* vcp2 */ +static struct omap_hwmod dra7xx_vcp2_hwmod = { + .name = "vcp2", + .class = &dra7xx_vcp_hwmod_class, + .clkdm_name = "l3main1_clkdm", + .main_clk = "l3_iclk_div", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET, + }, + }, +}; + +/* + * 'wd_timer' class + * + */ + +static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = { + .rev_offs = 0x0000, + .sysc_offs = 0x0010, + .syss_offs = 0x0014, + .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | + SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | + SIDLE_SMART_WKUP), + .sysc_fields = &omap_hwmod_sysc_type1, +}; + +static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = { + .name = "wd_timer", + .sysc = &dra7xx_wd_timer_sysc, + .pre_shutdown = &omap2_wd_timer_disable, + .reset = &omap2_wd_timer_reset, +}; + +/* wd_timer2 */ +static struct omap_hwmod dra7xx_wd_timer2_hwmod = { + .name = "wd_timer2", + .class = &dra7xx_wd_timer_hwmod_class, + .clkdm_name = "wkupaon_clkdm", + .main_clk = "sys_32k_ck", + .prcm = { + .omap4 = { + .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET, + .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET, + .modulemode = MODULEMODE_SWCTRL, + }, + }, +}; + + +/* + * Interfaces + */ + +/* l3_main_2 -> l3_instr */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = { + .master = &dra7xx_l3_main_2_hwmod, + .slave = &dra7xx_l3_instr_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* mpu -> l3_main_1 */ +static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = { + .master = &dra7xx_mpu_hwmod, + .slave = &dra7xx_l3_main_1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l3_main_1 -> l3_main_2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU, +}; + +/* l4_cfg -> l3_main_2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_l3_main_2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_cfg */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l4_cfg_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_per1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l4_per1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_per2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l4_per2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_per3 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l4_per3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> l4_wkup */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_l4_wkup_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> atl */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_atl_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> bb2d */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_bb2d_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> counter_32k */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_counter_32k_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> ctrl_module_wkup */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_ctrl_module_wkup_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> dcan1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_dcan1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> dcan2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_dcan2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = { + { + .pa_start = 0x4a056000, + .pa_end = 0x4a056fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> dma_system */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_dma_system_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_dma_system_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = { + { + .name = "family", + .pa_start = 0x58000000, + .pa_end = 0x5800007f, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_1 -> dss */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_dss_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_dss_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = { + { + .name = "dispc", + .pa_start = 0x58001000, + .pa_end = 0x58001fff, + .flags = ADDR_TYPE_RT + }, +}; + +/* l3_main_1 -> dispc */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_dss_dispc_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_dss_dispc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = { + { + .name = "hdmi_wp", + .pa_start = 0x58040000, + .pa_end = 0x580400ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> dispc */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_dss_hdmi_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_dss_hdmi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = { + { + .pa_start = 0x48078000, + .pa_end = 0x48078fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per1 -> elm */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_elm_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_elm_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> gpio1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_gpio1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio7_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> gpio8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_gpio8_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = { + { + .pa_start = 0x50000000, + .pa_end = 0x500003ff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> gpmc */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_gpmc_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_gpmc_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = { + { + .pa_start = 0x480b2000, + .pa_end = 0x480b201f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_per1 -> hdq1w */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_hdq1w_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_hdq1w_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> i2c1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_i2c1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> i2c2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_i2c2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> i2c3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_i2c3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> i2c4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_i2c4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> i2c5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_i2c5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mcspi1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mcspi1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mcspi2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mcspi2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mcspi3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mcspi3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mcspi4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mcspi4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mmc1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mmc1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mmc2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mmc2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mmc3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mmc3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> mmc4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_mmc4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_cfg -> mpu */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_mpu_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = { + { + .pa_start = 0x4a080000, + .pa_end = 0x4a08001f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> ocp2scp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_ocp2scp1_hwmod, + .clk = "l4_root_clk_div", + .addr = dra7xx_ocp2scp1_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = { + { + .pa_start = 0x4b300000, + .pa_end = 0x4b30007f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l3_main_1 -> qspi */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_qspi_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_qspi_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = { + { + .name = "sysc", + .pa_start = 0x4a141100, + .pa_end = 0x4a141107, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> sata */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_sata_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_sata_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = { + { + .pa_start = 0x4a0dd000, + .pa_end = 0x4a0dd07f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_core */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_smartreflex_core_hwmod, + .clk = "l4_root_clk_div", + .addr = dra7xx_smartreflex_core_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = { + { + .pa_start = 0x4a0d9000, + .pa_end = 0x4a0d907f, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> smartreflex_mpu */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_smartreflex_mpu_hwmod, + .clk = "l4_root_clk_div", + .addr = dra7xx_smartreflex_mpu_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = { + { + .pa_start = 0x4a0f6000, + .pa_end = 0x4a0f6fff, + .flags = ADDR_TYPE_RT + }, + { } +}; + +/* l4_cfg -> spinlock */ +static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = { + .master = &dra7xx_l4_cfg_hwmod, + .slave = &dra7xx_spinlock_hwmod, + .clk = "l3_iclk_div", + .addr = dra7xx_spinlock_addrs, + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> timer1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_timer1_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> timer5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_timer5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> timer6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_timer6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> timer7 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_timer7_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> timer8 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_timer8_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer9 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer9_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer10 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer10_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> timer11 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_timer11_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart3_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart4_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart5 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart5_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per1 -> uart6 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = { + .master = &dra7xx_l4_per1_hwmod, + .slave = &dra7xx_uart6_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> usb_otg_ss1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_usb_otg_ss1_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> usb_otg_ss2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_usb_otg_ss2_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> usb_otg_ss3 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_usb_otg_ss3_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per3 -> usb_otg_ss4 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = { + .master = &dra7xx_l4_per3_hwmod, + .slave = &dra7xx_usb_otg_ss4_hwmod, + .clk = "dpll_core_h13x2_ck", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> vcp1 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_vcp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> vcp1 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_vcp1_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l3_main_1 -> vcp2 */ +static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = { + .master = &dra7xx_l3_main_1_hwmod, + .slave = &dra7xx_vcp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_per2 -> vcp2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = { + .master = &dra7xx_l4_per2_hwmod, + .slave = &dra7xx_vcp2_hwmod, + .clk = "l3_iclk_div", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +/* l4_wkup -> wd_timer2 */ +static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = { + .master = &dra7xx_l4_wkup_hwmod, + .slave = &dra7xx_wd_timer2_hwmod, + .clk = "wkupaon_iclk_mux", + .user = OCP_USER_MPU | OCP_USER_SDMA, +}; + +static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = { + &dra7xx_l3_main_2__l3_instr, + &dra7xx_l4_cfg__l3_main_1, + &dra7xx_mpu__l3_main_1, + &dra7xx_l3_main_1__l3_main_2, + &dra7xx_l4_cfg__l3_main_2, + &dra7xx_l3_main_1__l4_cfg, + &dra7xx_l3_main_1__l4_per1, + &dra7xx_l3_main_1__l4_per2, + &dra7xx_l3_main_1__l4_per3, + &dra7xx_l3_main_1__l4_wkup, + &dra7xx_l4_per2__atl, + &dra7xx_l3_main_1__bb2d, + &dra7xx_l4_wkup__counter_32k, + &dra7xx_l4_wkup__ctrl_module_wkup, + &dra7xx_l4_wkup__dcan1, + &dra7xx_l4_per2__dcan2, + &dra7xx_l4_cfg__dma_system, + &dra7xx_l3_main_1__dss, + &dra7xx_l3_main_1__dispc, + &dra7xx_l3_main_1__hdmi, + &dra7xx_l4_per1__elm, + &dra7xx_l4_wkup__gpio1, + &dra7xx_l4_per1__gpio2, + &dra7xx_l4_per1__gpio3, + &dra7xx_l4_per1__gpio4, + &dra7xx_l4_per1__gpio5, + &dra7xx_l4_per1__gpio6, + &dra7xx_l4_per1__gpio7, + &dra7xx_l4_per1__gpio8, + &dra7xx_l3_main_1__gpmc, + &dra7xx_l4_per1__hdq1w, + &dra7xx_l4_per1__i2c1, + &dra7xx_l4_per1__i2c2, + &dra7xx_l4_per1__i2c3, + &dra7xx_l4_per1__i2c4, + &dra7xx_l4_per1__i2c5, + &dra7xx_l4_per1__mcspi1, + &dra7xx_l4_per1__mcspi2, + &dra7xx_l4_per1__mcspi3, + &dra7xx_l4_per1__mcspi4, + &dra7xx_l4_per1__mmc1, + &dra7xx_l4_per1__mmc2, + &dra7xx_l4_per1__mmc3, + &dra7xx_l4_per1__mmc4, + &dra7xx_l4_cfg__mpu, + &dra7xx_l4_cfg__ocp2scp1, + &dra7xx_l3_main_1__qspi, + &dra7xx_l4_cfg__sata, + &dra7xx_l4_cfg__smartreflex_core, + &dra7xx_l4_cfg__smartreflex_mpu, + &dra7xx_l4_cfg__spinlock, + &dra7xx_l4_wkup__timer1, + &dra7xx_l4_per1__timer2, + &dra7xx_l4_per1__timer3, + &dra7xx_l4_per1__timer4, + &dra7xx_l4_per3__timer5, + &dra7xx_l4_per3__timer6, + &dra7xx_l4_per3__timer7, + &dra7xx_l4_per3__timer8, + &dra7xx_l4_per1__timer9, + &dra7xx_l4_per1__timer10, + &dra7xx_l4_per1__timer11, + &dra7xx_l4_per1__uart1, + &dra7xx_l4_per1__uart2, + &dra7xx_l4_per1__uart3, + &dra7xx_l4_per1__uart4, + &dra7xx_l4_per1__uart5, + &dra7xx_l4_per1__uart6, + &dra7xx_l4_per3__usb_otg_ss1, + &dra7xx_l4_per3__usb_otg_ss2, + &dra7xx_l4_per3__usb_otg_ss3, + &dra7xx_l4_per3__usb_otg_ss4, + &dra7xx_l3_main_1__vcp1, + &dra7xx_l4_per2__vcp1, + &dra7xx_l3_main_1__vcp2, + &dra7xx_l4_per2__vcp2, + &dra7xx_l4_wkup__wd_timer2, + NULL, +}; + +int __init dra7xx_hwmod_init(void) +{ + omap_hwmod_init(); + return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs); +} diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h index e4d7bd6f94b8..baf3d8bf6bea 100644 --- a/arch/arm/mach-omap2/powerdomain.h +++ b/arch/arm/mach-omap2/powerdomain.h @@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void); extern void am33xx_powerdomains_init(void); extern void omap44xx_powerdomains_init(void); extern void omap54xx_powerdomains_init(void); +extern void dra7xx_powerdomains_init(void); extern struct pwrdm_ops omap2_pwrdm_operations; extern struct pwrdm_ops omap3_pwrdm_operations; diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index e2d4bd804523..328c1037cb60 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = { .voltdm = { .name = "core" }, }; +static struct powerdomain alwon_81xx_pwrdm = { + .name = "alwon_pwrdm", + .prcm_offs = TI81XX_PRM_ALWON_MOD, + .pwrsts = PWRSTS_OFF_ON, + .voltdm = { .name = "core" }, +}; + static struct powerdomain device_81xx_pwrdm = { .name = "device_pwrdm", .prcm_offs = TI81XX_PRM_DEVICE_MOD, @@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = { }; static struct powerdomain *powerdomains_ti81xx[] __initdata = { + &alwon_81xx_pwrdm, &device_81xx_pwrdm, &active_816x_pwrdm, &default_816x_pwrdm, diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c index 81f8a7cc26ee..ce1d752af991 100644 --- a/arch/arm/mach-omap2/powerdomains54xx_data.c +++ b/arch/arm/mach-omap2/powerdomains54xx_data.c @@ -25,7 +25,6 @@ #include "prcm-common.h" #include "prcm44xx.h" -#include "prm-regbits-54xx.h" #include "prm54xx.h" #include "prcm_mpu54xx.h" diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c new file mode 100644 index 000000000000..48151d1cfde0 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomains7xx_data.c @@ -0,0 +1,454 @@ +/* + * DRA7xx Power domains framework + * + * Copyright (C) 2009-2013 Texas Instruments, Inc. + * Copyright (C) 2009-2011 Nokia Corporation + * + * Generated by code originally written by: + * Abhijit Pagare (abhijitpagare@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * Paul Walmsley (paul@pwsan.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "powerdomain.h" + +#include "prcm-common.h" +#include "prcm44xx.h" +#include "prm7xx.h" +#include "prcm_mpu7xx.h" + +/* iva_7xx_pwrdm: IVA-HD power domain */ +static struct powerdomain iva_7xx_pwrdm = { + .name = "iva_pwrdm", + .prcm_offs = DRA7XX_PRM_IVA_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 4, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* hwa_mem */ + [1] = PWRSTS_OFF_RET, /* sl2_mem */ + [2] = PWRSTS_OFF_RET, /* tcm1_mem */ + [3] = PWRSTS_OFF_RET, /* tcm2_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* rtc_7xx_pwrdm: */ +static struct powerdomain rtc_7xx_pwrdm = { + .name = "rtc_pwrdm", + .prcm_offs = DRA7XX_PRM_RTC_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, +}; + +/* custefuse_7xx_pwrdm: Customer efuse controller power domain */ +static struct powerdomain custefuse_7xx_pwrdm = { + .name = "custefuse_pwrdm", + .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* ipu_7xx_pwrdm: Audio back end power domain */ +static struct powerdomain ipu_7xx_pwrdm = { + .name = "ipu_pwrdm", + .prcm_offs = DRA7XX_PRM_IPU_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* aessmem */ + [1] = PWRSTS_OFF_RET, /* periphmem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dss_7xx_pwrdm: Display subsystem power domain */ +static struct powerdomain dss_7xx_pwrdm = { + .name = "dss_pwrdm", + .prcm_offs = DRA7XX_PRM_DSS_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dss_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* l4per_7xx_pwrdm: Target peripherals power domain */ +static struct powerdomain l4per_7xx_pwrdm = { + .name = "l4per_pwrdm", + .prcm_offs = DRA7XX_PRM_L4PER_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* nonretained_bank */ + [1] = PWRSTS_OFF_RET, /* retained_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* nonretained_bank */ + [1] = PWRSTS_OFF_RET, /* retained_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* gpu_7xx_pwrdm: 3D accelerator power domain */ +static struct powerdomain gpu_7xx_pwrdm = { + .name = "gpu_pwrdm", + .prcm_offs = DRA7XX_PRM_GPU_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* gpu_mem */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* wkupaon_7xx_pwrdm: Wake-up power domain */ +static struct powerdomain wkupaon_7xx_pwrdm = { + .name = "wkupaon_pwrdm", + .prcm_offs = DRA7XX_PRM_WKUPAON_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, + .banks = 1, + .pwrsts_mem_ret = { + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* wkup_bank */ + }, +}; + +/* core_7xx_pwrdm: CORE power domain */ +static struct powerdomain core_7xx_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = DRA7XX_PRM_CORE_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 5, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* core_nret_bank */ + [1] = PWRSTS_OFF_RET, /* core_ocmram */ + [2] = PWRSTS_OFF_RET, /* core_other_bank */ + [3] = PWRSTS_OFF_RET, /* ipu_l2ram */ + [4] = PWRSTS_OFF_RET, /* ipu_unicache */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ +static struct powerdomain coreaon_7xx_pwrdm = { + .name = "coreaon_pwrdm", + .prcm_offs = DRA7XX_PRM_COREAON_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_ON, +}; + +/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ +static struct powerdomain cpu0_7xx_pwrdm = { + .name = "cpu0_pwrdm", + .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, + .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu0_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu0_l1 */ + }, +}; + +/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ +static struct powerdomain cpu1_7xx_pwrdm = { + .name = "cpu1_pwrdm", + .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, + .prcm_partition = DRA7XX_MPU_PRCM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* cpu1_l1 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_ON, /* cpu1_l1 */ + }, +}; + +/* vpe_7xx_pwrdm: */ +static struct powerdomain vpe_7xx_pwrdm = { + .name = "vpe_pwrdm", + .prcm_offs = DRA7XX_PRM_VPE_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* vpe_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* vpe_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ +static struct powerdomain mpu_7xx_pwrdm = { + .name = "mpu_pwrdm", + .prcm_offs = DRA7XX_PRM_MPU_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_RET, /* mpu_ram */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* mpu_l2 */ + [1] = PWRSTS_OFF_RET, /* mpu_ram */ + }, +}; + +/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ +static struct powerdomain l3init_7xx_pwrdm = { + .name = "l3init_pwrdm", + .prcm_offs = DRA7XX_PRM_L3INIT_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_RET_ON, + .pwrsts_logic_ret = PWRSTS_OFF_RET, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* gmac_bank */ + [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* gmac_bank */ + [1] = PWRSTS_OFF_RET, /* l3init_bank1 */ + [2] = PWRSTS_OFF_RET, /* l3init_bank2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* eve3_7xx_pwrdm: */ +static struct powerdomain eve3_7xx_pwrdm = { + .name = "eve3_pwrdm", + .prcm_offs = DRA7XX_PRM_EVE3_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* eve3_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* eve3_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* emu_7xx_pwrdm: Emulation power domain */ +static struct powerdomain emu_7xx_pwrdm = { + .name = "emu_pwrdm", + .prcm_offs = DRA7XX_PRM_EMU_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* emu_bank */ + }, +}; + +/* dsp2_7xx_pwrdm: */ +static struct powerdomain dsp2_7xx_pwrdm = { + .name = "dsp2_pwrdm", + .prcm_offs = DRA7XX_PRM_DSP2_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dsp2_edma */ + [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dsp2_edma */ + [1] = PWRSTS_OFF_RET, /* dsp2_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp2_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* dsp1_7xx_pwrdm: Tesla processor power domain */ +static struct powerdomain dsp1_7xx_pwrdm = { + .name = "dsp1_pwrdm", + .prcm_offs = DRA7XX_PRM_DSP1_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 3, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* dsp1_edma */ + [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* dsp1_edma */ + [1] = PWRSTS_OFF_RET, /* dsp1_l1 */ + [2] = PWRSTS_OFF_RET, /* dsp1_l2 */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* cam_7xx_pwrdm: Camera subsystem power domain */ +static struct powerdomain cam_7xx_pwrdm = { + .name = "cam_pwrdm", + .prcm_offs = DRA7XX_PRM_CAM_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* vip_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* vip_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* eve4_7xx_pwrdm: */ +static struct powerdomain eve4_7xx_pwrdm = { + .name = "eve4_pwrdm", + .prcm_offs = DRA7XX_PRM_EVE4_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* eve4_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* eve4_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* eve2_7xx_pwrdm: */ +static struct powerdomain eve2_7xx_pwrdm = { + .name = "eve2_pwrdm", + .prcm_offs = DRA7XX_PRM_EVE2_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* eve2_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* eve2_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* eve1_7xx_pwrdm: */ +static struct powerdomain eve1_7xx_pwrdm = { + .name = "eve1_pwrdm", + .prcm_offs = DRA7XX_PRM_EVE1_INST, + .prcm_partition = DRA7XX_PRM_PARTITION, + .pwrsts = PWRSTS_OFF_ON, + .banks = 1, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* eve1_bank */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET, /* eve1_bank */ + }, + .flags = PWRDM_HAS_LOWPOWERSTATECHANGE, +}; + +/* + * The following power domains are not under SW control + * + * mpuaon + * mmaon + */ + +/* As powerdomains are added or removed above, this list must also be changed */ +static struct powerdomain *powerdomains_dra7xx[] __initdata = { + &iva_7xx_pwrdm, + &rtc_7xx_pwrdm, + &custefuse_7xx_pwrdm, + &ipu_7xx_pwrdm, + &dss_7xx_pwrdm, + &l4per_7xx_pwrdm, + &gpu_7xx_pwrdm, + &wkupaon_7xx_pwrdm, + &core_7xx_pwrdm, + &coreaon_7xx_pwrdm, + &cpu0_7xx_pwrdm, + &cpu1_7xx_pwrdm, + &vpe_7xx_pwrdm, + &mpu_7xx_pwrdm, + &l3init_7xx_pwrdm, + &eve3_7xx_pwrdm, + &emu_7xx_pwrdm, + &dsp2_7xx_pwrdm, + &dsp1_7xx_pwrdm, + &cam_7xx_pwrdm, + &eve4_7xx_pwrdm, + &eve2_7xx_pwrdm, + &eve1_7xx_pwrdm, + NULL +}; + +void __init dra7xx_powerdomains_init(void) +{ + pwrdm_register_platform_funcs(&omap4_pwrdm_operations); + pwrdm_register_pwrdms(powerdomains_dra7xx); + pwrdm_complete_init(); +} diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index ff1ac4a82a04..0e841fd9498a 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -58,6 +58,7 @@ #define TI816X_PRM_IVAHD1_MOD 0x0d00 #define TI816X_PRM_IVAHD2_MOD 0x0e00 #define TI816X_PRM_SGX_MOD 0x0f00 +#define TI81XX_PRM_ALWON_MOD 0x1800 /* 24XX register bits shared between CM & PRM registers */ diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h index f429cdd5a118..4fea2cfdf2c3 100644 --- a/arch/arm/mach-omap2/prcm44xx.h +++ b/arch/arm/mach-omap2/prcm44xx.h @@ -38,6 +38,11 @@ #define OMAP54XX_SCRM_PARTITION 4 #define OMAP54XX_PRCM_MPU_PARTITION 5 +#define DRA7XX_PRM_PARTITION 1 +#define DRA7XX_CM_CORE_AON_PARTITION 2 +#define DRA7XX_CM_CORE_PARTITION 3 +#define DRA7XX_MPU_PRCM_PARTITION 5 + /* * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition * IDs, plus one diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h new file mode 100644 index 000000000000..9ebb5ce0878f --- /dev/null +++ b/arch/arm/mach-omap2/prcm_mpu7xx.h @@ -0,0 +1,78 @@ +/* + * DRA7xx PRCM MPU instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Generated by code originally written by: + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H +#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H + +#include "prcm_mpu_44xx_54xx.h" + +#define DRA7XX_PRCM_MPU_BASE 0x48243000 + +#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg)) + +/* MPU_PRCM instances */ +#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000 +#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200 +#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400 +#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600 +#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800 +#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00 + +/* PRCM_MPU clockdomain register offsets (from instance start) */ +#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000 +#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000 + + +/* MPU_PRCM */ + +/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */ +#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000 + +/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */ +#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010 +#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014 + +/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */ +#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024 + +/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */ +#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020) + +/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */ +#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024 + +/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */ +#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020) + +#endif diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 91aa5106d637..37fc905c9636 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -16,274 +16,27 @@ #include "prm2xxx.h" -/* Bits shared between registers */ - -/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2) -#define OMAP24XX_WKUP2_ST_MASK (1 << 1) -#define OMAP24XX_WKUP1_ST_MASK (1 << 0) - -/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */ -#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2) -#define OMAP24XX_WKUP2_EN_MASK (1 << 1) -#define OMAP24XX_WKUP1_EN_MASK (1 << 0) - -/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */ -#define OMAP24XX_EN_MPU_SHIFT 1 -#define OMAP24XX_EN_MPU_MASK (1 << 1) #define OMAP24XX_EN_CORE_SHIFT 0 -#define OMAP24XX_EN_CORE_MASK (1 << 0) - -/* - * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM - * shared bits - */ -#define OMAP24XX_MEMONSTATE_SHIFT 10 -#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEMRETSTATE_MASK (1 << 3) - -/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */ #define OMAP24XX_FORCESTATE_MASK (1 << 18) - -/* - * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP, - * PM_PWSTST_MDM shared bits - */ -#define OMAP24XX_CLKACTIVITY_MASK (1 << 19) - -/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */ -#define OMAP24XX_LASTSTATEENTERED_SHIFT 4 -#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4) - -/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */ -#define OMAP2430_MEMSTATEST_SHIFT 10 -#define OMAP2430_MEMSTATEST_MASK (0x3 << 10) - -/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */ -#define OMAP24XX_POWERSTATEST_SHIFT 0 -#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0) - - -/* Bits specific to each register */ - -/* PRCM_REVISION */ -#define OMAP24XX_REV_SHIFT 0 -#define OMAP24XX_REV_MASK (0xff << 0) - -/* PRCM_SYSCONFIG */ #define OMAP24XX_AUTOIDLE_MASK (1 << 0) - -/* PRCM_IRQSTATUS_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6) -#define OMAP24XX_TRANSITION_ST_MASK (1 << 5) -#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4) -#define OMAP24XX_EVGENON_ST_MASK (1 << 3) - -/* PRCM_IRQENABLE_MPU specific bits */ -#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6) -#define OMAP24XX_TRANSITION_EN_MASK (1 << 5) -#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4) -#define OMAP24XX_EVGENON_EN_MASK (1 << 3) - -/* PRCM_VOLTCTRL */ #define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) -#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14) #define OMAP24XX_SETOFF_LEVEL_SHIFT 12 -#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12) #define OMAP24XX_MEMRETCTRL_MASK (1 << 8) #define OMAP24XX_SETRET_LEVEL_SHIFT 6 -#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6) #define OMAP24XX_VOLT_LEVEL_SHIFT 0 -#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0) - -/* PRCM_VOLTST */ -#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0 -#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0) - -/* PRCM_CLKSRC_CTRL specific bits */ - -/* PRCM_CLKOUT_CTRL */ #define OMAP2420_CLKOUT2_EN_SHIFT 15 -#define OMAP2420_CLKOUT2_EN_MASK (1 << 15) #define OMAP2420_CLKOUT2_DIV_SHIFT 11 -#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11) #define OMAP2420_CLKOUT2_DIV_WIDTH 3 -#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8 #define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) #define OMAP24XX_CLKOUT_EN_SHIFT 7 -#define OMAP24XX_CLKOUT_EN_MASK (1 << 7) #define OMAP24XX_CLKOUT_DIV_SHIFT 3 -#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3) #define OMAP24XX_CLKOUT_DIV_WIDTH 3 -#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0 #define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) - -/* PRCM_CLKEMUL_CTRL */ #define OMAP24XX_EMULATION_EN_SHIFT 0 -#define OMAP24XX_EMULATION_EN_MASK (1 << 0) - -/* PRCM_CLKCFG_CTRL */ -#define OMAP24XX_VALID_CONFIG_MASK (1 << 0) - -/* PRCM_CLKCFG_STATUS */ -#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0) - -/* PRCM_VOLTSETUP specific bits */ - -/* PRCM_CLKSSETUP specific bits */ - -/* PRCM_POLCTRL */ -#define OMAP2420_CLKOUT2_POL_MASK (1 << 10) -#define OMAP24XX_CLKOUT_POL_MASK (1 << 9) -#define OMAP24XX_CLKREQ_POL_MASK (1 << 8) -#define OMAP2430_USE_POWEROK_MASK (1 << 2) -#define OMAP2430_POWEROK_POL_MASK (1 << 1) -#define OMAP24XX_EXTVOL_POL_MASK (1 << 0) - -/* RM_RSTST_MPU specific bits */ -/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */ - -/* PM_WKDEP_MPU specific bits */ #define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 -#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5) #define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 -#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2) - -/* PM_EVGENCTRL_MPU specific bits */ - -/* PM_EVEGENONTIM_MPU specific bits */ - -/* PM_EVEGENOFFTIM_MPU specific bits */ - -/* PM_PWSTCTRL_MPU specific bits */ -#define OMAP2430_FORCESTATE_MASK (1 << 18) - -/* PM_PWSTST_MPU specific bits */ -/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */ - -/* PM_WKEN1_CORE specific bits */ - -/* PM_WKEN2_CORE specific bits */ - -/* PM_WKST1_CORE specific bits*/ - -/* PM_WKST2_CORE specific bits */ - -/* PM_WKDEP_CORE specific bits*/ -#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5) -#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3) -#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2) - -/* PM_PWSTCTRL_CORE specific bits */ -#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20) -#define OMAP24XX_MEM3ONSTATE_SHIFT 14 -#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14) -#define OMAP24XX_MEM2ONSTATE_SHIFT 12 -#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12) -#define OMAP24XX_MEM1ONSTATE_SHIFT 10 -#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10) -#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5) -#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4) -#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3) - -/* PM_PWSTST_CORE specific bits */ -#define OMAP24XX_MEM3STATEST_SHIFT 14 -#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14) -#define OMAP24XX_MEM2STATEST_SHIFT 12 -#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12) -#define OMAP24XX_MEM1STATEST_SHIFT 10 -#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10) - -/* RM_RSTCTRL_GFX */ -#define OMAP24XX_GFX_RST_MASK (1 << 0) - -/* RM_RSTST_GFX specific bits */ -#define OMAP24XX_GFX_SW_RST_MASK (1 << 4) - -/* PM_PWSTCTRL_GFX specific bits */ - -/* PM_WKDEP_GFX specific bits */ -/* 2430 often calls EN_WAKEUP "EN_WKUP" */ - -/* RM_RSTCTRL_WKUP specific bits */ - -/* RM_RSTTIME_WKUP specific bits */ - -/* RM_RSTST_WKUP specific bits */ -/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */ #define OMAP24XX_EXTWMPU_RST_SHIFT 6 -#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6) #define OMAP24XX_SECU_WD_RST_SHIFT 5 -#define OMAP24XX_SECU_WD_RST_MASK (1 << 5) #define OMAP24XX_MPU_WD_RST_SHIFT 4 -#define OMAP24XX_MPU_WD_RST_MASK (1 << 4) #define OMAP24XX_SECU_VIOL_RST_SHIFT 3 -#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3) - -/* PM_WKEN_WKUP specific bits */ - -/* PM_WKST_WKUP specific bits */ - -/* RM_RSTCTRL_DSP */ -#define OMAP2420_RST_IVA_MASK (1 << 8) -#define OMAP24XX_RST2_DSP_MASK (1 << 1) -#define OMAP24XX_RST1_DSP_MASK (1 << 0) - -/* RM_RSTST_DSP specific bits */ -/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */ -#define OMAP2420_IVA_SW_RST_MASK (1 << 8) -#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5) -#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4) - -/* PM_WKDEP_DSP specific bits */ - -/* PM_PWSTCTRL_DSP specific bits */ -/* 2430 only: MEMONSTATE, MEMRETSTATE */ -#define OMAP2420_MEMIONSTATE_SHIFT 12 -#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12) -#define OMAP2420_MEMIRETSTATE_MASK (1 << 4) - -/* PM_PWSTST_DSP specific bits */ -/* MEMSTATEST is 2430 only */ -#define OMAP2420_MEMISTATEST_SHIFT 12 -#define OMAP2420_MEMISTATEST_MASK (0x3 << 12) - -/* PRCM_IRQSTATUS_DSP specific bits */ - -/* PRCM_IRQENABLE_DSP specific bits */ - -/* RM_RSTCTRL_MDM */ -/* 2430 only */ -#define OMAP2430_PWRON1_MDM_MASK (1 << 1) -#define OMAP2430_RST1_MDM_MASK (1 << 0) - -/* RM_RSTST_MDM specific bits */ -/* 2430 only */ -#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6) -#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5) -#define OMAP2430_MDM_SW_RST1_MASK (1 << 4) - -/* PM_WKEN_MDM */ -/* 2430 only */ -#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0) - -/* PM_WKST_MDM specific bits */ -/* 2430 only */ - -/* PM_WKDEP_MDM specific bits */ -/* 2430 only */ - -/* PM_PWSTCTRL_MDM specific bits */ -/* 2430 only */ -#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19) - -/* PM_PWSTST_MDM specific bits */ -/* 2430 only */ - -/* PRCM_IRQSTATUS_IVA */ -/* 2420 only */ - -/* PRCM_IRQENABLE_IVA */ -/* 2420 only */ - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h index 0221b5c20e87..84feecee4fe6 100644 --- a/arch/arm/mach-omap2/prm-regbits-33xx.h +++ b/arch/arm/mach-omap2/prm-regbits-33xx.h @@ -18,340 +18,35 @@ #include "prm.h" -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1 -#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_AIPOFF_SHIFT 8 -#define AM33XX_AIPOFF_MASK (1 << 8) - -/* Used by PM_WKUP_PWRSTST */ -#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17 -#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0 -#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12 -#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14 -#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15 -#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13 -#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11 -#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13 -#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15 -#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_EMULATION_M3_RST_SHIFT 6 -#define AM33XX_EMULATION_M3_RST_MASK (1 << 6) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_EMULATION_MPU_RST_SHIFT 5 -#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC1_EXPORT_SHIFT 3 -#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC3_EXPORT_SHIFT 5 -#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC4_SHIFT 6 -#define AM33XX_ENFUNC4_MASK (1 << 6) - -/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */ -#define AM33XX_ENFUNC5_SHIFT 7 -#define AM33XX_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_RSTST */ -#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5 -#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_FORCEWKUP_EN_SHIFT 10 -#define AM33XX_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_FORCEWKUP_ST_SHIFT 10 -#define AM33XX_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17 #define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) - -/* Used by PM_GFX_PWRSTCTRL */ -#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6 #define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) - -/* Used by PM_GFX_PWRSTST */ -#define AM33XX_GFX_MEM_STATEST_SHIFT 4 #define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) - -/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */ -#define AM33XX_GFX_RST_SHIFT 0 -#define AM33XX_GFX_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_COLD_RST_SHIFT 0 -#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1 #define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by RM_WKUP_RSTST */ -#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7 -#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7) - -/* Used by RM_MPU_RSTST */ -#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6 -#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6) - -/* Used by PRM_RSTST */ -#define AM33XX_ICEPICK_RST_SHIFT 9 -#define AM33XX_ICEPICK_RST_MASK (1 << 9) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PRUSS_LRST_SHIFT 1 -#define AM33XX_PRUSS_LRST_MASK (1 << 1) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5 +#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) #define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7 #define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23 #define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ -#define AM33XX_INTRANSITION_SHIFT 20 -#define AM33XX_INTRANSITION_MASK (1 << 20) - -/* Used by PM_CEFUSE_PWRSTST */ #define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 #define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_SHIFT 2 #define AM33XX_LOGICRETSTATE_MASK (1 << 2) - -/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */ -#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3 #define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) - -/* - * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST, - * PM_WKUP_PWRSTST, PM_RTC_PWRSTST - */ #define AM33XX_LOGICSTATEST_SHIFT 2 #define AM33XX_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL - */ #define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 #define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_ONSTATE_SHIFT 18 #define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L1_RETSTATE_SHIFT 22 #define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L1_STATEST_SHIFT 6 #define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_ONSTATE_SHIFT 20 #define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_L2_RETSTATE_SHIFT 23 #define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_L2_STATEST_SHIFT 8 #define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16 #define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_MPU_PWRSTCTRL */ -#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24 #define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) - -/* Used by PM_MPU_PWRSTST */ -#define AM33XX_MPU_RAM_STATEST_SHIFT 4 #define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ -#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_PCHARGECNT_VALUE_SHIFT 0 -#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by RM_PER_RSTCTRL */ -#define AM33XX_PCI_LRST_SHIFT 0 -#define AM33XX_PCI_LRST_MASK (1 << 0) - -/* Renamed from PCI_LRST Used by RM_PER_RSTST */ -#define AM33XX_PCI_LRST_5_5_SHIFT 5 -#define AM33XX_PCI_LRST_5_5_MASK (1 << 5) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_ONSTATE_SHIFT 25 #define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_PER_MEM_RETSTATE_SHIFT 29 #define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_PER_MEM_STATEST_SHIFT 17 #define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) - -/* - * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL - */ -#define AM33XX_POWERSTATE_SHIFT 0 -#define AM33XX_POWERSTATE_MASK (0x3 << 0) - -/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */ -#define AM33XX_POWERSTATEST_SHIFT 0 -#define AM33XX_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30 #define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) - -/* Used by PM_PER_PWRSTCTRL */ -#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27 #define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) - -/* Used by PM_PER_PWRSTST */ -#define AM33XX_RAM_MEM_STATEST_SHIFT 21 #define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_RETMODE_ENABLE_SHIFT 0 -#define AM33XX_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define AM33XX_REV_SHIFT 0 -#define AM33XX_REV_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME1_SHIFT 0 -#define AM33XX_RSTTIME1_MASK (0xff << 0) - -/* Used by PRM_RSTTIME */ -#define AM33XX_RSTTIME2_SHIFT 8 -#define AM33XX_RSTTIME2_MASK (0x1f << 8) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1 -#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0 -#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_SLPCNT_VALUE_SHIFT 16 -#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAMLDO_STATUS_SHIFT 8 -#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8) - -/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */ -#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9 -#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_STARTUP_COUNT_SHIFT 24 -#define AM33XX_STARTUP_COUNT_MASK (0xff << 24) - -/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */ -#define AM33XX_TRANSITION_EN_SHIFT 8 -#define AM33XX_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */ -#define AM33XX_TRANSITION_ST_SHIFT 8 -#define AM33XX_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_SRAM_COUNT */ -#define AM33XX_VSETUPCNT_VALUE_SHIFT 8 -#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT0_RST_SHIFT 3 -#define AM33XX_WDT0_RST_MASK (1 << 3) - -/* Used by PRM_RSTST */ -#define AM33XX_WDT1_RST_SHIFT 4 -#define AM33XX_WDT1_RST_MASK (1 << 4) - -/* Used by RM_WKUP_RSTCTRL */ -#define AM33XX_WKUP_M3_LRST_SHIFT 3 -#define AM33XX_WKUP_M3_LRST_MASK (1 << 3) - -/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */ -#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5 -#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5) - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index b0a2142eeb91..cebad565ed37 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -16,115 +16,25 @@ #include "prm3xxx.h" -/* Shared register bits */ - -/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */ -#define OMAP3430_ON_SHIFT 24 -#define OMAP3430_ON_MASK (0xff << 24) -#define OMAP3430_ONLP_SHIFT 16 -#define OMAP3430_ONLP_MASK (0xff << 16) -#define OMAP3430_RET_SHIFT 8 -#define OMAP3430_RET_MASK (0xff << 8) -#define OMAP3430_OFF_SHIFT 0 -#define OMAP3430_OFF_MASK (0xff << 0) - -/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */ -#define OMAP3430_ERROROFFSET_SHIFT 24 #define OMAP3430_ERROROFFSET_MASK (0xff << 24) -#define OMAP3430_ERRORGAIN_SHIFT 16 #define OMAP3430_ERRORGAIN_MASK (0xff << 16) -#define OMAP3430_INITVOLTAGE_SHIFT 8 #define OMAP3430_INITVOLTAGE_MASK (0xff << 8) #define OMAP3430_TIMEOUTEN_MASK (1 << 3) #define OMAP3430_INITVDD_MASK (1 << 2) #define OMAP3430_FORCEUPDATE_MASK (1 << 1) #define OMAP3430_VPENABLE_MASK (1 << 0) - -/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */ #define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8) #define OMAP3430_VSTEPMIN_SHIFT 0 -#define OMAP3430_VSTEPMIN_MASK (0xff << 0) - -/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */ #define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8) #define OMAP3430_VSTEPMAX_SHIFT 0 -#define OMAP3430_VSTEPMAX_MASK (0xff << 0) - -/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */ #define OMAP3430_VDDMAX_SHIFT 24 -#define OMAP3430_VDDMAX_MASK (0xff << 24) #define OMAP3430_VDDMIN_SHIFT 16 -#define OMAP3430_VDDMIN_MASK (0xff << 16) #define OMAP3430_TIMEOUT_SHIFT 0 -#define OMAP3430_TIMEOUT_MASK (0xffff << 0) - -/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */ -#define OMAP3430_VPVOLTAGE_SHIFT 0 #define OMAP3430_VPVOLTAGE_MASK (0xff << 0) - -/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */ -#define OMAP3430_VPINIDLE_MASK (1 << 0) - -/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */ #define OMAP3430_EN_PER_SHIFT 7 -#define OMAP3430_EN_PER_MASK (1 << 7) - -/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */ -#define OMAP3430_MEMORYCHANGE_MASK (1 << 3) - -/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */ #define OMAP3430_LOGICSTATEST_MASK (1 << 2) - -/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */ #define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) - -/* - * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE, - * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM, - * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits - */ -#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0 #define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) - -/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */ -#define OMAP3430_WKUP_ST_MASK (1 << 0) - -/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */ -#define OMAP3430_WKUP_EN_MASK (1 << 0) - -/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */ -#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25) -#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24) -#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21) -#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20) -#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19) -#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18) -#define OMAP3430_GRPSEL_I2C3_SHIFT 17 -#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17) -#define OMAP3430_GRPSEL_I2C2_SHIFT 16 -#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16) -#define OMAP3430_GRPSEL_I2C1_SHIFT 15 -#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15) -#define OMAP3430_GRPSEL_UART2_MASK (1 << 14) -#define OMAP3430_GRPSEL_UART1_MASK (1 << 13) -#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12) -#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11) -#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10) -#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9) -#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4) -#define OMAP3430_GRPSEL_D2D_MASK (1 << 3) - -/* - * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, - * PM_PWSTCTRL_PER shared bits - */ -#define OMAP3430_MEMONSTATE_SHIFT 16 -#define OMAP3430_MEMONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEMRETSTATE_MASK (1 << 8) - -/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */ #define OMAP3630_GRPSEL_UART4_MASK (1 << 18) #define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) #define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) @@ -132,480 +42,89 @@ #define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) #define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) #define OMAP3430_GRPSEL_UART3_MASK (1 << 11) -#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10) -#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9) -#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8) -#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7) -#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6) -#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5) -#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4) -#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3) #define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) #define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) #define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) - -/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */ -#define OMAP3430_GRPSEL_IO_MASK (1 << 8) -#define OMAP3430_GRPSEL_SR2_MASK (1 << 7) -#define OMAP3430_GRPSEL_SR1_MASK (1 << 6) #define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) #define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) #define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) - -/* Bits specific to each register */ - -/* RM_RSTCTRL_IVA2 */ #define OMAP3430_RST3_IVA2_MASK (1 << 2) #define OMAP3430_RST2_IVA2_MASK (1 << 1) #define OMAP3430_RST1_IVA2_MASK (1 << 0) - -/* RM_RSTST_IVA2 specific bits */ -#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13) -#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12) -#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11) -#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10) -#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9) -#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8) - -/* PM_WKDEP_IVA2 specific bits */ - -/* PM_PWSTCTRL_IVA2 specific bits */ -#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22 #define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) -#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20 #define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) -#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18 #define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) -#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16 #define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) #define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) #define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) #define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) #define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) - -/* PM_PWSTST_IVA2 specific bits */ -#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10 #define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) -#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8 #define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) -#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6 #define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) -#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4 #define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) - -/* PM_PREPWSTST_IVA2 specific bits */ -#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10 #define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) -#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8 #define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) -#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6 -#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4 -#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4) - -/* PRM_IRQSTATUS_IVA2 specific bits */ -#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2) -#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1) - -/* PRM_IRQENABLE_IVA2 specific bits */ -#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2) -#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1) - -/* PRM_REVISION specific bits */ - -/* PRM_SYSCONFIG specific bits */ - -/* PRM_IRQSTATUS_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24) -#define OMAP3430_VC_RAERR_ST_MASK (1 << 23) -#define OMAP3430_VC_SAERR_ST_MASK (1 << 22) #define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) -#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19) -#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18) -#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16) #define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) -#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13) -#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12) -#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10) -#define OMAP3430_IO_ST_MASK (1 << 9) -#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8) #define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 -#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7) #define OMAP3430_MPU_DPLL_ST_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 -#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5) #define OMAP3430_CORE_DPLL_ST_SHIFT 5 -#define OMAP3430_TRANSITION_ST_MASK (1 << 4) -#define OMAP3430_EVGENOFF_ST_MASK (1 << 3) -#define OMAP3430_EVGENON_ST_MASK (1 << 2) -#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1) - -/* PRM_IRQENABLE_MPU specific bits */ #define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 -#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25) -#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24) -#define OMAP3430_VC_RAERR_EN_MASK (1 << 23) -#define OMAP3430_VC_SAERR_EN_MASK (1 << 22) -#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21) -#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20) -#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19) -#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18) -#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17) -#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16) -#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15) -#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14) -#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13) -#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12) -#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11) -#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10) -#define OMAP3430_IO_EN_MASK (1 << 9) -#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8) #define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 -#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7) #define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 -#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6) #define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 -#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5) #define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 -#define OMAP3430_TRANSITION_EN_MASK (1 << 4) -#define OMAP3430_EVGENOFF_EN_MASK (1 << 3) -#define OMAP3430_EVGENON_EN_MASK (1 << 2) -#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1) - -/* RM_RSTST_MPU specific bits */ -#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11) - -/* PM_WKDEP_MPU specific bits */ #define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 -#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5) #define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 -#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2) - -/* PM_EVGENCTRL_MPU */ -#define OMAP3430_OFFLOADMODE_SHIFT 3 -#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3) -#define OMAP3430_ONLOADMODE_SHIFT 1 -#define OMAP3430_ONLOADMODE_MASK (0x3 << 1) -#define OMAP3430_ENABLE_MASK (1 << 0) - -/* PM_EVGENONTIM_MPU */ -#define OMAP3430_ONTIMEVAL_SHIFT 0 -#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0) - -/* PM_EVGENOFFTIM_MPU */ -#define OMAP3430_OFFTIMEVAL_SHIFT 0 -#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0) - -/* PM_PWSTCTRL_MPU specific bits */ -#define OMAP3430_L2CACHEONSTATE_SHIFT 16 -#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16) -#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8) -#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2) - -/* PM_PWSTST_MPU specific bits */ -#define OMAP3430_L2CACHESTATEST_SHIFT 6 -#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6) -#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2) - -/* PM_PREPWSTST_MPU specific bits */ -#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6 -#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2) - -/* RM_RSTCTRL_CORE */ #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) #define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) - -/* RM_RSTST_CORE specific bits */ -#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9) -#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8) - -/* PM_WKEN1_CORE specific bits */ - -/* PM_MPUGRPSEL1_CORE specific bits */ -#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5) - -/* PM_IVA2GRPSEL1_CORE specific bits */ - -/* PM_WKST1_CORE specific bits */ - -/* PM_PWSTCTRL_CORE specific bits */ -#define OMAP3430_MEM2ONSTATE_SHIFT 18 -#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18) -#define OMAP3430_MEM1ONSTATE_SHIFT 16 -#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16) -#define OMAP3430_MEM2RETSTATE_MASK (1 << 9) -#define OMAP3430_MEM1RETSTATE_MASK (1 << 8) - -/* PM_PWSTST_CORE specific bits */ -#define OMAP3430_MEM2STATEST_SHIFT 6 -#define OMAP3430_MEM2STATEST_MASK (0x3 << 6) -#define OMAP3430_MEM1STATEST_SHIFT 4 -#define OMAP3430_MEM1STATEST_MASK (0x3 << 4) - -/* PM_PREPWSTST_CORE specific bits */ -#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6 #define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) -#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4 #define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) - -/* RM_RSTST_GFX specific bits */ - -/* PM_WKDEP_GFX specific bits */ -#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_GFX specific bits */ - -/* PM_PWSTST_GFX specific bits */ - -/* PM_PREPWSTST_GFX specific bits */ - -/* PM_WKEN_WKUP specific bits */ #define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) #define OMAP3430_EN_IO_MASK (1 << 8) #define OMAP3430_EN_GPIO1_MASK (1 << 3) - -/* PM_MPUGRPSEL_WKUP specific bits */ - -/* PM_IVA2GRPSEL_WKUP specific bits */ - -/* PM_WKST_WKUP specific bits */ #define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) #define OMAP3430_ST_IO_MASK (1 << 8) - -/* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 -#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) #define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 - -/* PRM_CLKOUT_CTRL */ -#define OMAP3430_CLKOUT_EN_MASK (1 << 7) #define OMAP3430_CLKOUT_EN_SHIFT 7 - -/* RM_RSTST_DSS specific bits */ - -/* PM_WKEN_DSS */ #define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) - -/* PM_WKDEP_DSS specific bits */ -#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_DSS specific bits */ - -/* PM_PWSTST_DSS specific bits */ - -/* PM_PREPWSTST_DSS specific bits */ - -/* RM_RSTST_CAM specific bits */ - -/* PM_WKDEP_CAM specific bits */ -#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_CAM specific bits */ - -/* PM_PWSTST_CAM specific bits */ - -/* PM_PREPWSTST_CAM specific bits */ - -/* PM_PWSTCTRL_USBHOST specific bits */ #define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 - -/* RM_RSTST_PER specific bits */ - -/* PM_WKEN_PER specific bits */ - -/* PM_MPUGRPSEL_PER specific bits */ - -/* PM_IVA2GRPSEL_PER specific bits */ - -/* PM_WKST_PER specific bits */ - -/* PM_WKDEP_PER specific bits */ -#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2) - -/* PM_PWSTCTRL_PER specific bits */ - -/* PM_PWSTST_PER specific bits */ - -/* PM_PREPWSTST_PER specific bits */ - -/* RM_RSTST_EMU specific bits */ - -/* PM_PWSTST_EMU specific bits */ - -/* PRM_VC_SMPS_SA */ #define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 #define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) #define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 #define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) - -/* PRM_VC_SMPS_VOL_RA */ -#define OMAP3430_VOLRA1_SHIFT 16 #define OMAP3430_VOLRA1_MASK (0xff << 16) -#define OMAP3430_VOLRA0_SHIFT 0 #define OMAP3430_VOLRA0_MASK (0xff << 0) - -/* PRM_VC_SMPS_CMD_RA */ -#define OMAP3430_CMDRA1_SHIFT 16 #define OMAP3430_CMDRA1_MASK (0xff << 16) -#define OMAP3430_CMDRA0_SHIFT 0 #define OMAP3430_CMDRA0_MASK (0xff << 0) - -/* PRM_VC_CMD_VAL_0 specific bits */ #define OMAP3430_VC_CMD_ON_SHIFT 24 #define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) #define OMAP3430_VC_CMD_ONLP_SHIFT 16 -#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16) #define OMAP3430_VC_CMD_RET_SHIFT 8 -#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8) #define OMAP3430_VC_CMD_OFF_SHIFT 0 -#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0) - -/* PRM_VC_CMD_VAL_1 specific bits */ - -/* PRM_VC_CH_CONF */ -#define OMAP3430_CMD1_MASK (1 << 20) -#define OMAP3430_RACEN1_MASK (1 << 19) -#define OMAP3430_RAC1_MASK (1 << 18) -#define OMAP3430_RAV1_MASK (1 << 17) -#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16) -#define OMAP3430_CMD0_MASK (1 << 4) -#define OMAP3430_RACEN0_MASK (1 << 3) -#define OMAP3430_RAC0_MASK (1 << 2) -#define OMAP3430_RAV0_MASK (1 << 1) -#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0) - -/* PRM_VC_I2C_CFG */ -#define OMAP3430_HSMASTER_MASK (1 << 5) -#define OMAP3430_SREN_MASK (1 << 4) #define OMAP3430_HSEN_MASK (1 << 3) -#define OMAP3430_MCODE_SHIFT 0 #define OMAP3430_MCODE_MASK (0x7 << 0) - -/* PRM_VC_BYPASS_VAL */ #define OMAP3430_VALID_MASK (1 << 24) #define OMAP3430_DATA_SHIFT 16 -#define OMAP3430_DATA_MASK (0xff << 16) #define OMAP3430_REGADDR_SHIFT 8 -#define OMAP3430_REGADDR_MASK (0xff << 8) #define OMAP3430_SLAVEADDR_SHIFT 0 -#define OMAP3430_SLAVEADDR_MASK (0x7f << 0) - -/* PRM_RSTCTRL */ -#define OMAP3430_RST_DPLL3_MASK (1 << 2) -#define OMAP3430_RST_GS_MASK (1 << 1) - -/* PRM_RSTTIME */ -#define OMAP3430_RSTTIME2_SHIFT 8 -#define OMAP3430_RSTTIME2_MASK (0x1f << 8) -#define OMAP3430_RSTTIME1_SHIFT 0 -#define OMAP3430_RSTTIME1_MASK (0xff << 0) - -/* PRM_RSTST */ #define OMAP3430_ICECRUSHER_RST_SHIFT 10 -#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) #define OMAP3430_ICEPICK_RST_SHIFT 9 -#define OMAP3430_ICEPICK_RST_MASK (1 << 9) #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 -#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 -#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) #define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 -#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) #define OMAP3430_SECURE_WD_RST_SHIFT 5 -#define OMAP3430_SECURE_WD_RST_MASK (1 << 5) #define OMAP3430_MPU_WD_RST_SHIFT 4 -#define OMAP3430_MPU_WD_RST_MASK (1 << 4) #define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 -#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) #define OMAP3430_GLOBAL_SW_RST_SHIFT 1 -#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) #define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) - -/* PRM_VOLTCTRL */ -#define OMAP3430_SEL_VMODE_MASK (1 << 4) #define OMAP3430_SEL_OFF_MASK (1 << 3) #define OMAP3430_AUTO_OFF_MASK (1 << 2) -#define OMAP3430_AUTO_RET_MASK (1 << 1) -#define OMAP3430_AUTO_SLEEP_MASK (1 << 0) - -/* PRM_SRAM_PCHARGE */ -#define OMAP3430_PCHARGE_TIME_SHIFT 0 -#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0) - -/* PRM_CLKSRC_CTRL */ -#define OMAP3430_SYSCLKDIV_SHIFT 6 -#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6) -#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3 -#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3) -#define OMAP3430_SYSCLKSEL_SHIFT 0 -#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0) - -/* PRM_VOLTSETUP1 */ -#define OMAP3430_SETUP_TIME2_SHIFT 16 #define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) -#define OMAP3430_SETUP_TIME1_SHIFT 0 #define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) - -/* PRM_VOLTOFFSET */ -#define OMAP3430_OFFSET_TIME_SHIFT 0 -#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0) - -/* PRM_CLKSETUP */ -#define OMAP3430_SETUP_TIME_SHIFT 0 -#define OMAP3430_SETUP_TIME_MASK (0xffff << 0) - -/* PRM_POLCTRL */ -#define OMAP3430_OFFMODE_POL_MASK (1 << 3) -#define OMAP3430_CLKOUT_POL_MASK (1 << 2) -#define OMAP3430_CLKREQ_POL_MASK (1 << 1) -#define OMAP3430_EXTVOL_POL_MASK (1 << 0) - -/* PRM_VOLTSETUP2 */ -#define OMAP3430_OFFMODESETUPTIME_SHIFT 0 -#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0) - -/* PRM_VP1_CONFIG specific bits */ - -/* PRM_VP1_VSTEPMIN specific bits */ - -/* PRM_VP1_VSTEPMAX specific bits */ - -/* PRM_VP1_VLIMITTO specific bits */ - -/* PRM_VP1_VOLTAGE specific bits */ - -/* PRM_VP1_STATUS specific bits */ - -/* PRM_VP2_CONFIG specific bits */ - -/* PRM_VP2_VSTEPMIN specific bits */ - -/* PRM_VP2_VSTEPMAX specific bits */ - -/* PRM_VP2_VLIMITTO specific bits */ - -/* PRM_VP2_VOLTAGE specific bits */ - -/* PRM_VP2_STATUS specific bits */ - -/* RM_RSTST_NEON specific bits */ - -/* PM_WKDEP_NEON specific bits */ - -/* PM_PWSTCTRL_NEON specific bits */ - -/* PM_PWSTST_NEON specific bits */ - -/* PM_PREPWSTST_NEON specific bits */ - #endif diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 3cb247bebdaa..b1c7a33e00e7 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -22,2306 +22,80 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1 -#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2 -#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31 -#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1 -#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_AESSMEM_STATEST_SHIFT 4 -#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_AIPOFF_SHIFT 8 -#define OMAP4430_AIPOFF_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4 -#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_RA_ERR_SHIFT 25 -#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_SA_ERR_SHIFT 24 -#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26 -#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26) - -/* Used by PRM_RSTST */ #define OMAP4430_C2C_RST_SHIFT 10 -#define OMAP4430_C2C_RST_MASK (1 << 10) - -/* Used by PM_CAM_PWRSTCTRL */ -#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CAM_PWRSTST */ -#define OMAP4430_CAM_MEM_STATEST_SHIFT 4 -#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_CLKREQCTRL */ -#define OMAP4430_CLKREQ_COND_SHIFT 0 -#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) - -/* Used by PRM_VC_VAL_SMPS_RA_CMD */ -#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4 -#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12 -#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17 -#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP4430_CUSTOM_SHIFT 6 -#define OMAP4430_CUSTOM_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_DATA_SHIFT 16 -#define OMAP4430_DATA_MASK (0xff << 16) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_DFILTEREN_SHIFT 6 -#define OMAP4430_DFILTEREN_MASK (1 << 6) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP - */ -#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0 -#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6 -#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7 -#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSS_PWRSTST */ -#define OMAP4430_DSS_MEM_STATEST_SHIFT 4 -#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20 -#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10 -#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8 -#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10 -#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8 -#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9 -#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_EMULATION_RST_SHIFT 0 -#define OMAP4430_EMULATION_RST_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_EMULATION_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3 -#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4 -#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4) - -/* Used by PM_EMU_PWRSTCTRL */ -#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_EMU_PWRSTST */ -#define OMAP4430_EMU_BANK_STATEST_SHIFT 4 -#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3 -#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5 -#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC4_SHIFT 6 -#define OMAP4430_ENFUNC4_MASK (1 << 6) - -/* - * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, - * PRM_LDO_SRAM_MPU_SETUP - */ -#define OMAP4430_ENFUNC5_SHIFT 7 -#define OMAP4430_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERRORGAIN_SHIFT 16 #define OMAP4430_ERRORGAIN_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_ERROROFFSET_SHIFT 24 #define OMAP4430_ERROROFFSET_MASK (0xff << 24) - -/* Used by PRM_RSTST */ #define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_FORCEUPDATE_SHIFT 1 #define OMAP4430_FORCEUPDATE_MASK (1 << 1) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */ -#define OMAP4430_FORCEWKUP_EN_SHIFT 10 -#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */ -#define OMAP4430_FORCEWKUP_ST_SHIFT 10 -#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP4430_FUNC_SHIFT 16 -#define OMAP4430_FUNC_MASK (0xfff << 16) - -/* Used by PM_GFX_PWRSTCTRL */ -#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_GFX_PWRSTST */ -#define OMAP4430_GFX_MEM_STATEST_SHIFT 4 -#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ #define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_GLOBAL_WUEN_SHIFT 16 #define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMCODE_SHIFT 0 #define OMAP4430_HSMCODE_MASK (0x7 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_HSMODEEN_SHIFT 3 #define OMAP4430_HSMODEEN_MASK (1 << 3) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP4430_HSSCLH_SHIFT 16 -#define OMAP4430_HSSCLH_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_HSSCLL_SHIFT 24 -#define OMAP4430_HSSCLL_MASK (0xff << 24) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_HWA_MEM_STATEST_SHIFT 4 -#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4) - -/* Used by RM_MPU_RSTST */ -#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1 -#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5) - -/* Used by RM_DUCATI_RSTST */ -#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5 -#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5) - -/* Used by RM_IVAHD_RSTST */ -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6 -#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6) - -/* Used by PRM_RSTST */ #define OMAP4430_ICEPICK_RST_SHIFT 9 -#define OMAP4430_ICEPICK_RST_MASK (1 << 9) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVDD_SHIFT 2 #define OMAP4430_INITVDD_MASK (1 << 2) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_INITVOLTAGE_SHIFT 8 #define OMAP4430_INITVOLTAGE_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_INTRANSITION_SHIFT 20 -#define OMAP4430_INTRANSITION_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_IO_EN_SHIFT 9 -#define OMAP4430_IO_EN_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_IO_ON_STATUS_SHIFT 5 -#define OMAP4430_IO_ON_STATUS_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_IO_ST_SHIFT 9 -#define OMAP4430_IO_ST_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOCLK_STATUS_SHIFT 1 -#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_ISOOVR_EXTEND_SHIFT 4 -#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4) - -/* Used by PRM_IO_COUNT */ -#define OMAP4430_ISO_2_ON_TIME_SHIFT 0 -#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* - * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ #define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 #define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ #define OMAP4430_LOGICRETSTATE_SHIFT 2 #define OMAP4430_LOGICRETSTATE_MASK (1 << 2) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ #define OMAP4430_LOGICSTATEST_SHIFT 2 #define OMAP4430_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT, - * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT, - * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT, - * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT, - * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT, - * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT, - * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT, - * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT, - * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT, - * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT, - * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT, - * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT, - * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT, - * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT, - * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, - * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT, - * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT, - * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT, - * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT, - * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0 #define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT, - * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT, - * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT, - * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT, - * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT, - * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, - * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT, - * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT, - * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT, - * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT - */ -#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1) - -/* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8 #define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) - -/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8) - -/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8) - -/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9 -#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9) - -/* Used by RM_L3_2_OCMC_RAM_CONTEXT */ -#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) - -/* - * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT, - * RM_SDMA_SDMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) - -/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9 -#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9) - -/* Used by RM_DUCATI_DUCATI_CONTEXT */ -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8 -#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8) - -/* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8) - -/* Used by RM_GFX_GFX_CONTEXT */ -#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10) - -/* - * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT, - * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT, - * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT - */ -#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10) - -/* - * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, - * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, - * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT - */ -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) - -/* - * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, - * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT - */ -#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8) - -/* - * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT, - * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, - * RM_L4SEC_CRYPTODMA_CONTEXT - */ -#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8) - -/* Used by RM_IVAHD_SL2_CONTEXT */ -#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8) - -/* Used by RM_IVAHD_IVAHD_CONTEXT */ -#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10 -#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8 -#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8) - -/* Used by RM_TESLA_TESLA_CONTEXT */ -#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9 -#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9) - -/* Used by RM_WKUP_SARRAM_CONTEXT */ -#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL, - * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ #define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 #define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_READY_SHIFT 1 -#define OMAP4430_MODEM_READY_MASK (1 << 1) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16 -#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16 -#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8 -#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L1_STATEST_SHIFT 4 -#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_L2_STATEST_SHIFT 6 -#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP4430_MPU_RAM_STATEST_SHIFT 8 -#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_RSTST */ #define OMAP4430_MPU_WDT_RST_SHIFT 3 -#define OMAP4430_MPU_WDT_RST_MASK (1 << 3) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18 -#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9 -#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6 -#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24 #define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12 #define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_OFF_SHIFT 0 -#define OMAP4430_OFF_MASK (0xff << 0) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_ON_SHIFT 24 #define OMAP4430_ON_MASK (0xff << 24) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_ONLP_SHIFT 16 -#define OMAP4430_ONLP_MASK (0xff << 16) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_CHANGE_SHIFT 2 -#define OMAP4430_OPP_CHANGE_MASK (1 << 2) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_OPP_SEL_SHIFT 0 -#define OMAP4430_OPP_SEL_MASK (0x3 << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PCHARGE_TIME_SHIFT 0 -#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_PHASE1_CNDP */ -#define OMAP4430_PHASE1_CNDP_SHIFT 0 -#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2A_CNDP */ -#define OMAP4430_PHASE2A_CNDP_SHIFT 0 -#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2B_CNDP */ -#define OMAP4430_PHASE2B_CNDP_SHIFT 0 -#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, - * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL, - * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, - * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL - */ -#define OMAP4430_POWERSTATE_SHIFT 0 -#define OMAP4430_POWERSTATE_MASK (0x3 << 0) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST, - * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST, - * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST - */ -#define OMAP4430_POWERSTATEST_SHIFT 0 -#define OMAP4430_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PRM_PWRREQCTRL */ -#define OMAP4430_PWRREQ_COND_SHIFT 0 -#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3 -#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11 -#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20 -#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2 -#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10 -#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19 -#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_UP_COUNT_SHIFT 0 -#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ #define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1 -#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9 -#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9) - -/* Used by PRM_VC_CFG_CHANNEL */ -#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18 -#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_REGADDR_SHIFT 8 -#define OMAP4430_REGADDR_MASK (0xff << 8) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ #define OMAP4430_RET_SHIFT 8 -#define OMAP4430_RET_MASK (0xff << 8) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16 -#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L4PER_PWRSTCTRL */ -#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8 -#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_L4PER_PWRSTST */ -#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4 -#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_RETMODE_ENABLE_SHIFT 0 -#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ -#define OMAP4430_RST1_SHIFT 0 -#define OMAP4430_RST1_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ -#define OMAP4430_RST1ST_SHIFT 0 -#define OMAP4430_RST1ST_MASK (1 << 0) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */ -#define OMAP4430_RST2_SHIFT 1 -#define OMAP4430_RST2_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */ -#define OMAP4430_RST2ST_SHIFT 1 -#define OMAP4430_RST2ST_MASK (1 << 1) - -/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */ -#define OMAP4430_RST3_SHIFT 2 -#define OMAP4430_RST3_MASK (1 << 2) - -/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */ -#define OMAP4430_RST3ST_SHIFT 2 -#define OMAP4430_RST3ST_MASK (1 << 2) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME1_SHIFT 0 -#define OMAP4430_RSTTIME1_MASK (0x3ff << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP4430_RSTTIME2_SHIFT 10 -#define OMAP4430_RSTTIME2_MASK (0x1f << 10) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0 #define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by REVISION_PRM */ -#define OMAP4430_R_RTL_SHIFT 11 -#define OMAP4430_R_RTL_MASK (0x1f << 11) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_CORE_L_SHIFT 0 -#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0) - -/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0 #define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_IVA_L_SHIFT 8 -#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8) - -/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8 #define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) - -/* Used by PRM_VC_CFG_CHANNEL */ #define OMAP4430_SA_VDD_MPU_L_SHIFT 16 -#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16) - -/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */ -#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16 #define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) - -/* Used by REVISION_PRM */ -#define OMAP4430_SCHEME_SHIFT 30 -#define OMAP4430_SCHEME_MASK (0x3 << 30) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLH_SHIFT 0 -#define OMAP4430_SCLH_MASK (0xff << 0) - -/* Used by PRM_VC_CFG_I2C_CLK */ #define OMAP4430_SCLL_SHIFT 8 -#define OMAP4430_SCLL_MASK (0xff << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_SECURE_WDT_RST_SHIFT 4 -#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_SL2_MEM_STATEST_SHIFT 6 -#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ #define OMAP4430_SLAVEADDR_SHIFT 0 -#define OMAP4430_SLAVEADDR_MASK (0x7f << 0) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3 -#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_SLPCNT_VALUE_SHIFT 16 -#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9 -#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17 -#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8 -#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16 -#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10 -#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18 -#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2EN_SHIFT 0 -#define OMAP4430_SR2EN_MASK (1 << 0) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6) - -/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */ -#define OMAP4430_SR2_STATUS_SHIFT 3 -#define OMAP4430_SR2_STATUS_MASK (0x3 << 3) - -/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */ -#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAMLDO_STATUS_SHIFT 8 -#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8) - -/* - * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL, - * PRM_LDO_SRAM_MPU_CTRL - */ -#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP4430_SRMODEEN_SHIFT 4 -#define OMAP4430_SRMODEEN_MASK (1 << 4) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_COUNT_SHIFT 0 -#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP4430_STABLE_PRESCAL_SHIFT 8 -#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_LDO_BANDGAP_SETUP */ -#define OMAP4430_STARTUP_COUNT_SHIFT 0 -#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_IVAHD_PWRSTCTRL */ -#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11) - -/* Used by PM_IVAHD_PWRSTST */ -#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2 -#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2) - -/* Used by RM_TESLA_RSTST */ -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3 -#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20 -#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10 -#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8 -#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16 -#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8 -#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L1_STATEST_SHIFT 4 -#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18 -#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_TESLA_PWRSTCTRL */ -#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9 -#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_TESLA_PWRSTST */ -#define OMAP4430_TESLA_L2_STATEST_SHIFT 6 -#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_TIMEOUT_SHIFT 0 -#define OMAP4430_TIMEOUT_MASK (0xffff << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_TIMEOUTEN_SHIFT 3 #define OMAP4430_TIMEOUTEN_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_TRANSITION_EN_SHIFT 8 -#define OMAP4430_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_TRANSITION_ST_SHIFT 8 -#define OMAP4430_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP4430_VALID_SHIFT 24 #define OMAP4430_VALID_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30 -#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_RAERR_EN_SHIFT 12 -#define OMAP4430_VC_RAERR_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_RAERR_ST_SHIFT 12 -#define OMAP4430_VC_RAERR_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_SAERR_EN_SHIFT 11 -#define OMAP4430_VC_SAERR_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_SAERR_ST_SHIFT 11 -#define OMAP4430_VC_SAERR_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VC_TOERR_EN_SHIFT 13 -#define OMAP4430_VC_TOERR_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VC_TOERR_ST_SHIFT 13 -#define OMAP4430_VC_TOERR_ST_MASK (1 << 13) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMAX_SHIFT 24 -#define OMAP4430_VDDMAX_MASK (0xff << 24) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */ #define OMAP4430_VDDMIN_SHIFT 16 -#define OMAP4430_VDDMIN_MASK (0xff << 16) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14 -#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9 -#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 -#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13) - -/* Used by PRM_VOLTCTRL */ -#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8) - -/* Used by PRM_RSTST */ #define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12 -#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20 -#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11 -#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19 -#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13 -#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13) - -/* Used by PRM_VC_ERRST */ -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21 -#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0 #define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8 #define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) - -/* Used by PRM_VC_VAL_SMPS_RA_VOL */ -#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16 #define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP4430_VPENABLE_SHIFT 0 #define OMAP4430_VPENABLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP4430_VPINIDLE_SHIFT 0 -#define OMAP4430_VPINIDLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP4430_VPVOLTAGE_SHIFT 0 #define OMAP4430_VPVOLTAGE_MASK (0xff << 0) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21 #define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28 -#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26 -#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25 -#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27 -#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29 -#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29) - -/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */ -#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29 #define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5 #define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ #define OMAP4430_VSTEPMAX_SHIFT 0 -#define OMAP4430_VSTEPMAX_MASK (0xff << 0) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ #define OMAP4430_VSTEPMIN_SHIFT 0 -#define OMAP4430_VSTEPMIN_MASK (0xff << 0) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP4430_WAKE_MODEM_SHIFT 0 -#define OMAP4430_WAKE_MODEM_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_DMTIMER10_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER11_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER2_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER3_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER4_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_DMTIMER9_WKDEP */ -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5 -#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4 -#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9 -#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11 -#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10 -#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_GPIO1_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13 -#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14 -#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14) - -/* Used by PM_L4PER_HECC1_WKDEP */ -#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_HECC2_WKDEP */ -#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_KEYBOARD_WKDEP */ -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCASP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCASP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCBSP4_WKDEP */ -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC6_WKDEP */ -#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD3_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD4_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMCSD5_WKDEP */ -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_PCIESS_WKDEP */ -#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_PDM_WKDEP */ -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_WKUP_RTC_WKDEP */ -#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_SLIMBUS_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6 -#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_SLIMBUS2_WKDEP */ -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1) - -/* Used by PM_ALWON_SR_CORE_WKDEP */ -#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1) - -/* Used by PM_ALWON_SR_IVA_WKDEP */ -#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0) - -/* Used by PM_ALWON_SR_MPU_WKDEP */ -#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_TIMER12_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_TIMER1_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2 -#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_UNIPRO1_WKDEP */ -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_WKDEP */ -#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_OTG_WKDEP */ -#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_TLL_WKDEP */ -#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0) - -/* Used by PM_WKUP_USIM_WKDEP */ -#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3 -#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1) - -/* Used by PM_WKUP_WDT2_WKDEP */ -#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_WDT3_WKDEP */ -#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0 -#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8 -#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8) - -/* Used by PM_L3INIT_XHPI_WKDEP */ -#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1 -#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP4430_WUCLK_CTRL_SHIFT 8 #define OMAP4430_WUCLK_CTRL_MASK (1 << 8) - -/* Used by PRM_IO_PMCTRL */ #define OMAP4430_WUCLK_STATUS_SHIFT 9 #define OMAP4430_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP4430_X_MAJOR_SHIFT 8 -#define OMAP4430_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP4430_Y_MINOR_SHIFT 0 -#define OMAP4430_Y_MINOR_MASK (0x3f << 0) #endif diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h deleted file mode 100644 index be31b21aa9c6..000000000000 --- a/arch/arm/mach-omap2/prm-regbits-54xx.h +++ /dev/null @@ -1,2701 +0,0 @@ -/* - * OMAP54xx Power Management register bits - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com - * - * Paul Walmsley (paul@pwsan.com) - * Rajendra Nayak (rnayak@ti.com) - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ABBOFF_ACT_SHIFT 1 -#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1 -#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2 -#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1 -#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31 -#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1 -#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31 -#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1 -#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7 -#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1 -#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7 -#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1 -#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2 -#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1 -#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16 -#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8 -#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP54XX_AESSMEM_STATEST_SHIFT 4 -#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2 -#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_AIPOFF_SHIFT 8 -#define OMAP54XX_AIPOFF_WIDTH 0x1 -#define OMAP54XX_AIPOFF_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0 -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4 -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2 -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2 -#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_RA_ERR_SHIFT 1 -#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_SA_ERR_SHIFT 0 -#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0) - -/* Used by PRM_VC_BYPASS_ERRST */ -#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2 -#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1 -#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_C2C_RST_SHIFT 10 -#define OMAP54XX_C2C_RST_WIDTH 0x1 -#define OMAP54XX_C2C_RST_MASK (1 << 10) - -/* Used by PM_CAM_PWRSTCTRL */ -#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CAM_PWRSTST */ -#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4 -#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_CLKREQCTRL */ -#define OMAP54XX_CLKREQ_COND_SHIFT 0 -#define OMAP54XX_CLKREQ_COND_WIDTH 0x3 -#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16 -#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8 -#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28 -#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18 -#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9 -#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6 -#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2 -#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16 -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8 -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1 -#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4 -#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4) - -/* Used by REVISION_PRM */ -#define OMAP54XX_CUSTOM_SHIFT 6 -#define OMAP54XX_CUSTOM_WIDTH 0x2 -#define OMAP54XX_CUSTOM_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_DATA_SHIFT 16 -#define OMAP54XX_DATA_WIDTH 0x8 -#define OMAP54XX_DATA_MASK (0xff << 16) - -/* Used by PRM_DEBUG_CORE_RET_TRANS */ -#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0 -#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c -#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa -#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7 -#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20 -#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0) - -/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */ -#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0 -#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc -#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0 -#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1 -#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_DFILTEREN_SHIFT 6 -#define OMAP54XX_DFILTEREN_WIDTH 0x1 -#define OMAP54XX_DFILTEREN_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4 -#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4 -#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0 -#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0 -#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2 -#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2 -#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1 -#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1 -#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3 -#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1 -#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3 -#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1 -#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20 -#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10 -#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8 -#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16 -#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8 -#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_L1_STATEST_SHIFT 4 -#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18 -#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_DSP_PWRSTCTRL */ -#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9 -#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_DSP_PWRSTST */ -#define OMAP54XX_DSP_L2_STATEST_SHIFT 6 -#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2 -#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_DSS_PWRSTCTRL */ -#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8 -#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_DSS_PWRSTST */ -#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4 -#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8 -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1 -#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8) - -/* Used by PRM_DEVICE_OFF_CTRL */ -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9 -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1 -#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9) - -/* Used by PM_EMU_PWRSTCTRL */ -#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16 -#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_EMU_PWRSTST */ -#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4 -#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4) - -/* - * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP, - * PRM_SRAM_WKUP_SETUP - */ -#define OMAP54XX_ENABLE_RTA_SHIFT 0 -#define OMAP54XX_ENABLE_RTA_WIDTH 0x1 -#define OMAP54XX_ENABLE_RTA_MASK (1 << 0) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC1_SHIFT 3 -#define OMAP54XX_ENFUNC1_WIDTH 0x1 -#define OMAP54XX_ENFUNC1_MASK (1 << 3) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC2_SHIFT 4 -#define OMAP54XX_ENFUNC2_WIDTH 0x1 -#define OMAP54XX_ENFUNC2_MASK (1 << 4) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC3_SHIFT 5 -#define OMAP54XX_ENFUNC3_WIDTH 0x1 -#define OMAP54XX_ENFUNC3_MASK (1 << 5) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC4_SHIFT 6 -#define OMAP54XX_ENFUNC4_WIDTH 0x1 -#define OMAP54XX_ENFUNC4_MASK (1 << 6) - -/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */ -#define OMAP54XX_ENFUNC5_SHIFT 7 -#define OMAP54XX_ENFUNC5_WIDTH 0x1 -#define OMAP54XX_ENFUNC5_MASK (1 << 7) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_ERRORGAIN_SHIFT 16 -#define OMAP54XX_ERRORGAIN_WIDTH 0x8 -#define OMAP54XX_ERRORGAIN_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_ERROROFFSET_SHIFT 24 -#define OMAP54XX_ERROROFFSET_WIDTH 0x8 -#define OMAP54XX_ERROROFFSET_MASK (0xff << 24) - -/* Used by PRM_RSTST */ -#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5 -#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1 -#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_FORCEUPDATE_SHIFT 1 -#define OMAP54XX_FORCEUPDATE_WIDTH 0x1 -#define OMAP54XX_FORCEUPDATE_MASK (1 << 1) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8 -#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18 -#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8) - -/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */ -#define OMAP54XX_FORCEWKUP_EN_SHIFT 10 -#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1 -#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10) - -/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */ -#define OMAP54XX_FORCEWKUP_ST_SHIFT 10 -#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1 -#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10) - -/* Used by REVISION_PRM */ -#define OMAP54XX_FUNC_SHIFT 16 -#define OMAP54XX_FUNC_WIDTH 0xc -#define OMAP54XX_FUNC_MASK (0xfff << 16) - -/* Used by PRM_RSTST */ -#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0 -#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1 -#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0) - -/* Used by PRM_RSTST */ -#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1 -#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1 -#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_GLOBAL_WUEN_SHIFT 16 -#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1 -#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16) - -/* Used by PM_GPU_PWRSTCTRL */ -#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_GPU_PWRSTST */ -#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4 -#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_HSMCODE_SHIFT 0 -#define OMAP54XX_HSMCODE_WIDTH 0x3 -#define OMAP54XX_HSMCODE_MASK (0x7 << 0) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_HSMODEEN_SHIFT 3 -#define OMAP54XX_HSMODEEN_WIDTH 0x1 -#define OMAP54XX_HSMODEEN_MASK (1 << 3) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_HSSCLH_SHIFT 16 -#define OMAP54XX_HSSCLH_WIDTH 0x8 -#define OMAP54XX_HSSCLH_MASK (0xff << 16) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_HSSCLL_SHIFT 24 -#define OMAP54XX_HSSCLL_WIDTH 0x8 -#define OMAP54XX_HSSCLL_MASK (0xff << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16 -#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8 -#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4 -#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4) - -/* Used by PRM_RSTST */ -#define OMAP54XX_ICEPICK_RST_SHIFT 9 -#define OMAP54XX_ICEPICK_RST_WIDTH 0x1 -#define OMAP54XX_ICEPICK_RST_MASK (1 << 9) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_INITVDD_SHIFT 2 -#define OMAP54XX_INITVDD_WIDTH 0x1 -#define OMAP54XX_INITVDD_MASK (1 << 2) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_INITVOLTAGE_SHIFT 8 -#define OMAP54XX_INITVOLTAGE_WIDTH 0x8 -#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST, - * PRM_VOLTST_MM, PRM_VOLTST_MPU - */ -#define OMAP54XX_INTRANSITION_SHIFT 20 -#define OMAP54XX_INTRANSITION_WIDTH 0x1 -#define OMAP54XX_INTRANSITION_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_IO_EN_SHIFT 9 -#define OMAP54XX_IO_EN_WIDTH 0x1 -#define OMAP54XX_IO_EN_MASK (1 << 9) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_IO_ON_STATUS_SHIFT 5 -#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1 -#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_IO_ST_SHIFT 9 -#define OMAP54XX_IO_ST_WIDTH 0x1 -#define OMAP54XX_IO_ST_MASK (1 << 9) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20 -#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10 -#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8 -#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2 -#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22 -#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2 -#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11 -#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1 -#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10 -#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2 -#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0 -#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1 -#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOCLK_STATUS_SHIFT 1 -#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1 -#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4 -#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1 -#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4) - -/* Used by PRM_IO_COUNT */ -#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0 -#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8 -#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16 -#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8 -#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1 -#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4 -#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18 -#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_L3INIT_PWRSTCTRL */ -#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9 -#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9) - -/* Used by PM_L3INIT_PWRSTST */ -#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6 -#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2 -#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24 -#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2 -#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) - -/* Used by PRM_RSTST */ -#define OMAP54XX_LLI_RST_SHIFT 14 -#define OMAP54XX_LLI_RST_WIDTH 0x1 -#define OMAP54XX_LLI_RST_MASK (1 << 14) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL, - * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_LOGICRETSTATE_SHIFT 2 -#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1 -#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_LOGICSTATEST_SHIFT 2 -#define OMAP54XX_LOGICSTATEST_WIDTH 0x1 -#define OMAP54XX_LOGICSTATEST_MASK (1 << 2) - -/* - * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT, - * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT, - * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT, - * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT, - * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, - * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT, - * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT, - * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT, - * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT, - * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT, - * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, - * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT, - * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT, - * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT, - * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, - * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, - * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, - * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT, - * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT, - * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, - * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, - * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, - * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, - * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT, - * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT, - * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, - * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT, - * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT, - * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT, - * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT, - * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT, - * RM_WKUPAON_WD_TIMER2_CONTEXT - */ -#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0 -#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1 -#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0) - -/* - * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT, - * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT, - * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, - * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT, - * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT, - * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT, - * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT, - * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT, - * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT, - * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT, - * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT, - * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT, - * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT, - * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, - * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, - * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT, - * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT, - * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT - */ -#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1 -#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1 -#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1) - -/* Used by RM_ABE_AESS_CONTEXT */ -#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8) - -/* Used by RM_CAM_CAL_CONTEXT */ -#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8) - -/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */ -#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8) - -/* Used by RM_EMIF_DMM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9) - -/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8) - -/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8) - -/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */ -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10 -#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8 -#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8) - -/* Used by RM_DSP_DSP_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9 -#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9) - -/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */ -#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8) - -/* Used by RM_EMU_DEBUGSS_CONTEXT */ -#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8) - -/* Used by RM_GPU_GPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10 -#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10) - -/* Used by RM_IPU_IPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9 -#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9) - -/* Used by RM_IPU_IPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8 -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8) - -/* - * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, - * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT, - * RM_L3INIT_USB_OTG_SS_CONTEXT - */ -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8 -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9 -#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9) - -/* Used by RM_MPU_MPU_CONTEXT */ -#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10 -#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10) - -/* - * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT, - * RM_L4SEC_FPKA_CONTEXT - */ -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8) - -/* - * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, - * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT - */ -#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8) - -/* - * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT, - * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT, - * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT - */ -#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8) - -/* Used by RM_IVA_SL2_CONTEXT */ -#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8 -#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8) - -/* Used by RM_IVA_IVA_CONTEXT */ -#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9 -#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9) - -/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */ -#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8 -#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1 -#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, - * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4 -#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1 -#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4) - -/* Used by PRM_DEBUG_TRANS_CFG */ -#define OMAP54XX_MODE_SHIFT 0 -#define OMAP54XX_MODE_WIDTH 0x2 -#define OMAP54XX_MODE_MASK (0x3 << 0) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9 -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1 -#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9) - -/* Used by PRM_MODEM_IF_CTRL */ -#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8 -#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1 -#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18 -#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2 -#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9 -#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1 -#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP54XX_MPU_L2_STATEST_SHIFT 6 -#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2 -#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20 -#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_MPU_PWRSTCTRL */ -#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10 -#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10) - -/* Used by PM_MPU_PWRSTST */ -#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8 -#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2 -#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2 -#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1 -#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_MPU_WDT_RST_SHIFT 3 -#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1 -#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_NOCAP_SHIFT 4 -#define OMAP54XX_NOCAP_WIDTH 0x1 -#define OMAP54XX_NOCAP_MASK (1 << 4) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24 -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2 -#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) - -/* Used by PM_CORE_PWRSTCTRL */ -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12 -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1 -#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) - -/* Used by PM_CORE_PWRSTST */ -#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12 -#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2 -#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_OFF_SHIFT 0 -#define OMAP54XX_OFF_WIDTH 0x8 -#define OMAP54XX_OFF_MASK (0xff << 0) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_ON_SHIFT 24 -#define OMAP54XX_ON_WIDTH 0x8 -#define OMAP54XX_ON_MASK (0xff << 24) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_ONLP_SHIFT 16 -#define OMAP54XX_ONLP_WIDTH 0x8 -#define OMAP54XX_ONLP_MASK (0xff << 16) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_OPP_CHANGE_SHIFT 2 -#define OMAP54XX_OPP_CHANGE_WIDTH 0x1 -#define OMAP54XX_OPP_CHANGE_MASK (1 << 2) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25 -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1 -#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_OPP_SEL_SHIFT 0 -#define OMAP54XX_OPP_SEL_WIDTH 0x2 -#define OMAP54XX_OPP_SEL_MASK (0x3 << 0) - -/* Used by PRM_DEBUG_OUT */ -#define OMAP54XX_OUTPUT_SHIFT 0 -#define OMAP54XX_OUTPUT_WIDTH 0x20 -#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0 -#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6 -#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP54XX_PCHARGE_TIME_SHIFT 0 -#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8 -#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20 -#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_ABE_PWRSTCTRL */ -#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10 -#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_ABE_PWRSTST */ -#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8 -#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2 -#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8) - -/* Used by PRM_PHASE1_CNDP */ -#define OMAP54XX_PHASE1_CNDP_SHIFT 0 -#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2A_CNDP */ -#define OMAP54XX_PHASE2A_CNDP_SHIFT 0 -#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PHASE2B_CNDP */ -#define OMAP54XX_PHASE2B_CNDP_SHIFT 0 -#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20 -#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0) - -/* Used by PRM_PSCON_COUNT */ -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8 -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8 -#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8) - -/* - * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL, - * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL, - * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, - * PM_MPU_PWRSTCTRL - */ -#define OMAP54XX_POWERSTATE_SHIFT 0 -#define OMAP54XX_POWERSTATE_WIDTH 0x2 -#define OMAP54XX_POWERSTATE_MASK (0x3 << 0) - -/* - * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST, - * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST, - * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST - */ -#define OMAP54XX_POWERSTATEST_SHIFT 0 -#define OMAP54XX_POWERSTATEST_WIDTH 0x2 -#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0) - -/* Used by PRM_PWRREQCTRL */ -#define OMAP54XX_PWRREQ_COND_SHIFT 0 -#define OMAP54XX_PWRREQ_COND_WIDTH 0x2 -#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27 -#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26 -#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16 -#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6 -#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24 -#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2 -#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0 -#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6 -#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0) - -/* - * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP, - * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF, - * PRM_VOLTSETUP_MPU_RET_SLEEP - */ -#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8 -#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2 -#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25 -#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_REGADDR_SHIFT 8 -#define OMAP54XX_REGADDR_WIDTH 0x8 -#define OMAP54XX_REGADDR_MASK (0xff << 8) - -/* - * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L, - * PRM_VC_VAL_CMD_VDD_MPU_L - */ -#define OMAP54XX_RET_SHIFT 8 -#define OMAP54XX_RET_WIDTH 0x8 -#define OMAP54XX_RET_MASK (0xff << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_RETMODE_ENABLE_SHIFT 0 -#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1 -#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP54XX_RSTTIME1_SHIFT 0 -#define OMAP54XX_RSTTIME1_WIDTH 0xa -#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0) - -/* Used by PRM_RSTTIME */ -#define OMAP54XX_RSTTIME2_SHIFT 10 -#define OMAP54XX_RSTTIME2_WIDTH 0x5 -#define OMAP54XX_RSTTIME2_MASK (0x1f << 10) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_CPU0_SHIFT 0 -#define OMAP54XX_RST_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_CPU0_MASK (1 << 0) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_CPU1_SHIFT 1 -#define OMAP54XX_RST_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_CPU1_MASK (1 << 1) - -/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_SHIFT 0 -#define OMAP54XX_RST_DSP_WIDTH 0x1 -#define OMAP54XX_RST_DSP_MASK (1 << 0) - -/* Used by RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_EMU_SHIFT 2 -#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1 -#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2) - -/* Used by RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3 -#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1 -#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3) - -/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */ -#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1 -#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1 -#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3 -#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4 -#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3 -#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4 -#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4) - -/* Used by PRM_RSTCTRL */ -#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1 -#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1 -#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1) - -/* Used by PRM_RSTCTRL */ -#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0 -#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1 -#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5 -#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5) - -/* Used by RM_IPU_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6 -#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5 -#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5) - -/* Used by RM_IVA_RSTST */ -#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6 -#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6) - -/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */ -#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2 -#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1 -#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_LOGIC_SHIFT 2 -#define OMAP54XX_RST_LOGIC_WIDTH 0x1 -#define OMAP54XX_RST_LOGIC_MASK (1 << 2) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_SEQ1_SHIFT 0 -#define OMAP54XX_RST_SEQ1_WIDTH 0x1 -#define OMAP54XX_RST_SEQ1_MASK (1 << 0) - -/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */ -#define OMAP54XX_RST_SEQ2_SHIFT 1 -#define OMAP54XX_RST_SEQ2_WIDTH 0x1 -#define OMAP54XX_RST_SEQ2_MASK (1 << 1) - -/* Used by REVISION_PRM */ -#define OMAP54XX_R_RTL_SHIFT 11 -#define OMAP54XX_R_RTL_WIDTH 0x5 -#define OMAP54XX_R_RTL_MASK (0x1f << 11) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0 -#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_SA_VDD_MM_L_SHIFT 0 -#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0 -#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7 -#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0) - -/* Used by REVISION_PRM */ -#define OMAP54XX_SCHEME_SHIFT 30 -#define OMAP54XX_SCHEME_WIDTH 0x2 -#define OMAP54XX_SCHEME_MASK (0x3 << 30) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_SCLH_SHIFT 0 -#define OMAP54XX_SCLH_WIDTH 0x8 -#define OMAP54XX_SCLH_MASK (0xff << 0) - -/* Used by PRM_VC_CFG_I2C_CLK */ -#define OMAP54XX_SCLL_SHIFT 8 -#define OMAP54XX_SCLL_WIDTH 0x8 -#define OMAP54XX_SCLL_MASK (0xff << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_SECURE_WDT_RST_SHIFT 4 -#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1 -#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24 -#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1 -#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18 -#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9 -#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6 -#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_SLAVEADDR_SHIFT 0 -#define OMAP54XX_SLAVEADDR_WIDTH 0x7 -#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_SLPCNT_VALUE_SHIFT 16 -#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8 -#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10 -#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8 -#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10 -#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1 -#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0 -#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_SR2EN_SHIFT 0 -#define OMAP54XX_SR2EN_WIDTH 0x1 -#define OMAP54XX_SR2EN_MASK (1 << 0) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6 -#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1 -#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6) - -/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */ -#define OMAP54XX_SR2_STATUS_SHIFT 3 -#define OMAP54XX_SR2_STATUS_WIDTH 0x2 -#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3) - -/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */ -#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8 -#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8 -#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1 -#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8) - -/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */ -#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9 -#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1 -#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9) - -/* Used by PRM_VC_CFG_I2C_MODE */ -#define OMAP54XX_SRMODEEN_SHIFT 4 -#define OMAP54XX_SRMODEEN_WIDTH 0x1 -#define OMAP54XX_SRMODEEN_MASK (1 << 4) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP54XX_STABLE_COUNT_SHIFT 0 -#define OMAP54XX_STABLE_COUNT_WIDTH 0x6 -#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0) - -/* Used by PRM_VOLTSETUP_WARMRESET */ -#define OMAP54XX_STABLE_PRESCAL_SHIFT 8 -#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2 -#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8) - -/* Used by PRM_BANDGAP_SETUP */ -#define OMAP54XX_STARTUP_COUNT_SHIFT 0 -#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8 -#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0) - -/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */ -#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24 -#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8 -#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20 -#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10 -#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8 -#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22 -#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2 -#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22) - -/* Used by PM_IVA_PWRSTCTRL */ -#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11 -#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1 -#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11) - -/* Used by PM_IVA_PWRSTST */ -#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10 -#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2 -#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_TIMEOUT_SHIFT 0 -#define OMAP54XX_TIMEOUT_WIDTH 0x10 -#define OMAP54XX_TIMEOUT_MASK (0xffff << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_TIMEOUTEN_SHIFT 3 -#define OMAP54XX_TIMEOUTEN_WIDTH 0x1 -#define OMAP54XX_TIMEOUTEN_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_TRANSITION_EN_SHIFT 8 -#define OMAP54XX_TRANSITION_EN_WIDTH 0x1 -#define OMAP54XX_TRANSITION_EN_MASK (1 << 8) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_TRANSITION_ST_SHIFT 8 -#define OMAP54XX_TRANSITION_ST_WIDTH 0x1 -#define OMAP54XX_TRANSITION_ST_MASK (1 << 8) - -/* Used by PRM_DEBUG_TRANS_CFG */ -#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2 -#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1 -#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13 -#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_MM_RST_SHIFT 12 -#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12) - -/* Used by PRM_RSTST */ -#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11 -#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1 -#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11) - -/* Used by PRM_VC_VAL_BYPASS */ -#define OMAP54XX_VALID_SHIFT 24 -#define OMAP54XX_VALID_WIDTH 0x1 -#define OMAP54XX_VALID_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14 -#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14 -#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22 -#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22 -#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30 -#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30 -#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6 -#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1 -#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6 -#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1 -#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_RAERR_EN_SHIFT 12 -#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_RAERR_ST_SHIFT 12 -#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_SAERR_EN_SHIFT 11 -#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_SAERR_ST_SHIFT 11 -#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VC_TOERR_EN_SHIFT 13 -#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1 -#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VC_TOERR_ST_SHIFT 13 -#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1 -#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_VDDMAX_SHIFT 24 -#define OMAP54XX_VDDMAX_WIDTH 0x8 -#define OMAP54XX_VDDMAX_MASK (0xff << 24) - -/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */ -#define OMAP54XX_VDDMIN_SHIFT 16 -#define OMAP54XX_VDDMIN_WIDTH 0x8 -#define OMAP54XX_VDDMIN_MASK (0xff << 16) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12 -#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8 -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14 -#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9 -#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1 -#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7 -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13 -#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13) - -/* Used by PRM_VOLTCTRL */ -#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8 -#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8) - -/* Used by PRM_RSTST */ -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6 -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1 -#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4 -#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3 -#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3) - -/* Used by PRM_VC_CORE_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5) - -/* Used by PRM_VC_MM_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5) - -/* Used by PRM_VC_MPU_ERRST */ -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1 -#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5) - -/* Used by PRM_VC_SMPS_CORE_CONFIG */ -#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8) - -/* Used by PRM_VC_SMPS_MM_CONFIG */ -#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8) - -/* Used by PRM_VC_SMPS_MPU_CONFIG */ -#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8 -#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8 -#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8) - -/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */ -#define OMAP54XX_VOLTSTATEST_SHIFT 0 -#define OMAP54XX_VOLTSTATEST_WIDTH 0x2 -#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0) - -/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */ -#define OMAP54XX_VPENABLE_SHIFT 0 -#define OMAP54XX_VPENABLE_WIDTH 0x1 -#define OMAP54XX_VPENABLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */ -#define OMAP54XX_VPINIDLE_SHIFT 0 -#define OMAP54XX_VPINIDLE_WIDTH 0x1 -#define OMAP54XX_VPINIDLE_MASK (1 << 0) - -/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */ -#define OMAP54XX_VPVOLTAGE_SHIFT 0 -#define OMAP54XX_VPVOLTAGE_WIDTH 0x8 -#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20 -#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20 -#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18 -#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18 -#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17 -#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17 -#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19 -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19 -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21 -#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21 -#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28 -#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28 -#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26 -#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26 -#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25 -#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25 -#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27 -#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27 -#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24) - -/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */ -#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29 -#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29) - -/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */ -#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29 -#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4 -#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4 -#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2 -#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2 -#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1 -#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1 -#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3 -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3 -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0) - -/* Used by PRM_IRQENABLE_MPU_2 */ -#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5 -#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1 -#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5) - -/* Used by PRM_IRQSTATUS_MPU_2 */ -#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5 -#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1 -#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5) - -/* Used by PRM_SRAM_COUNT */ -#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8 -#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8 -#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8) - -/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */ -#define OMAP54XX_VSTEPMAX_SHIFT 0 -#define OMAP54XX_VSTEPMAX_WIDTH 0x8 -#define OMAP54XX_VSTEPMAX_MASK (0xff << 0) - -/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */ -#define OMAP54XX_VSTEPMIN_SHIFT 0 -#define OMAP54XX_VSTEPMIN_WIDTH 0x8 -#define OMAP54XX_VSTEPMIN_MASK (0xff << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_DMIC_WKDEP */ -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5 -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4 -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10 -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9 -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8 -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11 -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17 -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16 -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15 -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18 -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_GPIO1_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO2_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO3_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO4_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO5_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO6_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6) - -/* Used by PM_L4PER_GPIO7_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_GPIO8_WKDEP */ -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19 -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14 -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13 -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13) - -/* Used by PM_DSS_DSS_WKDEP */ -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12 -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_HSI_WKDEP */ -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C1_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C2_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C3_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_I2C4_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_I2C5_WKDEP */ -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_KBD_WKDEP */ -#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCASP_WKDEP */ -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0) - -/* Used by PM_ABE_MCBSP3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_MCPDM_WKDEP */ -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI1_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI2_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI3_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MCSPI4_WKDEP */ -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC1_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_MMC2_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC3_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC4_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC4_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_MMC5_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_MMC5_WKDEP */ -#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_SATA_WKDEP */ -#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2) - -/* Used by PM_ABE_SLIMBUS1_WKDEP */ -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1) - -/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0) - -/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */ -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER10_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER11_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER11_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_TIMER12_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_TIMER1_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER2_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER4_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER4_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER5_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER6_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER7_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2) - -/* Used by PM_ABE_TIMER8_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_TIMER9_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_TIMER9_WKDEP */ -#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART1_WKDEP */ -#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART2_WKDEP */ -#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2 -#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART3_WKDEP */ -#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART4_WKDEP */ -#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART5_WKDEP */ -#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART5_WKDEP */ -#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3) - -/* Used by PM_L4PER_UART6_WKDEP */ -#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0) - -/* Used by PM_L4PER_UART6_WKDEP */ -#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3 -#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3) - -/* Used by PM_L3INIT_UNIPRO2_WKDEP */ -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0) - -/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1) - -/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */ -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0) - -/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */ -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0) - -/* Used by PM_ABE_WD_TIMER3_WKDEP */ -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0 -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1 -#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_WUCLK_CTRL_SHIFT 8 -#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1 -#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8) - -/* Used by PRM_IO_PMCTRL */ -#define OMAP54XX_WUCLK_STATUS_SHIFT 9 -#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1 -#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9) - -/* Used by REVISION_PRM */ -#define OMAP54XX_X_MAJOR_SHIFT 8 -#define OMAP54XX_X_MAJOR_WIDTH 0x3 -#define OMAP54XX_X_MAJOR_MASK (0x7 << 8) - -/* Used by REVISION_PRM */ -#define OMAP54XX_Y_MINOR_SHIFT 0 -#define OMAP54XX_Y_MINOR_WIDTH 0x6 -#define OMAP54XX_Y_MINOR_MASK (0x3f << 0) -#endif diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c index 415c7e0c9393..03a603476cfc 100644 --- a/arch/arm/mach-omap2/prm44xx.c +++ b/arch/arm/mach-omap2/prm44xx.c @@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) return 0; } +static int omap4_check_vcvp(void) +{ + /* No VC/VP on dra7xx devices */ + if (soc_is_dra7xx()) + return 0; + + return 1; +} + struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, @@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = { .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, .pwrdm_wait_transition = omap4_pwrdm_wait_transition, + .pwrdm_has_voltdm = omap4_check_vcvp, }; /* @@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = { int __init omap44xx_prm_init(void) { - if (!cpu_is_omap44xx() && !soc_is_omap54xx()) + if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx()) return 0; return prm_register(&omap44xx_prm_ll_data); diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h new file mode 100644 index 000000000000..d92a8404edc7 --- /dev/null +++ b/arch/arm/mach-omap2/prm7xx.h @@ -0,0 +1,678 @@ +/* + * DRA7xx PRM instance offset macros + * + * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com + * + * Generated by code originally written by: + * Paul Walmsley (paul@pwsan.com) + * Rajendra Nayak (rnayak@ti.com) + * Benoit Cousson (b-cousson@ti.com) + * + * This file is automatically generated from the OMAP hardware databases. + * We respectfully ask that any modifications to this file be coordinated + * with the public linux-omap@vger.kernel.org mailing list and the + * authors above to ensure that the autogeneration scripts are kept + * up-to-date with the file contents. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H + +#include "prm44xx_54xx.h" +#include "prcm-common.h" +#include "prm.h" + +#define DRA7XX_PRM_BASE 0x4ae06000 + +#define DRA7XX_PRM_REGADDR(inst, reg) \ + OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg)) + + +/* PRM instances */ +#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000 +#define DRA7XX_PRM_CKGEN_INST 0x0100 +#define DRA7XX_PRM_MPU_INST 0x0300 +#define DRA7XX_PRM_DSP1_INST 0x0400 +#define DRA7XX_PRM_IPU_INST 0x0500 +#define DRA7XX_PRM_COREAON_INST 0x0628 +#define DRA7XX_PRM_CORE_INST 0x0700 +#define DRA7XX_PRM_IVA_INST 0x0f00 +#define DRA7XX_PRM_CAM_INST 0x1000 +#define DRA7XX_PRM_DSS_INST 0x1100 +#define DRA7XX_PRM_GPU_INST 0x1200 +#define DRA7XX_PRM_L3INIT_INST 0x1300 +#define DRA7XX_PRM_L4PER_INST 0x1400 +#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600 +#define DRA7XX_PRM_WKUPAON_INST 0x1724 +#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800 +#define DRA7XX_PRM_EMU_INST 0x1900 +#define DRA7XX_PRM_EMU_CM_INST 0x1a00 +#define DRA7XX_PRM_DSP2_INST 0x1b00 +#define DRA7XX_PRM_EVE1_INST 0x1b40 +#define DRA7XX_PRM_EVE2_INST 0x1b80 +#define DRA7XX_PRM_EVE3_INST 0x1bc0 +#define DRA7XX_PRM_EVE4_INST 0x1c00 +#define DRA7XX_PRM_RTC_INST 0x1c60 +#define DRA7XX_PRM_VPE_INST 0x1c80 +#define DRA7XX_PRM_DEVICE_INST 0x1d00 +#define DRA7XX_PRM_INSTR_INST 0x1f00 + +/* PRM clockdomain register offsets (from instance start) */ +#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 +#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 + +/* PRM */ + +/* PRM.OCP_SOCKET_PRM register offsets */ +#define DRA7XX_REVISION_PRM_OFFSET 0x0000 +#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 +#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 +#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 +#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c +#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 +#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 +#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 +#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 +#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) +#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 +#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 +#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c +#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 +#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 +#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 +#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c +#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 +#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 +#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 +#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c +#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 +#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 +#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 +#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec +#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 + +/* PRM.CKGEN_PRM register offsets */ +#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 +#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) +#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 +#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) +#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c +#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) +#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 +#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) +#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 +#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) +#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 +#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) +#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c +#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) +#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 +#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) +#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 +#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) +#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 +#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) +#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c +#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) +#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 +#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) +#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 +#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) +#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 +#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) +#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 +#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) +#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 +#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) +#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 +#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) +#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c +#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) +#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 +#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) +#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 +#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) +#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 +#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) +#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c +#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) +#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 +#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) +#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 +#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) +#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 +#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) +#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c +#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) +#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 +#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) +#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 +#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) +#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 +#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) +#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 +#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) +#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 +#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) +#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 +#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) +#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c +#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) +#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 +#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) +#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 +#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) +#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 +#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) +#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c +#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) +#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 +#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) +#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 +#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) +#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 +#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) +#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac +#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) +#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 +#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) +#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 +#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) +#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 +#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) +#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc +#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) +#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 +#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) +#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 +#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) +#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 +#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) +#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc +#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) +#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 +#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) +#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 +#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) +#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 +#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) +#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc +#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) +#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 +#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) + +/* PRM.MPU_PRM register offsets */ +#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 + +/* PRM.DSP1_PRM register offsets */ +#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 + +/* PRM.IPU_PRM register offsets */ +#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 +#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 +#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 +#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 +#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c +#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 +#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 +#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 +#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c +#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 +#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 +#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 +#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c +#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 +#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 + +/* PRM.COREAON_PRM register offsets */ +#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 +#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 +#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 +#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 +#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 +#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 +#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 +#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 +#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 +#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 +#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 +#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 +#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 +#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 + +/* PRM.CORE_PRM register offsets */ +#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 +#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c +#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 +#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 +#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 +#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 +#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c +#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 +#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 +#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c +#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 +#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 +#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 +#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c +#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 +#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 +#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c +#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 +#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c +#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 +#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac +#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 +#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc +#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 +#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc +#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 +#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc +#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 +#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc +#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 +#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 +#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 +#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 +#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 +#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c +#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 +#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c +#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 +#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 +#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 +#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c +#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 +#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c +#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 +#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c +#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 +#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c +#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 +#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c +#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 +#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c +#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 +#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c +#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 +#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c +#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 +#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac +#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 +#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc +#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 +#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 +#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c +#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 + +/* PRM.IVA_PRM register offsets */ +#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 +#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c + +/* PRM.CAM_PRM register offsets */ +#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 +#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 +#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 +#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c +#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 +#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 +#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c +#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 +#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c + +/* PRM.DSS_PRM register offsets */ +#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 +#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 +#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 +#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 +#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c + +/* PRM.GPU_PRM register offsets */ +#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 + +/* PRM.L3INIT_PRM register offsets */ +#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 +#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 +#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c +#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 +#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 +#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 +#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 +#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 +#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c +#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 +#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 +#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c +#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c +#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 +#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c +#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 +#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 +#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec +#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 +#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 + +/* PRM.L4PER_PRM register offsets */ +#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c +#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 +#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c +#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 +#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 +#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c +#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 +#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 +#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 +#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c +#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 +#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 +#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 +#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c +#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 +#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 +#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c +#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 +#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 +#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 +#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c +#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 +#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 +#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 +#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c +#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 +#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 +#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c +#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 +#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c +#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 +#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 +#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 +#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac +#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 +#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 +#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 +#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc +#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 +#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 +#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 +#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc +#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 +#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 +#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 +#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc +#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 +#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 +#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 +#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc +#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 +#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 +#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 +#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c +#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 +#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 +#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 +#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c +#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 +#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 +#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 +#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c +#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 +#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 +#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 +#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c +#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 +#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 +#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 +#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c +#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 +#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 +#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 +#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c +#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 +#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 +#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 +#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c +#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 +#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 +#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 +#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c +#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 +#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 +#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 +#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c +#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 +#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 +#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 +#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c +#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 +#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac +#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 +#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc +#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 +#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc +#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 +#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 +#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc +#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 +#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 +#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 +#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec +#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 +#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 +#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc + +/* PRM.CUSTEFUSE_PRM register offsets */ +#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 + +/* PRM.WKUPAON_PRM register offsets */ +#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 +#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 +#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 +#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c +#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 +#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 +#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 +#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c +#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 +#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 +#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 +#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 +#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 +#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 +#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 +#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c +#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 +#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 +#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 +#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c +#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 +#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 +#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 +#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 +#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 +#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 +#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 + +/* PRM.WKUPAON_CM register offsets */ +#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 +#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) +#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 +#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) +#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 +#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) +#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 +#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) +#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 +#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) +#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 +#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) +#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 +#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) +#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 +#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) +#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 +#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) +#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 +#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) +#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 +#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) +#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 +#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) +#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 +#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) +#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 +#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 +#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) +#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 +#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) +#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 +#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) + +/* PRM.EMU_PRM register offsets */ +#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 + +/* PRM.EMU_CM register offsets */ +#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 +#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 +#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) +#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 +#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c +#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) + +/* PRM.DSP2_PRM register offsets */ +#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 +#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 + +/* PRM.EVE1_PRM register offsets */ +#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 +#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 + +/* PRM.EVE2_PRM register offsets */ +#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 +#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 + +/* PRM.EVE3_PRM register offsets */ +#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 +#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 + +/* PRM.EVE4_PRM register offsets */ +#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 +#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 +#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 +#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 + +/* PRM.RTC_PRM register offsets */ +#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 +#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 + +/* PRM.VPE_PRM register offsets */ +#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 +#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 +#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 +#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 + +/* PRM.DEVICE_PRM register offsets */ +#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 +#define DRA7XX_PRM_RSTST_OFFSET 0x0004 +#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 +#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c +#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 +#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 +#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 +#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c +#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 +#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 +#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 +#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c +#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 +#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 +#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 +#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c +#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc +#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 +#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 +#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 +#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc +#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 +#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 +#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 +#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc +#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 +#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 +#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 +#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec +#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 +#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 +#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 +#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc +#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 +#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 +#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 +#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 +#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c +#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 +#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 +#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 +#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c +#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 +#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 + +#endif diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index c12320c0ae95..6334b96b4097 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c @@ -20,10 +20,13 @@ #include "common.h" #include "prcm-common.h" #include "prm44xx.h" +#include "prm54xx.h" +#include "prm7xx.h" #include "prminst44xx.h" #include "prm-regbits-44xx.h" #include "prcm44xx.h" #include "prcm_mpu44xx.h" +#include "soc.h" static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; @@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst, void omap4_prminst_global_warm_sw_reset(void) { u32 v; - - v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, - OMAP4430_PRM_DEVICE_INST, - OMAP4_PRM_RSTCTRL_OFFSET); + s16 dev_inst; + + if (cpu_is_omap44xx()) + dev_inst = OMAP4430_PRM_DEVICE_INST; + else if (soc_is_omap54xx()) + dev_inst = OMAP54XX_PRM_DEVICE_INST; + else if (soc_is_dra7xx()) + dev_inst = DRA7XX_PRM_DEVICE_INST; + else + return; + + v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst, + OMAP4_PRM_RSTCTRL_OFFSET); v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, OMAP4430_PRM_DEVICE_INST, diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h index 8c616e436bc7..4588df1447ed 100644 --- a/arch/arm/mach-omap2/soc.h +++ b/arch/arm/mach-omap2/soc.h @@ -8,6 +8,7 @@ * Written by Tony Lindgren <tony.lindgren@nokia.com> * * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> + * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,6 +36,7 @@ #ifndef __ASSEMBLY__ #include <linux/bitops.h> +#include <linux/of.h> /* * Test if multicore OMAP support is needed @@ -105,6 +107,15 @@ # endif #endif +#ifdef CONFIG_SOC_DRA7XX +# ifdef OMAP_NAME +# undef MULTI_OMAP2 +# define MULTI_OMAP2 +# else +# define OMAP_NAME DRA7XX +# endif +#endif + /* * Omap device type i.e. EMU/HS/TST/GP/BAD */ @@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437) #define cpu_is_omap447x() 0 #define soc_is_omap54xx() 0 #define soc_is_omap543x() 0 +#define soc_is_dra7xx() 0 #if defined(MULTI_OMAP2) # if defined(CONFIG_ARCH_OMAP2) @@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430) # define soc_is_omap543x() is_omap543x() #endif +#if defined(CONFIG_SOC_DRA7XX) +#undef soc_is_dra7xx +#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7")) +#endif + /* Various silicon revisions for omap2 */ #define OMAP242X_CLASS 0x24200024 #define OMAP2420_REV_ES1_0 OMAP242X_CLASS diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index b37e1fcbad56..fa74a0625da1 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c @@ -537,7 +537,7 @@ static void __init realtime_counter_init(void) reg |= num; __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); - reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & + reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); @@ -594,13 +594,14 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL, 1, "timer_sys_ck", "ti,timer-alwon"); #endif -#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) +#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ + defined(CONFIG_SOC_DRA7XX) static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 2, "sys_clkin_ck", NULL); #endif #ifdef CONFIG_ARCH_OMAP4 -#ifdef CONFIG_LOCAL_TIMERS +#ifdef CONFIG_HAVE_ARM_TWD static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); void __init omap4_local_timer_init(void) { @@ -619,12 +620,12 @@ void __init omap4_local_timer_init(void) pr_err("twd_local_timer_register failed %d\n", err); } } -#else /* CONFIG_LOCAL_TIMERS */ +#else void __init omap4_local_timer_init(void) { omap4_sync32k_timer_init(); } -#endif /* CONFIG_LOCAL_TIMERS */ +#endif /* CONFIG_HAVE_ARM_TWD */ #endif /* CONFIG_ARCH_OMAP4 */ #ifdef CONFIG_SOC_OMAP5 diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c index 2eb19d4d0aa1..e83a6a4b184a 100644 --- a/arch/arm/mach-omap2/usb-host.c +++ b/arch/arm/mach-omap2/usb-host.c @@ -28,7 +28,7 @@ #include <linux/io.h> #include <linux/gpio.h> #include <linux/usb/phy.h> -#include <linux/usb/nop-usb-xceiv.h> +#include <linux/usb/usb_phy_gen_xceiv.h> #include "soc.h" #include "omap_device.h" @@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = { /* .init_data filled later */ }; -static const char *nop_name = "nop_usb_xceiv"; /* NOP PHY driver */ +static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */ static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */ /** @@ -460,9 +460,9 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys) pdevinfo.name = nop_name; pdevinfo.id = phy->port; pdevinfo.data = phy->platform_data; - pdevinfo.size_data = sizeof(struct nop_usb_xceiv_platform_data); - - scnprintf(phy_id, MAX_STR, "nop_usb_xceiv.%d", + pdevinfo.size_data = + sizeof(struct usb_phy_gen_xceiv_platform_data); + scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d", phy->port); pdev = platform_device_register_full(&pdevinfo); if (IS_ERR(pdev)) { |