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path: root/drivers/gpu/drm/msm
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2015-06-11drm/msm: drop redundant output in debug messageNicholas Mc Guire
wait_for_completion_timeout returns 0 in case of timeout so printing the return value here will always yield 0 and is therefor redundant - dropped. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: fix HZ dependency of timeoutNicholas Mc Guire
The timeout is passed as a constant which makes it HZ dependent because jiffies are expected so it should be converted to jiffies. The actual value is not clear from the code - my best guess is that this should be 300 milliseconds given that other timeouts are in milliseconds based on looking at other drm drivers (e.g. exynos_drm_dsi.c:356 300ms, tegra/dpaux.c:188 250ms) - this needs to be confirmed by someone who knows the details of the driver. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: fixup wait_for_completion_timeout handlingNicholas Mc Guire
wait_for_completion_timeout return >= 0 but never negative so the check logic looks inconsistent. Further the return value of wait_for_completion_timeout was being passed up the call chain but the x call sites as drm_dp_i2c_do_msg()/drm_dp_dpcd_access() check for < 0 thus timeout was being treated as success case. <snip> drivers/gpu/drm/drm_dp_helper.c:drm_dp_i2c_do_msg() mutex_lock(&aux->hw_mutex); ret = aux->transfer(aux, msg); mutex_unlock(&aux->hw_mutex); if (ret < 0) { <snip> logic in edp_aux_transfer() seems incorrect as it could return 0 (timeout) but checks of <= 0 to indicate error so the return probably should be -ETIMEDOUT in case wait_for_completion_timeout returns 0 (timeout occurred). Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm/mdp5: fix for crash in disable pathRob Clark
Seems like disable can race with complete_flip() in process of disabling a crtc, leading to: [ 49.065364] Call trace: [ 49.071441] [<ffffffc00041d5a0>] mdp5_ctl_blend+0x20/0x1c0 [ 49.073788] [<ffffffc00041ebcc>] mdp5_crtc_disable+0x3c/0xa8 [ 49.079348] [<ffffffc0003e7854>] disable_outputs.isra.4+0x11c/0x220 [ 49.085164] [<ffffffc0003e7afc>] drm_atomic_helper_commit_modeset_disables+0x14/0x38 [ 49.091155] [<ffffffc000425c80>] complete_commit+0x40/0xb8 [ 49.099136] [<ffffffc0004260ac>] msm_atomic_commit+0x364/0x398 [ 49.104430] [<ffffffc00040a614>] drm_atomic_commit+0x3c/0x70 [ 49.110249] [<ffffffc0003e67b8>] drm_atomic_helper_set_config+0x1b0/0x3e0 [ 49.116065] [<ffffffc0003f99bc>] drm_mode_set_config_internal+0x64/0xf8 [ 49.122746] [<ffffffc0003fa624>] drm_framebuffer_remove+0xe4/0x128 [ 49.129171] [<ffffffc0003feaf8>] drm_mode_rmfb+0xc0/0x100 [ 49.135420] [<ffffffc0003efba8>] drm_ioctl+0x258/0x4d0 [ 49.140889] [<ffffffc0001b0388>] do_vfs_ioctl+0x338/0x5d0 [ 49.145921] [<ffffffc0001b06a8>] SyS_ioctl+0x88/0xa0 It makes no sense to free the ctl without disabling all stages, so lets just move them together to avoid the crash. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: workaround for missing irq on a306/8x16Rob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: adreno a306 supportRob Clark
As found in apq8016 (used in DragonBoard 410c) and msm8916. Note that numerically a306 is actually 307 (since a305c already claimed 306). Nice and confusing. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: clarify downstream bus scalingRob Clark
A few spots in the driver have support for downstream android CONFIG_MSM_BUS_SCALING. This is mainly to simplify backporting the driver for various devices which do not have sufficient upstream kernel support. But the intentionally dead code seems to cause some confusion. Rename the #define to make this more clear. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm/mdp4: Support NV12MT format in mdp4Rob Clark
Using fb modifier flag, support NV12MT format in MDP4. v2: - rework the modifier's description [Daniel Vetter's comment] - drop .set_mode_config() callback [Rob Clark's comment] v3: - change VENDOR's name and restrict usage to NV12 [pointed by Daniel] Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: update generated headersRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm: add missing DRIVER_ATOMIC flagRob Clark
Somehow this got lost when msm atomic support was first merged. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-06-11drm/msm/adreno: dump scratch regs and other info on hangRob Clark
Dump a bit more info when the GPU hangs, without having hang_debug enabled (which dumps a *lot* of registers). Also dump the scratch registers, as they are useful for determining where in the cmdstream the GPU hung (and they seem always safe to read when GPU has hung). Note that the freedreno gallium driver emits increasing counter values to SCRATCH6 (to identify tile #) and SCRATCH7 (to identify draw #), so these two in particular can be used to "triangulate" where in the cmdstream the GPU hung. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-05-21drm/msm/mdp5: fix incorrect parameter for msm_framebuffer_iova()Stephane Viau
The index of ->planes[] array (3rd parameter) cannot be equal to MAX_PLANE. This looks like a typo that is now fixed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Acked-by: Rob Clark <robdclark@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-05-15drm/msm: fix locking inconsistencies in gpu->destroy()Rob Clark
In error paths, this was being called without struct_mutex held. Leading to panics like: msm 1a00000.qcom,mdss_mdp: No memory protection without IOMMU Kernel panic - not syncing: BUG! CPU: 0 PID: 1409 Comm: cat Not tainted 4.0.0-dirty #4 Hardware name: Qualcomm Technologies, Inc. APQ 8016 SBC (DT) Call trace: [<ffffffc000089c78>] dump_backtrace+0x0/0x118 [<ffffffc000089da0>] show_stack+0x10/0x20 [<ffffffc0006686d4>] dump_stack+0x84/0xc4 [<ffffffc0006678b4>] panic+0xd0/0x210 [<ffffffc0003e1ce4>] drm_gem_object_free+0x5c/0x60 [<ffffffc000402870>] adreno_gpu_cleanup+0x60/0x80 [<ffffffc0004035a0>] a3xx_destroy+0x20/0x70 [<ffffffc0004036f4>] a3xx_gpu_init+0x84/0x108 [<ffffffc0004018b8>] adreno_load_gpu+0x58/0x190 [<ffffffc000419dac>] msm_open+0x74/0x88 [<ffffffc0003e0a48>] drm_open+0x168/0x400 [<ffffffc0003e7210>] drm_stub_open+0xa8/0x118 [<ffffffc0001a0e84>] chrdev_open+0x94/0x198 [<ffffffc000199f88>] do_dentry_open+0x208/0x310 [<ffffffc00019a4c4>] vfs_open+0x44/0x50 [<ffffffc0001aa26c>] do_last.isra.14+0x2c4/0xc10 [<ffffffc0001aac38>] path_openat+0x80/0x5e8 [<ffffffc0001ac354>] do_filp_open+0x2c/0x98 [<ffffffc00019b60c>] do_sys_open+0x13c/0x228 [<ffffffc00019b72c>] SyS_openat+0xc/0x18 CPU1: stopping But there isn't any particularly good reason to hold struct_mutex for teardown, so just standardize on calling it without the mutex held and use the _unlocked() versions for GEM obj unref'ing Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-05-14drm/msm/dsi: Simplify the code to get the number of read byteHai Li
During cmd rx, only new versions of H/W provide register to read back the real number of byte returned by panel. For the old versions, reading this register will not get the right number. In fact, we only need to assume the returned data is the same size as we expected, because later we will check the data type to detect error. Signed-off-by: Hai Li <hali@codeaurora.org>
2015-05-14drm/msm: Attach assigned encoder to eDP and DSI connectorsHai Li
drm_mode_connector_attach_encoder() function call is missing during eDP and DSI connector initialization. As a result, no encoder is returned by DRM_IOCTL_MODE_GETCONNECTOR system call. This change is to fix this issue. Signed-off-by: Hai Li <hali@codeaurora.org>
2015-05-14drm/msm: setup vram after component_bind_all()Rob Clark
First of all, we don't want -EPROBE_DEFER when trying to bind children to cause us to forget to free our vram. And second we don't want vram allocation fail to trigger _unbind_all() before _bind_all(). Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-05-14drm/msm/dsi: use pr_err_ratelimitedRob Clark
When things go badly we can get a lot of these error irqs. Let's not DoS the user. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-05-14drm/msm: fix unbalanced DRM framebuffer init/destroyStephane Viau
When msm_framebuffer_init() fails before calling drm_framebuffer_init(), drm_framebuffer_cleanup() [called in msm_framebuffer_destroy()] is still being called even though drm_framebuffer_init() was not called for that buffer. Thus a NULL pointer derefencing: [ 247.529691] Unable to handle kernel NULL pointer dereference at virtual address 0000027c ... [ 247.563996] PC is at __mutex_lock_slowpath+0x94/0x3a8 ... [ 247.823025] [<c07c3c78>] (__mutex_lock_slowpath) from [<c07c3fac>] (mutex_lock+0x20/0x3c) [ 247.831186] [<c07c3fac>] (mutex_lock) from [<c0347cf0>] (drm_framebuffer_cleanup+0x18/0x38) [ 247.839520] [<c0347cf0>] (drm_framebuffer_cleanup) from [<c036d138>] (msm_framebuffer_destroy+0x48/0x100) [ 247.849066] [<c036d138>] (msm_framebuffer_destroy) from [<c036d580>] (msm_framebuffer_init+0x1e8/0x228) [ 247.858439] [<c036d580>] (msm_framebuffer_init) from [<c036d630>] (msm_framebuffer_create+0x70/0x134) [ 247.867642] [<c036d630>] (msm_framebuffer_create) from [<c03493ec>] (internal_framebuffer_create+0x67c/0x7b4) [ 247.877537] [<c03493ec>] (internal_framebuffer_create) from [<c034ce34>] (drm_mode_addfb2+0x20/0x98) [ 247.886650] [<c034ce34>] (drm_mode_addfb2) from [<c034071c>] (drm_ioctl+0x240/0x420) [ 247.894378] [<c034071c>] (drm_ioctl) from [<c011df7c>] (do_vfs_ioctl+0x4e4/0x5a4) ... Signed-off-by: Stephane Viau <sviau@codeaurora.org> [plus initialize msm_fb to NULL to -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-05-14drm/msm/mdp5: Fix iteration on INTF config arrayStephane Viau
The current iteration in get_dsi_id_from_intf() is wrong: instead of iterating until hw_cfg->intf.count, we need to iterate until MDP5_INTF_NUM_MAX here. Let's take the example of msm8x16: hw_cfg->intf.count = 1 intfs[0] = INTF_Disabled intfs[1] = INTF_DSI If we stop iterating once i reaches hw_cfg->intf.count (== 1), we will miss the test for intfs[1]. Actually, this hw_cfg->intf.count entry is quite confusing and is not (or *should not be*) used anywhere else; let's remove it. Signed-off-by: Stephane Viau <sviau@codeaurora.org>
2015-05-14drm/msm/dsi: Fixup missing *break* statement during cmd rxHai Li
Signed-off-by: Hai Li <hali@codeaurora.org>
2015-05-14drm/msm/dp: fix error return codeJulia Lawall
Return a negative error code on failure. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e1,e2; @@ ( if (\(ret < 0\|ret != 0\)) { ... return ret; } | ret = 0 ) ... when != ret = e1 when != &ret *if(...) { ... when != ret = e2 when forall return ret; } // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
2015-05-14drm: msm: Fix build when legacy fbdev support isn't setArchit Taneja
The DRM_KMS_FB_HELPER config is selected only when DRM_MSM_FBDEV config is selected. The driver accesses drm_fb_helper_* functions even when legacy fbdev support is disabled in msm. Wrap around these functions with #ifdef checks to prevent build break. Signed-off-by: Archit Taneja <architt@codeaurora.org>
2015-05-14drm/msm/dsi: Fix a couple more 64-bit build warningsStephane Viau
Avoid such errors at compilation time: format '%d' expects argument of type 'int', but argument 3 has type 'size_t' Signed-off-by: Stephane Viau <sviau@codeaurora.org>
2015-05-14drm/msm: Fix a couple of 64-bit build warningsThierry Reding
Avoid casts from pointers to fixed-size integers to prevent the compiler from warning. Print virtual memory addresses using %p instead. Also turn a couple of %d/%x specifiers into %zu/%zd/%zx to avoid further warnings due to mismatched format strings. Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Rob Clark <robdclark@gmail.com>
2015-04-20Merge Linus master into drm-nextDave Airlie
The merge is clean, but the arm build fails afterwards, due to API changes in the regulator tree. I've included the patch into the merge to fix the build. Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-04-10Merge remote-tracking branches 'regulator/topic/mode', ↵Mark Brown
'regulator/topic/notifier', 'regulator/topic/palmas', 'regulator/topic/qcom' and 'regulator/topic/stw481x' into regulator-next
2015-04-01drm/msm/mdp5: Enable DSI connector in msm drm driverHai Li
This change adds the support in mdp5 kms driver for single and dual DSI. Dual DSI case depends on the framework API and sequence change to support dual data path. v1: Initial change v2: Address Rob Clark's comment - Separate command mode encoder to a new file mdp5_cmd_encoder.c - Rebase to not depend on msm_drm_sub_dev change Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Initial add DSI connector supportHai Li
This change adds the DSI connector support in msm drm driver. v1: Initial change v2: - Address comments from Archit + minor clean-ups - Rebase to not depend on msm_drm_sub_dev change [Rob's comment] v3: Fix issues when initialization is failed Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: Add split display interfaceHai Li
This change is to add an interface to MDP for connector devices setting split display information. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Move *_modeset_init out of construct_encoder functionHai Li
This change is to make the content in construct_encoder reflect its name. Also, DSI connector may be connected to video mode or command mode encoder, so that 2 different encoders need to be constructed for DSI. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Remove CTL flush dummy bitsStephane Viau
This TODO can now be removed and replaced by the previous patch "drm/msm/mdp5: Update headers (add CTL flush bits)" Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (add CTL flush bits)Stephane Viau
Some upcoming targets have more bits to set in CTL_FLUSH registers. Example: msm8x16 needs to set TIMING1 bit so that some of the INTF1's interface registers get flushed. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add hardware configuration for msm8x16Stephane Viau
This change adds the hw configuration for msm8x16 chipsets in mdp5_cfg module. Note that only one external display interface is present in this configuration (DSI) but has not been enabled yet. It will be enabled once drm/msm driver supports DSI connectors. v2: add CTL flush register's hardware mask [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Get SMP client list from mdp5_cfgStephane Viau
SMP blocks are configured for specific client IDs (ports). These client IDs can be different from one chip to another for a given pipe. e.g.: DMA0 pipe fetch Y component is connected to: - port #10 for MDP5 v1.3 - port #4 for MDP5 v1.6 In order to be compatible for upcoming versions of MDP5, the client ID list is passed through the MDP5 config module rather than using a list of hard-coded enum values. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (remove enum mdp5_client_id)Stephane Viau
This patch contains the generated header file of the following change "drm/msm/mdp5: Get SMP client list from mdp5_cfg". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Separate MDP5 domain from MDSS domainStephane Viau
MDP block is actually contained inside the MDSS block. For some chipsets, the base address of the MDP registers is different from the current (assumed) 0x100 offset. Like CTL and LM blocks, this changes introduce a dynamic offset for the MDP instance, which can be found out at runtime, once the MDSS HW version is read. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update headers (introduce MDP5 domain)Stephane Viau
This change contains the generated header file for the following change "drm/msm/mdp5: Separate MDP5 domain from MDSS domain". Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/dsi: Update generated DSI header fileHai Li
Prepare for initial DSI implementation Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Fix PIPE source image size settingsHai Li
The width and height in SSPP_SRC_IMG_SIZE register should be the size of the entire source framebuffer, not the fetch size. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update generated mdp5 header file with DSI supportHai Li
This change adds the registers in mdp5 ping pong blocks and split display control registers. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add pingpong entry to mdp5 config tableHai Li
Pingpong register base addresses are different across platforms. This change adds this information to config table and initialize the values for 8x74 and 8084. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Make the intf connection in config moduleStephane Viau
Up until now, we assume that eDP is tight to intf_0 and HDMI to intf_3. This information shall actually come from the mdp5_cfg module since it can change from one chip to another. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] v3: add sanity check before writing in INTF_TIMING_ENGINE_EN registers Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Add START signal to kick off certain pipelinesStephane Viau
Some interfaces (WB, DSI Command Mode) need to be kicked off through a START Signal. This signal needs to be sent at the right time and requests in some cases to keep track of the pipeline status (eg: whether pipeline registers are flushed AND output WB buffers are ready, in case of WB interface). Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Enhance operation mode for pipeline configurationStephane Viau
DSI and WB interfaces need a more complex pipeline configuration than the current mdp5_ctl_set_intf(). For example, memory output connections need to be selected for WB. Interface mode (Video vs. Command modes) also need to be configured for DSI. This change takes care of configuring the whole pipeline as far as operation mode goes. DSI and WB interfaces will be added later. v2: rename macro to mdp5_cfg_intf_is_virtual() [pointed by Archit] Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Remove temp bisectability hack -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: Update generated header filesStephane Viau
Prepare for pipeline operation mode configuration, in particular for DSI and WB modes. Signed-off-by: Stephane Viau <sviau@codeaurora.org> [Throw in a #define temporarily to keep things bisectable -Rob] Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/mdp5: only flush on a CRTC ->atomic_flush()Stephane Viau
MDP5 hardware has some limitation and requires to avoid flushing registers more than once between two Vblanks. This change removes all FLUSH operations (except for HW cursor) beside the one coming from a CRTC's ->atomic_flush(). This avoid this type of behavior (eg: CRTC + 1 plane overlay): [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_ctl_commit] flush (20040) CTL + LM0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank and replaces it by: [drm:mdp5_crtc_vblank_irq] vblank [drm:mdp5_ctl_commit] flush (20048) CTL + LM0 + RGB0 [drm:mdp5_crtc_vblank_irq] blank [drm:mdp5_ctl_commit] flush (20049) CTL + LM0 + RGB0 + VIG0 [drm:mdp5_crtc_vblank_irq] blank Only *one* FLUSH is called between Vblanks interrupts. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm/hdmi: add 74.176MHz and 154.0MHz pix clksRob Clark
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: add support for "stolen" memRob Clark
Add support to use the VRAM carveout (if specified in dtb) for fbdev scanout buffer. This allows drm/msm to take over a bootloader splash- screen, and avoids corruption on screen that results if the kernel uses memory that is still being scanned out for itself. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-04-01drm/msm: split out vram initializationRob Clark
We'll want to extend this a bit to handle also a reserved-memory ("stolen") region, so that drm/msm can take-over bootloader splash screen. First split it out into it's own fxn to reduce noise in the following patch. Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-03-10regulator: fixes for regulator_set_optimum_mode name changeStephen Rothwell
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Mark Brown <broonie@kernel.org>
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-19 02:54:40 +0000