From d8005e6b95268cbb50db3773d5f180c32a9434fe Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 18 Jan 2013 15:12:18 +0530 Subject: ARC: Timers/counters/delay management ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1. Both have exactly same capabilies. * programmable to count from TIMER_CNT to TIMER_LIMIT * for count 0 and LIMIT ~1, provides a free-running counter by auto-wrapping when limit is reached. * optionally interrupt when LIMIT is reached (oneshot event semantics) * rearming the interrupt provides periodic semantics * run at CPU clk ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for clocksource (free-running clock). Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence is more apt for clocksource when available. SMP poses a bit of challenge for global timekeeping clocksource / sched_clock() backend: -TIMER1 based local clocks are out-of-sync hence can't be used (thus we default to jiffies based cs as well as sched_clock() one/both of which platform can override with it's specific hardware assist) -RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue ensures that) and thus usable for both requirements. Signed-off-by: Vineet Gupta Cc: Thomas Gleixner --- arch/arc/kernel/time.c | 295 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) create mode 100644 arch/arc/kernel/time.c (limited to 'arch/arc/kernel/time.c') diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c new file mode 100644 index 000000000000..05dba11fdb2d --- /dev/null +++ b/arch/arc/kernel/time.c @@ -0,0 +1,295 @@ +/* + * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * vineetg: Jan 1011 + * -sched_clock( ) no longer jiffies based. Uses the same clocksource + * as gtod + * + * Rajeshwarr/Vineetg: Mar 2008 + * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code) + * for arch independent gettimeofday() + * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers + * + * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c + */ + +/* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1 + * Each can programmed to go from @count to @limit and optionally + * interrupt when that happens. + * A write to Control Register clears the Interrupt + * + * We've designated TIMER0 for events (clockevents) + * while TIMER1 for free running (clocksource) + * + * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARC_TIMER_MAX 0xFFFFFFFF + +/********** Clock Source Device *********/ + +#ifdef CONFIG_ARC_HAS_RTSC + +int __cpuinit arc_counter_setup(void) +{ + /* RTSC insn taps into cpu clk, needs no setup */ + + /* For SMP, only allowed if cross-core-sync, hence usable as cs */ + return 1; +} + +static cycle_t arc_counter_read(struct clocksource *cs) +{ + unsigned long flags; + union { +#ifdef CONFIG_CPU_BIG_ENDIAN + struct { u32 high, low; }; +#else + struct { u32 low, high; }; +#endif + cycle_t full; + } stamp; + + flags = arch_local_irq_save(); + + __asm__ __volatile( + " .extCoreRegister tsch, 58, r, cannot_shortcut \n" + " rtsc %0, 0 \n" + " mov %1, tsch \n" /* TSCH is extn core reg 58 */ + : "=r" (stamp.low), "=r" (stamp.high)); + + arch_local_irq_restore(flags); + + return stamp.full; +} + +static struct clocksource arc_counter = { + .name = "ARC RTSC", + .rating = 300, + .read = arc_counter_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +#else /* !CONFIG_ARC_HAS_RTSC */ + +static bool is_usable_as_clocksource(void) +{ +#ifdef CONFIG_SMP + return 0; +#else + return 1; +#endif +} + +/* + * set 32bit TIMER1 to keep counting monotonically and wraparound + */ +int __cpuinit arc_counter_setup(void) +{ + write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); + write_aux_reg(ARC_REG_TIMER1_CNT, 0); + write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); + + return is_usable_as_clocksource(); +} + +static cycle_t arc_counter_read(struct clocksource *cs) +{ + return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); +} + +static struct clocksource arc_counter = { + .name = "ARC Timer1", + .rating = 300, + .read = arc_counter_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +#endif + +/********** Clock Event Device *********/ + +/* + * Arm the timer to interrupt after @limit cycles + * The distinction for oneshot/periodic is done in arc_event_timer_ack() below + */ +static void arc_timer_event_setup(unsigned int limit) +{ + write_aux_reg(ARC_REG_TIMER0_LIMIT, limit); + write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ + + write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); +} + +/* + * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic) + * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted) + * -Rearming is done by setting the IE bit + * + * Small optimisation: Normal code would have been + * if (irq_reenable) + * CTRL_REG = (IE | NH); + * else + * CTRL_REG = NH; + * However since IE is BIT0 we can fold the branch + */ +static void arc_timer_event_ack(unsigned int irq_reenable) +{ + write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); +} + +static int arc_clkevent_set_next_event(unsigned long delta, + struct clock_event_device *dev) +{ + arc_timer_event_setup(delta); + return 0; +} + +static void arc_clkevent_set_mode(enum clock_event_mode mode, + struct clock_event_device *dev) +{ + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: + arc_timer_event_setup(arc_get_core_freq() / HZ); + break; + case CLOCK_EVT_MODE_ONESHOT: + break; + default: + break; + } + + return; +} + +static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { + .name = "ARC Timer0", + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .mode = CLOCK_EVT_MODE_UNUSED, + .rating = 300, + .irq = TIMER0_IRQ, /* hardwired, no need for resources */ + .set_next_event = arc_clkevent_set_next_event, + .set_mode = arc_clkevent_set_mode, +}; + +static irqreturn_t timer_irq_handler(int irq, void *dev_id) +{ + struct clock_event_device *clk = &__get_cpu_var(arc_clockevent_device); + + arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC); + clk->event_handler(clk); + return IRQ_HANDLED; +} + +static struct irqaction arc_timer_irq = { + .name = "Timer0 (clock-evt-dev)", + .flags = IRQF_TIMER | IRQF_PERCPU, + .handler = timer_irq_handler, +}; + +/* + * Setup the local event timer for @cpu + * N.B. weak so that some exotic ARC SoCs can completely override it + */ +void __attribute__((weak)) __cpuinit arc_local_timer_setup(unsigned int cpu) +{ + struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu); + + clockevents_calc_mult_shift(clk, arc_get_core_freq(), 5); + + clk->max_delta_ns = clockevent_delta2ns(ARC_TIMER_MAX, clk); + clk->cpumask = cpumask_of(cpu); + + clockevents_register_device(clk); + + /* + * setup the per-cpu timer IRQ handler - for all cpus + * For non boot CPU explicitly unmask at intc + * setup_irq() -> .. -> irq_startup() already does this on boot-cpu + */ + if (!cpu) + setup_irq(TIMER0_IRQ, &arc_timer_irq); + else + arch_unmask_irq(TIMER0_IRQ); +} + +/* + * Called from start_kernel() - boot CPU only + * + * -Sets up h/w timers as applicable on boot cpu + * -Also sets up any global state needed for timer subsystem: + * - for "counting" timer, registers a clocksource, usable across CPUs + * (provided that underlying counter h/w is synchronized across cores) + * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic) + */ +void __init time_init(void) +{ + /* + * sets up the timekeeping free-flowing counter which also returns + * whether the counter is usable as clocksource + */ + if (arc_counter_setup()) + /* + * CLK upto 4.29 GHz can be safely represented in 32 bits + * because Max 32 bit number is 4,294,967,295 + */ + clocksource_register_hz(&arc_counter, arc_get_core_freq()); + + /* sets up the periodic event timer */ + arc_local_timer_setup(smp_processor_id()); +} + +#ifdef CONFIG_ARC_HAS_RTSC +/* + * sched_clock math assist + * ns = cycles * (ns_per_sec / cpu_freq_hz) + * ns = cycles * (10^6 / cpu_freq_khz) + * ns = cycles * (10^6 * 2^SF / cpu_freq_khz) / 2^SF + * ns = cycles * cyc2ns_scale >> SF + */ +#define CYC2NS_SF 10 /* 2^10, carefully chosen */ +#define CYC2NS_SCALE ((1000000 << CYC2NS_SF) / (arc_get_core_freq() / 1000)) + +static unsigned long long cycles2ns(unsigned long long cyc) +{ + return (cyc * CYC2NS_SCALE ) >> CYC2NS_SF; +} + +/* + * Scheduler clock - a monotonically increasing clock in nanosec units. + * It's return value must NOT wrap around. + * + * - Since 32bit TIMER1 will overflow almost immediately (53sec @ 80MHz), it + * can't be used directly. + * - Using getrawmonotonic (TIMER1 based, but with state for last + current + * snapshots), is no-good either because of seqlock deadlock possibilities + * - So only with native 64bit timer we do this, otherwise fallback to generic + * jiffies based version - which despite not being fine grained gaurantees + * the monotonically increasing semantics. + */ +unsigned long long sched_clock(void) +{ + return cycles2ns(arc_counter_read(NULL)); +} +#endif -- cgit v1.2.3 From 03a6d28cdddfbd11b338c23e7fe51d0816b9bdef Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Fri, 18 Jan 2013 15:12:26 +0530 Subject: ARC: [Review] Multi-platform image #2: Board callback Infrastructure The orig platform code orgnaization was singleton design pattern - only one platform (and board thereof) would build at a time. Thus any platform/board specific code (e.g. irq init, early init ...) expected by ARC common code was exported as well defined set of APIs, with only ONE instance building ever. Now with multiple-platform build requirement, that design of code no longer holds - multiple board specific calls need to build at the same time - so ARC common code can't use the API approach, it needs a callback based design where each board registers it's specific set of functions, and at runtime, depending on board detection, the callbacks are used from the registry. This commit adds all the infrastructure, where board specific callbacks are specified as a "maThine description". All the hooks are placed in right spots, no board callbacks registered yet (with MACHINE_STARt/END constructs) so the hooks will not run. Next commit will actually convert the platform to this infrastructure. Signed-off-by: Vineet Gupta Cc: Arnd Bergmann Acked-by: Arnd Bergmann --- arch/arc/include/asm/mach_desc.h | 85 ++++++++++++++++++++++++++++++++++++++++ arch/arc/include/asm/prom.h | 1 - arch/arc/kernel/devtree.c | 47 ++++++++++++++++++---- arch/arc/kernel/irq.c | 7 ++++ arch/arc/kernel/setup.c | 28 +++++++++++-- arch/arc/kernel/smp.c | 3 ++ arch/arc/kernel/time.c | 4 ++ arch/arc/kernel/vmlinux.lds.S | 6 +++ 8 files changed, 169 insertions(+), 12 deletions(-) create mode 100644 arch/arc/include/asm/mach_desc.h (limited to 'arch/arc/kernel/time.c') diff --git a/arch/arc/include/asm/mach_desc.h b/arch/arc/include/asm/mach_desc.h new file mode 100644 index 000000000000..eaebaf835f85 --- /dev/null +++ b/arch/arc/include/asm/mach_desc.h @@ -0,0 +1,85 @@ +/* + * Copyright (C) 2012 Synopsys, Inc. (www.synopsys.com) + * + * based on METAG mach/arch.h (which in turn was based on ARM) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _ASM_ARC_MACH_DESC_H_ +#define _ASM_ARC_MACH_DESC_H_ + +/** + * struct machine_desc - Board specific callbacks, called from ARC common code + * Provided by each ARC board using MACHINE_START()/MACHINE_END(), so + * a multi-platform kernel builds with array of such descriptors. + * We extend the early DT scan to also match the DT's "compatible" string + * against the @dt_compat of all such descriptors, and one with highest + * "DT score" is selected as global @machine_desc. + * + * @name: Board/SoC name + * @dt_compat: Array of device tree 'compatible' strings + * (XXX: although only 1st entry is looked at) + * @init_early: Very early callback [called from setup_arch()] + * @init_irq: setup external IRQ controllers [called from init_IRQ()] + * @init_smp: for each CPU (e.g. setup IPI) + * [(M):init_IRQ(), (o):start_kernel_secondary()] + * @init_time: platform specific clocksource/clockevent registration + * [called from time_init()] + * @init_machine: arch initcall level callback (e.g. populate static + * platform devices or parse Devicetree) + * @init_late: Late initcall level callback + * + */ +struct machine_desc { + const char *name; + const char **dt_compat; + + void (*init_early)(void); + void (*init_irq)(void); +#ifdef CONFIG_SMP + void (*init_smp)(unsigned int); +#endif + void (*init_time)(void); + void (*init_machine)(void); + void (*init_late)(void); + +}; + +/* + * Current machine - only accessible during boot. + */ +extern struct machine_desc *machine_desc; + +/* + * Machine type table - also only accessible during boot + */ +extern struct machine_desc __arch_info_begin[], __arch_info_end[]; +#define for_each_machine_desc(p) \ + for (p = __arch_info_begin; p < __arch_info_end; p++) + +static inline struct machine_desc *default_machine_desc(void) +{ + /* the default machine is the last one linked in */ + if (__arch_info_end - 1 < __arch_info_begin) + return NULL; + return __arch_info_end - 1; +} + +/* + * Set of macros to define architecture features. + * This is built into a table by the linker. + */ +#define MACHINE_START(_type, _name) \ +static const struct machine_desc __mach_desc_##_type \ +__used \ +__attribute__((__section__(".arch.info.init"))) = { \ + .name = _name, + +#define MACHINE_END \ +}; + +extern struct machine_desc *setup_machine_fdt(void *dt); +#endif diff --git a/arch/arc/include/asm/prom.h b/arch/arc/include/asm/prom.h index f54489bc4eca..692d0d0789a7 100644 --- a/arch/arc/include/asm/prom.h +++ b/arch/arc/include/asm/prom.h @@ -10,6 +10,5 @@ #define _ASM_ARC_PROM_H_ #define HAVE_ARCH_DEVTREE_FIXUPS -extern int __init setup_machine_fdt(void *dt); #endif diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index c8166dc02c38..a7d98b30358b 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -16,6 +16,7 @@ #include #include #include +#include /* called from unflatten_device_tree() to bootstrap devicetree itself */ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) @@ -30,27 +31,57 @@ void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align) * If a dtb was passed to the kernel, then use it to choose the correct * machine_desc and to setup the system. */ -int __init setup_machine_fdt(void *dt) +struct machine_desc * __init setup_machine_fdt(void *dt) { struct boot_param_header *devtree = dt; + struct machine_desc *mdesc = NULL, *mdesc_best = NULL; + unsigned int score, mdesc_score = ~1; unsigned long dt_root; - char *model, *compat; + const char *model, *compat; void *clk; char manufacturer[16]; unsigned long len; /* check device tree validity */ if (be32_to_cpu(devtree->magic) != OF_DT_HEADER) - return 1; + return NULL; - /* Search the mdescs for the 'best' compatible value match */ initial_boot_params = devtree; dt_root = of_get_flat_dt_root(); + /* + * The kernel could be multi-platform enabled, thus could have many + * "baked-in" machine descriptors. Search thru all for the best + * "compatible" string match. + */ + for_each_machine_desc(mdesc) { + score = of_flat_dt_match(dt_root, mdesc->dt_compat); + if (score > 0 && score < mdesc_score) { + mdesc_best = mdesc; + mdesc_score = score; + } + } + if (!mdesc_best) { + const char *prop; + long size; + + pr_err("\n unrecognized device tree list:\n[ "); + + prop = of_get_flat_dt_prop(dt_root, "compatible", &size); + if (prop) { + while (size > 0) { + printk("'%s' ", prop); + size -= strlen(prop) + 1; + prop += strlen(prop) + 1; + } + } + printk("]\n\n"); + + machine_halt(); + } + /* compat = "," */ - compat = of_get_flat_dt_prop(dt_root, "compatible", NULL); - if (!compat) - compat = ""; + compat = mdesc_best->dt_compat[0]; model = strchr(compat, ','); if (model) @@ -73,5 +104,5 @@ int __init setup_machine_fdt(void *dt) if (clk) arc_set_core_freq(of_read_ulong(clk, len/4)); - return 0; + return mdesc_best; } diff --git a/arch/arc/kernel/irq.c b/arch/arc/kernel/irq.c index df7da2b5a5bd..1198168850e8 100644 --- a/arch/arc/kernel/irq.c +++ b/arch/arc/kernel/irq.c @@ -13,6 +13,7 @@ #include #include #include +#include /* * Early Hardware specific Interrupt setup @@ -125,9 +126,15 @@ void __init init_IRQ(void) init_onchip_IRQ(); plat_init_IRQ(); + /* Any external intc can be setup here */ + if (machine_desc->init_irq) + machine_desc->init_irq(); + #ifdef CONFIG_SMP /* Master CPU can initialize it's side of IPI */ arc_platform_smp_init_cpu(); + if (machine_desc->init_smp) + machine_desc->init_smp(smp_processor_id()); #endif } diff --git a/arch/arc/kernel/setup.c b/arch/arc/kernel/setup.c index 6cc361c6751a..20273b89e545 100644 --- a/arch/arc/kernel/setup.c +++ b/arch/arc/kernel/setup.c @@ -25,12 +25,14 @@ #include #include #include +#include #define FIX_PTR(x) __asm__ __volatile__(";" : "+r"(x)) int running_on_hw = 1; /* vs. on ISS */ char __initdata command_line[COMMAND_LINE_SIZE]; +struct machine_desc *machine_desc __initdata; struct task_struct *_current_task[NR_CPUS]; /* For stack switching */ @@ -323,8 +325,6 @@ void __init __attribute__((weak)) arc_platform_early_init(void) void __init setup_arch(char **cmdline_p) { - int rc; - #ifdef CONFIG_CMDLINE_UBOOT /* Make sure that a whitespace is inserted before */ strlcat(command_line, " ", sizeof(command_line)); @@ -339,13 +339,17 @@ void __init setup_arch(char **cmdline_p) strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); *cmdline_p = command_line; - rc = setup_machine_fdt(__dtb_start); + machine_desc = setup_machine_fdt(__dtb_start); + if (!machine_desc) + panic("Embedded DT invalid\n"); /* To force early parsing of things like mem=xxx */ parse_early_param(); /* Platform/board specific: e.g. early console registration */ arc_platform_early_init(); + if (machine_desc->init_early) + machine_desc->init_early(); setup_processor(); @@ -372,6 +376,24 @@ void __init setup_arch(char **cmdline_p) arc_unwind_setup(); } +static int __init customize_machine(void) +{ + /* Add platform devices */ + if (machine_desc->init_machine) + machine_desc->init_machine(); + + return 0; +} +arch_initcall(customize_machine); + +static int __init init_late_machine(void) +{ + if (machine_desc->init_late) + machine_desc->init_late(); + + return 0; +} +late_initcall(init_late_machine); /* * Get CPU information for use by the procfs. */ diff --git a/arch/arc/kernel/smp.c b/arch/arc/kernel/smp.c index 1f762ad6969b..ea15f073452f 100644 --- a/arch/arc/kernel/smp.c +++ b/arch/arc/kernel/smp.c @@ -32,6 +32,7 @@ #include #include #include +#include arch_spinlock_t smp_atomic_ops_lock = __ARCH_SPIN_LOCK_UNLOCKED; arch_spinlock_t smp_bitops_lock = __ARCH_SPIN_LOCK_UNLOCKED; @@ -127,6 +128,8 @@ void __cpuinit start_kernel_secondary(void) pr_info("## CPU%u LIVE ##: Executing Code...\n", cpu); arc_platform_smp_init_cpu(); + if (machine_desc->init_smp) + machine_desc->init_smp(smp_processor_id()); arc_local_timer_setup(cpu); diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 05dba11fdb2d..0ce0e6f76eb0 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -43,6 +43,7 @@ #include #include #include +#include #define ARC_TIMER_MAX 0xFFFFFFFF @@ -258,6 +259,9 @@ void __init time_init(void) /* sets up the periodic event timer */ arc_local_timer_setup(smp_processor_id()); + + if (machine_desc->init_time) + machine_desc->init_time(); } #ifdef CONFIG_ARC_HAS_RTSC diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S index 8d3b0d447498..622d8b665a68 100644 --- a/arch/arc/kernel/vmlinux.lds.S +++ b/arch/arc/kernel/vmlinux.lds.S @@ -75,6 +75,12 @@ SECTIONS SECURITY_INITCALL } + .init.arch.info : { + __arch_info_begin = .; + *(.arch.info.init) + __arch_info_end = .; + } + PERCPU_SECTION(L1_CACHE_BYTES) /* -- cgit v1.2.3 From 1e266629933bb3e40ac7db128f3b661f5bab56c1 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Wed, 6 Feb 2013 15:09:13 +0530 Subject: ARC: 64bit RTSC timestamp hardware issue The 64bit RTSC is not reliable, causing spurious "jumps" in higher word, making Linux timekeeping go bonkers. So as of now just use the lower 32bit timestamp. A cleaner approach would have been removing RTSC support altogether as the 32bit RTSC is equivalent to old TIMER1 based solution, but some customers can use the 32bit RTSC in SMP syn fashion (vs. TIMER1 which being incore can't be done easily). A fallout of this is sched_clock()'s hardware assisted version needs to go away since it can't use 32bit wrapping counter - instead we use the generic "weak" jiffies based version. Signed-off-by: Vineet Gupta --- arch/arc/kernel/time.c | 38 ++------------------------------------ 1 file changed, 2 insertions(+), 36 deletions(-) (limited to 'arch/arc/kernel/time.c') diff --git a/arch/arc/kernel/time.c b/arch/arc/kernel/time.c index 0ce0e6f76eb0..f13f72807aa5 100644 --- a/arch/arc/kernel/time.c +++ b/arch/arc/kernel/time.c @@ -76,7 +76,7 @@ static cycle_t arc_counter_read(struct clocksource *cs) __asm__ __volatile( " .extCoreRegister tsch, 58, r, cannot_shortcut \n" " rtsc %0, 0 \n" - " mov %1, tsch \n" /* TSCH is extn core reg 58 */ + " mov %1, 0 \n" : "=r" (stamp.low), "=r" (stamp.high)); arch_local_irq_restore(flags); @@ -88,7 +88,7 @@ static struct clocksource arc_counter = { .name = "ARC RTSC", .rating = 300, .read = arc_counter_read, - .mask = CLOCKSOURCE_MASK(64), + .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; @@ -263,37 +263,3 @@ void __init time_init(void) if (machine_desc->init_time) machine_desc->init_time(); } - -#ifdef CONFIG_ARC_HAS_RTSC -/* - * sched_clock math assist - * ns = cycles * (ns_per_sec / cpu_freq_hz) - * ns = cycles * (10^6 / cpu_freq_khz) - * ns = cycles * (10^6 * 2^SF / cpu_freq_khz) / 2^SF - * ns = cycles * cyc2ns_scale >> SF - */ -#define CYC2NS_SF 10 /* 2^10, carefully chosen */ -#define CYC2NS_SCALE ((1000000 << CYC2NS_SF) / (arc_get_core_freq() / 1000)) - -static unsigned long long cycles2ns(unsigned long long cyc) -{ - return (cyc * CYC2NS_SCALE ) >> CYC2NS_SF; -} - -/* - * Scheduler clock - a monotonically increasing clock in nanosec units. - * It's return value must NOT wrap around. - * - * - Since 32bit TIMER1 will overflow almost immediately (53sec @ 80MHz), it - * can't be used directly. - * - Using getrawmonotonic (TIMER1 based, but with state for last + current - * snapshots), is no-good either because of seqlock deadlock possibilities - * - So only with native 64bit timer we do this, otherwise fallback to generic - * jiffies based version - which despite not being fine grained gaurantees - * the monotonically increasing semantics. - */ -unsigned long long sched_clock(void) -{ - return cycles2ns(arc_counter_read(NULL)); -} -#endif -- cgit v1.2.3