From fe87414f71d0035756cf91a80ac256557d16b488 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Wed, 12 Mar 2014 18:33:45 +0200 Subject: ARM: OMAP2+: PRCM: split PRCM module init to their own driver files Splits the clock related provider module inits under their own driver files. Previously this was done for all modules under the common PRM driver. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 47 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index da041b4ab29c..e8818242f968 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -14,6 +14,7 @@ #include #include +#include #include "soc.h" #include "iomap.h" @@ -25,6 +26,7 @@ #include "sdrc.h" #include "pm.h" #include "control.h" +#include "clock.h" /* Used by omap3_ctrl_save_padconf() */ #define START_PADCONF_SAVE 0x2 @@ -611,3 +613,48 @@ void __init omap3_ctrl_init(void) omap3_ctrl_setup_d2d_padconf(); } #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ + +struct control_init_data { + int index; +}; + +static struct control_init_data ctrl_data = { + .index = TI_CLKM_CTRL, +}; + +static const struct of_device_id omap_scrm_dt_match_table[] = { + { .compatible = "ti,am3-scrm", .data = &ctrl_data }, + { .compatible = "ti,am4-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap2-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap3-scrm", .data = &ctrl_data }, + { } +}; + +/** + * omap_control_init - low level init for the control driver + * + * Initializes the low level clock infrastructure for control driver. + * Returns 0 in success, negative error value in failure. + */ +int __init omap_control_init(void) +{ + struct device_node *np; + void __iomem *mem; + const struct of_device_id *match; + const struct omap_prcm_init_data *data; + int ret; + + for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { + data = match->data; + + mem = of_iomap(np, 0); + if (!mem) + return -ENOMEM; + + ret = omap2_clk_provider_init(np, data->index, mem); + if (ret) + return ret; + } + + return 0; +} -- cgit v1.2.3 From 2208bf115fecae211480ea41d25e6d56ec20d405 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 13 Nov 2014 19:17:34 +0200 Subject: ARM: OMAP2+: control: determine control module base address from DT There is no need to provide the control module base address through a low-level API from the low-level IO init, as this information is available through DT. This patch adds a new API to initialize the control module though, but mostly makes the old API obsolete. The old API can be completely removed once OMAP3 is made DT only. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 49 +++++++++++++++++++++++++++++++++++----- arch/arm/mach-omap2/control.h | 2 ++ arch/arm/mach-omap2/io.c | 34 +++++++++++++--------------- arch/arm/mach-omap2/prm.h | 1 - arch/arm/mach-omap2/prm_common.c | 5 ---- 5 files changed, 61 insertions(+), 30 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index e8818242f968..21ff32c6001a 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -616,6 +616,7 @@ void __init omap3_ctrl_init(void) struct control_init_data { int index; + void __iomem *mem; }; static struct control_init_data ctrl_data = { @@ -627,9 +628,38 @@ static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,am4-scrm", .data = &ctrl_data }, { .compatible = "ti,omap2-scrm", .data = &ctrl_data }, { .compatible = "ti,omap3-scrm", .data = &ctrl_data }, + { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, { } }; +/** + * omap2_control_base_init - initialize iomappings for the control driver + * + * Detects and initializes the iomappings for the control driver, based + * on the DT data. Returns 0 in success, negative error value + * otherwise. + */ +int __init omap2_control_base_init(void) +{ + struct device_node *np; + const struct of_device_id *match; + struct control_init_data *data; + void __iomem *mem; + + for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { + data = (struct control_init_data *)match->data; + + mem = of_iomap(np, 0); + if (!mem) + return -ENOMEM; + + omap2_ctrl_base = mem; + data->mem = mem; + } + + return 0; +} + /** * omap_control_init - low level init for the control driver * @@ -639,7 +669,6 @@ static const struct of_device_id omap_scrm_dt_match_table[] = { int __init omap_control_init(void) { struct device_node *np; - void __iomem *mem; const struct of_device_id *match; const struct omap_prcm_init_data *data; int ret; @@ -647,14 +676,22 @@ int __init omap_control_init(void) for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { data = match->data; - mem = of_iomap(np, 0); - if (!mem) - return -ENOMEM; - - ret = omap2_clk_provider_init(np, data->index, mem); + ret = omap2_clk_provider_init(np, data->index, data->mem); if (ret) return ret; } return 0; } + +/** + * omap3_control_legacy_iomap_init - legacy iomap init for clock providers + * + * Legacy iomap init for clock provider. Needed only by legacy boot mode, + * where the base addresses are not parsed from DT, but still required + * by the clock driver to be setup properly. + */ +void __init omap3_control_legacy_iomap_init(void) +{ + omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap2_ctrl_base); +} diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index baf5783cb05d..c1057eb9d4e4 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -464,9 +464,11 @@ extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); extern void omap3630_ctrl_disable_rta(void); extern int omap3_ctrl_save_padconf(void); void omap3_ctrl_init(void); +int omap2_control_base_init(void); int omap_control_init(void); extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); +void __init omap3_control_legacy_iomap_init(void); #else #define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 712dd42bb5c2..622ee3bddd32 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -384,8 +384,7 @@ void __init omap2420_init_early(void) omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE), - NULL); + omap2_control_base_init(); omap2xxx_check_revision(); omap2xxx_prm_init(); omap2xxx_cm_init(); @@ -412,8 +411,7 @@ void __init omap2430_init_early(void) omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), - NULL); + omap2_control_base_init(); omap2xxx_check_revision(); omap2xxx_prm_init(); omap2xxx_cm_init(); @@ -444,11 +442,15 @@ void __init omap3_init_early(void) omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); omap2_set_globals_sdrc(OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), - NULL); - /* XXX: remove these two once OMAP3 is DT only */ - omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); - omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); + /* XXX: remove these once OMAP3 is DT only */ + if (!of_have_populated_dt()) { + omap2_set_globals_control( + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL); + omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); + omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), + NULL); + } + omap2_control_base_init(); omap3xxx_check_revision(); omap3xxx_check_features(); omap3xxx_prm_init(); @@ -459,7 +461,7 @@ void __init omap3_init_early(void) omap3xxx_hwmod_init(); omap_hwmod_init_postsetup(); if (!of_have_populated_dt()) { - omap3_prcm_legacy_iomaps_init(); + omap3_control_legacy_iomap_init(); if (soc_is_am35xx()) omap_clk_soc_init = am35xx_clk_legacy_init; else if (cpu_is_omap3630()) @@ -546,8 +548,7 @@ void __init ti814x_init_early(void) { omap2_set_globals_tap(TI814X_CLASS, OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), - NULL); + omap2_control_base_init(); omap3xxx_check_revision(); ti81xx_check_features(); am33xx_prm_init(); @@ -565,8 +566,7 @@ void __init ti816x_init_early(void) { omap2_set_globals_tap(TI816X_CLASS, OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(TI81XX_CTRL_BASE), - NULL); + omap2_control_base_init(); omap3xxx_check_revision(); ti81xx_check_features(); am33xx_prm_init(); @@ -586,8 +586,7 @@ void __init am33xx_init_early(void) { omap2_set_globals_tap(AM335X_CLASS, AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); - omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), - NULL); + omap2_control_base_init(); omap3xxx_check_revision(); am33xx_check_features(); am33xx_prm_init(); @@ -610,8 +609,7 @@ void __init am43xx_init_early(void) { omap2_set_globals_tap(AM335X_CLASS, AM33XX_L4_WK_IO_ADDRESS(AM33XX_TAP_BASE)); - omap2_set_globals_control(AM33XX_L4_WK_IO_ADDRESS(AM33XX_CTRL_BASE), - NULL); + omap2_control_base_init(); omap3xxx_check_revision(); am33xx_check_features(); omap44xx_prm_init(); diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 6d0a808f33f7..670733365287 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -21,7 +21,6 @@ extern u16 prm_features; extern void omap2_set_globals_prm(void __iomem *prm); int omap_prcm_init(void); int omap2_prm_base_init(void); -void omap3_prcm_legacy_iomaps_init(void); # endif /* diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index b23d2327bafe..a943e1447536 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -722,11 +722,6 @@ int __init omap_prcm_init(void) return 0; } -void __init omap3_prcm_legacy_iomaps_init(void) -{ - omap2_clk_legacy_provider_init(TI_CLKM_SCRM, omap_ctrl_base_get()); -} - static int __init prm_late_init(void) { if (prm_ll_data->late_init) -- cgit v1.2.3 From 80cbb224b789d256ad5cb36b0af3e5c04ed46bca Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 6 Feb 2015 16:00:32 +0200 Subject: ARM: OMAP2+: clock: add low-level support for regmap Some of the TI clock providers will be converted to use syscon, thus low-level regmap support is needed for the clock drivers also. This patch adds this support, which can be enabled for individual drivers in later patches. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/clock.c | 48 ++++++++++++++++++++++++++++++++++------ arch/arm/mach-omap2/clock.h | 4 +++- arch/arm/mach-omap2/cm_common.c | 2 +- arch/arm/mach-omap2/control.c | 2 +- arch/arm/mach-omap2/prm_common.c | 2 +- 5 files changed, 47 insertions(+), 11 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 94080fba02f6..a699d7169307 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -23,7 +23,9 @@ #include #include #include +#include #include +#include #include #include @@ -73,20 +75,37 @@ struct ti_clk_features ti_clk_features; static bool clkdm_control = true; static LIST_HEAD(clk_hw_omap_clocks); -static void __iomem *clk_memmaps[CLK_MAX_MEMMAPS]; + +struct clk_iomap { + struct regmap *regmap; + void __iomem *mem; +}; + +static struct clk_iomap *clk_memmaps[CLK_MAX_MEMMAPS]; static void clk_memmap_writel(u32 val, void __iomem *reg) { struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; - writel_relaxed(val, clk_memmaps[r->index] + r->offset); + if (io->regmap) + regmap_write(io->regmap, r->offset, val); + else + writel_relaxed(val, io->mem + r->offset); } static u32 clk_memmap_readl(void __iomem *reg) { + u32 val; struct clk_omap_reg *r = (struct clk_omap_reg *)® + struct clk_iomap *io = clk_memmaps[r->index]; - return readl_relaxed(clk_memmaps[r->index] + r->offset); + if (io->regmap) + regmap_read(io->regmap, r->offset, &val); + else + val = readl_relaxed(io->mem + r->offset); + + return val; } void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg) @@ -115,18 +134,27 @@ static struct ti_clk_ll_ops omap_clk_ll_ops = { * @match_table: DT device table to match for devices to init * @np: device node pointer for the this clock provider * @index: index for the clock provider - * @mem: iomem pointer for the clock provider memory area + + @syscon: syscon regmap pointer + * @mem: iomem pointer for the clock provider memory area, only used if + * syscon is not provided * * Initializes a clock provider module (CM/PRM etc.), registering * the memory mapping at specified index and initializing the * low level driver infrastructure. Returns 0 in success. */ int __init omap2_clk_provider_init(struct device_node *np, int index, - void __iomem *mem) + struct regmap *syscon, void __iomem *mem) { + struct clk_iomap *io; + ti_clk_ll_ops = &omap_clk_ll_ops; - clk_memmaps[index] = mem; + io = kzalloc(sizeof(*io), GFP_KERNEL); + + io->regmap = syscon; + io->mem = mem; + + clk_memmaps[index] = io; ti_dt_clk_init_provider(np, index); @@ -142,9 +170,15 @@ int __init omap2_clk_provider_init(struct device_node *np, int index, */ void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem) { + struct clk_iomap *io; + ti_clk_ll_ops = &omap_clk_ll_ops; - clk_memmaps[index] = mem; + io = memblock_virt_alloc(sizeof(*io), 0); + + io->mem = mem; + + clk_memmaps[index] = io; } /* diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index b6433fc284ce..652ed0ab86ec 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h @@ -274,8 +274,10 @@ extern const struct clksel_rate div31_1to31_rates[]; extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); +struct regmap; + int __init omap2_clk_provider_init(struct device_node *np, int index, - void __iomem *mem); + struct regmap *syscon, void __iomem *mem); void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem); void __init ti_clk_init_features(void); diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c index ff24fdfb3bb2..23e8bcec34e3 100644 --- a/arch/arm/mach-omap2/cm_common.c +++ b/arch/arm/mach-omap2/cm_common.c @@ -361,7 +361,7 @@ int __init omap_cm_init(void) if (data->flags & CM_NO_CLOCKS) continue; - ret = omap2_clk_provider_init(np, data->index, data->mem); + ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); if (ret) return ret; } diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 21ff32c6001a..4b4094685087 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -676,7 +676,7 @@ int __init omap_control_init(void) for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { data = match->data; - ret = omap2_clk_provider_init(np, data->index, data->mem); + ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); if (ret) return ret; } diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c index 6832a31e9a70..7add7994dbfc 100644 --- a/arch/arm/mach-omap2/prm_common.c +++ b/arch/arm/mach-omap2/prm_common.c @@ -798,7 +798,7 @@ int __init omap_prcm_init(void) for_each_matching_node_and_match(np, omap_prcm_dt_match_table, &match) { data = match->data; - ret = omap2_clk_provider_init(np, data->index, data->mem); + ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); if (ret) return ret; } -- cgit v1.2.3 From ae0f6798474053eb76863fa9b3befd9deea58ba6 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 6 Feb 2015 16:20:13 +0200 Subject: ARM: OMAP2+: control: remove API for getting control module base address This shall not be used anymore, as control module driver is converted into using regmap. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 5 ----- arch/arm/mach-omap2/control.h | 2 -- 2 files changed, 7 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 4b4094685087..202fc725426b 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -145,11 +145,6 @@ void __init omap2_set_globals_control(void __iomem *ctrl, omap4_ctrl_pad_base = ctrl_pad; } -void __iomem *omap_ctrl_base_get(void) -{ - return omap2_ctrl_base; -} - u8 omap_ctrl_readb(u16 offset) { return readb_relaxed(OMAP_CTRL_REGADDR(offset)); diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index c1057eb9d4e4..5353ff45bf83 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -440,7 +440,6 @@ #ifndef __ASSEMBLY__ #ifdef CONFIG_ARCH_OMAP2PLUS -extern void __iomem *omap_ctrl_base_get(void); extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); @@ -470,7 +469,6 @@ extern void omap2_set_globals_control(void __iomem *ctrl, void __iomem *ctrl_pad); void __init omap3_control_legacy_iomap_init(void); #else -#define omap_ctrl_base_get() 0 #define omap_ctrl_readb(x) 0 #define omap_ctrl_readw(x) 0 #define omap_ctrl_readl(x) 0 -- cgit v1.2.3 From e5b635742e9824c8c0fc7fc524a24024cf88a448 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Feb 2015 11:24:11 +0200 Subject: ARM: OMAP2+: control: add syscon support for register accesses Control module driver needs to support syscon for register accesses, as the DT hierarchy for control module driver is going to be changed. All the control module related features will be moved under control module node, including clocks, pinctrl, and generic configuration register access. Temporary iomap is still provided very early in the boot for access while syscon is not yet ready. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 104 +++++++++++++++++++++++++++++++++++------- 1 file changed, 87 insertions(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 202fc725426b..4970c5cb1a11 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include #include "soc.h" #include "iomap.h" @@ -33,7 +35,9 @@ #define PADCONF_SAVE_DONE 0x1 static void __iomem *omap2_ctrl_base; +static s16 omap2_ctrl_offset; static void __iomem *omap4_ctrl_pad_base; +static struct regmap *omap2_ctrl_syscon; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) struct omap3_scratchpad { @@ -135,7 +139,6 @@ struct omap3_control_regs { static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ -#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg)) #define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) void __init omap2_set_globals_control(void __iomem *ctrl, @@ -147,32 +150,72 @@ void __init omap2_set_globals_control(void __iomem *ctrl, u8 omap_ctrl_readb(u16 offset) { - return readb_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + u8 byte_offset = offset & 0x3; + + val = omap_ctrl_readl(offset); + + return (val >> (byte_offset * 8)) & 0xff; } u16 omap_ctrl_readw(u16 offset) { - return readw_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + u16 byte_offset = offset & 0x2; + + val = omap_ctrl_readl(offset); + + return (val >> (byte_offset * 8)) & 0xffff; } u32 omap_ctrl_readl(u16 offset) { - return readl_relaxed(OMAP_CTRL_REGADDR(offset)); + u32 val; + + offset &= 0xfffc; + if (!omap2_ctrl_syscon) + val = readl_relaxed(omap2_ctrl_base + offset); + else + regmap_read(omap2_ctrl_syscon, omap2_ctrl_offset + offset, + &val); + + return val; } void omap_ctrl_writeb(u8 val, u16 offset) { - writeb_relaxed(val, OMAP_CTRL_REGADDR(offset)); + u32 tmp; + u8 byte_offset = offset & 0x3; + + tmp = omap_ctrl_readl(offset); + + tmp &= 0xffffffff ^ (0xff << (byte_offset * 8)); + tmp |= val << (byte_offset * 8); + + omap_ctrl_writel(tmp, offset); } void omap_ctrl_writew(u16 val, u16 offset) { - writew_relaxed(val, OMAP_CTRL_REGADDR(offset)); + u32 tmp; + u8 byte_offset = offset & 0x2; + + tmp = omap_ctrl_readl(offset); + + tmp &= 0xffffffff ^ (0xffff << (byte_offset * 8)); + tmp |= val << (byte_offset * 8); + + omap_ctrl_writel(tmp, offset); } void omap_ctrl_writel(u32 val, u16 offset) { - writel_relaxed(val, OMAP_CTRL_REGADDR(offset)); + offset &= 0xfffc; + if (!omap2_ctrl_syscon) + writel_relaxed(val, omap2_ctrl_base + offset); + else + regmap_write(omap2_ctrl_syscon, omap2_ctrl_offset + offset, + val); } /* @@ -611,7 +654,7 @@ void __init omap3_ctrl_init(void) struct control_init_data { int index; - void __iomem *mem; + s16 offset; }; static struct control_init_data ctrl_data = { @@ -639,17 +682,15 @@ int __init omap2_control_base_init(void) struct device_node *np; const struct of_device_id *match; struct control_init_data *data; - void __iomem *mem; for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { data = (struct control_init_data *)match->data; - mem = of_iomap(np, 0); - if (!mem) + omap2_ctrl_base = of_iomap(np, 0); + if (!omap2_ctrl_base) return -ENOMEM; - omap2_ctrl_base = mem; - data->mem = mem; + omap2_ctrl_offset = data->offset; } return 0; @@ -663,17 +704,46 @@ int __init omap2_control_base_init(void) */ int __init omap_control_init(void) { - struct device_node *np; + struct device_node *np, *scm_conf; const struct of_device_id *match; const struct omap_prcm_init_data *data; int ret; + struct regmap *syscon; for_each_matching_node_and_match(np, omap_scrm_dt_match_table, &match) { data = match->data; - ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); - if (ret) - return ret; + /* + * Check if we have scm_conf node, if yes, use this to + * access clock registers. + */ + scm_conf = of_get_child_by_name(np, "scm_conf"); + + if (scm_conf) { + syscon = syscon_node_to_regmap(scm_conf); + + if (IS_ERR(syscon)) + return PTR_ERR(syscon); + + omap2_ctrl_syscon = syscon; + + if (of_get_child_by_name(scm_conf, "clocks")) { + ret = omap2_clk_provider_init(scm_conf, + data->index, + syscon, NULL); + if (ret) + return ret; + } + + iounmap(omap2_ctrl_base); + omap2_ctrl_base = NULL; + } else { + /* No scm_conf found, direct access */ + ret = omap2_clk_provider_init(np, data->index, NULL, + omap2_ctrl_base); + if (ret) + return ret; + } } return 0; -- cgit v1.2.3 From 72b10ac00eb1c154037e398371685d3f1d2d4793 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Feb 2015 10:38:16 +0200 Subject: ARM: dts: omap24xx: add minimal l4 bus layout with control module support This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430 SoCs, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the new SCM node as the clock provider. Signed-off-by: Tero Kristo --- Documentation/devicetree/bindings/arm/omap/l4.txt | 17 ++++ .../devicetree/bindings/arm/omap/prcm.txt | 2 +- arch/arm/boot/dts/omap2420.dtsi | 80 +++++++++------ arch/arm/boot/dts/omap2430-clocks.dtsi | 8 +- arch/arm/boot/dts/omap2430.dtsi | 107 ++++++++++++--------- arch/arm/boot/dts/omap24xx-clocks.dtsi | 6 +- arch/arm/mach-omap2/control.c | 7 +- 7 files changed, 140 insertions(+), 87 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/omap/l4.txt (limited to 'arch/arm/mach-omap2/control.c') diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt new file mode 100644 index 000000000000..57569cc8df16 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -0,0 +1,17 @@ +L4 interconnect bindings + +These bindings describe the OMAP SoCs L4 interconnect bus. + +Required properties: +- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus + Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus +- ranges : contains the IO map range for the bus + +Examples: + +l4: l4@48000000 { + compatible "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; +}; diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index 68f96f8d3947..cce8365b66e8 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -14,7 +14,7 @@ Required properties: "ti,am4-prcm" "ti,am4-scrm" "ti,omap2-prcm" - "ti,omap2-scrm" + "ti,omap2-scm" "ti,omap3-prm" "ti,omap3-cm" "ti,omap3-scrm" diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index e2b2e93d7b61..5b9a376cc31e 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -14,47 +14,65 @@ compatible = "ti,omap2420", "ti,omap2"; ocp { - prcm: prcm@48008000 { - compatible = "ti,omap2-prcm"; - reg = <0x48008000 0x1000>; + l4: l4@48000000 { + compatible = "ti,omap2-l4", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x100000>; - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + prcm: prcm@8000 { + compatible = "ti,omap2-prcm"; + reg = <0x8000 0x1000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm: scrm@48000000 { - compatible = "ti,omap2-scrm"; - reg = <0x48000000 0x1000>; + prcm_clockdomains: clockdomains { + }; + }; - scrm_clocks: clocks { + scm: scm@0 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x0 0x1000>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; + ranges = <0 0x0 0x1000>; + + omap2420_pmx: pinmux@30 { + compatible = "ti,omap2420-padconf", + "pinctrl-single"; + reg = <0x30 0x0113>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x100>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + counter32k: counter@4000 { + compatible = "ti,omap-counter32k"; + reg = <0x4000 0x20>; + ti,hwmods = "counter_32k"; }; }; - counter32k: counter@48004000 { - compatible = "ti,omap-counter32k"; - reg = <0x48004000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2420_pmx: pinmux@48000030 { - compatible = "ti,omap2420-padconf", "pinctrl-single"; - reg = <0x48000030 0x0113>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - gpio1: gpio@48018000 { compatible = "ti,omap2-gpio"; reg = <0x48018000 0x200>; diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi index 805f75df1cf2..93fed68839b9 100644 --- a/arch/arm/boot/dts/omap2430-clocks.dtsi +++ b/arch/arm/boot/dts/omap2430-clocks.dtsi @@ -8,12 +8,12 @@ * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp3_mux_fck: mcbsp3_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp3_fck: mcbsp3_fck { @@ -27,7 +27,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp4_fck: mcbsp4_fck { @@ -41,7 +41,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02e8>; + reg = <0x78>; }; mcbsp5_fck: mcbsp5_fck { diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 0dc8de2782b1..11a7963be003 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -14,60 +14,73 @@ compatible = "ti,omap2430", "ti,omap2"; ocp { - prcm: prcm@49006000 { - compatible = "ti,omap2-prcm"; - reg = <0x49006000 0x1000>; + l4_wkup: l4_wkup@49000000 { + compatible = "ti,omap2-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x49000000 0x31000>; - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + prcm: prcm@6000 { + compatible = "ti,omap2-prcm"; + reg = <0x6000 0x1000>; - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@49002000 { - compatible = "ti,omap2-scrm"; - reg = <0x49002000 0x1000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@2000 { + compatible = "ti,omap2-scm", "simple-bus"; + reg = <0x2000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x1000>; + + omap2430_pmx: pinmux@30 { + compatible = "ti,omap2430-padconf", + "pinctrl-single"; + reg = <0x30 0x0154>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <8>; + pinctrl-single,function-mask = <0x3f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x240>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + + pbias_regulator: pbias_regulator { + compatible = "ti,pbias-omap"; + reg = <0x230 0x4>; + syscon = <&scm_conf>; + pbias_mmc_reg: pbias_mmc_omap2430 { + regulator-name = "pbias_mmc_omap2430"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + }; + }; + + scm_clockdomains: clockdomains { + }; }; - }; - - counter32k: counter@49020000 { - compatible = "ti,omap-counter32k"; - reg = <0x49020000 0x20>; - ti,hwmods = "counter_32k"; - }; - - omap2430_pmx: pinmux@49002030 { - compatible = "ti,omap2430-padconf", "pinctrl-single"; - reg = <0x49002030 0x0154>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <8>; - pinctrl-single,function-mask = <0x3f>; - }; - - omap2_scm_general: tisyscon@49002270 { - compatible = "syscon"; - reg = <0x49002270 0x240>; - }; - pbias_regulator: pbias_regulator { - compatible = "ti,pbias-omap"; - reg = <0x230 0x4>; - syscon = <&omap2_scm_general>; - pbias_mmc_reg: pbias_mmc_omap2430 { - regulator-name = "pbias_mmc_omap2430"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3000000>; + counter32k: counter@20000 { + compatible = "ti,omap-counter32k"; + reg = <0x20000 0x20>; + ti,hwmods = "counter_32k"; }; }; diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi index a1365ca926eb..63965b876973 100644 --- a/arch/arm/boot/dts/omap24xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi @@ -7,13 +7,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { mcbsp1_mux_fck: mcbsp1_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp1_fck: mcbsp1_fck { @@ -27,7 +27,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&func_96m_ck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x4>; }; mcbsp2_fck: mcbsp2_fck { diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 4970c5cb1a11..eb592ea51b78 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -661,10 +661,15 @@ static struct control_init_data ctrl_data = { .index = TI_CLKM_CTRL, }; +static const struct control_init_data omap2_ctrl_data = { + .index = TI_CLKM_CTRL, + .offset = -OMAP2_CONTROL_GENERAL, +}; + static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,am3-scrm", .data = &ctrl_data }, { .compatible = "ti,am4-scrm", .data = &ctrl_data }, - { .compatible = "ti,omap2-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,omap3-scrm", .data = &ctrl_data }, { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, { } -- cgit v1.2.3 From b8845074cfbbd1d1b46720a1b563d7b4240dac21 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Tue, 24 Feb 2015 16:22:45 +0200 Subject: ARM: dts: omap3: add minimal l4 bus layout with control module support This patch creates an l4_core interconnect for OMAP3, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by: Tero Kristo Reported-by: Tony Lindgren --- Documentation/devicetree/bindings/arm/omap/l4.txt | 1 + .../devicetree/bindings/arm/omap/prcm.txt | 2 +- arch/arm/boot/dts/am3517.dtsi | 2 +- arch/arm/boot/dts/am35xx-clocks.dtsi | 2 +- arch/arm/boot/dts/omap3.dtsi | 96 +++++++++++++--------- arch/arm/boot/dts/omap3xxx-clocks.dtsi | 13 +-- arch/arm/mach-omap2/control.c | 2 +- 7 files changed, 67 insertions(+), 51 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index 57569cc8df16..64020220024d 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -5,6 +5,7 @@ These bindings describe the OMAP SoCs L4 interconnect bus. Required properties: - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus + Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus - ranges : contains the IO map range for the bus Examples: diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index cce8365b66e8..ef5a74be6148 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -17,7 +17,7 @@ Required properties: "ti,omap2-scm" "ti,omap3-prm" "ti,omap3-cm" - "ti,omap3-scrm" + "ti,omap3-scm" "ti,omap4-cm1" "ti,omap4-prm" "ti,omap4-cm2" diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi index c90724bded10..f164dce08755 100644 --- a/arch/arm/boot/dts/am3517.dtsi +++ b/arch/arm/boot/dts/am3517.dtsi @@ -31,7 +31,7 @@ status = "disabled"; reg = <0x5c000000 0x30000>; interrupts = <67 68 69 70>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; ti,davinci-ctrl-reg-offset = <0x10000>; ti,davinci-ctrl-mod-reg-offset = <0>; ti,davinci-ctrl-ram-offset = <0x20000>; diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi index df489d310b50..518b8fde88b0 100644 --- a/arch/arm/boot/dts/am35xx-clocks.dtsi +++ b/arch/arm/boot/dts/am35xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { emac_ick: emac_ick { #clock-cells = <0>; compatible = "ti,am35xx-gate-clock"; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 01b71111bd55..b28791ade27a 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -87,6 +87,60 @@ ranges; ti,hwmods = "l3_main"; + l4_core: l4@48000000 { + compatible = "ti,omap3-l4-core", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x48000000 0x1000000>; + + scm: scm@2000 { + compatible = "ti,omap3-scm", "simple-bus"; + reg = <0x2000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2000 0x2000>; + + omap3_pmx_core: pinmux@30 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0x30 0x238>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + + scm_conf: scm_conf@270 { + compatible = "syscon"; + reg = <0x270 0x330>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; + + omap3_pmx_wkup: pinmux@a00 { + compatible = "ti,omap3-padconf", + "pinctrl-single"; + reg = <0xa00 0x5c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <16>; + pinctrl-single,function-mask = <0xff1f>; + }; + }; + }; + aes: aes@480c5000 { compatible = "ti,omap3-aes"; ti,hwmods = "aes"; @@ -121,19 +175,6 @@ }; }; - scrm: scrm@48002000 { - compatible = "ti,omap3-scrm"; - reg = <0x48002000 0x2000>; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - counter32k: counter@48320000 { compatible = "ti,omap-counter32k"; reg = <0x48320000 0x20>; @@ -159,37 +200,10 @@ #dma-requests = <96>; }; - omap3_pmx_core: pinmux@48002030 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002030 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_pmx_wkup: pinmux@48002a00 { - compatible = "ti,omap3-padconf", "pinctrl-single"; - reg = <0x48002a00 0x5c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xff1f>; - }; - - omap3_scm_general: tisyscon@48002270 { - compatible = "syscon"; - reg = <0x48002270 0x2f0>; - }; - pbias_regulator: pbias_regulator { compatible = "ti,pbias-omap"; reg = <0x2b0 0x4>; - syscon = <&omap3_scm_general>; + syscon = <&scm_conf>; pbias_mmc_reg: pbias_mmc_omap2430 { regulator-name = "pbias_mmc_omap2430"; regulator-min-microvolt = <1800000>; diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi index 5c375003bad1..bbba5bdc4bc9 100644 --- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi +++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi @@ -79,13 +79,14 @@ clock-div = <1>; }; }; -&scrm_clocks { + +&scm_clocks { mcbsp5_mux_fck: mcbsp5_mux_fck { #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <4>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp5_fck: mcbsp5_fck { @@ -99,7 +100,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&core_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp1_fck: mcbsp1_fck { @@ -113,7 +114,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <6>; - reg = <0x0274>; + reg = <0x04>; }; mcbsp2_fck: mcbsp2_fck { @@ -126,7 +127,7 @@ #clock-cells = <0>; compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp3_fck: mcbsp3_fck { @@ -140,7 +141,7 @@ compatible = "ti,composite-mux-clock"; clocks = <&per_96m_fck>, <&mcbsp_clks>; ti,bit-shift = <2>; - reg = <0x02d8>; + reg = <0x68>; }; mcbsp4_fck: mcbsp4_fck { diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index eb592ea51b78..30f5aff7645f 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -670,7 +670,7 @@ static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,am3-scrm", .data = &ctrl_data }, { .compatible = "ti,am4-scrm", .data = &ctrl_data }, { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, - { .compatible = "ti,omap3-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, { } }; -- cgit v1.2.3 From e3bc5358e0977b95652625f9329ba68f1ebb1a42 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 20 Mar 2015 13:08:29 +0200 Subject: ARM: dts: am33xx: add minimal l4 bus layout with control module support This patch creates an l4_wkup interconnect for AM33xx, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by: Tero Kristo --- Documentation/devicetree/bindings/arm/omap/l4.txt | 1 + .../devicetree/bindings/arm/omap/prcm.txt | 2 +- arch/arm/boot/dts/am33xx-clocks.dtsi | 2 +- arch/arm/boot/dts/am33xx.dtsi | 87 ++++++++++++---------- arch/arm/mach-omap2/control.c | 2 +- 5 files changed, 51 insertions(+), 43 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index 64020220024d..d333f0a9044e 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -6,6 +6,7 @@ Required properties: - compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus + Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus - ranges : contains the IO map range for the bus Examples: diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index ef5a74be6148..c8e202763be8 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -10,7 +10,7 @@ documentation about the individual clock/clockdomain nodes. Required properties: - compatible: Must be one of: "ti,am3-prcm" - "ti,am3-scrm" + "ti,am3-scm" "ti,am4-prcm" "ti,am4-scrm" "ti,omap2-prcm" diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi index 712edce7d6fb..236c78a3c6ca 100644 --- a/arch/arm/boot/dts/am33xx-clocks.dtsi +++ b/arch/arm/boot/dts/am33xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index acd37057bca9..21fcc440fc1a 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -83,20 +83,6 @@ }; }; - am33xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7fc>; - }; - - am33xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; - reg = <0x44e10800 0x0238>; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0x7f>; - }; - /* * XXX: Use a flat representation of the AM33XX interconnect. * The real AM33XX interconnect network is quite complex. Since @@ -111,37 +97,58 @@ ranges; ti,hwmods = "l3_main"; - prcm: prcm@44e00000 { - compatible = "ti,am3-prcm"; - reg = <0x44e00000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am3-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x280000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm: prcm@200000 { + compatible = "ti,am3-prcm"; + reg = <0x200000 0x4000>; - scrm: scrm@44e10000 { - compatible = "ti,am3-scrm"; - reg = <0x44e10000 0x2000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@210000 { + compatible = "ti,am3-scm", "simple-bus"; + reg = <0x210000 0x2000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x2000>; + + am33xx_pinmux: pinmux@800 { + compatible = "pinctrl-single"; + reg = <0x800 0x238>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x7f>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; }; - cm: syscon@44e10000 { - compatible = "ti,am33xx-controlmodule", "syscon"; - reg = <0x44e10000 0x800>; - }; - intc: interrupt-controller@48200000 { compatible = "ti,am33xx-intc"; interrupt-controller; @@ -350,7 +357,7 @@ reg = <0x481cc000 0x2000>; clocks = <&dcan0_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = <52>; status = "disabled"; }; @@ -361,7 +368,7 @@ reg = <0x481d0000 0x2000>; clocks = <&dcan1_fck>; clock-names = "fck"; - syscon-raminit = <&am33xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = <55>; status = "disabled"; }; @@ -720,7 +727,7 @@ */ interrupts = <40 41 42 43>; ranges; - syscon = <&cm>; + syscon = <&scm_conf>; status = "disabled"; davinci_mdio: mdio@4a101000 { diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 30f5aff7645f..477e2c8f26a6 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -667,7 +667,7 @@ static const struct control_init_data omap2_ctrl_data = { }; static const struct of_device_id omap_scrm_dt_match_table[] = { - { .compatible = "ti,am3-scrm", .data = &ctrl_data }, + { .compatible = "ti,am3-scm", .data = &ctrl_data }, { .compatible = "ti,am4-scrm", .data = &ctrl_data }, { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, -- cgit v1.2.3 From 83a5d6c98af24bb4531dfc05e7c2d3ac2562c6d9 Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Feb 2015 10:25:40 +0200 Subject: ARM: dts: am4372: add minimal l4 bus layout with control module support This patch creates an l4_wkup interconnect for AM43xx, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM nodea as the clock provider. Signed-off-by: Tero Kristo --- Documentation/devicetree/bindings/arm/omap/l4.txt | 1 + .../devicetree/bindings/arm/omap/prcm.txt | 2 +- arch/arm/boot/dts/am4372.dtsi | 85 +++++++++++++--------- arch/arm/boot/dts/am43xx-clocks.dtsi | 2 +- arch/arm/mach-omap2/control.c | 2 +- 5 files changed, 53 insertions(+), 39 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/Documentation/devicetree/bindings/arm/omap/l4.txt b/Documentation/devicetree/bindings/arm/omap/l4.txt index d333f0a9044e..941b914eb8cf 100644 --- a/Documentation/devicetree/bindings/arm/omap/l4.txt +++ b/Documentation/devicetree/bindings/arm/omap/l4.txt @@ -7,6 +7,7 @@ Required properties: Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus + Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus - ranges : contains the IO map range for the bus Examples: diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt index c8e202763be8..8af4f325ee23 100644 --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt @@ -12,7 +12,7 @@ Required properties: "ti,am3-prcm" "ti,am3-scm" "ti,am4-prcm" - "ti,am4-scrm" + "ti,am4-scm" "ti,omap2-prcm" "ti,omap2-scm" "ti,omap3-prm" diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 1943fc333e7c..f8a02a295e08 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -57,22 +57,6 @@ cache-level = <2>; }; - am43xx_control_module: control_module@4a002000 { - compatible = "syscon"; - reg = <0x44e10000 0x7f4>; - }; - - am43xx_pinmux: pinmux@44e10800 { - compatible = "ti,am437-padconf", "pinctrl-single"; - reg = <0x44e10800 0x31c>; - #address-cells = <1>; - #size-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - pinctrl-single,register-width = <32>; - pinctrl-single,function-mask = <0xffffffff>; - }; - ocp { compatible = "ti,am4372-l3-noc", "simple-bus"; #address-cells = <1>; @@ -84,29 +68,58 @@ interrupts = , ; - prcm: prcm@44df0000 { - compatible = "ti,am4-prcm"; - reg = <0x44df0000 0x11000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; + l4_wkup: l4_wkup@44c00000 { + compatible = "ti,am4-l4-wkup", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x44c00000 0x287000>; - prcm_clockdomains: clockdomains { - }; - }; + prcm: prcm@1f0000 { + compatible = "ti,am4-prcm"; + reg = <0x1f0000 0x11000>; - scrm: scrm@44e10000 { - compatible = "ti,am4-scrm"; - reg = <0x44e10000 0x2000>; + prcm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; + prcm_clockdomains: clockdomains { + }; }; - scrm_clockdomains: clockdomains { + scm: scm@210000 { + compatible = "ti,am4-scm", "simple-bus"; + reg = <0x210000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x210000 0x4000>; + + am43xx_pinmux: pinmux@800 { + compatible = "ti,am437-padconf", + "pinctrl-single"; + reg = <0x800 0x31c>; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0xffffffff>; + }; + + scm_conf: scm_conf@0 { + compatible = "syscon"; + reg = <0x0 0x800>; + #address-cells = <1>; + #size-cells = <1>; + + scm_clocks: clocks { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + scm_clockdomains: clockdomains { + }; }; }; @@ -933,7 +946,7 @@ clocks = <&dcan0_fck>; clock-names = "fck"; reg = <0x481cc000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 0>; + syscon-raminit = <&scm_conf 0x644 0>; interrupts = ; status = "disabled"; }; @@ -944,7 +957,7 @@ clocks = <&dcan1_fck>; clock-names = "fck"; reg = <0x481d0000 0x2000>; - syscon-raminit = <&am43xx_control_module 0x644 1>; + syscon-raminit = <&scm_conf 0x644 1>; interrupts = ; status = "disabled"; }; diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index c7dc9dab93a4..44869aa72642 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -7,7 +7,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -&scrm_clocks { +&scm_clocks { sys_clkin_ck: sys_clkin_ck { #clock-cells = <0>; compatible = "ti,mux-clock"; diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 477e2c8f26a6..404778449ef7 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -668,7 +668,7 @@ static const struct control_init_data omap2_ctrl_data = { static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,am3-scm", .data = &ctrl_data }, - { .compatible = "ti,am4-scrm", .data = &ctrl_data }, + { .compatible = "ti,am4-scm", .data = &ctrl_data }, { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, -- cgit v1.2.3 From efde234674d9db08b762d9faef4dbbaa2eba3a2e Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Fri, 20 Feb 2015 10:08:52 +0200 Subject: ARM: OMAP4+: control: remove support for legacy pad read/write omap4_ctrl_pad_readl/writel are no longer used by anybody, so remove these. Syscon / pinctrl should be used to access the padconf area instead. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 24 +----------------------- arch/arm/mach-omap2/control.h | 5 +---- arch/arm/mach-omap2/io.c | 11 ++++------- 3 files changed, 6 insertions(+), 34 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 404778449ef7..c8565d3dbefe 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -36,7 +36,6 @@ static void __iomem *omap2_ctrl_base; static s16 omap2_ctrl_offset; -static void __iomem *omap4_ctrl_pad_base; static struct regmap *omap2_ctrl_syscon; #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM) @@ -139,13 +138,9 @@ struct omap3_control_regs { static struct omap3_control_regs control_context; #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ -#define OMAP4_CTRL_PAD_REGADDR(reg) (omap4_ctrl_pad_base + (reg)) - -void __init omap2_set_globals_control(void __iomem *ctrl, - void __iomem *ctrl_pad) +void __init omap2_set_globals_control(void __iomem *ctrl) { omap2_ctrl_base = ctrl; - omap4_ctrl_pad_base = ctrl_pad; } u8 omap_ctrl_readb(u16 offset) @@ -218,23 +213,6 @@ void omap_ctrl_writel(u32 val, u16 offset) val); } -/* - * On OMAP4 control pad are not addressable from control - * core base. So the common omap_ctrl_read/write APIs breaks - * Hence export separate APIs to manage the omap4 pad control - * registers. This APIs will work only for OMAP4 - */ - -u32 omap4_ctrl_pad_readl(u16 offset) -{ - return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset)); -} - -void omap4_ctrl_pad_writel(u32 val, u16 offset) -{ - writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset)); -} - #ifdef CONFIG_ARCH_OMAP3 /** diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index 5353ff45bf83..80d2b7d8e36e 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h @@ -443,11 +443,9 @@ extern u8 omap_ctrl_readb(u16 offset); extern u16 omap_ctrl_readw(u16 offset); extern u32 omap_ctrl_readl(u16 offset); -extern u32 omap4_ctrl_pad_readl(u16 offset); extern void omap_ctrl_writeb(u8 val, u16 offset); extern void omap_ctrl_writew(u16 val, u16 offset); extern void omap_ctrl_writel(u32 val, u16 offset); -extern void omap4_ctrl_pad_writel(u32 val, u16 offset); extern void omap3_save_scratchpad_contents(void); extern void omap3_clear_scratchpad_contents(void); @@ -465,8 +463,7 @@ extern int omap3_ctrl_save_padconf(void); void omap3_ctrl_init(void); int omap2_control_base_init(void); int omap_control_init(void); -extern void omap2_set_globals_control(void __iomem *ctrl, - void __iomem *ctrl_pad); +void omap2_set_globals_control(void __iomem *ctrl); void __init omap3_control_legacy_iomap_init(void); #else #define omap_ctrl_readb(x) 0 diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index c3fa739ab4c8..6c39cc0caebc 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -443,7 +443,7 @@ void __init omap3_init_early(void) /* XXX: remove these once OMAP3 is DT only */ if (!of_have_populated_dt()) { omap2_set_globals_control( - OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), NULL); + OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE)); omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE)); omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), NULL); @@ -631,8 +631,7 @@ void __init omap4430_init_early(void) { omap2_set_globals_tap(OMAP443X_CLASS, OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), - OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); omap4xxx_check_revision(); omap4xxx_check_features(); @@ -660,8 +659,7 @@ void __init omap5_init_early(void) { omap2_set_globals_tap(OMAP54XX_CLASS, OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), - OMAP2_L4_IO_ADDRESS(OMAP54XX_CTRL_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap4_pm_init_early(); omap2_prcm_base_init(); @@ -686,8 +684,7 @@ void __init omap5_init_late(void) void __init dra7xx_init_early(void) { omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE), - OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE)); + omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); omap4_pm_init_early(); omap2_prcm_base_init(); -- cgit v1.2.3 From ca125b5e31f5ada6844f57c5a8e7cd104d26c8fa Mon Sep 17 00:00:00 2001 From: Tero Kristo Date: Thu, 12 Feb 2015 11:47:04 +0200 Subject: ARM: OMAP4+: control: add support for initializing control module via DT OMAP4, OMAP5 and DRA7 now parse DT entries for control module address spaces, and set up syscon mappings appropriately. Low level IO init is updated to remove the legacy control module mappings for these devices also. Signed-off-by: Tero Kristo --- arch/arm/mach-omap2/control.c | 3 +++ arch/arm/mach-omap2/io.c | 6 +++--- 2 files changed, 6 insertions(+), 3 deletions(-) (limited to 'arch/arm/mach-omap2/control.c') diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index c8565d3dbefe..af95a624fe71 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -650,6 +650,9 @@ static const struct of_device_id omap_scrm_dt_match_table[] = { { .compatible = "ti,omap2-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,omap3-scm", .data = &omap2_ctrl_data }, { .compatible = "ti,dm816-scrm", .data = &ctrl_data }, + { .compatible = "ti,omap4-scm-core", .data = &ctrl_data }, + { .compatible = "ti,omap5-scm-core", .data = &ctrl_data }, + { .compatible = "ti,dra7-scm-core", .data = &ctrl_data }, { } }; diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 6c39cc0caebc..7743e3672f98 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -631,8 +631,8 @@ void __init omap4430_init_early(void) { omap2_set_globals_tap(OMAP443X_CLASS, OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); + omap2_control_base_init(); omap4xxx_check_revision(); omap4xxx_check_features(); omap2_prcm_base_init(); @@ -659,8 +659,8 @@ void __init omap5_init_early(void) { omap2_set_globals_tap(OMAP54XX_CLASS, OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap2_control_base_init(); omap4_pm_init_early(); omap2_prcm_base_init(); omap5xxx_check_revision(); @@ -684,8 +684,8 @@ void __init omap5_init_late(void) void __init dra7xx_init_early(void) { omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); - omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); + omap2_control_base_init(); omap4_pm_init_early(); omap2_prcm_base_init(); dra7xxx_check_revision(); -- cgit v1.2.3