From 3eb635f1ca2d25bd11a697f5bdb52ac3d08c240e Mon Sep 17 00:00:00 2001 From: Boris BREZILLON Date: Thu, 3 Jul 2014 01:56:45 +0200 Subject: clk: composite: support determine_rate using rate_ops->round_rate + mux_ops->set_parent In case the rate_hw does not implement determine_rate, but only round_rate we fallback to best_parent selection if mux_hw is present and support reparenting. This also fixes a rate calculation problem when using the standard div and mux ops, as in this case currently only the mux->determine_rate is used in the composite rate calculation. So when for example the composite clock has two parents at 600 and 800MHz, the requested rate is 75MHz, which the divider could provide, without this change the rate would be set 600MHz ignoring the divider completely. This may be way out of spec for the component. Signed-off-by: Boris BREZILLON Signed-off-by: Heiko Stuebner [heiko@sntech.de: fixed output return a rate instead of the diff] Acked-By: Max Schwarz Tested-By: Max Schwarz Tested-by: Gabriel Fernandez Signed-off-by: Mike Turquette --- drivers/clk/clk-composite.c | 48 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) (limited to 'drivers/clk/clk-composite.c') diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 57a078e06efe..9548bfcbd56b 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -64,11 +64,56 @@ static long clk_composite_determine_rate(struct clk_hw *hw, unsigned long rate, const struct clk_ops *mux_ops = composite->mux_ops; struct clk_hw *rate_hw = composite->rate_hw; struct clk_hw *mux_hw = composite->mux_hw; + struct clk *parent; + unsigned long parent_rate; + long tmp_rate, best_rate = 0; + unsigned long rate_diff; + unsigned long best_rate_diff = ULONG_MAX; + int i; if (rate_hw && rate_ops && rate_ops->determine_rate) { rate_hw->clk = hw->clk; return rate_ops->determine_rate(rate_hw, rate, best_parent_rate, best_parent_p); + } else if (rate_hw && rate_ops && rate_ops->round_rate && + mux_hw && mux_ops && mux_ops->set_parent) { + *best_parent_p = NULL; + + if (__clk_get_flags(hw->clk) & CLK_SET_RATE_NO_REPARENT) { + *best_parent_p = clk_get_parent(mux_hw->clk); + *best_parent_rate = __clk_get_rate(*best_parent_p); + + return rate_ops->round_rate(rate_hw, rate, + best_parent_rate); + } + + for (i = 0; i < __clk_get_num_parents(mux_hw->clk); i++) { + parent = clk_get_parent_by_index(mux_hw->clk, i); + if (!parent) + continue; + + parent_rate = __clk_get_rate(parent); + + tmp_rate = rate_ops->round_rate(rate_hw, rate, + &parent_rate); + if (tmp_rate < 0) + continue; + + rate_diff = abs(rate - tmp_rate); + + if (!rate_diff || !*best_parent_p + || best_rate_diff > rate_diff) { + *best_parent_p = parent; + *best_parent_rate = parent_rate; + best_rate_diff = rate_diff; + best_rate = tmp_rate; + } + + if (!rate_diff) + return rate; + } + + return best_rate; } else if (mux_hw && mux_ops && mux_ops->determine_rate) { mux_hw->clk = hw->clk; return mux_ops->determine_rate(mux_hw, rate, best_parent_rate, @@ -196,7 +241,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name, composite->rate_hw = rate_hw; composite->rate_ops = rate_ops; clk_composite_ops->recalc_rate = clk_composite_recalc_rate; - if (rate_ops->determine_rate) + if (rate_ops->determine_rate || + (rate_ops->round_rate && clk_composite_ops->set_parent)) clk_composite_ops->determine_rate = clk_composite_determine_rate; } -- cgit v1.2.3 From 0c02cf2f1c2ffd75221b43bacb4f02a0e52e014b Mon Sep 17 00:00:00 2001 From: Heiko Stübner Date: Thu, 3 Jul 2014 01:57:30 +0200 Subject: clk: composite: allow read-only clocks This allows readl-only composite clocks by making mux_ops->set_parent and divider_ops->round_rate/set_rate optional. Signed-off-by: Heiko Stuebner Acked-By: Max Schwarz Tested-By: Max Schwarz Signed-off-by: Mike Turquette --- drivers/clk/clk-composite.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/clk/clk-composite.c') diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 9548bfcbd56b..faf7c32fe351 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -207,7 +207,7 @@ struct clk *clk_register_composite(struct device *dev, const char *name, clk_composite_ops = &composite->ops; if (mux_hw && mux_ops) { - if (!mux_ops->get_parent || !mux_ops->set_parent) { + if (!mux_ops->get_parent) { clk = ERR_PTR(-EINVAL); goto err; } @@ -215,7 +215,8 @@ struct clk *clk_register_composite(struct device *dev, const char *name, composite->mux_hw = mux_hw; composite->mux_ops = mux_ops; clk_composite_ops->get_parent = clk_composite_get_parent; - clk_composite_ops->set_parent = clk_composite_set_parent; + if (mux_ops->set_parent) + clk_composite_ops->set_parent = clk_composite_set_parent; if (mux_ops->determine_rate) clk_composite_ops->determine_rate = clk_composite_determine_rate; } @@ -232,10 +233,6 @@ struct clk *clk_register_composite(struct device *dev, const char *name, if (rate_ops->set_rate) { clk_composite_ops->set_rate = clk_composite_set_rate; } - } else { - WARN(rate_ops->set_rate, - "%s: missing round_rate op is required\n", - __func__); } composite->rate_hw = rate_hw; -- cgit v1.2.3 From 5a994e151f7c54a5fdeb07fe2fed4ed64b9321b8 Mon Sep 17 00:00:00 2001 From: Mike Turquette Date: Thu, 3 Jul 2014 01:58:14 +0200 Subject: clk: composite: improve rate_hw sanity check logic The function pointer population and sanity checking logic got a bit ugly with the advent of the .determine_rate callback. Clean it up. Signed-off-by: Mike Turquette --- drivers/clk/clk-composite.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) (limited to 'drivers/clk/clk-composite.c') diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index faf7c32fe351..b9355daf8065 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -226,21 +226,27 @@ struct clk *clk_register_composite(struct device *dev, const char *name, clk = ERR_PTR(-EINVAL); goto err; } + clk_composite_ops->recalc_rate = clk_composite_recalc_rate; - /* .round_rate is a prerequisite for .set_rate */ - if (rate_ops->round_rate) { - clk_composite_ops->round_rate = clk_composite_round_rate; - if (rate_ops->set_rate) { - clk_composite_ops->set_rate = clk_composite_set_rate; - } + if (rate_ops->determine_rate) + clk_composite_ops->determine_rate = + clk_composite_determine_rate; + else if (rate_ops->round_rate) + clk_composite_ops->round_rate = + clk_composite_round_rate; + + /* .set_rate requires either .round_rate or .determine_rate */ + if (rate_ops->set_rate) { + if (rate_ops->determine_rate || rate_ops->round_rate) + clk_composite_ops->set_rate = + clk_composite_set_rate; + else + WARN(1, "%s: missing round_rate op is required\n", + __func__); } composite->rate_hw = rate_hw; composite->rate_ops = rate_ops; - clk_composite_ops->recalc_rate = clk_composite_recalc_rate; - if (rate_ops->determine_rate || - (rate_ops->round_rate && clk_composite_ops->set_parent)) - clk_composite_ops->determine_rate = clk_composite_determine_rate; } if (gate_hw && gate_ops) { -- cgit v1.2.3