From e6749c89b4b0acaeddf4909eb75b7f6c8a4c15b2 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Sun, 9 Apr 2017 15:00:16 -0700 Subject: platform/x86: intel_pmc_ipc: fix gcr offset According to Broxton APL spec, PMC MIMO resources for Global Control Registers(GCR) are located at 4K(0x1000) offset from IPC base address. In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR region base address from IPC base address and its current value of 0x1008 is incorrect because it points to location for PMC_CFG register and not the GCR base address itself. GCR Base = IPC1 Base + 0x1000. This patch fixes this offset issue. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_ipc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/platform/x86/intel_pmc_ipc.c') diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 0651d47b8eeb..0a3359240227 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -82,7 +82,7 @@ /* exported resources from IFWI */ #define PLAT_RESOURCE_IPC_INDEX 0 #define PLAT_RESOURCE_IPC_SIZE 0x1000 -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 #define PLAT_RESOURCE_GCR_SIZE 0x1000 #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 -- cgit v1.2.3 From 496702068597ff29092e724301f77b91864454b3 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Sun, 9 Apr 2017 15:00:17 -0700 Subject: platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's This patch adds API's to read/write/update PMC GC registers. PMC dependent devices like iTCO_wdt, Telemetry has requirement to acces GCR registers. These API's can be used for this purpose. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Andy Shevchenko --- arch/x86/include/asm/intel_pmc_ipc.h | 21 +++++++ drivers/platform/x86/intel_pmc_ipc.c | 115 +++++++++++++++++++++++++++++++++++ 2 files changed, 136 insertions(+) (limited to 'drivers/platform/x86/intel_pmc_ipc.c') diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index 4291b6a5ddf7..8402efef10ad 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -23,6 +23,9 @@ #define IPC_ERR_EMSECURITY 6 #define IPC_ERR_UNSIGNEDKERNEL 7 +/* GCR reg offsets from gcr base*/ +#define PMC_GCR_PMC_CFG_REG 0x08 + #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) int intel_pmc_ipc_simple_command(int cmd, int sub); @@ -31,6 +34,9 @@ int intel_pmc_ipc_raw_cmd(u32 cmd, u32 sub, u8 *in, u32 inlen, int intel_pmc_ipc_command(u32 cmd, u32 sub, u8 *in, u32 inlen, u32 *out, u32 outlen); int intel_pmc_s0ix_counter_read(u64 *data); +int intel_pmc_gcr_read(u32 offset, u32 *data); +int intel_pmc_gcr_write(u32 offset, u32 data); +int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val); #else @@ -56,6 +62,21 @@ static inline int intel_pmc_s0ix_counter_read(u64 *data) return -EINVAL; } +static inline int intel_pmc_gcr_read(u32 offset, u32 *data) +{ + return -EINVAL; +} + +static inline int intel_pmc_gcr_write(u32 offset, u32 data) +{ + return -EINVAL; +} + +static inline int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) +{ + return -EINVAL; +} + #endif /*CONFIG_INTEL_PMC_IPC*/ #endif diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 0a3359240227..a0c773b3910e 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -128,6 +128,7 @@ static struct intel_pmc_ipc_dev { /* gcr */ resource_size_t gcr_base; int gcr_size; + void __iomem *gcr_mem_base; bool has_gcr_regs; /* punit */ @@ -199,6 +200,119 @@ static inline u64 gcr_data_readq(u32 offset) return readq(ipcdev.ipc_base + offset); } +static inline int is_gcr_valid(u32 offset) +{ + if (!ipcdev.has_gcr_regs) + return -EACCES; + + if (offset > PLAT_RESOURCE_GCR_SIZE) + return -EINVAL; + + return 0; +} + +/** + * intel_pmc_gcr_read() - Read PMC GCR register + * @offset: offset of GCR register from GCR address base + * @data: data pointer for storing the register output + * + * Reads the PMC GCR register of given offset. + * + * Return: negative value on error or 0 on success. + */ +int intel_pmc_gcr_read(u32 offset, u32 *data) +{ + int ret; + + mutex_lock(&ipclock); + + ret = is_gcr_valid(offset); + if (ret < 0) { + mutex_unlock(&ipclock); + return ret; + } + + *data = readl(ipcdev.gcr_mem_base + offset); + + mutex_unlock(&ipclock); + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pmc_gcr_read); + +/** + * intel_pmc_gcr_write() - Write PMC GCR register + * @offset: offset of GCR register from GCR address base + * @data: register update value + * + * Writes the PMC GCR register of given offset with given + * value. + * + * Return: negative value on error or 0 on success. + */ +int intel_pmc_gcr_write(u32 offset, u32 data) +{ + int ret; + + mutex_lock(&ipclock); + + ret = is_gcr_valid(offset); + if (ret < 0) { + mutex_unlock(&ipclock); + return ret; + } + + writel(data, ipcdev.gcr_mem_base + offset); + + mutex_unlock(&ipclock); + + return 0; +} +EXPORT_SYMBOL_GPL(intel_pmc_gcr_write); + +/** + * intel_pmc_gcr_update() - Update PMC GCR register bits + * @offset: offset of GCR register from GCR address base + * @mask: bit mask for update operation + * @val: update value + * + * Updates the bits of given GCR register as specified by + * @mask and @val. + * + * Return: negative value on error or 0 on success. + */ +int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val) +{ + u32 new_val; + int ret = 0; + + mutex_lock(&ipclock); + + ret = is_gcr_valid(offset); + if (ret < 0) + goto gcr_ipc_unlock; + + new_val = readl(ipcdev.gcr_mem_base + offset); + + new_val &= ~mask; + new_val |= val & mask; + + writel(new_val, ipcdev.gcr_mem_base + offset); + + new_val = readl(ipcdev.gcr_mem_base + offset); + + /* check whether the bit update is successful */ + if ((new_val & mask) != (val & mask)) { + ret = -EIO; + goto gcr_ipc_unlock; + } + +gcr_ipc_unlock: + mutex_unlock(&ipclock); + return ret; +} +EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); + static int intel_pmc_ipc_check_status(void) { int status; @@ -747,6 +861,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) ipcdev.ipc_base = addr; ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET; + ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; dev_info(&pdev->dev, "ipc res: %pR\n", res); -- cgit v1.2.3 From 9d855d468dc655d10be6cb52e36aa0bbfa6f515d Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Sun, 9 Apr 2017 15:00:20 -0700 Subject: platform/x86: intel_pmc_ipc: Fix iTCO_wdt GCS memory mapping failure iTCO_wdt driver need access to PMC_CFG GCR register to modify the noreboot setting. Currently, this is done by passing PMC_CFG reg address as memory resource to watchdog driver and allowing it directly modify the PMC_CFG register. But currently PMC driver also has requirement to memory map the entire GCR register space in this driver. This causes mem request failure in watchdog driver. So this patch fixes this issue by adding API to update noreboot flag and passes them to watchdog driver via platform data. Signed-off-by: Kuppuswamy Sathyanarayanan Signed-off-by: Andy Shevchenko --- drivers/platform/x86/intel_pmc_ipc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_ipc.c') diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index a0c773b3910e..0a39b0f17bbe 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -112,6 +112,13 @@ #define TCO_PMC_OFFSET 0x8 #define TCO_PMC_SIZE 0x4 +/* PMC register bit definitions */ + +/* PMC_CFG_REG bit masks */ +#define PMC_CFG_NO_REBOOT_MASK (1 << 4) +#define PMC_CFG_NO_REBOOT_EN (1 << 4) +#define PMC_CFG_NO_REBOOT_DIS (0 << 4) + static struct intel_pmc_ipc_dev { struct device *dev; void __iomem *ipc_base; @@ -126,8 +133,6 @@ static struct intel_pmc_ipc_dev { struct platform_device *tco_dev; /* gcr */ - resource_size_t gcr_base; - int gcr_size; void __iomem *gcr_mem_base; bool has_gcr_regs; @@ -313,6 +318,14 @@ gcr_ipc_unlock: } EXPORT_SYMBOL_GPL(intel_pmc_gcr_update); +static int update_no_reboot_bit(void *priv, bool set) +{ + u32 value = set ? PMC_CFG_NO_REBOOT_EN : PMC_CFG_NO_REBOOT_DIS; + + return intel_pmc_gcr_update(PMC_GCR_PMC_CFG_REG, + PMC_CFG_NO_REBOOT_MASK, value); +} + static int intel_pmc_ipc_check_status(void) { int status; @@ -630,15 +643,13 @@ static struct resource tco_res[] = { { .flags = IORESOURCE_IO, }, - /* GCS */ - { - .flags = IORESOURCE_MEM, - }, }; static struct itco_wdt_platform_data tco_info = { .name = "Apollo Lake SoC", .version = 5, + .no_reboot_priv = &ipcdev, + .update_no_reboot_bit = update_no_reboot_bit, }; #define TELEMETRY_RESOURCE_PUNIT_SSRAM 0 @@ -695,10 +706,6 @@ static int ipc_create_tco_device(void) res->start = ipcdev.acpi_io_base + SMI_EN_OFFSET; res->end = res->start + SMI_EN_SIZE - 1; - res = tco_res + TCO_RESOURCE_GCR_MEM; - res->start = ipcdev.gcr_base + TCO_PMC_OFFSET; - res->end = res->start + TCO_PMC_SIZE - 1; - pdev = platform_device_register_full(&pdevinfo); if (IS_ERR(pdev)) return PTR_ERR(pdev); @@ -860,9 +867,7 @@ static int ipc_plat_get_res(struct platform_device *pdev) } ipcdev.ipc_base = addr; - ipcdev.gcr_base = res->start + PLAT_RESOURCE_GCR_OFFSET; ipcdev.gcr_mem_base = addr + PLAT_RESOURCE_GCR_OFFSET; - ipcdev.gcr_size = PLAT_RESOURCE_GCR_SIZE; dev_info(&pdev->dev, "ipc res: %pR\n", res); ipcdev.telem_res_inval = 0; -- cgit v1.2.3 From 62a7b9c859d09af860c71cfbea4381061975ca72 Mon Sep 17 00:00:00 2001 From: Kuppuswamy Sathyanarayanan Date: Sun, 9 Apr 2017 15:00:21 -0700 Subject: platform/x86: intel_pmc_ipc: use gcr mem base for S0ix counter read To maintain the uniformity in accessing GCR registers, this patch modifies the S0ix counter read function to use GCR address base instead of ipc address base. Signed-off-by: Kuppuswamy Sathyanarayanan Reviewed-by: Rajneesh Bhardwaj Tested-by: Shanth Murthy Signed-off-by: Andy Shevchenko --- arch/x86/include/asm/intel_pmc_ipc.h | 2 ++ drivers/platform/x86/intel_pmc_ipc.c | 10 +++------- 2 files changed, 5 insertions(+), 7 deletions(-) (limited to 'drivers/platform/x86/intel_pmc_ipc.c') diff --git a/arch/x86/include/asm/intel_pmc_ipc.h b/arch/x86/include/asm/intel_pmc_ipc.h index 8402efef10ad..fac89eb78a6b 100644 --- a/arch/x86/include/asm/intel_pmc_ipc.h +++ b/arch/x86/include/asm/intel_pmc_ipc.h @@ -25,6 +25,8 @@ /* GCR reg offsets from gcr base*/ #define PMC_GCR_PMC_CFG_REG 0x08 +#define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78 +#define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80 #if IS_ENABLED(CONFIG_INTEL_PMC_IPC) diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c index 0a39b0f17bbe..e4d4dfe3e1d1 100644 --- a/drivers/platform/x86/intel_pmc_ipc.c +++ b/drivers/platform/x86/intel_pmc_ipc.c @@ -57,10 +57,6 @@ #define IPC_WRITE_BUFFER 0x80 #define IPC_READ_BUFFER 0x90 -/* PMC Global Control Registers */ -#define GCR_TELEM_DEEP_S0IX_OFFSET 0x1078 -#define GCR_TELEM_SHLW_S0IX_OFFSET 0x1080 - /* Residency with clock rate at 19.2MHz to usecs */ #define S0IX_RESIDENCY_IN_USECS(d, s) \ ({ \ @@ -202,7 +198,7 @@ static inline u32 ipc_data_readl(u32 offset) static inline u64 gcr_data_readq(u32 offset) { - return readq(ipcdev.ipc_base + offset); + return readq(ipcdev.gcr_mem_base + offset); } static inline int is_gcr_valid(u32 offset) @@ -902,8 +898,8 @@ int intel_pmc_s0ix_counter_read(u64 *data) if (!ipcdev.has_gcr_regs) return -EACCES; - deep = gcr_data_readq(GCR_TELEM_DEEP_S0IX_OFFSET); - shlw = gcr_data_readq(GCR_TELEM_SHLW_S0IX_OFFSET); + deep = gcr_data_readq(PMC_GCR_TELEM_DEEP_S0IX_REG); + shlw = gcr_data_readq(PMC_GCR_TELEM_SHLW_S0IX_REG); *data = S0IX_RESIDENCY_IN_USECS(deep, shlw); -- cgit v1.2.3