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authorRalf Baechle <ralf@linux-mips.org>2007-03-20 13:56:50 +0000
committerRalf Baechle <ralf@linux-mips.org>2007-03-24 17:01:49 +0000
commit7605b3906192a171e651076325b1ed1d5ea57ec9 (patch)
treea86d308b36fda5297349691089a868208a5a9688
parent83598f1cb06101e972b1f5aaf3408eb729622fa8 (diff)
downloadlinux-bcache-7605b3906192a171e651076325b1ed1d5ea57ec9.tar.zst
[MIPS] Fix pipeline hazard.
In the the sequence: ei .. mfc0 $x, $status the mfc0 may not see the SR_IE bit set. This was a deliberate bug in the kernel code because we knew this was a safe thing to do on all R2 silicon so far but new silicon is changing this. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
-rw-r--r--include/asm-mips/hazards.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
index 50073157a617..e50c77e69cb5 100644
--- a/include/asm-mips/hazards.h
+++ b/include/asm-mips/hazards.h
@@ -52,6 +52,7 @@ ASMMACRO(tlb_probe_hazard,
_ehb
)
ASMMACRO(irq_enable_hazard,
+ _ehb
)
ASMMACRO(irq_disable_hazard,
_ehb