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authorKalle Jokiniemi <kalle.jokiniemi@digia.com>2009-05-16 08:28:17 -0700
committerTony Lindgren <tony@atomide.com>2009-05-16 08:28:17 -0700
commit8dbe43930a4e9bede88eb67a9c613773a2747caf (patch)
tree168ad0e8495c97d0b1916c0fb9743f1c48e5e88f
parente102657ed16bbed49820d9c58509220fc8d9289a (diff)
ARM: OMAP3: Fix HW SAVEANDRESTORE shift define
The OMAP3430ES2_SAVEANDRESTORE_SHIFT macro is used by powerdomain code in "1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT" manner, but the definition was also (1 << 4), meaning we actually modified bit 16. So the definition needs to be 4. This fixes also a cold reset HW bug in OMAP3430 ES3.x where some of the efuse bits are not isolated during wake-up from off mode. This can cause randomish cold resets with off mode. Enabling the USBTLL hardware SAVEANDRESTORE causes the core power up assert to be delayed in a way that we will not get faulty values when boot ROM is reading the unisolated registers. Signed-off-by: Kalle Jokiniemi <kalle.jokiniemi@digia.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Acked-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index c6a7940f4287..9fd03a2ec95c 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -409,7 +409,7 @@
/* PM_PREPWSTST_CAM specific bits */
/* PM_PWSTCTRL_USBHOST specific bits */
-#define OMAP3430ES2_SAVEANDRESTORE_SHIFT (1 << 4)
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
/* RM_RSTST_PER specific bits */