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authorJiri Kosina <jkosina@suse.cz>2012-02-06 16:11:09 +0100
committerJiri Kosina <jkosina@suse.cz>2012-02-06 16:12:16 +0100
commitd4730ace0c7dbb64513e35b6fc5fd7e7f381e490 (patch)
tree18890c096cdd869a593c56de3257faa40af8e050 /arch/arm
parentc1c454b8691cc95aa83f19273ed7845914c70e83 (diff)
parent23783f817bceedd6d4e549385e3f400ea64059e5 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into upstream-fixes
Sync with Linus' tree. This is necessary to have a base for patch that fixes commit 35b4c01e29b ("power_supply: add "powers" links to self-powered HID devices") which went in through Anton's tree.
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Kconfig6
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/Makefile6
-rw-r--r--arch/arm/common/gic.c7
-rw-r--r--arch/arm/common/it8152.c9
-rw-r--r--arch/arm/common/via82c505.c3
-rw-r--r--arch/arm/configs/bonito_defconfig72
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig (renamed from arch/arm/configs/mx5_defconfig)61
-rw-r--r--arch/arm/configs/kota2_defconfig122
-rw-r--r--arch/arm/configs/marzen_defconfig87
-rw-r--r--arch/arm/configs/mx3_defconfig144
-rw-r--r--arch/arm/include/asm/assembler.h4
-rw-r--r--arch/arm/include/asm/domain.h8
-rw-r--r--arch/arm/include/asm/futex.h8
-rw-r--r--arch/arm/include/asm/gpio.h2
-rw-r--r--arch/arm/include/asm/hwcap.h4
-rw-r--r--arch/arm/include/asm/io.h2
-rw-r--r--arch/arm/include/asm/kprobes.h1
-rw-r--r--arch/arm/include/asm/mach/pci.h2
-rw-r--r--arch/arm/include/asm/memblock.h2
-rw-r--r--arch/arm/include/asm/pci.h12
-rw-r--r--arch/arm/include/asm/ptrace.h5
-rw-r--r--arch/arm/include/asm/smp.h6
-rw-r--r--arch/arm/include/asm/smp_plat.h6
-rw-r--r--arch/arm/include/asm/swab.h7
-rw-r--r--arch/arm/include/asm/thread_info.h6
-rw-r--r--arch/arm/include/asm/tlb.h10
-rw-r--r--arch/arm/include/asm/uaccess.h16
-rw-r--r--arch/arm/include/asm/unified.h4
-rw-r--r--arch/arm/include/asm/unistd.h4
-rw-r--r--arch/arm/kernel/bios32.c34
-rw-r--r--arch/arm/kernel/entry-armv.S2
-rw-r--r--arch/arm/kernel/entry-common.S19
-rw-r--r--arch/arm/kernel/head.S8
-rw-r--r--arch/arm/kernel/perf_event_v7.c28
-rw-r--r--arch/arm/kernel/ptrace.c24
-rw-r--r--arch/arm/kernel/setup.c17
-rw-r--r--arch/arm/kernel/signal.c5
-rw-r--r--arch/arm/kernel/smp.c24
-rw-r--r--arch/arm/kernel/smp_twd.c2
-rw-r--r--arch/arm/kernel/vmlinux.lds.S9
-rw-r--r--arch/arm/lib/getuser.S12
-rw-r--r--arch/arm/lib/putuser.S28
-rw-r--r--arch/arm/lib/uaccess.S82
-rw-r--r--arch/arm/mach-at91/Kconfig14
-rw-r--r--arch/arm/mach-at91/Makefile14
-rw-r--r--arch/arm/mach-at91/at91cap9.c9
-rw-r--r--arch/arm/mach-at91/at91sam9260.c1
-rw-r--r--arch/arm/mach-at91/at91sam9261.c1
-rw-r--r--arch/arm/mach-at91/at91sam9263.c1
-rw-r--r--arch/arm/mach-at91/at91sam9_alt_reset.S7
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c7
-rw-r--r--arch/arm/mach-at91/at91sam9g45_reset.S40
-rw-r--r--arch/arm/mach-at91/at91sam9rl.c1
-rw-r--r--arch/arm/mach-at91/generic.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91_rstc.h18
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h108
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9260.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9261.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9263.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h30
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9rl.h2
-rw-r--r--arch/arm/mach-at91/include/mach/board.h2
-rw-r--r--arch/arm/mach-at91/pm.c9
-rw-r--r--arch/arm/mach-at91/pm.h8
-rw-r--r--arch/arm/mach-at91/pm_slowclock.S5
-rw-r--r--arch/arm/mach-at91/setup.c16
-rw-r--r--arch/arm/mach-bcmring/arch.c2
-rw-r--r--arch/arm/mach-bcmring/dma.c812
-rw-r--r--arch/arm/mach-bcmring/include/mach/dma.h196
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c8
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c2
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c2
-rw-r--r--arch/arm/mach-davinci/da850.c32
-rw-r--r--arch/arm/mach-dove/pcie.c9
-rw-r--r--arch/arm/mach-ep93xx/include/mach/dma.h6
-rw-r--r--arch/arm/mach-exynos/headsmp.S2
-rw-r--r--arch/arm/mach-exynos/hotplug.c1
-rw-r--r--arch/arm/mach-exynos/include/mach/cpufreq.h34
-rw-r--r--arch/arm/mach-exynos/mach-origen.c3
-rw-r--r--arch/arm/mach-exynos/platsmp.c6
-rw-r--r--arch/arm/mach-footbridge/dc21285.c8
-rw-r--r--arch/arm/mach-highbank/highbank.c6
-rw-r--r--arch/arm/mach-imx/Kconfig238
-rw-r--r--arch/arm/mach-imx/Makefile21
-rw-r--r--arch/arm/mach-imx/Makefile.boot12
-rw-r--r--arch/arm/mach-imx/clock-imx6q.c11
-rw-r--r--arch/arm/mach-imx/clock-mx51-mx53.c (renamed from arch/arm/mach-mx5/clock-mx51-mx53.c)2
-rw-r--r--arch/arm/mach-imx/cpu-imx5.c (renamed from arch/arm/mach-mx5/cpu.c)0
-rw-r--r--arch/arm/mach-imx/cpu_op-mx51.c (renamed from arch/arm/mach-mx5/cpu_op-mx51.c)0
-rw-r--r--arch/arm/mach-imx/cpu_op-mx51.h (renamed from arch/arm/mach-mx5/cpu_op-mx51.h)0
-rw-r--r--arch/arm/mach-imx/crm-regs-imx5.h (renamed from arch/arm/mach-mx5/crm_regs.h)0
-rw-r--r--arch/arm/mach-imx/devices-imx50.h (renamed from arch/arm/mach-mx5/devices-imx50.h)0
-rw-r--r--arch/arm/mach-imx/devices-imx51.h (renamed from arch/arm/mach-mx5/devices-imx51.h)0
-rw-r--r--arch/arm/mach-imx/devices-imx53.h (renamed from arch/arm/mach-mx5/devices-imx53.h)0
-rw-r--r--arch/arm/mach-imx/efika.h (renamed from arch/arm/mach-mx5/efika.h)0
-rw-r--r--arch/arm/mach-imx/ehci-imx5.c (renamed from arch/arm/mach-mx5/ehci.c)0
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx51-baseboard.c (renamed from arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c)0
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c (renamed from arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c)0
-rw-r--r--arch/arm/mach-imx/imx51-dt.c (renamed from arch/arm/mach-mx5/imx51-dt.c)0
-rw-r--r--arch/arm/mach-imx/imx53-dt.c (renamed from arch/arm/mach-mx5/imx53-dt.c)0
-rw-r--r--arch/arm/mach-imx/mach-cpuimx51.c (renamed from arch/arm/mach-mx5/board-cpuimx51.c)0
-rw-r--r--arch/arm/mach-imx/mach-cpuimx51sd.c (renamed from arch/arm/mach-mx5/board-cpuimx51sd.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c5
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c5
-rw-r--r--arch/arm/mach-imx/mach-mx50_rdp.c (renamed from arch/arm/mach-mx5/board-mx50_rdp.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx51_3ds.c (renamed from arch/arm/mach-mx5/board-mx51_3ds.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx51_babbage.c (renamed from arch/arm/mach-mx5/board-mx51_babbage.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikamx.c (renamed from arch/arm/mach-mx5/board-mx51_efikamx.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx51_efikasb.c (renamed from arch/arm/mach-mx5/board-mx51_efikasb.c)0
-rw-r--r--arch/arm/mach-imx/mach-mx53_ard.c (renamed from arch/arm/mach-mx5/board-mx53_ard.c)5
-rw-r--r--arch/arm/mach-imx/mach-mx53_evk.c (renamed from arch/arm/mach-mx5/board-mx53_evk.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx53_loco.c (renamed from arch/arm/mach-mx5/board-mx53_loco.c)1
-rw-r--r--arch/arm/mach-imx/mach-mx53_smd.c (renamed from arch/arm/mach-mx5/board-mx53_smd.c)1
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c5
-rw-r--r--arch/arm/mach-imx/mm-imx5.c (renamed from arch/arm/mach-mx5/mm.c)0
-rw-r--r--arch/arm/mach-imx/mx51_efika.c (renamed from arch/arm/mach-mx5/mx51_efika.c)0
-rw-r--r--arch/arm/mach-imx/pm-imx5.c (renamed from arch/arm/mach-mx5/system.c)89
-rw-r--r--arch/arm/mach-imx/src.c8
-rw-r--r--arch/arm/mach-integrator/pci_v3.c19
-rw-r--r--arch/arm/mach-iop13xx/pci.c17
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c3
-rw-r--r--arch/arm/mach-ixp2000/pci.c8
-rw-r--r--arch/arm/mach-ixp23xx/pci.c8
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c8
-rw-r--r--arch/arm/mach-kirkwood/pcie.c8
-rw-r--r--arch/arm/mach-ks8695/pci.c8
-rw-r--r--arch/arm/mach-msm/headsmp.S1
-rw-r--r--arch/arm/mach-msm/hotplug.c1
-rw-r--r--arch/arm/mach-msm/platsmp.c1
-rw-r--r--arch/arm/mach-msm/vreg.c1
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c8
-rw-r--r--arch/arm/mach-mx5/Kconfig244
-rw-r--r--arch/arm/mach-mx5/Makefile26
-rw-r--r--arch/arm/mach-mx5/Makefile.boot9
-rw-r--r--arch/arm/mach-mx5/pm-imx5.c83
-rw-r--r--arch/arm/mach-omap2/Kconfig16
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c23
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c25
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c3
-rw-r--r--arch/arm/mach-omap2/devices.c20
-rw-r--r--arch/arm/mach-omap2/display.c39
-rw-r--r--arch/arm/mach-omap2/gpmc.c6
-rw-r--r--arch/arm/mach-omap2/hsmmc.c16
-rw-r--r--arch/arm/mach-omap2/io.c4
-rw-r--r--arch/arm/mach-omap2/mcbsp.c3
-rw-r--r--arch/arm/mach-omap2/omap-secure.c13
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c21
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c22
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c54
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c2
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c1
-rw-r--r--arch/arm/mach-omap2/smartreflex.c2
-rw-r--r--arch/arm/mach-omap2/timer.c2
-rw-r--r--arch/arm/mach-orion5x/pci.c16
-rw-r--r--arch/arm/mach-picoxcell/time.c2
-rw-r--r--arch/arm/mach-pxa/corgi.c9
-rw-r--r--arch/arm/mach-pxa/devices.c20
-rw-r--r--arch/arm/mach-pxa/eseries.c18
-rw-r--r--arch/arm/mach-pxa/poodle.c6
-rw-r--r--arch/arm/mach-pxa/pxa25x.c2
-rw-r--r--arch/arm/mach-pxa/pxa27x.c2
-rw-r--r--arch/arm/mach-pxa/pxa300.c1
-rw-r--r--arch/arm/mach-pxa/pxa320.c1
-rw-r--r--arch/arm/mach-pxa/pxa3xx.c1
-rw-r--r--arch/arm/mach-pxa/pxa95x.c1
-rw-r--r--arch/arm/mach-pxa/stargate2.c6
-rw-r--r--arch/arm/mach-pxa/tosa.c6
-rw-r--r--arch/arm/mach-realview/hotplug.c1
-rw-r--r--arch/arm/mach-realview/include/mach/board-eb.h18
-rw-r--r--arch/arm/mach-realview/include/mach/board-pb11mp.h2
-rw-r--r--arch/arm/mach-realview/platsmp.c3
-rw-r--r--arch/arm/mach-realview/realview_eb.c14
-rw-r--r--arch/arm/mach-realview/realview_pb1176.c3
-rw-r--r--arch/arm/mach-realview/realview_pb11mp.c16
-rw-r--r--arch/arm/mach-realview/realview_pba8.c3
-rw-r--r--arch/arm/mach-realview/realview_pbx.c3
-rw-r--r--arch/arm/mach-s3c64xx/include/mach/crag6410.h1
-rw-r--r--arch/arm/mach-s3c64xx/mach-crag6410.c19
-rw-r--r--arch/arm/mach-s3c64xx/pm.c13
-rw-r--r--arch/arm/mach-sa1100/assabet.c2
-rw-r--r--arch/arm/mach-sa1100/clock.c91
-rw-r--r--arch/arm/mach-sa1100/collie.c5
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c2
-rw-r--r--arch/arm/mach-sa1100/generic.c20
-rw-r--r--arch/arm/mach-sa1100/include/mach/gpio.h3
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c2
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c13
-rw-r--r--arch/arm/mach-shmobile/Kconfig27
-rw-r--r--arch/arm/mach-shmobile/Makefile9
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c43
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c47
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c522
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c18
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c157
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c382
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7779.c176
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c10
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c144
-rw-r--r--arch/arm/mach-shmobile/headsmp.S2
-rw-r--r--arch/arm/mach-shmobile/hotplug.c32
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h22
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h584
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h363
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c631
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7779.c58
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7740.c2562
-rw-r--r--arch/arm/mach-shmobile/pfc-r8a7779.c2645
-rw-r--r--arch/arm/mach-shmobile/platsmp.c21
-rw-r--r--arch/arm/mach-shmobile/pm-r8a7779.c249
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c2
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c352
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c239
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c23
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c2
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c154
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c1
-rw-r--r--arch/arm/mach-tegra/board-harmony.c8
-rw-r--r--arch/arm/mach-tegra/board-seaboard.c8
-rw-r--r--arch/arm/mach-tegra/include/mach/kbc.h1
-rw-r--r--arch/arm/mach-tegra/pcie.c9
-rw-r--r--arch/arm/mach-ux500/Kconfig1
-rw-r--r--arch/arm/mach-ux500/board-mop500-sdi.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500.c4
-rw-r--r--arch/arm/mach-ux500/board-u5500.c2
-rw-r--r--arch/arm/mach-ux500/cache-l2x0.c48
-rw-r--r--arch/arm/mach-ux500/headsmp.S2
-rw-r--r--arch/arm/mach-ux500/hotplug.c1
-rw-r--r--arch/arm/mach-ux500/include/mach/irqs-board-mop500.h2
-rw-r--r--arch/arm/mach-ux500/platsmp.c1
-rw-r--r--arch/arm/mach-ux500/usb.c6
-rw-r--r--arch/arm/mach-versatile/pci.c19
-rw-r--r--arch/arm/mach-vexpress/ct-ca9x4.c4
-rw-r--r--arch/arm/mach-vexpress/hotplug.c1
-rw-r--r--arch/arm/mach-vexpress/platsmp.c4
-rw-r--r--arch/arm/mach-w90x900/clksel.c2
-rw-r--r--arch/arm/mach-w90x900/cpu.c2
-rw-r--r--arch/arm/mach-w90x900/dev.c6
-rw-r--r--arch/arm/mach-w90x900/mfp.c2
-rw-r--r--arch/arm/mm/Kconfig1
-rw-r--r--arch/arm/mm/init.c17
-rw-r--r--arch/arm/mm/iomap.c21
-rw-r--r--arch/arm/mm/proc-v7.S26
-rw-r--r--arch/arm/plat-iop/pci.c8
-rw-r--r--arch/arm/plat-mxc/Kconfig15
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v1.h2
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3fb.h15
-rw-r--r--arch/arm/plat-nomadik/include/plat/ste_dma40.h11
-rw-r--r--arch/arm/plat-omap/cpu-omap.c171
-rw-r--r--arch/arm/plat-omap/devices.c5
-rw-r--r--arch/arm/plat-omap/include/plat/iommu.h31
-rw-r--r--arch/arm/plat-omap/include/plat/iovmm.h12
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c2
-rw-r--r--arch/arm/plat-samsung/dma-ops.c4
-rw-r--r--arch/arm/plat-samsung/include/plat/dma-ops.h5
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/keypad.h27
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h1
-rw-r--r--arch/arm/plat-samsung/platformdata.c2
-rw-r--r--arch/arm/plat-versatile/headsmp.S1
-rw-r--r--arch/arm/plat-versatile/platsmp.c1
270 files changed, 11088 insertions, 2741 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9d66dfc33a5a..a48aecc17eac 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -16,6 +16,7 @@ config ARM
select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
+ select ARCH_BINFMT_ELF_RANDOMIZE_PIE
select HAVE_GENERIC_DMA_COHERENT
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO
@@ -30,6 +31,7 @@ config ARM
select HAVE_SPARSE_IRQ
select GENERIC_IRQ_SHOW
select CPU_PM if (SUSPEND || CPU_IDLE)
+ select GENERIC_PCI_IOMAP
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
@@ -752,7 +754,7 @@ config ARCH_SA1100
select ARCH_HAS_CPUFREQ
select CPU_FREQ
select GENERIC_CLOCKEVENTS
- select CLKDEV_LOOKUP
+ select HAVE_CLK
select HAVE_SCHED_CLOCK
select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
@@ -823,7 +825,6 @@ config ARCH_S5PC100
select HAVE_CLK
select CLKDEV_LOOKUP
select CPU_V7
- select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C_RTC if RTC_CLASS
@@ -840,7 +841,6 @@ config ARCH_S5PV210
select HAVE_CLK
select CLKDEV_LOOKUP
select CLKSRC_MMIO
- select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 40319d91bb7f..1683bfb9166f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -160,7 +160,6 @@ machine-$(CONFIG_ARCH_MSM) := msm
machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
machine-$(CONFIG_ARCH_IMX_V4_V5) := imx
machine-$(CONFIG_ARCH_IMX_V6_V7) := imx
-machine-$(CONFIG_ARCH_MX5) := mx5
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 5df26a9976a2..fc871e719aae 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -59,9 +59,11 @@ $(obj)/zImage: $(obj)/compressed/vmlinux FORCE
endif
+targets += $(dtb-y)
+
# Rule to build device tree blobs
-$(obj)/%.dtb: $(src)/dts/%.dts
- $(call cmd,dtc)
+$(obj)/%.dtb: $(src)/dts/%.dts FORCE
+ $(call if_changed_dep,dtc)
$(obj)/dtbs: $(addprefix $(obj)/, $(dtb-y))
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index b2dc2dd7f1df..c47d6199b784 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -41,6 +41,7 @@
#include <asm/irq.h>
#include <asm/exception.h>
+#include <asm/smp_plat.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
@@ -352,11 +353,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic)
unsigned int gic_irqs = gic->gic_irqs;
struct irq_domain *domain = &gic->domain;
void __iomem *base = gic_data_dist_base(gic);
- u32 cpu = 0;
-
-#ifdef CONFIG_SMP
- cpu = cpu_logical_map(smp_processor_id());
-#endif
+ u32 cpu = cpu_logical_map(smp_processor_id());
cpumask = 1 << cpu;
cpumask |= cpumask << 8;
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index b539ec855e1a..d1bcd7b13ebc 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -299,8 +299,8 @@ int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
goto err1;
}
- sys->resource[0] = &it8152_io;
- sys->resource[1] = &it8152_mem;
+ pci_add_resource(&sys->resources, &it8152_io);
+ pci_add_resource(&sys->resources, &it8152_mem);
if (platform_notify || platform_notify_remove) {
printk(KERN_ERR "PCI: Can't use platform_notify\n");
@@ -327,6 +327,9 @@ err0:
*/
unsigned int pcibios_max_latency = 255;
+/* ITE bridge requires setting latency timer to avoid early bus access
+ termination by PCI bus master devices
+*/
void pcibios_set_master(struct pci_dev *dev)
{
u8 lat;
@@ -352,7 +355,7 @@ void pcibios_set_master(struct pci_dev *dev)
struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(nr, &it8152_ops, sys);
+ return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
}
EXPORT_SYMBOL(dma_set_coherent_mask);
diff --git a/arch/arm/common/via82c505.c b/arch/arm/common/via82c505.c
index 8421d39109b3..67dd2affc57a 100644
--- a/arch/arm/common/via82c505.c
+++ b/arch/arm/common/via82c505.c
@@ -86,7 +86,8 @@ int __init via82c505_setup(int nr, struct pci_sys_data *sys)
struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
{
if (nr == 0)
- return pci_scan_bus(0, &via82c505_ops, sysdata);
+ return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
+ &sysdata->resources);
return NULL;
}
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
new file mode 100644
index 000000000000..54571082d920
--- /dev/null
+++ b/arch/arm/configs/bonito_defconfig
@@ -0,0 +1,72 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7740=y
+CONFIG_MACH_BONITO=y
+# CONFIG_SH_TIMER_TMU is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_MTD=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_BLOCK2MTD=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_SH_MOBILE=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/configs/mx5_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index d0d8dfece37e..3a4fb2e5fc68 100644
--- a/arch/arm/configs/mx5_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -3,6 +3,7 @@ CONFIG_EXPERIMENTAL=y
CONFIG_KERNEL_LZO=y
CONFIG_SYSVIPC=y
CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
CONFIG_RELAY=y
CONFIG_EXPERT=y
# CONFIG_SLUB_DEBUG is not set
@@ -14,20 +15,31 @@ CONFIG_MODULE_SRCVERSION_ALL=y
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX5=y
-CONFIG_MACH_MX51_BABBAGE=y
+CONFIG_MACH_MX31LILLY=y
+CONFIG_MACH_MX31LITE=y
+CONFIG_MACH_PCM037=y
+CONFIG_MACH_PCM037_EET=y
+CONFIG_MACH_MX31_3DS=y
+CONFIG_MACH_MX31MOBOARD=y
+CONFIG_MACH_QONG=y
+CONFIG_MACH_ARMADILLO5X0=y
+CONFIG_MACH_KZM_ARM11_01=y
+CONFIG_MACH_PCM043=y
+CONFIG_MACH_MX35_3DS=y
+CONFIG_MACH_EUKREA_CPUIMX35=y
+CONFIG_MACH_VPR200=y
+CONFIG_MACH_IMX51_DT=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y
CONFIG_MACH_EUKREA_CPUIMX51SD=y
CONFIG_MACH_MX51_EFIKAMX=y
CONFIG_MACH_MX51_EFIKASB=y
-CONFIG_MACH_MX53_EVK=y
-CONFIG_MACH_MX53_SMD=y
-CONFIG_MACH_MX53_LOCO=y
-CONFIG_MACH_MX53_ARD=y
+CONFIG_MACH_IMX53_DT=y
+CONFIG_SOC_IMX6Q=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
CONFIG_VMSPLIT_2G=y
CONFIG_PREEMPT_VOLUNTARY=y
CONFIG_AEABI=y
@@ -49,7 +61,7 @@ CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
@@ -68,24 +80,20 @@ CONFIG_SCSI_SCAN_ASYNC=y
CONFIG_ATA=y
CONFIG_PATA_IMX=y
CONFIG_NETDEVICES=y
-CONFIG_MII=m
-CONFIG_MARVELL_PHY=y
-CONFIG_DAVICOM_PHY=y
-CONFIG_QSEMI_PHY=y
-CONFIG_LXT_PHY=y
-CONFIG_CICADA_PHY=y
-CONFIG_VITESSE_PHY=y
-CONFIG_SMSC_PHY=y
-CONFIG_BROADCOM_PHY=y
-CONFIG_ICPLUS_PHY=y
-CONFIG_REALTEK_PHY=y
-CONFIG_NATIONAL_PHY=y
-CONFIG_STE10XP=y
-CONFIG_LSI_ET1011C_PHY=y
-CONFIG_MICREL_PHY=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+CONFIG_FEC=y
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC91X=y
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
@@ -124,7 +132,6 @@ CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
-CONFIG_MMC_BLOCK=m
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -133,6 +140,8 @@ CONFIG_LEDS_CLASS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_INTF_DEV_UIE_EMUL=y
CONFIG_RTC_MXC=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/kota2_defconfig
new file mode 100644
index 000000000000..b7735d6347ac
--- /dev/null
+++ b/arch/arm/configs/kota2_defconfig
@@ -0,0 +1,122 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_KEYBOARD_GPIO_POLLED=y
+CONFIG_ARCH_SH73A0=y
+CONFIG_MACH_KOTA2=y
+CONFIG_MEMORY_SIZE=0x1e0000000
+# CONFIG_SH_TIMER_TMU is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_CPU_BPREDICT_DISABLE=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_742230=y
+CONFIG_ARM_ERRATA_742231=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_751472=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_NO_HZ=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+CONFIG_CPU_IDLE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_MAC80211=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_B43=y
+CONFIG_B43_PHY_N=y
+CONFIG_B43_DEBUG=y
+CONFIG_INPUT_SPARSEKMAP=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_SH_KEYSC=y
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=9
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C_SH_MOBILE=y
+# CONFIG_HWMON is not set
+CONFIG_BCMA=y
+CONFIG_BCMA_DEBUG=y
+CONFIG_FB=y
+CONFIG_FB_SH_MOBILE_LCDC=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHI=y
+CONFIG_MMC_SH_MMCIF=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_RENESAS_TPU=y
+CONFIG_LEDS_TRIGGERS=y
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
new file mode 100644
index 000000000000..864f9a5c39dd
--- /dev/null
+++ b/arch/arm/configs/marzen_defconfig
@@ -0,0 +1,87 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_KERNEL_LZMA=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_BLOCK is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7779=y
+CONFIG_MACH_MARZEN=y
+CONFIG_MEMORY_START=0x60000000
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_SHMOBILE_TIMER_HZ=1024
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_SWP_EMULATE is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_NO_HZ=y
+CONFIG_SMP=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+CONFIG_KEXEC=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_INET=y
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+CONFIG_SSB=y
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
deleted file mode 100644
index cb0717fbb03d..000000000000
--- a/arch/arm/configs/mx3_defconfig
+++ /dev/null
@@ -1,144 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_MXC=y
-CONFIG_MACH_MX31ADS_WM1133_EV1=y
-CONFIG_MACH_MX31LILLY=y
-CONFIG_MACH_MX31LITE=y
-CONFIG_MACH_PCM037=y
-CONFIG_MACH_PCM037_EET=y
-CONFIG_MACH_MX31_3DS=y
-CONFIG_MACH_MX31MOBOARD=y
-CONFIG_MACH_QONG=y
-CONFIG_MACH_ARMADILLO5X0=y
-CONFIG_MACH_KZM_ARM11_01=y
-CONFIG_MACH_PCM043=y
-CONFIG_MACH_MX35_3DS=y
-CONFIG_MACH_EUKREA_CPUIMX35=y
-CONFIG_MXC_IRQ_PRIOR=y
-CONFIG_MXC_PWM=y
-CONFIG_ARM_ERRATA_411920=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
-CONFIG_VFP=y
-CONFIG_PM_DEBUG=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_FW_LOADER=m
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_MXC=y
-CONFIG_MTD_UBI=y
-# CONFIG_BLK_DEV is not set
-CONFIG_MISC_DEVICES=y
-CONFIG_EEPROM_AT24=y
-CONFIG_NETDEVICES=y
-CONFIG_SMSC_PHY=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SMSC911X=y
-CONFIG_DNET=y
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_IMX=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_IMX=y
-CONFIG_SERIAL_IMX_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_IMX=y
-CONFIG_SPI=y
-CONFIG_W1=y
-CONFIG_W1_MASTER_MXC=y
-CONFIG_W1_SLAVE_THERM=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_IMX2_WDT=y
-CONFIG_MFD_WM8350_I2C=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_WM8350=y
-CONFIG_MEDIA_SUPPORT=y
-CONFIG_VIDEO_DEV=y
-# CONFIG_RC_CORE is not set
-# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
-CONFIG_SOC_CAMERA=y
-CONFIG_SOC_CAMERA_MT9M001=y
-CONFIG_SOC_CAMERA_MT9M111=y
-CONFIG_SOC_CAMERA_MT9T031=y
-CONFIG_SOC_CAMERA_MT9V022=y
-CONFIG_SOC_CAMERA_TW9910=y
-CONFIG_SOC_CAMERA_OV772X=y
-CONFIG_VIDEO_MX3=y
-# CONFIG_RADIO_ADAPTERS is not set
-CONFIG_FB=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_IMX_SOC=y
-CONFIG_SND_MXC_SOC_WM1133_EV1=y
-CONFIG_SND_SOC_PHYCORE_AC97=y
-CONFIG_SND_SOC_EUKREA_TLV320=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MXC=y
-CONFIG_USB_GADGET=m
-CONFIG_USB_FSL_USB2=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_USB_ULPI=y
-CONFIG_MMC=y
-CONFIG_MMC_MXC=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_MXC=y
-CONFIG_DMADEVICES=y
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_UBIFS_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index b6e65dedfd71..62f8095d46de 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -237,7 +237,7 @@
*/
#ifdef CONFIG_THUMB2_KERNEL
- .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
+ .macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
9999:
.if \inc == 1
\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
@@ -277,7 +277,7 @@
#else /* !CONFIG_THUMB2_KERNEL */
- .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
+ .macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
.rept \rept
9999:
.if \inc == 1
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index af18ceaacf5d..b5dc173d336f 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -83,9 +83,9 @@
* instructions (inline assembly)
*/
#ifdef CONFIG_CPU_USE_DOMAINS
-#define T(instr) #instr "t"
+#define TUSER(instr) #instr "t"
#else
-#define T(instr) #instr
+#define TUSER(instr) #instr
#endif
#else /* __ASSEMBLY__ */
@@ -95,9 +95,9 @@
* instructions
*/
#ifdef CONFIG_CPU_USE_DOMAINS
-#define T(instr) instr ## t
+#define TUSER(instr) instr ## t
#else
-#define T(instr) instr
+#define TUSER(instr) instr
#endif
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 253cc86318bf..7be54690aeec 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -75,9 +75,9 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
#define __futex_atomic_op(insn, ret, oldval, tmp, uaddr, oparg) \
__asm__ __volatile__( \
- "1: " T(ldr) " %1, [%3]\n" \
+ "1: " TUSER(ldr) " %1, [%3]\n" \
" " insn "\n" \
- "2: " T(str) " %0, [%3]\n" \
+ "2: " TUSER(str) " %0, [%3]\n" \
" mov %0, #0\n" \
__futex_atomic_ex_table("%5") \
: "=&r" (ret), "=&r" (oldval), "=&r" (tmp) \
@@ -95,10 +95,10 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
return -EFAULT;
__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
- "1: " T(ldr) " %1, [%4]\n"
+ "1: " TUSER(ldr) " %1, [%4]\n"
" teq %1, %2\n"
" it eq @ explicit IT needed for the 2b label\n"
- "2: " T(streq) " %3, [%4]\n"
+ "2: " TUSER(streq) " %3, [%4]\n"
__futex_atomic_ex_table("%5")
: "+r" (ret), "=&r" (val)
: "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h
index 7151753b0989..c402e9b31f4c 100644
--- a/arch/arm/include/asm/gpio.h
+++ b/arch/arm/include/asm/gpio.h
@@ -2,7 +2,7 @@
#define _ARCH_ARM_GPIO_H
#if CONFIG_ARCH_NR_GPIO > 0
-#define ARCH_NR_GPIO CONFIG_ARCH_NR_GPIO
+#define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO
#endif
/* not all ARM platforms necessarily support this API ... */
diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index c93a22a8b924..917626128a1d 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -25,7 +25,8 @@
#define HWCAP_IDIVT (1 << 18)
#define HWCAP_IDIV (HWCAP_IDIVA | HWCAP_IDIVT)
-#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+#if defined(__KERNEL__)
+#if !defined(__ASSEMBLY__)
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
@@ -33,5 +34,6 @@
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
#endif
+#endif
#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 065d100fa63e..9275828feb3d 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -27,6 +27,7 @@
#include <asm/byteorder.h>
#include <asm/memory.h>
#include <asm/system.h>
+#include <asm-generic/pci_iomap.h>
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
@@ -306,7 +307,6 @@ extern void ioport_unmap(void __iomem *addr);
struct pci_dev;
-extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
/*
diff --git a/arch/arm/include/asm/kprobes.h b/arch/arm/include/asm/kprobes.h
index feec86768f9c..f82ec22eeb11 100644
--- a/arch/arm/include/asm/kprobes.h
+++ b/arch/arm/include/asm/kprobes.h
@@ -24,7 +24,6 @@
#define MAX_INSN_SIZE 2
#define MAX_STACK_SIZE 64 /* 32 would probably be OK */
-#define regs_return_value(regs) ((regs)->ARM_r0)
#define flush_insn_slot(p) do { } while (0)
#define kretprobe_blacklist_size 0
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 186efd4e05c9..d943b7d20f11 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -40,7 +40,7 @@ struct pci_sys_data {
u64 mem_offset; /* bus->cpu memory mapping offset */
unsigned long io_offset; /* bus->cpu IO mapping offset */
struct pci_bus *bus; /* PCI bus */
- struct resource *resource[3]; /* Primary PCI bus resources */
+ struct list_head resources; /* root bus resources (apertures) */
/* Bridge swizzling */
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index b8da2e415e4e..00ca5f92648e 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -6,4 +6,6 @@ struct machine_desc;
extern void arm_memblock_init(struct meminfo *, struct machine_desc *);
+phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
+
#endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 2b1f245db0c6..da337ba57ffd 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -31,18 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
}
#endif /* CONFIG_PCI_DOMAINS */
-#ifdef CONFIG_PCI_HOST_ITE8152
-/* ITE bridge requires setting latency timer to avoid early bus access
- termination by PIC bus mater devices
-*/
-extern void pcibios_set_master(struct pci_dev *dev);
-#else
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
- /* No special bus mastering setup handling */
-}
-#endif
-
static inline void pcibios_penalize_isa_irq(int irq, int active)
{
/* We don't do dynamic PCI IRQ allocation */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 96187ff58c24..451808ba1211 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -189,6 +189,11 @@ static inline int valid_user_regs(struct pt_regs *regs)
return 0;
}
+static inline long regs_return_value(struct pt_regs *regs)
+{
+ return regs->ARM_r0;
+}
+
#define instruction_pointer(regs) (regs)->ARM_pc
#ifdef CONFIG_SMP
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 1e5717afc4ac..ae29293270a3 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -71,12 +71,6 @@ extern void platform_secondary_init(unsigned int cpu);
extern void platform_smp_prepare_cpus(unsigned int);
/*
- * Logical CPU mapping.
- */
-extern int __cpu_logical_map[NR_CPUS];
-#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
-
-/*
* Initial data for bringing up a secondary CPU.
*/
struct secondary_data {
diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index f24c1b9e211d..558d6c80aca9 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -43,4 +43,10 @@ static inline int cache_ops_need_broadcast(void)
}
#endif
+/*
+ * Logical CPU mapping.
+ */
+extern int __cpu_logical_map[];
+#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
+
#endif
diff --git a/arch/arm/include/asm/swab.h b/arch/arm/include/asm/swab.h
index 32ee164a2f6b..b859d82e30ca 100644
--- a/arch/arm/include/asm/swab.h
+++ b/arch/arm/include/asm/swab.h
@@ -22,7 +22,8 @@
# define __SWAB_64_THRU_32__
#endif
-#if defined(__KERNEL__) && __LINUX_ARM_ARCH__ >= 6
+#if defined(__KERNEL__)
+#if __LINUX_ARM_ARCH__ >= 6
static inline __attribute_const__ __u32 __arch_swahb32(__u32 x)
{
@@ -39,8 +40,10 @@ static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
}
#define __arch_swab32 __arch_swab32
-#else
+#endif
+#endif
+#if !defined(__KERNEL__) || __LINUX_ARM_ARCH__ < 6
static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
{
__u32 t;
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 0f30c3a78fc1..d4c24d412a8d 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -129,6 +129,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
/*
* thread information flags:
* TIF_SYSCALL_TRACE - syscall trace active
+ * TIF_SYSCAL_AUDIT - syscall auditing active
* TIF_SIGPENDING - signal pending
* TIF_NEED_RESCHED - rescheduling necessary
* TIF_NOTIFY_RESUME - callback before returning to user
@@ -139,6 +140,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
#define TIF_NEED_RESCHED 1
#define TIF_NOTIFY_RESUME 2 /* callback before returning to user */
#define TIF_SYSCALL_TRACE 8
+#define TIF_SYSCALL_AUDIT 9
#define TIF_POLLING_NRFLAG 16
#define TIF_USING_IWMMXT 17
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
@@ -149,11 +151,15 @@ extern void vfp_flush_hwstate(struct thread_info *);
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
+#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
#define _TIF_POLLING_NRFLAG (1 << TIF_POLLING_NRFLAG)
#define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT)
#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
+/* Checks for any syscall work in entry-common.S */
+#define _TIF_SYSCALL_WORK (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT)
+
/*
* Change these and you break ASM code in entry-common.S
*/
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 5d3ed7e38561..314d4664eae7 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -198,7 +198,15 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
unsigned long addr)
{
pgtable_page_dtor(pte);
- tlb_add_flush(tlb, addr);
+
+ /*
+ * With the classic ARM MMU, a pte page has two corresponding pmd
+ * entries, each covering 1MB.
+ */
+ addr &= PMD_MASK;
+ tlb_add_flush(tlb, addr + SZ_1M - PAGE_SIZE);
+ tlb_add_flush(tlb, addr + SZ_1M);
+
tlb_remove_page(tlb, pte);
}
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index b293616a1a1a..2958976d867b 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do { \
#define __get_user_asm_byte(x,addr,err) \
__asm__ __volatile__( \
- "1: " T(ldrb) " %1,[%2],#0\n" \
+ "1: " TUSER(ldrb) " %1,[%2],#0\n" \
"2:\n" \
" .pushsection .fixup,\"ax\"\n" \
" .align 2\n" \
@@ -263,7 +263,7 @@ do { \
#define __get_user_asm_word(x,addr,err) \
__asm__ __volatile__( \
- "1: " T(ldr) " %1,[%2],#0\n" \
+ "1: " TUSER(ldr) " %1,[%2],#0\n" \
"2:\n" \
" .pushsection .fixup,\"ax\"\n" \
" .align 2\n" \
@@ -308,7 +308,7 @@ do { \
#define __put_user_asm_byte(x,__pu_addr,err) \
__asm__ __volatile__( \
- "1: " T(strb) " %1,[%2],#0\n" \
+ "1: " TUSER(strb) " %1,[%2],#0\n" \
"2:\n" \
" .pushsection .fixup,\"ax\"\n" \
" .align 2\n" \
@@ -341,7 +341,7 @@ do { \
#define __put_user_asm_word(x,__pu_addr,err) \
__asm__ __volatile__( \
- "1: " T(str) " %1,[%2],#0\n" \
+ "1: " TUSER(str) " %1,[%2],#0\n" \
"2:\n" \
" .pushsection .fixup,\"ax\"\n" \
" .align 2\n" \
@@ -366,10 +366,10 @@ do { \
#define __put_user_asm_dword(x,__pu_addr,err) \
__asm__ __volatile__( \
- ARM( "1: " T(str) " " __reg_oper1 ", [%1], #4\n" ) \
- ARM( "2: " T(str) " " __reg_oper0 ", [%1]\n" ) \
- THUMB( "1: " T(str) " " __reg_oper1 ", [%1]\n" ) \
- THUMB( "2: " T(str) " " __reg_oper0 ", [%1, #4]\n" ) \
+ ARM( "1: " TUSER(str) " " __reg_oper1 ", [%1], #4\n" ) \
+ ARM( "2: " TUSER(str) " " __reg_oper0 ", [%1]\n" ) \
+ THUMB( "1: " TUSER(str) " " __reg_oper1 ", [%1]\n" ) \
+ THUMB( "2: " TUSER(str) " " __reg_oper0 ", [%1, #4]\n" ) \
"3:\n" \
" .pushsection .fixup,\"ax\"\n" \
" .align 2\n" \
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
index bc631161e9c6..f5989f46b4d2 100644
--- a/arch/arm/include/asm/unified.h
+++ b/arch/arm/include/asm/unified.h
@@ -37,8 +37,8 @@
#define THUMB(x...) x
#ifdef __ASSEMBLY__
#define W(instr) instr.w
-#endif
#define BSYM(sym) sym + 1
+#endif
#else /* !CONFIG_THUMB2_KERNEL */
@@ -49,8 +49,8 @@
#define THUMB(x...)
#ifdef __ASSEMBLY__
#define W(instr) instr
-#endif
#define BSYM(sym) sym
+#endif
#endif /* CONFIG_THUMB2_KERNEL */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 4a1123783806..512cd1473454 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -427,7 +427,8 @@
/*
* The following syscalls are obsolete and no longer available for EABI.
*/
-#if defined(__ARM_EABI__) && !defined(__KERNEL__)
+#if !defined(__KERNEL__)
+#if defined(__ARM_EABI__)
#undef __NR_time
#undef __NR_umount
#undef __NR_stime
@@ -441,6 +442,7 @@
#undef __NR_syscall
#undef __NR_ipc
#endif
+#endif
#ifdef __KERNEL__
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index b530e9116a0c..f58ba3589908 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -316,21 +316,6 @@ pdev_fixup_device_resources(struct pci_sys_data *root, struct pci_dev *dev)
}
}
-static void __devinit
-pbus_assign_bus_resources(struct pci_bus *bus, struct pci_sys_data *root)
-{
- struct pci_dev *dev = bus->self;
- int i;
-
- if (!dev) {
- /*
- * Assign root bus resources.
- */
- for (i = 0; i < 3; i++)
- bus->resource[i] = root->resource[i];
- }
-}
-
/*
* pcibios_fixup_bus - Called after each bus is probed,
* but before its children are examined.
@@ -341,8 +326,6 @@ void pcibios_fixup_bus(struct pci_bus *bus)
struct pci_dev *dev;
u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
- pbus_assign_bus_resources(bus, root);
-
/*
* Walk the devices on this bus, working out what we can
* and can't support.
@@ -508,12 +491,18 @@ static void __init pcibios_init_hw(struct hw_pci *hw)
sys->busnr = busnr;
sys->swizzle = hw->swizzle;
sys->map_irq = hw->map_irq;
- sys->resource[0] = &ioport_resource;
- sys->resource[1] = &iomem_resource;
+ INIT_LIST_HEAD(&sys->resources);
ret = hw->setup(nr, sys);
if (ret > 0) {
+ if (list_empty(&sys->resources)) {
+ pci_add_resource(&sys->resources,
+ &ioport_resource);
+ pci_add_resource(&sys->resources,
+ &iomem_resource);
+ }
+
sys->bus = hw->scan(nr, sys);
if (!sys->bus)
@@ -571,6 +560,13 @@ void __init pci_common_init(struct hw_pci *hw)
}
}
+#ifndef CONFIG_PCI_HOST_ITE8152
+void pcibios_set_master(struct pci_dev *dev)
+{
+ /* No special bus mastering setup handling */
+}
+#endif
+
char * __init pcibios_setup(char *str)
{
if (!strcmp(str, "debug")) {
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 3a456c6c7005..be16a48007b4 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -790,7 +790,7 @@ __kuser_cmpxchg64: @ 0xffff0f60
smp_dmb arm
rsbs r0, r3, #0 @ set returned val and C flag
ldmfd sp!, {r4, r5, r6, r7}
- bx lr
+ usr_ret lr
#elif !defined(CONFIG_SMP)
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index b2a27b6b0046..9fd0ba90c1d2 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -87,7 +87,7 @@ ENTRY(ret_from_fork)
get_thread_info tsk
ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing
mov why, #1
- tst r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
+ tst r1, #_TIF_SYSCALL_WORK @ are we tracing syscalls?
beq ret_slow_syscall
mov r1, sp
mov r0, #1 @ trace exit [IP = 1]
@@ -149,6 +149,11 @@ ENDPROC(ret_from_fork)
#endif
#endif
+.macro mcount_adjust_addr rd, rn
+ bic \rd, \rn, #1 @ clear the Thumb bit if present
+ sub \rd, \rd, #MCOUNT_INSN_SIZE
+.endm
+
.macro __mcount suffix
mcount_enter
ldr r0, =ftrace_trace_function
@@ -173,8 +178,7 @@ ENDPROC(ret_from_fork)
mcount_exit
1: mcount_get_lr r1 @ lr of instrumented func
- mov r0, lr @ instrumented function
- sub r0, r0, #MCOUNT_INSN_SIZE
+ mcount_adjust_addr r0, lr @ instrumented function
adr lr, BSYM(2f)
mov pc, r2
2: mcount_exit
@@ -184,8 +188,7 @@ ENDPROC(ret_from_fork)
mcount_enter
mcount_get_lr r1 @ lr of instrumented func
- mov r0, lr @ instrumented function
- sub r0, r0, #MCOUNT_INSN_SIZE
+ mcount_adjust_addr r0, lr @ instrumented function
.globl ftrace_call\suffix
ftrace_call\suffix:
@@ -205,11 +208,11 @@ ftrace_graph_call\suffix:
#ifdef CONFIG_DYNAMIC_FTRACE
@ called from __ftrace_caller, saved in mcount_enter
ldr r1, [sp, #16] @ instrumented routine (func)
+ mcount_adjust_addr r1, r1
#else
@ called from __mcount, untouched in lr
- mov r1, lr @ instrumented routine (func)
+ mcount_adjust_addr r1, lr @ instrumented routine (func)
#endif
- sub r1, r1, #MCOUNT_INSN_SIZE
mov r2, fp @ frame pointer
bl prepare_ftrace_return
mcount_exit
@@ -443,7 +446,7 @@ ENTRY(vector_swi)
1:
#endif
- tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
+ tst r10, #_TIF_SYSCALL_WORK @ are we tracing syscalls?
bne __sys_trace
cmp scno, #NR_syscalls @ check upper syscall limit
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 14e277d2ff91..6d5791144066 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -99,6 +99,14 @@ ENTRY(stext)
THUMB( it eq ) @ force fixup-able long branch encoding
beq __error_p @ yes, error 'p'
+#ifdef CONFIG_ARM_LPAE
+ mrc p15, 0, r3, c0, c1, 4 @ read ID_MMFR0
+ and r3, r3, #0xf @ extract VMSA support
+ cmp r3, #5 @ long-descriptor translation table format?
+ THUMB( it lo ) @ force fixup-able long branch encoding
+ blo __error_p @ only classic page table format
+#endif
+
#ifndef CONFIG_XIP_KERNEL
adr r3, 2f
ldmia r3, {r4, r8}
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 460bbbb6b885..6933244c68f9 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -469,6 +469,20 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
+ [C(NODE)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ },
};
/*
@@ -579,6 +593,20 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
},
},
+ [C(NODE)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
+ [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
+ },
+ },
};
/*
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 483727ad6892..e33870ff0ac0 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -699,10 +699,13 @@ static int vfp_set(struct task_struct *target,
{
int ret;
struct thread_info *thread = task_thread_info(target);
- struct vfp_hard_struct new_vfp = thread->vfpstate.hard;
+ struct vfp_hard_struct new_vfp;
const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
+ vfp_sync_hwstate(thread);
+ new_vfp = thread->vfpstate.hard;
+
ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
&new_vfp.fpregs,
user_fpregs_offset,
@@ -723,9 +726,8 @@ static int vfp_set(struct task_struct *target,
if (ret)
return ret;
- vfp_sync_hwstate(thread);
- thread->vfpstate.hard = new_vfp;
vfp_flush_hwstate(thread);
+ thread->vfpstate.hard = new_vfp;
return 0;
}
@@ -906,11 +908,6 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
{
unsigned long ip;
- if (!test_thread_flag(TIF_SYSCALL_TRACE))
- return scno;
- if (!(current->ptrace & PT_PTRACED))
- return scno;
-
/*
* Save IP. IP is used to denote syscall entry/exit:
* IP = 0 -> entry, = 1 -> exit
@@ -918,6 +915,17 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
ip = regs->ARM_ip;
regs->ARM_ip = why;
+ if (!ip)
+ audit_syscall_exit(regs);
+ else
+ audit_syscall_entry(AUDIT_ARCH_ARMEB, scno, regs->ARM_r0,
+ regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
+
+ if (!test_thread_flag(TIF_SYSCALL_TRACE))
+ return scno;
+ if (!(current->ptrace & PT_PTRACED))
+ return scno;
+
current_thread_info()->syscall = scno;
/* the 0x80 provides a way for the tracing parent to distinguish
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 129fbd55bde8..a255c39612ca 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/kexec.h>
#include <linux/of_fdt.h>
-#include <linux/crash_dump.h>
#include <linux/root_dev.h>
#include <linux/cpu.h>
#include <linux/interrupt.h>
@@ -160,7 +159,7 @@ static struct resource mem_res[] = {
.flags = IORESOURCE_MEM
},
{
- .name = "Kernel text",
+ .name = "Kernel code",
.start = 0,
.end = 0,
.flags = IORESOURCE_MEM
@@ -427,6 +426,20 @@ void cpu_init(void)
: "r14");
}
+int __cpu_logical_map[NR_CPUS];
+
+void __init smp_setup_processor_id(void)
+{
+ int i;
+ u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
+
+ cpu_logical_map(0) = cpu;
+ for (i = 1; i < NR_CPUS; ++i)
+ cpu_logical_map(i) = i == cpu ? 0 : i;
+
+ printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
+}
+
static void __init setup_processor(void)
{
struct proc_info_list *list;
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 0340224cf73c..9e617bd4a146 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -227,6 +227,8 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
return -EINVAL;
+ vfp_flush_hwstate(thread);
+
/*
* Copy the floating point registers. There can be unused
* registers see asm/hwcap.h for details.
@@ -251,9 +253,6 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
__get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
__get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
- if (!err)
- vfp_flush_hwstate(thread);
-
return err ? -EFAULT : 0;
}
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 57db122a4f62..cdeb727527d3 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -233,20 +233,6 @@ void __ref cpu_die(void)
}
#endif /* CONFIG_HOTPLUG_CPU */
-int __cpu_logical_map[NR_CPUS];
-
-void __init smp_setup_processor_id(void)
-{
- int i;
- u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0;
-
- cpu_logical_map(0) = cpu;
- for (i = 1; i < NR_CPUS; ++i)
- cpu_logical_map(i) = i == cpu ? 0 : i;
-
- printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu);
-}
-
/*
* Called by both boot and secondaries to move global data into
* per-processor storage.
@@ -443,9 +429,7 @@ static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
static void ipi_timer(void)
{
struct clock_event_device *evt = &__get_cpu_var(percpu_clockevent);
- irq_enter();
evt->event_handler(evt);
- irq_exit();
}
#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
@@ -548,7 +532,9 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
switch (ipinr) {
case IPI_TIMER:
+ irq_enter();
ipi_timer();
+ irq_exit();
break;
case IPI_RESCHEDULE:
@@ -556,15 +542,21 @@ void handle_IPI(int ipinr, struct pt_regs *regs)
break;
case IPI_CALL_FUNC:
+ irq_enter();
generic_smp_call_function_interrupt();
+ irq_exit();
break;
case IPI_CALL_FUNC_SINGLE:
+ irq_enter();
generic_smp_call_function_single_interrupt();
+ irq_exit();
break;
case IPI_CPU_STOP:
+ irq_enter();
ipi_cpu_stop(cpu);
+ irq_exit();
break;
default:
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index c8e938553d47..4285daa077b0 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -252,6 +252,8 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
else
twd_calibrate_rate();
+ __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
+
clk->name = "local_timer";
clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
CLOCK_EVT_FEAT_C3STOP;
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index f76e75548670..1e19691e0406 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -4,6 +4,7 @@
*/
#include <asm-generic/vmlinux.lds.h>
+#include <asm/cache.h>
#include <asm/thread_info.h>
#include <asm/memory.h>
#include <asm/page.h>
@@ -181,7 +182,7 @@ SECTIONS
}
#endif
- PERCPU_SECTION(32)
+ PERCPU_SECTION(L1_CACHE_BYTES)
#ifdef CONFIG_XIP_KERNEL
__data_loc = ALIGN(4); /* location in binary */
@@ -212,13 +213,13 @@ SECTIONS
#endif
NOSAVE_DATA
- CACHELINE_ALIGNED_DATA(32)
- READ_MOSTLY_DATA(32)
+ CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES)
+ READ_MOSTLY_DATA(L1_CACHE_BYTES)
/*
* The exception fixup table (might need resorting at runtime)
*/
- . = ALIGN(32);
+ . = ALIGN(4);
__start___ex_table = .;
#ifdef CONFIG_MMU
*(__ex_table)
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 1b049cd7a49a..11093a7c3e32 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -31,18 +31,18 @@
#include <asm/domain.h>
ENTRY(__get_user_1)
-1: T(ldrb) r2, [r0]
+1: TUSER(ldrb) r2, [r0]
mov r0, #0
mov pc, lr
ENDPROC(__get_user_1)
ENTRY(__get_user_2)
#ifdef CONFIG_THUMB2_KERNEL
-2: T(ldrb) r2, [r0]
-3: T(ldrb) r3, [r0, #1]
+2: TUSER(ldrb) r2, [r0]
+3: TUSER(ldrb) r3, [r0, #1]
#else
-2: T(ldrb) r2, [r0], #1
-3: T(ldrb) r3, [r0]
+2: TUSER(ldrb) r2, [r0], #1
+3: TUSER(ldrb) r3, [r0]
#endif
#ifndef __ARMEB__
orr r2, r2, r3, lsl #8
@@ -54,7 +54,7 @@ ENTRY(__get_user_2)
ENDPROC(__get_user_2)
ENTRY(__get_user_4)
-4: T(ldr) r2, [r0]
+4: TUSER(ldr) r2, [r0]
mov r0, #0
mov pc, lr
ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index c023fc11e86c..7db25990c589 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -31,7 +31,7 @@
#include <asm/domain.h>
ENTRY(__put_user_1)
-1: T(strb) r2, [r0]
+1: TUSER(strb) r2, [r0]
mov r0, #0
mov pc, lr
ENDPROC(__put_user_1)
@@ -40,19 +40,19 @@ ENTRY(__put_user_2)
mov ip, r2, lsr #8
#ifdef CONFIG_THUMB2_KERNEL
#ifndef __ARMEB__
-2: T(strb) r2, [r0]
-3: T(strb) ip, [r0, #1]
+2: TUSER(strb) r2, [r0]
+3: TUSER(strb) ip, [r0, #1]
#else
-2: T(strb) ip, [r0]
-3: T(strb) r2, [r0, #1]
+2: TUSER(strb) ip, [r0]
+3: TUSER(strb) r2, [r0, #1]
#endif
#else /* !CONFIG_THUMB2_KERNEL */
#ifndef __ARMEB__
-2: T(strb) r2, [r0], #1
-3: T(strb) ip, [r0]
+2: TUSER(strb) r2, [r0], #1
+3: TUSER(strb) ip, [r0]
#else
-2: T(strb) ip, [r0], #1
-3: T(strb) r2, [r0]
+2: TUSER(strb) ip, [r0], #1
+3: TUSER(strb) r2, [r0]
#endif
#endif /* CONFIG_THUMB2_KERNEL */
mov r0, #0
@@ -60,18 +60,18 @@ ENTRY(__put_user_2)
ENDPROC(__put_user_2)
ENTRY(__put_user_4)
-4: T(str) r2, [r0]
+4: TUSER(str) r2, [r0]
mov r0, #0
mov pc, lr
ENDPROC(__put_user_4)
ENTRY(__put_user_8)
#ifdef CONFIG_THUMB2_KERNEL
-5: T(str) r2, [r0]
-6: T(str) r3, [r0, #4]
+5: TUSER(str) r2, [r0]
+6: TUSER(str) r3, [r0, #4]
#else
-5: T(str) r2, [r0], #4
-6: T(str) r3, [r0]
+5: TUSER(str) r2, [r0], #4
+6: TUSER(str) r3, [r0]
#endif
mov r0, #0
mov pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index d0ece2aeb70d..5c908b1cb8ed 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -32,11 +32,11 @@
rsb ip, ip, #4
cmp ip, #2
ldrb r3, [r1], #1
-USER( T(strb) r3, [r0], #1) @ May fault
+USER( TUSER( strb) r3, [r0], #1) @ May fault
ldrgeb r3, [r1], #1
-USER( T(strgeb) r3, [r0], #1) @ May fault
+USER( TUSER( strgeb) r3, [r0], #1) @ May fault
ldrgtb r3, [r1], #1
-USER( T(strgtb) r3, [r0], #1) @ May fault
+USER( TUSER( strgtb) r3, [r0], #1) @ May fault
sub r2, r2, ip
b .Lc2u_dest_aligned
@@ -59,7 +59,7 @@ ENTRY(__copy_to_user)
addmi ip, r2, #4
bmi .Lc2u_0nowords
ldr r3, [r1], #4
-USER( T(str) r3, [r0], #4) @ May fault
+USER( TUSER( str) r3, [r0], #4) @ May fault
mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
rsb ip, ip, #0
movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -88,18 +88,18 @@ USER( T(str) r3, [r0], #4) @ May fault
stmneia r0!, {r3 - r4} @ Shouldnt fault
tst ip, #4
ldrne r3, [r1], #4
- T(strne) r3, [r0], #4 @ Shouldnt fault
+ TUSER( strne) r3, [r0], #4 @ Shouldnt fault
ands ip, ip, #3
beq .Lc2u_0fupi
.Lc2u_0nowords: teq ip, #0
beq .Lc2u_finished
.Lc2u_nowords: cmp ip, #2
ldrb r3, [r1], #1
-USER( T(strb) r3, [r0], #1) @ May fault
+USER( TUSER( strb) r3, [r0], #1) @ May fault
ldrgeb r3, [r1], #1
-USER( T(strgeb) r3, [r0], #1) @ May fault
+USER( TUSER( strgeb) r3, [r0], #1) @ May fault
ldrgtb r3, [r1], #1
-USER( T(strgtb) r3, [r0], #1) @ May fault
+USER( TUSER( strgtb) r3, [r0], #1) @ May fault
b .Lc2u_finished
.Lc2u_not_enough:
@@ -120,7 +120,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
mov r3, r7, pull #8
ldr r7, [r1], #4
orr r3, r3, r7, push #24
-USER( T(str) r3, [r0], #4) @ May fault
+USER( TUSER( str) r3, [r0], #4) @ May fault
mov ip, r0, lsl #32 - PAGE_SHIFT
rsb ip, ip, #0
movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -155,18 +155,18 @@ USER( T(str) r3, [r0], #4) @ May fault
movne r3, r7, pull #8
ldrne r7, [r1], #4
orrne r3, r3, r7, push #24
- T(strne) r3, [r0], #4 @ Shouldnt fault
+ TUSER( strne) r3, [r0], #4 @ Shouldnt fault
ands ip, ip, #3
beq .Lc2u_1fupi
.Lc2u_1nowords: mov r3, r7, get_byte_1
teq ip, #0
beq .Lc2u_finished
cmp ip, #2
-USER( T(strb) r3, [r0], #1) @ May fault
+USER( TUSER( strb) r3, [r0], #1) @ May fault
movge r3, r7, get_byte_2
-USER( T(strgeb) r3, [r0], #1) @ May fault
+USER( TUSER( strgeb) r3, [r0], #1) @ May fault
movgt r3, r7, get_byte_3
-USER( T(strgtb) r3, [r0], #1) @ May fault
+USER( TUSER( strgtb) r3, [r0], #1) @ May fault
b .Lc2u_finished
.Lc2u_2fupi: subs r2, r2, #4
@@ -175,7 +175,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
mov r3, r7, pull #16
ldr r7, [r1], #4
orr r3, r3, r7, push #16
-USER( T(str) r3, [r0], #4) @ May fault
+USER( TUSER( str) r3, [r0], #4) @ May fault
mov ip, r0, lsl #32 - PAGE_SHIFT
rsb ip, ip, #0
movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -210,18 +210,18 @@ USER( T(str) r3, [r0], #4) @ May fault
movne r3, r7, pull #16
ldrne r7, [r1], #4
orrne r3, r3, r7, push #16
- T(strne) r3, [r0], #4 @ Shouldnt fault
+ TUSER( strne) r3, [r0], #4 @ Shouldnt fault
ands ip, ip, #3
beq .Lc2u_2fupi
.Lc2u_2nowords: mov r3, r7, get_byte_2
teq ip, #0
beq .Lc2u_finished
cmp ip, #2
-USER( T(strb) r3, [r0], #1) @ May fault
+USER( TUSER( strb) r3, [r0], #1) @ May fault
movge r3, r7, get_byte_3
-USER( T(strgeb) r3, [r0], #1) @ May fault
+USER( TUSER( strgeb) r3, [r0], #1) @ May fault
ldrgtb r3, [r1], #0
-USER( T(strgtb) r3, [r0], #1) @ May fault
+USER( TUSER( strgtb) r3, [r0], #1) @ May fault
b .Lc2u_finished
.Lc2u_3fupi: subs r2, r2, #4
@@ -230,7 +230,7 @@ USER( T(strgtb) r3, [r0], #1) @ May fault
mov r3, r7, pull #24
ldr r7, [r1], #4
orr r3, r3, r7, push #8
-USER( T(str) r3, [r0], #4) @ May fault
+USER( TUSER( str) r3, [r0], #4) @ May fault
mov ip, r0, lsl #32 - PAGE_SHIFT
rsb ip, ip, #0
movs ip, ip, lsr #32 - PAGE_SHIFT
@@ -265,18 +265,18 @@ USER( T(str) r3, [r0], #4) @ May fault
movne r3, r7, pull #24
ldrne r7, [r1], #4
orrne r3, r3, r7, push #8
- T(strne) r3, [r0], #4 @ Shouldnt fault
+ TUSER( strne) r3, [r0], #4 @ Shouldnt fault
ands ip, ip, #3
beq .Lc2u_3fupi
.Lc2u_3nowords: mov r3, r7, get_byte_3
teq ip, #0
beq .Lc2u_finished
cmp ip, #2
-USER( T(strb) r3, [r0], #1) @ May fault
+USER( TUSER( strb) r3, [r0], #1) @ May fault
ldrgeb r3, [r1], #1
-USER( T(strgeb) r3, [r0], #1) @ May fault
+USER( TUSER( strgeb) r3, [r0], #1) @ May fault
ldrgtb r3, [r1], #0
-USER( T(strgtb) r3, [r0], #1) @ May fault
+USER( TUSER( strgtb) r3, [r0], #1) @ May fault
b .Lc2u_finished
ENDPROC(__copy_to_user)
@@ -295,11 +295,11 @@ ENDPROC(__copy_to_user)
.Lcfu_dest_not_aligned:
rsb ip, ip, #4
cmp ip, #2
-USER( T(ldrb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrb) r3, [r1], #1) @ May fault
strb r3, [r0], #1
-USER( T(ldrgeb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
strgeb r3, [r0], #1
-USER( T(ldrgtb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
strgtb r3, [r0], #1
sub r2, r2, ip
b .Lcfu_dest_aligned
@@ -322,7 +322,7 @@ ENTRY(__copy_from_user)
.Lcfu_0fupi: subs r2, r2, #4
addmi ip, r2, #4
bmi .Lcfu_0nowords
-USER( T(ldr) r3, [r1], #4)
+USER( TUSER( ldr) r3, [r1], #4)
str r3, [r0], #4
mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
rsb ip, ip, #0
@@ -351,18 +351,18 @@ USER( T(ldr) r3, [r1], #4)
ldmneia r1!, {r3 - r4} @ Shouldnt fault
stmneia r0!, {r3 - r4}
tst ip, #4
- T(ldrne) r3, [r1], #4 @ Shouldnt fault
+ TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault
strne r3, [r0], #4
ands ip, ip, #3
beq .Lcfu_0fupi
.Lcfu_0nowords: teq ip, #0
beq .Lcfu_finished
.Lcfu_nowords: cmp ip, #2
-USER( T(ldrb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrb) r3, [r1], #1) @ May fault
strb r3, [r0], #1
-USER( T(ldrgeb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
strgeb r3, [r0], #1
-USER( T(ldrgtb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
strgtb r3, [r0], #1
b .Lcfu_finished
@@ -375,7 +375,7 @@ USER( T(ldrgtb) r3, [r1], #1) @ May fault
.Lcfu_src_not_aligned:
bic r1, r1, #3
-USER( T(ldr) r7, [r1], #4) @ May fault
+USER( TUSER( ldr) r7, [r1], #4) @ May fault
cmp ip, #2
bgt .Lcfu_3fupi
beq .Lcfu_2fupi
@@ -383,7 +383,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
addmi ip, r2, #4
bmi .Lcfu_1nowords
mov r3, r7, pull #8
-USER( T(ldr) r7, [r1], #4) @ May fault
+USER( TUSER( ldr) r7, [r1], #4) @ May fault
orr r3, r3, r7, push #24
str r3, [r0], #4
mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -418,7 +418,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
stmneia r0!, {r3 - r4}
tst ip, #4
movne r3, r7, pull #8
-USER( T(ldrne) r7, [r1], #4) @ May fault
+USER( TUSER( ldrne) r7, [r1], #4) @ May fault
orrne r3, r3, r7, push #24
strne r3, [r0], #4
ands ip, ip, #3
@@ -438,7 +438,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
addmi ip, r2, #4
bmi .Lcfu_2nowords
mov r3, r7, pull #16
-USER( T(ldr) r7, [r1], #4) @ May fault
+USER( TUSER( ldr) r7, [r1], #4) @ May fault
orr r3, r3, r7, push #16
str r3, [r0], #4
mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -474,7 +474,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
stmneia r0!, {r3 - r4}
tst ip, #4
movne r3, r7, pull #16
-USER( T(ldrne) r7, [r1], #4) @ May fault
+USER( TUSER( ldrne) r7, [r1], #4) @ May fault
orrne r3, r3, r7, push #16
strne r3, [r0], #4
ands ip, ip, #3
@@ -486,7 +486,7 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
strb r3, [r0], #1
movge r3, r7, get_byte_3
strgeb r3, [r0], #1
-USER( T(ldrgtb) r3, [r1], #0) @ May fault
+USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
strgtb r3, [r0], #1
b .Lcfu_finished
@@ -494,7 +494,7 @@ USER( T(ldrgtb) r3, [r1], #0) @ May fault
addmi ip, r2, #4
bmi .Lcfu_3nowords
mov r3, r7, pull #24
-USER( T(ldr) r7, [r1], #4) @ May fault
+USER( TUSER( ldr) r7, [r1], #4) @ May fault
orr r3, r3, r7, push #8
str r3, [r0], #4
mov ip, r1, lsl #32 - PAGE_SHIFT
@@ -529,7 +529,7 @@ USER( T(ldr) r7, [r1], #4) @ May fault
stmneia r0!, {r3 - r4}
tst ip, #4
movne r3, r7, pull #24
-USER( T(ldrne) r7, [r1], #4) @ May fault
+USER( TUSER( ldrne) r7, [r1], #4) @ May fault
orrne r3, r3, r7, push #8
strne r3, [r0], #4
ands ip, ip, #3
@@ -539,9 +539,9 @@ USER( T(ldrne) r7, [r1], #4) @ May fault
beq .Lcfu_finished
cmp ip, #2
strb r3, [r0], #1
-USER( T(ldrgeb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
strgeb r3, [r0], #1
-USER( T(ldrgtb) r3, [r1], #1) @ May fault
+USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
strgtb r3, [r0], #1
b .Lcfu_finished
ENDPROC(__copy_from_user)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 4f991f295284..71feb00a1e99 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -18,6 +18,12 @@ config HAVE_AT91_USART4
config HAVE_AT91_USART5
bool
+config AT91_SAM9_ALT_RESET
+ bool
+
+config AT91_SAM9G45_RESET
+ bool
+
menu "Atmel AT91 System-on-Chip"
choice
@@ -39,6 +45,7 @@ config ARCH_AT91SAM9260
select HAVE_AT91_USART4
select HAVE_AT91_USART5
select HAVE_NET_MACB
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9261
bool "AT91SAM9261"
@@ -46,6 +53,7 @@ config ARCH_AT91SAM9261
select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU0
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9G10
bool "AT91SAM9G10"
@@ -53,6 +61,7 @@ config ARCH_AT91SAM9G10
select GENERIC_CLOCKEVENTS
select HAVE_AT91_DBGU0
select HAVE_FB_ATMEL
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9263
bool "AT91SAM9263"
@@ -61,6 +70,7 @@ config ARCH_AT91SAM9263
select HAVE_FB_ATMEL
select HAVE_NET_MACB
select HAVE_AT91_DBGU1
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
@@ -69,6 +79,7 @@ config ARCH_AT91SAM9RL
select HAVE_AT91_USART3
select HAVE_FB_ATMEL
select HAVE_AT91_DBGU0
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9G20
bool "AT91SAM9G20"
@@ -79,6 +90,7 @@ config ARCH_AT91SAM9G20
select HAVE_AT91_USART4
select HAVE_AT91_USART5
select HAVE_NET_MACB
+ select AT91_SAM9_ALT_RESET
config ARCH_AT91SAM9G45
bool "AT91SAM9G45"
@@ -88,6 +100,7 @@ config ARCH_AT91SAM9G45
select HAVE_FB_ATMEL
select HAVE_NET_MACB
select HAVE_AT91_DBGU1
+ select AT91_SAM9G45_RESET
config ARCH_AT91CAP9
bool "AT91CAP9"
@@ -96,6 +109,7 @@ config ARCH_AT91CAP9
select HAVE_FB_ATMEL
select HAVE_NET_MACB
select HAVE_AT91_DBGU1
+ select AT91_SAM9G45_RESET
config ARCH_AT91X40
bool "AT91x40"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 242174f9f355..705e1fbded39 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -8,15 +8,17 @@ obj-n :=
obj- :=
obj-$(CONFIG_AT91_PMC_UNIT) += clock.o
+obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o
+obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o
# CPU-specific support
obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o
+obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
diff --git a/arch/arm/mach-at91/at91cap9.c b/arch/arm/mach-at91/at91cap9.c
index edb879ac04c8..a42edc25a87e 100644
--- a/arch/arm/mach-at91/at91cap9.c
+++ b/arch/arm/mach-at91/at91cap9.c
@@ -21,7 +21,6 @@
#include <mach/cpu.h>
#include <mach/at91cap9.h>
#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
#include "soc.h"
#include "generic.h"
@@ -314,11 +313,6 @@ static struct at91_gpio_bank at91cap9_gpio[] __initdata = {
}
};
-static void at91cap9_restart(char mode, const char *cmd)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
/* --------------------------------------------------------------------
* AT91CAP9 processor initialization
* -------------------------------------------------------------------- */
@@ -331,13 +325,14 @@ static void __init at91cap9_map_io(void)
static void __init at91cap9_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91CAP9_BASE_SHDWC);
+ at91_ioremap_rstc(AT91CAP9_BASE_RSTC);
at91sam926x_ioremap_pit(AT91CAP9_BASE_PIT);
at91sam9_ioremap_smc(0, AT91CAP9_BASE_SMC);
}
static void __init at91cap9_initialize(void)
{
- arm_pm_restart = at91cap9_restart;
+ arm_pm_restart = at91sam9g45_restart;
at91_extern_irq = (1 << AT91CAP9_ID_IRQ0) | (1 << AT91CAP9_ID_IRQ1);
/* Register GPIO subsystem */
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 5e46e4a96430..d4036ba43612 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -323,6 +323,7 @@ static void __init at91sam9260_map_io(void)
static void __init at91sam9260_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9260_BASE_SHDWC);
+ at91_ioremap_rstc(AT91SAM9260_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9260_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9260_BASE_SMC);
}
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index b85b9ea60170..023c2ff138df 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -281,6 +281,7 @@ static void __init at91sam9261_map_io(void)
static void __init at91sam9261_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9261_BASE_SHDWC);
+ at91_ioremap_rstc(AT91SAM9261_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9261_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9261_BASE_SMC);
}
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index 79e3669b1117..75e876c258af 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -301,6 +301,7 @@ static void __init at91sam9263_map_io(void)
static void __init at91sam9263_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9263_BASE_SHDWC);
+ at91_ioremap_rstc(AT91SAM9263_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9263_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9263_BASE_SMC0);
at91sam9_ioremap_smc(1, AT91SAM9263_BASE_SMC1);
diff --git a/arch/arm/mach-at91/at91sam9_alt_reset.S b/arch/arm/mach-at91/at91sam9_alt_reset.S
index d3f931c5942e..518e42377171 100644
--- a/arch/arm/mach-at91/at91sam9_alt_reset.S
+++ b/arch/arm/mach-at91/at91sam9_alt_reset.S
@@ -23,7 +23,8 @@
.globl at91sam9_alt_restart
at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
- ldr r1, .at91_va_base_rstc_cr
+ ldr r1, =at91_rstc_base
+ ldr r1, [r1]
mov r2, #1
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
@@ -33,11 +34,9 @@ at91sam9_alt_restart: ldr r0, .at91_va_base_sdramc @ preload constants
str r2, [r0, #AT91_SDRAMC_TR] @ disable SDRAM access
str r3, [r0, #AT91_SDRAMC_LPR] @ power down SDRAM
- str r4, [r1] @ reset processor
+ str r4, [r1, #AT91_RSTC_CR] @ reset processor
b .
.at91_va_base_sdramc:
.word AT91_VA_BASE_SYS + AT91_SDRAMC0
-.at91_va_base_rstc_cr:
- .word AT91_VA_BASE_SYS + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 7032dd32cdf0..1cb6a96b1c1e 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,7 +18,6 @@
#include <asm/mach/map.h>
#include <mach/at91sam9g45.h>
#include <mach/at91_pmc.h>
-#include <mach/at91_rstc.h>
#include <mach/cpu.h>
#include "soc.h"
@@ -318,11 +317,6 @@ static struct at91_gpio_bank at91sam9g45_gpio[] __initdata = {
}
};
-static void at91sam9g45_restart(char mode, const char *cmd)
-{
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
-}
-
/* --------------------------------------------------------------------
* AT91SAM9G45 processor initialization
* -------------------------------------------------------------------- */
@@ -336,6 +330,7 @@ static void __init at91sam9g45_map_io(void)
static void __init at91sam9g45_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9G45_BASE_SHDWC);
+ at91_ioremap_rstc(AT91SAM9G45_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9G45_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9G45_BASE_SMC);
}
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
new file mode 100644
index 000000000000..0468be10980b
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -0,0 +1,40 @@
+/*
+ * reset AT91SAM9G45 as per errata
+ *
+ * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcosoft.com>
+ *
+ * unless the SDRAM is cleanly shutdown before we hit the
+ * reset register it can be left driving the data bus and
+ * killing the chance of a subsequent boot from NAND
+ *
+ * GPLv2 Only
+ */
+
+#include <linux/linkage.h>
+#include <mach/hardware.h>
+#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_rstc.h>
+
+ .arm
+
+ .globl at91sam9g45_restart
+
+at91sam9g45_restart:
+ ldr r0, .at91_va_base_sdramc0 @ preload constants
+ ldr r1, =at91_rstc_base
+ ldr r1, [r1]
+
+ mov r2, #1
+ mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
+ ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
+
+ .balign 32 @ align to cache line
+
+ str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
+ str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
+ str r4, [r1, #AT91_RSTC_CR] @ reset processor
+
+ b .
+
+.at91_va_base_sdramc0:
+ .word AT91_VA_BASE_SYS + AT91_DDRSDRC0
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index d6bcb1da11df..d2c91a841cb8 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -286,6 +286,7 @@ static void __init at91sam9rl_map_io(void)
static void __init at91sam9rl_ioremap_registers(void)
{
at91_ioremap_shdwc(AT91SAM9RL_BASE_SHDWC);
+ at91_ioremap_rstc(AT91SAM9RL_BASE_RSTC);
at91sam926x_ioremap_pit(AT91SAM9RL_BASE_PIT);
at91sam9_ioremap_smc(0, AT91SAM9RL_BASE_SMC);
}
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 4866b8180d66..594133451c0c 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -58,7 +58,9 @@ extern void at91_irq_suspend(void);
extern void at91_irq_resume(void);
/* reset */
+extern void at91_ioremap_rstc(u32 base_addr);
extern void at91sam9_alt_restart(char, const char *);
+extern void at91sam9g45_restart(char, const char *);
/* shutdown */
extern void at91_ioremap_shdwc(u32 base_addr);
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index cbd2bf052c1f..875fa336800b 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,25 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
-#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
+#ifndef __ASSEMBLY__
+extern void __iomem *at91_rstc_base;
+
+#define at91_rstc_read(field) \
+ __raw_readl(at91_rstc_base + field)
+
+#define at91_rstc_write(field, value) \
+ __raw_writel(value, at91_rstc_base + field);
+#else
+.extern at91_rstc_base
+#endif
+
+#define AT91_RSTC_CR 0x00 /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
-#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
+#define AT91_RSTC_SR 0x04 /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +45,7 @@
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
-#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
+#define AT91_RSTC_MR 0x08 /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91cap9.h b/arch/arm/mach-at91/include/mach/at91cap9.h
index 4c0e2f6011d7..61d952902f2b 100644
--- a/arch/arm/mach-at91/include/mach/at91cap9.h
+++ b/arch/arm/mach-at91/include/mach/at91cap9.h
@@ -83,7 +83,6 @@
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (cpu_is_at91cap9_revB() ? \
(0xfffffd50 - AT91_BASE_SYS) : \
(0xfffffd60 - AT91_BASE_SYS))
@@ -96,6 +95,7 @@
#define AT91CAP9_BASE_PIOB 0xfffff400
#define AT91CAP9_BASE_PIOC 0xfffff600
#define AT91CAP9_BASE_PIOD 0xfffff800
+#define AT91CAP9_BASE_RSTC 0xfffffd00
#define AT91CAP9_BASE_SHDWC 0xfffffd10
#define AT91CAP9_BASE_RTT 0xfffffd20
#define AT91CAP9_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
deleted file mode 100644
index 976f4a6c3353..000000000000
--- a/arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91cap9_ddrsdr.h
- *
- * (C) 2008 Andrew Victor
- *
- * DDR/SDR Controller (DDRSDRC) - System peripherals registers.
- * Based on AT91CAP9 datasheet revision B.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91CAP9_DDRSDR_H
-#define AT91CAP9_DDRSDR_H
-
-#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
-#define AT91_DDRSDRC_MODE (0xf << 0) /* Command Mode */
-#define AT91_DDRSDRC_MODE_NORMAL 0
-#define AT91_DDRSDRC_MODE_NOP 1
-#define AT91_DDRSDRC_MODE_PRECHARGE 2
-#define AT91_DDRSDRC_MODE_LMR 3
-#define AT91_DDRSDRC_MODE_REFRESH 4
-#define AT91_DDRSDRC_MODE_EXT_LMR 5
-#define AT91_DDRSDRC_MODE_DEEP 6
-
-#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
-#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
-
-#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
-#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
-#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
-#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
-#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
-#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
-#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
-#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
-#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
-#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_DDRSDRC_NR_11 (0 << 2)
-#define AT91_DDRSDRC_NR_12 (1 << 2)
-#define AT91_DDRSDRC_NR_13 (2 << 2)
-#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
-#define AT91_DDRSDRC_CAS_2 (2 << 4)
-#define AT91_DDRSDRC_CAS_3 (3 << 4)
-#define AT91_DDRSDRC_CAS_25 (6 << 4)
-#define AT91_DDRSDRC_DLL (1 << 7) /* Reset DLL */
-#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
-
-#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
-#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
-#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
-#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
-#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
-#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
-#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
-#define AT91_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
-#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
-
-#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
-#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
-#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
-#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
-#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
-
-#define AT91_DDRSDRC_LPR 0x18 /* Low Power Register */
-#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
-#define AT91_DDRSDRC_LPCB_DISABLE 0
-#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
-#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
-#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
-#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
-#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
-#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
-#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
-#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
-#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
-#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
-#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
-
-#define AT91_DDRSDRC_MDR 0x1C /* Memory Device Register */
-#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
-#define AT91_DDRSDRC_MD_SDR 0
-#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
-#define AT91_DDRSDRC_MD_DDR 2
-#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
-
-#define AT91_DDRSDRC_DLLR 0x20 /* DLL Information Register */
-#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
-#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
-#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
-#define AT91_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
-#define AT91_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
-#define AT91_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
-#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
-#define AT91_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
-#define AT91_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
-
-/* Register access macros */
-#define at91_ramc_read(num, reg) \
- at91_sys_read(AT91_DDRSDRC##num + reg)
-#define at91_ramc_write(num, reg, value) \
- at91_sys_write(AT91_DDRSDRC##num + reg, value)
-
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index f937c476bb67..fa5ca278adeb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -83,7 +83,6 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9260_BASE_ECC 0xffffe800
@@ -92,6 +91,7 @@
#define AT91SAM9260_BASE_PIOA 0xfffff400
#define AT91SAM9260_BASE_PIOB 0xfffff600
#define AT91SAM9260_BASE_PIOC 0xfffff800
+#define AT91SAM9260_BASE_RSTC 0xfffffd00
#define AT91SAM9260_BASE_SHDWC 0xfffffd10
#define AT91SAM9260_BASE_RTT 0xfffffd20
#define AT91SAM9260_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 175604e261be..7cde2d36570e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -68,7 +68,6 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
#define AT91SAM9261_BASE_SMC 0xffffec00
@@ -76,6 +75,7 @@
#define AT91SAM9261_BASE_PIOA 0xfffff400
#define AT91SAM9261_BASE_PIOB 0xfffff600
#define AT91SAM9261_BASE_PIOC 0xfffff800
+#define AT91SAM9261_BASE_RSTC 0xfffffd00
#define AT91SAM9261_BASE_SHDWC 0xfffffd10
#define AT91SAM9261_BASE_RTT 0xfffffd20
#define AT91SAM9261_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index 80c915002d83..5949abda962b 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -78,7 +78,6 @@
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9263_BASE_ECC0 0xffffe000
@@ -91,6 +90,7 @@
#define AT91SAM9263_BASE_PIOC 0xfffff600
#define AT91SAM9263_BASE_PIOD 0xfffff800
#define AT91SAM9263_BASE_PIOE 0xfffffa00
+#define AT91SAM9263_BASE_RSTC 0xfffffd00
#define AT91SAM9263_BASE_SHDWC 0xfffffd10
#define AT91SAM9263_BASE_RTT0 0xfffffd20
#define AT91SAM9263_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index d27b15ba8ebf..e2f8da8ce5bc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -46,10 +46,10 @@
#define AT91_DDRSDRC_CAS_25 (6 << 4)
#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
-#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL */
-#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver */
-#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared */
-#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y */
+#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
+#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
+#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
+#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
@@ -59,7 +59,8 @@
#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
-#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay */
+#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
+#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
@@ -68,13 +69,14 @@
#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
-#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register */
+#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
+#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_DDRSDRC_LPCB_DISABLE 0
#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
@@ -92,32 +94,40 @@
#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
+#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
#define AT91_DDRSDRC_MD_SDR 0
#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
+#define AT91CAP9_DDRSDRC_MD_DDR 2
#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
-#define AT91_DDRSDRC_MD_DDR2 6
+#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
+#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
+#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
+#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
+#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
+#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
+#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
-#define AT91_DDRSDRC_HS 0x2C /* High Speed Register */
+#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
-#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register */
+#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
-#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register */
+#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index f0c23c960dec..dd9c95ea0862 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -90,7 +90,6 @@
#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91SAM9G45_BASE_ECC 0xffffe200
@@ -102,6 +101,7 @@
#define AT91SAM9G45_BASE_PIOC 0xfffff600
#define AT91SAM9G45_BASE_PIOD 0xfffff800
#define AT91SAM9G45_BASE_PIOE 0xfffffa00
+#define AT91SAM9G45_BASE_RSTC 0xfffffd00
#define AT91SAM9G45_BASE_SHDWC 0xfffffd10
#define AT91SAM9G45_BASE_RTT 0xfffffd20
#define AT91SAM9G45_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/at91sam9rl.h b/arch/arm/mach-at91/include/mach/at91sam9rl.h
index 2bb359e60b97..d7bead7118da 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9rl.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9rl.h
@@ -72,7 +72,6 @@
#define AT91_SDRAMC0 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
@@ -84,6 +83,7 @@
#define AT91SAM9RL_BASE_PIOB 0xfffff600
#define AT91SAM9RL_BASE_PIOC 0xfffff800
#define AT91SAM9RL_BASE_PIOD 0xfffffa00
+#define AT91SAM9RL_BASE_RSTC 0xfffffd00
#define AT91SAM9RL_BASE_SHDWC 0xfffffd10
#define AT91SAM9RL_BASE_RTT 0xfffffd20
#define AT91SAM9RL_BASE_PIT 0xfffffd30
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index d0b377b21bd7..3b33f07b1e11 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -88,7 +88,7 @@ extern void __init at91_add_device_eth(struct macb_platform_data *data);
struct at91_usbh_data {
u8 ports; /* number of ports on root hub */
int vbus_pin[2]; /* port power-control pin */
- u8 vbus_pin_inverted;
+ u8 vbus_pin_active_low[2];
u8 overcurrent_supported;
int overcurrent_pin[2];
u8 overcurrent_status[2];
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 62ad95556c36..1606379ac284 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -34,7 +34,6 @@
/*
* Show the reason for the previous system reset.
*/
-#if defined(AT91_RSTC)
#include <mach/at91_rstc.h>
#include <mach/at91_shdwc.h>
@@ -58,10 +57,10 @@ static void __init show_reset_status(void)
char *reason, *r2 = reset;
u32 reset_type, wake_type;
- if (!at91_shdwc_base)
+ if (!at91_shdwc_base || !at91_rstc_base)
return;
- reset_type = at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
+ reset_type = at91_rstc_read(AT91_RSTC_SR) & AT91_RSTC_RSTTYP;
wake_type = at91_shdwc_read(AT91_SHDW_SR);
switch (reset_type) {
@@ -102,10 +101,6 @@ static void __init show_reset_status(void)
}
pr_info("AT91: Starting after %s %s\n", reason, r2);
}
-#else
-static void __init show_reset_status(void) {}
-#endif
-
static int at91_pm_valid_state(suspend_state_t state)
{
diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
index ce9a20699111..7eb40d24242f 100644
--- a/arch/arm/mach-at91/pm.h
+++ b/arch/arm/mach-at91/pm.h
@@ -25,21 +25,21 @@ static inline u32 sdram_selfrefresh_enable(void)
: : "r" (0))
#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_ddrsdr.h>
+#include <mach/at91sam9_ddrsdr.h>
static inline u32 sdram_selfrefresh_enable(void)
{
u32 saved_lpr, lpr;
- saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR);
+ saved_lpr = at91_ramc_read(0, AT91CAP9_DDRSDRC_LPR);
lpr = saved_lpr & ~AT91_DDRSDRC_LPCB;
- at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
+ at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, lpr | AT91_DDRSDRC_LPCB_SELF_REFRESH);
return saved_lpr;
}
-#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr)
+#define sdram_selfrefresh_disable(saved_lpr) at91_ramc_write(0, AT91CAP9_DDRSDRC_LPR, saved_lpr)
#define wait_for_interrupt_enable() cpu_do_idle()
#elif defined(CONFIG_ARCH_AT91SAM9G45)
diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S
index f7922a436172..92dfb8461392 100644
--- a/arch/arm/mach-at91/pm_slowclock.S
+++ b/arch/arm/mach-at91/pm_slowclock.S
@@ -18,9 +18,8 @@
#if defined(CONFIG_ARCH_AT91RM9200)
#include <mach/at91rm9200_mc.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_ddrsdr.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#elif defined(CONFIG_ARCH_AT91CAP9) \
+ || defined(CONFIG_ARCH_AT91SAM9G45)
#include <mach/at91sam9_ddrsdr.h>
#else
#include <mach/at91sam9_sdramc.h>
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 8bdcc3cb6012..69d3fc4c46f3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -29,9 +29,12 @@ EXPORT_SYMBOL(at91_soc_initdata);
void __init at91rm9200_set_type(int type)
{
if (type == ARCH_REVISON_9200_PQFP)
- at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
- else
at91_soc_initdata.subtype = AT91_SOC_RM9200_PQFP;
+ else
+ at91_soc_initdata.subtype = AT91_SOC_RM9200_BGA;
+
+ pr_info("AT91: filled in soc subtype: %s\n",
+ at91_get_soc_subtype(&at91_soc_initdata));
}
void __init at91_init_irq_default(void)
@@ -281,6 +284,15 @@ void __init at91_ioremap_shdwc(u32 base_addr)
pm_power_off = at91sam9_poweroff;
}
+void __iomem *at91_rstc_base;
+
+void __init at91_ioremap_rstc(u32 base_addr)
+{
+ at91_rstc_base = ioremap(base_addr, 16);
+ if (!at91_rstc_base)
+ panic("Impossible to ioremap at91_rstc_base\n");
+}
+
void __init at91_initialize(unsigned long main_clock)
{
at91_boot_soc.ioremap_registers();
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 9e5e7552498c..45c97b1ee9b1 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -194,6 +194,6 @@ MACHINE_START(BCMRING, "BCMRING")
.init_early = bcmring_init_early,
.init_irq = bcmring_init_irq,
.timer = &bcmring_timer,
- .init_machine = bcmring_init_machine
+ .init_machine = bcmring_init_machine,
.restart = bcmring_restart,
MACHINE_END
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index 1a1a27dd5654..1024396797e1 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -33,17 +33,11 @@
#include <mach/timer.h>
-#include <linux/mm.h>
#include <linux/pfn.h>
#include <linux/atomic.h>
#include <linux/sched.h>
#include <mach/dma.h>
-/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
-/* especially since dc4 doesn't use kmalloc'd memory. */
-
-#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
-
/* ---- Public Variables ------------------------------------------------- */
/* ---- Private Constants and Types -------------------------------------- */
@@ -53,24 +47,12 @@
#define CONTROLLER_FROM_HANDLE(handle) (((handle) >> 4) & 0x0f)
#define CHANNEL_FROM_HANDLE(handle) ((handle) & 0x0f)
-#define DMA_MAP_DEBUG 0
-
-#if DMA_MAP_DEBUG
-# define DMA_MAP_PRINT(fmt, args...) printk("%s: " fmt, __func__, ## args)
-#else
-# define DMA_MAP_PRINT(fmt, args...)
-#endif
/* ---- Private Variables ------------------------------------------------ */
static DMA_Global_t gDMA;
static struct proc_dir_entry *gDmaDir;
-static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
-static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
-static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
-static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
-
#include "dma_device.c"
/* ---- Private Function Prototypes -------------------------------------- */
@@ -79,34 +61,6 @@ static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
/****************************************************************************/
/**
-* Displays information for /proc/dma/mem-type
-*/
-/****************************************************************************/
-
-static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
- int count, int *eof, void *data)
-{
- int len = 0;
-
- len += sprintf(buf + len, "dma_map_mem statistics\n");
- len +=
- sprintf(buf + len, "coherent: %d\n",
- atomic_read(&gDmaStatMemTypeCoherent));
- len +=
- sprintf(buf + len, "kmalloc: %d\n",
- atomic_read(&gDmaStatMemTypeKmalloc));
- len +=
- sprintf(buf + len, "vmalloc: %d\n",
- atomic_read(&gDmaStatMemTypeVmalloc));
- len +=
- sprintf(buf + len, "user: %d\n",
- atomic_read(&gDmaStatMemTypeUser));
-
- return len;
-}
-
-/****************************************************************************/
-/**
* Displays information for /proc/dma/channels
*/
/****************************************************************************/
@@ -846,8 +800,6 @@ int dma_init(void)
dma_proc_read_channels, NULL);
create_proc_read_entry("devices", 0, gDmaDir,
dma_proc_read_devices, NULL);
- create_proc_read_entry("mem-type", 0, gDmaDir,
- dma_proc_read_mem_type, NULL);
}
out:
@@ -1565,767 +1517,3 @@ int dma_set_device_handler(DMA_Device_t dev, /* Device to set the callback for.
}
EXPORT_SYMBOL(dma_set_device_handler);
-
-/****************************************************************************/
-/**
-* Initializes a memory mapping structure
-*/
-/****************************************************************************/
-
-int dma_init_mem_map(DMA_MemMap_t *memMap)
-{
- memset(memMap, 0, sizeof(*memMap));
-
- sema_init(&memMap->lock, 1);
-
- return 0;
-}
-
-EXPORT_SYMBOL(dma_init_mem_map);
-
-/****************************************************************************/
-/**
-* Releases any memory currently being held by a memory mapping structure.
-*/
-/****************************************************************************/
-
-int dma_term_mem_map(DMA_MemMap_t *memMap)
-{
- down(&memMap->lock); /* Just being paranoid */
-
- /* Free up any allocated memory */
-
- up(&memMap->lock);
- memset(memMap, 0, sizeof(*memMap));
-
- return 0;
-}
-
-EXPORT_SYMBOL(dma_term_mem_map);
-
-/****************************************************************************/
-/**
-* Looks at a memory address and categorizes it.
-*
-* @return One of the values from the DMA_MemType_t enumeration.
-*/
-/****************************************************************************/
-
-DMA_MemType_t dma_mem_type(void *addr)
-{
- unsigned long addrVal = (unsigned long)addr;
-
- if (addrVal >= CONSISTENT_BASE) {
- /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
-
- /* dma_alloc_xxx pages are physically and virtually contiguous */
-
- return DMA_MEM_TYPE_DMA;
- }
-
- /* Technically, we could add one more classification. Addresses between VMALLOC_END */
- /* and the beginning of the DMA virtual address could be considered to be I/O space. */
- /* Right now, nobody cares about this particular classification, so we ignore it. */
-
- if (is_vmalloc_addr(addr)) {
- /* Address comes from the vmalloc'd region. Pages are virtually */
- /* contiguous but NOT physically contiguous */
-
- return DMA_MEM_TYPE_VMALLOC;
- }
-
- if (addrVal >= PAGE_OFFSET) {
- /* PAGE_OFFSET is typically 0xC0000000 */
-
- /* kmalloc'd pages are physically contiguous */
-
- return DMA_MEM_TYPE_KMALLOC;
- }
-
- return DMA_MEM_TYPE_USER;
-}
-
-EXPORT_SYMBOL(dma_mem_type);
-
-/****************************************************************************/
-/**
-* Looks at a memory address and determines if we support DMA'ing to/from
-* that type of memory.
-*
-* @return boolean -
-* return value != 0 means dma supported
-* return value == 0 means dma not supported
-*/
-/****************************************************************************/
-
-int dma_mem_supports_dma(void *addr)
-{
- DMA_MemType_t memType = dma_mem_type(addr);
-
- return (memType == DMA_MEM_TYPE_DMA)
-#if ALLOW_MAP_OF_KMALLOC_MEMORY
- || (memType == DMA_MEM_TYPE_KMALLOC)
-#endif
- || (memType == DMA_MEM_TYPE_USER);
-}
-
-EXPORT_SYMBOL(dma_mem_supports_dma);
-
-/****************************************************************************/
-/**
-* Maps in a memory region such that it can be used for performing a DMA.
-*
-* @return
-*/
-/****************************************************************************/
-
-int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
- enum dma_data_direction dir /* Direction that the mapping will be going */
- ) {
- int rc;
-
- down(&memMap->lock);
-
- DMA_MAP_PRINT("memMap: %p\n", memMap);
-
- if (memMap->inUse) {
- printk(KERN_ERR "%s: memory map %p is already being used\n",
- __func__, memMap);
- rc = -EBUSY;
- goto out;
- }
-
- memMap->inUse = 1;
- memMap->dir = dir;
- memMap->numRegionsUsed = 0;
-
- rc = 0;
-
-out:
-
- DMA_MAP_PRINT("returning %d", rc);
-
- up(&memMap->lock);
-
- return rc;
-}
-
-EXPORT_SYMBOL(dma_map_start);
-
-/****************************************************************************/
-/**
-* Adds a segment of memory to a memory map. Each segment is both
-* physically and virtually contiguous.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-static int dma_map_add_segment(DMA_MemMap_t *memMap, /* Stores state information about the map */
- DMA_Region_t *region, /* Region that the segment belongs to */
- void *virtAddr, /* Virtual address of the segment being added */
- dma_addr_t physAddr, /* Physical address of the segment being added */
- size_t numBytes /* Number of bytes of the segment being added */
- ) {
- DMA_Segment_t *segment;
-
- DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
- physAddr, numBytes);
-
- /* Sanity check */
-
- if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
- || (((unsigned long)virtAddr + numBytes)) >
- ((unsigned long)region->virtAddr + region->numBytes)) {
- printk(KERN_ERR
- "%s: virtAddr %p is outside region @ %p len: %d\n",
- __func__, virtAddr, region->virtAddr, region->numBytes);
- return -EINVAL;
- }
-
- if (region->numSegmentsUsed > 0) {
- /* Check to see if this segment is physically contiguous with the previous one */
-
- segment = &region->segment[region->numSegmentsUsed - 1];
-
- if ((segment->physAddr + segment->numBytes) == physAddr) {
- /* It is - just add on to the end */
-
- DMA_MAP_PRINT("appending %d bytes to last segment\n",
- numBytes);
-
- segment->numBytes += numBytes;
-
- return 0;
- }
- }
-
- /* Reallocate to hold more segments, if required. */
-
- if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
- DMA_Segment_t *newSegment;
- size_t oldSize =
- region->numSegmentsAllocated * sizeof(*newSegment);
- int newAlloc = region->numSegmentsAllocated + 4;
- size_t newSize = newAlloc * sizeof(*newSegment);
-
- newSegment = kmalloc(newSize, GFP_KERNEL);
- if (newSegment == NULL) {
- return -ENOMEM;
- }
- memcpy(newSegment, region->segment, oldSize);
- memset(&((uint8_t *) newSegment)[oldSize], 0,
- newSize - oldSize);
- kfree(region->segment);
-
- region->numSegmentsAllocated = newAlloc;
- region->segment = newSegment;
- }
-
- segment = &region->segment[region->numSegmentsUsed];
- region->numSegmentsUsed++;
-
- segment->virtAddr = virtAddr;
- segment->physAddr = physAddr;
- segment->numBytes = numBytes;
-
- DMA_MAP_PRINT("returning success\n");
-
- return 0;
-}
-
-/****************************************************************************/
-/**
-* Adds a region of memory to a memory map. Each region is virtually
-* contiguous, but not necessarily physically contiguous.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
- void *mem, /* Virtual address that we want to get a map of */
- size_t numBytes /* Number of bytes being mapped */
- ) {
- unsigned long addr = (unsigned long)mem;
- unsigned int offset;
- int rc = 0;
- DMA_Region_t *region;
- dma_addr_t physAddr;
-
- down(&memMap->lock);
-
- DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
-
- if (!memMap->inUse) {
- printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
- __func__);
- rc = -EINVAL;
- goto out;
- }
-
- /* Reallocate to hold more regions. */
-
- if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
- DMA_Region_t *newRegion;
- size_t oldSize =
- memMap->numRegionsAllocated * sizeof(*newRegion);
- int newAlloc = memMap->numRegionsAllocated + 4;
- size_t newSize = newAlloc * sizeof(*newRegion);
-
- newRegion = kmalloc(newSize, GFP_KERNEL);
- if (newRegion == NULL) {
- rc = -ENOMEM;
- goto out;
- }
- memcpy(newRegion, memMap->region, oldSize);
- memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
-
- kfree(memMap->region);
-
- memMap->numRegionsAllocated = newAlloc;
- memMap->region = newRegion;
- }
-
- region = &memMap->region[memMap->numRegionsUsed];
- memMap->numRegionsUsed++;
-
- offset = addr & ~PAGE_MASK;
-
- region->memType = dma_mem_type(mem);
- region->virtAddr = mem;
- region->numBytes = numBytes;
- region->numSegmentsUsed = 0;
- region->numLockedPages = 0;
- region->lockedPages = NULL;
-
- switch (region->memType) {
- case DMA_MEM_TYPE_VMALLOC:
- {
- atomic_inc(&gDmaStatMemTypeVmalloc);
-
- /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
-
- /* vmalloc'd pages are not physically contiguous */
-
- rc = -EINVAL;
- break;
- }
-
- case DMA_MEM_TYPE_KMALLOC:
- {
- atomic_inc(&gDmaStatMemTypeKmalloc);
-
- /* kmalloc'd pages are physically contiguous, so they'll have exactly */
- /* one segment */
-
-#if ALLOW_MAP_OF_KMALLOC_MEMORY
- physAddr =
- dma_map_single(NULL, mem, numBytes, memMap->dir);
- rc = dma_map_add_segment(memMap, region, mem, physAddr,
- numBytes);
-#else
- rc = -EINVAL;
-#endif
- break;
- }
-
- case DMA_MEM_TYPE_DMA:
- {
- /* dma_alloc_xxx pages are physically contiguous */
-
- atomic_inc(&gDmaStatMemTypeCoherent);
-
- physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
-
- dma_sync_single_for_cpu(NULL, physAddr, numBytes,
- memMap->dir);
- rc = dma_map_add_segment(memMap, region, mem, physAddr,
- numBytes);
- break;
- }
-
- case DMA_MEM_TYPE_USER:
- {
- size_t firstPageOffset;
- size_t firstPageSize;
- struct page **pages;
- struct task_struct *userTask;
-
- atomic_inc(&gDmaStatMemTypeUser);
-
-#if 1
- /* If the pages are user pages, then the dma_mem_map_set_user_task function */
- /* must have been previously called. */
-
- if (memMap->userTask == NULL) {
- printk(KERN_ERR
- "%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
- __func__);
- return -EINVAL;
- }
-
- /* User pages need to be locked. */
-
- firstPageOffset =
- (unsigned long)region->virtAddr & (PAGE_SIZE - 1);
- firstPageSize = PAGE_SIZE - firstPageOffset;
-
- region->numLockedPages = (firstPageOffset
- + region->numBytes +
- PAGE_SIZE - 1) / PAGE_SIZE;
- pages =
- kmalloc(region->numLockedPages *
- sizeof(struct page *), GFP_KERNEL);
-
- if (pages == NULL) {
- region->numLockedPages = 0;
- return -ENOMEM;
- }
-
- userTask = memMap->userTask;
-
- down_read(&userTask->mm->mmap_sem);
- rc = get_user_pages(userTask, /* task */
- userTask->mm, /* mm */
- (unsigned long)region->virtAddr, /* start */
- region->numLockedPages, /* len */
- memMap->dir == DMA_FROM_DEVICE, /* write */
- 0, /* force */
- pages, /* pages (array of pointers to page) */
- NULL); /* vmas */
- up_read(&userTask->mm->mmap_sem);
-
- if (rc != region->numLockedPages) {
- kfree(pages);
- region->numLockedPages = 0;
-
- if (rc >= 0) {
- rc = -EINVAL;
- }
- } else {
- uint8_t *virtAddr = region->virtAddr;
- size_t bytesRemaining;
- int pageIdx;
-
- rc = 0; /* Since get_user_pages returns +ve number */
-
- region->lockedPages = pages;
-
- /* We've locked the user pages. Now we need to walk them and figure */
- /* out the physical addresses. */
-
- /* The first page may be partial */
-
- dma_map_add_segment(memMap,
- region,
- virtAddr,
- PFN_PHYS(page_to_pfn
- (pages[0])) +
- firstPageOffset,
- firstPageSize);
-
- virtAddr += firstPageSize;
- bytesRemaining =
- region->numBytes - firstPageSize;
-
- for (pageIdx = 1;
- pageIdx < region->numLockedPages;
- pageIdx++) {
- size_t bytesThisPage =
- (bytesRemaining >
- PAGE_SIZE ? PAGE_SIZE :
- bytesRemaining);
-
- DMA_MAP_PRINT
- ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
- pageIdx, pages[pageIdx],
- page_to_pfn(pages[pageIdx]),
- PFN_PHYS(page_to_pfn
- (pages[pageIdx])));
-
- dma_map_add_segment(memMap,
- region,
- virtAddr,
- PFN_PHYS(page_to_pfn
- (pages
- [pageIdx])),
- bytesThisPage);
-
- virtAddr += bytesThisPage;
- bytesRemaining -= bytesThisPage;
- }
- }
-#else
- printk(KERN_ERR
- "%s: User mode pages are not yet supported\n",
- __func__);
-
- /* user pages are not physically contiguous */
-
- rc = -EINVAL;
-#endif
- break;
- }
-
- default:
- {
- printk(KERN_ERR "%s: Unsupported memory type: %d\n",
- __func__, region->memType);
-
- rc = -EINVAL;
- break;
- }
- }
-
- if (rc != 0) {
- memMap->numRegionsUsed--;
- }
-
-out:
-
- DMA_MAP_PRINT("returning %d\n", rc);
-
- up(&memMap->lock);
-
- return rc;
-}
-
-EXPORT_SYMBOL(dma_map_add_segment);
-
-/****************************************************************************/
-/**
-* Maps in a memory region such that it can be used for performing a DMA.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
- void *mem, /* Virtual address that we want to get a map of */
- size_t numBytes, /* Number of bytes being mapped */
- enum dma_data_direction dir /* Direction that the mapping will be going */
- ) {
- int rc;
-
- rc = dma_map_start(memMap, dir);
- if (rc == 0) {
- rc = dma_map_add_region(memMap, mem, numBytes);
- if (rc < 0) {
- /* Since the add fails, this function will fail, and the caller won't */
- /* call unmap, so we need to do it here. */
-
- dma_unmap(memMap, 0);
- }
- }
-
- return rc;
-}
-
-EXPORT_SYMBOL(dma_map_mem);
-
-/****************************************************************************/
-/**
-* Setup a descriptor ring for a given memory map.
-*
-* It is assumed that the descriptor ring has already been initialized, and
-* this routine will only reallocate a new descriptor ring if the existing
-* one is too small.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
- DMA_MemMap_t *memMap, /* Memory map that will be used */
- dma_addr_t devPhysAddr /* Physical address of device */
- ) {
- int rc;
- int numDescriptors;
- DMA_DeviceAttribute_t *devAttr;
- DMA_Region_t *region;
- DMA_Segment_t *segment;
- dma_addr_t srcPhysAddr;
- dma_addr_t dstPhysAddr;
- int regionIdx;
- int segmentIdx;
-
- devAttr = &DMA_gDeviceAttribute[dev];
-
- down(&memMap->lock);
-
- /* Figure out how many descriptors we need */
-
- numDescriptors = 0;
- for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
- region = &memMap->region[regionIdx];
-
- for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
- segmentIdx++) {
- segment = &region->segment[segmentIdx];
-
- if (memMap->dir == DMA_TO_DEVICE) {
- srcPhysAddr = segment->physAddr;
- dstPhysAddr = devPhysAddr;
- } else {
- srcPhysAddr = devPhysAddr;
- dstPhysAddr = segment->physAddr;
- }
-
- rc =
- dma_calculate_descriptor_count(dev, srcPhysAddr,
- dstPhysAddr,
- segment->
- numBytes);
- if (rc < 0) {
- printk(KERN_ERR
- "%s: dma_calculate_descriptor_count failed: %d\n",
- __func__, rc);
- goto out;
- }
- numDescriptors += rc;
- }
- }
-
- /* Adjust the size of the ring, if it isn't big enough */
-
- if (numDescriptors > devAttr->ring.descriptorsAllocated) {
- dma_free_descriptor_ring(&devAttr->ring);
- rc =
- dma_alloc_descriptor_ring(&devAttr->ring,
- numDescriptors);
- if (rc < 0) {
- printk(KERN_ERR
- "%s: dma_alloc_descriptor_ring failed: %d\n",
- __func__, rc);
- goto out;
- }
- } else {
- rc =
- dma_init_descriptor_ring(&devAttr->ring,
- numDescriptors);
- if (rc < 0) {
- printk(KERN_ERR
- "%s: dma_init_descriptor_ring failed: %d\n",
- __func__, rc);
- goto out;
- }
- }
-
- /* Populate the descriptors */
-
- for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
- region = &memMap->region[regionIdx];
-
- for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
- segmentIdx++) {
- segment = &region->segment[segmentIdx];
-
- if (memMap->dir == DMA_TO_DEVICE) {
- srcPhysAddr = segment->physAddr;
- dstPhysAddr = devPhysAddr;
- } else {
- srcPhysAddr = devPhysAddr;
- dstPhysAddr = segment->physAddr;
- }
-
- rc =
- dma_add_descriptors(&devAttr->ring, dev,
- srcPhysAddr, dstPhysAddr,
- segment->numBytes);
- if (rc < 0) {
- printk(KERN_ERR
- "%s: dma_add_descriptors failed: %d\n",
- __func__, rc);
- goto out;
- }
- }
- }
-
- rc = 0;
-
-out:
-
- up(&memMap->lock);
- return rc;
-}
-
-EXPORT_SYMBOL(dma_map_create_descriptor_ring);
-
-/****************************************************************************/
-/**
-* Maps in a memory region such that it can be used for performing a DMA.
-*
-* @return
-*/
-/****************************************************************************/
-
-int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
- int dirtied /* non-zero if any of the pages were modified */
- ) {
-
- int rc = 0;
- int regionIdx;
- int segmentIdx;
- DMA_Region_t *region;
- DMA_Segment_t *segment;
-
- down(&memMap->lock);
-
- for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
- region = &memMap->region[regionIdx];
-
- for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
- segmentIdx++) {
- segment = &region->segment[segmentIdx];
-
- switch (region->memType) {
- case DMA_MEM_TYPE_VMALLOC:
- {
- printk(KERN_ERR
- "%s: vmalloc'd pages are not yet supported\n",
- __func__);
- rc = -EINVAL;
- goto out;
- }
-
- case DMA_MEM_TYPE_KMALLOC:
- {
-#if ALLOW_MAP_OF_KMALLOC_MEMORY
- dma_unmap_single(NULL,
- segment->physAddr,
- segment->numBytes,
- memMap->dir);
-#endif
- break;
- }
-
- case DMA_MEM_TYPE_DMA:
- {
- dma_sync_single_for_cpu(NULL,
- segment->
- physAddr,
- segment->
- numBytes,
- memMap->dir);
- break;
- }
-
- case DMA_MEM_TYPE_USER:
- {
- /* Nothing to do here. */
-
- break;
- }
-
- default:
- {
- printk(KERN_ERR
- "%s: Unsupported memory type: %d\n",
- __func__, region->memType);
- rc = -EINVAL;
- goto out;
- }
- }
-
- segment->virtAddr = NULL;
- segment->physAddr = 0;
- segment->numBytes = 0;
- }
-
- if (region->numLockedPages > 0) {
- int pageIdx;
-
- /* Some user pages were locked. We need to go and unlock them now. */
-
- for (pageIdx = 0; pageIdx < region->numLockedPages;
- pageIdx++) {
- struct page *page =
- region->lockedPages[pageIdx];
-
- if (memMap->dir == DMA_FROM_DEVICE) {
- SetPageDirty(page);
- }
- page_cache_release(page);
- }
- kfree(region->lockedPages);
- region->numLockedPages = 0;
- region->lockedPages = NULL;
- }
-
- region->memType = DMA_MEM_TYPE_NONE;
- region->virtAddr = NULL;
- region->numBytes = 0;
- region->numSegmentsUsed = 0;
- }
- memMap->userTask = NULL;
- memMap->numRegionsUsed = 0;
- memMap->inUse = 0;
-
-out:
- up(&memMap->lock);
-
- return rc;
-}
-
-EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
index 1f2c5319c056..72543781207b 100644
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -26,15 +26,9 @@
/* ---- Include Files ---------------------------------------------------- */
#include <linux/kernel.h>
-#include <linux/wait.h>
#include <linux/semaphore.h>
#include <csp/dmacHw.h>
#include <mach/timer.h>
-#include <linux/scatterlist.h>
-#include <linux/dma-mapping.h>
-#include <linux/mm.h>
-#include <linux/vmalloc.h>
-#include <linux/pagemap.h>
/* ---- Constants and Types ---------------------------------------------- */
@@ -113,78 +107,6 @@ typedef struct {
/****************************************************************************
*
-* The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
-* DMA chains from a variety of memory sources.
-*
-*****************************************************************************/
-
-#define DMA_MEM_MAP_MIN_SIZE 4096 /* Pages less than this size are better */
- /* off not being DMA'd. */
-
-typedef enum {
- DMA_MEM_TYPE_NONE, /* Not a valid setting */
- DMA_MEM_TYPE_VMALLOC, /* Memory came from vmalloc call */
- DMA_MEM_TYPE_KMALLOC, /* Memory came from kmalloc call */
- DMA_MEM_TYPE_DMA, /* Memory came from dma_alloc_xxx call */
- DMA_MEM_TYPE_USER, /* Memory came from user space. */
-
-} DMA_MemType_t;
-
-/* A segment represents a physically and virtually contiguous chunk of memory. */
-/* i.e. each segment can be DMA'd */
-/* A user of the DMA code will add memory regions. Each region may need to be */
-/* represented by one or more segments. */
-
-typedef struct {
- void *virtAddr; /* Virtual address used for this segment */
- dma_addr_t physAddr; /* Physical address this segment maps to */
- size_t numBytes; /* Size of the segment, in bytes */
-
-} DMA_Segment_t;
-
-/* A region represents a virtually contiguous chunk of memory, which may be */
-/* made up of multiple segments. */
-
-typedef struct {
- DMA_MemType_t memType;
- void *virtAddr;
- size_t numBytes;
-
- /* Each region (virtually contiguous) consists of one or more segments. Each */
- /* segment is virtually and physically contiguous. */
-
- int numSegmentsUsed;
- int numSegmentsAllocated;
- DMA_Segment_t *segment;
-
- /* When a region corresponds to user memory, we need to lock all of the pages */
- /* down before we can figure out the physical addresses. The lockedPage array contains */
- /* the pages that were locked, and which subsequently need to be unlocked once the */
- /* memory is unmapped. */
-
- unsigned numLockedPages;
- struct page **lockedPages;
-
-} DMA_Region_t;
-
-typedef struct {
- int inUse; /* Is this mapping currently being used? */
- struct semaphore lock; /* Acquired when using this structure */
- enum dma_data_direction dir; /* Direction this transfer is intended for */
-
- /* In the event that we're mapping user memory, we need to know which task */
- /* the memory is for, so that we can obtain the correct mm locks. */
-
- struct task_struct *userTask;
-
- int numRegionsUsed;
- int numRegionsAllocated;
- DMA_Region_t *region;
-
-} DMA_MemMap_t;
-
-/****************************************************************************
-*
* The DMA_DeviceAttribute_t contains information which describes a
* particular DMA device (or peripheral).
*
@@ -570,124 +492,6 @@ int dma_alloc_double_dst_descriptors(DMA_Handle_t handle, /* DMA Handle */
/****************************************************************************/
/**
-* Initializes a DMA_MemMap_t data structure
-*/
-/****************************************************************************/
-
-int dma_init_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
- );
-
-/****************************************************************************/
-/**
-* Releases any memory currently being held by a memory mapping structure.
-*/
-/****************************************************************************/
-
-int dma_term_mem_map(DMA_MemMap_t *memMap /* Stores state information about the map */
- );
-
-/****************************************************************************/
-/**
-* Looks at a memory address and categorizes it.
-*
-* @return One of the values from the DMA_MemType_t enumeration.
-*/
-/****************************************************************************/
-
-DMA_MemType_t dma_mem_type(void *addr);
-
-/****************************************************************************/
-/**
-* Sets the process (aka userTask) associated with a mem map. This is
-* required if user-mode segments will be added to the mapping.
-*/
-/****************************************************************************/
-
-static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
- struct task_struct *task)
-{
- memMap->userTask = task;
-}
-
-/****************************************************************************/
-/**
-* Looks at a memory address and determines if we support DMA'ing to/from
-* that type of memory.
-*
-* @return boolean -
-* return value != 0 means dma supported
-* return value == 0 means dma not supported
-*/
-/****************************************************************************/
-
-int dma_mem_supports_dma(void *addr);
-
-/****************************************************************************/
-/**
-* Initializes a memory map for use. Since this function acquires a
-* sempaphore within the memory map, it is VERY important that dma_unmap
-* be called when you're finished using the map.
-*/
-/****************************************************************************/
-
-int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
- enum dma_data_direction dir /* Direction that the mapping will be going */
- );
-
-/****************************************************************************/
-/**
-* Adds a segment of memory to a memory map.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-int dma_map_add_region(DMA_MemMap_t *memMap, /* Stores state information about the map */
- void *mem, /* Virtual address that we want to get a map of */
- size_t numBytes /* Number of bytes being mapped */
- );
-
-/****************************************************************************/
-/**
-* Creates a descriptor ring from a memory mapping.
-*
-* @return 0 on success, error code otherwise.
-*/
-/****************************************************************************/
-
-int dma_map_create_descriptor_ring(DMA_Device_t dev, /* DMA device (where the ring is stored) */
- DMA_MemMap_t *memMap, /* Memory map that will be used */
- dma_addr_t devPhysAddr /* Physical address of device */
- );
-
-/****************************************************************************/
-/**
-* Maps in a memory region such that it can be used for performing a DMA.
-*
-* @return
-*/
-/****************************************************************************/
-
-int dma_map_mem(DMA_MemMap_t *memMap, /* Stores state information about the map */
- void *addr, /* Virtual address that we want to get a map of */
- size_t count, /* Number of bytes being mapped */
- enum dma_data_direction dir /* Direction that the mapping will be going */
- );
-
-/****************************************************************************/
-/**
-* Maps in a memory region such that it can be used for performing a DMA.
-*
-* @return
-*/
-/****************************************************************************/
-
-int dma_unmap(DMA_MemMap_t *memMap, /* Stores state information about the map */
- int dirtied /* non-zero if any of the pages were modified */
- );
-
-/****************************************************************************/
-/**
* Initiates a transfer when the descriptors have already been setup.
*
* This is a special case, and normally, the dma_transfer_xxx functions should
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 0f8fca48a5ed..e159d69967c9 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -151,13 +151,12 @@ static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
struct resource *res_io = &cnspci->res_io;
struct resource *res_mem = &cnspci->res_mem;
- struct resource **sysres = sys->resource;
BUG_ON(request_resource(&iomem_resource, res_io) ||
request_resource(&iomem_resource, res_mem));
- sysres[0] = res_io;
- sysres[1] = res_mem;
+ pci_add_resource(&sys->resources, res_io);
+ pci_add_resource(&sys->resources, res_mem);
return 1;
}
@@ -169,7 +168,8 @@ static struct pci_ops cns3xxx_pcie_ops = {
static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
+ &sys->resources);
}
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index f8a682f60a42..d5088900af6c 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -44,7 +44,7 @@
#include <mach/aemif.h>
#include <mach/spi.h>
-#define DA850_EVM_PHY_ID "0:00"
+#define DA850_EVM_PHY_ID "davinci_mdio-0:00"
#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8)
#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15)
@@ -127,7 +127,7 @@ static void da850_evm_m25p80_notify_add(struct mtd_info *mtd)
size_t retlen;
if (!strcmp(mtd->name, "MAC-Address")) {
- mtd->read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
+ mtd_read(mtd, 0, ETH_ALEN, &retlen, mac_addr);
if (retlen == ETH_ALEN)
pr_info("Read MAC addr from SPI Flash: %pM\n",
mac_addr);
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 346e1de2f5a8..849311d3cb7c 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -54,7 +54,7 @@ static inline int have_tvp7002(void)
return 0;
}
-#define DM365_EVM_PHY_ID "0:01"
+#define DM365_EVM_PHY_ID "davinci_mdio-0:01"
/*
* A MAX-II CPLD is used for various board control functions.
*/
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index a64b49cfedca..1247ecdcf752 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -40,7 +40,7 @@
#include <mach/usb.h>
#include <mach/aemif.h>
-#define DM644X_EVM_PHY_ID "0:01"
+#define DM644X_EVM_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID (0x001378e2)
#define LXT971_PHY_MASK (0xfffffff0)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 64017558860b..872ac69fa049 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -736,7 +736,7 @@ static struct davinci_uart_config uart_config __initdata = {
.enabled_uarts = (1 << 0),
};
-#define DM646X_EVM_PHY_ID "0:01"
+#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
/*
* The following EDMA channels/slots are not being used by drivers (for
* example: Timer, GPIO, UART events etc) on dm646x, hence they are being
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 6c4a16415d47..8d34f513d415 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -39,7 +39,7 @@
#include <mach/mmc.h>
#include <mach/usb.h>
-#define NEUROS_OSD2_PHY_ID "0:01"
+#define NEUROS_OSD2_PHY_ID "davinci_mdio-0:01"
#define LXT971_PHY_ID 0x001378e2
#define LXT971_PHY_MASK 0xfffffff0
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index e7c0c7c53493..45e815760a27 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -21,7 +21,7 @@
#include <mach/da8xx.h>
#include <mach/mux.h>
-#define HAWKBOARD_PHY_ID "0:07"
+#define HAWKBOARD_PHY_ID "davinci_mdio-0:07"
#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12)
#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13)
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 0b136a831c59..31da3c5b2ba3 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -42,7 +42,7 @@
#include <mach/mux.h>
#include <mach/usb.h>
-#define SFFSDR_PHY_ID "0:01"
+#define SFFSDR_PHY_ID "davinci_mdio-0:01"
static struct mtd_partition davinci_sffsdr_nandflash_partition[] = {
/* U-Boot Environment: Block 0
* UBL: Block 1
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 0ed7fdb64efb..992c4c410185 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -153,34 +153,6 @@ static struct clk pll1_sysclk3 = {
.div_reg = PLLDIV3,
};
-static struct clk pll1_sysclk4 = {
- .name = "pll1_sysclk4",
- .parent = &pll1_clk,
- .flags = CLK_PLL,
- .div_reg = PLLDIV4,
-};
-
-static struct clk pll1_sysclk5 = {
- .name = "pll1_sysclk5",
- .parent = &pll1_clk,
- .flags = CLK_PLL,
- .div_reg = PLLDIV5,
-};
-
-static struct clk pll1_sysclk6 = {
- .name = "pll0_sysclk6",
- .parent = &pll0_clk,
- .flags = CLK_PLL,
- .div_reg = PLLDIV6,
-};
-
-static struct clk pll1_sysclk7 = {
- .name = "pll1_sysclk7",
- .parent = &pll1_clk,
- .flags = CLK_PLL,
- .div_reg = PLLDIV7,
-};
-
static struct clk i2c0_clk = {
.name = "i2c0",
.parent = &pll0_aux_clk,
@@ -397,10 +369,6 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, "pll1_aux", &pll1_aux_clk),
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
- CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
- CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
- CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
- CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
CLK("i2c_davinci.1", NULL, &i2c0_clk),
CLK(NULL, "timer0", &timerp64_0_clk),
CLK("watchdog", NULL, &timerp64_1_clk),
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 6c11a4df7178..52e96d397ba8 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -69,7 +69,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
pp->res[0].flags = IORESOURCE_IO;
if (request_resource(&ioport_resource, &pp->res[0]))
panic("Request PCIe IO resource failed\n");
- sys->resource[0] = &pp->res[0];
+ pci_add_resource(&sys->resources, &pp->res[0]);
/*
* IORESOURCE_MEM
@@ -88,9 +88,7 @@ static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys)
pp->res[1].flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pp->res[1]))
panic("Request PCIe Memory resource failed\n");
- sys->resource[1] = &pp->res[1];
-
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &pp->res[1]);
return 1;
}
@@ -184,7 +182,8 @@ dove_pcie_scan_bus(int nr, struct pci_sys_data *sys)
struct pci_bus *bus;
if (nr < num_pcie_ports) {
- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+ &sys->resources);
} else {
bus = NULL;
BUG();
diff --git a/arch/arm/mach-ep93xx/include/mach/dma.h b/arch/arm/mach-ep93xx/include/mach/dma.h
index 46d4d876e6fb..e82c642fa53c 100644
--- a/arch/arm/mach-ep93xx/include/mach/dma.h
+++ b/arch/arm/mach-ep93xx/include/mach/dma.h
@@ -37,7 +37,7 @@
*/
struct ep93xx_dma_data {
int port;
- enum dma_data_direction direction;
+ enum dma_transfer_direction direction;
const char *name;
};
@@ -80,14 +80,14 @@ static inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan)
* channel supports given DMA direction. Only M2P channels have such
* limitation, for M2M channels the direction is configurable.
*/
-static inline enum dma_data_direction
+static inline enum dma_transfer_direction
ep93xx_dma_chan_direction(struct dma_chan *chan)
{
if (!ep93xx_dma_chan_is_m2p(chan))
return DMA_NONE;
/* even channels are for TX, odd for RX */
- return (chan->chan_id % 2 == 0) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+ return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
}
#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S
index 3cdeb3647542..5364d4bfa8bc 100644
--- a/arch/arm/mach-exynos/headsmp.S
+++ b/arch/arm/mach-exynos/headsmp.S
@@ -36,6 +36,8 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
+ENDPROC(exynos4_secondary_startup)
+ .align 2
1: .long .
.long pen_release
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index da70e7e39937..dd1ad55524c9 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
#include <mach/regs-pmu.h>
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
new file mode 100644
index 000000000000..3df27f2d5034
--- /dev/null
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-exynos/include/mach/cpufreq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS - CPUFreq support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+enum cpufreq_level_index {
+ L0, L1, L2, L3, L4,
+ L5, L6, L7, L8, L9,
+ L10, L11, L12, L13, L14,
+ L15, L16, L17, L18, L19,
+ L20,
+};
+
+struct exynos_dvfs_info {
+ unsigned long mpll_freq_khz;
+ unsigned int pll_safe_idx;
+ unsigned int pm_lock_idx;
+ unsigned int max_support_idx;
+ unsigned int min_support_idx;
+ struct clk *cpu_clk;
+ unsigned int *volt_table;
+ struct cpufreq_frequency_table *freq_table;
+ void (*set_freq)(unsigned int, unsigned int);
+ bool (*need_apll_change)(unsigned int, unsigned int);
+};
+
+extern int exynos4210_cpufreq_init(struct exynos_dvfs_info *);
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 2b11e046d391..0679b8ad2d1e 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -597,7 +597,8 @@ static struct s3c_fb_pd_win origen_fb_win0 = {
static struct s3c_fb_platdata origen_lcd_pdata __initdata = {
.win[0] = &origen_fb_win0,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
- .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC |
+ VIDCON1_INV_VCLK,
.setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
};
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60bc45e3e709..0f2035a1eb6e 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -23,8 +23,8 @@
#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
+#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
-#include <asm/unified.h>
#include <mach/hardware.h>
#include <mach/regs-clock.h>
@@ -137,7 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
while (time_before(jiffies, timeout)) {
smp_rmb();
- __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
gic_raise_softirq(cpumask_of(cpu), 1);
@@ -192,6 +192,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
CPU1_BOOT_REG);
}
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 18c32a5541d9..f685650c25d7 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -275,9 +275,9 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
allocate_resource(&iomem_resource, &res[0], 0x40000000,
0x80000000, 0xffffffff, 0x40000000, NULL, NULL);
- sys->resource[0] = &ioport_resource;
- sys->resource[1] = &res[0];
- sys->resource[2] = &res[1];
+ pci_add_resource(&sys->resources, &ioport_resource);
+ pci_add_resource(&sys->resources, &res[0]);
+ pci_add_resource(&sys->resources, &res[1]);
sys->mem_offset = DC21285_PCI_MEM;
return 1;
@@ -285,7 +285,7 @@ int __init dc21285_setup(int nr, struct pci_sys_data *sys)
struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(0, &dc21285_ops, sys);
+ return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
}
#define dc21285_request_irq(_a, _b, _c, _d, _e) \
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 804c4a55f803..8394d512a402 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -25,7 +25,7 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
-#include <asm/unified.h>
+#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/timer-sp.h>
@@ -73,10 +73,8 @@ static void __init highbank_map_io(void)
void highbank_set_cpu_jump(int cpu, void *jump_addr)
{
-#ifdef CONFIG_SMP
cpu = cpu_logical_map(cpu);
-#endif
- writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+ writel(virt_to_phys(jump_addr), HB_JUMP_TABLE_VIRT(cpu));
__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
HB_JUMP_TABLE_PHYS(cpu) + 15);
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0e6de366c648..4defb97bbfc8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -22,6 +22,18 @@ config ARCH_MX25
config MACH_MX27
bool
+config ARCH_MX5
+ bool
+
+config ARCH_MX50
+ bool
+
+config ARCH_MX51
+ bool
+
+config ARCH_MX53
+ bool
+
config SOC_IMX1
bool
select ARCH_MX1
@@ -73,6 +85,31 @@ config SOC_IMX35
select MXC_AVIC
select SMP_ON_UP if SMP
+config SOC_IMX5
+ select CPU_V7
+ select MXC_TZIC
+ select ARCH_MXC_IOMUX_V3
+ select ARCH_MXC_AUDMUX_V2
+ select ARCH_HAS_CPUFREQ
+ select ARCH_MX5
+ bool
+
+config SOC_IMX50
+ bool
+ select SOC_IMX5
+ select ARCH_MX50
+
+config SOC_IMX51
+ bool
+ select SOC_IMX5
+ select ARCH_MX5
+ select ARCH_MX51
+
+config SOC_IMX53
+ bool
+ select SOC_IMX5
+ select ARCH_MX5
+ select ARCH_MX53
if ARCH_IMX_V4_V5
@@ -592,6 +629,207 @@ config MACH_VPR200
Include support for VPR200 platform. This includes specific
configurations for the board and its peripherals.
+comment "i.MX5 platforms:"
+
+config MACH_MX50_RDP
+ bool "Support MX50 reference design platform"
+ depends on BROKEN
+ select SOC_IMX50
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Include support for MX50 reference design platform (RDP) board. This
+ includes specific configurations for the board and its peripherals.
+
+comment "i.MX51 machines:"
+
+config MACH_IMX51_DT
+ bool "Support i.MX51 platforms from device tree"
+ select SOC_IMX51
+ select USE_OF
+ select MACH_MX51_BABBAGE
+ help
+ Include support for Freescale i.MX51 based platforms
+ using the device tree for discovery
+
+config MACH_MX51_BABBAGE
+ bool "Support MX51 BABBAGE platforms"
+ select SOC_IMX51
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Include support for MX51 Babbage platform, also known as MX51EVK in
+ u-boot. This includes specific configurations for the board and its
+ peripherals.
+
+config MACH_MX51_3DS
+ bool "Support MX51PDK (3DS)"
+ select SOC_IMX51
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_KEYPAD
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_DEBUG_BOARD
+ help
+ Include support for MX51PDK (3DS) platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX51
+ bool "Support Eukrea CPUIMX51 module"
+ select SOC_IMX51
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Include support for Eukrea CPUIMX51 platform. This includes
+ specific configurations for the module and its peripherals.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_EUKREA_CPUIMX51
+ default MACH_EUKREA_MBIMX51_BASEBOARD
+
+config MACH_EUKREA_MBIMX51_BASEBOARD
+ prompt "Eukrea MBIMX51 development board"
+ bool
+ select IMX_HAVE_PLATFORM_IMX_KEYPAD
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select LEDS_GPIO_REGISTER
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMX51 evaluation board.
+
+endchoice
+
+config MACH_EUKREA_CPUIMX51SD
+ bool "Support Eukrea CPUIMX51SD module"
+ select SOC_IMX51
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Include support for Eukrea CPUIMX51SD platform. This includes
+ specific configurations for the module and its peripherals.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_EUKREA_CPUIMX51SD
+ default MACH_EUKREA_MBIMXSD51_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD51_BASEBOARD
+ prompt "Eukrea MBIMXSD development board"
+ bool
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select LEDS_GPIO_REGISTER
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMXSD evaluation board.
+
+endchoice
+
+config MX51_EFIKA_COMMON
+ bool
+ select SOC_IMX51
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_PATA_IMX
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+
+config MACH_MX51_EFIKAMX
+ bool "Support MX51 Genesi Efika MX nettop"
+ select LEDS_GPIO_REGISTER
+ select MX51_EFIKA_COMMON
+ help
+ Include support for Genesi Efika MX nettop. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX51_EFIKASB
+ bool "Support MX51 Genesi Efika Smartbook"
+ select LEDS_GPIO_REGISTER
+ select MX51_EFIKA_COMMON
+ help
+ Include support for Genesi Efika Smartbook. This includes specific
+ configurations for the board and its peripherals.
+
+comment "i.MX53 machines:"
+
+config MACH_IMX53_DT
+ bool "Support i.MX53 platforms from device tree"
+ select SOC_IMX53
+ select USE_OF
+ select MACH_MX53_ARD
+ select MACH_MX53_EVK
+ select MACH_MX53_LOCO
+ select MACH_MX53_SMD
+ help
+ Include support for Freescale i.MX53 based platforms
+ using the device tree for discovery
+
+config MACH_MX53_EVK
+ bool "Support MX53 EVK platforms"
+ select SOC_IMX53
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select LEDS_GPIO_REGISTER
+ help
+ Include support for MX53 EVK platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX53_SMD
+ bool "Support MX53 SMD platforms"
+ select SOC_IMX53
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ help
+ Include support for MX53 SMD platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX53_LOCO
+ bool "Support MX53 LOCO platforms"
+ select SOC_IMX53
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select LEDS_GPIO_REGISTER
+ help
+ Include support for MX53 LOCO platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX53_ARD
+ bool "Support MX53 ARD platforms"
+ select SOC_IMX53
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ help
+ Include support for MX53 ARD platform. This includes specific
+ configurations for the board and its peripherals.
+
comment "i.MX6 family:"
config SOC_IMX6Q
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f5920c24f7d7..55db9c488f2b 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clock-mx51-mx53.o ehci-imx5.o pm-imx5.o cpu_op-mx51.o
+
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
@@ -75,3 +77,22 @@ obj-$(CONFIG_SOC_IMX6Q) += clock-imx6q.o mach-imx6q.o
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_SOC_IMX6Q) += pm-imx6q.o
endif
+
+# i.MX5 based machines
+obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
+obj-$(CONFIG_MACH_MX51_3DS) += mach-mx51_3ds.o
+obj-$(CONFIG_MACH_MX53_EVK) += mach-mx53_evk.o
+obj-$(CONFIG_MACH_MX53_SMD) += mach-mx53_smd.o
+obj-$(CONFIG_MACH_MX53_LOCO) += mach-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_ARD) += mach-mx53_ard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += mach-cpuimx51.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
+obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
+obj-$(CONFIG_MACH_MX51_EFIKAMX) += mach-mx51_efikamx.o
+obj-$(CONFIG_MACH_MX51_EFIKASB) += mach-mx51_efikasb.o
+obj-$(CONFIG_MACH_MX50_RDP) += mach-mx50_rdp.o
+
+obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
+obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 5f4d06af4912..6dfdbcc83afd 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -22,6 +22,18 @@ zreladdr-$(CONFIG_SOC_IMX35) += 0x80008000
params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
+zreladdr-$(CONFIG_SOC_IMX50) += 0x70008000
+params_phys-$(CONFIG_SOC_IMX50) := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX50) := 0x70800000
+
+zreladdr-$(CONFIG_SOC_IMX51) += 0x90008000
+params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
+initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
+
+zreladdr-$(CONFIG_SOC_IMX53) += 0x70008000
+params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
+initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
+
zreladdr-$(CONFIG_SOC_IMX6Q) += 0x10008000
params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
diff --git a/arch/arm/mach-imx/clock-imx6q.c b/arch/arm/mach-imx/clock-imx6q.c
index 9273c2a24b54..2d88f8b9a454 100644
--- a/arch/arm/mach-imx/clock-imx6q.c
+++ b/arch/arm/mach-imx/clock-imx6q.c
@@ -814,6 +814,16 @@ DEF_PFD(pll3_pfd_540m, PFD_480, PFD1, &pll3_usb_otg);
DEF_PFD(pll3_pfd_508m, PFD_480, PFD2, &pll3_usb_otg);
DEF_PFD(pll3_pfd_454m, PFD_480, PFD3, &pll3_usb_otg);
+static unsigned long twd_clk_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) / 2;
+}
+
+static struct clk twd_clk = {
+ .parent = &arm_clk,
+ .get_rate = twd_clk_get_rate,
+};
+
static unsigned long pll2_200m_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / 2;
@@ -1894,6 +1904,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("20ec000.sdma", NULL, sdma_clk),
_REGISTER_CLOCK("20bc000.wdog", NULL, dummy_clk),
_REGISTER_CLOCK("20c0000.wdog", NULL, dummy_clk),
+ _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
_REGISTER_CLOCK(NULL, "ckih", ckih_clk),
_REGISTER_CLOCK(NULL, "ckil_clk", ckil_clk),
_REGISTER_CLOCK(NULL, "aips_tz1_clk", aips_tz1_clk),
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-imx/clock-mx51-mx53.c
index 4cb276977190..08470504a088 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-imx/clock-mx51-mx53.c
@@ -23,7 +23,7 @@
#include <mach/common.h>
#include <mach/clock.h>
-#include "crm_regs.h"
+#include "crm-regs-imx5.h"
/* External clock values passed-in by the board code */
static unsigned long external_high_reference, external_low_reference;
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-imx/cpu-imx5.c
index 5e2e7a843860..5e2e7a843860 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-imx/cpu-imx5.c
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
index 9d34c3d4c024..9d34c3d4c024 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.c
+++ b/arch/arm/mach-imx/cpu_op-mx51.c
diff --git a/arch/arm/mach-mx5/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
index 97477fecb469..97477fecb469 100644
--- a/arch/arm/mach-mx5/cpu_op-mx51.h
+++ b/arch/arm/mach-imx/cpu_op-mx51.h
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-imx/crm-regs-imx5.h
index 5e11ba7daee2..5e11ba7daee2 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-imx/crm-regs-imx5.h
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-imx/devices-imx50.h
index 7216667eaafc..7216667eaafc 100644
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ b/arch/arm/mach-imx/devices-imx50.h
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index af488bc0e225..af488bc0e225 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
index 6e1e5d1f8c3a..6e1e5d1f8c3a 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-imx/devices-imx53.h
diff --git a/arch/arm/mach-mx5/efika.h b/arch/arm/mach-imx/efika.h
index 014aa985faae..014aa985faae 100644
--- a/arch/arm/mach-mx5/efika.h
+++ b/arch/arm/mach-imx/efika.h
diff --git a/arch/arm/mach-mx5/ehci.c b/arch/arm/mach-imx/ehci-imx5.c
index c17fa131728b..c17fa131728b 100644
--- a/arch/arm/mach-mx5/ehci.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
index a6a3ab8f1b1c..a6a3ab8f1b1c 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx51-baseboard.c
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
index d817fc80b986..d817fc80b986 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd-baseboard.c
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index e6bad17b908c..e6bad17b908c 100644
--- a/arch/arm/mach-mx5/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index 05ebb3e68679..05ebb3e68679 100644
--- a/arch/arm/mach-mx5/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-imx/mach-cpuimx51.c
index 944025da8333..944025da8333 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-imx/mach-cpuimx51.c
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9fbe923c8b08..9fbe923c8b08 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 89c33258639f..4d1aab154400 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -36,6 +36,7 @@
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
+#include <asm/memblock.h>
#include <mach/common.h>
#include <mach/iomux-mx3.h>
#include <mach/3ds_debugboard.h>
@@ -754,10 +755,8 @@ static struct sys_timer mx31_3ds_timer = {
static void __init mx31_3ds_reserve(void)
{
/* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
- mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+ mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
MX31_3DS_CAMERA_BUF_SIZE);
- memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
- memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
}
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index b95981dacb2b..f225262b5c38 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -41,6 +41,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include <asm/memblock.h>
#include <mach/board-mx31moboard.h>
#include <mach/common.h>
#include <mach/hardware.h>
@@ -584,10 +585,8 @@ struct sys_timer mx31moboard_timer = {
static void __init mx31moboard_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
- mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+ mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
- memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
- memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-imx/mach-mx50_rdp.c
index 42b66e8d9615..42b66e8d9615 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-imx/mach-mx50_rdp.c
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 83eab4176ca4..83eab4176ca4 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index e4b822e9f719..e4b822e9f719 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-imx/mach-mx51_efikamx.c
index 3a5ed2dd885a..3a5ed2dd885a 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-imx/mach-mx51_efikamx.c
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-imx/mach-mx51_efikasb.c
index ea5f65b0381a..ea5f65b0381a 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-imx/mach-mx51_efikasb.c
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 5f224f1c3eb6..753f4fc9ec04 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -32,7 +32,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
@@ -189,8 +188,10 @@ static int weim_cs_config(void)
return -ENOMEM;
iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
- if (!iomuxc_base)
+ if (!iomuxc_base) {
+ iounmap(weim_base);
return -ENOMEM;
+ }
/* CS1 timings for LAN9220 */
writel(0x20001, (weim_base + 0x18));
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
index d6ce137896d6..5a72188b9cdb 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-imx/mach-mx53_evk.c
@@ -37,7 +37,6 @@
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
#define MX53EVK_LED IMX_GPIO_NR(7, 7)
-#include "crm_regs.h"
#include "devices-imx53.h"
static iomux_v3_cfg_t mx53_evk_pads[] = {
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
index fd8b524e1c58..37f67cac15a4 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-imx/mach-mx53_loco.c
@@ -32,7 +32,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define MX53_LOCO_POWER IMX_GPIO_NR(1, 8)
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
index 22c53c9b18aa..8e972c5c3e13 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-imx/mach-mx53_smd.c
@@ -31,7 +31,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include "crm_regs.h"
#include "devices-imx53.h"
#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6)
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index d7e151669ed3..e48854b9d990 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -39,6 +39,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
+#include <asm/memblock.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
@@ -680,10 +681,8 @@ struct sys_timer pcm037_timer = {
static void __init pcm037_reserve(void)
{
/* reserve 4 MiB for mx3-camera */
- mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+ mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
MX3_CAMERA_BUF_SIZE);
- memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
- memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
}
MACHINE_START(PCM037, "Phytec Phycore pcm037")
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-imx/mm-imx5.c
index bc17dfea3817..bc17dfea3817 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-imx/mm-imx5.c
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-imx/mx51_efika.c
index ec6ca91b299b..ec6ca91b299b 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-imx/mx51_efika.c
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-imx/pm-imx5.c
index 5eebfaad1226..6dc093448057 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -1,8 +1,6 @@
/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
@@ -10,14 +8,22 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
-#include <linux/platform_device.h>
+#include <linux/suspend.h>
+#include <linux/clk.h>
#include <linux/io.h>
-#include <mach/hardware.h>
+#include <linux/err.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
#include <mach/common.h>
-#include "crm_regs.h"
+#include <mach/hardware.h>
+#include "crm-regs-imx5.h"
+
+static struct clk *gpc_dvfs_clk;
-/* set cpu low power mode before WFI instruction. This function is called
- * mx5 because it can be used for mx50, mx51, and mx53.*/
+/*
+ * set cpu low power mode before WFI instruction. This function is called
+ * mx5 because it can be used for mx50, mx51, and mx53.
+ */
void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
{
u32 plat_lpc, arm_srpgcr, ccm_clpcr;
@@ -80,3 +86,68 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
__raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR);
}
}
+
+static int mx5_suspend_prepare(void)
+{
+ return clk_enable(gpc_dvfs_clk);
+}
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_MEM:
+ mx5_cpu_lp_set(STOP_POWER_OFF);
+ break;
+ case PM_SUSPEND_STANDBY:
+ mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (state == PM_SUSPEND_MEM) {
+ local_flush_tlb_all();
+ flush_cache_all();
+
+ /*clear the EMPGC0/1 bits */
+ __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+ __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+ }
+ cpu_do_idle();
+ return 0;
+}
+
+static void mx5_suspend_finish(void)
+{
+ clk_disable(gpc_dvfs_clk);
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+ return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+static const struct platform_suspend_ops mx5_suspend_ops = {
+ .valid = mx5_pm_valid,
+ .prepare = mx5_suspend_prepare,
+ .enter = mx5_suspend_enter,
+ .finish = mx5_suspend_finish,
+};
+
+static int __init mx5_pm_init(void)
+{
+ if (!cpu_is_mx51() && !cpu_is_mx53())
+ return 0;
+
+ if (gpc_dvfs_clk == NULL)
+ gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+
+ if (!IS_ERR(gpc_dvfs_clk)) {
+ if (cpu_is_mx51())
+ suspend_set_ops(&mx5_suspend_ops);
+ } else
+ return -EPERM;
+
+ return 0;
+}
+device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 4bde04f99e38..e15f1555c59b 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -15,7 +15,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/smp.h>
-#include <asm/unified.h>
+#include <asm/smp_plat.h>
#define SRC_SCR 0x000
#define SRC_GPR1 0x020
@@ -25,10 +25,6 @@
static void __iomem *src_base;
-#ifndef CONFIG_SMP
-#define cpu_logical_map(cpu) 0
-#endif
-
void imx_enable_cpu(int cpu, bool enable)
{
u32 mask, val;
@@ -43,7 +39,7 @@ void imx_enable_cpu(int cpu, bool enable)
void imx_set_cpu_jump(int cpu, void *jump_addr)
{
cpu = cpu_logical_map(cpu);
- writel_relaxed(BSYM(virt_to_phys(jump_addr)),
+ writel_relaxed(virt_to_phys(jump_addr),
src_base + SRC_GPR1 + cpu * 8);
}
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b4d8f8b8a085..3c82566acece 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -359,7 +359,7 @@ static struct resource pre_mem = {
.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
};
-static int __init pci_v3_setup_resources(struct resource **resource)
+static int __init pci_v3_setup_resources(struct pci_sys_data *sys)
{
if (request_resource(&iomem_resource, &non_mem)) {
printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -374,13 +374,13 @@ static int __init pci_v3_setup_resources(struct resource **resource)
}
/*
- * bus->resource[0] is the IO resource for this bus
- * bus->resource[1] is the mem resource for this bus
- * bus->resource[2] is the prefetch mem resource for this bus
+ * the IO resource for this bus
+ * the mem resource for this bus
+ * the prefetch mem resource for this bus
*/
- resource[0] = &ioport_resource;
- resource[1] = &non_mem;
- resource[2] = &pre_mem;
+ pci_add_resource(&sys->resources, &ioport_resource);
+ pci_add_resource(&sys->resources, &non_mem);
+ pci_add_resource(&sys->resources, &pre_mem);
return 1;
}
@@ -481,7 +481,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
if (nr == 0) {
sys->mem_offset = PHYS_PCI_MEM_BASE;
- ret = pci_v3_setup_resources(sys->resource);
+ ret = pci_v3_setup_resources(sys);
}
return ret;
@@ -489,7 +489,8 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &pci_v3_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
+ &sys->resources);
}
/*
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index db012fadf88c..b8f5a8736511 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -537,14 +537,14 @@ struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
while(time_before(jiffies, atux_trhfa_timeout))
udelay(100);
- bus = pci_bus_atux = pci_scan_bus(sys->busnr,
- &iop13xx_atux_ops,
- sys);
+ bus = pci_bus_atux = pci_scan_root_bus(NULL, sys->busnr,
+ &iop13xx_atux_ops,
+ sys, &sys->resources);
break;
case IOP13XX_INIT_ATU_ATUE:
- bus = pci_bus_atue = pci_scan_bus(sys->busnr,
- &iop13xx_atue_ops,
- sys);
+ bus = pci_bus_atue = pci_scan_root_bus(NULL, sys->busnr,
+ &iop13xx_atue_ops,
+ sys, &sys->resources);
break;
}
@@ -1084,9 +1084,8 @@ int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
- sys->resource[0] = &res[0];
- sys->resource[1] = &res[1];
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &res[0]);
+ pci_add_resource(&sys->resources, &res[1]);
return 1;
}
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index ee525416f0d2..e872d238cd0f 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -145,7 +145,8 @@ static struct pci_ops enp2611_pci_ops = {
static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
+ &sys->resources);
}
static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index f5098b306fd3..626fda435aa9 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -132,7 +132,8 @@ static struct pci_ops ixp2000_pci_ops = {
struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
{
- return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata);
+ return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
+ sysdata, &sysdata->resources);
}
@@ -242,9 +243,8 @@ int ixp2000_pci_setup(int nr, struct pci_sys_data *sys)
if (nr >= 1)
return 0;
- sys->resource[0] = &ixp2000_pci_io_space;
- sys->resource[1] = &ixp2000_pci_mem_space;
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &ixp2000_pci_io_space);
+ pci_add_resource(&sys->resources, &ixp2000_pci_mem_space);
return 1;
}
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index e6be5711c700..25b5c462cea2 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -143,7 +143,8 @@ struct pci_ops ixp23xx_pci_ops = {
struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
{
- return pci_scan_bus(sysdata->busnr, &ixp23xx_pci_ops, sysdata);
+ return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
+ sysdata, &sysdata->resources);
}
int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
@@ -280,9 +281,8 @@ int ixp23xx_pci_setup(int nr, struct pci_sys_data *sys)
if (nr >= 1)
return 0;
- sys->resource[0] = &ixp23xx_pci_io_space;
- sys->resource[1] = &ixp23xx_pci_mem_space;
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &ixp23xx_pci_io_space);
+ pci_add_resource(&sys->resources, &ixp23xx_pci_mem_space);
return 1;
}
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index 8325058ef871..5eff15f24bc2 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -472,9 +472,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
request_resource(&ioport_resource, &res[0]);
request_resource(&iomem_resource, &res[1]);
- sys->resource[0] = &res[0];
- sys->resource[1] = &res[1];
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &res[0]);
+ pci_add_resource(&sys->resources, &res[1]);
platform_notify = ixp4xx_pci_platform_notify;
platform_notify_remove = ixp4xx_pci_platform_notify_remove;
@@ -484,7 +483,8 @@ int ixp4xx_setup(int nr, struct pci_sys_data *sys)
struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &ixp4xx_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
+ &sys->resources);
}
int dma_set_coherent_mask(struct device *dev, u64 mask)
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index fb451bfe478b..a066a6d8d9d2 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -198,9 +198,8 @@ static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
if (request_resource(&iomem_resource, &pp->res[1]))
panic("Request PCIe%d Memory resource failed\n", index);
- sys->resource[0] = &pp->res[0];
- sys->resource[1] = &pp->res[1];
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &pp->res[0]);
+ pci_add_resource(&sys->resources, &pp->res[1]);
sys->io_offset = 0;
/*
@@ -236,7 +235,8 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
struct pci_bus *bus;
if (nr < num_pcie_ports) {
- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+ &sys->resources);
} else {
bus = NULL;
BUG();
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index c7c9a188d105..b26f992071df 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -143,7 +143,8 @@ static struct pci_ops ks8695_pci_ops = {
static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &ks8695_pci_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
+ &sys->resources);
}
static struct resource pci_mem = {
@@ -168,9 +169,8 @@ static int __init ks8695_pci_setup(int nr, struct pci_sys_data *sys)
request_resource(&iomem_resource, &pci_mem);
request_resource(&ioport_resource, &pci_io);
- sys->resource[0] = &pci_io;
- sys->resource[1] = &pci_mem;
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &pci_io);
+ pci_add_resource(&sys->resources, &pci_mem);
/* Assign and enable processor bridge */
ks8695_local_writeconfig(PCI_BASE_ADDRESS_0, KS8695_PCIMEM_PA);
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
index 0c631a9f8647..bcd5af223dea 100644
--- a/arch/arm/mach-msm/headsmp.S
+++ b/arch/arm/mach-msm/headsmp.S
@@ -34,6 +34,7 @@ pen: ldr r7, [r6]
* should now contain the SVC stack for this core
*/
b secondary_startup
+ENDPROC(msm_secondary_startup)
.align
1: .long .
diff --git a/arch/arm/mach-msm/hotplug.c b/arch/arm/mach-msm/hotplug.c
index 41c252de0215..a446fc14221f 100644
--- a/arch/arm/mach-msm/hotplug.c
+++ b/arch/arm/mach-msm/hotplug.c
@@ -11,6 +11,7 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
extern volatile int pen_release;
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 0b3e357c4c8c..db0117ec55f4 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -20,6 +20,7 @@
#include <asm/cacheflush.h>
#include <asm/cputype.h>
#include <asm/mach-types.h>
+#include <asm/smp_plat.h>
#include <mach/msm_iomap.h>
diff --git a/arch/arm/mach-msm/vreg.c b/arch/arm/mach-msm/vreg.c
index a9103bc6615f..bd66ed04d6dc 100644
--- a/arch/arm/mach-msm/vreg.c
+++ b/arch/arm/mach-msm/vreg.c
@@ -19,6 +19,7 @@
#include <linux/device.h>
#include <linux/init.h>
#include <linux/debugfs.h>
+#include <linux/module.h>
#include <linux/string.h>
#include <mach/vreg.h>
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 12fcb108b0e1..8459f6d7d8ca 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -155,9 +155,8 @@ static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
orion_pcie_setup(pp->base);
- sys->resource[0] = &pp->res[0];
- sys->resource[1] = &pp->res[1];
- sys->resource[2] = NULL;
+ pci_add_resource(&sys->resources, &pp->res[0]);
+ pci_add_resource(&sys->resources, &pp->res[1]);
return 1;
}
@@ -251,7 +250,8 @@ mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
struct pci_bus *bus;
if (nr < num_pcie_ports) {
- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+ &sys->resources);
} else {
bus = NULL;
BUG();
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
deleted file mode 100644
index af0c212e3c7b..000000000000
--- a/arch/arm/mach-mx5/Kconfig
+++ /dev/null
@@ -1,244 +0,0 @@
-if ARCH_MX5
-
-# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
-# image. So for most time, SOC_IMX50/51/53 should be used.
-
-config ARCH_MX51
- bool
-
-config ARCH_MX50
- bool
-
-config ARCH_MX53
- bool
-
-config SOC_IMX50
- bool
- select CPU_V7
- select ARM_L1_CACHE_SHIFT_6
- select MXC_TZIC
- select ARCH_MXC_IOMUX_V3
- select ARCH_MXC_AUDMUX_V2
- select ARCH_HAS_CPUFREQ
- select ARCH_MX50
-
-config SOC_IMX51
- bool
- select CPU_V7
- select ARM_L1_CACHE_SHIFT_6
- select MXC_TZIC
- select ARCH_MXC_IOMUX_V3
- select ARCH_MXC_AUDMUX_V2
- select ARCH_HAS_CPUFREQ
- select ARCH_MX51
-
-config SOC_IMX53
- bool
- select CPU_V7
- select ARM_L1_CACHE_SHIFT_6
- select MXC_TZIC
- select ARCH_MXC_IOMUX_V3
- select ARCH_MX53
-
-#comment "i.MX50 machines:"
-
-config MACH_MX50_RDP
- bool "Support MX50 reference design platform"
- depends on BROKEN
- select SOC_IMX50
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Include support for MX50 reference design platform (RDP) board. This
- includes specific configurations for the board and its peripherals.
-
-comment "i.MX51 machines:"
-
-config MACH_IMX51_DT
- bool "Support i.MX51 platforms from device tree"
- select SOC_IMX51
- select USE_OF
- select MACH_MX51_BABBAGE
- help
- Include support for Freescale i.MX51 based platforms
- using the device tree for discovery
-
-config MACH_MX51_BABBAGE
- bool "Support MX51 BABBAGE platforms"
- select SOC_IMX51
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Include support for MX51 Babbage platform, also known as MX51EVK in
- u-boot. This includes specific configurations for the board and its
- peripherals.
-
-config MACH_MX51_3DS
- bool "Support MX51PDK (3DS)"
- select SOC_IMX51
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_KEYPAD
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_DEBUG_BOARD
- help
- Include support for MX51PDK (3DS) platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_EUKREA_CPUIMX51
- bool "Support Eukrea CPUIMX51 module"
- select SOC_IMX51
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Include support for Eukrea CPUIMX51 platform. This includes
- specific configurations for the module and its peripherals.
-
-choice
- prompt "Baseboard"
- depends on MACH_EUKREA_CPUIMX51
- default MACH_EUKREA_MBIMX51_BASEBOARD
-
-config MACH_EUKREA_MBIMX51_BASEBOARD
- prompt "Eukrea MBIMX51 development board"
- bool
- select IMX_HAVE_PLATFORM_IMX_KEYPAD
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select LEDS_GPIO_REGISTER
- help
- This adds board specific devices that can be found on Eukrea's
- MBIMX51 evaluation board.
-
-endchoice
-
-config MACH_EUKREA_CPUIMX51SD
- bool "Support Eukrea CPUIMX51SD module"
- select SOC_IMX51
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Include support for Eukrea CPUIMX51SD platform. This includes
- specific configurations for the module and its peripherals.
-
-choice
- prompt "Baseboard"
- depends on MACH_EUKREA_CPUIMX51SD
- default MACH_EUKREA_MBIMXSD51_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD51_BASEBOARD
- prompt "Eukrea MBIMXSD development board"
- bool
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select LEDS_GPIO_REGISTER
- help
- This adds board specific devices that can be found on Eukrea's
- MBIMXSD evaluation board.
-
-endchoice
-
-config MX51_EFIKA_COMMON
- bool
- select SOC_IMX51
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_PATA_IMX
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_ULPI if USB_ULPI
-
-config MACH_MX51_EFIKAMX
- bool "Support MX51 Genesi Efika MX nettop"
- select LEDS_GPIO_REGISTER
- select MX51_EFIKA_COMMON
- help
- Include support for Genesi Efika MX nettop. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX51_EFIKASB
- bool "Support MX51 Genesi Efika Smartbook"
- select LEDS_GPIO_REGISTER
- select MX51_EFIKA_COMMON
- help
- Include support for Genesi Efika Smartbook. This includes specific
- configurations for the board and its peripherals.
-
-comment "i.MX53 machines:"
-
-config MACH_IMX53_DT
- bool "Support i.MX53 platforms from device tree"
- select SOC_IMX53
- select USE_OF
- select MACH_MX53_ARD
- select MACH_MX53_EVK
- select MACH_MX53_LOCO
- select MACH_MX53_SMD
- help
- Include support for Freescale i.MX53 based platforms
- using the device tree for discovery
-
-config MACH_MX53_EVK
- bool "Support MX53 EVK platforms"
- select SOC_IMX53
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- select LEDS_GPIO_REGISTER
- help
- Include support for MX53 EVK platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX53_SMD
- bool "Support MX53 SMD platforms"
- select SOC_IMX53
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- help
- Include support for MX53 SMD platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX53_LOCO
- bool "Support MX53 LOCO platforms"
- select SOC_IMX53
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- select LEDS_GPIO_REGISTER
- help
- Include support for MX53 LOCO platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX53_ARD
- bool "Support MX53 ARD platforms"
- select SOC_IMX53
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_GPIO_KEYS
- help
- Include support for MX53 ARD platform. This includes specific
- configurations for the board and its peripherals.
-
-endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
deleted file mode 100644
index 0fc60807fa2b..000000000000
--- a/arch/arm/mach-mx5/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-obj-y := cpu.o mm.o clock-mx51-mx53.o ehci.o system.o
-
-obj-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
-obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
-obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
-obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
-obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
-obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
-obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
-obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
-obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
-obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
-obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
-
-obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
-obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
deleted file mode 100644
index ca207ca305ec..000000000000
--- a/arch/arm/mach-mx5/Makefile.boot
+++ /dev/null
@@ -1,9 +0,0 @@
- zreladdr-$(CONFIG_ARCH_MX50) += 0x70008000
-params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
-initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
- zreladdr-$(CONFIG_ARCH_MX51) += 0x90008000
-params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
-initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
- zreladdr-$(CONFIG_ARCH_MX53) += 0x70008000
-params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
-initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
deleted file mode 100644
index 98052fc852c7..000000000000
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/suspend.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include "crm_regs.h"
-
-static struct clk *gpc_dvfs_clk;
-
-static int mx5_suspend_prepare(void)
-{
- return clk_enable(gpc_dvfs_clk);
-}
-
-static int mx5_suspend_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_MEM:
- mx5_cpu_lp_set(STOP_POWER_OFF);
- break;
- case PM_SUSPEND_STANDBY:
- mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
- break;
- default:
- return -EINVAL;
- }
-
- if (state == PM_SUSPEND_MEM) {
- local_flush_tlb_all();
- flush_cache_all();
-
- /*clear the EMPGC0/1 bits */
- __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
- __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
- }
- cpu_do_idle();
- return 0;
-}
-
-static void mx5_suspend_finish(void)
-{
- clk_disable(gpc_dvfs_clk);
-}
-
-static int mx5_pm_valid(suspend_state_t state)
-{
- return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
-}
-
-static const struct platform_suspend_ops mx5_suspend_ops = {
- .valid = mx5_pm_valid,
- .prepare = mx5_suspend_prepare,
- .enter = mx5_suspend_enter,
- .finish = mx5_suspend_finish,
-};
-
-static int __init mx5_pm_init(void)
-{
- if (gpc_dvfs_clk == NULL)
- gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-
- if (!IS_ERR(gpc_dvfs_clk)) {
- if (cpu_is_mx51())
- suspend_set_ops(&mx5_suspend_ops);
- } else
- return -EPERM;
-
- return 0;
-}
-device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 904bd1dfcd2e..d965da45160e 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -33,7 +33,6 @@ config ARCH_OMAP3
default y
select CPU_V7
select USB_ARCH_HAS_EHCI
- select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
select ARCH_HAS_OPP
select PM_OPP if PM
select ARM_CPU_SUSPEND if PM
@@ -214,13 +213,12 @@ config MACH_OMAP3_PANDORA
depends on ARCH_OMAP3
default y
select OMAP_PACKAGE_CBB
- select REGULATOR_FIXED_VOLTAGE
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_OMAP3_TOUCHBOOK
bool "OMAP3 Touch Book"
depends on ARCH_OMAP3
default y
- select BACKLIGHT_CLASS_DEVICE
config MACH_OMAP_3430SDP
bool "OMAP 3430 SDP board"
@@ -266,7 +264,7 @@ config MACH_OMAP_ZOOM2
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
- select REGULATOR_FIXED_VOLTAGE
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_OMAP_ZOOM3
bool "OMAP3630 Zoom3 board"
@@ -276,7 +274,7 @@ config MACH_OMAP_ZOOM3
select SERIAL_8250
select SERIAL_CORE_CONSOLE
select SERIAL_8250_CONSOLE
- select REGULATOR_FIXED_VOLTAGE
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_CM_T35
bool "CompuLab CM-T35/CM-T3730 modules"
@@ -335,7 +333,7 @@ config MACH_OMAP_4430SDP
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
- select REGULATOR_FIXED_VOLTAGE
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_OMAP4_PANDA
bool "OMAP4 Panda Board"
@@ -343,7 +341,7 @@ config MACH_OMAP4_PANDA
depends on ARCH_OMAP4
select OMAP_PACKAGE_CBL
select OMAP_PACKAGE_CBS
- select REGULATOR_FIXED_VOLTAGE
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
config OMAP3_EMU
bool "OMAP3 debugging peripherals"
@@ -366,8 +364,8 @@ config OMAP3_SDRC_AC_TIMING
going on could result in system crashes;
config OMAP4_ERRATA_I688
- bool "OMAP4 errata: Async Bridge Corruption"
- depends on ARCH_OMAP4
+ bool "OMAP4 errata: Async Bridge Corruption (BROKEN)"
+ depends on ARCH_OMAP4 && BROKEN
select ARCH_HAS_BARRIERS
help
If a data is stalled inside asynchronous bridge because of back
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 2ceb75d21eb2..39fba9df17fb 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -602,20 +602,6 @@ static void __init omap_sfh7741prox_init(void)
__func__, OMAP4_SFH7741_ENABLE_GPIO, error);
}
-static void sdp4430_hdmi_mux_init(void)
-{
- /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
- omap_mux_init_signal("hdmi_hpd",
- OMAP_PIN_INPUT_PULLUP);
- omap_mux_init_signal("hdmi_cec",
- OMAP_PIN_INPUT_PULLUP);
- /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
- omap_mux_init_signal("hdmi_ddc_scl",
- OMAP_PIN_INPUT_PULLUP);
- omap_mux_init_signal("hdmi_ddc_sda",
- OMAP_PIN_INPUT_PULLUP);
-}
-
static struct gpio sdp4430_hdmi_gpios[] = {
{ HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
{ HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -833,9 +819,16 @@ static void omap_4430sdp_display_init(void)
pr_err("%s: Could not get display_sel GPIO\n", __func__);
sdp4430_lcd_init();
- sdp4430_hdmi_mux_init();
sdp4430_picodlp_init();
omap_display_init(&sdp4430_dss_data);
+ /*
+ * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+ * later have external pull up on the HDMI I2C lines
+ */
+ if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+ omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+ else
+ omap_hdmi_init(0);
}
#ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e96a2e7ad36f..30ad40db2cf3 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -412,21 +412,6 @@ int __init omap4_panda_dvi_init(void)
return r;
}
-
-static void omap4_panda_hdmi_mux_init(void)
-{
- /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
- omap_mux_init_signal("hdmi_hpd",
- OMAP_PIN_INPUT_PULLUP);
- omap_mux_init_signal("hdmi_cec",
- OMAP_PIN_INPUT_PULLUP);
- /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
- omap_mux_init_signal("hdmi_ddc_scl",
- OMAP_PIN_INPUT_PULLUP);
- omap_mux_init_signal("hdmi_ddc_sda",
- OMAP_PIN_INPUT_PULLUP);
-}
-
static struct gpio panda_hdmi_gpios[] = {
{ HDMI_GPIO_HPD, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_hpd" },
{ HDMI_GPIO_LS_OE, GPIOF_OUT_INIT_HIGH, "hdmi_gpio_ls_oe" },
@@ -478,8 +463,16 @@ void omap4_panda_display_init(void)
if (r)
pr_err("error initializing panda DVI\n");
- omap4_panda_hdmi_mux_init();
omap_display_init(&omap4_panda_dss_data);
+
+ /*
+ * OMAP4460SDP/Blaze and OMAP4430 ES2.3 SDP/Blaze boards and
+ * later have external pull up on the HDMI I2C lines
+ */
+ if (cpu_is_omap446x() || omap_rev() > OMAP4430_REV_ES2_2)
+ omap_hdmi_init(OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP);
+ else
+ omap_hdmi_init(0);
}
static void __init omap4_panda_init(void)
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index d67bcdf724d7..acb4e77b39ef 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -945,6 +945,9 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
},
#endif
{
+ I2C_BOARD_INFO("bq27200", 0x55),
+ },
+ {
I2C_BOARD_INFO("tpa6130a2", 0x60),
.platform_data = &rx51_tpa6130a2_data,
}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 35d5dffab7e1..283d11eae693 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -127,6 +127,10 @@ static struct platform_device omap2cam_device = {
};
#endif
+#if defined(CONFIG_IOMMU_API)
+
+#include <plat/iommu.h>
+
static struct resource omap3isp_resources[] = {
{
.start = OMAP3430_ISP_BASE,
@@ -211,12 +215,27 @@ static struct platform_device omap3isp_device = {
.resource = omap3isp_resources,
};
+static struct omap_iommu_arch_data omap3_isp_iommu = {
+ .name = "isp",
+};
+
int omap3_init_camera(struct isp_platform_data *pdata)
{
omap3isp_device.dev.platform_data = pdata;
+ omap3isp_device.dev.archdata.iommu = &omap3_isp_iommu;
+
return platform_device_register(&omap3isp_device);
}
+#else /* !CONFIG_IOMMU_API */
+
+int omap3_init_camera(struct isp_platform_data *pdata)
+{
+ return 0;
+}
+
+#endif
+
static inline void omap_init_camera(void)
{
#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
@@ -386,6 +405,7 @@ static int omap_mcspi_init(struct omap_hwmod *oh, void *unused)
break;
default:
pr_err("Invalid McSPI Revision value\n");
+ kfree(pdata);
return -EINVAL;
}
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index bc6cf863a563..3c446d1a1781 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -30,6 +30,7 @@
#include <plat/omap-pm.h>
#include "common.h"
+#include "mux.h"
#include "control.h"
#include "display.h"
@@ -97,6 +98,36 @@ static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
{ "dss_hdmi", "omapdss_hdmi", -1 },
};
+static void omap4_hdmi_mux_pads(enum omap_hdmi_flags flags)
+{
+ u32 reg;
+ u16 control_i2c_1;
+
+ /* PAD0_HDMI_HPD_PAD1_HDMI_CEC */
+ omap_mux_init_signal("hdmi_hpd",
+ OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("hdmi_cec",
+ OMAP_PIN_INPUT_PULLUP);
+ /* PAD0_HDMI_DDC_SCL_PAD1_HDMI_DDC_SDA */
+ omap_mux_init_signal("hdmi_ddc_scl",
+ OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("hdmi_ddc_sda",
+ OMAP_PIN_INPUT_PULLUP);
+
+ /*
+ * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and
+ * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable
+ * internal pull up resistor.
+ */
+ if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) {
+ control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1;
+ reg = omap4_ctrl_pad_readl(control_i2c_1);
+ reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK |
+ OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK);
+ omap4_ctrl_pad_writel(reg, control_i2c_1);
+ }
+}
+
static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
u32 enable_mask, enable_shift;
@@ -130,6 +161,14 @@ static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
return 0;
}
+int omap_hdmi_init(enum omap_hdmi_flags flags)
+{
+ if (cpu_is_omap44xx())
+ omap4_hdmi_mux_pads(flags);
+
+ return 0;
+}
+
static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
if (cpu_is_omap44xx())
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 130034bf01d5..dfffbbf4c009 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -528,7 +528,13 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
case GPMC_CONFIG_DEV_SIZE:
regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
+
+ /* clear 2 target bits */
+ regval &= ~GPMC_CONFIG1_DEVICESIZE(3);
+
+ /* set the proper value */
regval |= GPMC_CONFIG1_DEVICESIZE(wval);
+
gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval);
break;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index bd844af13af5..ad0adb5a1e0e 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -175,14 +175,15 @@ static void hsmmc2_select_input_clk_src(struct omap_mmc_platform_data *mmc)
{
u32 reg;
- if (mmc->slots[0].internal_clock) {
- reg = omap_ctrl_readl(control_devconf1_offset);
+ reg = omap_ctrl_readl(control_devconf1_offset);
+ if (mmc->slots[0].internal_clock)
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
- omap_ctrl_writel(reg, control_devconf1_offset);
- }
+ else
+ reg &= ~OMAP2_MMCSDIO2ADPCLKISEL;
+ omap_ctrl_writel(reg, control_devconf1_offset);
}
-static void hsmmc23_before_set_reg(struct device *dev, int slot,
+static void hsmmc2_before_set_reg(struct device *dev, int slot,
int power_on, int vdd)
{
struct omap_mmc_platform_data *mmc = dev->platform_data;
@@ -407,14 +408,13 @@ static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
c->caps &= ~MMC_CAP_8_BIT_DATA;
c->caps |= MMC_CAP_4_BIT_DATA;
}
- /* FALLTHROUGH */
- case 3:
if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
/* off-chip level shifting, or none */
- mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+ mmc->slots[0].before_set_reg = hsmmc2_before_set_reg;
mmc->slots[0].after_set_reg = NULL;
}
break;
+ case 3:
case 4:
case 5:
mmc->slots[0].before_set_reg = NULL;
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3f174d51f67f..eb50c29fb644 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -388,7 +388,7 @@ static void __init omap_hwmod_init_postsetup(void)
omap_pm_if_early_init();
}
-#ifdef CONFIG_ARCH_OMAP2
+#ifdef CONFIG_SOC_OMAP2420
void __init omap2420_init_early(void)
{
omap2_set_globals_242x();
@@ -400,7 +400,9 @@ void __init omap2420_init_early(void)
omap_hwmod_init_postsetup();
omap2420_clk_init();
}
+#endif
+#ifdef CONFIG_SOC_OMAP2430
void __init omap2430_init_early(void)
{
omap2_set_globals_243x();
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 28fcb27005d2..fb4bcf81a183 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -156,6 +156,9 @@ static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
else
/* The FIFO has 128 locations */
pdata->buffer_size = 0x80;
+ } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
+ /* The FIFO has 128 locations for all instances */
+ pdata->buffer_size = 0x80;
}
if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
diff --git a/arch/arm/mach-omap2/omap-secure.c b/arch/arm/mach-omap2/omap-secure.c
index 69f3c72d959b..d8f8ef40290f 100644
--- a/arch/arm/mach-omap2/omap-secure.c
+++ b/arch/arm/mach-omap2/omap-secure.c
@@ -16,6 +16,7 @@
#include <linux/memblock.h>
#include <asm/cacheflush.h>
+#include <asm/memblock.h>
#include <mach/omap-secure.h>
@@ -57,20 +58,10 @@ u32 omap_secure_dispatcher(u32 idx, u32 flag, u32 nargs, u32 arg1, u32 arg2,
/* Allocate the memory to save secure ram */
int __init omap_secure_ram_reserve_memblock(void)
{
- phys_addr_t paddr;
u32 size = OMAP_SECURE_RAM_STORAGE;
size = ALIGN(size, SZ_1M);
- paddr = memblock_alloc(size, SZ_1M);
- if (!paddr) {
- pr_err("%s: failed to reserve %x bytes\n",
- __func__, size);
- return -ENOMEM;
- }
- memblock_free(paddr, size);
- memblock_remove(paddr, size);
-
- omap_secure_memblock_base = paddr;
+ omap_secure_memblock_base = arm_memblock_steal(size, SZ_1M);
return 0;
}
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index bc16c818c6b7..40a8fbc07e4b 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -20,6 +20,7 @@
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/map.h>
+#include <asm/memblock.h>
#include <plat/irqs.h>
#include <plat/sram.h>
@@ -61,13 +62,8 @@ static int __init omap_barriers_init(void)
return -ENODEV;
size = ALIGN(PAGE_SIZE, SZ_1M);
- paddr = memblock_alloc(size, SZ_1M);
- if (!paddr) {
- pr_err("%s: failed to reserve 4 Kbytes\n", __func__);
- return -ENOMEM;
- }
- memblock_free(paddr, size);
- memblock_remove(paddr, size);
+ paddr = arm_memblock_steal(size, SZ_1M);
+
dram_io_desc[0].virtual = OMAP4_DRAM_BARRIER_VA;
dram_io_desc[0].pfn = __phys_to_pfn(paddr);
dram_io_desc[0].length = size;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
index c11273da5dcc..f08e442af397 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -56,27 +56,6 @@ struct omap_hwmod_class omap2_dss_hwmod_class = {
};
/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-struct omap_hwmod_class omap2_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap2_dispc_sysc,
-};
-
-/*
* 'rfbi' class
* remote frame buffer interface
*/
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index 177dee20faef..2a6729741b06 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -28,6 +28,28 @@ struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .dma_req = -1 }
};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &omap2_dispc_sysc,
+};
+
/* OMAP2xxx Timer Common */
static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
.rev_offs = 0x0000,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5324e8d93bc0..3c8dd928628e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1480,6 +1480,28 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.masters_cnt = ARRAY_SIZE(omap3xxx_dss_masters),
};
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSC_HAS_ENAWAKEUP),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &omap3_dispc_sysc,
+};
+
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod,
@@ -1503,7 +1525,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.name = "dss_dispc",
- .class = &omap2_dispc_hwmod_class,
+ .class = &omap3_dispc_hwmod_class,
.mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_alwon_fck",
.prcm = {
@@ -3523,12 +3545,6 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_uart2_hwmod,
&omap3xxx_uart3_hwmod,
- /* dss class */
- &omap3xxx_dss_dispc_hwmod,
- &omap3xxx_dss_dsi1_hwmod,
- &omap3xxx_dss_rfbi_hwmod,
- &omap3xxx_dss_venc_hwmod,
-
/* i2c class */
&omap3xxx_i2c1_hwmod,
&omap3xxx_i2c2_hwmod,
@@ -3635,6 +3651,15 @@ static __initdata struct omap_hwmod *am35xx_hwmods[] = {
NULL
};
+static __initdata struct omap_hwmod *omap3xxx_dss_hwmods[] = {
+ /* dss class */
+ &omap3xxx_dss_dispc_hwmod,
+ &omap3xxx_dss_dsi1_hwmod,
+ &omap3xxx_dss_rfbi_hwmod,
+ &omap3xxx_dss_venc_hwmod,
+ NULL
+};
+
int __init omap3xxx_hwmod_init(void)
{
int r;
@@ -3708,6 +3733,21 @@ int __init omap3xxx_hwmod_init(void)
if (h)
r = omap_hwmod_register(h);
+ if (r < 0)
+ return r;
+
+ /*
+ * DSS code presumes that dss_core hwmod is handled first,
+ * _before_ any other DSS related hwmods so register common
+ * DSS hwmods last to ensure that dss_core is already registered.
+ * Otherwise some change things may happen, for ex. if dispc
+ * is handled before dss_core and DSS is enabled in bootloader
+ * DIPSC will be reset with outputs enabled which sometimes leads
+ * to unrecoverable L3 error.
+ * XXX The long-term fix to this is to ensure modules are set up
+ * in dependency order in the hwmod core code.
+ */
+ r = omap_hwmod_register(omap3xxx_dss_hwmods);
return r;
}
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index f9f151081760..ef0524c10a84 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -1031,6 +1031,7 @@ static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
{
+ .name = "mpu",
.pa_start = 0x4012e000,
.pa_end = 0x4012e07f,
.flags = ADDR_TYPE_RT
@@ -1049,6 +1050,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
{
+ .name = "dma",
.pa_start = 0x4902e000,
.pa_end = 0x4902e07f,
.flags = ADDR_TYPE_RT
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index c1c4d86a79a8..9ce765407ad5 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -19,6 +19,7 @@
#include "common.h"
#include <plat/cpu.h>
#include <plat/prcm.h>
+#include <plat/irqs.h>
#include "vp.h"
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index 9dd93453e563..7e755bb0ffc4 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -897,7 +897,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
ret = sr_late_init(sr_info);
if (ret) {
pr_warning("%s: Error in SR late init\n", __func__);
- return ret;
+ goto err_iounmap;
}
}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 6eeff0e0ae01..5c9acea95761 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -270,7 +270,7 @@ static struct clocksource clocksource_gpt = {
static u32 notrace dmtimer_read_sched_clock(void)
{
if (clksrc.reserved)
- return __omap_dm_timer_read_counter(clksrc.io_base, 1);
+ return __omap_dm_timer_read_counter(&clksrc, 1);
return 0;
}
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index a494c470e3e4..09a045f0c406 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -177,7 +177,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCIe IO resource failed\n");
- sys->resource[0] = &res[0];
+ pci_add_resource(&sys->resources, &res[0]);
/*
* IORESOURCE_MEM
@@ -188,9 +188,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCIe Memory resource failed\n");
- sys->resource[1] = &res[1];
+ pci_add_resource(&sys->resources, &res[1]);
- sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
@@ -506,7 +505,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
if (request_resource(&ioport_resource, &res[0]))
panic("Request PCI IO resource failed\n");
- sys->resource[0] = &res[0];
+ pci_add_resource(&sys->resources, &res[0]);
/*
* IORESOURCE_MEM
@@ -517,9 +516,8 @@ static int __init pci_setup(struct pci_sys_data *sys)
res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
if (request_resource(&iomem_resource, &res[1]))
panic("Request PCI Memory resource failed\n");
- sys->resource[1] = &res[1];
+ pci_add_resource(&sys->resources, &res[1]);
- sys->resource[2] = NULL;
sys->io_offset = 0;
return 1;
@@ -580,9 +578,11 @@ struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys
struct pci_bus *bus;
if (nr == 0) {
- bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
+ bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
+ &sys->resources);
} else if (nr == 1 && !orion5x_pci_disabled) {
- bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
+ bus = pci_scan_root_bus(NULL, sys->busnr, &pci_ops, sys,
+ &sys->resources);
} else {
bus = NULL;
BUG();
diff --git a/arch/arm/mach-picoxcell/time.c b/arch/arm/mach-picoxcell/time.c
index 6c89cf8ab22e..2ecba6743b8e 100644
--- a/arch/arm/mach-picoxcell/time.c
+++ b/arch/arm/mach-picoxcell/time.c
@@ -67,7 +67,7 @@ static void picoxcell_add_clocksource(struct device_node *source_timer)
static void __iomem *sched_io_base;
-unsigned u32 notrace picoxcell_read_sched_clock(void)
+static u32 picoxcell_read_sched_clock(void)
{
return __raw_readl(sched_io_base);
}
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 66600f05e436..11f1e735966e 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -436,6 +436,14 @@ static struct platform_device corgiled_device = {
};
/*
+ * Corgi Audio
+ */
+static struct platform_device corgi_audio_device = {
+ .name = "corgi-audio",
+ .id = -1,
+};
+
+/*
* MMC/SD Device
*
* The card detect interrupt isn't debounced so we delay it by 250ms
@@ -641,6 +649,7 @@ static struct platform_device *devices[] __initdata = {
&corgifb_device,
&corgikbd_device,
&corgiled_device,
+ &corgi_audio_device,
&sharpsl_nand_device,
&sharpsl_rom_device,
};
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 18fd177073f4..5bc13121eac5 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -415,29 +415,9 @@ static struct resource pxa_rtc_resources[] = {
},
};
-static struct resource sa1100_rtc_resources[] = {
- [0] = {
- .start = 0x40900000,
- .end = 0x409000ff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_RTC1Hz,
- .end = IRQ_RTC1Hz,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_RTCAlrm,
- .end = IRQ_RTCAlrm,
- .flags = IORESOURCE_IRQ,
- },
-};
-
struct platform_device sa1100_device_rtc = {
.name = "sa1100-rtc",
.id = -1,
- .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
- .resource = sa1100_rtc_resources,
};
struct platform_device pxa_device_rtc = {
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index f79a610c62fc..4cb2391a782e 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -528,12 +528,18 @@ static struct platform_device e740_t7l66xb_device = {
.resource = eseries_tmio_resources,
};
+static struct platform_device e740_audio_device = {
+ .name = "e740-audio",
+ .id = -1,
+};
+
/* ----------------------------------------------------------------------- */
static struct platform_device *e740_devices[] __initdata = {
&e740_fb_device,
&e740_t7l66xb_device,
&e7xx_gpio_vbus,
+ &e740_audio_device,
};
static void __init e740_init(void)
@@ -722,12 +728,18 @@ static struct platform_device e750_tc6393xb_device = {
.resource = eseries_tmio_resources,
};
+static struct platform_device e750_audio_device = {
+ .name = "e750-audio",
+ .id = -1,
+};
+
/* ------------------------------------------------------------- */
static struct platform_device *e750_devices[] __initdata = {
&e750_fb_device,
&e750_tc6393xb_device,
&e7xx_gpio_vbus,
+ &e750_audio_device,
};
static void __init e750_init(void)
@@ -929,12 +941,18 @@ static struct platform_device e800_tc6393xb_device = {
.resource = eseries_tmio_resources,
};
+static struct platform_device e800_audio_device = {
+ .name = "e800-audio",
+ .id = -1,
+};
+
/* ----------------------------------------------------------------------- */
static struct platform_device *e800_devices[] __initdata = {
&e800_fb_device,
&e800_tc6393xb_device,
&e800_gpio_vbus,
+ &e800_audio_device,
};
static void __init e800_init(void)
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 69036e42ca31..744baee12c0c 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -158,6 +158,11 @@ static struct scoop_pcmcia_config poodle_pcmcia_config = {
EXPORT_SYMBOL(poodle_scoop_device);
+static struct platform_device poodle_audio_device = {
+ .name = "poodle-audio",
+ .id = -1,
+};
+
/* LoCoMo device */
static struct resource locomo_resources[] = {
[0] = {
@@ -407,6 +412,7 @@ static struct platform_device sharpsl_rom_device = {
static struct platform_device *devices[] __initdata = {
&poodle_locomo_device,
&poodle_scoop_device,
+ &poodle_audio_device,
&sharpsl_nand_device,
&sharpsl_rom_device,
};
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index adf058fa97ee..91e4f6c03766 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -209,8 +209,6 @@ static struct clk_lookup pxa25x_clkregs[] = {
INIT_CLKREG(&clk_pxa25x_gpio11, NULL, "GPIO11_CLK"),
INIT_CLKREG(&clk_pxa25x_gpio12, NULL, "GPIO12_CLK"),
INIT_CLKREG(&clk_pxa25x_mem, "pxa2xx-pcmcia", NULL),
- INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
static struct clk_lookup pxa25x_hwuart_clkreg =
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 180bd8675d4b..aed6cbcf3866 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -230,8 +230,6 @@ static struct clk_lookup pxa27x_clkregs[] = {
INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
- INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
#ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pxa300.c b/arch/arm/mach-pxa/pxa300.c
index 0388eda7878a..40bb16501d86 100644
--- a/arch/arm/mach-pxa/pxa300.c
+++ b/arch/arm/mach-pxa/pxa300.c
@@ -89,7 +89,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA300_GCU, 0, 0);
static struct clk_lookup common_clkregs[] = {
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
diff --git a/arch/arm/mach-pxa/pxa320.c b/arch/arm/mach-pxa/pxa320.c
index d487e1ff4c9a..8d614ecd8e99 100644
--- a/arch/arm/mach-pxa/pxa320.c
+++ b/arch/arm/mach-pxa/pxa320.c
@@ -83,7 +83,6 @@ static DEFINE_PXA3_CKEN(gcu, PXA320_GCU, 0, 0);
static struct clk_lookup pxa320_clkregs[] = {
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_gcu, "pxa3xx-gcu", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
};
static int __init pxa320_init(void)
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f107c71c7589..4f402afa6609 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -67,7 +67,6 @@ static struct clk_lookup pxa3xx_clkregs[] = {
INIT_CLKREG(&clk_pxa3xx_pout, NULL, "CLK_POUT"),
/* Power I2C clock is always on */
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
INIT_CLKREG(&clk_pxa3xx_lcd, "pxa2xx-fb", NULL),
INIT_CLKREG(&clk_pxa3xx_camera, NULL, "CAMCLK"),
INIT_CLKREG(&clk_pxa3xx_ac97, NULL, "AC97CLK"),
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index fccc644702e6..d082a583df78 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -217,7 +217,6 @@ static struct clk_lookup pxa95x_clkregs[] = {
INIT_CLKREG(&clk_pxa95x_pout, NULL, "CLK_POUT"),
/* Power I2C clock is always on */
INIT_CLKREG(&clk_dummy, "pxa3xx-pwri2c.1", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
INIT_CLKREG(&clk_pxa95x_lcd, "pxa2xx-fb", NULL),
INIT_CLKREG(&clk_pxa95x_ffuart, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_pxa95x_btuart, "pxa2xx-uart.1", NULL),
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index d8a2467de92e..b0656e158d90 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -593,10 +593,16 @@ static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
.udc_command = sg2_udc_command,
};
+static struct platform_device imote2_audio_device = {
+ .name = "imote2-audio",
+ .id = -1,
+};
+
static struct platform_device *imote2_devices[] = {
&stargate2_flash_device,
&imote2_leds,
&sht15,
+ &imote2_audio_device,
};
static void __init imote2_init(void)
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 7ce5c436cc4e..4d4eb60bad1e 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -889,6 +889,11 @@ static struct platform_device wm9712_device = {
.id = -1,
};
+static struct platform_device tosa_audio_device = {
+ .name = "tosa-audio",
+ .id = -1,
+};
+
static struct platform_device *devices[] __initdata = {
&tosascoop_device,
&tosascoop_jc_device,
@@ -901,6 +906,7 @@ static struct platform_device *devices[] __initdata = {
&sharpsl_rom_device,
&wm9712_device,
&tosa_gpio_vbus,
+ &tosa_audio_device,
};
static void tosa_poweroff(void)
diff --git a/arch/arm/mach-realview/hotplug.c b/arch/arm/mach-realview/hotplug.c
index ac1aed2a8da4..eb55f05bef3a 100644
--- a/arch/arm/mach-realview/hotplug.c
+++ b/arch/arm/mach-realview/hotplug.c
@@ -13,6 +13,7 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
extern volatile int pen_release;
diff --git a/arch/arm/mach-realview/include/mach/board-eb.h b/arch/arm/mach-realview/include/mach/board-eb.h
index 794a8d91a6a6..124bce6b4d7b 100644
--- a/arch/arm/mach-realview/include/mach/board-eb.h
+++ b/arch/arm/mach-realview/include/mach/board-eb.h
@@ -47,21 +47,23 @@
#define REALVIEW_EB_USB_BASE 0x4F000000 /* USB */
#ifdef CONFIG_REALVIEW_EB_ARM11MP_REVB
-#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
-#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB11MP_TWD_BASE 0x10100600
-#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
#else
-#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
-#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
-#define REALVIEW_EB11MP_TWD_BASE 0x1F000600
-#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
+#define REALVIEW_EB11MP_PRIV_MEM_BASE 0x1F000000
#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
#endif
+#define REALVIEW_EB11MP_PRIV_MEM_SIZE SZ_8K
+#define REALVIEW_EB11MP_PRIV_MEM_OFF(x) (REALVIEW_EB11MP_PRIV_MEM_BASE + (x))
+
+#define REALVIEW_EB11MP_SCU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0) /* SCU registers */
+#define REALVIEW_EB11MP_GIC_CPU_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0100) /* Generic interrupt controller CPU interface */
+#define REALVIEW_EB11MP_TWD_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x0600)
+#define REALVIEW_EB11MP_GIC_DIST_BASE REALVIEW_EB11MP_PRIV_MEM_OFF(0x1000) /* Generic interrupt controller distributor */
+
/*
* Core tile identification (REALVIEW_SYS_PROCID)
*/
diff --git a/arch/arm/mach-realview/include/mach/board-pb11mp.h b/arch/arm/mach-realview/include/mach/board-pb11mp.h
index 7abf918b77e9..aa2d4e02ea2c 100644
--- a/arch/arm/mach-realview/include/mach/board-pb11mp.h
+++ b/arch/arm/mach-realview/include/mach/board-pb11mp.h
@@ -75,6 +75,8 @@
/*
* Testchip peripheral and fpga gic regions
*/
+#define REALVIEW_TC11MP_PRIV_MEM_BASE 0x1F000000
+#define REALVIEW_TC11MP_PRIV_MEM_SIZE SZ_8K
#define REALVIEW_TC11MP_SCU_BASE 0x1F000000 /* IRQ, Test chip */
#define REALVIEW_TC11MP_GIC_CPU_BASE 0x1F000100 /* Test chip interrupt controller CPU interface */
#define REALVIEW_TC11MP_TWD_BASE 0x1F000600
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index e83c654a58d0..17c878ddbc70 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -17,7 +17,6 @@
#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
-#include <asm/unified.h>
#include <mach/board-eb.h>
#include <mach/board-pb11mp.h>
@@ -75,6 +74,6 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
*/
- __raw_writel(BSYM(virt_to_phys(versatile_secondary_startup)),
+ __raw_writel(virt_to_phys(versatile_secondary_startup),
__io_address(REALVIEW_SYS_FLAGSSET));
}
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 0069561464f9..9578145f2df0 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -91,14 +91,9 @@ static struct map_desc realview_eb_io_desc[] __initdata = {
static struct map_desc realview_eb11mp_io_desc[] __initdata = {
{
- .virtual = IO_ADDRESS(REALVIEW_EB11MP_SCU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB11MP_SCU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_EB11MP_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_EB11MP_GIC_DIST_BASE),
- .length = SZ_4K,
+ .virtual = IO_ADDRESS(REALVIEW_EB11MP_PRIV_MEM_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_EB11MP_PRIV_MEM_BASE),
+ .length = REALVIEW_EB11MP_PRIV_MEM_SIZE,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_EB11MP_L220_BASE),
@@ -117,17 +112,14 @@ static void __init realview_eb_map_io(void)
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
- .irq_base = -1,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = -1,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
- .irq_base = -1,
};
static struct pl022_ssp_controller ssp0_plat_data = {
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 8fe395568a47..e4abe94fb11a 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -113,17 +113,14 @@ static void __init realview_pb1176_map_io(void)
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
- .irq_base = -1,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = -1,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
- .irq_base = -1,
};
static struct pl022_ssp_controller ssp0_plat_data = {
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 34a26011bb89..2147335f66f5 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -64,15 +64,10 @@ static struct map_desc realview_pb11mp_io_desc[] __initdata = {
.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
.length = SZ_4K,
.type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_CPU_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_CPU_BASE),
- .length = SZ_4K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(REALVIEW_TC11MP_GIC_DIST_BASE),
- .pfn = __phys_to_pfn(REALVIEW_TC11MP_GIC_DIST_BASE),
- .length = SZ_4K,
+ }, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
+ .virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
+ .pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
+ .length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
.type = MT_DEVICE,
}, {
.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
@@ -112,17 +107,14 @@ static void __init realview_pb11mp_map_io(void)
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
- .irq_base = -1,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = -1,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
- .irq_base = -1,
};
static struct pl022_ssp_controller ssp0_plat_data = {
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index d26a6def1d65..25b2e59296f8 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -102,17 +102,14 @@ static void __init realview_pba8_map_io(void)
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
- .irq_base = -1,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = -1,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
- .irq_base = -1,
};
static struct pl022_ssp_controller ssp0_plat_data = {
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a250fb4124bf..ac715645b860 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -124,17 +124,14 @@ static void __init realview_pbx_map_io(void)
static struct pl061_platform_data gpio0_plat_data = {
.gpio_base = 0,
- .irq_base = -1,
};
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = -1,
};
static struct pl061_platform_data gpio2_plat_data = {
.gpio_base = 16,
- .irq_base = -1,
};
static struct pl022_ssp_controller ssp0_plat_data = {
diff --git a/arch/arm/mach-s3c64xx/include/mach/crag6410.h b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
index 5d55ab018b6b..4cb2f951f1e9 100644
--- a/arch/arm/mach-s3c64xx/include/mach/crag6410.h
+++ b/arch/arm/mach-s3c64xx/include/mach/crag6410.h
@@ -21,5 +21,6 @@
#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 32)
#define BANFF_PMIC_GPIO_BASE (GPIO_BOARD_START + 64)
+#define MMGPIO_GPIO_BASE (GPIO_BOARD_START + 96)
#endif
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 680fd758ff2d..8077f650eb0e 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -260,6 +260,7 @@ static struct platform_device crag6410_dm9k_device = {
static struct resource crag6410_mmgpio_resource[] = {
[0] = {
+ .name = "dat",
.start = S3C64XX_PA_XM0CSN4 + 1,
.end = S3C64XX_PA_XM0CSN4 + 1,
.flags = IORESOURCE_MEM,
@@ -272,7 +273,7 @@ static struct platform_device crag6410_mmgpio = {
.resource = crag6410_mmgpio_resource,
.num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
.dev.platform_data = &(struct bgpio_pdata) {
- .base = -1,
+ .base = MMGPIO_GPIO_BASE,
},
};
@@ -286,8 +287,8 @@ static struct platform_device lowland_device = {
.id = -1,
};
-static struct platform_device speyside_wm8962_device = {
- .name = "speyside-wm8962",
+static struct platform_device tobermory_device = {
+ .name = "tobermory",
.id = -1,
};
@@ -328,7 +329,6 @@ static struct platform_device wallvdd_device = {
static struct platform_device *crag6410_devices[] __initdata = {
&s3c_device_hsmmc0,
- &s3c_device_hsmmc1,
&s3c_device_hsmmc2,
&s3c_device_i2c0,
&s3c_device_i2c1,
@@ -347,7 +347,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
&crag6410_lcd_powerdev,
&crag6410_backlight_device,
&speyside_device,
- &speyside_wm8962_device,
+ &tobermory_device,
&littlemill_device,
&lowland_device,
&wallvdd_device,
@@ -355,7 +355,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
static struct pca953x_platform_data crag6410_pca_data = {
.gpio_base = PCA935X_GPIO_BASE,
- .irq_base = 0,
+ .irq_base = -1,
};
/* VDDARM is controlled by DVS1 connected to GPK(0) */
@@ -683,12 +683,6 @@ static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
.cd_type = S3C_SDHCI_CD_PERMANENT,
};
-static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
- .max_width = 4,
- .cd_type = S3C_SDHCI_CD_GPIO,
- .ext_cd_gpio = S3C64XX_GPF(11),
-};
-
static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
{
/* Set all the necessary GPG pins to special-function 2 */
@@ -723,7 +717,6 @@ static void __init crag6410_machine_init(void)
gpio_direction_output(S3C64XX_GPF(10), 1);
s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
- s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
s3c_i2c0_set_platdata(&i2c0_pdata);
diff --git a/arch/arm/mach-s3c64xx/pm.c b/arch/arm/mach-s3c64xx/pm.c
index 055dac90e0e2..7d3e81b9dd06 100644
--- a/arch/arm/mach-s3c64xx/pm.c
+++ b/arch/arm/mach-s3c64xx/pm.c
@@ -346,23 +346,10 @@ int __init s3c64xx_pm_init(void)
static __init int s3c64xx_pm_initcall(void)
{
- u32 val;
-
pm_cpu_prep = s3c64xx_pm_prepare;
pm_cpu_sleep = s3c64xx_cpu_suspend;
pm_uart_udivslot = 1;
- /*
- * Unconditionally disable power domains that contain only
- * blocks which have no mainline driver support.
- */
- val = __raw_readl(S3C64XX_NORMAL_CFG);
- val &= ~(S3C64XX_NORMALCFG_DOMAIN_G_ON |
- S3C64XX_NORMALCFG_DOMAIN_V_ON |
- S3C64XX_NORMALCFG_DOMAIN_I_ON |
- S3C64XX_NORMALCFG_DOMAIN_P_ON);
- __raw_writel(val, S3C64XX_NORMAL_CFG);
-
#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
gpio_request(S3C64XX_GPN(12), "DEBUG_LED0");
gpio_request(S3C64XX_GPN(13), "DEBUG_LED1");
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 6b93e200bcac..0c4b76ab4d8e 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -268,7 +268,7 @@ static void __init map_sa1100_gpio_regs( void )
int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
pmd_t *pmd;
- pmd = pmd_offset(pgd_offset_k(virt), virt);
+ pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt);
*pmd = __pmd(phys | prot);
flush_pmd_entry(pmd);
}
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index d6df9f6c9f7e..dab3c6347a8f 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,39 +11,17 @@
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/mutex.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
#include <mach/hardware.h>
-struct clkops {
- void (*enable)(struct clk *);
- void (*disable)(struct clk *);
- unsigned long (*getrate)(struct clk *);
-};
-
+/*
+ * Very simple clock implementation - we only have one clock to deal with.
+ */
struct clk {
- const struct clkops *ops;
- unsigned long rate;
unsigned int enabled;
};
-#define INIT_CLKREG(_clk, _devname, _conname) \
- { \
- .clk = _clk, \
- .dev_id = _devname, \
- .con_id = _conname, \
- }
-
-#define DEFINE_CLK(_name, _ops, _rate) \
-struct clk clk_##_name = { \
- .ops = _ops, \
- .rate = _rate, \
- }
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static void clk_gpio27_enable(struct clk *clk)
+static void clk_gpio27_enable(void)
{
/*
* First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -54,22 +32,38 @@ static void clk_gpio27_enable(struct clk *clk)
TUCR = TUCR_3_6864MHz;
}
-static void clk_gpio27_disable(struct clk *clk)
+static void clk_gpio27_disable(void)
{
TUCR = 0;
GPDR &= ~GPIO_32_768kHz;
GAFR &= ~GPIO_32_768kHz;
}
+static struct clk clk_gpio27;
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+ const char *devname = dev_name(dev);
+
+ return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
+}
+EXPORT_SYMBOL(clk_get);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
int clk_enable(struct clk *clk)
{
unsigned long flags;
spin_lock_irqsave(&clocks_lock, flags);
if (clk->enabled++ == 0)
- clk->ops->enable(clk);
+ clk_gpio27_enable();
spin_unlock_irqrestore(&clocks_lock, flags);
-
return 0;
}
EXPORT_SYMBOL(clk_enable);
@@ -82,48 +76,13 @@ void clk_disable(struct clk *clk)
spin_lock_irqsave(&clocks_lock, flags);
if (--clk->enabled == 0)
- clk->ops->disable(clk);
+ clk_gpio27_disable();
spin_unlock_irqrestore(&clocks_lock, flags);
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
- unsigned long rate;
-
- rate = clk->rate;
- if (clk->ops->getrate)
- rate = clk->ops->getrate(clk);
-
- return rate;
+ return 3686400;
}
EXPORT_SYMBOL(clk_get_rate);
-
-const struct clkops clk_gpio27_ops = {
- .enable = clk_gpio27_enable,
- .disable = clk_gpio27_disable,
-};
-
-static void clk_dummy_enable(struct clk *clk) { }
-static void clk_dummy_disable(struct clk *clk) { }
-
-const struct clkops clk_dummy_ops = {
- .enable = clk_dummy_enable,
- .disable = clk_dummy_disable,
-};
-
-static DEFINE_CLK(gpio27, &clk_gpio27_ops, 3686400);
-static DEFINE_CLK(dummy, &clk_dummy_ops, 0);
-
-static struct clk_lookup sa11xx_clkregs[] = {
- INIT_CLKREG(&clk_gpio27, "sa1111.0", NULL),
- INIT_CLKREG(&clk_dummy, "sa1100-rtc", NULL),
-};
-
-static int __init sa11xx_clk_init(void)
-{
- clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));
- return 0;
-}
-
-postcore_initcall(sa11xx_clk_init);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index b9060e236def..fd5652118ed1 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -138,8 +138,6 @@ static struct pda_power_pdata collie_power_data = {
static struct resource collie_power_resource[] = {
{
.name = "ac",
- .start = gpio_to_irq(COLLIE_GPIO_AC_IN),
- .end = gpio_to_irq(COLLIE_GPIO_AC_IN),
.flags = IORESOURCE_IRQ |
IORESOURCE_IRQ_HIGHEDGE |
IORESOURCE_IRQ_LOWEDGE,
@@ -341,7 +339,8 @@ static void __init collie_init(void)
GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
-
+ collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
+ collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
platform_scoop_config = &collie_pcmcia_config;
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index aaa8acf76b7b..19b2053f5af4 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -228,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
return 0;
}
-static struct cpufreq_driver sa1100_driver = {
+static struct cpufreq_driver sa1100_driver __refdata = {
.flags = CPUFREQ_STICKY,
.verify = sa11x0_verify_speed,
.target = sa1100_target,
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 480d2ea46b00..bb10ee2cb89f 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -345,29 +345,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
sa11x0_register_device(&sa11x0ir_device, irda);
}
-static struct resource sa11x0rtc_resources[] = {
- [0] = {
- .start = 0x90010000,
- .end = 0x900100ff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = IRQ_RTC1Hz,
- .end = IRQ_RTC1Hz,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
- .start = IRQ_RTCAlrm,
- .end = IRQ_RTCAlrm,
- .flags = IORESOURCE_IRQ,
- },
-};
-
static struct platform_device sa11x0rtc_device = {
.name = "sa1100-rtc",
.id = -1,
- .resource = sa11x0rtc_resources,
- .num_resources = ARRAY_SIZE(sa11x0rtc_resources),
};
static struct platform_device *sa11x0_devices[] __initdata = {
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index 703631887c94..a38fc4f54241 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -51,7 +51,4 @@ static inline void gpio_set_value(unsigned gpio, int value)
#define gpio_cansleep __gpio_cansleep
-#define gpio_to_irq(gpio) ((gpio < 11) ? (IRQ_GPIO0 + gpio) : \
- (IRQ_GPIO11 - 11 + gpio))
-
#endif
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index f50b00bd18a0..b412fc09c80c 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -198,3 +198,5 @@ static int __init jornada_ssp_init(void)
{
return platform_driver_register(&jornadassp_driver);
}
+
+module_init(jornada_ssp_init);
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index dd39fee59549..0d01ca788922 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -131,7 +131,8 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
{
- return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
+ return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
+ &sys->resources);
}
static struct resource pci_io_ports = {
@@ -226,7 +227,7 @@ static struct resource pci_prefetchable_memory = {
.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
};
-static int __init pci_nanoengine_setup_resources(struct resource **resource)
+static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
{
if (request_resource(&ioport_resource, &pci_io_ports)) {
printk(KERN_ERR "PCI: unable to allocate io port region\n");
@@ -243,9 +244,9 @@ static int __init pci_nanoengine_setup_resources(struct resource **resource)
printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
return -EBUSY;
}
- resource[0] = &pci_io_ports;
- resource[1] = &pci_non_prefetchable_memory;
- resource[2] = &pci_prefetchable_memory;
+ pci_add_resource(&sys->resources, &pci_io_ports);
+ pci_add_resource(&sys->resources, &pci_non_prefetchable_memory);
+ pci_add_resource(&sys->resources, &pci_prefetchable_memory);
return 1;
}
@@ -260,7 +261,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
if (nr == 0) {
sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
sys->io_offset = 0x400;
- ret = pci_nanoengine_setup_resources(sys->resource);
+ ret = pci_nanoengine_setup_resources(sys);
/* Enable alternate memory bus master mode, see
* "Intel StrongARM SA1110 Developer's Manual",
* section 10.8, "Alternate Memory Bus Master Mode". */
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0828fab2b65c..060e5644c49c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -28,6 +28,19 @@ config ARCH_SH73A0
select ARM_GIC
select I2C
+config ARCH_R8A7740
+ bool "R-Mobile A1 (R8A77400)"
+ select CPU_V7
+ select SH_CLK_CPG
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+
+config ARCH_R8A7779
+ bool "R-Car H1 (R8A77790)"
+ select CPU_V7
+ select SH_CLK_CPG
+ select ARM_GIC
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+
comment "SH-Mobile Board Type"
config MACH_G3EVM
@@ -75,6 +88,16 @@ config MACH_KOTA2
select ARCH_REQUIRE_GPIOLIB
depends on ARCH_SH73A0
+config MACH_BONITO
+ bool "bonito board"
+ select ARCH_REQUIRE_GPIOLIB
+ depends on ARCH_R8A7740
+
+config MACH_MARZEN
+ bool "MARZEN board"
+ depends on ARCH_R8A7779
+ select ARCH_REQUIRE_GPIOLIB
+
comment "SH-Mobile System Configuration"
menu "Memory configuration"
@@ -83,7 +106,7 @@ config MEMORY_START
hex "Physical memory start address"
default "0x50000000" if MACH_G3EVM
default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
- MACH_MACKEREL
+ MACH_MACKEREL || MACH_BONITO
default "0x41000000" if MACH_KOTA2
default "0x00000000"
---help---
@@ -95,7 +118,7 @@ config MEMORY_SIZE
hex "Physical memory size"
default "0x08000000" if MACH_G3EVM
default "0x08000000" if MACH_G4EVM
- default "0x20000000" if MACH_AG5EVM
+ default "0x20000000" if MACH_AG5EVM || MACH_BONITO
default "0x1e000000" if MACH_KOTA2
default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
default "0x04000000"
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 5ca1f9d66995..7ad6954c46cd 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -10,12 +10,15 @@ obj-$(CONFIG_ARCH_SH7367) += setup-sh7367.o clock-sh7367.o intc-sh7367.o
obj-$(CONFIG_ARCH_SH7377) += setup-sh7377.o clock-sh7377.o intc-sh7377.o
obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o
obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o
+obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o
+obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o
# SMP objects
smp-y := platsmp.o headsmp.o
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
smp-$(CONFIG_LOCAL_TIMERS) += localtimer.o
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o
+smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
# Pinmux setup
pfc-y :=
@@ -23,16 +26,20 @@ pfc-$(CONFIG_ARCH_SH7367) += pfc-sh7367.o
pfc-$(CONFIG_ARCH_SH7377) += pfc-sh7377.o
pfc-$(CONFIG_ARCH_SH7372) += pfc-sh7372.o
pfc-$(CONFIG_ARCH_SH73A0) += pfc-sh73a0.o
+pfc-$(CONFIG_ARCH_R8A7740) += pfc-r8a7740.o
+pfc-$(CONFIG_ARCH_R8A7779) += pfc-r8a7779.o
# IRQ objects
obj-$(CONFIG_ARCH_SH7367) += entry-intc.o
obj-$(CONFIG_ARCH_SH7377) += entry-intc.o
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
+obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
# PM objects
obj-$(CONFIG_SUSPEND) += suspend.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
+obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
# Board objects
obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
@@ -41,6 +48,8 @@ obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
+obj-$(CONFIG_MACH_BONITO) += board-bonito.o
+obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
# Framework support
obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index a4e6ca04e319..eff8a96c75ee 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -271,7 +271,7 @@ static struct sh_mobile_lcdc_info lcdc0_info = {
.flags = LCDC_FLAGS_DWPOL,
.lcd_size_cfg.width = 44,
.lcd_size_cfg.height = 79,
- .bpp = 16,
+ .fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = lcdc0_modes,
.num_cfg = ARRAY_SIZE(lcdc0_modes),
.board_cfg = {
@@ -321,12 +321,46 @@ static struct resource mipidsi0_resources[] = {
},
};
+#define DSI0PHYCR 0xe615006c
+static int sh_mipi_set_dot_clock(struct platform_device *pdev,
+ void __iomem *base,
+ int enable)
+{
+ struct clk *pck;
+ int ret;
+
+ pck = clk_get(&pdev->dev, "dsip_clk");
+ if (IS_ERR(pck)) {
+ ret = PTR_ERR(pck);
+ goto sh_mipi_set_dot_clock_pck_err;
+ }
+
+ if (enable) {
+ clk_set_rate(pck, clk_round_rate(pck, 24000000));
+ __raw_writel(0x2a809010, DSI0PHYCR);
+ clk_enable(pck);
+ } else {
+ clk_disable(pck);
+ }
+
+ ret = 0;
+
+ clk_put(pck);
+
+sh_mipi_set_dot_clock_pck_err:
+ return ret;
+}
+
static struct sh_mipi_dsi_info mipidsi0_info = {
.data_format = MIPI_RGB888,
.lcd_chan = &lcdc0_info.ch[0],
+ .lane = 2,
.vsynw_offset = 20,
.clksrc = 1,
- .flags = SH_MIPI_DSI_HSABM,
+ .flags = SH_MIPI_DSI_HSABM |
+ SH_MIPI_DSI_SYNC_PULSES_MODE |
+ SH_MIPI_DSI_HSbyteCLK,
+ .set_dot_clock = sh_mipi_set_dot_clock,
};
static struct platform_device mipidsi0_device = {
@@ -472,8 +506,6 @@ static void __init ag5evm_map_io(void)
shmobile_setup_console();
}
-#define DSI0PHYCR 0xe615006c
-
static void __init ag5evm_init(void)
{
sh73a0_pinmux_init();
@@ -554,9 +586,6 @@ static void __init ag5evm_init(void)
gpio_direction_output(GPIO_PORT235, 0);
lcd_backlight_reset();
- /* MIPI-DSI clock setup */
- __raw_writel(0x2a809010, DSI0PHYCR);
-
/* enable SDHI0 on CN15 [SD I/F] */
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHIWP0, NULL);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 6a6f9f7568c2..aab0a349f759 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -491,7 +491,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
- .bpp = 16,
+ .fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = ap4evb_lcdc_modes,
.num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
.meram_cfg = &lcd_meram_cfg,
@@ -564,6 +564,30 @@ static struct platform_device keysc_device = {
};
/* MIPI-DSI */
+#define PHYCTRL 0x0070
+static int sh_mipi_set_dot_clock(struct platform_device *pdev,
+ void __iomem *base,
+ int enable)
+{
+ struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
+ void __iomem *phy = base + PHYCTRL;
+
+ if (IS_ERR(pck))
+ return PTR_ERR(pck);
+
+ if (enable) {
+ clk_set_rate(pck, clk_round_rate(pck, 24000000));
+ iowrite32(ioread32(phy) | (0xb << 8), phy);
+ clk_enable(pck);
+ } else {
+ clk_disable(pck);
+ }
+
+ clk_put(pck);
+
+ return 0;
+}
+
static struct resource mipidsi0_resources[] = {
[0] = {
.start = 0xffc60000,
@@ -580,7 +604,11 @@ static struct resource mipidsi0_resources[] = {
static struct sh_mipi_dsi_info mipidsi0_info = {
.data_format = MIPI_RGB888,
.lcd_chan = &lcdc_info.ch[0],
+ .lane = 2,
.vsynw_offset = 17,
+ .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
+ SH_MIPI_DSI_HSbyteCLK,
+ .set_dot_clock = sh_mipi_set_dot_clock,
};
static struct platform_device mipidsi0_device = {
@@ -762,9 +790,22 @@ static struct platform_device fsi_device = {
},
};
+static struct fsi_ak4642_info fsi2_ak4643_info = {
+ .name = "AK4643",
+ .card = "FSI2A-AK4643",
+ .cpu_dai = "fsia-dai",
+ .codec = "ak4642-codec.0-0013",
+ .platform = "sh_fsi2",
+ .id = FSI_PORT_A,
+};
+
static struct platform_device fsi_ak4643_device = {
- .name = "sh_fsi2_a_ak4643",
+ .name = "fsi-ak4642-audio",
+ .dev = {
+ .platform_data = &fsi_info,
+ },
};
+
static struct sh_mobile_meram_cfg hdmi_meram_cfg = {
.icb[0] = {
.marker_icb = 30,
@@ -785,7 +826,7 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
.meram_dev = &meram_info,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
- .bpp = 16,
+ .fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
new file mode 100644
index 000000000000..4d2201622323
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -0,0 +1,522 @@
+/*
+ * bonito board support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/r8a7740.h>
+#include <video/sh_mobile_lcdc.h>
+
+/*
+ * CS Address device note
+ *----------------------------------------------------------------
+ * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
+ * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
+ * 4 -
+ * 5A -
+ * 5B 0x1600_0000 SRAM (8MB)
+ * 6 0x1800_0000 FPGA (64K)
+ * 0x1801_0000 Ether (4KB)
+ * 0x1801_1000 USB (4KB)
+ */
+
+/*
+ * SW12
+ *
+ * bit1 bit2 bit3
+ *----------------------------------------------------------------------------
+ * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
+ * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
+ */
+
+/*
+ * SCIFA5 (CN42)
+ *
+ * S38.3 = ON
+ * S39.6 = ON
+ * S43.1 = ON
+ */
+
+/*
+ * LCDC0 (CN3/CN4/CN7)
+ *
+ * S38.1 = OFF
+ * S38.2 = OFF
+ */
+
+/*
+ * FPGA
+ */
+#define IRQSR0 0x0020
+#define IRQSR1 0x0022
+#define IRQMR0 0x0030
+#define IRQMR1 0x0032
+#define BUSSWMR1 0x0070
+#define BUSSWMR2 0x0072
+#define BUSSWMR3 0x0074
+#define BUSSWMR4 0x0076
+
+#define LCDCR 0x10B4
+#define DEVRSTCR1 0x10D0
+#define DEVRSTCR2 0x10D2
+#define A1MDSR 0x10E0
+#define BVERR 0x1100
+
+/* FPGA IRQ */
+#define FPGA_IRQ_BASE (512)
+#define FPGA_IRQ0 (FPGA_IRQ_BASE)
+#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
+#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
+static u16 bonito_fpga_read(u32 offset)
+{
+ return __raw_readw(0xf0003000 + offset);
+}
+
+static void bonito_fpga_write(u32 offset, u16 val)
+{
+ __raw_writew(val, 0xf0003000 + offset);
+}
+
+static void bonito_fpga_irq_disable(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
+ int shift = irq % 16;
+
+ bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
+}
+
+static void bonito_fpga_irq_enable(struct irq_data *data)
+{
+ unsigned int irq = data->irq;
+ u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
+ int shift = irq % 16;
+
+ bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
+}
+
+static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
+ .name = "bonito FPGA",
+ .irq_mask = bonito_fpga_irq_disable,
+ .irq_unmask = bonito_fpga_irq_enable,
+};
+
+static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
+{
+ u32 val = bonito_fpga_read(IRQSR1) << 16 |
+ bonito_fpga_read(IRQSR0);
+ u32 mask = bonito_fpga_read(IRQMR1) << 16 |
+ bonito_fpga_read(IRQMR0);
+
+ int i;
+
+ val &= ~mask;
+
+ for (i = 0; i < 32; i++) {
+ if (!(val & (1 << i)))
+ continue;
+
+ generic_handle_irq(FPGA_IRQ_BASE + i);
+ }
+}
+
+static void bonito_fpga_init(void)
+{
+ int i;
+
+ bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
+ bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
+
+ /* Device reset */
+ bonito_fpga_write(DEVRSTCR1,
+ (1 << 2)); /* Eth */
+
+ /* FPGA irq require special handling */
+ for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
+ irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
+ handle_level_irq, "level");
+ set_irq_flags(i, IRQF_VALID); /* yuck */
+ }
+
+ irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
+ irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
+}
+
+/*
+* PMIC settings
+*
+* FIXME
+*
+* bonito board needs some settings by pmic which use i2c access.
+* pmic settings use device_initcall() here for use it.
+*/
+static __u8 *pmic_settings = NULL;
+static __u8 pmic_do_2A[] = {
+ 0x1C, 0x09,
+ 0x1A, 0x80,
+ 0xff, 0xff,
+};
+
+static int __init pmic_init(void)
+{
+ struct i2c_adapter *a = i2c_get_adapter(0);
+ struct i2c_msg msg;
+ __u8 buf[2];
+ int i, ret;
+
+ if (!pmic_settings)
+ return 0;
+ if (!a)
+ return 0;
+
+ msg.addr = 0x46;
+ msg.buf = buf;
+ msg.len = 2;
+ msg.flags = 0;
+
+ for (i = 0; ; i += 2) {
+ buf[0] = pmic_settings[i + 0];
+ buf[1] = pmic_settings[i + 1];
+
+ if ((0xff == buf[0]) && (0xff == buf[1]))
+ break;
+
+ ret = i2c_transfer(a, &msg, 1);
+ if (ret < 0) {
+ pr_err("i2c transfer fail\n");
+ break;
+ }
+ }
+
+ return 0;
+}
+device_initcall(pmic_init);
+
+/*
+ * LCDC0
+ */
+static const struct fb_videomode lcdc0_mode = {
+ .name = "WVGA Panel",
+ .xres = 800,
+ .yres = 480,
+ .left_margin = 88,
+ .right_margin = 40,
+ .hsync_len = 128,
+ .upper_margin = 20,
+ .lower_margin = 5,
+ .vsync_len = 5,
+ .sync = 0,
+};
+
+static struct sh_mobile_lcdc_info lcdc0_info = {
+ .clock_source = LCDC_CLK_BUS,
+ .ch[0] = {
+ .chan = LCDC_CHAN_MAINLCD,
+ .bpp = 16,
+ .interface_type = RGB24,
+ .clock_divider = 5,
+ .flags = 0,
+ .lcd_cfg = &lcdc0_mode,
+ .num_cfg = 1,
+ .lcd_size_cfg = {
+ .width = 152,
+ .height = 91,
+ },
+ },
+};
+
+static struct resource lcdc0_resources[] = {
+ [0] = {
+ .name = "LCDC0",
+ .start = 0xfe940000,
+ .end = 0xfe943fff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = intcs_evt2irq(0x0580),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device lcdc0_device = {
+ .name = "sh_mobile_lcdc_fb",
+ .id = 0,
+ .resource = lcdc0_resources,
+ .num_resources = ARRAY_SIZE(lcdc0_resources),
+ .dev = {
+ .platform_data = &lcdc0_info,
+ .coherent_dma_mask = ~0,
+ },
+};
+
+/*
+ * SMSC 9221
+ */
+static struct resource smsc_resources[] = {
+ [0] = {
+ .start = 0x18010000,
+ .end = 0x18011000 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = FPGA_ETH_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct smsc911x_platform_config smsc_platdata = {
+ .flags = SMSC911X_USE_16BIT,
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device smsc_device = {
+ .name = "smsc911x",
+ .dev = {
+ .platform_data = &smsc_platdata,
+ },
+ .resource = smsc_resources,
+ .num_resources = ARRAY_SIZE(smsc_resources),
+};
+
+/*
+ * core board devices
+ */
+static struct platform_device *bonito_core_devices[] __initdata = {
+};
+
+/*
+ * base board devices
+ */
+static struct platform_device *bonito_base_devices[] __initdata = {
+ &lcdc0_device,
+ &smsc_device,
+};
+
+/*
+ * map I/O
+ */
+static struct map_desc bonito_io_desc[] __initdata = {
+ /*
+ * for CPGA/INTC/PFC
+ * 0xe6000000-0xefffffff -> 0xe6000000-0xefffffff
+ */
+ {
+ .virtual = 0xe6000000,
+ .pfn = __phys_to_pfn(0xe6000000),
+ .length = 160 << 20,
+ .type = MT_DEVICE_NONSHARED
+ },
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * for l2x0_init()
+ * 0xf0100000-0xf0101000 -> 0xf0002000-0xf0003000
+ */
+ {
+ .virtual = 0xf0002000,
+ .pfn = __phys_to_pfn(0xf0100000),
+ .length = PAGE_SIZE,
+ .type = MT_DEVICE_NONSHARED
+ },
+#endif
+ /*
+ * for FPGA (0x1800000-0x19ffffff)
+ * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
+ */
+ {
+ .virtual = 0xf0003000,
+ .pfn = __phys_to_pfn(0x18000000),
+ .length = PAGE_SIZE * 2,
+ .type = MT_DEVICE_NONSHARED
+ }
+};
+
+static void __init bonito_map_io(void)
+{
+ iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
+
+ /* setup early devices and console here as well */
+ r8a7740_add_early_devices();
+ shmobile_setup_console();
+}
+
+/*
+ * board init
+ */
+#define BIT_ON(sw, bit) (sw & (1 << bit))
+#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
+
+#define VCCQ1CR 0xE6058140
+#define VCCQ1LCDCR 0xE6058186
+
+static void __init bonito_init(void)
+{
+ u16 val;
+
+ r8a7740_pinmux_init();
+ bonito_fpga_init();
+
+ pmic_settings = pmic_do_2A;
+
+ /*
+ * core board settings
+ */
+
+#ifdef CONFIG_CACHE_L2X0
+ /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+ l2x0_init(__io(0xf0002000), 0x40440000, 0x82000fff);
+#endif
+
+ r8a7740_add_standard_devices();
+
+ platform_add_devices(bonito_core_devices,
+ ARRAY_SIZE(bonito_core_devices));
+
+ /*
+ * base board settings
+ */
+ gpio_request(GPIO_PORT176, NULL);
+ gpio_direction_input(GPIO_PORT176);
+ if (!gpio_get_value(GPIO_PORT176)) {
+ u16 bsw2;
+ u16 bsw3;
+ u16 bsw4;
+
+ /*
+ * FPGA
+ */
+ gpio_request(GPIO_FN_CS5B, NULL);
+ gpio_request(GPIO_FN_CS6A, NULL);
+ gpio_request(GPIO_FN_CS5A_PORT105, NULL);
+ gpio_request(GPIO_FN_IRQ10, NULL);
+
+ val = bonito_fpga_read(BVERR);
+ pr_info("bonito version: cpu %02x, base %02x\n",
+ ((val >> 8) & 0xFF),
+ ((val >> 0) & 0xFF));
+
+ bsw2 = bonito_fpga_read(BUSSWMR2);
+ bsw3 = bonito_fpga_read(BUSSWMR3);
+ bsw4 = bonito_fpga_read(BUSSWMR4);
+
+ /*
+ * SCIFA5 (CN42)
+ */
+ if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
+ BIT_OFF(bsw3, 9) && /* S39.6 = ON */
+ BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
+ gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL);
+ gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL);
+ }
+
+ /*
+ * LCDC0 (CN3)
+ */
+ if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
+ BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
+ gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
+ gpio_request(GPIO_FN_LCD0_D0, NULL);
+ gpio_request(GPIO_FN_LCD0_D1, NULL);
+ gpio_request(GPIO_FN_LCD0_D2, NULL);
+ gpio_request(GPIO_FN_LCD0_D3, NULL);
+ gpio_request(GPIO_FN_LCD0_D4, NULL);
+ gpio_request(GPIO_FN_LCD0_D5, NULL);
+ gpio_request(GPIO_FN_LCD0_D6, NULL);
+ gpio_request(GPIO_FN_LCD0_D7, NULL);
+ gpio_request(GPIO_FN_LCD0_D8, NULL);
+ gpio_request(GPIO_FN_LCD0_D9, NULL);
+ gpio_request(GPIO_FN_LCD0_D10, NULL);
+ gpio_request(GPIO_FN_LCD0_D11, NULL);
+ gpio_request(GPIO_FN_LCD0_D12, NULL);
+ gpio_request(GPIO_FN_LCD0_D13, NULL);
+ gpio_request(GPIO_FN_LCD0_D14, NULL);
+ gpio_request(GPIO_FN_LCD0_D15, NULL);
+ gpio_request(GPIO_FN_LCD0_D16, NULL);
+ gpio_request(GPIO_FN_LCD0_D17, NULL);
+ gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
+ gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
+ gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
+ gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
+ gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
+ gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
+ gpio_request(GPIO_FN_LCD0_DCK, NULL);
+ gpio_request(GPIO_FN_LCD0_VSYN, NULL);
+ gpio_request(GPIO_FN_LCD0_HSYN, NULL);
+ gpio_request(GPIO_FN_LCD0_DISP, NULL);
+ gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
+
+ gpio_request(GPIO_PORT61, NULL); /* LCDDON */
+ gpio_direction_output(GPIO_PORT61, 1);
+
+ /* backlight on */
+ bonito_fpga_write(LCDCR, 1);
+
+ /* drivability Max */
+ __raw_writew(0x00FF , VCCQ1LCDCR);
+ __raw_writew(0xFFFF , VCCQ1CR);
+ }
+
+ platform_add_devices(bonito_base_devices,
+ ARRAY_SIZE(bonito_base_devices));
+ }
+}
+
+static void __init bonito_timer_init(void)
+{
+ u16 val;
+ u8 md_ck = 0;
+
+ /* read MD_CK value */
+ val = bonito_fpga_read(A1MDSR);
+ if (val & (1 << 10))
+ md_ck |= MD_CK2;
+ if (val & (1 << 9))
+ md_ck |= MD_CK1;
+ if (val & (1 << 8))
+ md_ck |= MD_CK0;
+
+ r8a7740_clock_init(md_ck);
+ shmobile_timer.init();
+}
+
+struct sys_timer bonito_timer = {
+ .init = bonito_timer_init,
+};
+
+MACHINE_START(BONITO, "bonito")
+ .map_io = bonito_map_io,
+ .init_irq = r8a7740_init_irq,
+ .handle_irq = shmobile_handle_irq_intc,
+ .init_machine = bonito_init,
+ .timer = &bonito_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index ed5256687397..9b42fbd10f8e 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -388,7 +388,7 @@ static struct sh_mobile_lcdc_info lcdc_info = {
.clock_source = LCDC_CLK_BUS,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
- .bpp = 16,
+ .fourcc = V4L2_PIX_FMT_RGB565,
.lcd_cfg = mackerel_lcdc_modes,
.num_cfg = ARRAY_SIZE(mackerel_lcdc_modes),
.interface_type = RGB24,
@@ -451,7 +451,7 @@ static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
.clock_source = LCDC_CLK_EXTERNAL,
.ch[0] = {
.chan = LCDC_CHAN_MAINLCD,
- .bpp = 16,
+ .fourcc = V4L2_PIX_FMT_RGB565,
.interface_type = RGB24,
.clock_divider = 1,
.flags = LCDC_FLAGS_DWPOL,
@@ -990,8 +990,20 @@ static struct platform_device fsi_device = {
},
};
+static struct fsi_ak4642_info fsi2_ak4643_info = {
+ .name = "AK4643",
+ .card = "FSI2A-AK4643",
+ .cpu_dai = "fsia-dai",
+ .codec = "ak4642-codec.0-0013",
+ .platform = "sh_fsi2",
+ .id = FSI_PORT_A,
+};
+
static struct platform_device fsi_ak4643_device = {
- .name = "sh_fsi2_a_ak4643",
+ .name = "fsi-ak4642-audio",
+ .dev = {
+ .platform_data = &fsi2_ak4643_info,
+ },
};
/*
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
new file mode 100644
index 000000000000..f0e02c0ce99f
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -0,0 +1,157 @@
+/*
+ * marzen board support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/dma-mapping.h>
+#include <linux/smsc911x.h>
+#include <mach/hardware.h>
+#include <mach/r8a7779.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
+#include <asm/traps.h>
+
+/* SMSC LAN89218 */
+static struct resource smsc911x_resources[] = {
+ [0] = {
+ .start = 0x18000000, /* ExCS0 */
+ .end = 0x180000ff, /* A1->A7 */
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(28), /* IRQ 1 */
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct smsc911x_platform_config smsc911x_platdata = {
+ .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device eth_device = {
+ .name = "smsc911x",
+ .id = 0,
+ .dev = {
+ .platform_data = &smsc911x_platdata,
+ },
+ .resource = smsc911x_resources,
+ .num_resources = ARRAY_SIZE(smsc911x_resources),
+};
+
+static struct platform_device *marzen_devices[] __initdata = {
+ &eth_device,
+};
+
+static struct map_desc marzen_io_desc[] __initdata = {
+ /* 2M entity map for 0xf0000000 (MPCORE) */
+ {
+ .virtual = 0xf0000000,
+ .pfn = __phys_to_pfn(0xf0000000),
+ .length = SZ_2M,
+ .type = MT_DEVICE_NONSHARED
+ },
+ /* 16M entity map for 0xfexxxxxx (DMAC-S/HPBREG/INTC2/LRAM/DBSC) */
+ {
+ .virtual = 0xfe000000,
+ .pfn = __phys_to_pfn(0xfe000000),
+ .length = SZ_16M,
+ .type = MT_DEVICE_NONSHARED
+ },
+};
+
+static void __init marzen_map_io(void)
+{
+ iotable_init(marzen_io_desc, ARRAY_SIZE(marzen_io_desc));
+}
+
+static void __init marzen_init_early(void)
+{
+ r8a7779_add_early_devices();
+
+ /* Early serial console setup is not included here due to
+ * memory map collisions. The SCIF serial ports in r8a7779
+ * are difficult to entity map 1:1 due to collision with the
+ * virtual memory range used by the coherent DMA code on ARM.
+ *
+ * Anyone wanting to debug early can remove UPF_IOREMAP from
+ * the sh-sci serial console platform data, adjust mapbase
+ * to a static M:N virt:phys mapping that needs to be added to
+ * the mappings passed with iotable_init() above.
+ *
+ * Then add a call to shmobile_setup_console() from this function.
+ *
+ * As a final step pass earlyprint=sh-sci.2,115200 on the kernel
+ * command line.
+ */
+}
+
+static void __init marzen_init(void)
+{
+ r8a7779_pinmux_init();
+
+ /* SCIF2 (CN18: DEBUG0) */
+ gpio_request(GPIO_FN_TX2_C, NULL);
+ gpio_request(GPIO_FN_RX2_C, NULL);
+
+ /* SCIF4 (CN19: DEBUG1) */
+ gpio_request(GPIO_FN_TX4, NULL);
+ gpio_request(GPIO_FN_RX4, NULL);
+
+ /* LAN89218 */
+ gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
+ gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
+
+ r8a7779_add_standard_devices();
+ platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
+}
+
+static void __init marzen_timer_init(void)
+{
+ r8a7779_clock_init();
+ shmobile_timer.init();
+ return;
+}
+
+struct sys_timer marzen_timer = {
+ .init = marzen_timer_init,
+};
+
+MACHINE_START(MARZEN, "marzen")
+ .map_io = marzen_map_io,
+ .init_early = marzen_init_early,
+ .nr_irqs = NR_IRQS_LEGACY,
+ .init_irq = r8a7779_init_irq,
+ .handle_irq = gic_handle_irq,
+ .init_machine = marzen_init,
+ .timer = &marzen_timer,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
new file mode 100644
index 000000000000..3b35b9afc001
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -0,0 +1,382 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+#include <mach/r8a7740.h>
+
+/*
+ * | MDx | XTAL1/EXTAL1 | System | EXTALR |
+ * Clock |-------+-----------------+ clock | 32.768 | RCLK
+ * Mode | 2/1/0 | src MHz | source | KHz | source
+ * -------+-------+-----------------+-----------+--------+----------
+ * 0 | 0 0 0 | External 20~50 | XTAL1 | O | EXTALR
+ * 1 | 0 0 1 | Crystal 20~30 | XTAL1 | O | EXTALR
+ * 2 | 0 1 0 | External 40~50 | XTAL1 / 2 | O | EXTALR
+ * 3 | 0 1 1 | Crystal 40~50 | XTAL1 / 2 | O | EXTALR
+ * 4 | 1 0 0 | External 20~50 | XTAL1 | x | XTAL1 / 1024
+ * 5 | 1 0 1 | Crystal 20~30 | XTAL1 | x | XTAL1 / 1024
+ * 6 | 1 1 0 | External 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
+ * 7 | 1 1 1 | Crystal 40~50 | XTAL1 / 2 | x | XTAL1 / 2048
+ */
+
+/* CPG registers */
+#define FRQCRA 0xe6150000
+#define FRQCRB 0xe6150004
+#define FRQCRC 0xe61500e0
+#define PLLC01CR 0xe6150028
+
+#define SUBCKCR 0xe6150080
+
+#define MSTPSR0 0xe6150030
+#define MSTPSR1 0xe6150038
+#define MSTPSR2 0xe6150040
+#define MSTPSR3 0xe6150048
+#define MSTPSR4 0xe615004c
+#define SMSTPCR0 0xe6150130
+#define SMSTPCR1 0xe6150134
+#define SMSTPCR2 0xe6150138
+#define SMSTPCR3 0xe615013c
+#define SMSTPCR4 0xe6150140
+
+/* Fixed 32 KHz root clock from EXTALR pin */
+static struct clk extalr_clk = {
+ .rate = 32768,
+};
+
+/*
+ * 25MHz default rate for the EXTAL1 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk extal1_clk = {
+ .rate = 25000000,
+};
+
+/*
+ * 48MHz default rate for the EXTAL2 root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk extal2_clk = {
+ .rate = 48000000,
+};
+
+/*
+ * 27MHz default rate for the DV_CLKI root input clock.
+ * If needed, reset this with clk_set_rate() from the platform code.
+ */
+static struct clk dv_clk = {
+ .rate = 27000000,
+};
+
+static unsigned long div_recalc(struct clk *clk)
+{
+ return clk->parent->rate / (int)(clk->priv);
+}
+
+static struct clk_ops div_clk_ops = {
+ .recalc = div_recalc,
+};
+
+/* extal1 / 2 */
+static struct clk extal1_div2_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)2,
+ .parent = &extal1_clk,
+};
+
+/* extal1 / 1024 */
+static struct clk extal1_div1024_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)1024,
+ .parent = &extal1_clk,
+};
+
+/* extal1 / 2 / 1024 */
+static struct clk extal1_div2048_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)1024,
+ .parent = &extal1_div2_clk,
+};
+
+/* extal2 / 2 */
+static struct clk extal2_div2_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)2,
+ .parent = &extal2_clk,
+};
+
+static struct clk_ops followparent_clk_ops = {
+ .recalc = followparent_recalc,
+};
+
+/* Main clock */
+static struct clk system_clk = {
+ .ops = &followparent_clk_ops,
+};
+
+static struct clk system_div2_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)2,
+ .parent = &system_clk,
+};
+
+/* r_clk */
+static struct clk r_clk = {
+ .ops = &followparent_clk_ops,
+};
+
+/* PLLC0/PLLC1 */
+static unsigned long pllc01_recalc(struct clk *clk)
+{
+ unsigned long mult = 1;
+
+ if (__raw_readl(PLLC01CR) & (1 << 14))
+ mult = ((__raw_readl(clk->enable_reg) >> 24) & 0x7f) + 1;
+
+ return clk->parent->rate * mult;
+}
+
+static struct clk_ops pllc01_clk_ops = {
+ .recalc = pllc01_recalc,
+};
+
+static struct clk pllc0_clk = {
+ .ops = &pllc01_clk_ops,
+ .flags = CLK_ENABLE_ON_INIT,
+ .parent = &system_clk,
+ .enable_reg = (void __iomem *)FRQCRC,
+};
+
+static struct clk pllc1_clk = {
+ .ops = &pllc01_clk_ops,
+ .flags = CLK_ENABLE_ON_INIT,
+ .parent = &system_div2_clk,
+ .enable_reg = (void __iomem *)FRQCRA,
+};
+
+/* PLLC1 / 2 */
+static struct clk pllc1_div2_clk = {
+ .ops = &div_clk_ops,
+ .priv = (void *)2,
+ .parent = &pllc1_clk,
+};
+
+struct clk *main_clks[] = {
+ &extalr_clk,
+ &extal1_clk,
+ &extal2_clk,
+ &extal1_div2_clk,
+ &extal1_div1024_clk,
+ &extal1_div2048_clk,
+ &extal2_div2_clk,
+ &dv_clk,
+ &system_clk,
+ &system_div2_clk,
+ &r_clk,
+ &pllc0_clk,
+ &pllc1_clk,
+ &pllc1_div2_clk,
+};
+
+static void div4_kick(struct clk *clk)
+{
+ unsigned long value;
+
+ /* set KICK bit in FRQCRB to update hardware setting */
+ value = __raw_readl(FRQCRB);
+ value |= (1 << 31);
+ __raw_writel(value, FRQCRB);
+}
+
+static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
+ 24, 32, 36, 48, 0, 72, 96, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+ .divisors = divisors,
+ .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+ .div_mult_table = &div4_div_mult_table,
+ .kick = div4_kick,
+};
+
+enum {
+ DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_HP,
+ DIV4_HPP, DIV4_S, DIV4_ZB, DIV4_M3, DIV4_CP,
+ DIV4_NR
+};
+
+struct clk div4_clks[DIV4_NR] = {
+ [DIV4_I] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
+ [DIV4_ZG] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
+ [DIV4_B] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
+ [DIV4_M1] = SH_CLK_DIV4(&pllc1_clk, FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
+ [DIV4_HP] = SH_CLK_DIV4(&pllc1_clk, FRQCRB, 4, 0x6fff, 0),
+ [DIV4_HPP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 20, 0x6fff, 0),
+ [DIV4_S] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 12, 0x6fff, 0),
+ [DIV4_ZB] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 8, 0x6fff, 0),
+ [DIV4_M3] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 4, 0x6fff, 0),
+ [DIV4_CP] = SH_CLK_DIV4(&pllc1_clk, FRQCRC, 0, 0x6fff, 0),
+};
+
+enum {
+ DIV6_SUB,
+ DIV6_NR
+};
+
+static struct clk div6_clks[DIV6_NR] = {
+ [DIV6_SUB] = SH_CLK_DIV6(&pllc1_div2_clk, SUBCKCR, 0),
+};
+
+enum {
+ MSTP125,
+ MSTP116, MSTP111, MSTP100, MSTP117,
+
+ MSTP230,
+ MSTP222,
+ MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
+
+ MSTP329, MSTP323,
+
+ MSTP_NR
+};
+
+static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP125] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
+ [MSTP117] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
+ [MSTP116] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+ [MSTP111] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR1, 11, 0), /* TMU1 */
+ [MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
+
+ [MSTP230] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 30, 0), /* SCIFA6 */
+ [MSTP222] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 22, 0), /* SCIFA7 */
+ [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
+ [MSTP206] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
+ [MSTP204] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
+ [MSTP203] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
+ [MSTP202] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
+ [MSTP201] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
+ [MSTP200] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
+
+ [MSTP329] = SH_CLK_MSTP32(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
+ [MSTP323] = SH_CLK_MSTP32(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
+};
+
+static struct clk_lookup lookups[] = {
+ /* main clocks */
+ CLKDEV_CON_ID("extalr", &extalr_clk),
+ CLKDEV_CON_ID("extal1", &extal1_clk),
+ CLKDEV_CON_ID("extal2", &extal2_clk),
+ CLKDEV_CON_ID("extal1_div2", &extal1_div2_clk),
+ CLKDEV_CON_ID("extal1_div1024", &extal1_div1024_clk),
+ CLKDEV_CON_ID("extal1_div2048", &extal1_div2048_clk),
+ CLKDEV_CON_ID("extal2_div2", &extal2_div2_clk),
+ CLKDEV_CON_ID("dv_clk", &dv_clk),
+ CLKDEV_CON_ID("system_clk", &system_clk),
+ CLKDEV_CON_ID("system_div2_clk", &system_div2_clk),
+ CLKDEV_CON_ID("r_clk", &r_clk),
+ CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
+ CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
+ CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
+
+ /* DIV4 clocks */
+ CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
+ CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
+ CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
+ CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
+ CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
+ CLKDEV_CON_ID("hpp_clk", &div4_clks[DIV4_HPP]),
+ CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
+ CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
+ CLKDEV_CON_ID("m3_clk", &div4_clks[DIV4_M3]),
+ CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
+
+ /* DIV6 clocks */
+ CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
+
+ /* MSTP32 clocks */
+ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]),
+ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP111]),
+ CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]),
+ CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]),
+ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]),
+
+ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
+ CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
+ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
+ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
+ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
+ CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
+ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
+
+ CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
+ CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
+
+ CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
+ CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
+};
+
+void __init r8a7740_clock_init(u8 md_ck)
+{
+ int k, ret = 0;
+
+ /* detect system clock parent */
+ if (md_ck & MD_CK1)
+ system_clk.parent = &extal1_div2_clk;
+ else
+ system_clk.parent = &extal1_clk;
+
+ /* detect RCLK parent */
+ switch (md_ck & (MD_CK2 | MD_CK1)) {
+ case MD_CK2 | MD_CK1:
+ r_clk.parent = &extal1_div2048_clk;
+ break;
+ case MD_CK2:
+ r_clk.parent = &extal1_div1024_clk;
+ break;
+ case MD_CK1:
+ default:
+ r_clk.parent = &extalr_clk;
+ break;
+ }
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+ if (!ret)
+ ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+
+ if (!ret)
+ ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ if (!ret)
+ clk_init();
+ else
+ panic("failed to setup r8a7740 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
new file mode 100644
index 000000000000..b4b0e8cd096d
--- /dev/null
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -0,0 +1,176 @@
+/*
+ * r8a7779 clock framework support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/sh_clk.h>
+#include <linux/clkdev.h>
+#include <mach/common.h>
+
+#define FRQMR 0xffc80014
+#define MSTPCR0 0xffc80030
+#define MSTPCR1 0xffc80034
+#define MSTPCR3 0xffc8003c
+#define MSTPSR1 0xffc80044
+#define MSTPSR4 0xffc80048
+#define MSTPSR6 0xffc8004c
+#define MSTPCR4 0xffc80050
+#define MSTPCR5 0xffc80054
+#define MSTPCR6 0xffc80058
+#define MSTPCR7 0xffc80040
+
+/* ioremap() through clock mapping mandatory to avoid
+ * collision with ARM coherent DMA virtual memory range.
+ */
+
+static struct clk_mapping cpg_mapping = {
+ .phys = 0xffc80000,
+ .len = 0x80,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk plla_clk = {
+ .rate = 1500000000,
+ .mapping = &cpg_mapping,
+};
+
+static struct clk *main_clks[] = {
+ &plla_clk,
+};
+
+static int divisors[] = { 0, 0, 0, 6, 8, 12, 16, 0, 24, 32, 36, 0, 0, 0, 0, 0 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+ .divisors = divisors,
+ .nr_divisors = ARRAY_SIZE(divisors),
+};
+
+static struct clk_div4_table div4_table = {
+ .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_S, DIV4_OUT, DIV4_S4, DIV4_S3, DIV4_S1, DIV4_P, DIV4_NR };
+
+static struct clk div4_clks[DIV4_NR] = {
+ [DIV4_S] = SH_CLK_DIV4(&plla_clk, FRQMR, 20,
+ 0x0018, CLK_ENABLE_ON_INIT),
+ [DIV4_OUT] = SH_CLK_DIV4(&plla_clk, FRQMR, 16,
+ 0x0700, CLK_ENABLE_ON_INIT),
+ [DIV4_S4] = SH_CLK_DIV4(&plla_clk, FRQMR, 12,
+ 0x0040, CLK_ENABLE_ON_INIT),
+ [DIV4_S3] = SH_CLK_DIV4(&plla_clk, FRQMR, 8,
+ 0x0010, CLK_ENABLE_ON_INIT),
+ [DIV4_S1] = SH_CLK_DIV4(&plla_clk, FRQMR, 4,
+ 0x0060, CLK_ENABLE_ON_INIT),
+ [DIV4_P] = SH_CLK_DIV4(&plla_clk, FRQMR, 0,
+ 0x0300, CLK_ENABLE_ON_INIT),
+};
+
+enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+ MSTP016, MSTP015, MSTP014,
+ MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
+ [MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
+ [MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
+ [MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0), /* SCIF3 */
+ [MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0), /* SCIF4 */
+ [MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0), /* SCIF5 */
+ [MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0), /* TMU0 */
+ [MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), /* TMU1 */
+ [MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0), /* TMU2 */
+};
+
+static unsigned long mul4_recalc(struct clk *clk)
+{
+ return clk->parent->rate * 4;
+}
+
+static struct clk_ops mul4_clk_ops = {
+ .recalc = mul4_recalc,
+};
+
+struct clk clkz_clk = {
+ .ops = &mul4_clk_ops,
+ .parent = &div4_clks[DIV4_S],
+};
+
+struct clk clkzs_clk = {
+ /* clks x 4 / 4 = clks */
+ .parent = &div4_clks[DIV4_S],
+};
+
+static struct clk *late_main_clks[] = {
+ &clkz_clk,
+ &clkzs_clk,
+};
+
+static struct clk_lookup lookups[] = {
+ /* main clocks */
+ CLKDEV_CON_ID("plla_clk", &plla_clk),
+ CLKDEV_CON_ID("clkz_clk", &clkz_clk),
+ CLKDEV_CON_ID("clkzs_clk", &clkzs_clk),
+
+ /* DIV4 clocks */
+ CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_S]),
+ CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_OUT]),
+ CLKDEV_CON_ID("shyway4_clk", &div4_clks[DIV4_S4]),
+ CLKDEV_CON_ID("shyway3_clk", &div4_clks[DIV4_S3]),
+ CLKDEV_CON_ID("shyway1_clk", &div4_clks[DIV4_S1]),
+ CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+
+ /* MSTP32 clocks */
+ CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
+ CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
+ CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
+ CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
+ CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
+ CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
+ CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
+ CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+};
+
+void __init r8a7779_clock_init(void)
+{
+ int k, ret = 0;
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+ ret = clk_register(main_clks[k]);
+
+ if (!ret)
+ ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+ if (!ret)
+ ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
+
+ for (k = 0; !ret && (k < ARRAY_SIZE(late_main_clks)); k++)
+ ret = clk_register(late_main_clks[k]);
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ if (!ret)
+ clk_init();
+ else
+ panic("failed to setup r8a7779 clocks\n");
+}
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 995a9c3aec8f..293456d8dcfd 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -411,11 +411,11 @@ static struct clk *fsibckcr_parent[] = {
};
static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
- [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
+ [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
- [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
+ [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
- [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
+ [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
};
@@ -612,8 +612,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
- CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
- CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+ CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+ CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 1370a89ca358..afbead6a6e17 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -92,6 +92,24 @@ static struct clk_ops div2_clk_ops = {
.recalc = div2_recalc,
};
+static unsigned long div7_recalc(struct clk *clk)
+{
+ return clk->parent->rate / 7;
+}
+
+static struct clk_ops div7_clk_ops = {
+ .recalc = div7_recalc,
+};
+
+static unsigned long div13_recalc(struct clk *clk)
+{
+ return clk->parent->rate / 13;
+}
+
+static struct clk_ops div13_clk_ops = {
+ .recalc = div13_recalc,
+};
+
/* Divide extal1 by two */
static struct clk extal1_div2_clk = {
.ops = &div2_clk_ops,
@@ -174,12 +192,29 @@ static struct clk pll3_clk = {
.enable_bit = 3,
};
-/* Divide PLL1 by two */
+/* Divide PLL */
static struct clk pll1_div2_clk = {
.ops = &div2_clk_ops,
.parent = &pll1_clk,
};
+static struct clk pll1_div7_clk = {
+ .ops = &div7_clk_ops,
+ .parent = &pll1_clk,
+};
+
+static struct clk pll1_div13_clk = {
+ .ops = &div13_clk_ops,
+ .parent = &pll1_clk,
+};
+
+/* External input clock */
+struct clk sh73a0_extcki_clk = {
+};
+
+struct clk sh73a0_extalr_clk = {
+};
+
static struct clk *main_clks[] = {
&r_clk,
&sh73a0_extal1_clk,
@@ -193,6 +228,10 @@ static struct clk *main_clks[] = {
&pll2_clk,
&pll3_clk,
&pll1_div2_clk,
+ &pll1_div7_clk,
+ &pll1_div13_clk,
+ &sh73a0_extcki_clk,
+ &sh73a0_extalr_clk,
};
static void div4_kick(struct clk *clk)
@@ -246,27 +285,84 @@ enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_ZB1,
DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
DIV6_NR };
+static struct clk *vck_parent[8] = {
+ [0] = &pll1_div2_clk,
+ [1] = &pll2_clk,
+ [2] = &sh73a0_extcki_clk,
+ [3] = &sh73a0_extal2_clk,
+ [4] = &main_div2_clk,
+ [5] = &sh73a0_extalr_clk,
+ [6] = &main_clk,
+};
+
+static struct clk *pll_parent[4] = {
+ [0] = &pll1_div2_clk,
+ [1] = &pll2_clk,
+ [2] = &pll1_div13_clk,
+};
+
+static struct clk *hsi_parent[4] = {
+ [0] = &pll1_div2_clk,
+ [1] = &pll2_clk,
+ [2] = &pll1_div7_clk,
+};
+
+static struct clk *pll_extal2_parent[] = {
+ [0] = &pll1_div2_clk,
+ [1] = &pll2_clk,
+ [2] = &sh73a0_extal2_clk,
+ [3] = &sh73a0_extal2_clk,
+};
+
+static struct clk *dsi_parent[8] = {
+ [0] = &pll1_div2_clk,
+ [1] = &pll2_clk,
+ [2] = &main_clk,
+ [3] = &sh73a0_extal2_clk,
+ [4] = &sh73a0_extcki_clk,
+};
+
static struct clk div6_clks[DIV6_NR] = {
- [DIV6_VCK1] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR1, 0),
- [DIV6_VCK2] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR2, 0),
- [DIV6_VCK3] = SH_CLK_DIV6(&pll1_div2_clk, VCLKCR3, 0),
- [DIV6_ZB1] = SH_CLK_DIV6(&pll1_div2_clk, ZBCKCR, CLK_ENABLE_ON_INIT),
- [DIV6_FLCTL] = SH_CLK_DIV6(&pll1_div2_clk, FLCKCR, 0),
- [DIV6_SDHI0] = SH_CLK_DIV6(&pll1_div2_clk, SD0CKCR, 0),
- [DIV6_SDHI1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
- [DIV6_SDHI2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
- [DIV6_FSIA] = SH_CLK_DIV6(&pll1_div2_clk, FSIACKCR, 0),
- [DIV6_FSIB] = SH_CLK_DIV6(&pll1_div2_clk, FSIBCKCR, 0),
- [DIV6_SUB] = SH_CLK_DIV6(&sh73a0_extal2_clk, SUBCKCR, 0),
- [DIV6_SPUA] = SH_CLK_DIV6(&pll1_div2_clk, SPUACKCR, 0),
- [DIV6_SPUV] = SH_CLK_DIV6(&pll1_div2_clk, SPUVCKCR, 0),
- [DIV6_MSU] = SH_CLK_DIV6(&pll1_div2_clk, MSUCKCR, 0),
- [DIV6_HSI] = SH_CLK_DIV6(&pll1_div2_clk, HSICKCR, 0),
- [DIV6_MFG1] = SH_CLK_DIV6(&pll1_div2_clk, MFCK1CR, 0),
- [DIV6_MFG2] = SH_CLK_DIV6(&pll1_div2_clk, MFCK2CR, 0),
- [DIV6_DSIT] = SH_CLK_DIV6(&pll1_div2_clk, DSITCKCR, 0),
- [DIV6_DSI0P] = SH_CLK_DIV6(&pll1_div2_clk, DSI0PCKCR, 0),
- [DIV6_DSI1P] = SH_CLK_DIV6(&pll1_div2_clk, DSI1PCKCR, 0),
+ [DIV6_VCK1] = SH_CLK_DIV6_EXT(VCLKCR1, 0,
+ vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
+ [DIV6_VCK2] = SH_CLK_DIV6_EXT(VCLKCR2, 0,
+ vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
+ [DIV6_VCK3] = SH_CLK_DIV6_EXT(VCLKCR3, 0,
+ vck_parent, ARRAY_SIZE(vck_parent), 12, 3),
+ [DIV6_ZB1] = SH_CLK_DIV6_EXT(ZBCKCR, CLK_ENABLE_ON_INIT,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_FLCTL] = SH_CLK_DIV6_EXT(FLCKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_SDHI0] = SH_CLK_DIV6_EXT(SD0CKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
+ [DIV6_SDHI1] = SH_CLK_DIV6_EXT(SD1CKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
+ [DIV6_SDHI2] = SH_CLK_DIV6_EXT(SD2CKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 6, 2),
+ [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
+ [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 6, 1),
+ [DIV6_SUB] = SH_CLK_DIV6_EXT(SUBCKCR, 0,
+ pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+ [DIV6_SPUA] = SH_CLK_DIV6_EXT(SPUACKCR, 0,
+ pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+ [DIV6_SPUV] = SH_CLK_DIV6_EXT(SPUVCKCR, 0,
+ pll_extal2_parent, ARRAY_SIZE(pll_extal2_parent), 6, 2),
+ [DIV6_MSU] = SH_CLK_DIV6_EXT(MSUCKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_HSI] = SH_CLK_DIV6_EXT(HSICKCR, 0,
+ hsi_parent, ARRAY_SIZE(hsi_parent), 6, 2),
+ [DIV6_MFG1] = SH_CLK_DIV6_EXT(MFCK1CR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_MFG2] = SH_CLK_DIV6_EXT(MFCK2CR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_DSIT] = SH_CLK_DIV6_EXT(DSITCKCR, 0,
+ pll_parent, ARRAY_SIZE(pll_parent), 7, 1),
+ [DIV6_DSI0P] = SH_CLK_DIV6_EXT(DSI0PCKCR, 0,
+ dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
+ [DIV6_DSI1P] = SH_CLK_DIV6_EXT(DSI1PCKCR, 0,
+ dsi_parent, ARRAY_SIZE(dsi_parent), 12, 3),
};
enum { MSTP001,
@@ -331,8 +427,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
- CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
- CLKDEV_ICK_ID("dsi1p_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
+ CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
+ CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */
@@ -403,7 +499,7 @@ void __init sh73a0_clock_init(void)
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
if (!ret)
- ret = sh_clk_div6_register(div6_clks, DIV6_NR);
+ ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR);
if (!ret)
ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 26079d933d91..6ac015c89206 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -14,7 +14,7 @@
#include <linux/init.h>
#include <asm/memory.h>
- __INIT
+ __CPUINIT
/*
* Reset vector for secondary CPUs.
diff --git a/arch/arm/mach-shmobile/hotplug.c b/arch/arm/mach-shmobile/hotplug.c
index 238a0d97d2d5..828d22f3af57 100644
--- a/arch/arm/mach-shmobile/hotplug.c
+++ b/arch/arm/mach-shmobile/hotplug.c
@@ -12,14 +12,43 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <mach/common.h>
+#include <asm/cacheflush.h>
+
+static cpumask_t dead_cpus;
int platform_cpu_kill(unsigned int cpu)
{
- return 1;
+ int k;
+
+ /* this function is running on another CPU than the offline target,
+ * here we need wait for shutdown code in platform_cpu_die() to
+ * finish before asking SoC-specific code to power off the CPU core.
+ */
+ for (k = 0; k < 1000; k++) {
+ if (cpumask_test_cpu(cpu, &dead_cpus))
+ return shmobile_platform_cpu_kill(cpu);
+
+ mdelay(1);
+ }
+
+ return 0;
}
void platform_cpu_die(unsigned int cpu)
{
+ /* hardware shutdown code running on the CPU that is being offlined */
+ flush_cache_all();
+ dsb();
+
+ /* notify platform_cpu_kill() that hardware shutdown is finished */
+ cpumask_set_cpu(cpu, &dead_cpus);
+
+ /* wait for SoC code in platform_cpu_kill() to shut off CPU core
+ * power. CPU bring up starts from the reset vector.
+ */
while (1) {
/*
* here's the WFI
@@ -33,6 +62,7 @@ void platform_cpu_die(unsigned int cpu)
int platform_cpu_disable(unsigned int cpu)
{
+ cpumask_clear_cpu(cpu, &dead_cpus);
/*
* we don't allow CPU 0 to be shutdown (it is still too special
* e.g. clock tick interrupts)
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index be78a2c73db4..e4b945e271e7 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,6 +4,7 @@
extern struct sys_timer shmobile_timer;
extern void shmobile_setup_console(void);
extern void shmobile_secondary_vector(void);
+extern int shmobile_platform_cpu_kill(unsigned int cpu);
struct clk;
extern int clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
@@ -46,10 +47,31 @@ extern void sh73a0_clock_init(void);
extern void sh73a0_pinmux_init(void);
extern struct clk sh73a0_extal1_clk;
extern struct clk sh73a0_extal2_clk;
+extern struct clk sh73a0_extcki_clk;
+extern struct clk sh73a0_extalr_clk;
extern unsigned int sh73a0_get_core_count(void);
extern void sh73a0_secondary_init(unsigned int cpu);
extern int sh73a0_boot_secondary(unsigned int cpu);
extern void sh73a0_smp_prepare_cpus(void);
+extern void r8a7740_init_irq(void);
+extern void r8a7740_add_early_devices(void);
+extern void r8a7740_add_standard_devices(void);
+extern void r8a7740_clock_init(u8 md_ck);
+extern void r8a7740_pinmux_init(void);
+
+extern void r8a7779_init_irq(void);
+extern void r8a7779_add_early_devices(void);
+extern void r8a7779_add_standard_devices(void);
+extern void r8a7779_clock_init(void);
+extern void r8a7779_pinmux_init(void);
+extern void r8a7779_pm_init(void);
+
+extern unsigned int r8a7779_get_core_count(void);
+extern int r8a7779_platform_cpu_kill(unsigned int cpu);
+extern void r8a7779_secondary_init(unsigned int cpu);
+extern int r8a7779_boot_secondary(unsigned int cpu);
+extern void r8a7779_smp_prepare_cpus(void);
+
#endif /* __ARCH_MACH_COMMON_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
new file mode 100644
index 000000000000..9d447abb969c
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -0,0 +1,584 @@
+/*
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ASM_R8A7740_H__
+#define __ASM_R8A7740_H__
+
+/*
+ * MD_CKx pin
+ */
+#define MD_CK2 (1 << 2)
+#define MD_CK1 (1 << 1)
+#define MD_CK0 (1 << 0)
+
+/*
+ * Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ /* PORT */
+ GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
+ GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
+
+ GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
+ GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
+
+ GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
+ GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
+
+ GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
+ GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
+
+ GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
+ GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
+
+ GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
+ GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
+
+ GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
+ GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
+
+ GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
+ GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
+
+ GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
+ GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
+
+ GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
+ GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
+
+ GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
+ GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
+
+ GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
+ GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119,
+
+ GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124,
+ GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129,
+
+ GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
+ GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
+
+ GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
+ GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
+
+ GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
+ GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
+
+ GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
+ GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169,
+
+ GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174,
+ GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179,
+
+ GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184,
+ GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189,
+
+ GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
+ GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
+
+ GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
+ GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
+
+ GPIO_PORT210, GPIO_PORT211,
+
+ /* IRQ */
+ GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13,
+ GPIO_FN_IRQ1,
+ GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12,
+ GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14,
+ GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172,
+ GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1,
+ GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173,
+ GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209,
+ GPIO_FN_IRQ8,
+ GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210,
+ GPIO_FN_IRQ10,
+ GPIO_FN_IRQ11,
+ GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97,
+ GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98,
+ GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99,
+ GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100,
+ GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211,
+ GPIO_FN_IRQ17,
+ GPIO_FN_IRQ18,
+ GPIO_FN_IRQ19,
+ GPIO_FN_IRQ20,
+ GPIO_FN_IRQ21,
+ GPIO_FN_IRQ22,
+ GPIO_FN_IRQ23,
+ GPIO_FN_IRQ24,
+ GPIO_FN_IRQ25,
+ GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81,
+ GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168,
+ GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169,
+ GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170,
+ GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171,
+ GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167,
+
+ /* Function */
+
+ /* DBGT */
+ GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0,
+ GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20,
+ GPIO_FN_DBGMD21,
+
+ /* FSI */
+ GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */
+ GPIO_FN_FSIAISLD_PORT5,
+ GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */
+ GPIO_FN_FSIASPDIF_PORT18,
+ GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2,
+ GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT,
+ GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC,
+ GPIO_FN_FSIACK, GPIO_FN_FSIAILR,
+ GPIO_FN_FSIAIBT,
+
+ /* FMSI */
+ GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */
+ GPIO_FN_FMSISLD_PORT6,
+ GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT,
+ GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT,
+ GPIO_FN_FMSICK, GPIO_FN_FMSOILR,
+ GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR,
+ GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD,
+ GPIO_FN_FMSOCK,
+
+ /* SCIFA0 */
+ GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS,
+ GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD,
+ GPIO_FN_SCIFA0_TXD,
+
+ /* SCIFA1 */
+ GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK,
+ GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD,
+ GPIO_FN_SCIFA1_RTS,
+
+ /* SCIFA2 */
+ GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */
+ GPIO_FN_SCIFA2_SCK_PORT199,
+ GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD,
+ GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS,
+
+ /* SCIFA3 */
+ GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */
+ GPIO_FN_SCIFA3_SCK_PORT116,
+ GPIO_FN_SCIFA3_CTS_PORT117,
+ GPIO_FN_SCIFA3_RXD_PORT174,
+ GPIO_FN_SCIFA3_TXD_PORT175,
+
+ GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */
+ GPIO_FN_SCIFA3_SCK_PORT158,
+ GPIO_FN_SCIFA3_CTS_PORT162,
+ GPIO_FN_SCIFA3_RXD_PORT159,
+ GPIO_FN_SCIFA3_TXD_PORT160,
+
+ /* SCIFA4 */
+ GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */
+ GPIO_FN_SCIFA4_TXD_PORT13,
+
+ GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */
+ GPIO_FN_SCIFA4_TXD_PORT203,
+
+ GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */
+ GPIO_FN_SCIFA4_TXD_PORT93,
+
+ GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */
+ GPIO_FN_SCIFA4_SCK_PORT205,
+
+ /* SCIFA5 */
+ GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */
+ GPIO_FN_SCIFA5_RXD_PORT10,
+
+ GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */
+ GPIO_FN_SCIFA5_TXD_PORT208,
+
+ GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */
+ GPIO_FN_SCIFA5_RXD_PORT92,
+
+ GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */
+ GPIO_FN_SCIFA5_SCK_PORT206,
+
+ /* SCIFA6 */
+ GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD,
+
+ /* SCIFA7 */
+ GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD,
+
+ /* SCIFAB */
+ GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */
+ GPIO_FN_SCIFB_RXD_PORT191,
+ GPIO_FN_SCIFB_TXD_PORT192,
+ GPIO_FN_SCIFB_RTS_PORT186,
+ GPIO_FN_SCIFB_CTS_PORT187,
+
+ GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */
+ GPIO_FN_SCIFB_RXD_PORT3,
+ GPIO_FN_SCIFB_TXD_PORT4,
+ GPIO_FN_SCIFB_RTS_PORT172,
+ GPIO_FN_SCIFB_CTS_PORT173,
+
+ /* LCD0 */
+ GPIO_FN_LCDC0_SELECT,
+ GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
+ GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
+ GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
+ GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
+ GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
+ GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
+ GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
+
+ GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
+ GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
+
+ GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
+ GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
+
+ GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
+ GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
+ GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
+ GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
+
+ GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
+ GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
+ GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
+ GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
+
+ /* LCD1 */
+ GPIO_FN_LCDC1_SELECT,
+ GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
+ GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
+ GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
+ GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
+ GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
+ GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
+ GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
+ GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
+ GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
+ GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
+
+ GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
+ GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
+
+ GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
+ GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
+
+ /* RSPI */
+ GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
+ GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A,
+ GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A,
+ GPIO_FN_RSPI_CK_A,
+
+ /* VIO CKO */
+ GPIO_FN_VIO_CKO1,
+ GPIO_FN_VIO_CKO2,
+ GPIO_FN_VIO_CKO_1,
+ GPIO_FN_VIO_CKO,
+
+ /* VIO0 */
+ GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2,
+ GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5,
+ GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8,
+ GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11,
+ GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD,
+ GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD,
+
+ GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */
+ GPIO_FN_VIO0_D14_PORT25,
+ GPIO_FN_VIO0_D15_PORT24,
+
+ GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */
+ GPIO_FN_VIO0_D14_PORT95,
+ GPIO_FN_VIO0_D15_PORT96,
+
+ /* VIO1 */
+ GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2,
+ GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5,
+ GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD,
+ GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD,
+
+ /* TPU0 */
+ GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1,
+ GPIO_FN_TPU0TO3,
+ GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */
+ GPIO_FN_TPU0TO2_PORT202,
+
+ /* SSP1 0 */
+ GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2,
+ GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5,
+ GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN,
+ GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC,
+
+ /* SSP1 1 */
+ GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3,
+ GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6,
+ GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC,
+
+ GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */
+ GPIO_FN_STP1_IPEN_PORT187,
+
+ GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */
+ GPIO_FN_STP1_IPEN_PORT193,
+
+ /* SIM */
+ GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK,
+ GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
+ GPIO_FN_SIM_D_PORT199,
+
+ /* SDHI0 */
+ GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
+ GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
+ GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
+
+ /* SDHI1 */
+ GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
+ GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
+ GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
+
+ /* SDHI2 */
+ GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
+ GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
+
+ GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
+ GPIO_FN_SDHI2_WP_PORT25,
+
+ GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
+ GPIO_FN_SDHI2_CD_PORT202,
+
+ /* MSIOF2 */
+ GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
+ GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
+ GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC,
+ GPIO_FN_MSIOF2_RSCK,
+
+ /* KEYSC */
+ GPIO_FN_KEYIN4, GPIO_FN_KEYIN5,
+ GPIO_FN_KEYIN6, GPIO_FN_KEYIN7,
+ GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2,
+ GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5,
+ GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7,
+
+ GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */
+ GPIO_FN_KEYIN1_PORT44,
+ GPIO_FN_KEYIN2_PORT45,
+ GPIO_FN_KEYIN3_PORT46,
+
+ GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */
+ GPIO_FN_KEYIN1_PORT57,
+ GPIO_FN_KEYIN2_PORT56,
+ GPIO_FN_KEYIN3_PORT55,
+
+ /* VOU */
+ GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3,
+ GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7,
+ GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11,
+ GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15,
+ GPIO_FN_DV_CLK,
+ GPIO_FN_DV_VSYNC,
+ GPIO_FN_DV_HSYNC,
+
+ /* MEMC */
+ GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2,
+ GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5,
+ GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8,
+ GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11,
+ GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14,
+ GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT,
+ GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE,
+
+ GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */
+ GPIO_FN_MEMC_ADV,
+ GPIO_FN_MEMC_WAIT,
+ GPIO_FN_MEMC_BUSCLK,
+
+ GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */
+ GPIO_FN_MEMC_DREQ0,
+ GPIO_FN_MEMC_DREQ1,
+ GPIO_FN_MEMC_A0,
+
+ /* MMC */
+ GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
+ GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
+ GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
+ GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
+ GPIO_FN_MMC0_CLK_PORT66,
+ GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
+
+ GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
+ GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
+ GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
+ GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
+ GPIO_FN_MMC1_CLK_PORT103,
+ GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC,
+
+ /* MSIOF1 */
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC,
+ GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1,
+
+ GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117,
+ GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119,
+ GPIO_FN_MSIOF1_TSYNC_PORT120,
+ GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */
+
+ GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72,
+ GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74,
+ GPIO_FN_MSIOF1_RXD_PORT75,
+ GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPIO_FN_GPO0, GPIO_FN_GPI0,
+ GPIO_FN_GPO1, GPIO_FN_GPI1,
+
+ /* USB0 */
+ GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS,
+
+ /* USB1 */
+ GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON,
+
+ /* BBIF1 */
+ GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC,
+ GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC,
+ GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N,
+
+ /* BBIF2 */
+ GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */
+ GPIO_FN_BBIF2_RXD2_PORT60,
+ GPIO_FN_BBIF2_TSYNC2_PORT6,
+ GPIO_FN_BBIF2_TSCK2_PORT59,
+
+ GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */
+ GPIO_FN_BBIF2_TXD2_PORT183,
+ GPIO_FN_BBIF2_TSCK2_PORT89,
+ GPIO_FN_BBIF2_TSYNC2_PORT184,
+
+ /* BSC / FLCTL / PCMCIA */
+ GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4,
+ GPIO_FN_CS5B, GPIO_FN_CS6A,
+ GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */
+ GPIO_FN_CS5A_PORT19,
+ GPIO_FN_IOIS16, /* ? */
+
+ GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3,
+ GPIO_FN_A4_FOE, /* share with FLCTL */
+ GPIO_FN_A5_FCDE, /* share with FLCTL */
+ GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9,
+ GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13,
+ GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17,
+ GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21,
+ GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25,
+ GPIO_FN_A26,
+
+ GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */
+ GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */
+ GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */
+ GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */
+ GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */
+ GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */
+ GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */
+ GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */
+
+ GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19,
+ GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23,
+ GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27,
+ GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31,
+
+ GPIO_FN_WE0_FWE, /* share with FLCTL */
+ GPIO_FN_WE1,
+ GPIO_FN_WE2_ICIORD, /* share with PCMCIA */
+ GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */
+ GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR,
+ GPIO_FN_RD_FSC, /* share with FLCTL */
+ GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */
+ GPIO_FN_WAIT_PORT90,
+
+ GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */
+
+ /* IRDA */
+ GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT,
+
+ /* ATAPI */
+ GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2,
+ GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5,
+ GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8,
+ GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11,
+ GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14,
+ GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1,
+ GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1,
+ GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY,
+ GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION,
+ GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ,
+
+ /* RMII */
+ GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0,
+ GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0,
+ GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO,
+ GPIO_FN_RMII_REF50CK, /* for RMII */
+ GPIO_FN_RMII_REF125CK, /* for GMII */
+
+ /* GEther */
+ GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0,
+ GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3,
+ GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */
+ GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */
+ GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER,
+ GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV,
+ GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1,
+ GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3,
+ GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */
+ GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */
+ GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS,
+ GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO,
+ GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT,
+ GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK,
+
+ /* DMA0 */
+ GPIO_FN_DREQ0, GPIO_FN_DACK0,
+
+ /* DMA1 */
+ GPIO_FN_DREQ1, GPIO_FN_DACK1,
+
+ /* SYSC */
+ GPIO_FN_RESETOUTS,
+ GPIO_FN_RESETP_PULLUP,
+ GPIO_FN_RESETP_PLAIN,
+
+ /* SDENC */
+ GPIO_FN_SDENC_CPG,
+ GPIO_FN_SDENC_DV_CLKI,
+
+ /* IRREM */
+ GPIO_FN_IROUT,
+
+ /* DEBUG */
+ GPIO_FN_EDEBGREQ_PULLDOWN,
+ GPIO_FN_EDEBGREQ_PULLUP,
+
+ GPIO_FN_TRACEAUD_FROM_VIO,
+ GPIO_FN_TRACEAUD_FROM_LCDC0,
+ GPIO_FN_TRACEAUD_FROM_MEMC,
+};
+
+#endif /* __ASM_R8A7740_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
new file mode 100644
index 000000000000..b07ad318eb2e
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -0,0 +1,363 @@
+#ifndef __ASM_R8A7779_H__
+#define __ASM_R8A7779_H__
+
+#include <linux/sh_clk.h>
+#include <linux/pm_domain.h>
+
+/* Pin Function Controller:
+ * GPIO_FN_xx - GPIO used to select pin function
+ * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
+ */
+enum {
+ GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
+ GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
+ GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
+ GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
+ GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
+ GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
+ GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
+ GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
+
+ GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
+ GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
+ GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
+ GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
+ GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
+ GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
+ GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
+ GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
+
+ GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
+ GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
+ GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
+ GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
+ GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
+ GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
+ GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
+ GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
+
+ GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
+ GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
+ GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
+ GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
+ GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
+ GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
+ GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
+ GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
+
+ GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
+ GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
+ GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
+ GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
+ GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
+ GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
+ GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
+ GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
+
+ GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
+ GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
+ GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
+ GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
+ GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
+ GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
+ GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
+ GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
+
+ GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
+ GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
+ GPIO_GP_6_8,
+
+ GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
+ GPIO_FN_A19,
+
+ /* IPSR0 */
+ GPIO_FN_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
+ GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
+ GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
+ GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
+ GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
+ GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
+ GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
+ GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
+ GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
+ GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
+ GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
+ GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
+ GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
+ GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
+ GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
+ GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
+
+ /* IPSR1 */
+ GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
+ GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
+ GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
+ GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
+ GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
+ GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
+ GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
+ GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
+ GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
+ GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
+ GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
+ GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
+ GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
+ GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
+ GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
+ GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
+ GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
+
+ /* IPSR2 */
+ GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
+ GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
+ GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
+ GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
+ GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
+ GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
+ GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
+ GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
+ GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
+ GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
+ GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
+ GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
+ GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
+ GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
+ GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
+ GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
+ GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
+ GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
+ GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
+ GPIO_FN_AUDATA2,
+
+ /* IPSR3 */
+ GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
+ GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
+ GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
+ GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
+ GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
+ GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
+ GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
+ GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
+ GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
+ GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
+ GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
+ GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
+ GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
+ GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
+ GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
+ GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
+ GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
+ GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
+ GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
+
+ /* IPSR4 */
+ GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
+ GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
+ GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
+ GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
+ GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
+ GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
+ GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
+ GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
+ GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
+ GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
+ GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
+ GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
+ GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
+ GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
+ GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
+ GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
+ GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
+ GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
+ GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
+
+ /* IPSR5 */
+ GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
+ GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
+ GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
+ GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
+ GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
+ GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
+ GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
+ GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
+ GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
+ GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+ GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
+ GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
+ GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
+ GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
+ GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
+ GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
+ GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
+ GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
+ GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
+ GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
+ GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
+ GPIO_FN_MOUT0,
+
+ /* IPSR6 */
+ GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
+ GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
+ GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
+ GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
+ GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
+ GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
+ GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
+ GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
+ GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
+ GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
+ GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
+ GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
+ GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
+ GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
+ GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
+ GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
+
+ /* IPSR7 */
+ GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
+ GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
+ GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
+ GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
+ GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
+ GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
+ GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
+ GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
+ GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
+ GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
+ GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
+ GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
+ GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
+ GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
+ GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
+ GPIO_FN_CTS1_B,
+
+ /* IPSR8 */
+ GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
+ GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
+ GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
+ GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
+ GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
+ GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
+ GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
+ GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
+ GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
+ GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
+ GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
+ GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
+ GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
+ GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
+ GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
+ GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
+ GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
+ GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
+ GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
+
+ /* IPSR9 */
+ GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
+ GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
+ GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
+ GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
+ GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
+ GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
+ GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
+ GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
+ GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
+ GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
+ GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
+ GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
+ GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
+ GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
+ GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
+ GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
+ GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
+ GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
+
+ /* IPSR10 */
+ GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
+ GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
+ GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
+ GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
+ GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
+ GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
+ GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
+ GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
+ GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
+ GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
+ GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
+ GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
+ GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
+ GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
+ GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
+ GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
+ GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
+ GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
+ GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
+
+ /* IPSR11 */
+ GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
+ GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
+ GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
+ GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
+ GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
+ GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
+ GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
+ GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
+ GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
+ GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
+ GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
+ GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
+ GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
+ GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
+ GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
+ GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
+ GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
+ GPIO_FN_HRTS0_B,
+
+ /* IPSR12 */
+ GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
+ GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
+ GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
+ GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
+ GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
+ GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
+ GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
+ GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
+ GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
+};
+
+struct platform_device;
+
+struct r8a7779_pm_ch {
+ unsigned long chan_offs;
+ unsigned int chan_bit;
+ unsigned int isr_bit;
+};
+
+struct r8a7779_pm_domain {
+ struct generic_pm_domain genpd;
+ struct r8a7779_pm_ch ch;
+};
+
+static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
+{
+ return &container_of(d, struct r8a7779_pm_domain, genpd)->ch;
+}
+
+extern int r8a7779_sysc_power_down(struct r8a7779_pm_ch *r8a7779_ch);
+extern int r8a7779_sysc_power_up(struct r8a7779_pm_ch *r8a7779_ch);
+
+#ifdef CONFIG_PM
+extern struct r8a7779_pm_domain r8a7779_sh4a;
+extern struct r8a7779_pm_domain r8a7779_sgx;
+extern struct r8a7779_pm_domain r8a7779_vdp1;
+extern struct r8a7779_pm_domain r8a7779_impx3;
+
+extern void r8a7779_init_pm_domain(struct r8a7779_pm_domain *r8a7779_pd);
+extern void r8a7779_add_device_to_domain(struct r8a7779_pm_domain *r8a7779_pd,
+ struct platform_device *pdev);
+#else
+#define r8a7779_init_pm_domain(pd) do { } while (0)
+#define r8a7779_add_device_to_domain(pd, pdev) do { } while (0)
+#endif /* CONFIG_PM */
+
+#endif /* __ASM_R8A7779_H__ */
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
new file mode 100644
index 000000000000..272c84c20c83
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -0,0 +1,631 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/sh_intc.h>
+#include <mach/intc.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/*
+ * INTCA
+ */
+enum {
+ UNUSED_INTCA = 0,
+
+ /* interrupt sources INTCA */
+ DIRC,
+ ATAPI,
+ IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
+ AP_ARM_COMMTX, AP_ARM_COMMRX,
+ MFI, MFIS,
+ BBIF1, BBIF2,
+ USBHSDMAC,
+ USBF_OUL_SOF, USBF_IXL_INT,
+ SGX540,
+ CMT1_0, CMT1_1, CMT1_2, CMT1_3,
+ CMT2,
+ CMT3,
+ KEYSC,
+ SCIFA0, SCIFA1, SCIFA2, SCIFA3,
+ MSIOF2, MSIOF1,
+ SCIFA4, SCIFA5, SCIFB,
+ FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
+ SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
+ SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
+ AP_ARM_L2CINT,
+ IRDA,
+ TPU0,
+ SCIFA6, SCIFA7,
+ GbEther,
+ ICBS0,
+ DDM,
+ SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
+ RWDT0,
+ DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
+ DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
+ DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
+ DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
+ DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
+ DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
+ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
+ USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
+ RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
+ SPU2_0, SPU2_1,
+ FSI, FMSI,
+ IPMMU,
+ AP_ARM_CTIIRQ, AP_ARM_PMURQ,
+ MFIS2,
+ CPORTR2S,
+ CMT14, CMT15,
+ MMCIF_0, MMCIF_1, MMCIF_2,
+ SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
+ STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
+
+ /* interrupt groups INTCA */
+ DMAC1_1, DMAC1_2,
+ DMAC2_1, DMAC2_2,
+ DMAC3_1, DMAC3_2,
+ AP_ARM1, AP_ARM2,
+ SDHI0, SDHI1, SDHI2,
+ SHWYSTAT,
+ USBF, USBH1, USBH2,
+ RSPI, SPU2, FLCTL, IIC1,
+};
+
+static struct intc_vect intca_vectors[] __initdata = {
+ INTC_VECT(DIRC, 0x0560),
+ INTC_VECT(ATAPI, 0x05E0),
+ INTC_VECT(IIC1_ALI, 0x0780),
+ INTC_VECT(IIC1_TACKI, 0x07A0),
+ INTC_VECT(IIC1_WAITI, 0x07C0),
+ INTC_VECT(IIC1_DTEI, 0x07E0),
+ INTC_VECT(AP_ARM_COMMTX, 0x0840),
+ INTC_VECT(AP_ARM_COMMRX, 0x0860),
+ INTC_VECT(MFI, 0x0900),
+ INTC_VECT(MFIS, 0x0920),
+ INTC_VECT(BBIF1, 0x0940),
+ INTC_VECT(BBIF2, 0x0960),
+ INTC_VECT(USBHSDMAC, 0x0A00),
+ INTC_VECT(USBF_OUL_SOF, 0x0A20),
+ INTC_VECT(USBF_IXL_INT, 0x0A40),
+ INTC_VECT(SGX540, 0x0A60),
+ INTC_VECT(CMT1_0, 0x0B00),
+ INTC_VECT(CMT1_1, 0x0B20),
+ INTC_VECT(CMT1_2, 0x0B40),
+ INTC_VECT(CMT1_3, 0x0B60),
+ INTC_VECT(CMT2, 0x0B80),
+ INTC_VECT(CMT3, 0x0BA0),
+ INTC_VECT(KEYSC, 0x0BE0),
+ INTC_VECT(SCIFA0, 0x0C00),
+ INTC_VECT(SCIFA1, 0x0C20),
+ INTC_VECT(SCIFA2, 0x0C40),
+ INTC_VECT(SCIFA3, 0x0C60),
+ INTC_VECT(MSIOF2, 0x0C80),
+ INTC_VECT(MSIOF1, 0x0D00),
+ INTC_VECT(SCIFA4, 0x0D20),
+ INTC_VECT(SCIFA5, 0x0D40),
+ INTC_VECT(SCIFB, 0x0D60),
+ INTC_VECT(FLCTL_FLSTEI, 0x0D80),
+ INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
+ INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
+ INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
+ INTC_VECT(SDHI0_0, 0x0E00),
+ INTC_VECT(SDHI0_1, 0x0E20),
+ INTC_VECT(SDHI0_2, 0x0E40),
+ INTC_VECT(SDHI0_3, 0x0E60),
+ INTC_VECT(SDHI1_0, 0x0E80),
+ INTC_VECT(SDHI1_1, 0x0EA0),
+ INTC_VECT(SDHI1_2, 0x0EC0),
+ INTC_VECT(SDHI1_3, 0x0EE0),
+ INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
+ INTC_VECT(IRDA, 0x0480),
+ INTC_VECT(TPU0, 0x04A0),
+ INTC_VECT(SCIFA6, 0x04C0),
+ INTC_VECT(SCIFA7, 0x04E0),
+ INTC_VECT(GbEther, 0x0500),
+ INTC_VECT(ICBS0, 0x0540),
+ INTC_VECT(DDM, 0x1140),
+ INTC_VECT(SDHI2_0, 0x1200),
+ INTC_VECT(SDHI2_1, 0x1220),
+ INTC_VECT(SDHI2_2, 0x1240),
+ INTC_VECT(SDHI2_3, 0x1260),
+ INTC_VECT(RWDT0, 0x1280),
+ INTC_VECT(DMAC1_1_DEI0, 0x2000),
+ INTC_VECT(DMAC1_1_DEI1, 0x2020),
+ INTC_VECT(DMAC1_1_DEI2, 0x2040),
+ INTC_VECT(DMAC1_1_DEI3, 0x2060),
+ INTC_VECT(DMAC1_2_DEI4, 0x2080),
+ INTC_VECT(DMAC1_2_DEI5, 0x20A0),
+ INTC_VECT(DMAC1_2_DADERR, 0x20C0),
+ INTC_VECT(DMAC2_1_DEI0, 0x2100),
+ INTC_VECT(DMAC2_1_DEI1, 0x2120),
+ INTC_VECT(DMAC2_1_DEI2, 0x2140),
+ INTC_VECT(DMAC2_1_DEI3, 0x2160),
+ INTC_VECT(DMAC2_2_DEI4, 0x2180),
+ INTC_VECT(DMAC2_2_DEI5, 0x21A0),
+ INTC_VECT(DMAC2_2_DADERR, 0x21C0),
+ INTC_VECT(DMAC3_1_DEI0, 0x2200),
+ INTC_VECT(DMAC3_1_DEI1, 0x2220),
+ INTC_VECT(DMAC3_1_DEI2, 0x2240),
+ INTC_VECT(DMAC3_1_DEI3, 0x2260),
+ INTC_VECT(DMAC3_2_DEI4, 0x2280),
+ INTC_VECT(DMAC3_2_DEI5, 0x22A0),
+ INTC_VECT(DMAC3_2_DADERR, 0x22C0),
+ INTC_VECT(SHWYSTAT_RT, 0x1300),
+ INTC_VECT(SHWYSTAT_HS, 0x1320),
+ INTC_VECT(SHWYSTAT_COM, 0x1340),
+ INTC_VECT(USBH_INT, 0x1540),
+ INTC_VECT(USBH_OHCI, 0x1560),
+ INTC_VECT(USBH_EHCI, 0x1580),
+ INTC_VECT(USBH_PME, 0x15A0),
+ INTC_VECT(USBH_BIND, 0x15C0),
+ INTC_VECT(RSPI_OVRF, 0x1780),
+ INTC_VECT(RSPI_SPTEF, 0x17A0),
+ INTC_VECT(RSPI_SPRF, 0x17C0),
+ INTC_VECT(SPU2_0, 0x1800),
+ INTC_VECT(SPU2_1, 0x1820),
+ INTC_VECT(FSI, 0x1840),
+ INTC_VECT(FMSI, 0x1860),
+ INTC_VECT(IPMMU, 0x1920),
+ INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
+ INTC_VECT(AP_ARM_PMURQ, 0x19A0),
+ INTC_VECT(MFIS2, 0x1A00),
+ INTC_VECT(CPORTR2S, 0x1A20),
+ INTC_VECT(CMT14, 0x1A40),
+ INTC_VECT(CMT15, 0x1A60),
+ INTC_VECT(MMCIF_0, 0x1AA0),
+ INTC_VECT(MMCIF_1, 0x1AC0),
+ INTC_VECT(MMCIF_2, 0x1AE0),
+ INTC_VECT(SIM_ERI, 0x1C00),
+ INTC_VECT(SIM_RXI, 0x1C20),
+ INTC_VECT(SIM_TXI, 0x1C40),
+ INTC_VECT(SIM_TEI, 0x1C60),
+ INTC_VECT(STPRO_0, 0x1C80),
+ INTC_VECT(STPRO_1, 0x1CA0),
+ INTC_VECT(STPRO_2, 0x1CC0),
+ INTC_VECT(STPRO_3, 0x1CE0),
+ INTC_VECT(STPRO_4, 0x1D00),
+};
+
+static struct intc_group intca_groups[] __initdata = {
+ INTC_GROUP(DMAC1_1,
+ DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
+ INTC_GROUP(DMAC1_2,
+ DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
+ INTC_GROUP(DMAC2_1,
+ DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
+ INTC_GROUP(DMAC2_2,
+ DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
+ INTC_GROUP(DMAC3_1,
+ DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
+ INTC_GROUP(DMAC3_2,
+ DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
+ INTC_GROUP(AP_ARM1,
+ AP_ARM_COMMTX, AP_ARM_COMMRX),
+ INTC_GROUP(AP_ARM2,
+ AP_ARM_CTIIRQ, AP_ARM_PMURQ),
+ INTC_GROUP(USBF,
+ USBF_OUL_SOF, USBF_IXL_INT),
+ INTC_GROUP(SDHI0,
+ SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
+ INTC_GROUP(SDHI1,
+ SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
+ INTC_GROUP(SDHI2,
+ SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
+ INTC_GROUP(SHWYSTAT,
+ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
+ INTC_GROUP(USBH1, /* FIXME */
+ USBH_INT, USBH_OHCI),
+ INTC_GROUP(USBH2, /* FIXME */
+ USBH_EHCI,
+ USBH_PME, USBH_BIND),
+ INTC_GROUP(RSPI,
+ RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
+ INTC_GROUP(SPU2,
+ SPU2_0, SPU2_1),
+ INTC_GROUP(FLCTL,
+ FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
+ INTC_GROUP(IIC1,
+ IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
+};
+
+static struct intc_mask_reg intca_mask_registers[] __initdata = {
+ { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
+ { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
+ 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
+ { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
+ { ATAPI, 0, DIRC, 0,
+ DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
+ { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
+ { 0, 0, 0, 0,
+ BBIF1, BBIF2, MFIS, MFI } },
+ { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
+ { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
+ DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
+ { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
+ { DDM, 0, 0, 0,
+ 0, 0, 0, 0 } },
+ { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
+ { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
+ SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
+ { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
+ { SCIFB, SCIFA5, SCIFA4, MSIOF1,
+ 0, 0, MSIOF2, 0 } },
+ { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
+ { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
+ FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
+ { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
+ { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
+ 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
+ { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
+ { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
+ CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
+ { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
+ { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
+ 0, 0, 0, 0 } },
+ { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
+ { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
+ ICBS0, 0, 0, 0 } },
+ { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
+ { 0, 0, TPU0, SCIFA6,
+ SCIFA7, GbEther, 0, 0 } },
+ { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
+ { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
+ 0, CMT3, 0, RWDT0 } },
+ { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
+ { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
+ 0, 0, 0, 0 } },
+ /* IMR1A3 / IMCR1A3 */
+ { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
+ { 0, 0, USBH_INT, USBH_OHCI,
+ USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
+ /* IMR3A3 / IMCR3A3 */
+ { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
+ { 0, 0, 0, 0,
+ RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
+ { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
+ { SPU2_0, SPU2_1, FSI, FMSI,
+ 0, 0, 0, 0 } },
+ { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
+ { 0, IPMMU, 0, 0,
+ AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
+ { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
+ { MFIS2, CPORTR2S, CMT14, CMT15,
+ 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
+ /* IMR8A3 / IMCR8A3 */
+ { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
+ { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
+ STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
+ { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
+ { STPRO_4, 0, 0, 0,
+ 0, 0, 0, 0 } },
+};
+
+static struct intc_prio_reg intca_prio_registers[] __initdata = {
+ { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
+ { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
+ { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
+ { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
+ { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
+ { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
+ SGX540, CMT1_0 } },
+ { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
+ SCIFA2, SCIFA3 } },
+ { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
+ FLCTL, SDHI0 } },
+ { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
+ { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
+ AP_ARM_L2CINT, 0 } },
+ { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
+ { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
+ SCIFA7, GbEther } },
+ { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
+ { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
+ { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
+ { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
+ /* IPRBA3 */
+ /* IPRCA3 */
+ /* IPRDA3 */
+ { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
+ { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
+ /* IPRGA3 */
+ /* IPRHA3 */
+ /* IPRIA3 */
+ { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
+ { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
+ /* IPRLA3 */
+ { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
+ { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
+ { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
+ CMT14, CMT15 } },
+ { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
+ /* IPRQA3 */
+ /* IPRRA3 */
+ { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
+ SIM_TXI, SIM_TEI } },
+ { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
+ STPRO_2, STPRO_3 } },
+ { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
+};
+
+static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
+ intca_vectors, intca_groups,
+ intca_mask_registers, intca_prio_registers,
+ NULL);
+
+INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
+ INTC_VECT, "r8a7740-intca-irq-pins");
+
+
+/*
+ * INTCS
+ */
+enum {
+ UNUSED_INTCS = 0,
+
+ INTCS,
+
+ /* interrupt sources INTCS */
+
+ /* HUDI */
+ /* STPRO */
+ /* RTDMAC(1) */
+ VPU5HA2,
+ _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
+ /* MFI */
+ /* BBIF2 */
+ VPU5F,
+ _2DG_BRK_INT,
+ /* SGX540 */
+ /* 2DDMAC */
+ /* IPMMU */
+ /* RTDMAC 2 */
+ /* KEYSC */
+ /* MSIOF */
+ IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
+ TMU0_0, TMU0_1, TMU0_2,
+ CMT0,
+ /* CMT2 */
+ LMB,
+ CTI,
+ VOU,
+ /* RWDT0 */
+ ICB,
+ VIO6C,
+ CEU20, CEU21,
+ JPU,
+ LCDC0,
+ LCRC,
+ /* RTDMAC2(1) */
+ /* RTDMAC2(2) */
+ LCDC1,
+ /* SPU2 */
+ /* FSI */
+ /* FMSI */
+ TMU1_0, TMU1_1, TMU1_2,
+ CMT4,
+ DISP,
+ DSRV,
+ /* MFIS2 */
+ CPORTS2R,
+
+ /* interrupt groups INTCS */
+ _2DG1,
+ IIC0, TMU1,
+};
+
+static struct intc_vect intcs_vectors[] = {
+ /* HUDI */
+ /* STPRO */
+ /* RTDMAC(1) */
+ INTCS_VECT(VPU5HA2, 0x0880),
+ INTCS_VECT(_2DG_TRAP, 0x08A0),
+ INTCS_VECT(_2DG_GPM_INT, 0x08C0),
+ INTCS_VECT(_2DG_CER_INT, 0x08E0),
+ /* MFI */
+ /* BBIF2 */
+ INTCS_VECT(VPU5F, 0x0980),
+ INTCS_VECT(_2DG_BRK_INT, 0x09A0),
+ /* SGX540 */
+ /* 2DDMAC */
+ /* IPMMU */
+ /* RTDMAC(2) */
+ /* KEYSC */
+ /* MSIOF */
+ INTCS_VECT(IIC0_ALI, 0x0E00),
+ INTCS_VECT(IIC0_TACKI, 0x0E20),
+ INTCS_VECT(IIC0_WAITI, 0x0E40),
+ INTCS_VECT(IIC0_DTEI, 0x0E60),
+ INTCS_VECT(TMU0_0, 0x0E80),
+ INTCS_VECT(TMU0_1, 0x0EA0),
+ INTCS_VECT(TMU0_2, 0x0EC0),
+ INTCS_VECT(CMT0, 0x0F00),
+ /* CMT2 */
+ INTCS_VECT(LMB, 0x0F60),
+ INTCS_VECT(CTI, 0x0400),
+ INTCS_VECT(VOU, 0x0420),
+ /* RWDT0 */
+ INTCS_VECT(ICB, 0x0480),
+ INTCS_VECT(VIO6C, 0x04E0),
+ INTCS_VECT(CEU20, 0x0500),
+ INTCS_VECT(CEU21, 0x0520),
+ INTCS_VECT(JPU, 0x0560),
+ INTCS_VECT(LCDC0, 0x0580),
+ INTCS_VECT(LCRC, 0x05A0),
+ /* RTDMAC2(1) */
+ /* RTDMAC2(2) */
+ INTCS_VECT(LCDC1, 0x1780),
+ /* SPU2 */
+ /* FSI */
+ /* FMSI */
+ INTCS_VECT(TMU1_0, 0x1900),
+ INTCS_VECT(TMU1_1, 0x1920),
+ INTCS_VECT(TMU1_2, 0x1940),
+ INTCS_VECT(CMT4, 0x1980),
+ INTCS_VECT(DISP, 0x19A0),
+ INTCS_VECT(DSRV, 0x19C0),
+ /* MFIS2 */
+ INTCS_VECT(CPORTS2R, 0x1A20),
+
+ INTC_VECT(INTCS, 0xf80),
+};
+
+static struct intc_group intcs_groups[] __initdata = {
+ INTC_GROUP(_2DG1, /*FIXME*/
+ _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
+ INTC_GROUP(IIC0,
+ IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
+ INTC_GROUP(TMU1,
+ TMU1_0, TMU1_1, TMU1_2),
+};
+
+static struct intc_mask_reg intcs_mask_registers[] = {
+ /* IMR0SA / IMCR0SA */ /* all 0 */
+ { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
+ { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
+ 0, 0, 0, 0 /*STPRO*/ } },
+ { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
+ { 0/*STPRO*/, 0, CEU21, VPU5F,
+ 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
+ { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
+ { 0, 0, 0, 0, /*2DDMAC*/
+ VIO6C, 0, 0, ICB } },
+ { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
+ { 0, 0, VOU, CTI,
+ JPU, 0, LCRC, LCDC0 } },
+ /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
+ /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
+ { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
+ { 0, TMU0_2, TMU0_1, TMU0_0,
+ 0, 0, 0, 0 } },
+ { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
+ { 0, 0, 0, 0,
+ CEU20, 0, 0, 0 } },
+ { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
+ { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
+ 0, 0, 0, 0 } },
+ /* IMR10SA / IMCR10SA */ /*IPMMU*/
+ { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
+ { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
+ 0, _2DG_BRK_INT, LMB, 0 } },
+ /* IMR12SA / IMCR12SA */
+ /* IMR13SA / IMCR13SA */
+ /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
+ /* IMR1SA3 / IMCR1SA3 */
+ /* IMR2SA3 / IMCR2SA3 */
+ /* IMR3SA3 / IMCR3SA3 */
+ { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
+ { 0, 0, 0, 0,
+ LCDC1, 0, 0, 0 } },
+ /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
+ { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
+ { TMU1_0, TMU1_1, TMU1_2, 0,
+ CMT4, DISP, DSRV, 0 } },
+ { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
+ { 0/*MFIS2*/, CPORTS2R, 0, 0,
+ 0, 0, 0, 0 } },
+ { /* INTAMASK */ 0xffd20104, 0, 16,
+ { 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, INTCS } },
+};
+
+/* Priority is needed for INTCA to receive the INTCS interrupt */
+static struct intc_prio_reg intcs_prio_registers[] = {
+ { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
+ { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
+ /* IPRCS */ /*BBIF2*/
+ /* IPRDS */
+ { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
+ 0/*MFI*/, VPU5F } },
+ { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
+ 0/*CMT2*/, CMT0 } },
+ { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
+ TMU0_2, _2DG1 } },
+ { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
+ _2DG_BRK_INT/*FIXME*/ } },
+ { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
+ { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
+ { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
+ { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
+ /* IPRMS */ /*RWDT0*/
+ /* IPRAS3 */ /*RTDMAC2(1)*/
+ /* IPRBS3 */ /*RTDMAC2(2)*/
+ /* IPRCS3 */
+ /* IPRDS3 */
+ /* IPRES3 */
+ /* IPRFS3 */
+ /* IPRGS3 */
+ /* IPRHS3 */
+ /* IPRIS3 */
+ { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
+ /* IPRKS3 */ /*SPU2/FSI/FMSi*/
+ /* IPRLS3 */
+ { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
+ { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
+ { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
+ /* IPRPS3 */
+};
+
+static struct resource intcs_resources[] __initdata = {
+ [0] = {
+ .start = 0xffd20000,
+ .end = 0xffd201ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = 0xffd50000,
+ .end = 0xffd501ff,
+ .flags = IORESOURCE_MEM,
+ }
+};
+
+static struct intc_desc intcs_desc __initdata = {
+ .name = "r8a7740-intcs",
+ .resource = intcs_resources,
+ .num_resources = ARRAY_SIZE(intcs_resources),
+ .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
+ intcs_prio_registers, NULL, NULL),
+};
+
+static void intcs_demux(unsigned int irq, struct irq_desc *desc)
+{
+ void __iomem *reg = (void *)irq_get_handler_data(irq);
+ unsigned int evtcodeas = ioread32(reg);
+
+ generic_handle_irq(intcs_evt2irq(evtcodeas));
+}
+
+void __init r8a7740_init_irq(void)
+{
+ void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
+
+ register_intc_controller(&intca_desc);
+ register_intc_controller(&intca_irq_pins_desc);
+ register_intc_controller(&intcs_desc);
+
+ /* demux using INTEVTSA */
+ irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
+ irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
+}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
new file mode 100644
index 000000000000..5d92fcde2bc3
--- /dev/null
+++ b/arch/arm/mach-shmobile/intc-r8a7779.c
@@ -0,0 +1,58 @@
+/*
+ * r8a7779 processor support - INTC hardware block
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <mach/common.h>
+#include <mach/intc.h>
+#include <mach/r8a7779.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define INT2SMSKCR0 0xfe7822a0
+#define INT2SMSKCR1 0xfe7822a4
+#define INT2SMSKCR2 0xfe7822a8
+#define INT2SMSKCR3 0xfe7822ac
+#define INT2SMSKCR4 0xfe7822b0
+
+static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
+{
+ return 0; /* always allow wakeup */
+}
+
+void __init r8a7779_init_irq(void)
+{
+ void __iomem *gic_dist_base = __io(0xf0001000);
+ void __iomem *gic_cpu_base = __io(0xf0000100);
+
+ /* use GIC to handle interrupts */
+ gic_init(0, 29, gic_dist_base, gic_cpu_base);
+ gic_arch_extn.irq_set_wake = r8a7779_set_wake;
+
+ /* unmask all known interrupts in INTCS2 */
+ __raw_writel(0xfffffff0, INT2SMSKCR0);
+ __raw_writel(0xfff7ffff, INT2SMSKCR1);
+ __raw_writel(0xfffbffdf, INT2SMSKCR2);
+ __raw_writel(0xbffffffc, INT2SMSKCR3);
+ __raw_writel(0x003fee3f, INT2SMSKCR4);
+}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7740.c b/arch/arm/mach-shmobile/pfc-r8a7740.c
new file mode 100644
index 000000000000..a4fff6950b03
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7740.c
@@ -0,0 +1,2562 @@
+/*
+ * R8A7740 processor support
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/r8a7740.h>
+
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
+ PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##20, sfx), \
+ PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ /* PORT0_DATA -> PORT211_DATA */
+ PINMUX_DATA_BEGIN,
+ PORT_ALL(DATA),
+ PINMUX_DATA_END,
+
+ /* PORT0_IN -> PORT211_IN */
+ PINMUX_INPUT_BEGIN,
+ PORT_ALL(IN),
+ PINMUX_INPUT_END,
+
+ /* PORT0_IN_PU -> PORT211_IN_PU */
+ PINMUX_INPUT_PULLUP_BEGIN,
+ PORT_ALL(IN_PU),
+ PINMUX_INPUT_PULLUP_END,
+
+ /* PORT0_IN_PD -> PORT211_IN_PD */
+ PINMUX_INPUT_PULLDOWN_BEGIN,
+ PORT_ALL(IN_PD),
+ PINMUX_INPUT_PULLDOWN_END,
+
+ /* PORT0_OUT -> PORT211_OUT */
+ PINMUX_OUTPUT_BEGIN,
+ PORT_ALL(OUT),
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
+ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
+ PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
+ PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
+ PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
+ PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
+ PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
+ PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
+ PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
+ PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
+
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ MSEL1CR_30_0, MSEL1CR_30_1,
+ MSEL1CR_29_0, MSEL1CR_29_1,
+ MSEL1CR_28_0, MSEL1CR_28_1,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ MSEL1CR_26_0, MSEL1CR_26_1,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ MSEL1CR_9_0, MSEL1CR_9_1,
+ MSEL1CR_7_0, MSEL1CR_7_1,
+ MSEL1CR_6_0, MSEL1CR_6_1,
+ MSEL1CR_5_0, MSEL1CR_5_1,
+ MSEL1CR_4_0, MSEL1CR_4_1,
+ MSEL1CR_3_0, MSEL1CR_3_1,
+ MSEL1CR_2_0, MSEL1CR_2_1,
+ MSEL1CR_0_0, MSEL1CR_0_1,
+
+ MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
+ MSEL3CR_6_0, MSEL3CR_6_1,
+
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ MSEL4CR_6_0, MSEL4CR_6_1,
+ MSEL4CR_4_0, MSEL4CR_4_1,
+ MSEL4CR_1_0, MSEL4CR_1_1,
+
+ MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ MSEL5CR_8_0, MSEL5CR_8_1,
+ MSEL5CR_7_0, MSEL5CR_7_1,
+ MSEL5CR_6_0, MSEL5CR_6_1,
+ MSEL5CR_5_0, MSEL5CR_5_1,
+ MSEL5CR_4_0, MSEL5CR_4_1,
+ MSEL5CR_3_0, MSEL5CR_3_1,
+ MSEL5CR_2_0, MSEL5CR_2_1,
+ MSEL5CR_0_0, MSEL5CR_0_1,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+ /* IRQ */
+ IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
+ IRQ1_MARK,
+ IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
+ IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
+ IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
+ IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
+ IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
+ IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
+ IRQ8_MARK,
+ IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
+ IRQ10_MARK,
+ IRQ11_MARK,
+ IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
+ IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
+ IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
+ IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
+ IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
+ IRQ17_MARK,
+ IRQ18_MARK,
+ IRQ19_MARK,
+ IRQ20_MARK,
+ IRQ21_MARK,
+ IRQ22_MARK,
+ IRQ23_MARK,
+ IRQ24_MARK,
+ IRQ25_MARK,
+ IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
+ IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
+ IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
+ IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
+ IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
+ IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
+
+ /* Function */
+
+ /* DBGT */
+ DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
+ DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
+ DBGMD21_MARK,
+
+ /* FSI */
+ FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
+ FSIAISLD_PORT5_MARK,
+ FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
+ FSIASPDIF_PORT18_MARK,
+ FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
+ FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
+ FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
+
+ /* FMSI */
+ FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
+ FMSISLD_PORT6_MARK,
+ FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
+ FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
+ FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
+
+ /* SCIFA0 */
+ SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+
+ /* SCIFA1 */
+ SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
+ SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
+
+ /* SCIFA2 */
+ SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
+ SCIFA2_SCK_PORT199_MARK,
+ SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+ SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
+
+ /* SCIFA3 */
+ SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
+ SCIFA3_SCK_PORT116_MARK,
+ SCIFA3_CTS_PORT117_MARK,
+ SCIFA3_RXD_PORT174_MARK,
+ SCIFA3_TXD_PORT175_MARK,
+
+ SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
+ SCIFA3_SCK_PORT158_MARK,
+ SCIFA3_CTS_PORT162_MARK,
+ SCIFA3_RXD_PORT159_MARK,
+ SCIFA3_TXD_PORT160_MARK,
+
+ /* SCIFA4 */
+ SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
+ SCIFA4_TXD_PORT13_MARK,
+
+ SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
+ SCIFA4_TXD_PORT203_MARK,
+
+ SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
+ SCIFA4_TXD_PORT93_MARK,
+
+ SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
+ SCIFA4_SCK_PORT205_MARK,
+
+ /* SCIFA5 */
+ SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
+ SCIFA5_RXD_PORT10_MARK,
+
+ SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
+ SCIFA5_TXD_PORT208_MARK,
+
+ SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
+ SCIFA5_RXD_PORT92_MARK,
+
+ SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
+ SCIFA5_SCK_PORT206_MARK,
+
+ /* SCIFA6 */
+ SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+
+ /* SCIFA7 */
+ SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
+
+ /* SCIFAB */
+ SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
+ SCIFB_RXD_PORT191_MARK,
+ SCIFB_TXD_PORT192_MARK,
+ SCIFB_RTS_PORT186_MARK,
+ SCIFB_CTS_PORT187_MARK,
+
+ SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
+ SCIFB_RXD_PORT3_MARK,
+ SCIFB_TXD_PORT4_MARK,
+ SCIFB_RTS_PORT172_MARK,
+ SCIFB_CTS_PORT173_MARK,
+
+ /* LCD0 */
+ LCDC0_SELECT_MARK,
+
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK,
+ LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+ LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
+ LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
+ LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
+ LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
+
+ LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
+ LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
+ LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
+ LCD0_LCLK_PORT165_MARK,
+
+ LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
+ LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
+ LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
+ LCD0_LCLK_PORT102_MARK,
+
+ /* LCD1 */
+ LCDC1_SELECT_MARK,
+
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+ LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+ LCD1_DON_MARK, LCD1_VCPWC_MARK,
+ LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
+
+ LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
+ LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
+ LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
+ LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
+
+ /* RSPI */
+ RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
+ RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
+ RSPI_MISO_A_MARK,
+
+ /* VIO CKO */
+ VIO_CKO1_MARK, /* needs fixup */
+ VIO_CKO2_MARK,
+ VIO_CKO_1_MARK,
+ VIO_CKO_MARK,
+
+ /* VIO0 */
+ VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+ VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+ VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+ VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
+ VIO0_FIELD_MARK,
+
+ VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
+ VIO0_D14_PORT25_MARK,
+ VIO0_D15_PORT24_MARK,
+
+ VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
+ VIO0_D14_PORT95_MARK,
+ VIO0_D15_PORT96_MARK,
+
+ /* VIO1 */
+ VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+ VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+ VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
+
+ /* TPU0 */
+ TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
+ TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
+ TPU0TO2_PORT202_MARK,
+
+ /* SSP1 0 */
+ STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
+ STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
+ STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
+
+ /* SSP1 1 */
+ STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
+ STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
+ STP1_IPSYNC_MARK,
+
+ STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
+ STP1_IPEN_PORT187_MARK,
+
+ STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
+ STP1_IPEN_PORT193_MARK,
+
+ /* SIM */
+ SIM_RST_MARK, SIM_CLK_MARK,
+ SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
+ SIM_D_PORT199_MARK,
+
+ /* SDHI0 */
+ SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+ SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+
+ /* SDHI1 */
+ SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+ SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+
+ /* SDHI2 */
+ SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+ SDHI2_CLK_MARK, SDHI2_CMD_MARK,
+
+ SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
+ SDHI2_WP_PORT25_MARK,
+
+ SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
+ SDHI2_CD_PORT202_MARK,
+
+ /* MSIOF2 */
+ MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
+ MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
+ MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
+ MSIOF2_RSCK_MARK,
+
+ /* KEYSC */
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+ KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+
+ KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
+ KEYIN1_PORT44_MARK,
+ KEYIN2_PORT45_MARK,
+ KEYIN3_PORT46_MARK,
+
+ KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
+ KEYIN1_PORT57_MARK,
+ KEYIN2_PORT56_MARK,
+ KEYIN3_PORT55_MARK,
+
+ /* VOU */
+ DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
+ DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
+ DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
+ DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
+ DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
+
+ /* MEMC */
+ MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
+ MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
+ MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
+ MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
+ MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
+
+ MEMC_CS1_MARK, /* MSEL4CR_6_0 */
+ MEMC_ADV_MARK,
+ MEMC_WAIT_MARK,
+ MEMC_BUSCLK_MARK,
+
+ MEMC_A1_MARK, /* MSEL4CR_6_1 */
+ MEMC_DREQ0_MARK,
+ MEMC_DREQ1_MARK,
+ MEMC_A0_MARK,
+
+ /* MMC */
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
+ MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
+ MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
+ MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
+
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
+ MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
+ MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
+ MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
+ MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
+ MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
+ MSIOF0_TSYNC_MARK,
+
+ /* MSIOF1 */
+ MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
+ MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
+
+ MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
+ MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
+ MSIOF1_TSYNC_PORT120_MARK,
+ MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
+
+ MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
+ MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
+ MSIOF1_RXD_PORT75_MARK,
+ MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
+
+ /* USB0 */
+ USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
+
+ /* USB1 */
+ USB1_OCI_MARK, USB1_PPON_MARK,
+
+ /* BBIF1 */
+ BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
+ BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
+ BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
+
+ /* BBIF2 */
+ BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
+ BBIF2_RXD2_PORT60_MARK,
+ BBIF2_TSYNC2_PORT6_MARK,
+ BBIF2_TSCK2_PORT59_MARK,
+
+ BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
+ BBIF2_TXD2_PORT183_MARK,
+ BBIF2_TSCK2_PORT89_MARK,
+ BBIF2_TSYNC2_PORT184_MARK,
+
+ /* BSC / FLCTL / PCMCIA */
+ CS0_MARK, CS2_MARK, CS4_MARK,
+ CS5B_MARK, CS6A_MARK,
+ CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
+ CS5A_PORT19_MARK,
+ IOIS16_MARK, /* ? */
+
+ A0_MARK, A1_MARK, A2_MARK, A3_MARK,
+ A4_FOE_MARK, /* share with FLCTL */
+ A5_FCDE_MARK, /* share with FLCTL */
+ A6_MARK, A7_MARK, A8_MARK, A9_MARK,
+ A10_MARK, A11_MARK, A12_MARK, A13_MARK,
+ A14_MARK, A15_MARK, A16_MARK, A17_MARK,
+ A18_MARK, A19_MARK, A20_MARK, A21_MARK,
+ A22_MARK, A23_MARK, A24_MARK, A25_MARK,
+ A26_MARK,
+
+ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
+ D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
+ D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
+ D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
+ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
+ D15_NAF15_MARK, /* share with FLCTL */
+ D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+ D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+ D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+ D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+
+ WE0_FWE_MARK, /* share with FLCTL */
+ WE1_MARK,
+ WE2_ICIORD_MARK, /* share with PCMCIA */
+ WE3_ICIOWR_MARK, /* share with PCMCIA */
+ CKO_MARK, BS_MARK, RDWR_MARK,
+ RD_FSC_MARK, /* share with FLCTL */
+ WAIT_PORT177_MARK, /* WAIT Port 90/177 */
+ WAIT_PORT90_MARK,
+
+ FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
+
+ /* IRDA */
+ IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
+
+ /* ATAPI */
+ IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
+ IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
+ IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
+ IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
+ IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
+ IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
+ IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
+ IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
+
+ /* RMII */
+ RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
+ RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
+ RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
+ RMII_REF50CK_MARK, /* for RMII */
+ RMII_REF125CK_MARK, /* for GMII */
+
+ /* GEther */
+ ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
+ ET_ETXD2_MARK, ET_ETXD3_MARK,
+ ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
+ ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
+ ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
+ ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+ ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
+ ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
+ ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+ ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
+
+ /* DMA0 */
+ DREQ0_MARK, DACK0_MARK,
+
+ /* DMA1 */
+ DREQ1_MARK, DACK1_MARK,
+
+ /* SYSC */
+ RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
+
+ /* IRREM */
+ IROUT_MARK,
+
+ /* SDENC */
+ SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
+
+ /* DEBUG */
+ EDEBGREQ_PULLUP_MARK, /* for JTAG */
+ EDEBGREQ_PULLDOWN_MARK,
+
+ TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
+ TRACEAUD_FROM_LCDC0_MARK,
+ TRACEAUD_FROM_MEMC_MARK,
+
+ PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+ /* specify valid pin states for each pin in GPIO mode */
+
+ /* I/O and Pull U/D */
+ PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
+ PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3),
+ PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5),
+ PORT_DATA_IO_PD(6), PORT_DATA_IO(7),
+ PORT_DATA_IO(8), PORT_DATA_IO(9),
+
+ PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11),
+ PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13),
+ PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15),
+ PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17),
+ PORT_DATA_IO(18), PORT_DATA_IO_PU(19),
+
+ PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21),
+ PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23),
+ PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25),
+ PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27),
+ PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29),
+
+ PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31),
+ PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33),
+ PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35),
+ PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37),
+ PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39),
+
+ PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41),
+ PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43),
+ PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45),
+ PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47),
+ PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49),
+
+ PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51),
+ PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53),
+ PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55),
+ PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57),
+ PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59),
+
+ PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61),
+ PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63),
+ PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65),
+ PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67),
+ PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69),
+
+ PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71),
+ PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73),
+ PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75),
+ PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77),
+ PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79),
+
+ PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81),
+ PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83),
+ PORT_DATA_IO(84), PORT_DATA_IO_PD(85),
+ PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87),
+ PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89),
+
+ PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91),
+ PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93),
+ PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95),
+ PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97),
+ PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99),
+
+ PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101),
+ PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103),
+ PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105),
+ PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107),
+ PORT_DATA_IO(108), PORT_DATA_IO(109),
+
+ PORT_DATA_IO(110), PORT_DATA_IO(111),
+ PORT_DATA_IO(112), PORT_DATA_IO(113),
+ PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115),
+ PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117),
+ PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119),
+
+ PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121),
+ PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123),
+ PORT_DATA_IO_PD(124), PORT_DATA_IO(125),
+ PORT_DATA_IO(126), PORT_DATA_IO(127),
+ PORT_DATA_IO(128), PORT_DATA_IO(129),
+
+ PORT_DATA_IO(130), PORT_DATA_IO(131),
+ PORT_DATA_IO(132), PORT_DATA_IO(133),
+ PORT_DATA_IO(134), PORT_DATA_IO(135),
+ PORT_DATA_IO(136), PORT_DATA_IO(137),
+ PORT_DATA_IO(138), PORT_DATA_IO(139),
+
+ PORT_DATA_IO(140), PORT_DATA_IO(141),
+ PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143),
+ PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145),
+ PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147),
+ PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149),
+
+ PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151),
+ PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153),
+ PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155),
+ PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157),
+ PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159),
+
+ PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161),
+ PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163),
+ PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165),
+ PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167),
+ PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169),
+
+ PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171),
+ PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173),
+ PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175),
+ PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177),
+ PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179),
+
+ PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181),
+ PORT_DATA_IO_PU(182), PORT_DATA_IO(183),
+ PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185),
+ PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187),
+ PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189),
+
+ PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191),
+ PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193),
+ PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195),
+ PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197),
+ PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199),
+
+ PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201),
+ PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203),
+ PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205),
+ PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207),
+ PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209),
+
+ PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211),
+
+ /* Port0 */
+ PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
+ PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
+ PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
+ PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
+ PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
+ PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
+
+ /* Port1 */
+ PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
+ PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
+ PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
+ PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
+ PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
+ PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
+
+ /* Port2 */
+ PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
+ PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
+ PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
+
+ /* Port3 */
+ PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
+ PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
+
+ /* Port4 */
+ PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
+ PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
+
+ /* Port5 */
+ PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
+ PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
+ PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
+ PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
+
+ /* Port6 */
+ PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
+ PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
+ PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
+ PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
+
+ /* Port7 */
+ PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
+
+ /* Port8 */
+ PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
+
+ /* Port9 */
+ PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
+ PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
+
+ /* Port10 */
+ PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
+ PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
+ PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
+
+ /* Port11 */
+ PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
+ PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
+
+ /* Port12 */
+ PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
+ PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
+ PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
+ PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
+ PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
+
+ /* Port13 */
+ PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
+ PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
+ PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
+ PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
+
+ /* Port14 */
+ PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
+ PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
+ PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
+ PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
+ PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
+
+ /* Port15 */
+ PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
+ PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
+ PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
+ PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
+ PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
+
+ /* Port16 */
+ PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
+ PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
+
+ /* Port17 */
+ PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
+ PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
+
+ /* Port18 */
+ PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
+ PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
+
+ /* Port19 */
+ PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
+ PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
+ PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
+
+ /* Port20 */
+ PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
+ PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
+ PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
+
+ /* Port21 */
+ PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
+ PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
+ PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
+ PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
+ PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
+ PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
+
+ /* Port22 */
+ PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
+ PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
+ PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
+
+ /* Port23 */
+ PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
+ PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
+ PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
+ PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
+ PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
+ PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
+
+ /* Port24 */
+ PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
+ PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
+ PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
+
+ /* Port25 */
+ PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
+ PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
+ PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
+
+ /* Port26 */
+ PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
+ PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
+ PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
+
+ /* Port27 - Port39 Function */
+ PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
+ PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
+ PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
+ PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
+ PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
+ PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
+ PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
+ PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
+ PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
+ PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
+ PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
+ PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
+ PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
+
+ /* Port38 IRQ */
+ PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
+
+ /* Port40 */
+ PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
+ PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
+ PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
+
+ /* Port41 */
+ PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
+ PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
+ PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
+
+ /* Port42 */
+ PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
+ PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
+ PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
+
+ /* Port43 */
+ PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
+ PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
+ PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
+
+ /* Port44 */
+ PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
+ PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
+ PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
+
+ /* Port45 */
+ PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
+ PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
+ PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
+
+ /* Port46 */
+ PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
+ PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
+ PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
+
+ /* Port47 */
+ PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
+ PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
+ PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
+
+ /* Port48 */
+ PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
+ PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
+ PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
+
+ /* Port49 */
+ PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
+ PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
+ PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
+ PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
+
+ /* Port50 */
+ PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
+ PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
+ PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
+ PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
+
+ /* Port51 */
+ PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
+ PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
+ PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
+
+ /* Port52 */
+ PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
+ PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
+ PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
+
+ /* Port53 */
+ PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
+ PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
+ PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
+
+ /* Port54 */
+ PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
+ PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
+ PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
+
+ /* Port55 */
+ PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
+ PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
+ PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
+
+ /* Port56 */
+ PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
+ PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
+ PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
+ PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
+
+ /* Port57 */
+ PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
+ PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
+ PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
+ PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
+
+ /* Port58 */
+ PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1),
+ PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
+ PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
+ PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
+ PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
+
+ /* Port59 */
+ PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
+ PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
+
+ /* Port60 */
+ PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
+ PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
+ PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
+
+ /* Port61 */
+ PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
+ PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
+
+ /* Port62 */
+ PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
+ PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
+ PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
+ PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
+
+ /* Port63 */
+ PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
+ PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
+ PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
+
+ /* Port64 */
+ PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
+ PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
+ PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
+ PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
+
+ /* Port65 */
+ PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
+ PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
+ PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
+
+ /* Port66 */
+ PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
+ PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
+ PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
+
+ /* Port67 - Port73 Function1 */
+ PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
+ PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
+ PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
+ PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
+ PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
+ PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
+ PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
+
+ /* Port67 - Port73 Function2 */
+ PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
+ PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
+ PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
+ PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
+ PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
+
+ /* Port67 - Port73 Function4 */
+ PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
+
+ /* Port67 - Port73 Function6 */
+ PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
+ PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
+ PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
+ PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
+ PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
+ PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
+ PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
+
+ /* Port67 - Port71 IRQ */
+ PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
+ PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
+ PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
+ PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
+ PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
+
+ /* Port74 */
+ PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
+ PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
+ PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
+
+ /* Port75 */
+ PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
+ PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
+ PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
+ PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
+
+ /* Port76 - Port80 Function */
+ PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
+ PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
+ PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
+ PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
+ PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
+
+ /* Port81 */
+ PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
+ PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
+
+ /* Port82 - Port88 Function */
+ PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
+ PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
+ PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
+ PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
+ PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
+ PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
+ PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
+
+ /* Port89 */
+ PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
+ PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
+
+ /* Port90 */
+ PINMUX_DATA(DACK0_MARK, PORT90_FN1),
+ PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
+ PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
+
+ /* Port91 */
+ PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
+ PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
+ PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
+ PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
+
+ /* Port92 */
+ PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
+ PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
+ PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
+ PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
+ PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
+
+ /* Port93 */
+ PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
+ PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
+ PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
+ PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
+ PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
+
+ /* Port94 */
+ PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
+ PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
+ PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
+ PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
+ PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
+
+ /* Port95 */
+ PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
+ PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
+ PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
+ PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
+
+ /* Port96 */
+ PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
+ PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
+ PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
+ PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
+
+ /* Port97 */
+ PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
+ PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
+ PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
+ PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
+ PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
+
+ /* Port98 */
+ PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
+ PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
+ PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
+ PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
+
+ /* Port99 */
+ PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
+ PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
+ PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
+ PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
+ PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
+
+ /* Port100 */
+ PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
+ PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
+ PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
+ PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
+
+ /* Port101 */
+ PINMUX_DATA(FCE0_MARK, PORT101_FN1),
+
+ /* Port102 */
+ PINMUX_DATA(FRB_MARK, PORT102_FN1),
+ PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
+
+ /* Port103 */
+ PINMUX_DATA(CS5B_MARK, PORT103_FN1),
+ PINMUX_DATA(FCE1_MARK, PORT103_FN2),
+ PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
+
+ /* Port104 */
+ PINMUX_DATA(CS6A_MARK, PORT104_FN1),
+ PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
+
+ /* Port105 */
+ PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
+ PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
+
+ /* Port106 */
+ PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
+ PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
+
+ /* Port107 - Port115 Function */
+ PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
+ PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
+ PINMUX_DATA(CS0_MARK, PORT109_FN1),
+ PINMUX_DATA(CS2_MARK, PORT110_FN1),
+ PINMUX_DATA(CS4_MARK, PORT111_FN1),
+ PINMUX_DATA(WE1_MARK, PORT112_FN1),
+ PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
+ PINMUX_DATA(RDWR_MARK, PORT114_FN1),
+ PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
+
+ /* Port116 */
+ PINMUX_DATA(A25_MARK, PORT116_FN1),
+ PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
+ PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
+ PINMUX_DATA(GPO1_MARK, PORT116_FN5),
+
+ /* Port117 */
+ PINMUX_DATA(A24_MARK, PORT117_FN1),
+ PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
+ PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
+ PINMUX_DATA(GPO0_MARK, PORT117_FN5),
+
+ /* Port118 */
+ PINMUX_DATA(A23_MARK, PORT118_FN1),
+ PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
+ PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(GPI1_MARK, PORT118_FN5),
+ PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
+
+ /* Port119 */
+ PINMUX_DATA(A22_MARK, PORT119_FN1),
+ PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
+ PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(GPI0_MARK, PORT119_FN5),
+ PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
+
+ /* Port120 */
+ PINMUX_DATA(A21_MARK, PORT120_FN1),
+ PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
+ PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0),
+
+ /* Port121 */
+ PINMUX_DATA(A20_MARK, PORT121_FN1),
+ PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
+ PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
+ PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
+
+ /* Port122 */
+ PINMUX_DATA(A19_MARK, PORT122_FN1),
+ PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
+
+ /* Port123 */
+ PINMUX_DATA(A18_MARK, PORT123_FN1),
+ PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
+
+ /* Port124 */
+ PINMUX_DATA(A17_MARK, PORT124_FN1),
+ PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
+
+ /* Port125 - Port141 Function */
+ PINMUX_DATA(A16_MARK, PORT125_FN1),
+ PINMUX_DATA(A15_MARK, PORT126_FN1),
+ PINMUX_DATA(A14_MARK, PORT127_FN1),
+ PINMUX_DATA(A13_MARK, PORT128_FN1),
+ PINMUX_DATA(A12_MARK, PORT129_FN1),
+ PINMUX_DATA(A11_MARK, PORT130_FN1),
+ PINMUX_DATA(A10_MARK, PORT131_FN1),
+ PINMUX_DATA(A9_MARK, PORT132_FN1),
+ PINMUX_DATA(A8_MARK, PORT133_FN1),
+ PINMUX_DATA(A7_MARK, PORT134_FN1),
+ PINMUX_DATA(A6_MARK, PORT135_FN1),
+ PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
+ PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
+ PINMUX_DATA(A3_MARK, PORT138_FN1),
+ PINMUX_DATA(A2_MARK, PORT139_FN1),
+ PINMUX_DATA(A1_MARK, PORT140_FN1),
+ PINMUX_DATA(CKO_MARK, PORT141_FN1),
+
+ /* Port142 - Port157 Function1 */
+ PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
+ PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
+ PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
+ PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
+ PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
+ PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
+ PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
+ PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
+ PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
+ PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
+ PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
+ PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
+ PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
+ PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
+ PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
+ PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
+
+ /* Port142 - Port149 Function3 */
+ PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
+ PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
+
+ /* Port158 */
+ PINMUX_DATA(D31_MARK, PORT158_FN1),
+ PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
+ PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
+ PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
+
+ /* Port159 */
+ PINMUX_DATA(D30_MARK, PORT159_FN1),
+ PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
+ PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
+
+ /* Port160 */
+ PINMUX_DATA(D29_MARK, PORT160_FN1),
+ PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
+ PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
+
+ /* Port161 */
+ PINMUX_DATA(D28_MARK, PORT161_FN1),
+ PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
+ PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
+ PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
+
+ /* Port162 */
+ PINMUX_DATA(D27_MARK, PORT162_FN1),
+ PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
+ PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
+ PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
+
+ /* Port163 */
+ PINMUX_DATA(D26_MARK, PORT163_FN1),
+ PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
+ PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
+ PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IROUT_MARK, PORT163_FN5),
+ PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
+
+ /* Port164 */
+ PINMUX_DATA(D25_MARK, PORT164_FN1),
+ PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
+ PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
+ PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
+ PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
+
+ /* Port165 */
+ PINMUX_DATA(D24_MARK, PORT165_FN1),
+ PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
+ PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
+ PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
+
+ /* Port166 - Port171 Function1 */
+ PINMUX_DATA(D21_MARK, PORT166_FN1),
+ PINMUX_DATA(D20_MARK, PORT167_FN1),
+ PINMUX_DATA(D19_MARK, PORT168_FN1),
+ PINMUX_DATA(D18_MARK, PORT169_FN1),
+ PINMUX_DATA(D17_MARK, PORT170_FN1),
+ PINMUX_DATA(D16_MARK, PORT171_FN1),
+
+ /* Port166 - Port171 Function3 */
+ PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
+ PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
+ PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
+ PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
+ PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
+ PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
+
+ /* Port166 - Port171 Function6 */
+ PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
+ PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
+ PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
+ PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
+ PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
+ PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
+
+ /* Port167 - Port171 IRQ */
+ PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
+ PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
+ PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
+ PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
+ PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
+
+ /* Port172 */
+ PINMUX_DATA(D23_MARK, PORT172_FN1),
+ PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
+ PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
+ PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
+
+ /* Port173 */
+ PINMUX_DATA(D22_MARK, PORT173_FN1),
+ PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
+ PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
+ PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
+ PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
+
+ /* Port174 */
+ PINMUX_DATA(A26_MARK, PORT174_FN1),
+ PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
+ PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
+ PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
+
+ /* Port175 */
+ PINMUX_DATA(A0_MARK, PORT175_FN1),
+ PINMUX_DATA(BS_MARK, PORT175_FN2),
+ PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
+ PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
+
+ /* Port176 */
+ PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
+
+ /* Port177 */
+ PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
+ PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
+ PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
+ PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
+
+ /* Port178 */
+ PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
+ PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
+ PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
+
+ /* Port179 */
+ PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
+ PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
+ PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
+
+ /* Port180 */
+ PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
+ PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
+ PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
+ PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
+ PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
+
+ /* Port181 */
+ PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
+ PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
+ PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
+
+ /* Port182 */
+ PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
+ PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
+ PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
+
+ /* Port183 */
+ PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
+ PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
+
+ /* Port184 */
+ PINMUX_DATA(DACK1_MARK, PORT184_FN1),
+ PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
+ PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
+
+ /* Port185 - Port192 Function1 */
+ PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
+ PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
+ PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
+ PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
+
+ /* Port185 - Port192 Function3 */
+ PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
+ PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
+ PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
+ PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
+ PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
+ PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
+ PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
+ PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
+
+ /* Port185 - Port192 Function6 */
+ PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
+ PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
+ PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
+ PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
+ PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
+ PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
+ PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
+ PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
+
+ /* Port193 */
+ PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
+ PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
+ PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
+ PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
+
+ /* Port194 */
+ PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
+ PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
+ PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
+ PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
+
+ /* Port195 */
+ PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
+ PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
+ PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
+ PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
+
+ /* Port196 */
+ PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
+ PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
+ PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
+ PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
+
+ /* Port197 */
+ PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
+ PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
+ PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
+ PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
+
+ /* Port198 */
+ PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
+ PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
+ PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
+ PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
+
+ /* Port199 */
+ PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
+ PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
+ PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
+ PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
+ PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
+ PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
+
+ /* Port200 */
+ PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
+ PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
+ PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
+ PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
+ PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
+
+ /* Port201 */
+ PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
+ PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
+ PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
+ PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
+
+ /* Port202 */
+ PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
+ PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
+
+ PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
+ PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
+ PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
+ PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
+ PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
+ PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
+
+ /* Port203 - Port208 Function1 */
+ PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
+ PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
+ PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
+ PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
+ PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
+ PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
+
+ /* Port203 - Port208 Function3 */
+ PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
+ PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
+ PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
+ PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
+ PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
+ PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
+
+ /* Port203 - Port208 Function6 */
+ PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
+ PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
+ PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
+ PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
+ PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
+ PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
+
+ /* Port203 - Port208 Function7 */
+ PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
+ PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
+ PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
+ PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
+ PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
+ PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
+
+ /* Port209 */
+ PINMUX_DATA(VBUS_MARK, PORT209_FN1),
+ PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1),
+
+ /* Port210 */
+ PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
+
+ /* Port211 */
+ PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
+
+ /* LCDC select */
+ PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0),
+ PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1),
+
+ /* SDENC */
+ PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
+ PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
+
+ /* SYSC */
+ PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
+ PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
+
+ /* DEBUG */
+ PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
+ PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
+
+ PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
+ PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
+ PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+ /* PORT */
+ GPIO_PORT_ALL(),
+
+ /* IRQ */
+ GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
+ GPIO_FN(IRQ1),
+ GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12),
+ GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14),
+ GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172),
+ GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1),
+ GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173),
+ GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209),
+ GPIO_FN(IRQ8),
+ GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210),
+ GPIO_FN(IRQ10),
+ GPIO_FN(IRQ11),
+ GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97),
+ GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98),
+ GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99),
+ GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100),
+ GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211),
+ GPIO_FN(IRQ17),
+ GPIO_FN(IRQ18),
+ GPIO_FN(IRQ19),
+ GPIO_FN(IRQ20),
+ GPIO_FN(IRQ21),
+ GPIO_FN(IRQ22),
+ GPIO_FN(IRQ23),
+ GPIO_FN(IRQ24),
+ GPIO_FN(IRQ25),
+ GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81),
+ GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168),
+ GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169),
+ GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170),
+ GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171),
+ GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167),
+
+ /* Function */
+
+ /* DBGT */
+ GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0),
+ GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20),
+ GPIO_FN(DBGMD21),
+
+ /* FSI */
+ GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */
+ GPIO_FN(FSIAISLD_PORT5),
+ GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */
+ GPIO_FN(FSIASPDIF_PORT18),
+ GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR),
+ GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC),
+ GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT),
+
+ /* FMSI */
+ GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
+ GPIO_FN(FMSISLD_PORT6),
+ GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR),
+ GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR),
+ GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT),
+ GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK),
+
+ /* SCIFA0 */
+ GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS),
+ GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD),
+
+ /* SCIFA1 */
+ GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK),
+ GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS),
+
+ /* SCIFA2 */
+ GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
+ GPIO_FN(SCIFA2_SCK_PORT199),
+ GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD),
+ GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS),
+
+ /* SCIFA3 */
+ GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
+ GPIO_FN(SCIFA3_SCK_PORT116),
+ GPIO_FN(SCIFA3_CTS_PORT117),
+ GPIO_FN(SCIFA3_RXD_PORT174),
+ GPIO_FN(SCIFA3_TXD_PORT175),
+
+ GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
+ GPIO_FN(SCIFA3_SCK_PORT158),
+ GPIO_FN(SCIFA3_CTS_PORT162),
+ GPIO_FN(SCIFA3_RXD_PORT159),
+ GPIO_FN(SCIFA3_TXD_PORT160),
+
+ /* SCIFA4 */
+ GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
+ GPIO_FN(SCIFA4_TXD_PORT13),
+
+ GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
+ GPIO_FN(SCIFA4_TXD_PORT203),
+
+ GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
+ GPIO_FN(SCIFA4_TXD_PORT93),
+
+ GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
+ GPIO_FN(SCIFA4_SCK_PORT205),
+
+ /* SCIFA5 */
+ GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
+ GPIO_FN(SCIFA5_RXD_PORT10),
+
+ GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
+ GPIO_FN(SCIFA5_TXD_PORT208),
+
+ GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
+ GPIO_FN(SCIFA5_RXD_PORT92),
+
+ GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
+ GPIO_FN(SCIFA5_SCK_PORT206),
+
+ /* SCIFA6 */
+ GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD),
+
+ /* SCIFA7 */
+ GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD),
+
+ /* SCIFAB */
+ GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
+ GPIO_FN(SCIFB_RXD_PORT191),
+ GPIO_FN(SCIFB_TXD_PORT192),
+ GPIO_FN(SCIFB_RTS_PORT186),
+ GPIO_FN(SCIFB_CTS_PORT187),
+
+ GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
+ GPIO_FN(SCIFB_RXD_PORT3),
+ GPIO_FN(SCIFB_TXD_PORT4),
+ GPIO_FN(SCIFB_RTS_PORT172),
+ GPIO_FN(SCIFB_CTS_PORT173),
+
+ /* LCD0 */
+ GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
+ GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
+ GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
+ GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
+ GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
+ GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
+ GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
+ GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
+ GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
+ GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
+ GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
+
+ GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
+ GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
+ GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
+ GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
+
+ GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
+ GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
+ GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
+ GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
+
+ /* LCD1 */
+ GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
+ GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
+ GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
+ GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
+ GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
+ GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
+ GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
+ GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
+ GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
+ GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
+ GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
+ GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
+
+ /* RSPI */
+ GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
+ GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
+ GPIO_FN(RSPI_MISO_A),
+
+ /* VIO CKO */
+ GPIO_FN(VIO_CKO1),
+ GPIO_FN(VIO_CKO2),
+ GPIO_FN(VIO_CKO_1),
+ GPIO_FN(VIO_CKO),
+
+ /* VIO0 */
+ GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2),
+ GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5),
+ GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8),
+ GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11),
+ GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD),
+ GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD),
+
+ GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
+ GPIO_FN(VIO0_D14_PORT25),
+ GPIO_FN(VIO0_D15_PORT24),
+
+ GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
+ GPIO_FN(VIO0_D14_PORT95),
+ GPIO_FN(VIO0_D15_PORT96),
+
+ /* VIO1 */
+ GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2),
+ GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5),
+ GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD),
+ GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD),
+
+ /* TPU0 */
+ GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3),
+ GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
+ GPIO_FN(TPU0TO2_PORT202),
+
+ /* SSP1 0 */
+ GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2),
+ GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5),
+ GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN),
+ GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC),
+
+ /* SSP1 1 */
+ GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3),
+ GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6),
+ GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC),
+
+ GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
+ GPIO_FN(STP1_IPEN_PORT187),
+
+ GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
+ GPIO_FN(STP1_IPEN_PORT193),
+
+ /* SIM */
+ GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK),
+ GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
+ GPIO_FN(SIM_D_PORT199),
+
+ /* SDHI0 */
+ GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
+ GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
+ GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
+
+ /* SDHI1 */
+ GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
+ GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
+ GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
+
+ /* SDHI2 */
+ GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
+ GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
+
+ GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
+ GPIO_FN(SDHI2_WP_PORT25),
+
+ GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
+ GPIO_FN(SDHI2_CD_PORT202),
+
+ /* MSIOF2 */
+ GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
+ GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
+ GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC),
+ GPIO_FN(MSIOF2_RSCK),
+
+ /* KEYSC */
+ GPIO_FN(KEYIN4), GPIO_FN(KEYIN5),
+ GPIO_FN(KEYIN6), GPIO_FN(KEYIN7),
+ GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2),
+ GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5),
+ GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7),
+
+ GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
+ GPIO_FN(KEYIN1_PORT44),
+ GPIO_FN(KEYIN2_PORT45),
+ GPIO_FN(KEYIN3_PORT46),
+
+ GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
+ GPIO_FN(KEYIN1_PORT57),
+ GPIO_FN(KEYIN2_PORT56),
+ GPIO_FN(KEYIN3_PORT55),
+
+ /* VOU */
+ GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2),
+ GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5),
+ GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8),
+ GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11),
+ GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14),
+ GPIO_FN(DV_D15), GPIO_FN(DV_CLK),
+ GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC),
+
+ /* MEMC */
+ GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2),
+ GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5),
+ GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8),
+ GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11),
+ GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14),
+ GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT),
+ GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1),
+ GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0),
+ GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
+ GPIO_FN(MEMC_A0),
+
+ /* MMC */
+ GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
+ GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
+ GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
+ GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
+ GPIO_FN(MMC0_CLK_PORT66),
+ GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
+
+ GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
+ GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
+ GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
+ GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
+ GPIO_FN(MMC1_CLK_PORT103),
+ GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
+
+ /* MSIOF0 */
+ GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
+ GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
+ GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK),
+ GPIO_FN(MSIOF0_TSYNC),
+
+ /* MSIOF1 */
+ GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC),
+ GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1),
+
+ GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117),
+ GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119),
+ GPIO_FN(MSIOF1_TSYNC_PORT120),
+ GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */
+
+ GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72),
+ GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74),
+ GPIO_FN(MSIOF1_RXD_PORT75),
+ GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */
+
+ /* GPIO */
+ GPIO_FN(GPO0), GPIO_FN(GPI0),
+ GPIO_FN(GPO1), GPIO_FN(GPI1),
+
+ /* USB0 */
+ GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS),
+
+ /* USB1 */
+ GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON),
+
+ /* BBIF1 */
+ GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC),
+ GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
+ GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N),
+
+ /* BBIF2 */
+ GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
+ GPIO_FN(BBIF2_RXD2_PORT60),
+ GPIO_FN(BBIF2_TSYNC2_PORT6),
+ GPIO_FN(BBIF2_TSCK2_PORT59),
+
+ GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
+ GPIO_FN(BBIF2_TXD2_PORT183),
+ GPIO_FN(BBIF2_TSCK2_PORT89),
+ GPIO_FN(BBIF2_TSYNC2_PORT184),
+
+ /* BSC / FLCTL / PCMCIA */
+ GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4),
+ GPIO_FN(CS5B), GPIO_FN(CS6A),
+ GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
+ GPIO_FN(CS5A_PORT19),
+ GPIO_FN(IOIS16), /* ? */
+
+ GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3),
+ GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */
+ GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9),
+ GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13),
+ GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17),
+ GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21),
+ GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25),
+ GPIO_FN(A26),
+
+ GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */
+ GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */
+ GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */
+ GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */
+ GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */
+ GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */
+ GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */
+ GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */
+ GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19),
+ GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23),
+ GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27),
+ GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31),
+
+ GPIO_FN(WE0_FWE), /* share with FLCTL */
+ GPIO_FN(WE1),
+ GPIO_FN(WE2_ICIORD), /* share with PCMCIA */
+ GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */
+ GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR),
+ GPIO_FN(RD_FSC), /* share with FLCTL */
+ GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
+ GPIO_FN(WAIT_PORT90),
+
+ GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */
+
+ /* IRDA */
+ GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT),
+
+ /* ATAPI */
+ GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2),
+ GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5),
+ GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8),
+ GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11),
+ GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14),
+ GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1),
+ GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1),
+ GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY),
+ GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION),
+ GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ),
+
+ /* RMII */
+ GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0),
+ GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0),
+ GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO),
+ GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */
+
+ /* GEther */
+ GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0),
+ GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3),
+ GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */
+ GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */
+ GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK),
+ GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1),
+ GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3),
+ GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */
+ GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */
+ GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC),
+ GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT),
+ GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK),
+
+ /* DMA0 */
+ GPIO_FN(DREQ0), GPIO_FN(DACK0),
+
+ /* DMA1 */
+ GPIO_FN(DREQ1), GPIO_FN(DACK1),
+
+ /* SYSC */
+ GPIO_FN(RESETOUTS),
+
+ /* IRREM */
+ GPIO_FN(IROUT),
+
+ /* LCDC */
+ GPIO_FN(LCDC0_SELECT),
+ GPIO_FN(LCDC1_SELECT),
+
+ /* SDENC */
+ GPIO_FN(SDENC_CPG),
+ GPIO_FN(SDENC_DV_CLKI),
+
+ /* SYSC */
+ GPIO_FN(RESETP_PULLUP),
+ GPIO_FN(RESETP_PLAIN),
+
+ /* DEBUG */
+ GPIO_FN(EDEBGREQ_PULLDOWN),
+ GPIO_FN(EDEBGREQ_PULLUP),
+
+ GPIO_FN(TRACEAUD_FROM_VIO),
+ GPIO_FN(TRACEAUD_FROM_LCDC0),
+ GPIO_FN(TRACEAUD_FROM_MEMC),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ PORTCR(0, 0xe6050000), /* PORT0CR */
+ PORTCR(1, 0xe6050001), /* PORT1CR */
+ PORTCR(2, 0xe6050002), /* PORT2CR */
+ PORTCR(3, 0xe6050003), /* PORT3CR */
+ PORTCR(4, 0xe6050004), /* PORT4CR */
+ PORTCR(5, 0xe6050005), /* PORT5CR */
+ PORTCR(6, 0xe6050006), /* PORT6CR */
+ PORTCR(7, 0xe6050007), /* PORT7CR */
+ PORTCR(8, 0xe6050008), /* PORT8CR */
+ PORTCR(9, 0xe6050009), /* PORT9CR */
+ PORTCR(10, 0xe605000a), /* PORT10CR */
+ PORTCR(11, 0xe605000b), /* PORT11CR */
+ PORTCR(12, 0xe605000c), /* PORT12CR */
+ PORTCR(13, 0xe605000d), /* PORT13CR */
+ PORTCR(14, 0xe605000e), /* PORT14CR */
+ PORTCR(15, 0xe605000f), /* PORT15CR */
+ PORTCR(16, 0xe6050010), /* PORT16CR */
+ PORTCR(17, 0xe6050011), /* PORT17CR */
+ PORTCR(18, 0xe6050012), /* PORT18CR */
+ PORTCR(19, 0xe6050013), /* PORT19CR */
+ PORTCR(20, 0xe6050014), /* PORT20CR */
+ PORTCR(21, 0xe6050015), /* PORT21CR */
+ PORTCR(22, 0xe6050016), /* PORT22CR */
+ PORTCR(23, 0xe6050017), /* PORT23CR */
+ PORTCR(24, 0xe6050018), /* PORT24CR */
+ PORTCR(25, 0xe6050019), /* PORT25CR */
+ PORTCR(26, 0xe605001a), /* PORT26CR */
+ PORTCR(27, 0xe605001b), /* PORT27CR */
+ PORTCR(28, 0xe605001c), /* PORT28CR */
+ PORTCR(29, 0xe605001d), /* PORT29CR */
+ PORTCR(30, 0xe605001e), /* PORT30CR */
+ PORTCR(31, 0xe605001f), /* PORT31CR */
+ PORTCR(32, 0xe6050020), /* PORT32CR */
+ PORTCR(33, 0xe6050021), /* PORT33CR */
+ PORTCR(34, 0xe6050022), /* PORT34CR */
+ PORTCR(35, 0xe6050023), /* PORT35CR */
+ PORTCR(36, 0xe6050024), /* PORT36CR */
+ PORTCR(37, 0xe6050025), /* PORT37CR */
+ PORTCR(38, 0xe6050026), /* PORT38CR */
+ PORTCR(39, 0xe6050027), /* PORT39CR */
+ PORTCR(40, 0xe6050028), /* PORT40CR */
+ PORTCR(41, 0xe6050029), /* PORT41CR */
+ PORTCR(42, 0xe605002a), /* PORT42CR */
+ PORTCR(43, 0xe605002b), /* PORT43CR */
+ PORTCR(44, 0xe605002c), /* PORT44CR */
+ PORTCR(45, 0xe605002d), /* PORT45CR */
+ PORTCR(46, 0xe605002e), /* PORT46CR */
+ PORTCR(47, 0xe605002f), /* PORT47CR */
+ PORTCR(48, 0xe6050030), /* PORT48CR */
+ PORTCR(49, 0xe6050031), /* PORT49CR */
+ PORTCR(50, 0xe6050032), /* PORT50CR */
+ PORTCR(51, 0xe6050033), /* PORT51CR */
+ PORTCR(52, 0xe6050034), /* PORT52CR */
+ PORTCR(53, 0xe6050035), /* PORT53CR */
+ PORTCR(54, 0xe6050036), /* PORT54CR */
+ PORTCR(55, 0xe6050037), /* PORT55CR */
+ PORTCR(56, 0xe6050038), /* PORT56CR */
+ PORTCR(57, 0xe6050039), /* PORT57CR */
+ PORTCR(58, 0xe605003a), /* PORT58CR */
+ PORTCR(59, 0xe605003b), /* PORT59CR */
+ PORTCR(60, 0xe605003c), /* PORT60CR */
+ PORTCR(61, 0xe605003d), /* PORT61CR */
+ PORTCR(62, 0xe605003e), /* PORT62CR */
+ PORTCR(63, 0xe605003f), /* PORT63CR */
+ PORTCR(64, 0xe6050040), /* PORT64CR */
+ PORTCR(65, 0xe6050041), /* PORT65CR */
+ PORTCR(66, 0xe6050042), /* PORT66CR */
+ PORTCR(67, 0xe6050043), /* PORT67CR */
+ PORTCR(68, 0xe6050044), /* PORT68CR */
+ PORTCR(69, 0xe6050045), /* PORT69CR */
+ PORTCR(70, 0xe6050046), /* PORT70CR */
+ PORTCR(71, 0xe6050047), /* PORT71CR */
+ PORTCR(72, 0xe6050048), /* PORT72CR */
+ PORTCR(73, 0xe6050049), /* PORT73CR */
+ PORTCR(74, 0xe605004a), /* PORT74CR */
+ PORTCR(75, 0xe605004b), /* PORT75CR */
+ PORTCR(76, 0xe605004c), /* PORT76CR */
+ PORTCR(77, 0xe605004d), /* PORT77CR */
+ PORTCR(78, 0xe605004e), /* PORT78CR */
+ PORTCR(79, 0xe605004f), /* PORT79CR */
+ PORTCR(80, 0xe6050050), /* PORT80CR */
+ PORTCR(81, 0xe6050051), /* PORT81CR */
+ PORTCR(82, 0xe6050052), /* PORT82CR */
+ PORTCR(83, 0xe6050053), /* PORT83CR */
+
+ PORTCR(84, 0xe6051054), /* PORT84CR */
+ PORTCR(85, 0xe6051055), /* PORT85CR */
+ PORTCR(86, 0xe6051056), /* PORT86CR */
+ PORTCR(87, 0xe6051057), /* PORT87CR */
+ PORTCR(88, 0xe6051058), /* PORT88CR */
+ PORTCR(89, 0xe6051059), /* PORT89CR */
+ PORTCR(90, 0xe605105a), /* PORT90CR */
+ PORTCR(91, 0xe605105b), /* PORT91CR */
+ PORTCR(92, 0xe605105c), /* PORT92CR */
+ PORTCR(93, 0xe605105d), /* PORT93CR */
+ PORTCR(94, 0xe605105e), /* PORT94CR */
+ PORTCR(95, 0xe605105f), /* PORT95CR */
+ PORTCR(96, 0xe6051060), /* PORT96CR */
+ PORTCR(97, 0xe6051061), /* PORT97CR */
+ PORTCR(98, 0xe6051062), /* PORT98CR */
+ PORTCR(99, 0xe6051063), /* PORT99CR */
+ PORTCR(100, 0xe6051064), /* PORT100CR */
+ PORTCR(101, 0xe6051065), /* PORT101CR */
+ PORTCR(102, 0xe6051066), /* PORT102CR */
+ PORTCR(103, 0xe6051067), /* PORT103CR */
+ PORTCR(104, 0xe6051068), /* PORT104CR */
+ PORTCR(105, 0xe6051069), /* PORT105CR */
+ PORTCR(106, 0xe605106a), /* PORT106CR */
+ PORTCR(107, 0xe605106b), /* PORT107CR */
+ PORTCR(108, 0xe605106c), /* PORT108CR */
+ PORTCR(109, 0xe605106d), /* PORT109CR */
+ PORTCR(110, 0xe605106e), /* PORT110CR */
+ PORTCR(111, 0xe605106f), /* PORT111CR */
+ PORTCR(112, 0xe6051070), /* PORT112CR */
+ PORTCR(113, 0xe6051071), /* PORT113CR */
+ PORTCR(114, 0xe6051072), /* PORT114CR */
+
+ PORTCR(115, 0xe6052073), /* PORT115CR */
+ PORTCR(116, 0xe6052074), /* PORT116CR */
+ PORTCR(117, 0xe6052075), /* PORT117CR */
+ PORTCR(118, 0xe6052076), /* PORT118CR */
+ PORTCR(119, 0xe6052077), /* PORT119CR */
+ PORTCR(120, 0xe6052078), /* PORT120CR */
+ PORTCR(121, 0xe6052079), /* PORT121CR */
+ PORTCR(122, 0xe605207a), /* PORT122CR */
+ PORTCR(123, 0xe605207b), /* PORT123CR */
+ PORTCR(124, 0xe605207c), /* PORT124CR */
+ PORTCR(125, 0xe605207d), /* PORT125CR */
+ PORTCR(126, 0xe605207e), /* PORT126CR */
+ PORTCR(127, 0xe605207f), /* PORT127CR */
+ PORTCR(128, 0xe6052080), /* PORT128CR */
+ PORTCR(129, 0xe6052081), /* PORT129CR */
+ PORTCR(130, 0xe6052082), /* PORT130CR */
+ PORTCR(131, 0xe6052083), /* PORT131CR */
+ PORTCR(132, 0xe6052084), /* PORT132CR */
+ PORTCR(133, 0xe6052085), /* PORT133CR */
+ PORTCR(134, 0xe6052086), /* PORT134CR */
+ PORTCR(135, 0xe6052087), /* PORT135CR */
+ PORTCR(136, 0xe6052088), /* PORT136CR */
+ PORTCR(137, 0xe6052089), /* PORT137CR */
+ PORTCR(138, 0xe605208a), /* PORT138CR */
+ PORTCR(139, 0xe605208b), /* PORT139CR */
+ PORTCR(140, 0xe605208c), /* PORT140CR */
+ PORTCR(141, 0xe605208d), /* PORT141CR */
+ PORTCR(142, 0xe605208e), /* PORT142CR */
+ PORTCR(143, 0xe605208f), /* PORT143CR */
+ PORTCR(144, 0xe6052090), /* PORT144CR */
+ PORTCR(145, 0xe6052091), /* PORT145CR */
+ PORTCR(146, 0xe6052092), /* PORT146CR */
+ PORTCR(147, 0xe6052093), /* PORT147CR */
+ PORTCR(148, 0xe6052094), /* PORT148CR */
+ PORTCR(149, 0xe6052095), /* PORT149CR */
+ PORTCR(150, 0xe6052096), /* PORT150CR */
+ PORTCR(151, 0xe6052097), /* PORT151CR */
+ PORTCR(152, 0xe6052098), /* PORT152CR */
+ PORTCR(153, 0xe6052099), /* PORT153CR */
+ PORTCR(154, 0xe605209a), /* PORT154CR */
+ PORTCR(155, 0xe605209b), /* PORT155CR */
+ PORTCR(156, 0xe605209c), /* PORT156CR */
+ PORTCR(157, 0xe605209d), /* PORT157CR */
+ PORTCR(158, 0xe605209e), /* PORT158CR */
+ PORTCR(159, 0xe605209f), /* PORT159CR */
+ PORTCR(160, 0xe60520a0), /* PORT160CR */
+ PORTCR(161, 0xe60520a1), /* PORT161CR */
+ PORTCR(162, 0xe60520a2), /* PORT162CR */
+ PORTCR(163, 0xe60520a3), /* PORT163CR */
+ PORTCR(164, 0xe60520a4), /* PORT164CR */
+ PORTCR(165, 0xe60520a5), /* PORT165CR */
+ PORTCR(166, 0xe60520a6), /* PORT166CR */
+ PORTCR(167, 0xe60520a7), /* PORT167CR */
+ PORTCR(168, 0xe60520a8), /* PORT168CR */
+ PORTCR(169, 0xe60520a9), /* PORT169CR */
+ PORTCR(170, 0xe60520aa), /* PORT170CR */
+ PORTCR(171, 0xe60520ab), /* PORT171CR */
+ PORTCR(172, 0xe60520ac), /* PORT172CR */
+ PORTCR(173, 0xe60520ad), /* PORT173CR */
+ PORTCR(174, 0xe60520ae), /* PORT174CR */
+ PORTCR(175, 0xe60520af), /* PORT175CR */
+ PORTCR(176, 0xe60520b0), /* PORT176CR */
+ PORTCR(177, 0xe60520b1), /* PORT177CR */
+ PORTCR(178, 0xe60520b2), /* PORT178CR */
+ PORTCR(179, 0xe60520b3), /* PORT179CR */
+ PORTCR(180, 0xe60520b4), /* PORT180CR */
+ PORTCR(181, 0xe60520b5), /* PORT181CR */
+ PORTCR(182, 0xe60520b6), /* PORT182CR */
+ PORTCR(183, 0xe60520b7), /* PORT183CR */
+ PORTCR(184, 0xe60520b8), /* PORT184CR */
+ PORTCR(185, 0xe60520b9), /* PORT185CR */
+ PORTCR(186, 0xe60520ba), /* PORT186CR */
+ PORTCR(187, 0xe60520bb), /* PORT187CR */
+ PORTCR(188, 0xe60520bc), /* PORT188CR */
+ PORTCR(189, 0xe60520bd), /* PORT189CR */
+ PORTCR(190, 0xe60520be), /* PORT190CR */
+ PORTCR(191, 0xe60520bf), /* PORT191CR */
+ PORTCR(192, 0xe60520c0), /* PORT192CR */
+ PORTCR(193, 0xe60520c1), /* PORT193CR */
+ PORTCR(194, 0xe60520c2), /* PORT194CR */
+ PORTCR(195, 0xe60520c3), /* PORT195CR */
+ PORTCR(196, 0xe60520c4), /* PORT196CR */
+ PORTCR(197, 0xe60520c5), /* PORT197CR */
+ PORTCR(198, 0xe60520c6), /* PORT198CR */
+ PORTCR(199, 0xe60520c7), /* PORT199CR */
+ PORTCR(200, 0xe60520c8), /* PORT200CR */
+ PORTCR(201, 0xe60520c9), /* PORT201CR */
+ PORTCR(202, 0xe60520ca), /* PORT202CR */
+ PORTCR(203, 0xe60520cb), /* PORT203CR */
+ PORTCR(204, 0xe60520cc), /* PORT204CR */
+ PORTCR(205, 0xe60520cd), /* PORT205CR */
+ PORTCR(206, 0xe60520ce), /* PORT206CR */
+ PORTCR(207, 0xe60520cf), /* PORT207CR */
+ PORTCR(208, 0xe60520d0), /* PORT208CR */
+ PORTCR(209, 0xe60520d1), /* PORT209CR */
+
+ PORTCR(210, 0xe60530d2), /* PORT210CR */
+ PORTCR(211, 0xe60530d3), /* PORT211CR */
+
+ { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ MSEL1CR_30_0, MSEL1CR_30_1,
+ MSEL1CR_29_0, MSEL1CR_29_1,
+ MSEL1CR_28_0, MSEL1CR_28_1,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ MSEL1CR_26_0, MSEL1CR_26_1,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ 0, 0, 0, 0,
+ MSEL1CR_9_0, MSEL1CR_9_1,
+ 0, 0,
+ MSEL1CR_7_0, MSEL1CR_7_1,
+ MSEL1CR_6_0, MSEL1CR_6_1,
+ MSEL1CR_5_0, MSEL1CR_5_1,
+ MSEL1CR_4_0, MSEL1CR_4_1,
+ MSEL1CR_3_0, MSEL1CR_3_1,
+ MSEL1CR_2_0, MSEL1CR_2_1,
+ 0, 0,
+ MSEL1CR_0_0, MSEL1CR_0_1,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL3CR_15_0, MSEL3CR_15_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL3CR_6_0, MSEL3CR_6_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ 0, 0, 0, 0,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ 0, 0, 0, 0, 0, 0,
+ MSEL4CR_6_0, MSEL4CR_6_1,
+ 0, 0,
+ MSEL4CR_4_0, MSEL4CR_4_1,
+ 0, 0, 0, 0,
+ MSEL4CR_1_0, MSEL4CR_1_1,
+ 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
+ MSEL5CR_31_0, MSEL5CR_31_1,
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ 0, 0,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ 0, 0,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ 0, 0,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ 0, 0,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ 0, 0,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ 0, 0,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ 0, 0,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ 0, 0,
+ MSEL5CR_8_0, MSEL5CR_8_1,
+ MSEL5CR_7_0, MSEL5CR_7_1,
+ MSEL5CR_6_0, MSEL5CR_6_1,
+ MSEL5CR_5_0, MSEL5CR_5_1,
+ MSEL5CR_4_0, MSEL5CR_4_1,
+ MSEL5CR_3_0, MSEL5CR_3_1,
+ MSEL5CR_2_0, MSEL5CR_2_1,
+ 0, 0,
+ MSEL5CR_0_0, MSEL5CR_0_1,
+ }
+ },
+ { },
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+ { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
+ PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+ PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+ PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+ PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+ PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+ PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+ PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+ PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
+ },
+ { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
+ PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
+ PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
+ PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
+ PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
+ PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
+ PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
+ PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+ PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
+ },
+ { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+ PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+ PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+ PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+ PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
+ },
+ { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
+ PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
+ PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
+ PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+ PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+ PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+ PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+ PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
+ PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+ PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+ PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+ PORT115_DATA, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
+ PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
+ PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
+ PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
+ PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
+ PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
+ PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
+ PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+ PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
+ PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
+ PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
+ PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
+ PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+ PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+ PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+ PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+ PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
+ },
+ { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, PORT209_DATA, PORT208_DATA,
+ PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+ PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+ PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+ PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
+ },
+ { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ PORT211_DATA, PORT210_DATA, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0 }
+ },
+ { },
+};
+
+static struct pinmux_info r8a7740_pinmux_info = {
+ .name = "r8a7740_pfc",
+ .reserved_id = PINMUX_RESERVED,
+ .data = { PINMUX_DATA_BEGIN,
+ PINMUX_DATA_END },
+ .input = { PINMUX_INPUT_BEGIN,
+ PINMUX_INPUT_END },
+ .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
+ PINMUX_INPUT_PULLUP_END },
+ .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN,
+ PINMUX_INPUT_PULLDOWN_END },
+ .output = { PINMUX_OUTPUT_BEGIN,
+ PINMUX_OUTPUT_END },
+ .mark = { PINMUX_MARK_BEGIN,
+ PINMUX_MARK_END },
+ .function = { PINMUX_FUNCTION_BEGIN,
+ PINMUX_FUNCTION_END },
+
+ .first_gpio = GPIO_PORT0,
+ .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
+
+ .gpios = pinmux_gpios,
+ .cfg_regs = pinmux_config_regs,
+ .data_regs = pinmux_data_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+void r8a7740_pinmux_init(void)
+{
+ register_pinmux(&r8a7740_pinmux_info);
+}
diff --git a/arch/arm/mach-shmobile/pfc-r8a7779.c b/arch/arm/mach-shmobile/pfc-r8a7779.c
new file mode 100644
index 000000000000..963532f2b2c4
--- /dev/null
+++ b/arch/arm/mach-shmobile/pfc-r8a7779.c
@@ -0,0 +1,2645 @@
+/*
+ * r8a7779 processor support - PFC hardware block
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/ioport.h>
+#include <mach/r8a7779.h>
+
+#define CPU_32_PORT(fn, pfx, sfx) \
+ PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_1(fn, pfx##31, sfx)
+
+#define CPU_32_PORT6(fn, pfx, sfx) \
+ PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
+ PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
+ PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
+ PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
+ PORT_1(fn, pfx##8, sfx)
+
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ CPU_32_PORT(fn, pfx##_0_, sfx), \
+ CPU_32_PORT(fn, pfx##_1_, sfx), \
+ CPU_32_PORT(fn, pfx##_2_, sfx), \
+ CPU_32_PORT(fn, pfx##_3_, sfx), \
+ CPU_32_PORT(fn, pfx##_4_, sfx), \
+ CPU_32_PORT(fn, pfx##_5_, sfx), \
+ CPU_32_PORT6(fn, pfx##_6_, sfx)
+
+#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
+#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
+ GP##pfx##_IN, GP##pfx##_OUT)
+
+#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
+#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
+
+#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
+#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
+#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
+
+
+#define PORT_10_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
+ PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
+ PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
+ PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
+ PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
+
+#define CPU_32_PORT_REV(fn, pfx, sfx) \
+ PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
+ PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
+ PORT_10_REV(fn, pfx, sfx)
+
+#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
+#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+ FN_##ipsr, FN_##fn)
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ PINMUX_DATA_BEGIN,
+ GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
+ PINMUX_DATA_END,
+
+ PINMUX_INPUT_BEGIN,
+ GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
+ PINMUX_INPUT_END,
+
+ PINMUX_OUTPUT_BEGIN,
+ GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
+
+ /* GPSR0 */
+ FN_AVS1, FN_AVS2, FN_IP0_7_6, FN_A17,
+ FN_A18, FN_A19, FN_IP0_9_8, FN_IP0_11_10,
+ FN_IP0_13_12, FN_IP0_15_14, FN_IP0_18_16, FN_IP0_22_19,
+ FN_IP0_24_23, FN_IP0_25, FN_IP0_27_26, FN_IP1_1_0,
+ FN_IP1_3_2, FN_IP1_6_4, FN_IP1_10_7, FN_IP1_14_11,
+ FN_IP1_18_15, FN_IP0_5_3, FN_IP0_30_28, FN_IP2_18_16,
+ FN_IP2_21_19, FN_IP2_30_28, FN_IP3_2_0, FN_IP3_11_9,
+ FN_IP3_14_12, FN_IP3_22_21, FN_IP3_26_24, FN_IP3_31_29,
+
+ /* GPSR1 */
+ FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5, FN_IP4_10_8,
+ FN_IP4_11, FN_IP4_12, FN_IP4_13, FN_IP4_14,
+ FN_IP4_15, FN_IP4_16, FN_IP4_19_17, FN_IP4_22_20,
+ FN_IP4_23, FN_IP4_24, FN_IP4_25, FN_IP4_26,
+ FN_IP4_27, FN_IP4_28, FN_IP4_31_29, FN_IP5_2_0,
+ FN_IP5_3, FN_IP5_4, FN_IP5_5, FN_IP5_6,
+ FN_IP5_7, FN_IP5_8, FN_IP5_10_9, FN_IP5_12_11,
+ FN_IP5_14_13, FN_IP5_16_15, FN_IP5_20_17, FN_IP5_23_21,
+
+ /* GPSR2 */
+ FN_IP5_27_24, FN_IP8_20, FN_IP8_22_21, FN_IP8_24_23,
+ FN_IP8_27_25, FN_IP8_30_28, FN_IP9_1_0, FN_IP9_3_2,
+ FN_IP9_4, FN_IP9_5, FN_IP9_6, FN_IP9_7,
+ FN_IP9_9_8, FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14,
+ FN_IP9_18_16, FN_IP9_21_19, FN_IP9_23_22, FN_IP9_25_24,
+ FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
+ FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
+ FN_IP10_20_18, FN_IP10_23_21, FN_IP10_25_24, FN_IP10_28_26,
+
+ /* GPSR3 */
+ FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
+ FN_IP11_11_9, FN_IP11_14_12, FN_IP11_17_15, FN_IP11_20_18,
+ FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
+ FN_IP12_5_3, FN_IP12_8_6, FN_IP12_11_9, FN_IP12_14_12,
+ FN_IP12_17_15, FN_IP7_16_15, FN_IP7_18_17, FN_IP7_28_27,
+ FN_IP7_30_29, FN_IP7_20_19, FN_IP7_22_21, FN_IP7_24_23,
+ FN_IP7_26_25, FN_IP1_20_19, FN_IP1_22_21, FN_IP1_24_23,
+ FN_IP5_28, FN_IP5_30_29, FN_IP6_1_0, FN_IP6_3_2,
+
+ /* GPSR4 */
+ FN_IP6_5_4, FN_IP6_7_6, FN_IP6_8, FN_IP6_11_9,
+ FN_IP6_14_12, FN_IP6_17_15, FN_IP6_19_18, FN_IP6_22_20,
+ FN_IP6_24_23, FN_IP6_26_25, FN_IP6_30_29, FN_IP7_1_0,
+ FN_IP7_3_2, FN_IP7_6_4, FN_IP7_9_7, FN_IP7_12_10,
+ FN_IP7_14_13, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
+ FN_IP1_28_25, FN_IP2_3_0, FN_IP8_3_0, FN_IP8_7_4,
+ FN_IP8_11_8, FN_IP8_15_12, FN_PENC0, FN_PENC1,
+ FN_IP0_2_0, FN_IP8_17_16, FN_IP8_18, FN_IP8_19,
+
+ /* GPSR5 */
+ FN_A1, FN_A2, FN_A3, FN_A4,
+ FN_A5, FN_A6, FN_A7, FN_A8,
+ FN_A9, FN_A10, FN_A11, FN_A12,
+ FN_A13, FN_A14, FN_A15, FN_A16,
+ FN_RD, FN_WE0, FN_WE1, FN_EX_WAIT0,
+ FN_IP3_23, FN_IP3_27, FN_IP3_28, FN_IP2_22,
+ FN_IP2_23, FN_IP2_24, FN_IP2_25, FN_IP2_26,
+ FN_IP2_27, FN_IP3_3, FN_IP3_4, FN_IP3_5,
+
+ /* GPSR6 */
+ FN_IP3_6, FN_IP3_7, FN_IP3_8, FN_IP3_15,
+ FN_IP3_16, FN_IP3_17, FN_IP3_18, FN_IP3_19,
+ FN_IP3_20,
+
+ /* IPSR0 */
+ FN_RD_WR, FN_FWE, FN_ATAG0, FN_VI1_R7,
+ FN_HRTS1, FN_RX4_C,
+ FN_CS1_A26, FN_HSPI_TX2, FN_SDSELF_B,
+ FN_CS0, FN_HSPI_CS2_B,
+ FN_CLKOUT, FN_TX3C_IRDA_TX_C, FN_PWM0_B,
+ FN_A25, FN_SD1_WP, FN_MMC0_D5, FN_FD5,
+ FN_HSPI_RX2, FN_VI1_R3, FN_TX5_B, FN_SSI_SDATA7_B,
+ FN_CTS0_B,
+ FN_A24, FN_SD1_CD, FN_MMC0_D4, FN_FD4,
+ FN_HSPI_CS2, FN_VI1_R2, FN_SSI_WS78_B,
+ FN_A23, FN_FCLE, FN_HSPI_CLK2, FN_VI1_R1,
+ FN_A22, FN_RX5_D, FN_HSPI_RX2_B, FN_VI1_R0,
+ FN_A21, FN_SCK5_D, FN_HSPI_CLK2_B,
+ FN_A20, FN_TX5_D, FN_HSPI_TX2_B,
+ FN_A0, FN_SD1_DAT3, FN_MMC0_D3, FN_FD3,
+ FN_BS, FN_SD1_DAT2, FN_MMC0_D2, FN_FD2,
+ FN_ATADIR0, FN_SDSELF, FN_HCTS1, FN_TX4_C,
+ FN_PENC2, FN_SCK0, FN_PWM1, FN_PWMFSW0,
+ FN_SCIF_CLK, FN_TCLK0_C,
+
+ /* IPSR1 */
+ FN_EX_CS0, FN_RX3_C_IRDA_RX_C, FN_MMC0_D6,
+ FN_FD6, FN_EX_CS1, FN_MMC0_D7, FN_FD7,
+ FN_EX_CS2, FN_SD1_CLK, FN_MMC0_CLK, FN_FALE,
+ FN_ATACS00, FN_EX_CS3, FN_SD1_CMD, FN_MMC0_CMD,
+ FN_FRE, FN_ATACS10, FN_VI1_R4, FN_RX5_B,
+ FN_HSCK1, FN_SSI_SDATA8_B, FN_RTS0_B_TANS_B, FN_SSI_SDATA9,
+ FN_EX_CS4, FN_SD1_DAT0, FN_MMC0_D0, FN_FD0,
+ FN_ATARD0, FN_VI1_R5, FN_SCK5_B, FN_HTX1,
+ FN_TX2_E, FN_TX0_B, FN_SSI_SCK9, FN_EX_CS5,
+ FN_SD1_DAT1, FN_MMC0_D1, FN_FD1, FN_ATAWR0,
+ FN_VI1_R6, FN_HRX1, FN_RX2_E, FN_RX0_B,
+ FN_SSI_WS9, FN_MLB_CLK, FN_PWM2, FN_SCK4,
+ FN_MLB_SIG, FN_PWM3, FN_TX4, FN_MLB_DAT,
+ FN_PWM4, FN_RX4, FN_HTX0, FN_TX1,
+ FN_SDATA, FN_CTS0_C, FN_SUB_TCK, FN_CC5_STATE2,
+ FN_CC5_STATE10, FN_CC5_STATE18, FN_CC5_STATE26, FN_CC5_STATE34,
+
+ /* IPSR2 */
+ FN_HRX0, FN_RX1, FN_SCKZ, FN_RTS0_C_TANS_C,
+ FN_SUB_TDI, FN_CC5_STATE3, FN_CC5_STATE11, FN_CC5_STATE19,
+ FN_CC5_STATE27, FN_CC5_STATE35, FN_HSCK0, FN_SCK1,
+ FN_MTS, FN_PWM5, FN_SCK0_C, FN_SSI_SDATA9_B,
+ FN_SUB_TDO, FN_CC5_STATE0, FN_CC5_STATE8, FN_CC5_STATE16,
+ FN_CC5_STATE24, FN_CC5_STATE32, FN_HCTS0, FN_CTS1,
+ FN_STM, FN_PWM0_D, FN_RX0_C, FN_SCIF_CLK_C,
+ FN_SUB_TRST, FN_TCLK1_B, FN_CC5_OSCOUT, FN_HRTS0,
+ FN_RTS1_TANS, FN_MDATA, FN_TX0_C, FN_SUB_TMS,
+ FN_CC5_STATE1, FN_CC5_STATE9, FN_CC5_STATE17, FN_CC5_STATE25,
+ FN_CC5_STATE33, FN_DU0_DR0, FN_LCDOUT0, FN_DREQ0,
+ FN_GPS_CLK_B, FN_AUDATA0, FN_TX5_C, FN_DU0_DR1,
+ FN_LCDOUT1, FN_DACK0, FN_DRACK0, FN_GPS_SIGN_B,
+ FN_AUDATA1, FN_RX5_C, FN_DU0_DR2, FN_LCDOUT2,
+ FN_DU0_DR3, FN_LCDOUT3, FN_DU0_DR4, FN_LCDOUT4,
+ FN_DU0_DR5, FN_LCDOUT5, FN_DU0_DR6, FN_LCDOUT6,
+ FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
+ FN_DREQ1, FN_SCL2, FN_AUDATA2,
+
+ /* IPSR3 */
+ FN_DU0_DG1, FN_LCDOUT9, FN_DACK1, FN_SDA2,
+ FN_AUDATA3, FN_DU0_DG2, FN_LCDOUT10, FN_DU0_DG3,
+ FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12, FN_DU0_DG5,
+ FN_LCDOUT13, FN_DU0_DG6, FN_LCDOUT14, FN_DU0_DG7,
+ FN_LCDOUT15, FN_DU0_DB0, FN_LCDOUT16, FN_EX_WAIT1,
+ FN_SCL1, FN_TCLK1, FN_AUDATA4, FN_DU0_DB1,
+ FN_LCDOUT17, FN_EX_WAIT2, FN_SDA1, FN_GPS_MAG_B,
+ FN_AUDATA5, FN_SCK5_C, FN_DU0_DB2, FN_LCDOUT18,
+ FN_DU0_DB3, FN_LCDOUT19, FN_DU0_DB4, FN_LCDOUT20,
+ FN_DU0_DB5, FN_LCDOUT21, FN_DU0_DB6, FN_LCDOUT22,
+ FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
+ FN_TX3_D_IRDA_TX_D, FN_SCL3_B, FN_DU0_DOTCLKOUT0, FN_QCLK,
+ FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_RX3_D_IRDA_RX_D, FN_SDA3_B,
+ FN_SDA2_C, FN_DACK0_B, FN_DRACK0_B, FN_DU0_EXHSYNC_DU0_HSYNC,
+ FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
+ FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CAN1_TX,
+ FN_TX2_C, FN_SCL2_C, FN_REMOCON,
+
+ /* IPSR4 */
+ FN_DU0_DISP, FN_QPOLA, FN_CAN_CLK_C, FN_SCK2_C,
+ FN_DU0_CDE, FN_QPOLB, FN_CAN1_RX, FN_RX2_C,
+ FN_DREQ0_B, FN_SSI_SCK78_B, FN_SCK0_B, FN_DU1_DR0,
+ FN_VI2_DATA0_VI2_B0, FN_PWM6, FN_SD3_CLK, FN_TX3_E_IRDA_TX_E,
+ FN_AUDCK, FN_PWMFSW0_B, FN_DU1_DR1, FN_VI2_DATA1_VI2_B1,
+ FN_PWM0, FN_SD3_CMD, FN_RX3_E_IRDA_RX_E, FN_AUDSYNC,
+ FN_CTS0_D, FN_DU1_DR2, FN_VI2_G0, FN_DU1_DR3,
+ FN_VI2_G1, FN_DU1_DR4, FN_VI2_G2, FN_DU1_DR5,
+ FN_VI2_G3, FN_DU1_DR6, FN_VI2_G4, FN_DU1_DR7,
+ FN_VI2_G5, FN_DU1_DG0, FN_VI2_DATA2_VI2_B2, FN_SCL1_B,
+ FN_SD3_DAT2, FN_SCK3_E, FN_AUDATA6, FN_TX0_D,
+ FN_DU1_DG1, FN_VI2_DATA3_VI2_B3, FN_SDA1_B, FN_SD3_DAT3,
+ FN_SCK5, FN_AUDATA7, FN_RX0_D, FN_DU1_DG2,
+ FN_VI2_G6, FN_DU1_DG3, FN_VI2_G7, FN_DU1_DG4,
+ FN_VI2_R0, FN_DU1_DG5, FN_VI2_R1, FN_DU1_DG6,
+ FN_VI2_R2, FN_DU1_DG7, FN_VI2_R3, FN_DU1_DB0,
+ FN_VI2_DATA4_VI2_B4, FN_SCL2_B, FN_SD3_DAT0, FN_TX5,
+ FN_SCK0_D,
+
+ /* IPSR5 */
+ FN_DU1_DB1, FN_VI2_DATA5_VI2_B5, FN_SDA2_B, FN_SD3_DAT1,
+ FN_RX5, FN_RTS0_D_TANS_D, FN_DU1_DB2, FN_VI2_R4,
+ FN_DU1_DB3, FN_VI2_R5, FN_DU1_DB4, FN_VI2_R6,
+ FN_DU1_DB5, FN_VI2_R7, FN_DU1_DB6, FN_SCL2_D,
+ FN_DU1_DB7, FN_SDA2_D, FN_DU1_DOTCLKIN, FN_VI2_CLKENB,
+ FN_HSPI_CS1, FN_SCL1_D, FN_DU1_DOTCLKOUT, FN_VI2_FIELD,
+ FN_SDA1_D, FN_DU1_EXHSYNC_DU1_HSYNC, FN_VI2_HSYNC,
+ FN_VI3_HSYNC, FN_DU1_EXVSYNC_DU1_VSYNC, FN_VI2_VSYNC, FN_VI3_VSYNC,
+ FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_VI2_CLK, FN_TX3_B_IRDA_TX_B,
+ FN_SD3_CD, FN_HSPI_TX1, FN_VI1_CLKENB, FN_VI3_CLKENB,
+ FN_AUDIO_CLKC, FN_TX2_D, FN_SPEEDIN, FN_GPS_SIGN_D,
+ FN_DU1_DISP, FN_VI2_DATA6_VI2_B6, FN_TCLK0, FN_QSTVA_B_QVS_B,
+ FN_HSPI_CLK1, FN_SCK2_D, FN_AUDIO_CLKOUT_B, FN_GPS_MAG_D,
+ FN_DU1_CDE, FN_VI2_DATA7_VI2_B7, FN_RX3_B_IRDA_RX_B,
+ FN_SD3_WP, FN_HSPI_RX1, FN_VI1_FIELD, FN_VI3_FIELD,
+ FN_AUDIO_CLKOUT, FN_RX2_D, FN_GPS_CLK_C, FN_GPS_CLK_D,
+ FN_AUDIO_CLKA, FN_CAN_TXCLK, FN_AUDIO_CLKB, FN_USB_OVC2,
+ FN_CAN_DEBUGOUT0, FN_MOUT0,
+
+ /* IPSR6 */
+ FN_SSI_SCK0129, FN_CAN_DEBUGOUT1, FN_MOUT1, FN_SSI_WS0129,
+ FN_CAN_DEBUGOUT2, FN_MOUT2, FN_SSI_SDATA0, FN_CAN_DEBUGOUT3,
+ FN_MOUT5, FN_SSI_SDATA1, FN_CAN_DEBUGOUT4, FN_MOUT6,
+ FN_SSI_SDATA2, FN_CAN_DEBUGOUT5, FN_SSI_SCK34, FN_CAN_DEBUGOUT6,
+ FN_CAN0_TX_B, FN_IERX, FN_SSI_SCK9_C, FN_SSI_WS34,
+ FN_CAN_DEBUGOUT7, FN_CAN0_RX_B, FN_IETX, FN_SSI_WS9_C,
+ FN_SSI_SDATA3, FN_PWM0_C, FN_CAN_DEBUGOUT8, FN_CAN_CLK_B,
+ FN_IECLK, FN_SCIF_CLK_B, FN_TCLK0_B, FN_SSI_SDATA4,
+ FN_CAN_DEBUGOUT9, FN_SSI_SDATA9_C, FN_SSI_SCK5, FN_ADICLK,
+ FN_CAN_DEBUGOUT10, FN_SCK3, FN_TCLK0_D, FN_SSI_WS5,
+ FN_ADICS_SAMP, FN_CAN_DEBUGOUT11, FN_TX3_IRDA_TX, FN_SSI_SDATA5,
+ FN_ADIDATA, FN_CAN_DEBUGOUT12, FN_RX3_IRDA_RX, FN_SSI_SCK6,
+ FN_ADICHS0, FN_CAN0_TX, FN_IERX_B,
+
+ /* IPSR7 */
+ FN_SSI_WS6, FN_ADICHS1, FN_CAN0_RX, FN_IETX_B,
+ FN_SSI_SDATA6, FN_ADICHS2, FN_CAN_CLK, FN_IECLK_B,
+ FN_SSI_SCK78, FN_CAN_DEBUGOUT13, FN_IRQ0_B, FN_SSI_SCK9_B,
+ FN_HSPI_CLK1_C, FN_SSI_WS78, FN_CAN_DEBUGOUT14, FN_IRQ1_B,
+ FN_SSI_WS9_B, FN_HSPI_CS1_C, FN_SSI_SDATA7, FN_CAN_DEBUGOUT15,
+ FN_IRQ2_B, FN_TCLK1_C, FN_HSPI_TX1_C, FN_SSI_SDATA8,
+ FN_VSP, FN_IRQ3_B, FN_HSPI_RX1_C, FN_SD0_CLK,
+ FN_ATACS01, FN_SCK1_B, FN_SD0_CMD, FN_ATACS11,
+ FN_TX1_B, FN_CC5_TDO, FN_SD0_DAT0, FN_ATADIR1,
+ FN_RX1_B, FN_CC5_TRST, FN_SD0_DAT1, FN_ATAG1,
+ FN_SCK2_B, FN_CC5_TMS, FN_SD0_DAT2, FN_ATARD1,
+ FN_TX2_B, FN_CC5_TCK, FN_SD0_DAT3, FN_ATAWR1,
+ FN_RX2_B, FN_CC5_TDI, FN_SD0_CD, FN_DREQ2,
+ FN_RTS1_B_TANS_B, FN_SD0_WP, FN_DACK2, FN_CTS1_B,
+
+ /* IPSR8 */
+ FN_HSPI_CLK0, FN_CTS0, FN_USB_OVC0, FN_AD_CLK,
+ FN_CC5_STATE4, FN_CC5_STATE12, FN_CC5_STATE20, FN_CC5_STATE28,
+ FN_CC5_STATE36, FN_HSPI_CS0, FN_RTS0_TANS, FN_USB_OVC1,
+ FN_AD_DI, FN_CC5_STATE5, FN_CC5_STATE13, FN_CC5_STATE21,
+ FN_CC5_STATE29, FN_CC5_STATE37, FN_HSPI_TX0, FN_TX0,
+ FN_CAN_DEBUG_HW_TRIGGER, FN_AD_DO, FN_CC5_STATE6, FN_CC5_STATE14,
+ FN_CC5_STATE22, FN_CC5_STATE30, FN_CC5_STATE38, FN_HSPI_RX0,
+ FN_RX0, FN_CAN_STEP0, FN_AD_NCS, FN_CC5_STATE7,
+ FN_CC5_STATE15, FN_CC5_STATE23, FN_CC5_STATE31, FN_CC5_STATE39,
+ FN_FMCLK, FN_RDS_CLK, FN_PCMOE, FN_BPFCLK,
+ FN_PCMWE, FN_FMIN, FN_RDS_DATA, FN_VI0_CLK,
+ FN_MMC1_CLK, FN_VI0_CLKENB, FN_TX1_C, FN_HTX1_B,
+ FN_MT1_SYNC, FN_VI0_FIELD, FN_RX1_C, FN_HRX1_B,
+ FN_VI0_HSYNC, FN_VI0_DATA0_B_VI0_B0_B, FN_CTS1_C, FN_TX4_D,
+ FN_MMC1_CMD, FN_HSCK1_B, FN_VI0_VSYNC, FN_VI0_DATA1_B_VI0_B1_B,
+ FN_RTS1_C_TANS_C, FN_RX4_D, FN_PWMFSW0_C,
+
+ /* IPSR9 */
+ FN_VI0_DATA0_VI0_B0, FN_HRTS1_B, FN_MT1_VCXO, FN_VI0_DATA1_VI0_B1,
+ FN_HCTS1_B, FN_MT1_PWM, FN_VI0_DATA2_VI0_B2, FN_MMC1_D0,
+ FN_VI0_DATA3_VI0_B3, FN_MMC1_D1, FN_VI0_DATA4_VI0_B4, FN_MMC1_D2,
+ FN_VI0_DATA5_VI0_B5, FN_MMC1_D3, FN_VI0_DATA6_VI0_B6, FN_MMC1_D4,
+ FN_ARM_TRACEDATA_0, FN_VI0_DATA7_VI0_B7, FN_MMC1_D5,
+ FN_ARM_TRACEDATA_1, FN_VI0_G0, FN_SSI_SCK78_C, FN_IRQ0,
+ FN_ARM_TRACEDATA_2, FN_VI0_G1, FN_SSI_WS78_C, FN_IRQ1,
+ FN_ARM_TRACEDATA_3, FN_VI0_G2, FN_ETH_TXD1, FN_MMC1_D6,
+ FN_ARM_TRACEDATA_4, FN_TS_SPSYNC0, FN_VI0_G3, FN_ETH_CRS_DV,
+ FN_MMC1_D7, FN_ARM_TRACEDATA_5, FN_TS_SDAT0, FN_VI0_G4,
+ FN_ETH_TX_EN, FN_SD2_DAT0_B, FN_ARM_TRACEDATA_6, FN_VI0_G5,
+ FN_ETH_RX_ER, FN_SD2_DAT1_B, FN_ARM_TRACEDATA_7, FN_VI0_G6,
+ FN_ETH_RXD0, FN_SD2_DAT2_B, FN_ARM_TRACEDATA_8, FN_VI0_G7,
+ FN_ETH_RXD1, FN_SD2_DAT3_B, FN_ARM_TRACEDATA_9,
+
+ /* IPSR10 */
+ FN_VI0_R0, FN_SSI_SDATA7_C, FN_SCK1_C, FN_DREQ1_B,
+ FN_ARM_TRACEDATA_10, FN_DREQ0_C, FN_VI0_R1, FN_SSI_SDATA8_C,
+ FN_DACK1_B, FN_ARM_TRACEDATA_11, FN_DACK0_C, FN_DRACK0_C,
+ FN_VI0_R2, FN_ETH_LINK, FN_SD2_CLK_B, FN_IRQ2,
+ FN_ARM_TRACEDATA_12, FN_VI0_R3, FN_ETH_MAGIC, FN_SD2_CMD_B,
+ FN_IRQ3, FN_ARM_TRACEDATA_13, FN_VI0_R4, FN_ETH_REFCLK,
+ FN_SD2_CD_B, FN_HSPI_CLK1_B, FN_ARM_TRACEDATA_14, FN_MT1_CLK,
+ FN_TS_SCK0, FN_VI0_R5, FN_ETH_TXD0, FN_SD2_WP_B, FN_HSPI_CS1_B,
+ FN_ARM_TRACEDATA_15, FN_MT1_D, FN_TS_SDEN0, FN_VI0_R6,
+ FN_ETH_MDC, FN_DREQ2_C, FN_HSPI_TX1_B, FN_TRACECLK,
+ FN_MT1_BEN, FN_PWMFSW0_D, FN_VI0_R7, FN_ETH_MDIO,
+ FN_DACK2_C, FN_HSPI_RX1_B, FN_SCIF_CLK_D, FN_TRACECTL,
+ FN_MT1_PEN, FN_VI1_CLK, FN_SIM_D, FN_SDA3,
+ FN_VI1_HSYNC, FN_VI3_CLK, FN_SSI_SCK4, FN_GPS_SIGN_C,
+ FN_PWMFSW0_E, FN_VI1_VSYNC, FN_AUDIO_CLKOUT_C, FN_SSI_WS4,
+ FN_SIM_CLK, FN_GPS_MAG_C, FN_SPV_TRST, FN_SCL3,
+
+ /* IPSR11 */
+ FN_VI1_DATA0_VI1_B0, FN_SD2_DAT0, FN_SIM_RST, FN_SPV_TCK,
+ FN_ADICLK_B, FN_VI1_DATA1_VI1_B1, FN_SD2_DAT1, FN_MT0_CLK,
+ FN_SPV_TMS, FN_ADICS_B_SAMP_B, FN_VI1_DATA2_VI1_B2, FN_SD2_DAT2,
+ FN_MT0_D, FN_SPVTDI, FN_ADIDATA_B, FN_VI1_DATA3_VI1_B3,
+ FN_SD2_DAT3, FN_MT0_BEN, FN_SPV_TDO, FN_ADICHS0_B,
+ FN_VI1_DATA4_VI1_B4, FN_SD2_CLK, FN_MT0_PEN, FN_SPA_TRST,
+ FN_HSPI_CLK1_D, FN_ADICHS1_B, FN_VI1_DATA5_VI1_B5, FN_SD2_CMD,
+ FN_MT0_SYNC, FN_SPA_TCK, FN_HSPI_CS1_D, FN_ADICHS2_B,
+ FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
+ FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
+ FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
+ FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
+ FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
+ FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
+
+ /* IPSR12 */
+ FN_VI1_G2, FN_VI3_DATA2, FN_SSI_WS1, FN_TS_SPSYNC1,
+ FN_SCK2, FN_HSCK0_B, FN_VI1_G3, FN_VI3_DATA3,
+ FN_SSI_SCK2, FN_TS_SDAT1, FN_SCL1_C, FN_HTX0_B,
+ FN_VI1_G4, FN_VI3_DATA4, FN_SSI_WS2, FN_SDA1_C,
+ FN_SIM_RST_B, FN_HRX0_B, FN_VI1_G5, FN_VI3_DATA5,
+ FN_GPS_CLK, FN_FSE, FN_TX4_B, FN_SIM_D_B,
+ FN_VI1_G6, FN_VI3_DATA6, FN_GPS_SIGN, FN_FRB,
+ FN_RX4_B, FN_SIM_CLK_B, FN_VI1_G7, FN_VI3_DATA7,
+ FN_GPS_MAG, FN_FCE, FN_SCK4_B,
+
+ FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
+ FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
+ FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
+ FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
+ FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
+ FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
+ FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
+ FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
+ FN_SEL_SSI9_0, FN_SEL_SSI9_1, FN_SEL_SSI9_2,
+ FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+ FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+ FN_SEL_VI0_0, FN_SEL_VI0_1,
+ FN_SEL_SD2_0, FN_SEL_SD2_1,
+ FN_SEL_INT3_0, FN_SEL_INT3_1,
+ FN_SEL_INT2_0, FN_SEL_INT2_1,
+ FN_SEL_INT1_0, FN_SEL_INT1_1,
+ FN_SEL_INT0_0, FN_SEL_INT0_1,
+ FN_SEL_IE_0, FN_SEL_IE_1,
+ FN_SEL_EXBUS2_0, FN_SEL_EXBUS2_1, FN_SEL_EXBUS2_2,
+ FN_SEL_EXBUS1_0, FN_SEL_EXBUS1_1,
+ FN_SEL_EXBUS0_0, FN_SEL_EXBUS0_1, FN_SEL_EXBUS0_2,
+
+ FN_SEL_TMU1_0, FN_SEL_TMU1_1, FN_SEL_TMU1_2,
+ FN_SEL_TMU0_0, FN_SEL_TMU0_1, FN_SEL_TMU0_2, FN_SEL_TMU0_3,
+ FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
+ FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+ FN_SEL_CAN0_0, FN_SEL_CAN0_1,
+ FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+ FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
+ FN_SEL_PWMFSW_0, FN_SEL_PWMFSW_1, FN_SEL_PWMFSW_2,
+ FN_SEL_PWMFSW_3, FN_SEL_PWMFSW_4,
+ FN_SEL_ADI_0, FN_SEL_ADI_1,
+ FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
+ FN_SEL_SIM_0, FN_SEL_SIM_1,
+ FN_SEL_HSPI2_0, FN_SEL_HSPI2_1,
+ FN_SEL_HSPI1_0, FN_SEL_HSPI1_1, FN_SEL_HSPI1_2, FN_SEL_HSPI1_3,
+ FN_SEL_I2C3_0, FN_SEL_I2C3_1,
+ FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+ FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+ AVS1_MARK, AVS2_MARK, A17_MARK, A18_MARK,
+ A19_MARK,
+
+ RD_WR_MARK, FWE_MARK, ATAG0_MARK, VI1_R7_MARK,
+ HRTS1_MARK, RX4_C_MARK,
+ CS1_A26_MARK, HSPI_TX2_MARK, SDSELF_B_MARK,
+ CS0_MARK, HSPI_CS2_B_MARK,
+ CLKOUT_MARK, TX3C_IRDA_TX_C_MARK, PWM0_B_MARK,
+ A25_MARK, SD1_WP_MARK, MMC0_D5_MARK, FD5_MARK,
+ HSPI_RX2_MARK, VI1_R3_MARK, TX5_B_MARK, SSI_SDATA7_B_MARK, CTS0_B_MARK,
+ A24_MARK, SD1_CD_MARK, MMC0_D4_MARK, FD4_MARK,
+ HSPI_CS2_MARK, VI1_R2_MARK, SSI_WS78_B_MARK,
+ A23_MARK, FCLE_MARK, HSPI_CLK2_MARK, VI1_R1_MARK,
+ A22_MARK, RX5_D_MARK, HSPI_RX2_B_MARK, VI1_R0_MARK,
+ A21_MARK, SCK5_D_MARK, HSPI_CLK2_B_MARK,
+ A20_MARK, TX5_D_MARK, HSPI_TX2_B_MARK,
+ A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
+ BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
+ ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
+ PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+ SCIF_CLK_MARK, TCLK0_C_MARK,
+
+ EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
+ FD6_MARK, EX_CS1_MARK, MMC0_D7_MARK, FD7_MARK,
+ EX_CS2_MARK, SD1_CLK_MARK, MMC0_CLK_MARK, FALE_MARK,
+ ATACS00_MARK, EX_CS3_MARK, SD1_CMD_MARK, MMC0_CMD_MARK,
+ FRE_MARK, ATACS10_MARK, VI1_R4_MARK, RX5_B_MARK,
+ HSCK1_MARK, SSI_SDATA8_B_MARK, RTS0_B_TANS_B_MARK, SSI_SDATA9_MARK,
+ EX_CS4_MARK, SD1_DAT0_MARK, MMC0_D0_MARK, FD0_MARK,
+ ATARD0_MARK, VI1_R5_MARK, SCK5_B_MARK, HTX1_MARK,
+ TX2_E_MARK, TX0_B_MARK, SSI_SCK9_MARK, EX_CS5_MARK,
+ SD1_DAT1_MARK, MMC0_D1_MARK, FD1_MARK, ATAWR0_MARK,
+ VI1_R6_MARK, HRX1_MARK, RX2_E_MARK, RX0_B_MARK,
+ SSI_WS9_MARK, MLB_CLK_MARK, PWM2_MARK, SCK4_MARK,
+ MLB_SIG_MARK, PWM3_MARK, TX4_MARK, MLB_DAT_MARK,
+ PWM4_MARK, RX4_MARK, HTX0_MARK, TX1_MARK,
+ SDATA_MARK, CTS0_C_MARK, SUB_TCK_MARK, CC5_STATE2_MARK,
+ CC5_STATE10_MARK, CC5_STATE18_MARK, CC5_STATE26_MARK, CC5_STATE34_MARK,
+
+ HRX0_MARK, RX1_MARK, SCKZ_MARK, RTS0_C_TANS_C_MARK,
+ SUB_TDI_MARK, CC5_STATE3_MARK, CC5_STATE11_MARK, CC5_STATE19_MARK,
+ CC5_STATE27_MARK, CC5_STATE35_MARK, HSCK0_MARK, SCK1_MARK,
+ MTS_MARK, PWM5_MARK, SCK0_C_MARK, SSI_SDATA9_B_MARK,
+ SUB_TDO_MARK, CC5_STATE0_MARK, CC5_STATE8_MARK, CC5_STATE16_MARK,
+ CC5_STATE24_MARK, CC5_STATE32_MARK, HCTS0_MARK, CTS1_MARK,
+ STM_MARK, PWM0_D_MARK, RX0_C_MARK, SCIF_CLK_C_MARK,
+ SUB_TRST_MARK, TCLK1_B_MARK, CC5_OSCOUT_MARK, HRTS0_MARK,
+ RTS1_TANS_MARK, MDATA_MARK, TX0_C_MARK, SUB_TMS_MARK,
+ CC5_STATE1_MARK, CC5_STATE9_MARK, CC5_STATE17_MARK, CC5_STATE25_MARK,
+ CC5_STATE33_MARK, DU0_DR0_MARK, LCDOUT0_MARK, DREQ0_MARK,
+ GPS_CLK_B_MARK, AUDATA0_MARK, TX5_C_MARK, DU0_DR1_MARK,
+ LCDOUT1_MARK, DACK0_MARK, DRACK0_MARK, GPS_SIGN_B_MARK,
+ AUDATA1_MARK, RX5_C_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
+ DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
+ DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
+ DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
+ DREQ1_MARK, SCL2_MARK, AUDATA2_MARK,
+
+ DU0_DG1_MARK, LCDOUT9_MARK, DACK1_MARK, SDA2_MARK,
+ AUDATA3_MARK, DU0_DG2_MARK, LCDOUT10_MARK, DU0_DG3_MARK,
+ LCDOUT11_MARK, DU0_DG4_MARK, LCDOUT12_MARK, DU0_DG5_MARK,
+ LCDOUT13_MARK, DU0_DG6_MARK, LCDOUT14_MARK, DU0_DG7_MARK,
+ LCDOUT15_MARK, DU0_DB0_MARK, LCDOUT16_MARK, EX_WAIT1_MARK,
+ SCL1_MARK, TCLK1_MARK, AUDATA4_MARK, DU0_DB1_MARK,
+ LCDOUT17_MARK, EX_WAIT2_MARK, SDA1_MARK, GPS_MAG_B_MARK,
+ AUDATA5_MARK, SCK5_C_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
+ DU0_DB3_MARK, LCDOUT19_MARK, DU0_DB4_MARK, LCDOUT20_MARK,
+ DU0_DB5_MARK, LCDOUT21_MARK, DU0_DB6_MARK, LCDOUT22_MARK,
+ DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
+ TX3_D_IRDA_TX_D_MARK, SCL3_B_MARK, DU0_DOTCLKOUT0_MARK, QCLK_MARK,
+ DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, RX3_D_IRDA_RX_D_MARK, SDA3_B_MARK,
+ SDA2_C_MARK, DACK0_B_MARK, DRACK0_B_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK,
+ QSTH_QHS_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CAN1_TX_MARK,
+ TX2_C_MARK, SCL2_C_MARK, REMOCON_MARK,
+
+ DU0_DISP_MARK, QPOLA_MARK, CAN_CLK_C_MARK, SCK2_C_MARK,
+ DU0_CDE_MARK, QPOLB_MARK, CAN1_RX_MARK, RX2_C_MARK,
+ DREQ0_B_MARK, SSI_SCK78_B_MARK, SCK0_B_MARK, DU1_DR0_MARK,
+ VI2_DATA0_VI2_B0_MARK, PWM6_MARK, SD3_CLK_MARK, TX3_E_IRDA_TX_E_MARK,
+ AUDCK_MARK, PWMFSW0_B_MARK, DU1_DR1_MARK, VI2_DATA1_VI2_B1_MARK,
+ PWM0_MARK, SD3_CMD_MARK, RX3_E_IRDA_RX_E_MARK, AUDSYNC_MARK,
+ CTS0_D_MARK, DU1_DR2_MARK, VI2_G0_MARK, DU1_DR3_MARK,
+ VI2_G1_MARK, DU1_DR4_MARK, VI2_G2_MARK, DU1_DR5_MARK,
+ VI2_G3_MARK, DU1_DR6_MARK, VI2_G4_MARK, DU1_DR7_MARK,
+ VI2_G5_MARK, DU1_DG0_MARK, VI2_DATA2_VI2_B2_MARK, SCL1_B_MARK,
+ SD3_DAT2_MARK, SCK3_E_MARK, AUDATA6_MARK, TX0_D_MARK,
+ DU1_DG1_MARK, VI2_DATA3_VI2_B3_MARK, SDA1_B_MARK, SD3_DAT3_MARK,
+ SCK5_MARK, AUDATA7_MARK, RX0_D_MARK, DU1_DG2_MARK,
+ VI2_G6_MARK, DU1_DG3_MARK, VI2_G7_MARK, DU1_DG4_MARK,
+ VI2_R0_MARK, DU1_DG5_MARK, VI2_R1_MARK, DU1_DG6_MARK,
+ VI2_R2_MARK, DU1_DG7_MARK, VI2_R3_MARK, DU1_DB0_MARK,
+ VI2_DATA4_VI2_B4_MARK, SCL2_B_MARK, SD3_DAT0_MARK, TX5_MARK,
+ SCK0_D_MARK,
+
+ DU1_DB1_MARK, VI2_DATA5_VI2_B5_MARK, SDA2_B_MARK, SD3_DAT1_MARK,
+ RX5_MARK, RTS0_D_TANS_D_MARK, DU1_DB2_MARK, VI2_R4_MARK,
+ DU1_DB3_MARK, VI2_R5_MARK, DU1_DB4_MARK, VI2_R6_MARK,
+ DU1_DB5_MARK, VI2_R7_MARK, DU1_DB6_MARK, SCL2_D_MARK,
+ DU1_DB7_MARK, SDA2_D_MARK, DU1_DOTCLKIN_MARK, VI2_CLKENB_MARK,
+ HSPI_CS1_MARK, SCL1_D_MARK, DU1_DOTCLKOUT_MARK, VI2_FIELD_MARK,
+ SDA1_D_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, VI2_HSYNC_MARK,
+ VI3_HSYNC_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, VI2_VSYNC_MARK,
+ VI3_VSYNC_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, VI2_CLK_MARK,
+ TX3_B_IRDA_TX_B_MARK, SD3_CD_MARK, HSPI_TX1_MARK, VI1_CLKENB_MARK,
+ VI3_CLKENB_MARK, AUDIO_CLKC_MARK, TX2_D_MARK, SPEEDIN_MARK,
+ GPS_SIGN_D_MARK, DU1_DISP_MARK, VI2_DATA6_VI2_B6_MARK, TCLK0_MARK,
+ QSTVA_B_QVS_B_MARK, HSPI_CLK1_MARK, SCK2_D_MARK, AUDIO_CLKOUT_B_MARK,
+ GPS_MAG_D_MARK, DU1_CDE_MARK, VI2_DATA7_VI2_B7_MARK,
+ RX3_B_IRDA_RX_B_MARK, SD3_WP_MARK, HSPI_RX1_MARK, VI1_FIELD_MARK,
+ VI3_FIELD_MARK, AUDIO_CLKOUT_MARK, RX2_D_MARK, GPS_CLK_C_MARK,
+ GPS_CLK_D_MARK, AUDIO_CLKA_MARK, CAN_TXCLK_MARK, AUDIO_CLKB_MARK,
+ USB_OVC2_MARK, CAN_DEBUGOUT0_MARK, MOUT0_MARK,
+
+ SSI_SCK0129_MARK, CAN_DEBUGOUT1_MARK, MOUT1_MARK, SSI_WS0129_MARK,
+ CAN_DEBUGOUT2_MARK, MOUT2_MARK, SSI_SDATA0_MARK, CAN_DEBUGOUT3_MARK,
+ MOUT5_MARK, SSI_SDATA1_MARK, CAN_DEBUGOUT4_MARK, MOUT6_MARK,
+ SSI_SDATA2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK34_MARK,
+ CAN_DEBUGOUT6_MARK, CAN0_TX_B_MARK, IERX_MARK, SSI_SCK9_C_MARK,
+ SSI_WS34_MARK, CAN_DEBUGOUT7_MARK, CAN0_RX_B_MARK, IETX_MARK,
+ SSI_WS9_C_MARK, SSI_SDATA3_MARK, PWM0_C_MARK, CAN_DEBUGOUT8_MARK,
+ CAN_CLK_B_MARK, IECLK_MARK, SCIF_CLK_B_MARK, TCLK0_B_MARK,
+ SSI_SDATA4_MARK, CAN_DEBUGOUT9_MARK, SSI_SDATA9_C_MARK, SSI_SCK5_MARK,
+ ADICLK_MARK, CAN_DEBUGOUT10_MARK, SCK3_MARK, TCLK0_D_MARK,
+ SSI_WS5_MARK, ADICS_SAMP_MARK, CAN_DEBUGOUT11_MARK, TX3_IRDA_TX_MARK,
+ SSI_SDATA5_MARK, ADIDATA_MARK, CAN_DEBUGOUT12_MARK, RX3_IRDA_RX_MARK,
+ SSI_SCK6_MARK, ADICHS0_MARK, CAN0_TX_MARK, IERX_B_MARK,
+
+ SSI_WS6_MARK, ADICHS1_MARK, CAN0_RX_MARK, IETX_B_MARK,
+ SSI_SDATA6_MARK, ADICHS2_MARK, CAN_CLK_MARK, IECLK_B_MARK,
+ SSI_SCK78_MARK, CAN_DEBUGOUT13_MARK, IRQ0_B_MARK, SSI_SCK9_B_MARK,
+ HSPI_CLK1_C_MARK, SSI_WS78_MARK, CAN_DEBUGOUT14_MARK, IRQ1_B_MARK,
+ SSI_WS9_B_MARK, HSPI_CS1_C_MARK, SSI_SDATA7_MARK, CAN_DEBUGOUT15_MARK,
+ IRQ2_B_MARK, TCLK1_C_MARK, HSPI_TX1_C_MARK, SSI_SDATA8_MARK,
+ VSP_MARK, IRQ3_B_MARK, HSPI_RX1_C_MARK, SD0_CLK_MARK,
+ ATACS01_MARK, SCK1_B_MARK, SD0_CMD_MARK, ATACS11_MARK,
+ TX1_B_MARK, CC5_TDO_MARK, SD0_DAT0_MARK, ATADIR1_MARK,
+ RX1_B_MARK, CC5_TRST_MARK, SD0_DAT1_MARK, ATAG1_MARK,
+ SCK2_B_MARK, CC5_TMS_MARK, SD0_DAT2_MARK, ATARD1_MARK,
+ TX2_B_MARK, CC5_TCK_MARK, SD0_DAT3_MARK, ATAWR1_MARK,
+ RX2_B_MARK, CC5_TDI_MARK, SD0_CD_MARK, DREQ2_MARK,
+ RTS1_B_TANS_B_MARK, SD0_WP_MARK, DACK2_MARK, CTS1_B_MARK,
+
+ HSPI_CLK0_MARK, CTS0_MARK, USB_OVC0_MARK, AD_CLK_MARK,
+ CC5_STATE4_MARK, CC5_STATE12_MARK, CC5_STATE20_MARK, CC5_STATE28_MARK,
+ CC5_STATE36_MARK, HSPI_CS0_MARK, RTS0_TANS_MARK, USB_OVC1_MARK,
+ AD_DI_MARK, CC5_STATE5_MARK, CC5_STATE13_MARK, CC5_STATE21_MARK,
+ CC5_STATE29_MARK, CC5_STATE37_MARK, HSPI_TX0_MARK, TX0_MARK,
+ CAN_DEBUG_HW_TRIGGER_MARK, AD_DO_MARK, CC5_STATE6_MARK,
+ CC5_STATE14_MARK, CC5_STATE22_MARK, CC5_STATE30_MARK,
+ CC5_STATE38_MARK, HSPI_RX0_MARK, RX0_MARK, CAN_STEP0_MARK,
+ AD_NCS_MARK, CC5_STATE7_MARK, CC5_STATE15_MARK, CC5_STATE23_MARK,
+ CC5_STATE31_MARK, CC5_STATE39_MARK, FMCLK_MARK, RDS_CLK_MARK,
+ PCMOE_MARK, BPFCLK_MARK, PCMWE_MARK, FMIN_MARK, RDS_DATA_MARK,
+ VI0_CLK_MARK, MMC1_CLK_MARK, VI0_CLKENB_MARK, TX1_C_MARK, HTX1_B_MARK,
+ MT1_SYNC_MARK, VI0_FIELD_MARK, RX1_C_MARK, HRX1_B_MARK,
+ VI0_HSYNC_MARK, VI0_DATA0_B_VI0_B0_B_MARK, CTS1_C_MARK, TX4_D_MARK,
+ MMC1_CMD_MARK, HSCK1_B_MARK, VI0_VSYNC_MARK, VI0_DATA1_B_VI0_B1_B_MARK,
+ RTS1_C_TANS_C_MARK, RX4_D_MARK, PWMFSW0_C_MARK,
+
+ VI0_DATA0_VI0_B0_MARK, HRTS1_B_MARK, MT1_VCXO_MARK,
+ VI0_DATA1_VI0_B1_MARK, HCTS1_B_MARK, MT1_PWM_MARK,
+ VI0_DATA2_VI0_B2_MARK, MMC1_D0_MARK, VI0_DATA3_VI0_B3_MARK,
+ MMC1_D1_MARK, VI0_DATA4_VI0_B4_MARK, MMC1_D2_MARK,
+ VI0_DATA5_VI0_B5_MARK, MMC1_D3_MARK, VI0_DATA6_VI0_B6_MARK,
+ MMC1_D4_MARK, ARM_TRACEDATA_0_MARK, VI0_DATA7_VI0_B7_MARK,
+ MMC1_D5_MARK, ARM_TRACEDATA_1_MARK, VI0_G0_MARK, SSI_SCK78_C_MARK,
+ IRQ0_MARK, ARM_TRACEDATA_2_MARK, VI0_G1_MARK, SSI_WS78_C_MARK,
+ IRQ1_MARK, ARM_TRACEDATA_3_MARK, VI0_G2_MARK, ETH_TXD1_MARK,
+ MMC1_D6_MARK, ARM_TRACEDATA_4_MARK, TS_SPSYNC0_MARK, VI0_G3_MARK,
+ ETH_CRS_DV_MARK, MMC1_D7_MARK, ARM_TRACEDATA_5_MARK, TS_SDAT0_MARK,
+ VI0_G4_MARK, ETH_TX_EN_MARK, SD2_DAT0_B_MARK, ARM_TRACEDATA_6_MARK,
+ VI0_G5_MARK, ETH_RX_ER_MARK, SD2_DAT1_B_MARK, ARM_TRACEDATA_7_MARK,
+ VI0_G6_MARK, ETH_RXD0_MARK, SD2_DAT2_B_MARK, ARM_TRACEDATA_8_MARK,
+ VI0_G7_MARK, ETH_RXD1_MARK, SD2_DAT3_B_MARK, ARM_TRACEDATA_9_MARK,
+
+ VI0_R0_MARK, SSI_SDATA7_C_MARK, SCK1_C_MARK, DREQ1_B_MARK,
+ ARM_TRACEDATA_10_MARK, DREQ0_C_MARK, VI0_R1_MARK, SSI_SDATA8_C_MARK,
+ DACK1_B_MARK, ARM_TRACEDATA_11_MARK, DACK0_C_MARK, DRACK0_C_MARK,
+ VI0_R2_MARK, ETH_LINK_MARK, SD2_CLK_B_MARK, IRQ2_MARK,
+ ARM_TRACEDATA_12_MARK, VI0_R3_MARK, ETH_MAGIC_MARK, SD2_CMD_B_MARK,
+ IRQ3_MARK, ARM_TRACEDATA_13_MARK, VI0_R4_MARK, ETH_REFCLK_MARK,
+ SD2_CD_B_MARK, HSPI_CLK1_B_MARK, ARM_TRACEDATA_14_MARK, MT1_CLK_MARK,
+ TS_SCK0_MARK, VI0_R5_MARK, ETH_TXD0_MARK, SD2_WP_B_MARK,
+ HSPI_CS1_B_MARK, ARM_TRACEDATA_15_MARK, MT1_D_MARK, TS_SDEN0_MARK,
+ VI0_R6_MARK, ETH_MDC_MARK, DREQ2_C_MARK, HSPI_TX1_B_MARK,
+ TRACECLK_MARK, MT1_BEN_MARK, PWMFSW0_D_MARK, VI0_R7_MARK,
+ ETH_MDIO_MARK, DACK2_C_MARK, HSPI_RX1_B_MARK, SCIF_CLK_D_MARK,
+ TRACECTL_MARK, MT1_PEN_MARK, VI1_CLK_MARK, SIM_D_MARK, SDA3_MARK,
+ VI1_HSYNC_MARK, VI3_CLK_MARK, SSI_SCK4_MARK, GPS_SIGN_C_MARK,
+ PWMFSW0_E_MARK, VI1_VSYNC_MARK, AUDIO_CLKOUT_C_MARK, SSI_WS4_MARK,
+ SIM_CLK_MARK, GPS_MAG_C_MARK, SPV_TRST_MARK, SCL3_MARK,
+
+ VI1_DATA0_VI1_B0_MARK, SD2_DAT0_MARK, SIM_RST_MARK, SPV_TCK_MARK,
+ ADICLK_B_MARK, VI1_DATA1_VI1_B1_MARK, SD2_DAT1_MARK, MT0_CLK_MARK,
+ SPV_TMS_MARK, ADICS_B_SAMP_B_MARK, VI1_DATA2_VI1_B2_MARK,
+ SD2_DAT2_MARK, MT0_D_MARK, SPVTDI_MARK, ADIDATA_B_MARK,
+ VI1_DATA3_VI1_B3_MARK, SD2_DAT3_MARK, MT0_BEN_MARK, SPV_TDO_MARK,
+ ADICHS0_B_MARK, VI1_DATA4_VI1_B4_MARK, SD2_CLK_MARK, MT0_PEN_MARK,
+ SPA_TRST_MARK, HSPI_CLK1_D_MARK, ADICHS1_B_MARK,
+ VI1_DATA5_VI1_B5_MARK, SD2_CMD_MARK, MT0_SYNC_MARK, SPA_TCK_MARK,
+ HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
+ MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
+ SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
+ VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
+ DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
+ VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
+ DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
+
+ VI1_G2_MARK, VI3_DATA2_MARK, SSI_WS1_MARK, TS_SPSYNC1_MARK,
+ SCK2_MARK, HSCK0_B_MARK, VI1_G3_MARK, VI3_DATA3_MARK,
+ SSI_SCK2_MARK, TS_SDAT1_MARK, SCL1_C_MARK, HTX0_B_MARK,
+ VI1_G4_MARK, VI3_DATA4_MARK, SSI_WS2_MARK, SDA1_C_MARK,
+ SIM_RST_B_MARK, HRX0_B_MARK, VI1_G5_MARK, VI3_DATA5_MARK,
+ GPS_CLK_MARK, FSE_MARK, TX4_B_MARK, SIM_D_B_MARK,
+ VI1_G6_MARK, VI3_DATA6_MARK, GPS_SIGN_MARK, FRB_MARK,
+ RX4_B_MARK, SIM_CLK_B_MARK, VI1_G7_MARK, VI3_DATA7_MARK,
+ GPS_MAG_MARK, FCE_MARK, SCK4_B_MARK,
+ PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+ PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+ PINMUX_DATA(AVS1_MARK, FN_AVS1),
+ PINMUX_DATA(AVS1_MARK, FN_AVS1),
+ PINMUX_DATA(A17_MARK, FN_A17),
+ PINMUX_DATA(A18_MARK, FN_A18),
+ PINMUX_DATA(A19_MARK, FN_A19),
+
+ PINMUX_IPSR_DATA(IP0_2_0, PENC2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
+ PINMUX_IPSR_DATA(IP0_2_0, PWM1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, PWMFSW0, SEL_PWMFSW_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCIF_CLK, SEL_SCIF_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_2_0, TCLK0_C, SEL_TMU0_2),
+ PINMUX_IPSR_DATA(IP0_5_3, BS),
+ PINMUX_IPSR_DATA(IP0_5_3, SD1_DAT2),
+ PINMUX_IPSR_DATA(IP0_5_3, MMC0_D2),
+ PINMUX_IPSR_DATA(IP0_5_3, FD2),
+ PINMUX_IPSR_DATA(IP0_5_3, ATADIR0),
+ PINMUX_IPSR_DATA(IP0_5_3, SDSELF),
+ PINMUX_IPSR_MODSEL_DATA(IP0_5_3, HCTS1, SEL_HSCIF1_0),
+ PINMUX_IPSR_DATA(IP0_5_3, TX4_C),
+ PINMUX_IPSR_DATA(IP0_7_6, A0),
+ PINMUX_IPSR_DATA(IP0_7_6, SD1_DAT3),
+ PINMUX_IPSR_DATA(IP0_7_6, MMC0_D3),
+ PINMUX_IPSR_DATA(IP0_7_6, FD3),
+ PINMUX_IPSR_DATA(IP0_9_8, A20),
+ PINMUX_IPSR_DATA(IP0_9_8, TX5_D),
+ PINMUX_IPSR_DATA(IP0_9_8, HSPI_TX2_B),
+ PINMUX_IPSR_DATA(IP0_11_10, A21),
+ PINMUX_IPSR_MODSEL_DATA(IP0_11_10, SCK5_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MODSEL_DATA(IP0_11_10, HSPI_CLK2_B, SEL_HSPI2_1),
+ PINMUX_IPSR_DATA(IP0_13_12, A22),
+ PINMUX_IPSR_MODSEL_DATA(IP0_13_12, RX5_D, SEL_SCIF5_3),
+ PINMUX_IPSR_MODSEL_DATA(IP0_13_12, HSPI_RX2_B, SEL_HSPI2_1),
+ PINMUX_IPSR_DATA(IP0_13_12, VI1_R0),
+ PINMUX_IPSR_DATA(IP0_15_14, A23),
+ PINMUX_IPSR_DATA(IP0_15_14, FCLE),
+ PINMUX_IPSR_MODSEL_DATA(IP0_15_14, HSPI_CLK2, SEL_HSPI2_0),
+ PINMUX_IPSR_DATA(IP0_15_14, VI1_R1),
+ PINMUX_IPSR_DATA(IP0_18_16, A24),
+ PINMUX_IPSR_DATA(IP0_18_16, SD1_CD),
+ PINMUX_IPSR_DATA(IP0_18_16, MMC0_D4),
+ PINMUX_IPSR_DATA(IP0_18_16, FD4),
+ PINMUX_IPSR_MODSEL_DATA(IP0_18_16, HSPI_CS2, SEL_HSPI2_0),
+ PINMUX_IPSR_DATA(IP0_18_16, VI1_R2),
+ PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SSI_WS78_B, SEL_SSI7_1),
+ PINMUX_IPSR_DATA(IP0_22_19, A25),
+ PINMUX_IPSR_DATA(IP0_22_19, SD1_WP),
+ PINMUX_IPSR_DATA(IP0_22_19, MMC0_D5),
+ PINMUX_IPSR_DATA(IP0_22_19, FD5),
+ PINMUX_IPSR_MODSEL_DATA(IP0_22_19, HSPI_RX2, SEL_HSPI2_0),
+ PINMUX_IPSR_DATA(IP0_22_19, VI1_R3),
+ PINMUX_IPSR_DATA(IP0_22_19, TX5_B),
+ PINMUX_IPSR_MODSEL_DATA(IP0_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+ PINMUX_IPSR_MODSEL_DATA(IP0_22_19, CTS0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_DATA(IP0_24_23, CLKOUT),
+ PINMUX_IPSR_DATA(IP0_24_23, TX3C_IRDA_TX_C),
+ PINMUX_IPSR_DATA(IP0_24_23, PWM0_B),
+ PINMUX_IPSR_DATA(IP0_25, CS0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_25, HSPI_CS2_B, SEL_HSPI2_1),
+ PINMUX_IPSR_DATA(IP0_27_26, CS1_A26),
+ PINMUX_IPSR_DATA(IP0_27_26, HSPI_TX2),
+ PINMUX_IPSR_DATA(IP0_27_26, SDSELF_B),
+ PINMUX_IPSR_DATA(IP0_30_28, RD_WR),
+ PINMUX_IPSR_DATA(IP0_30_28, FWE),
+ PINMUX_IPSR_DATA(IP0_30_28, ATAG0),
+ PINMUX_IPSR_DATA(IP0_30_28, VI1_R7),
+ PINMUX_IPSR_MODSEL_DATA(IP0_30_28, HRTS1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP0_30_28, RX4_C, SEL_SCIF4_2),
+
+ PINMUX_IPSR_DATA(IP1_1_0, EX_CS0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_1_0, RX3_C_IRDA_RX_C, SEL_SCIF3_2),
+ PINMUX_IPSR_DATA(IP1_1_0, MMC0_D6),
+ PINMUX_IPSR_DATA(IP1_1_0, FD6),
+ PINMUX_IPSR_DATA(IP1_3_2, EX_CS1),
+ PINMUX_IPSR_DATA(IP1_3_2, MMC0_D7),
+ PINMUX_IPSR_DATA(IP1_3_2, FD7),
+ PINMUX_IPSR_DATA(IP1_6_4, EX_CS2),
+ PINMUX_IPSR_DATA(IP1_6_4, SD1_CLK),
+ PINMUX_IPSR_DATA(IP1_6_4, MMC0_CLK),
+ PINMUX_IPSR_DATA(IP1_6_4, FALE),
+ PINMUX_IPSR_DATA(IP1_6_4, ATACS00),
+ PINMUX_IPSR_DATA(IP1_10_7, EX_CS3),
+ PINMUX_IPSR_DATA(IP1_10_7, SD1_CMD),
+ PINMUX_IPSR_DATA(IP1_10_7, MMC0_CMD),
+ PINMUX_IPSR_DATA(IP1_10_7, FRE),
+ PINMUX_IPSR_DATA(IP1_10_7, ATACS10),
+ PINMUX_IPSR_DATA(IP1_10_7, VI1_R4),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RX5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_7, HSCK1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA8_B, SEL_SSI8_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_7, RTS0_B_TANS_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_10_7, SSI_SDATA9, SEL_SSI9_0),
+ PINMUX_IPSR_DATA(IP1_14_11, EX_CS4),
+ PINMUX_IPSR_DATA(IP1_14_11, SD1_DAT0),
+ PINMUX_IPSR_DATA(IP1_14_11, MMC0_D0),
+ PINMUX_IPSR_DATA(IP1_14_11, FD0),
+ PINMUX_IPSR_DATA(IP1_14_11, ATARD0),
+ PINMUX_IPSR_DATA(IP1_14_11, VI1_R5),
+ PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SCK5_B, SEL_SCIF5_1),
+ PINMUX_IPSR_DATA(IP1_14_11, HTX1),
+ PINMUX_IPSR_DATA(IP1_14_11, TX2_E),
+ PINMUX_IPSR_DATA(IP1_14_11, TX0_B),
+ PINMUX_IPSR_MODSEL_DATA(IP1_14_11, SSI_SCK9, SEL_SSI9_0),
+ PINMUX_IPSR_DATA(IP1_18_15, EX_CS5),
+ PINMUX_IPSR_DATA(IP1_18_15, SD1_DAT1),
+ PINMUX_IPSR_DATA(IP1_18_15, MMC0_D1),
+ PINMUX_IPSR_DATA(IP1_18_15, FD1),
+ PINMUX_IPSR_DATA(IP1_18_15, ATAWR0),
+ PINMUX_IPSR_DATA(IP1_18_15, VI1_R6),
+ PINMUX_IPSR_MODSEL_DATA(IP1_18_15, HRX1, SEL_HSCIF1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX2_E, SEL_SCIF2_4),
+ PINMUX_IPSR_MODSEL_DATA(IP1_18_15, RX0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP1_18_15, SSI_WS9, SEL_SSI9_0),
+ PINMUX_IPSR_DATA(IP1_20_19, MLB_CLK),
+ PINMUX_IPSR_DATA(IP1_20_19, PWM2),
+ PINMUX_IPSR_MODSEL_DATA(IP1_20_19, SCK4, SEL_SCIF4_0),
+ PINMUX_IPSR_DATA(IP1_22_21, MLB_SIG),
+ PINMUX_IPSR_DATA(IP1_22_21, PWM3),
+ PINMUX_IPSR_DATA(IP1_22_21, TX4),
+ PINMUX_IPSR_DATA(IP1_24_23, MLB_DAT),
+ PINMUX_IPSR_DATA(IP1_24_23, PWM4),
+ PINMUX_IPSR_MODSEL_DATA(IP1_24_23, RX4, SEL_SCIF4_0),
+ PINMUX_IPSR_DATA(IP1_28_25, HTX0),
+ PINMUX_IPSR_DATA(IP1_28_25, TX1),
+ PINMUX_IPSR_DATA(IP1_28_25, SDATA),
+ PINMUX_IPSR_MODSEL_DATA(IP1_28_25, CTS0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_DATA(IP1_28_25, SUB_TCK),
+ PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE2),
+ PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE10),
+ PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE18),
+ PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE26),
+ PINMUX_IPSR_DATA(IP1_28_25, CC5_STATE34),
+
+ PINMUX_IPSR_MODSEL_DATA(IP2_3_0, HRX0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RX1, SEL_SCIF1_0),
+ PINMUX_IPSR_DATA(IP2_3_0, SCKZ),
+ PINMUX_IPSR_MODSEL_DATA(IP2_3_0, RTS0_C_TANS_C, SEL_SCIF0_2),
+ PINMUX_IPSR_DATA(IP2_3_0, SUB_TDI),
+ PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE3),
+ PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE11),
+ PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE19),
+ PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE27),
+ PINMUX_IPSR_DATA(IP2_3_0, CC5_STATE35),
+ PINMUX_IPSR_MODSEL_DATA(IP2_7_4, HSCK0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK1, SEL_SCIF1_0),
+ PINMUX_IPSR_DATA(IP2_7_4, MTS),
+ PINMUX_IPSR_DATA(IP2_7_4, PWM5),
+ PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SCK0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP2_7_4, SSI_SDATA9_B, SEL_SSI9_1),
+ PINMUX_IPSR_DATA(IP2_7_4, SUB_TDO),
+ PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE0),
+ PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE8),
+ PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE16),
+ PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE24),
+ PINMUX_IPSR_DATA(IP2_7_4, CC5_STATE32),
+ PINMUX_IPSR_MODSEL_DATA(IP2_11_8, HCTS0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_11_8, CTS1, SEL_SCIF1_0),
+ PINMUX_IPSR_DATA(IP2_11_8, STM),
+ PINMUX_IPSR_DATA(IP2_11_8, PWM0_D),
+ PINMUX_IPSR_MODSEL_DATA(IP2_11_8, RX0_C, SEL_SCIF0_2),
+ PINMUX_IPSR_MODSEL_DATA(IP2_11_8, SCIF_CLK_C, SEL_SCIF_2),
+ PINMUX_IPSR_DATA(IP2_11_8, SUB_TRST),
+ PINMUX_IPSR_MODSEL_DATA(IP2_11_8, TCLK1_B, SEL_TMU1_1),
+ PINMUX_IPSR_DATA(IP2_11_8, CC5_OSCOUT),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_12, HRTS0, SEL_HSCIF0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_15_12, RTS1_TANS, SEL_SCIF1_0),
+ PINMUX_IPSR_DATA(IP2_15_12, MDATA),
+ PINMUX_IPSR_DATA(IP2_15_12, TX0_C),
+ PINMUX_IPSR_DATA(IP2_15_12, SUB_TMS),
+ PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE1),
+ PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE9),
+ PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE17),
+ PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE25),
+ PINMUX_IPSR_DATA(IP2_15_12, CC5_STATE33),
+ PINMUX_IPSR_DATA(IP2_18_16, DU0_DR0),
+ PINMUX_IPSR_DATA(IP2_18_16, LCDOUT0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ0, SEL_EXBUS0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_18_16, GPS_CLK_B, SEL_GPS_1),
+ PINMUX_IPSR_DATA(IP2_18_16, AUDATA0),
+ PINMUX_IPSR_DATA(IP2_18_16, TX5_C),
+ PINMUX_IPSR_DATA(IP2_21_19, DU0_DR1),
+ PINMUX_IPSR_DATA(IP2_21_19, LCDOUT1),
+ PINMUX_IPSR_DATA(IP2_21_19, DACK0),
+ PINMUX_IPSR_DATA(IP2_21_19, DRACK0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_21_19, GPS_SIGN_B, SEL_GPS_1),
+ PINMUX_IPSR_DATA(IP2_21_19, AUDATA1),
+ PINMUX_IPSR_MODSEL_DATA(IP2_21_19, RX5_C, SEL_SCIF5_2),
+ PINMUX_IPSR_DATA(IP2_22, DU0_DR2),
+ PINMUX_IPSR_DATA(IP2_22, LCDOUT2),
+ PINMUX_IPSR_DATA(IP2_23, DU0_DR3),
+ PINMUX_IPSR_DATA(IP2_23, LCDOUT3),
+ PINMUX_IPSR_DATA(IP2_24, DU0_DR4),
+ PINMUX_IPSR_DATA(IP2_24, LCDOUT4),
+ PINMUX_IPSR_DATA(IP2_25, DU0_DR5),
+ PINMUX_IPSR_DATA(IP2_25, LCDOUT5),
+ PINMUX_IPSR_DATA(IP2_26, DU0_DR6),
+ PINMUX_IPSR_DATA(IP2_26, LCDOUT6),
+ PINMUX_IPSR_DATA(IP2_27, DU0_DR7),
+ PINMUX_IPSR_DATA(IP2_27, LCDOUT7),
+ PINMUX_IPSR_DATA(IP2_30_28, DU0_DG0),
+ PINMUX_IPSR_DATA(IP2_30_28, LCDOUT8),
+ PINMUX_IPSR_MODSEL_DATA(IP2_30_28, DREQ1, SEL_EXBUS1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP2_30_28, SCL2, SEL_I2C2_0),
+ PINMUX_IPSR_DATA(IP2_30_28, AUDATA2),
+
+ PINMUX_IPSR_DATA(IP3_2_0, DU0_DG1),
+ PINMUX_IPSR_DATA(IP3_2_0, LCDOUT9),
+ PINMUX_IPSR_DATA(IP3_2_0, DACK1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_2_0, SDA2, SEL_I2C2_0),
+ PINMUX_IPSR_DATA(IP3_2_0, AUDATA3),
+ PINMUX_IPSR_DATA(IP3_3, DU0_DG2),
+ PINMUX_IPSR_DATA(IP3_3, LCDOUT10),
+ PINMUX_IPSR_DATA(IP3_4, DU0_DG3),
+ PINMUX_IPSR_DATA(IP3_4, LCDOUT11),
+ PINMUX_IPSR_DATA(IP3_5, DU0_DG4),
+ PINMUX_IPSR_DATA(IP3_5, LCDOUT12),
+ PINMUX_IPSR_DATA(IP3_6, DU0_DG5),
+ PINMUX_IPSR_DATA(IP3_6, LCDOUT13),
+ PINMUX_IPSR_DATA(IP3_7, DU0_DG6),
+ PINMUX_IPSR_DATA(IP3_7, LCDOUT14),
+ PINMUX_IPSR_DATA(IP3_8, DU0_DG7),
+ PINMUX_IPSR_DATA(IP3_8, LCDOUT15),
+ PINMUX_IPSR_DATA(IP3_11_9, DU0_DB0),
+ PINMUX_IPSR_DATA(IP3_11_9, LCDOUT16),
+ PINMUX_IPSR_DATA(IP3_11_9, EX_WAIT1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCL1, SEL_I2C1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_11_9, TCLK1, SEL_TMU1_0),
+ PINMUX_IPSR_DATA(IP3_11_9, AUDATA4),
+ PINMUX_IPSR_DATA(IP3_14_12, DU0_DB1),
+ PINMUX_IPSR_DATA(IP3_14_12, LCDOUT17),
+ PINMUX_IPSR_DATA(IP3_14_12, EX_WAIT2),
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SDA1, SEL_I2C1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, GPS_MAG_B, SEL_GPS_1),
+ PINMUX_IPSR_DATA(IP3_14_12, AUDATA5),
+ PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCK5_C, SEL_SCIF5_2),
+ PINMUX_IPSR_DATA(IP3_15, DU0_DB2),
+ PINMUX_IPSR_DATA(IP3_15, LCDOUT18),
+ PINMUX_IPSR_DATA(IP3_16, DU0_DB3),
+ PINMUX_IPSR_DATA(IP3_16, LCDOUT19),
+ PINMUX_IPSR_DATA(IP3_17, DU0_DB4),
+ PINMUX_IPSR_DATA(IP3_17, LCDOUT20),
+ PINMUX_IPSR_DATA(IP3_18, DU0_DB5),
+ PINMUX_IPSR_DATA(IP3_18, LCDOUT21),
+ PINMUX_IPSR_DATA(IP3_19, DU0_DB6),
+ PINMUX_IPSR_DATA(IP3_19, LCDOUT22),
+ PINMUX_IPSR_DATA(IP3_20, DU0_DB7),
+ PINMUX_IPSR_DATA(IP3_20, LCDOUT23),
+ PINMUX_IPSR_DATA(IP3_22_21, DU0_DOTCLKIN),
+ PINMUX_IPSR_DATA(IP3_22_21, QSTVA_QVS),
+ PINMUX_IPSR_DATA(IP3_22_21, TX3_D_IRDA_TX_D),
+ PINMUX_IPSR_MODSEL_DATA(IP3_22_21, SCL3_B, SEL_I2C3_1),
+ PINMUX_IPSR_DATA(IP3_23, DU0_DOTCLKOUT0),
+ PINMUX_IPSR_DATA(IP3_23, QCLK),
+ PINMUX_IPSR_DATA(IP3_26_24, DU0_DOTCLKOUT1),
+ PINMUX_IPSR_DATA(IP3_26_24, QSTVB_QVE),
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, RX3_D_IRDA_RX_D, SEL_SCIF3_3),
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA3_B, SEL_I2C3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP3_26_24, SDA2_C, SEL_I2C2_2),
+ PINMUX_IPSR_DATA(IP3_26_24, DACK0_B),
+ PINMUX_IPSR_DATA(IP3_26_24, DRACK0_B),
+ PINMUX_IPSR_DATA(IP3_27, DU0_EXHSYNC_DU0_HSYNC),
+ PINMUX_IPSR_DATA(IP3_27, QSTH_QHS),
+ PINMUX_IPSR_DATA(IP3_28, DU0_EXVSYNC_DU0_VSYNC),
+ PINMUX_IPSR_DATA(IP3_28, QSTB_QHE),
+ PINMUX_IPSR_DATA(IP3_31_29, DU0_EXODDF_DU0_ODDF_DISP_CDE),
+ PINMUX_IPSR_DATA(IP3_31_29, QCPV_QDE),
+ PINMUX_IPSR_DATA(IP3_31_29, CAN1_TX),
+ PINMUX_IPSR_DATA(IP3_31_29, TX2_C),
+ PINMUX_IPSR_MODSEL_DATA(IP3_31_29, SCL2_C, SEL_I2C2_2),
+ PINMUX_IPSR_DATA(IP3_31_29, REMOCON),
+
+ PINMUX_IPSR_DATA(IP4_1_0, DU0_DISP),
+ PINMUX_IPSR_DATA(IP4_1_0, QPOLA),
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, CAN_CLK_C, SEL_CANCLK_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCK2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_DATA(IP4_4_2, DU0_CDE),
+ PINMUX_IPSR_DATA(IP4_4_2, QPOLB),
+ PINMUX_IPSR_DATA(IP4_4_2, CAN1_RX),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, RX2_C, SEL_SCIF2_2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, DREQ0_B, SEL_EXBUS0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK78_B, SEL_SSI7_1),
+ PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SCK0_B, SEL_SCIF0_1),
+ PINMUX_IPSR_DATA(IP4_7_5, DU1_DR0),
+ PINMUX_IPSR_DATA(IP4_7_5, VI2_DATA0_VI2_B0),
+ PINMUX_IPSR_DATA(IP4_7_5, PWM6),
+ PINMUX_IPSR_DATA(IP4_7_5, SD3_CLK),
+ PINMUX_IPSR_DATA(IP4_7_5, TX3_E_IRDA_TX_E),
+ PINMUX_IPSR_DATA(IP4_7_5, AUDCK),
+ PINMUX_IPSR_MODSEL_DATA(IP4_7_5, PWMFSW0_B, SEL_PWMFSW_1),
+ PINMUX_IPSR_DATA(IP4_10_8, DU1_DR1),
+ PINMUX_IPSR_DATA(IP4_10_8, VI2_DATA1_VI2_B1),
+ PINMUX_IPSR_DATA(IP4_10_8, PWM0),
+ PINMUX_IPSR_DATA(IP4_10_8, SD3_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP4_10_8, RX3_E_IRDA_RX_E, SEL_SCIF3_4),
+ PINMUX_IPSR_DATA(IP4_10_8, AUDSYNC),
+ PINMUX_IPSR_MODSEL_DATA(IP4_10_8, CTS0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_DATA(IP4_11, DU1_DR2),
+ PINMUX_IPSR_DATA(IP4_11, VI2_G0),
+ PINMUX_IPSR_DATA(IP4_12, DU1_DR3),
+ PINMUX_IPSR_DATA(IP4_12, VI2_G1),
+ PINMUX_IPSR_DATA(IP4_13, DU1_DR4),
+ PINMUX_IPSR_DATA(IP4_13, VI2_G2),
+ PINMUX_IPSR_DATA(IP4_14, DU1_DR5),
+ PINMUX_IPSR_DATA(IP4_14, VI2_G3),
+ PINMUX_IPSR_DATA(IP4_15, DU1_DR6),
+ PINMUX_IPSR_DATA(IP4_15, VI2_G4),
+ PINMUX_IPSR_DATA(IP4_16, DU1_DR7),
+ PINMUX_IPSR_DATA(IP4_16, VI2_G5),
+ PINMUX_IPSR_DATA(IP4_19_17, DU1_DG0),
+ PINMUX_IPSR_DATA(IP4_19_17, VI2_DATA2_VI2_B2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCL1_B, SEL_I2C1_1),
+ PINMUX_IPSR_DATA(IP4_19_17, SD3_DAT2),
+ PINMUX_IPSR_MODSEL_DATA(IP4_19_17, SCK3_E, SEL_SCIF3_4),
+ PINMUX_IPSR_DATA(IP4_19_17, AUDATA6),
+ PINMUX_IPSR_DATA(IP4_19_17, TX0_D),
+ PINMUX_IPSR_DATA(IP4_22_20, DU1_DG1),
+ PINMUX_IPSR_DATA(IP4_22_20, VI2_DATA3_VI2_B3),
+ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SDA1_B, SEL_I2C1_1),
+ PINMUX_IPSR_DATA(IP4_22_20, SD3_DAT3),
+ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, SCK5, SEL_SCIF5_0),
+ PINMUX_IPSR_DATA(IP4_22_20, AUDATA7),
+ PINMUX_IPSR_MODSEL_DATA(IP4_22_20, RX0_D, SEL_SCIF0_3),
+ PINMUX_IPSR_DATA(IP4_23, DU1_DG2),
+ PINMUX_IPSR_DATA(IP4_23, VI2_G6),
+ PINMUX_IPSR_DATA(IP4_24, DU1_DG3),
+ PINMUX_IPSR_DATA(IP4_24, VI2_G7),
+ PINMUX_IPSR_DATA(IP4_25, DU1_DG4),
+ PINMUX_IPSR_DATA(IP4_25, VI2_R0),
+ PINMUX_IPSR_DATA(IP4_26, DU1_DG5),
+ PINMUX_IPSR_DATA(IP4_26, VI2_R1),
+ PINMUX_IPSR_DATA(IP4_27, DU1_DG6),
+ PINMUX_IPSR_DATA(IP4_27, VI2_R2),
+ PINMUX_IPSR_DATA(IP4_28, DU1_DG7),
+ PINMUX_IPSR_DATA(IP4_28, VI2_R3),
+ PINMUX_IPSR_DATA(IP4_31_29, DU1_DB0),
+ PINMUX_IPSR_DATA(IP4_31_29, VI2_DATA4_VI2_B4),
+ PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCL2_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP4_31_29, SD3_DAT0),
+ PINMUX_IPSR_DATA(IP4_31_29, TX5),
+ PINMUX_IPSR_MODSEL_DATA(IP4_31_29, SCK0_D, SEL_SCIF0_3),
+
+ PINMUX_IPSR_DATA(IP5_2_0, DU1_DB1),
+ PINMUX_IPSR_DATA(IP5_2_0, VI2_DATA5_VI2_B5),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, SDA2_B, SEL_I2C2_1),
+ PINMUX_IPSR_DATA(IP5_2_0, SD3_DAT1),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RX5, SEL_SCIF5_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_2_0, RTS0_D_TANS_D, SEL_SCIF0_3),
+ PINMUX_IPSR_DATA(IP5_3, DU1_DB2),
+ PINMUX_IPSR_DATA(IP5_3, VI2_R4),
+ PINMUX_IPSR_DATA(IP5_4, DU1_DB3),
+ PINMUX_IPSR_DATA(IP5_4, VI2_R5),
+ PINMUX_IPSR_DATA(IP5_5, DU1_DB4),
+ PINMUX_IPSR_DATA(IP5_5, VI2_R6),
+ PINMUX_IPSR_DATA(IP5_6, DU1_DB5),
+ PINMUX_IPSR_DATA(IP5_6, VI2_R7),
+ PINMUX_IPSR_DATA(IP5_7, DU1_DB6),
+ PINMUX_IPSR_MODSEL_DATA(IP5_7, SCL2_D, SEL_I2C2_3),
+ PINMUX_IPSR_DATA(IP5_8, DU1_DB7),
+ PINMUX_IPSR_MODSEL_DATA(IP5_8, SDA2_D, SEL_I2C2_3),
+ PINMUX_IPSR_DATA(IP5_10_9, DU1_DOTCLKIN),
+ PINMUX_IPSR_DATA(IP5_10_9, VI2_CLKENB),
+ PINMUX_IPSR_MODSEL_DATA(IP5_10_9, HSPI_CS1, SEL_HSPI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_10_9, SCL1_D, SEL_I2C1_3),
+ PINMUX_IPSR_DATA(IP5_12_11, DU1_DOTCLKOUT),
+ PINMUX_IPSR_DATA(IP5_12_11, VI2_FIELD),
+ PINMUX_IPSR_MODSEL_DATA(IP5_12_11, SDA1_D, SEL_I2C1_3),
+ PINMUX_IPSR_DATA(IP5_14_13, DU1_EXHSYNC_DU1_HSYNC),
+ PINMUX_IPSR_DATA(IP5_14_13, VI2_HSYNC),
+ PINMUX_IPSR_DATA(IP5_14_13, VI3_HSYNC),
+ PINMUX_IPSR_DATA(IP5_16_15, DU1_EXVSYNC_DU1_VSYNC),
+ PINMUX_IPSR_DATA(IP5_16_15, VI2_VSYNC),
+ PINMUX_IPSR_DATA(IP5_16_15, VI3_VSYNC),
+ PINMUX_IPSR_DATA(IP5_20_17, DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ PINMUX_IPSR_DATA(IP5_20_17, VI2_CLK),
+ PINMUX_IPSR_DATA(IP5_20_17, TX3_B_IRDA_TX_B),
+ PINMUX_IPSR_DATA(IP5_20_17, SD3_CD),
+ PINMUX_IPSR_DATA(IP5_20_17, HSPI_TX1),
+ PINMUX_IPSR_DATA(IP5_20_17, VI1_CLKENB),
+ PINMUX_IPSR_DATA(IP5_20_17, VI3_CLKENB),
+ PINMUX_IPSR_DATA(IP5_20_17, AUDIO_CLKC),
+ PINMUX_IPSR_DATA(IP5_20_17, TX2_D),
+ PINMUX_IPSR_DATA(IP5_20_17, SPEEDIN),
+ PINMUX_IPSR_MODSEL_DATA(IP5_20_17, GPS_SIGN_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP5_23_21, DU1_DISP),
+ PINMUX_IPSR_DATA(IP5_23_21, VI2_DATA6_VI2_B6),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, TCLK0, SEL_TMU0_0),
+ PINMUX_IPSR_DATA(IP5_23_21, QSTVA_B_QVS_B),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, HSPI_CLK1, SEL_HSPI1_0),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCK2_D, SEL_SCIF2_3),
+ PINMUX_IPSR_DATA(IP5_23_21, AUDIO_CLKOUT_B),
+ PINMUX_IPSR_MODSEL_DATA(IP5_23_21, GPS_MAG_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP5_27_24, DU1_CDE),
+ PINMUX_IPSR_DATA(IP5_27_24, VI2_DATA7_VI2_B7),
+ PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX3_B_IRDA_RX_B, SEL_SCIF3_1),
+ PINMUX_IPSR_DATA(IP5_27_24, SD3_WP),
+ PINMUX_IPSR_MODSEL_DATA(IP5_27_24, HSPI_RX1, SEL_HSPI1_0),
+ PINMUX_IPSR_DATA(IP5_27_24, VI1_FIELD),
+ PINMUX_IPSR_DATA(IP5_27_24, VI3_FIELD),
+ PINMUX_IPSR_DATA(IP5_27_24, AUDIO_CLKOUT),
+ PINMUX_IPSR_MODSEL_DATA(IP5_27_24, RX2_D, SEL_SCIF2_3),
+ PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP5_27_24, GPS_CLK_D, SEL_GPS_3),
+ PINMUX_IPSR_DATA(IP5_28, AUDIO_CLKA),
+ PINMUX_IPSR_DATA(IP5_28, CAN_TXCLK),
+ PINMUX_IPSR_DATA(IP5_30_29, AUDIO_CLKB),
+ PINMUX_IPSR_DATA(IP5_30_29, USB_OVC2),
+ PINMUX_IPSR_DATA(IP5_30_29, CAN_DEBUGOUT0),
+ PINMUX_IPSR_DATA(IP5_30_29, MOUT0),
+
+ PINMUX_IPSR_DATA(IP6_1_0, SSI_SCK0129),
+ PINMUX_IPSR_DATA(IP6_1_0, CAN_DEBUGOUT1),
+ PINMUX_IPSR_DATA(IP6_1_0, MOUT1),
+ PINMUX_IPSR_DATA(IP6_3_2, SSI_WS0129),
+ PINMUX_IPSR_DATA(IP6_3_2, CAN_DEBUGOUT2),
+ PINMUX_IPSR_DATA(IP6_3_2, MOUT2),
+ PINMUX_IPSR_DATA(IP6_5_4, SSI_SDATA0),
+ PINMUX_IPSR_DATA(IP6_5_4, CAN_DEBUGOUT3),
+ PINMUX_IPSR_DATA(IP6_5_4, MOUT5),
+ PINMUX_IPSR_DATA(IP6_7_6, SSI_SDATA1),
+ PINMUX_IPSR_DATA(IP6_7_6, CAN_DEBUGOUT4),
+ PINMUX_IPSR_DATA(IP6_7_6, MOUT6),
+ PINMUX_IPSR_DATA(IP6_8, SSI_SDATA2),
+ PINMUX_IPSR_DATA(IP6_8, CAN_DEBUGOUT5),
+ PINMUX_IPSR_DATA(IP6_11_9, SSI_SCK34),
+ PINMUX_IPSR_DATA(IP6_11_9, CAN_DEBUGOUT6),
+ PINMUX_IPSR_DATA(IP6_11_9, CAN0_TX_B),
+ PINMUX_IPSR_MODSEL_DATA(IP6_11_9, IERX, SEL_IE_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_11_9, SSI_SCK9_C, SEL_SSI9_2),
+ PINMUX_IPSR_DATA(IP6_14_12, SSI_WS34),
+ PINMUX_IPSR_DATA(IP6_14_12, CAN_DEBUGOUT7),
+ PINMUX_IPSR_MODSEL_DATA(IP6_14_12, CAN0_RX_B, SEL_CAN0_1),
+ PINMUX_IPSR_DATA(IP6_14_12, IETX),
+ PINMUX_IPSR_MODSEL_DATA(IP6_14_12, SSI_WS9_C, SEL_SSI9_2),
+ PINMUX_IPSR_DATA(IP6_17_15, SSI_SDATA3),
+ PINMUX_IPSR_DATA(IP6_17_15, PWM0_C),
+ PINMUX_IPSR_DATA(IP6_17_15, CAN_DEBUGOUT8),
+ PINMUX_IPSR_MODSEL_DATA(IP6_17_15, CAN_CLK_B, SEL_CANCLK_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_17_15, IECLK, SEL_IE_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_17_15, SCIF_CLK_B, SEL_SCIF_1),
+ PINMUX_IPSR_MODSEL_DATA(IP6_17_15, TCLK0_B, SEL_TMU0_1),
+ PINMUX_IPSR_DATA(IP6_19_18, SSI_SDATA4),
+ PINMUX_IPSR_DATA(IP6_19_18, CAN_DEBUGOUT9),
+ PINMUX_IPSR_MODSEL_DATA(IP6_19_18, SSI_SDATA9_C, SEL_SSI9_2),
+ PINMUX_IPSR_DATA(IP6_22_20, SSI_SCK5),
+ PINMUX_IPSR_DATA(IP6_22_20, ADICLK),
+ PINMUX_IPSR_DATA(IP6_22_20, CAN_DEBUGOUT10),
+ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK3, SEL_SCIF3_0),
+ PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TCLK0_D, SEL_TMU0_3),
+ PINMUX_IPSR_DATA(IP6_24_23, SSI_WS5),
+ PINMUX_IPSR_MODSEL_DATA(IP6_24_23, ADICS_SAMP, SEL_ADI_0),
+ PINMUX_IPSR_DATA(IP6_24_23, CAN_DEBUGOUT11),
+ PINMUX_IPSR_DATA(IP6_24_23, TX3_IRDA_TX),
+ PINMUX_IPSR_DATA(IP6_26_25, SSI_SDATA5),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_25, ADIDATA, SEL_ADI_0),
+ PINMUX_IPSR_DATA(IP6_26_25, CAN_DEBUGOUT12),
+ PINMUX_IPSR_MODSEL_DATA(IP6_26_25, RX3_IRDA_RX, SEL_SCIF3_0),
+ PINMUX_IPSR_DATA(IP6_30_29, SSI_SCK6),
+ PINMUX_IPSR_DATA(IP6_30_29, ADICHS0),
+ PINMUX_IPSR_DATA(IP6_30_29, CAN0_TX),
+ PINMUX_IPSR_MODSEL_DATA(IP6_30_29, IERX_B, SEL_IE_1),
+
+ PINMUX_IPSR_DATA(IP7_1_0, SSI_WS6),
+ PINMUX_IPSR_DATA(IP7_1_0, ADICHS1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_1_0, CAN0_RX, SEL_CAN0_0),
+ PINMUX_IPSR_DATA(IP7_1_0, IETX_B),
+ PINMUX_IPSR_DATA(IP7_3_2, SSI_SDATA6),
+ PINMUX_IPSR_DATA(IP7_3_2, ADICHS2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_3_2, CAN_CLK, SEL_CANCLK_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_3_2, IECLK_B, SEL_IE_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK78, SEL_SSI7_0),
+ PINMUX_IPSR_DATA(IP7_6_4, CAN_DEBUGOUT13),
+ PINMUX_IPSR_MODSEL_DATA(IP7_6_4, IRQ0_B, SEL_INT0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_6_4, SSI_SCK9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_6_4, HSPI_CLK1_C, SEL_HSPI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS78, SEL_SSI7_0),
+ PINMUX_IPSR_DATA(IP7_9_7, CAN_DEBUGOUT14),
+ PINMUX_IPSR_MODSEL_DATA(IP7_9_7, IRQ1_B, SEL_INT1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_9_7, SSI_WS9_B, SEL_SSI9_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_9_7, HSPI_CS1_C, SEL_HSPI1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, SSI_SDATA7, SEL_SSI7_0),
+ PINMUX_IPSR_DATA(IP7_12_10, CAN_DEBUGOUT15),
+ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, IRQ2_B, SEL_INT2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TCLK1_C, SEL_TMU1_2),
+ PINMUX_IPSR_DATA(IP7_12_10, HSPI_TX1_C),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA8, SEL_SSI8_0),
+ PINMUX_IPSR_DATA(IP7_14_13, VSP),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_13, IRQ3_B, SEL_INT3_1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_14_13, HSPI_RX1_C, SEL_HSPI1_2),
+ PINMUX_IPSR_DATA(IP7_16_15, SD0_CLK),
+ PINMUX_IPSR_DATA(IP7_16_15, ATACS01),
+ PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SCK1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_DATA(IP7_18_17, SD0_CMD),
+ PINMUX_IPSR_DATA(IP7_18_17, ATACS11),
+ PINMUX_IPSR_DATA(IP7_18_17, TX1_B),
+ PINMUX_IPSR_DATA(IP7_18_17, CC5_TDO),
+ PINMUX_IPSR_DATA(IP7_20_19, SD0_DAT0),
+ PINMUX_IPSR_DATA(IP7_20_19, ATADIR1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_20_19, RX1_B, SEL_SCIF1_1),
+ PINMUX_IPSR_DATA(IP7_20_19, CC5_TRST),
+ PINMUX_IPSR_DATA(IP7_22_21, SD0_DAT1),
+ PINMUX_IPSR_DATA(IP7_22_21, ATAG1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_22_21, SCK2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_DATA(IP7_22_21, CC5_TMS),
+ PINMUX_IPSR_DATA(IP7_24_23, SD0_DAT2),
+ PINMUX_IPSR_DATA(IP7_24_23, ATARD1),
+ PINMUX_IPSR_DATA(IP7_24_23, TX2_B),
+ PINMUX_IPSR_DATA(IP7_24_23, CC5_TCK),
+ PINMUX_IPSR_DATA(IP7_26_25, SD0_DAT3),
+ PINMUX_IPSR_DATA(IP7_26_25, ATAWR1),
+ PINMUX_IPSR_MODSEL_DATA(IP7_26_25, RX2_B, SEL_SCIF2_1),
+ PINMUX_IPSR_DATA(IP7_26_25, CC5_TDI),
+ PINMUX_IPSR_DATA(IP7_28_27, SD0_CD),
+ PINMUX_IPSR_MODSEL_DATA(IP7_28_27, DREQ2, SEL_EXBUS2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP7_28_27, RTS1_B_TANS_B, SEL_SCIF1_1),
+ PINMUX_IPSR_DATA(IP7_30_29, SD0_WP),
+ PINMUX_IPSR_DATA(IP7_30_29, DACK2),
+ PINMUX_IPSR_MODSEL_DATA(IP7_30_29, CTS1_B, SEL_SCIF1_1),
+
+ PINMUX_IPSR_DATA(IP8_3_0, HSPI_CLK0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_3_0, CTS0, SEL_SCIF0_0),
+ PINMUX_IPSR_DATA(IP8_3_0, USB_OVC0),
+ PINMUX_IPSR_DATA(IP8_3_0, AD_CLK),
+ PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE4),
+ PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE12),
+ PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE20),
+ PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE28),
+ PINMUX_IPSR_DATA(IP8_3_0, CC5_STATE36),
+ PINMUX_IPSR_DATA(IP8_7_4, HSPI_CS0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_7_4, RTS0_TANS, SEL_SCIF0_0),
+ PINMUX_IPSR_DATA(IP8_7_4, USB_OVC1),
+ PINMUX_IPSR_DATA(IP8_7_4, AD_DI),
+ PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE5),
+ PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE13),
+ PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE21),
+ PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE29),
+ PINMUX_IPSR_DATA(IP8_7_4, CC5_STATE37),
+ PINMUX_IPSR_DATA(IP8_11_8, HSPI_TX0),
+ PINMUX_IPSR_DATA(IP8_11_8, TX0),
+ PINMUX_IPSR_DATA(IP8_11_8, CAN_DEBUG_HW_TRIGGER),
+ PINMUX_IPSR_DATA(IP8_11_8, AD_DO),
+ PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE6),
+ PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE14),
+ PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE22),
+ PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE30),
+ PINMUX_IPSR_DATA(IP8_11_8, CC5_STATE38),
+ PINMUX_IPSR_DATA(IP8_15_12, HSPI_RX0),
+ PINMUX_IPSR_MODSEL_DATA(IP8_15_12, RX0, SEL_SCIF0_0),
+ PINMUX_IPSR_DATA(IP8_15_12, CAN_STEP0),
+ PINMUX_IPSR_DATA(IP8_15_12, AD_NCS),
+ PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE7),
+ PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE15),
+ PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE23),
+ PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE31),
+ PINMUX_IPSR_DATA(IP8_15_12, CC5_STATE39),
+ PINMUX_IPSR_DATA(IP8_17_16, FMCLK),
+ PINMUX_IPSR_DATA(IP8_17_16, RDS_CLK),
+ PINMUX_IPSR_DATA(IP8_17_16, PCMOE),
+ PINMUX_IPSR_DATA(IP8_18, BPFCLK),
+ PINMUX_IPSR_DATA(IP8_18, PCMWE),
+ PINMUX_IPSR_DATA(IP8_19, FMIN),
+ PINMUX_IPSR_DATA(IP8_19, RDS_DATA),
+ PINMUX_IPSR_DATA(IP8_20, VI0_CLK),
+ PINMUX_IPSR_DATA(IP8_20, MMC1_CLK),
+ PINMUX_IPSR_DATA(IP8_22_21, VI0_CLKENB),
+ PINMUX_IPSR_DATA(IP8_22_21, TX1_C),
+ PINMUX_IPSR_DATA(IP8_22_21, HTX1_B),
+ PINMUX_IPSR_DATA(IP8_22_21, MT1_SYNC),
+ PINMUX_IPSR_DATA(IP8_24_23, VI0_FIELD),
+ PINMUX_IPSR_MODSEL_DATA(IP8_24_23, RX1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_24_23, HRX1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_DATA(IP8_27_25, VI0_HSYNC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27_25, VI0_DATA0_B_VI0_B0_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27_25, CTS1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_DATA(IP8_27_25, TX4_D),
+ PINMUX_IPSR_DATA(IP8_27_25, MMC1_CMD),
+ PINMUX_IPSR_MODSEL_DATA(IP8_27_25, HSCK1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_DATA(IP8_30_28, VI0_VSYNC),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, VI0_DATA1_B_VI0_B1_B, SEL_VI0_1),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RTS1_C_TANS_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, RX4_D, SEL_SCIF4_3),
+ PINMUX_IPSR_MODSEL_DATA(IP8_30_28, PWMFSW0_C, SEL_PWMFSW_2),
+
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI0_DATA0_VI0_B0, SEL_VI0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_1_0, HRTS1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_DATA(IP9_1_0, MT1_VCXO),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI0_DATA1_VI0_B1, SEL_VI0_0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_3_2, HCTS1_B, SEL_HSCIF1_1),
+ PINMUX_IPSR_DATA(IP9_3_2, MT1_PWM),
+ PINMUX_IPSR_DATA(IP9_4, VI0_DATA2_VI0_B2),
+ PINMUX_IPSR_DATA(IP9_4, MMC1_D0),
+ PINMUX_IPSR_DATA(IP9_5, VI0_DATA3_VI0_B3),
+ PINMUX_IPSR_DATA(IP9_5, MMC1_D1),
+ PINMUX_IPSR_DATA(IP9_6, VI0_DATA4_VI0_B4),
+ PINMUX_IPSR_DATA(IP9_6, MMC1_D2),
+ PINMUX_IPSR_DATA(IP9_7, VI0_DATA5_VI0_B5),
+ PINMUX_IPSR_DATA(IP9_7, MMC1_D3),
+ PINMUX_IPSR_DATA(IP9_9_8, VI0_DATA6_VI0_B6),
+ PINMUX_IPSR_DATA(IP9_9_8, MMC1_D4),
+ PINMUX_IPSR_DATA(IP9_9_8, ARM_TRACEDATA_0),
+ PINMUX_IPSR_DATA(IP9_11_10, VI0_DATA7_VI0_B7),
+ PINMUX_IPSR_DATA(IP9_11_10, MMC1_D5),
+ PINMUX_IPSR_DATA(IP9_11_10, ARM_TRACEDATA_1),
+ PINMUX_IPSR_DATA(IP9_13_12, VI0_G0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_13_12, SSI_SCK78_C, SEL_SSI7_2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_13_12, IRQ0, SEL_INT0_0),
+ PINMUX_IPSR_DATA(IP9_13_12, ARM_TRACEDATA_2),
+ PINMUX_IPSR_DATA(IP9_15_14, VI0_G1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_14, SSI_WS78_C, SEL_SSI7_2),
+ PINMUX_IPSR_MODSEL_DATA(IP9_15_14, IRQ1, SEL_INT1_0),
+ PINMUX_IPSR_DATA(IP9_15_14, ARM_TRACEDATA_3),
+ PINMUX_IPSR_DATA(IP9_18_16, VI0_G2),
+ PINMUX_IPSR_DATA(IP9_18_16, ETH_TXD1),
+ PINMUX_IPSR_DATA(IP9_18_16, MMC1_D6),
+ PINMUX_IPSR_DATA(IP9_18_16, ARM_TRACEDATA_4),
+ PINMUX_IPSR_DATA(IP9_18_16, TS_SPSYNC0),
+ PINMUX_IPSR_DATA(IP9_21_19, VI0_G3),
+ PINMUX_IPSR_DATA(IP9_21_19, ETH_CRS_DV),
+ PINMUX_IPSR_DATA(IP9_21_19, MMC1_D7),
+ PINMUX_IPSR_DATA(IP9_21_19, ARM_TRACEDATA_5),
+ PINMUX_IPSR_DATA(IP9_21_19, TS_SDAT0),
+ PINMUX_IPSR_DATA(IP9_23_22, VI0_G4),
+ PINMUX_IPSR_DATA(IP9_23_22, ETH_TX_EN),
+ PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SD2_DAT0_B, SEL_SD2_1),
+ PINMUX_IPSR_DATA(IP9_23_22, ARM_TRACEDATA_6),
+ PINMUX_IPSR_DATA(IP9_25_24, VI0_G5),
+ PINMUX_IPSR_DATA(IP9_25_24, ETH_RX_ER),
+ PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SD2_DAT1_B, SEL_SD2_1),
+ PINMUX_IPSR_DATA(IP9_25_24, ARM_TRACEDATA_7),
+ PINMUX_IPSR_DATA(IP9_27_26, VI0_G6),
+ PINMUX_IPSR_DATA(IP9_27_26, ETH_RXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SD2_DAT2_B, SEL_SD2_1),
+ PINMUX_IPSR_DATA(IP9_27_26, ARM_TRACEDATA_8),
+ PINMUX_IPSR_DATA(IP9_29_28, VI0_G7),
+ PINMUX_IPSR_DATA(IP9_29_28, ETH_RXD1),
+ PINMUX_IPSR_MODSEL_DATA(IP9_29_28, SD2_DAT3_B, SEL_SD2_1),
+ PINMUX_IPSR_DATA(IP9_29_28, ARM_TRACEDATA_9),
+
+ PINMUX_IPSR_DATA(IP10_2_0, VI0_R0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SSI_SDATA7_C, SEL_SSI7_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCK1_C, SEL_SCIF1_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ1_B, SEL_EXBUS1_0),
+ PINMUX_IPSR_DATA(IP10_2_0, ARM_TRACEDATA_10),
+ PINMUX_IPSR_MODSEL_DATA(IP10_2_0, DREQ0_C, SEL_EXBUS0_2),
+ PINMUX_IPSR_DATA(IP10_5_3, VI0_R1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SSI_SDATA8_C, SEL_SSI8_2),
+ PINMUX_IPSR_DATA(IP10_5_3, DACK1_B),
+ PINMUX_IPSR_DATA(IP10_5_3, ARM_TRACEDATA_11),
+ PINMUX_IPSR_DATA(IP10_5_3, DACK0_C),
+ PINMUX_IPSR_DATA(IP10_5_3, DRACK0_C),
+ PINMUX_IPSR_DATA(IP10_8_6, VI0_R2),
+ PINMUX_IPSR_DATA(IP10_8_6, ETH_LINK),
+ PINMUX_IPSR_DATA(IP10_8_6, SD2_CLK_B),
+ PINMUX_IPSR_MODSEL_DATA(IP10_8_6, IRQ2, SEL_INT2_0),
+ PINMUX_IPSR_DATA(IP10_8_6, ARM_TRACEDATA_12),
+ PINMUX_IPSR_DATA(IP10_11_9, VI0_R3),
+ PINMUX_IPSR_DATA(IP10_11_9, ETH_MAGIC),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SD2_CMD_B, SEL_SD2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_11_9, IRQ3, SEL_INT3_0),
+ PINMUX_IPSR_DATA(IP10_11_9, ARM_TRACEDATA_13),
+ PINMUX_IPSR_DATA(IP10_14_12, VI0_R4),
+ PINMUX_IPSR_DATA(IP10_14_12, ETH_REFCLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SD2_CD_B, SEL_SD2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HSPI_CLK1_B, SEL_HSPI1_1),
+ PINMUX_IPSR_DATA(IP10_14_12, ARM_TRACEDATA_14),
+ PINMUX_IPSR_DATA(IP10_14_12, MT1_CLK),
+ PINMUX_IPSR_DATA(IP10_14_12, TS_SCK0),
+ PINMUX_IPSR_DATA(IP10_17_15, VI0_R5),
+ PINMUX_IPSR_DATA(IP10_17_15, ETH_TXD0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_17_15, SD2_WP_B, SEL_SD2_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_17_15, HSPI_CS1_B, SEL_HSPI1_1),
+ PINMUX_IPSR_DATA(IP10_17_15, ARM_TRACEDATA_15),
+ PINMUX_IPSR_DATA(IP10_17_15, MT1_D),
+ PINMUX_IPSR_DATA(IP10_17_15, TS_SDEN0),
+ PINMUX_IPSR_DATA(IP10_20_18, VI0_R6),
+ PINMUX_IPSR_DATA(IP10_20_18, ETH_MDC),
+ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, DREQ2_C, SEL_EXBUS2_2),
+ PINMUX_IPSR_DATA(IP10_20_18, HSPI_TX1_B),
+ PINMUX_IPSR_DATA(IP10_20_18, TRACECLK),
+ PINMUX_IPSR_DATA(IP10_20_18, MT1_BEN),
+ PINMUX_IPSR_MODSEL_DATA(IP10_20_18, PWMFSW0_D, SEL_PWMFSW_3),
+ PINMUX_IPSR_DATA(IP10_23_21, VI0_R7),
+ PINMUX_IPSR_DATA(IP10_23_21, ETH_MDIO),
+ PINMUX_IPSR_DATA(IP10_23_21, DACK2_C),
+ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, HSPI_RX1_B, SEL_HSPI1_1),
+ PINMUX_IPSR_MODSEL_DATA(IP10_23_21, SCIF_CLK_D, SEL_SCIF_3),
+ PINMUX_IPSR_DATA(IP10_23_21, TRACECTL),
+ PINMUX_IPSR_DATA(IP10_23_21, MT1_PEN),
+ PINMUX_IPSR_DATA(IP10_25_24, VI1_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SIM_D, SEL_SIM_0),
+ PINMUX_IPSR_MODSEL_DATA(IP10_25_24, SDA3, SEL_I2C3_0),
+ PINMUX_IPSR_DATA(IP10_28_26, VI1_HSYNC),
+ PINMUX_IPSR_DATA(IP10_28_26, VI3_CLK),
+ PINMUX_IPSR_DATA(IP10_28_26, SSI_SCK4),
+ PINMUX_IPSR_MODSEL_DATA(IP10_28_26, GPS_SIGN_C, SEL_GPS_2),
+ PINMUX_IPSR_MODSEL_DATA(IP10_28_26, PWMFSW0_E, SEL_PWMFSW_4),
+ PINMUX_IPSR_DATA(IP10_31_29, VI1_VSYNC),
+ PINMUX_IPSR_DATA(IP10_31_29, AUDIO_CLKOUT_C),
+ PINMUX_IPSR_DATA(IP10_31_29, SSI_WS4),
+ PINMUX_IPSR_DATA(IP10_31_29, SIM_CLK),
+ PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GPS_MAG_C, SEL_GPS_2),
+ PINMUX_IPSR_DATA(IP10_31_29, SPV_TRST),
+ PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL3, SEL_I2C3_0),
+
+ PINMUX_IPSR_DATA(IP11_2_0, VI1_DATA0_VI1_B0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SD2_DAT0, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_2_0, SIM_RST),
+ PINMUX_IPSR_DATA(IP11_2_0, SPV_TCK),
+ PINMUX_IPSR_DATA(IP11_2_0, ADICLK_B),
+ PINMUX_IPSR_DATA(IP11_5_3, VI1_DATA1_VI1_B1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SD2_DAT1, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_5_3, MT0_CLK),
+ PINMUX_IPSR_DATA(IP11_5_3, SPV_TMS),
+ PINMUX_IPSR_MODSEL_DATA(IP11_5_3, ADICS_B_SAMP_B, SEL_ADI_1),
+ PINMUX_IPSR_DATA(IP11_8_6, VI1_DATA2_VI1_B2),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SD2_DAT2, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_8_6, MT0_D),
+ PINMUX_IPSR_DATA(IP11_8_6, SPVTDI),
+ PINMUX_IPSR_MODSEL_DATA(IP11_8_6, ADIDATA_B, SEL_ADI_1),
+ PINMUX_IPSR_DATA(IP11_11_9, VI1_DATA3_VI1_B3),
+ PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SD2_DAT3, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_11_9, MT0_BEN),
+ PINMUX_IPSR_DATA(IP11_11_9, SPV_TDO),
+ PINMUX_IPSR_DATA(IP11_11_9, ADICHS0_B),
+ PINMUX_IPSR_DATA(IP11_14_12, VI1_DATA4_VI1_B4),
+ PINMUX_IPSR_DATA(IP11_14_12, SD2_CLK),
+ PINMUX_IPSR_DATA(IP11_14_12, MT0_PEN),
+ PINMUX_IPSR_DATA(IP11_14_12, SPA_TRST),
+ PINMUX_IPSR_MODSEL_DATA(IP11_14_12, HSPI_CLK1_D, SEL_HSPI1_3),
+ PINMUX_IPSR_DATA(IP11_14_12, ADICHS1_B),
+ PINMUX_IPSR_DATA(IP11_17_15, VI1_DATA5_VI1_B5),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SD2_CMD, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_17_15, MT0_SYNC),
+ PINMUX_IPSR_DATA(IP11_17_15, SPA_TCK),
+ PINMUX_IPSR_MODSEL_DATA(IP11_17_15, HSPI_CS1_D, SEL_HSPI1_3),
+ PINMUX_IPSR_DATA(IP11_17_15, ADICHS2_B),
+ PINMUX_IPSR_DATA(IP11_20_18, VI1_DATA6_VI1_B6),
+ PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SD2_CD, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_20_18, MT0_VCXO),
+ PINMUX_IPSR_DATA(IP11_20_18, SPA_TMS),
+ PINMUX_IPSR_DATA(IP11_20_18, HSPI_TX1_D),
+ PINMUX_IPSR_DATA(IP11_23_21, VI1_DATA7_VI1_B7),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SD2_WP, SEL_SD2_0),
+ PINMUX_IPSR_DATA(IP11_23_21, MT0_PWM),
+ PINMUX_IPSR_DATA(IP11_23_21, SPA_TDI),
+ PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
+ PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
+ PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
+ PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
+ PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
+ PINMUX_IPSR_DATA(IP11_26_24, TX2),
+ PINMUX_IPSR_DATA(IP11_26_24, SPA_TDO),
+ PINMUX_IPSR_MODSEL_DATA(IP11_26_24, HCTS0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_DATA(IP11_29_27, VI1_G1),
+ PINMUX_IPSR_DATA(IP11_29_27, VI3_DATA1),
+ PINMUX_IPSR_DATA(IP11_29_27, SSI_SCK1),
+ PINMUX_IPSR_DATA(IP11_29_27, TS_SDEN1),
+ PINMUX_IPSR_DATA(IP11_29_27, DACK2_B),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RX2, SEL_SCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP11_29_27, HRTS0_B, SEL_HSCIF0_1),
+
+ PINMUX_IPSR_DATA(IP12_2_0, VI1_G2),
+ PINMUX_IPSR_DATA(IP12_2_0, VI3_DATA2),
+ PINMUX_IPSR_DATA(IP12_2_0, SSI_WS1),
+ PINMUX_IPSR_DATA(IP12_2_0, TS_SPSYNC1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, SCK2, SEL_SCIF2_0),
+ PINMUX_IPSR_MODSEL_DATA(IP12_2_0, HSCK0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_DATA(IP12_5_3, VI1_G3),
+ PINMUX_IPSR_DATA(IP12_5_3, VI3_DATA3),
+ PINMUX_IPSR_DATA(IP12_5_3, SSI_SCK2),
+ PINMUX_IPSR_DATA(IP12_5_3, TS_SDAT1),
+ PINMUX_IPSR_MODSEL_DATA(IP12_5_3, SCL1_C, SEL_I2C1_2),
+ PINMUX_IPSR_DATA(IP12_5_3, HTX0_B),
+ PINMUX_IPSR_DATA(IP12_8_6, VI1_G4),
+ PINMUX_IPSR_DATA(IP12_8_6, VI3_DATA4),
+ PINMUX_IPSR_DATA(IP12_8_6, SSI_WS2),
+ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, SDA1_C, SEL_I2C1_2),
+ PINMUX_IPSR_DATA(IP12_8_6, SIM_RST_B),
+ PINMUX_IPSR_MODSEL_DATA(IP12_8_6, HRX0_B, SEL_HSCIF0_1),
+ PINMUX_IPSR_DATA(IP12_11_9, VI1_G5),
+ PINMUX_IPSR_DATA(IP12_11_9, VI3_DATA5),
+ PINMUX_IPSR_MODSEL_DATA(IP12_11_9, GPS_CLK, SEL_GPS_0),
+ PINMUX_IPSR_DATA(IP12_11_9, FSE),
+ PINMUX_IPSR_DATA(IP12_11_9, TX4_B),
+ PINMUX_IPSR_MODSEL_DATA(IP12_11_9, SIM_D_B, SEL_SIM_1),
+ PINMUX_IPSR_DATA(IP12_14_12, VI1_G6),
+ PINMUX_IPSR_DATA(IP12_14_12, VI3_DATA6),
+ PINMUX_IPSR_MODSEL_DATA(IP12_14_12, GPS_SIGN, SEL_GPS_0),
+ PINMUX_IPSR_DATA(IP12_14_12, FRB),
+ PINMUX_IPSR_MODSEL_DATA(IP12_14_12, RX4_B, SEL_SCIF4_1),
+ PINMUX_IPSR_DATA(IP12_14_12, SIM_CLK_B),
+ PINMUX_IPSR_DATA(IP12_17_15, VI1_G7),
+ PINMUX_IPSR_DATA(IP12_17_15, VI3_DATA7),
+ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, GPS_MAG, SEL_GPS_0),
+ PINMUX_IPSR_DATA(IP12_17_15, FCE),
+ PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+ PINMUX_GPIO_GP_ALL(),
+ GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
+ GPIO_FN(A19),
+
+ /* IPSR0 */
+ GPIO_FN(PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
+ GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
+ GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
+ GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
+ GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
+ GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
+ GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
+ GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
+ GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
+ GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
+ GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
+ GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
+ GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
+ GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
+ GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
+ GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
+ GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
+
+ /* IPSR1 */
+ GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
+ GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
+ GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
+ GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
+ GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
+ GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
+ GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
+ GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
+ GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
+ GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
+ GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
+ GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
+ GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
+ GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
+ GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
+ GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
+ GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
+ GPIO_FN(CC5_STATE34),
+
+ /* IPSR2 */
+ GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
+ GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
+ GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
+ GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
+ GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
+ GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
+ GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
+ GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
+ GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
+ GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
+ GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
+ GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
+ GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
+ GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
+ GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
+ GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
+ GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
+ GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
+ GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
+ GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
+ GPIO_FN(AUDATA2),
+
+ /* IPSR3 */
+ GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
+ GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
+ GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
+ GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
+ GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
+ GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
+ GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
+ GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
+ GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
+ GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
+ GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
+ GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
+ GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
+ GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
+ GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
+ GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
+ GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
+ GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
+ GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
+ GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
+ GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
+
+ /* IPSR4 */
+ GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
+ GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
+ GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
+ GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
+ GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
+ GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
+ GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
+ GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
+ GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
+ GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
+ GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
+ GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
+ GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
+ GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
+ GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
+ GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
+ GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
+ GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
+ GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
+ GPIO_FN(TX5), GPIO_FN(SCK0_D),
+
+ /* IPSR5 */
+ GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
+ GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
+ GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
+ GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
+ GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
+ GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
+ GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
+ GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
+ GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
+ GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
+ GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
+ GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
+ GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
+ GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
+ GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
+ GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
+ GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
+ GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
+ GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
+ GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
+ GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
+ GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
+
+ /* IPSR6 */
+ GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
+ GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
+ GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
+ GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
+ GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
+ GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
+ GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
+ GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
+ GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
+ GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
+ GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
+ GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
+ GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
+ GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
+ GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
+ GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
+ GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
+
+ /* IPSR7 */
+ GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
+ GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
+ GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
+ GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
+ GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
+ GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
+ GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
+ GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
+ GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
+ GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
+ GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
+ GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
+ GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
+ GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
+ GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
+ GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
+ GPIO_FN(CTS1_B),
+
+ /* IPSR8 */
+ GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
+ GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
+ GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
+ GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
+ GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
+ GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
+ GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
+ GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
+ GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
+ GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
+ GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
+ GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
+ GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
+ GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
+ GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
+ GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
+ GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
+ GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
+ GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
+ GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
+
+ /* IPSR9 */
+ GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
+ GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
+ GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
+ GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
+ GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
+ GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
+ GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
+ GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
+ GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
+ GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
+ GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
+ GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
+ GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
+ GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
+ GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
+ GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
+ GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
+ GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
+
+ /* IPSR10 */
+ GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
+ GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
+ GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
+ GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
+ GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
+ GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
+ GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
+ GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
+ GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
+ GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
+ GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
+ GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
+ GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
+ GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
+ GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
+ GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
+ GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
+ GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
+ GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
+ GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
+ GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
+
+ /* IPSR11 */
+ GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
+ GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
+ GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
+ GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
+ GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
+ GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
+ GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
+ GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
+ GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
+ GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
+ GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
+ GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
+ GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
+ GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
+ GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
+ GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
+ GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
+ GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
+ GPIO_FN(HRTS0_B),
+
+ /* IPSR12 */
+ GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
+ GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
+ GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
+ GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
+ GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
+ GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
+ GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
+ GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
+ GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
+ GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+ { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+ GP_0_31_FN, FN_IP3_31_29,
+ GP_0_30_FN, FN_IP3_26_24,
+ GP_0_29_FN, FN_IP3_22_21,
+ GP_0_28_FN, FN_IP3_14_12,
+ GP_0_27_FN, FN_IP3_11_9,
+ GP_0_26_FN, FN_IP3_2_0,
+ GP_0_25_FN, FN_IP2_30_28,
+ GP_0_24_FN, FN_IP2_21_19,
+ GP_0_23_FN, FN_IP2_18_16,
+ GP_0_22_FN, FN_IP0_30_28,
+ GP_0_21_FN, FN_IP0_5_3,
+ GP_0_20_FN, FN_IP1_18_15,
+ GP_0_19_FN, FN_IP1_14_11,
+ GP_0_18_FN, FN_IP1_10_7,
+ GP_0_17_FN, FN_IP1_6_4,
+ GP_0_16_FN, FN_IP1_3_2,
+ GP_0_15_FN, FN_IP1_1_0,
+ GP_0_14_FN, FN_IP0_27_26,
+ GP_0_13_FN, FN_IP0_25,
+ GP_0_12_FN, FN_IP0_24_23,
+ GP_0_11_FN, FN_IP0_22_19,
+ GP_0_10_FN, FN_IP0_18_16,
+ GP_0_9_FN, FN_IP0_15_14,
+ GP_0_8_FN, FN_IP0_13_12,
+ GP_0_7_FN, FN_IP0_11_10,
+ GP_0_6_FN, FN_IP0_9_8,
+ GP_0_5_FN, FN_A19,
+ GP_0_4_FN, FN_A18,
+ GP_0_3_FN, FN_A17,
+ GP_0_2_FN, FN_IP0_7_6,
+ GP_0_1_FN, FN_AVS2,
+ GP_0_0_FN, FN_AVS1 }
+ },
+ { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+ GP_1_31_FN, FN_IP5_23_21,
+ GP_1_30_FN, FN_IP5_20_17,
+ GP_1_29_FN, FN_IP5_16_15,
+ GP_1_28_FN, FN_IP5_14_13,
+ GP_1_27_FN, FN_IP5_12_11,
+ GP_1_26_FN, FN_IP5_10_9,
+ GP_1_25_FN, FN_IP5_8,
+ GP_1_24_FN, FN_IP5_7,
+ GP_1_23_FN, FN_IP5_6,
+ GP_1_22_FN, FN_IP5_5,
+ GP_1_21_FN, FN_IP5_4,
+ GP_1_20_FN, FN_IP5_3,
+ GP_1_19_FN, FN_IP5_2_0,
+ GP_1_18_FN, FN_IP4_31_29,
+ GP_1_17_FN, FN_IP4_28,
+ GP_1_16_FN, FN_IP4_27,
+ GP_1_15_FN, FN_IP4_26,
+ GP_1_14_FN, FN_IP4_25,
+ GP_1_13_FN, FN_IP4_24,
+ GP_1_12_FN, FN_IP4_23,
+ GP_1_11_FN, FN_IP4_22_20,
+ GP_1_10_FN, FN_IP4_19_17,
+ GP_1_9_FN, FN_IP4_16,
+ GP_1_8_FN, FN_IP4_15,
+ GP_1_7_FN, FN_IP4_14,
+ GP_1_6_FN, FN_IP4_13,
+ GP_1_5_FN, FN_IP4_12,
+ GP_1_4_FN, FN_IP4_11,
+ GP_1_3_FN, FN_IP4_10_8,
+ GP_1_2_FN, FN_IP4_7_5,
+ GP_1_1_FN, FN_IP4_4_2,
+ GP_1_0_FN, FN_IP4_1_0 }
+ },
+ { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+ GP_2_31_FN, FN_IP10_28_26,
+ GP_2_30_FN, FN_IP10_25_24,
+ GP_2_29_FN, FN_IP10_23_21,
+ GP_2_28_FN, FN_IP10_20_18,
+ GP_2_27_FN, FN_IP10_17_15,
+ GP_2_26_FN, FN_IP10_14_12,
+ GP_2_25_FN, FN_IP10_11_9,
+ GP_2_24_FN, FN_IP10_8_6,
+ GP_2_23_FN, FN_IP10_5_3,
+ GP_2_22_FN, FN_IP10_2_0,
+ GP_2_21_FN, FN_IP9_29_28,
+ GP_2_20_FN, FN_IP9_27_26,
+ GP_2_19_FN, FN_IP9_25_24,
+ GP_2_18_FN, FN_IP9_23_22,
+ GP_2_17_FN, FN_IP9_21_19,
+ GP_2_16_FN, FN_IP9_18_16,
+ GP_2_15_FN, FN_IP9_15_14,
+ GP_2_14_FN, FN_IP9_13_12,
+ GP_2_13_FN, FN_IP9_11_10,
+ GP_2_12_FN, FN_IP9_9_8,
+ GP_2_11_FN, FN_IP9_7,
+ GP_2_10_FN, FN_IP9_6,
+ GP_2_9_FN, FN_IP9_5,
+ GP_2_8_FN, FN_IP9_4,
+ GP_2_7_FN, FN_IP9_3_2,
+ GP_2_6_FN, FN_IP9_1_0,
+ GP_2_5_FN, FN_IP8_30_28,
+ GP_2_4_FN, FN_IP8_27_25,
+ GP_2_3_FN, FN_IP8_24_23,
+ GP_2_2_FN, FN_IP8_22_21,
+ GP_2_1_FN, FN_IP8_20,
+ GP_2_0_FN, FN_IP5_27_24 }
+ },
+ { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+ GP_3_31_FN, FN_IP6_3_2,
+ GP_3_30_FN, FN_IP6_1_0,
+ GP_3_29_FN, FN_IP5_30_29,
+ GP_3_28_FN, FN_IP5_28,
+ GP_3_27_FN, FN_IP1_24_23,
+ GP_3_26_FN, FN_IP1_22_21,
+ GP_3_25_FN, FN_IP1_20_19,
+ GP_3_24_FN, FN_IP7_26_25,
+ GP_3_23_FN, FN_IP7_24_23,
+ GP_3_22_FN, FN_IP7_22_21,
+ GP_3_21_FN, FN_IP7_20_19,
+ GP_3_20_FN, FN_IP7_30_29,
+ GP_3_19_FN, FN_IP7_28_27,
+ GP_3_18_FN, FN_IP7_18_17,
+ GP_3_17_FN, FN_IP7_16_15,
+ GP_3_16_FN, FN_IP12_17_15,
+ GP_3_15_FN, FN_IP12_14_12,
+ GP_3_14_FN, FN_IP12_11_9,
+ GP_3_13_FN, FN_IP12_8_6,
+ GP_3_12_FN, FN_IP12_5_3,
+ GP_3_11_FN, FN_IP12_2_0,
+ GP_3_10_FN, FN_IP11_29_27,
+ GP_3_9_FN, FN_IP11_26_24,
+ GP_3_8_FN, FN_IP11_23_21,
+ GP_3_7_FN, FN_IP11_20_18,
+ GP_3_6_FN, FN_IP11_17_15,
+ GP_3_5_FN, FN_IP11_14_12,
+ GP_3_4_FN, FN_IP11_11_9,
+ GP_3_3_FN, FN_IP11_8_6,
+ GP_3_2_FN, FN_IP11_5_3,
+ GP_3_1_FN, FN_IP11_2_0,
+ GP_3_0_FN, FN_IP10_31_29 }
+ },
+ { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+ GP_4_31_FN, FN_IP8_19,
+ GP_4_30_FN, FN_IP8_18,
+ GP_4_29_FN, FN_IP8_17_16,
+ GP_4_28_FN, FN_IP0_2_0,
+ GP_4_27_FN, FN_PENC1,
+ GP_4_26_FN, FN_PENC0,
+ GP_4_25_FN, FN_IP8_15_12,
+ GP_4_24_FN, FN_IP8_11_8,
+ GP_4_23_FN, FN_IP8_7_4,
+ GP_4_22_FN, FN_IP8_3_0,
+ GP_4_21_FN, FN_IP2_3_0,
+ GP_4_20_FN, FN_IP1_28_25,
+ GP_4_19_FN, FN_IP2_15_12,
+ GP_4_18_FN, FN_IP2_11_8,
+ GP_4_17_FN, FN_IP2_7_4,
+ GP_4_16_FN, FN_IP7_14_13,
+ GP_4_15_FN, FN_IP7_12_10,
+ GP_4_14_FN, FN_IP7_9_7,
+ GP_4_13_FN, FN_IP7_6_4,
+ GP_4_12_FN, FN_IP7_3_2,
+ GP_4_11_FN, FN_IP7_1_0,
+ GP_4_10_FN, FN_IP6_30_29,
+ GP_4_9_FN, FN_IP6_26_25,
+ GP_4_8_FN, FN_IP6_24_23,
+ GP_4_7_FN, FN_IP6_22_20,
+ GP_4_6_FN, FN_IP6_19_18,
+ GP_4_5_FN, FN_IP6_17_15,
+ GP_4_4_FN, FN_IP6_14_12,
+ GP_4_3_FN, FN_IP6_11_9,
+ GP_4_2_FN, FN_IP6_8,
+ GP_4_1_FN, FN_IP6_7_6,
+ GP_4_0_FN, FN_IP6_5_4 }
+ },
+ { PINMUX_CFG_REG("GPSR5", 0xfffc0018, 32, 1) {
+ GP_5_31_FN, FN_IP3_5,
+ GP_5_30_FN, FN_IP3_4,
+ GP_5_29_FN, FN_IP3_3,
+ GP_5_28_FN, FN_IP2_27,
+ GP_5_27_FN, FN_IP2_26,
+ GP_5_26_FN, FN_IP2_25,
+ GP_5_25_FN, FN_IP2_24,
+ GP_5_24_FN, FN_IP2_23,