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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-03 15:16:33 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-08-03 15:16:33 -0700
commit22da317629bad23816f3fa26d657fb46e7af21c7 (patch)
treeea9e97afd3aca46c16b77468ef91e5e39d36ed7f /include/asm-powerpc
parent3e847423bf029c2170692c75580a856debed617b (diff)
parent67439b76f29cb278bb3412fc873b980fc65110c9 (diff)
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: [POWERPC] Fixes for the SLB shadow buffer code [POWERPC] Fix a compile warning in powermac/feature.c [POWERPC] Fix a compile warning in pci_32.c [POWERPC] Fix parse_drconf_memory() for 64-bit start addresses [POWERPC] Fix num_cpus calculation in smp_call_function_map() [POWERPC] ps3: Fix section mismatch in ps3/setup.c [POWERPC] spufs: Fix affinity after introduction of node_allowed() calls [POWERPC] Fix special PTE code for secondary hash bucket [POWERPC] Expand RPN field to 34 bits when using 64k pages
Diffstat (limited to 'include/asm-powerpc')
-rw-r--r--include/asm-powerpc/mmu-hash64.h1
-rw-r--r--include/asm-powerpc/pgtable-64k.h8
2 files changed, 4 insertions, 5 deletions
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 695962f02059..3112ad14ad95 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -262,6 +262,7 @@ extern void slb_initialize(void);
extern void slb_flush_and_rebolt(void);
extern void stab_initialize(unsigned long stab);
+extern void slb_vmalloc_update(void);
#endif /* __ASSEMBLY__ */
/*
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 31cbd3d7fce8..33ae9018fe72 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -49,12 +49,10 @@
/* Shift to put page number into pte.
*
- * That gives us a max RPN of 32 bits, which means a max of 48 bits
- * of addressable physical space.
- * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
- * 32 makes PTEs more readable for debugging for now :)
+ * That gives us a max RPN of 34 bits, which means a max of 50 bits
+ * of addressable physical space, or 46 bits for the special 4k PFNs.
*/
-#define PTE_RPN_SHIFT (32)
+#define PTE_RPN_SHIFT (30)
#define PTE_RPN_MAX (1UL << (64 - PTE_RPN_SHIFT))
#define PTE_RPN_MASK (~((1UL<<PTE_RPN_SHIFT)-1))