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-rw-r--r--Documentation/devicetree/bindings/gpio/gpio.txt6
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt107
-rw-r--r--arch/arm/boot/dts/Makefile5
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts52
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts32
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen-reference.dts47
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts31
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts79
-rw-r--r--arch/arm/boot/dts/sh73a0-reference.dtsi24
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi44
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi4
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi4
-rw-r--r--arch/arm/boot/dts/spear310.dtsi4
-rw-r--r--arch/arm/boot/dts/spear320.dtsi4
-rw-r--r--arch/arm/configs/bockw_defconfig66
-rw-r--r--arch/arm/mach-shmobile/Kconfig48
-rw-r--r--arch/arm/mach-shmobile/Makefile5
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c172
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c91
-rw-r--r--arch/arm/mach-shmobile/board-ape6evm.c94
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c300
-rw-r--r--arch/arm/mach-shmobile/board-bockw.c43
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c52
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c208
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c107
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c230
-rw-r--r--arch/arm/mach-shmobile/board-lager.c46
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c187
-rw-r--r--arch/arm/mach-shmobile/board-marzen-reference.c75
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c120
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h74
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h321
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h29
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h363
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c58
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c13
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c13
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c13
-rw-r--r--arch/sh/kernel/cpu/sh3/pinmux-sh7720.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-shx3.c17
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-pl061.c117
-rw-r--r--drivers/gpio/gpio-rcar.c396
-rw-r--r--drivers/gpio/gpiolib-of.c20
-rw-r--r--drivers/pinctrl/Kconfig1
-rw-r--r--drivers/pinctrl/core.c39
-rw-r--r--drivers/pinctrl/devicetree.c4
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c6
-rw-r--r--drivers/pinctrl/pinconf-generic.c14
-rw-r--r--drivers/pinctrl/pinconf.c4
-rw-r--r--drivers/pinctrl/pinconf.h10
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c9
-rw-r--r--drivers/pinctrl/pinctrl-at91.c6
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c6
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c6
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx.c6
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c4
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c6
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c6
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.c4
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c6
-rw-r--r--drivers/pinctrl/pinctrl-single.c515
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c4
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c978
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c6
-rw-r--r--drivers/pinctrl/pinctrl-u300.c6
-rw-r--r--drivers/pinctrl/pinctrl-xway.c2
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig6
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c302
-rw-r--r--drivers/pinctrl/sh-pfc/core.h55
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c372
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c2587
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c626
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c1695
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c488
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c460
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c624
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c323
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c2656
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c333
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c480
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c642
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c638
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c55
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c620
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c354
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c296
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c148
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c491
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h135
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
-rw-r--r--include/linux/pinctrl/pinctrl.h6
-rw-r--r--include/linux/platform_data/gpio-rcar.h26
102 files changed, 13754 insertions, 6143 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index a33628759d36..d933af370697 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
- gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
+ gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
}
@@ -107,8 +107,8 @@ where,
Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
- pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
- by this gpio controller.
+ pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
+ pinctrl2 with gpio offset 10 is handled by this gpio controller.
The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 2c81e45f1374..fa1746b639b9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -1,7 +1,9 @@
One-register-per-pin type device tree based pinctrl driver
Required properties:
-- compatible : "pinctrl-single"
+- compatible : "pinctrl-single" or "pinconf-single".
+ "pinctrl-single" means that pinconf isn't supported.
+ "pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
@@ -14,9 +16,61 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
+
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
+- pinctrl-single,drive-strength : array of value that are used to configure
+ drive strength in the pinmux register. They're value of drive strength
+ current and drive strength mask.
+
+ /* drive strength current, mask */
+ pinctrl-single,power-source = <0x30 0xf0>;
+
+- pinctrl-single,bias-pullup : array of value that are used to configure the
+ input bias pullup in the pinmux register.
+
+ /* input, enabled pullup bits, disabled pullup bits, mask */
+ pinctrl-single,bias-pullup = <0 1 0 1>;
+
+- pinctrl-single,bias-pulldown : array of value that are used to configure the
+ input bias pulldown in the pinmux register.
+
+ /* input, enabled pulldown bits, disabled pulldown bits, mask */
+ pinctrl-single,bias-pulldown = <2 2 0 2>;
+
+ * Two bits to control input bias pullup and pulldown: User should use
+ pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
+ pullup, and the other one bit means pulldown.
+ * Three bits to control input bias enable, pullup and pulldown. User should
+ use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
+ enable bit should be included in pullup or pulldown bits.
+ * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
+ pinctrl-single,bias-disable. Because pinctrl single driver could implement
+ it by calling pulldown, pullup disabled.
+
+- pinctrl-single,input-schmitt : array of value that are used to configure
+ input schmitt in the pinmux register. In some silicons, there're two input
+ schmitt value (rising-edge & falling-edge) in the pinmux register.
+
+ /* input schmitt value, mask */
+ pinctrl-single,input-schmitt = <0x30 0x70>;
+
+- pinctrl-single,input-schmitt-enable : array of value that are used to
+ configure input schmitt enable or disable in the pinmux register.
+
+ /* input, enable bits, disable bits, mask */
+ pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
+
+- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
+ range. They're value of subnode phandle, pin base in pinctrl device, pin
+ number in this range, GPIO function value of this GPIO range.
+ The number of parameters is depend on #pinctrl-single,gpio-range-cells
+ property.
+
+ /* pin base, nr pins & gpio function */
+ pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
+
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
+
+Optional sub-node: In case some pins could be configured as GPIO in the pinmux
+register, those pins could be defined as a GPIO range. This sub-node is required
+by pinctrl-single,gpio-range property.
+
+Required properties in sub-node:
+- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
+ pinctrl-single,gpio-range property.
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+
+
Example:
/* SoC common file */
@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
pinctrl-single,function-mask = <0x5F>;
};
+/* third controller instance for pins in gpio domain */
+pmx_gpio: pinmux@d401e000 {
+ compatible = "pinconf-single";
+ reg = <0xd401e000 0x0330>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+
+ /* sparse GPIO range could be supported */
+ pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
+ &range 12 1 0 &range 13 29 1
+ &range 43 1 0 &range 44 49 1
+ &range 94 1 1 &range 96 2 1>;
+
+ range: gpio-range {
+ #pinctrl-single,gpio-range-cells = <3>;
+ };
+};
+
+
/* board specific .dts file */
&pmx_core {
@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
>;
};
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x208 0 /* UART0_RXD (IOCFG138) */
+ 0x20c 0 /* UART0_TXD (IOCFG139) */
+ >;
+ pinctrl-single,bias-pulldown = <0 2 2>;
+ pinctrl-single,bias-pullup = <0 1 1>;
+ };
+
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+};
+
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9c6255884cbb..47b6be7cf1e8 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -136,7 +136,12 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
+ r8a7778-bockw.dtb \
+ r8a7779-marzen-reference.dtb \
+ r8a7790-lager.dtb \
sh73a0-kzm9g.dtb \
+ sh73a0-kzm9g-reference.dtb \
+ r8a73a4-ape6evm.dtb \
sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
socfpga_vt.dtb
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
new file mode 100644
index 000000000000..f603c6946c29
--- /dev/null
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -0,0 +1,52 @@
+/*
+ * Device Tree Source for the APE6EVM board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a73a4.dtsi"
+
+/ {
+ model = "APE6EVM";
+ compatible = "renesas,ape6evm", "renesas,r8a73a4";
+
+ chosen {
+ bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ ape6evm_fixed_3v3: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ethernet@8000000 {
+ compatible = "smsc,lan9118", "smsc,lan9115";
+ reg = <0x08000000 0x1000>;
+ interrupt-parent = <&irqc1>;
+ interrupts = <8 0x4>;
+ phy-mode = "mii";
+ reg-io-width = <4>;
+ smsc,irq-active-high;
+ smsc,irq-push-pull;
+ vdd33a-supply = <&ape6evm_fixed_3v3>;
+ vddvario-supply = <&ape6evm_fixed_3v3>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
new file mode 100644
index 000000000000..735c964920f9
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -0,0 +1,32 @@
+/*
+ * Reference Device Tree Source for the Bock-W board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * based on r8a7779
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7778.dtsi"
+
+/ {
+ model = "bockw";
+ compatible = "renesas,bockw", "renesas,r8a7778";
+
+ chosen {
+ bootargs = "console=ttySC0,115200 ignore_loglevel";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x10000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
new file mode 100644
index 000000000000..72be4c87cfb5
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -0,0 +1,47 @@
+/*
+ * Reference Device Tree Source for the Marzen board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7779.dtsi"
+
+/ {
+ model = "marzen";
+ compatible = "renesas,marzen-reference", "renesas,r8a7779";
+
+ chosen {
+ bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ fixedregulator3v3: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ lan0@18000000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x18000000 0x100>;
+ phy-mode = "mii";
+ interrupt-parent = <&gic>;
+ interrupts = <0 28 0x4>;
+ reg-io-width = <4>;
+ vddvario-supply = <&fixedregulator3v3>;
+ vdd33a-supply = <&fixedregulator3v3>;
+ };
+};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
new file mode 100644
index 000000000000..09a84fce89d6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -0,0 +1,31 @@
+/*
+ * Device Tree Source for the Lager board
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "r8a7790.dtsi"
+
+/ {
+ model = "Lager";
+ compatible = "renesas,lager", "renesas,r8a7790";
+
+ chosen {
+ bootargs = "console=ttySC6,115200 ignore_loglevel";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+
+ lbsc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
new file mode 100644
index 000000000000..5972abb55f9c
--- /dev/null
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -0,0 +1,79 @@
+/*
+ * Device Tree Source for the KZM-A9-GT board
+ *
+ * Copyright (C) 2012 Horms Solutions Ltd.
+ *
+ * Based on sh73a0-kzm9g.dts
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+/include/ "sh73a0.dtsi"
+
+/ {
+ model = "KZM-A9-GT";
+ compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
+
+ chosen {
+ bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x41000000 0x1e800000>;
+ };
+
+ reg_1p8v: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ reg_3p3v: regulator@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ lan9220@10000000 {
+ compatible = "smsc,lan9220", "smsc,lan9115";
+ reg = <0x10000000 0x100>;
+ phy-mode = "mii";
+ interrupt-parent = <&irqpin0>;
+ interrupts = <3 0>; /* active low */
+ reg-io-width = <4>;
+ smsc,irq-push-pull;
+ smsc,save-mac-address;
+ vddvario-supply = <&reg_1p8v>;
+ vdd33a-supply = <&reg_3p3v>;
+ };
+};
+
+&mmcif {
+ bus-width = <8>;
+ vmmc-supply = <&reg_1p8v>;
+ status = "okay";
+};
+
+&sdhi0 {
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&sdhi2 {
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <4>;
+ broken-cd;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/sh73a0-reference.dtsi b/arch/arm/boot/dts/sh73a0-reference.dtsi
deleted file mode 100644
index d4bb0125b2b2..000000000000
--- a/arch/arm/boot/dts/sh73a0-reference.dtsi
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Device Tree Source for the SH73A0 SoC
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/include/ "sh73a0.dtsi"
-
-/ {
- compatible = "renesas,sh73a0";
-
- mmcif: mmcif@0x10010000 {
- compatible = "renesas,sh-mmcif";
- reg = <0xe6bd0000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 140 0x4
- 0 141 0x4>;
- reg-io-width = <4>;
- };
-};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 7e71e3a85767..ec40bf78289e 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -178,4 +178,48 @@
0 189 0x4
0 190 0x4>;
};
+
+ mmcif: mmcif@0x10010000 {
+ compatible = "renesas,sh-mmcif";
+ reg = <0xe6bd0000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 140 0x4
+ 0 141 0x4>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ sdhi0: sdhi@0xee100000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee100000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 83 4
+ 0 84 4
+ 0 85 4>;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
+
+ /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
+ sdhi1: sdhi@0xee120000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee120000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 88 4
+ 0 89 4>;
+ toshiba,mmc-wrprotect-disable;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
+
+ sdhi2: sdhi@0xee140000 {
+ compatible = "renesas,r8a7740-sdhi";
+ reg = <0xee140000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 104 4
+ 0 105 4>;
+ toshiba,mmc-wrprotect-disable;
+ cap-sd-highspeed;
+ status = "disabled";
+ };
};
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 1513c1927cc8..122ae94076c8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -89,7 +89,7 @@
pinmux: pinmux@e0700000 {
compatible = "st,spear1310-pinmux";
reg = <0xe0700000 0x1000>;
- #gpio-range-cells = <2>;
+ #gpio-range-cells = <3>;
};
apb {
@@ -212,7 +212,7 @@
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinmux 0 246>;
+ gpio-ranges = <&pinmux 0 0 246>;
status = "disabled";
st-plgpio,ngpio = <246>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..c511c4772efd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -63,7 +63,7 @@
pinmux: pinmux@e0700000 {
compatible = "st,spear1340-pinmux";
reg = <0xe0700000 0x1000>;
- #gpio-range-cells = <2>;
+ #gpio-range-cells = <3>;
};
pwm: pwm@e0180000 {
@@ -127,7 +127,7 @@
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinmux 0 252>;
+ gpio-ranges = <&pinmux 0 0 252>;
status = "disabled";
st-plgpio,ngpio = <250>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index ab45b8c81982..95372080eea6 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -25,7 +25,7 @@
pinmux: pinmux@b4000000 {
compatible = "st,spear310-pinmux";
reg = <0xb4000000 0x1000>;
- #gpio-range-cells = <2>;
+ #gpio-range-cells = <3>;
};
fsmc: flash@44000000 {
@@ -102,7 +102,7 @@
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinmux 0 102>;
+ gpio-ranges = <&pinmux 0 0 102>;
status = "disabled";
st-plgpio,ngpio = <102>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index caa5520b1fd4..ffea342aeec9 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -24,7 +24,7 @@
pinmux: pinmux@b3000000 {
compatible = "st,spear320-pinmux";
reg = <0xb3000000 0x1000>;
- #gpio-range-cells = <2>;
+ #gpio-range-cells = <3>;
};
clcd@90000000 {
@@ -130,7 +130,7 @@
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
- gpio-ranges = <&pinmux 0 102>;
+ gpio-ranges = <&pinmux 0 0 102>;
status = "disabled";
st-plgpio,ngpio = <102>;
diff --git a/arch/arm/configs/bockw_defconfig b/arch/arm/configs/bockw_defconfig
new file mode 100644
index 000000000000..6037705b7b67
--- /dev/null
+++ b/arch/arm/configs/bockw_defconfig
@@ -0,0 +1,66 @@
+# CONFIG_ARM_PATCH_PHYS_VIRT is not set
+CONFIG_KERNEL_LZMA=y
+CONFIG_NO_HZ=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_SHMOBILE=y
+CONFIG_ARCH_R8A7778=y
+CONFIG_MACH_BOCKW=y
+CONFIG_MEMORY_START=0x60000000
+CONFIG_MEMORY_SIZE=0x10000000
+CONFIG_SHMOBILE_TIMER_HZ=1024
+# CONFIG_SH_TIMER_CMT is not set
+# CONFIG_EM_TIMER_STI is not set
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_458693=y
+CONFIG_ARM_ERRATA_460075=y
+CONFIG_ARM_ERRATA_743622=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CMDLINE="console=ttySC0,115200 ignore_loglevel"
+CONFIG_CMDLINE_FORCE=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=6
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_IOMMU_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY_USER is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_KEYS=y
+CONFIG_CRYPTO=y
+CONFIG_AVERAGE=y
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index ff674c5f2d03..549e05985745 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -96,6 +96,11 @@ config MACH_AG5EVM
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SH_LCD_MIPI_DSI
+config MACH_APE6EVM
+ bool "APE6EVM board"
+ depends on ARCH_R8A73A4
+ select USE_OF
+
config MACH_MACKEREL
bool "mackerel board"
depends on ARCH_SH7372
@@ -124,12 +129,36 @@ config MACH_ARMADILLO800EVA
select SND_SOC_WM8978 if SND_SIMPLE_CARD
select USE_OF
+config MACH_BOCKW
+ bool "BOCK-W platform"
+ depends on ARCH_R8A7778
+ select ARCH_REQUIRE_GPIOLIB
+ select USE_OF
+
config MACH_MARZEN
bool "MARZEN board"
depends on ARCH_R8A7779
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
+config MACH_MARZEN_REFERENCE
+ bool "MARZEN board - Reference Device Tree Implementation"
+ depends on ARCH_R8A7779
+ select ARCH_REQUIRE_GPIOLIB
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select USE_OF
+ ---help---
+ Use reference implementation of Marzen board support
+ which makes use of device tree at the expense
+ of not supporting a number of devices.
+
+ This is intended to aid developers
+
+config MACH_LAGER
+ bool "Lager board"
+ depends on ARCH_R8A7790
+ select USE_OF
+
config MACH_KZM9D
bool "KZM9D board"
depends on ARCH_EMEV2
@@ -144,6 +173,20 @@ config MACH_KZM9G
select SND_SOC_AK4642 if SND_SIMPLE_CARD
select USE_OF
+config MACH_KZM9G_REFERENCE
+ bool "KZM-A9-GT board - Reference Device Tree Implementation"
+ depends on ARCH_SH73A0
+ select ARCH_REQUIRE_GPIOLIB
+ select REGULATOR_FIXED_VOLTAGE if REGULATOR
+ select SND_SOC_AK4642 if SND_SIMPLE_CARD
+ select USE_OF
+ ---help---
+ Use reference implementation of KZM-A9-GT board support
+ which makes as greater use of device tree at the expense
+ of not supporting a number of devices.
+
+ This is intended to aid developers
+
comment "SH-Mobile System Configuration"
config CPU_HAS_INTEVT
@@ -156,7 +199,8 @@ config MEMORY_START
hex "Physical memory start address"
default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
MACH_MACKEREL || MACH_BONITO || \
- MACH_ARMADILLO800EVA
+ MACH_ARMADILLO800EVA || MACH_APE6EVM || \
+ MACH_LAGER
default "0x41000000" if MACH_KOTA2
default "0x00000000"
---help---
@@ -166,6 +210,8 @@ config MEMORY_START
config MEMORY_SIZE
hex "Physical memory size"
+ default "0x80000000" if MACH_LAGER
+ default "0x40000000" if MACH_APE6EVM
default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
MACH_ARMADILLO800EVA
default "0x1e000000" if MACH_KOTA2
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 709b9b421f93..068f1dadc46b 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -37,13 +37,18 @@ obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
# Board objects
obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
+obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
+obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
+obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
+obj-$(CONFIG_MACH_LAGER) += board-lager.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
+obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
# Framework support
obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a19c48c..c7540710906f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,8 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
if (brightness == 0) {
/* Reset the chip */
- gpio_set_value(GPIO_PORT235, 0);
+ gpio_set_value(235, 0);
mdelay(24);
- gpio_set_value(GPIO_PORT235, 1);
+ gpio_set_value(235, 1);
return 0;
}
@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
- .cd_gpio = GPIO_PORT251,
+ .cd_gpio = 251,
};
static struct resource sdhi0_resources[] = {
@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
static struct fixed_voltage_config cn4_power_info = {
.supply_name = "CN4 SD/MMC Vdd",
.microvolts = 3300000,
- .gpio = GPIO_PORT114,
+ .gpio = 114,
.enable_high = 1,
.init_data = &cn4_power_init_data,
};
@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
static int power_gpio = -EINVAL;
if (power_gpio < 0) {
- int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
+ int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
"sdhi1_power");
if (!ret)
- power_gpio = GPIO_PORT114;
+ power_gpio = 114;
}
/*
@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
* regulator driver. We have to live with the race in case the driver
* gets unloaded and the GPIO freed between these two steps.
*/
- gpio_set_value(GPIO_PORT114, state);
+ gpio_set_value(114, state);
}
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map ag5evm_pinctrl_map[] = {
+ /* FSIA */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_mclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_sclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_out", "fsia"),
+ /* I2C2 & I2C3 */
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
+ "i2c2_0", "i2c2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+ "i2c3_0", "i2c3"),
+ /* IrDA */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
+ "irda_0", "irda"),
+ /* KEYSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out04", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out5", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out6_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out7_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out8_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out9_2", "keysc"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", pin_pullup_conf),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
+ /* SCIFA2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_data_0", "scifa2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_ctrl_0", "scifa2"),
+ /* SDHI0 (CN15 [SD I/F]) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 (CN4 [WLAN I/F]) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "PORT263", pin_pullup_conf),
+};
+
static void __init ag5evm_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(ag5evm_pinctrl_map,
+ ARRAY_SIZE(ag5evm_pinctrl_map));
sh73a0_pinmux_init();
- /* enable SCIFA2 */
- gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
- gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
- /* enable KEYSC */
- gpio_request(GPIO_FN_KEYIN0_PU, NULL);
- gpio_request(GPIO_FN_KEYIN1_PU, NULL);
- gpio_request(GPIO_FN_KEYIN2_PU, NULL);
- gpio_request(GPIO_FN_KEYIN3_PU, NULL);
- gpio_request(GPIO_FN_KEYIN4_PU, NULL);
- gpio_request(GPIO_FN_KEYIN5_PU, NULL);
- gpio_request(GPIO_FN_KEYIN6_PU, NULL);
- gpio_request(GPIO_FN_KEYIN7_PU, NULL);
- gpio_request(GPIO_FN_KEYOUT0, NULL);
- gpio_request(GPIO_FN_KEYOUT1, NULL);
- gpio_request(GPIO_FN_KEYOUT2, NULL);
- gpio_request(GPIO_FN_KEYOUT3, NULL);
- gpio_request(GPIO_FN_KEYOUT4, NULL);
- gpio_request(GPIO_FN_KEYOUT5, NULL);
- gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
- gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
- gpio_request(GPIO_FN_KEYOUT8, NULL);
- gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
-
- /* enable I2C channel 2 and 3 */
- gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
- gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
- gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
- gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
-
/* enable MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
- gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
+ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* enable SMSC911X */
- gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
- gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
- /* FSI A */
- gpio_request(GPIO_FN_FSIACK, NULL);
- gpio_request(GPIO_FN_FSIAILR, NULL);
- gpio_request(GPIO_FN_FSIAIBT, NULL);
- gpio_request(GPIO_FN_FSIAISLD, NULL);
- gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
- /* IrDA */
- gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
- gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
- gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
+ gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* LCD panel */
- gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+ gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
mdelay(1);
- gpio_set_value(GPIO_PORT217, 1);
+ gpio_set_value(217, 1);
mdelay(100);
/* LCD backlight controller */
- gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
+ gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
lcd_backlight_set_brightness(0);
- /* enable SDHI0 on CN15 [SD I/F] */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
- /* enable SDHI1 on CN4 [WLAN I/F] */
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
-
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259a0daf..45f78cadec1d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/io.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
+ * connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
- return !gpio_get_value(GPIO_PORT41);
+ return !gpio_get_value(41);
}
/* MERAM */
static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
- .gpio = GPIO_PORT185,
+ .gpio = 185,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
- .gpio = GPIO_PORT186,
+ .gpio = 186,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
- .gpio = GPIO_PORT187,
+ .gpio = 187,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
- .gpio = GPIO_PORT188,
+ .gpio = 188,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@@ -1026,10 +1027,10 @@ out:
/* TouchScreen */
#ifdef CONFIG_AP4EVB_QHD
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
-# define GPIO_TSC_PORT GPIO_PORT123
+# define GPIO_TSC_PORT 123
#else /* WVGA */
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
-# define GPIO_TSC_PORT GPIO_PORT40
+# define GPIO_TSC_PORT 40
#endif
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
};
+static const struct pinctrl_map ap4evb_pinctrl_map[] = {
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_ctrl_0", "mmc0"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_ctrl", "sdhi1"),
+};
+
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define USCCR1 IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+ pinctrl_register_mappings(ap4evb_pinctrl_map,
+ ARRAY_SIZE(ap4evb_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable Debug switch (S6) */
- gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
- gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
-
- /* SDHI0 */
- gpio_request(GPIO_FN_SDHICD0, NULL);
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
- /* SDHI1 */
- gpio_request(GPIO_FN_SDHICMD1, NULL);
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHID1_3, NULL);
- gpio_request(GPIO_FN_SDHID1_2, NULL);
- gpio_request(GPIO_FN_SDHID1_1, NULL);
- gpio_request(GPIO_FN_SDHID1_0, NULL);
-
- /* MMCIF */
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request(GPIO_FN_MMCCLK0, NULL);
+ gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
+ gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* USB enable */
gpio_request(GPIO_FN_VBUS0_1, NULL);
@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
- gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
- gpio_request(GPIO_PORT9, NULL);
- gpio_request(GPIO_PORT10, NULL);
+ gpio_request(9, NULL);
+ gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
/* card detect pin for MMC slot (CN7) */
- gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
+ gpio_request_one(41, GPIOF_IN, NULL);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
- gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
- gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
+ gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
lcdc_info.clock_source = LCDC_CLK_BUS;
lcdc_info.ch[0].interface_type = RGB18;
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
new file mode 100644
index 000000000000..55b8c9fef954
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -0,0 +1,94 @@
+/*
+ * APE6EVM board support
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/smsc911x.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <mach/r8a73a4.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/* Dummy supplies, where voltage doesn't matter */
+static struct regulator_consumer_supply dummy_supplies[] = {
+ REGULATOR_SUPPLY("vddvario", "smsc911x"),
+ REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
+/* SMSC LAN9220 */
+static const struct resource lan9220_res[] = {
+ DEFINE_RES_MEM(0x08000000, 0x1000),
+ {
+ .start = irq_pin(40), /* IRQ40 */
+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
+ },
+};
+
+static const struct smsc911x_platform_config lan9220_data = {
+ .flags = SMSC911X_USE_32BIT,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+};
+
+static const struct pinctrl_map ape6evm_pinctrl_map[] = {
+ /* SCIFA0 console */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
+ "scifa0_data", "scifa0"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
+ "irqc_irq40", "irqc"),
+};
+
+static void __init ape6evm_add_standard_devices(void)
+{
+ r8a73a4_clock_init();
+ pinctrl_register_mappings(ape6evm_pinctrl_map,
+ ARRAY_SIZE(ape6evm_pinctrl_map));
+ r8a73a4_pinmux_init();
+ r8a73a4_add_standard_devices();
+
+ /* LAN9220 ethernet */
+ gpio_request_one(270, GPIOF_OUT_INIT_HIGH, NULL); /* smsc9220 RESET */
+
+ regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+
+ platform_device_register_resndata(&platform_bus, "smsc911x", -1,
+ lan9220_res, ARRAY_SIZE(lan9220_res),
+ &lan9220_data, sizeof(lan9220_data));
+}
+
+static const char *ape6evm_boards_compat_dt[] __initdata = {
+ "renesas,ape6evm",
+ NULL,
+};
+
+DT_MACHINE_START(APE6EVM_DT, "ape6evm")
+ .init_irq = irqchip_init,
+ .init_time = shmobile_timer_init,
+ .init_machine = ape6evm_add_standard_devices,
+ .dt_compat = ape6evm_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e451327278af..81db74acaa44 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -28,7 +28,10 @@
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
+#include <linux/regulator/driver.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
+#include <linux/regulator/gpio-regulator.h>
#include <linux/regulator/machine.h>
#include <linux/sh_eth.h>
#include <linux/videodev2.h>
@@ -227,7 +230,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
static int usbhsf_get_vbus(struct platform_device *pdev)
{
- return gpio_get_value(GPIO_PORT209);
+ return gpio_get_value(209);
}
static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -535,10 +538,10 @@ static struct platform_device hdmi_lcdc_device = {
{ .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
static struct gpio_keys_button gpio_buttons[] = {
- GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1),
- GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"),
- GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"),
- GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"),
+ GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
+ GPIO_KEY(KEY_BACK, 100, "SW4"),
+ GPIO_KEY(KEY_MENU, 97, "SW5"),
+ GPIO_KEY(KEY_HOME, 98, "SW6"),
};
static struct gpio_keys_platform_data gpio_key_info = {
@@ -554,15 +557,119 @@ static struct platform_device gpio_keys_device = {
},
};
-/* Fixed 3.3V regulator to be used by SDHI0, SDHI1, MMCIF */
-static struct regulator_consumer_supply fixed3v3_power_consumers[] =
-{
+/* Fixed 3.3V regulator to be used by SDHI1, MMCIF */
+static struct regulator_consumer_supply fixed3v3_power_consumers[] = {
+ REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
+ REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+/* Fixed 3.3V regulator to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] = {
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
+ .consumer_supplies = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+ .supply_name = "SDHI0 Vcc",
+ .microvolts = 3300000,
+ .gpio = GPIO_PORT75,
+ .enable_high = 1,
+ .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &vcc_sdhi0_info,
+ },
+};
+
+/* 1.8 / 3.3V SDHI0 VccQ regulator */
+static struct regulator_consumer_supply vccq_sdhi0_consumers[] = {
REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vccq_sdhi0_init_data = {
+ .constraints = {
+ .input_uV = 3300000,
+ .min_uV = 1800000,
+ .max_uV = 3300000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vccq_sdhi0_consumers),
+ .consumer_supplies = vccq_sdhi0_consumers,
+};
+
+static struct gpio vccq_sdhi0_gpios[] = {
+ {GPIO_PORT17, GPIOF_OUT_INIT_LOW, "vccq-sdhi0" },
+};
+
+static struct gpio_regulator_state vccq_sdhi0_states[] = {
+ { .value = 3300000, .gpios = (0 << 0) },
+ { .value = 1800000, .gpios = (1 << 0) },
+};
+
+static struct gpio_regulator_config vccq_sdhi0_info = {
+ .supply_name = "vqmmc",
+
+ .enable_gpio = GPIO_PORT74,
+ .enable_high = 1,
+ .enabled_at_boot = 0,
+
+ .gpios = vccq_sdhi0_gpios,
+ .nr_gpios = ARRAY_SIZE(vccq_sdhi0_gpios),
+
+ .states = vccq_sdhi0_states,
+ .nr_states = ARRAY_SIZE(vccq_sdhi0_states),
+
+ .type = REGULATOR_VOLTAGE,
+ .init_data = &vccq_sdhi0_init_data,
+};
+
+static struct platform_device vccq_sdhi0 = {
+ .name = "gpio-regulator",
+ .id = -1,
+ .dev = {
+ .platform_data = &vccq_sdhi0_info,
+ },
+};
+
+/* Fixed 3.3V regulator to be used by SDHI1 */
+static struct regulator_consumer_supply vcc_sdhi1_consumers[] = {
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
- REGULATOR_SUPPLY("vmmc", "sh_mmcif"),
- REGULATOR_SUPPLY("vqmmc", "sh_mmcif"),
+};
+
+static struct regulator_init_data vcc_sdhi1_init_data = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi1_consumers),
+ .consumer_supplies = vcc_sdhi1_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi1_info = {
+ .supply_name = "SDHI1 Vcc",
+ .microvolts = 3300000,
+ .gpio = GPIO_PORT16,
+ .enable_high = 1,
+ .init_data = &vcc_sdhi1_init_data,
+};
+
+static struct platform_device vcc_sdhi1 = {
+ .name = "reg-fixed-voltage",
+ .id = 2,
+ .dev = {
+ .platform_data = &vcc_sdhi1_info,
+ },
};
/* SDHI0 */
@@ -578,10 +685,10 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
- .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |\
- MMC_CAP_NEEDS_POLL,
- .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ MMC_CAP_POWER_OFF_CARD,
+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+ .cd_gpio = GPIO_PORT167,
};
static struct resource sdhi0_resources[] = {
@@ -620,9 +727,11 @@ static struct platform_device sdhi0_device = {
static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
- .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
- .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
- .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ MMC_CAP_POWER_OFF_CARD,
+ .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
+ /* Port72 cannot generate IRQs, will be used in polling mode. */
+ .cd_gpio = GPIO_PORT72,
};
static struct resource sdhi1_resources[] = {
@@ -656,10 +765,20 @@ static struct platform_device sdhi1_device = {
.resource = sdhi1_resources,
};
+static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_cd", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
+ "sdhi1_wp", "sdhi1"),
+};
+
/* MMCIF */
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
- .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
.caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_8_BIT_DATA |
MMC_CAP_NONREMOVABLE,
@@ -708,9 +827,9 @@ static int mt9t111_power(struct device *dev, int mode)
/* video1 (= CON1 camera) expect 24MHz */
clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
clk_enable(mclk);
- gpio_set_value(GPIO_PORT158, 1);
+ gpio_set_value(158, 1);
} else {
- gpio_set_value(GPIO_PORT158, 0);
+ gpio_set_value(158, 0);
clk_disable(mclk);
}
@@ -864,8 +983,8 @@ static struct platform_device fsi_hdmi_device = {
/* RTC: RTC connects i2c-gpio. */
static struct i2c_gpio_platform_data i2c_gpio_data = {
- .sda_pin = GPIO_PORT208,
- .scl_pin = GPIO_PORT91,
+ .sda_pin = 208,
+ .scl_pin = 91,
.udelay = 5, /* 100 kHz */
};
@@ -902,6 +1021,8 @@ static struct platform_device *eva_devices[] __initdata = {
&lcdc0_device,
&gpio_keys_device,
&sh_eth_device,
+ &vcc_sdhi0,
+ &vccq_sdhi0,
&sdhi0_device,
&sh_mmcif_device,
&hdmi_device,
@@ -914,6 +1035,28 @@ static struct platform_device *eva_devices[] __initdata = {
&i2c_gpio_device,
};
+static const struct pinctrl_map eva_pinctrl_map[] = {
+ /* LCD0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_data24_0", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_lclk_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_sync", "lcd0"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+ "mmc0_data8_1", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
+ "mmc0_ctrl_1", "mmc0"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
+ "sdhi0_wp", "sdhi0"),
+};
+
static void __init eva_clock_init(void)
{
struct clk *system = clk_get(NULL, "system_clk");
@@ -961,6 +1104,8 @@ static void __init eva_init(void)
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
+ pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
+
r8a7740_pinmux_init();
r8a7740_meram_workaround();
@@ -970,42 +1115,13 @@ static void __init eva_init(void)
/* LCDC0 */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
- gpio_request(GPIO_FN_LCD0_D0, NULL);
- gpio_request(GPIO_FN_LCD0_D1, NULL);
- gpio_request(GPIO_FN_LCD0_D2, NULL);
- gpio_request(GPIO_FN_LCD0_D3, NULL);
- gpio_request(GPIO_FN_LCD0_D4, NULL);
- gpio_request(GPIO_FN_LCD0_D5, NULL);
- gpio_request(GPIO_FN_LCD0_D6, NULL);
- gpio_request(GPIO_FN_LCD0_D7, NULL);
- gpio_request(GPIO_FN_LCD0_D8, NULL);
- gpio_request(GPIO_FN_LCD0_D9, NULL);
- gpio_request(GPIO_FN_LCD0_D10, NULL);
- gpio_request(GPIO_FN_LCD0_D11, NULL);
- gpio_request(GPIO_FN_LCD0_D12, NULL);
- gpio_request(GPIO_FN_LCD0_D13, NULL);
- gpio_request(GPIO_FN_LCD0_D14, NULL);
- gpio_request(GPIO_FN_LCD0_D15, NULL);
- gpio_request(GPIO_FN_LCD0_D16, NULL);
- gpio_request(GPIO_FN_LCD0_D17, NULL);
- gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
- gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
- gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
- gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
- gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
- gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
- gpio_request(GPIO_FN_LCD0_DCK, NULL);
- gpio_request(GPIO_FN_LCD0_VSYN, NULL);
- gpio_request(GPIO_FN_LCD0_HSYN, NULL);
- gpio_request(GPIO_FN_LCD0_DISP, NULL);
- gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
- gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
- gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
+
+ gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
/* Touchscreen */
gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
- gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
+ gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
/* GETHER */
gpio_request(GPIO_FN_ET_CRS, NULL);
@@ -1028,12 +1144,12 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_ET_RX_DV, NULL);
gpio_request(GPIO_FN_ET_RX_CLK, NULL);
- gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
+ gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
/* USB */
- gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
+ gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
- if (gpio_get_value(GPIO_PORT159)) {
+ if (gpio_get_value(159)) {
/* USB Host */
} else {
/* USB Func */
@@ -1042,47 +1158,15 @@ static void __init eva_init(void)
* OTOH, usbhs interrupt needs its value (HI/LOW) to decide
* USB connection/disconnection (usbhsf_get_vbus()).
* This means we needs to select GPIO_FN_IRQ7_PORT209 first,
- * and select GPIO_PORT209 here
+ * and select GPIO 209 here
*/
gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
- gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL);
+ gpio_request_one(209, GPIOF_IN, NULL);
platform_device_register(&usbhsf_device);
usb = &usbhsf_device;
}
- /* SDHI0 */
- gpio_request(GPIO_FN_SDHI0_CMD, NULL);
- gpio_request(GPIO_FN_SDHI0_CLK, NULL);
- gpio_request(GPIO_FN_SDHI0_D0, NULL);
- gpio_request(GPIO_FN_SDHI0_D1, NULL);
- gpio_request(GPIO_FN_SDHI0_D2, NULL);
- gpio_request(GPIO_FN_SDHI0_D3, NULL);
- gpio_request(GPIO_FN_SDHI0_WP, NULL);
-
- gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
- gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
- gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
-
- /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
-
- /*
- * MMCIF
- *
- * Here doesn't care SW1.4 status,
- * since CON2 is not mounted.
- */
- gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
- gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
- gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
- gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
- gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
- gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
- gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
- gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
- gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
- gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
-
/* CEU0 */
gpio_request(GPIO_FN_VIO0_D7, NULL);
gpio_request(GPIO_FN_VIO0_D6, NULL);
@@ -1099,10 +1183,10 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_VIO_CKO, NULL);
/* CON1/CON15 Camera */
- gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
- gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
+ gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
+ gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
/* see mt9t111_power() */
- gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
+ gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
/* FSI-WM8978 */
gpio_request(GPIO_FN_FSIAIBT, NULL);
@@ -1111,8 +1195,8 @@ static void __init eva_init(void)
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
- gpio_request(GPIO_PORT7, NULL);
- gpio_request(GPIO_PORT8, NULL);
+ gpio_request(7, NULL);
+ gpio_request(8, NULL);
gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
@@ -1129,29 +1213,21 @@ static void __init eva_init(void)
* DBGMD/LCDC0/FSIA MUX
* DBGMD_SELECT_B should be set after setting PFC Function.
*/
- gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL);
+ gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
/*
* We can switch CON8/CON14 by SW1.5,
* but it needs after DBGMD_SELECT_B
*/
- gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL);
- if (gpio_get_value(GPIO_PORT6)) {
+ gpio_request_one(6, GPIOF_IN, NULL);
+ if (gpio_get_value(6)) {
/* CON14 enable */
} else {
/* CON8 (SDHI1) enable */
- gpio_request(GPIO_FN_SDHI1_CLK, NULL);
- gpio_request(GPIO_FN_SDHI1_CMD, NULL);
- gpio_request(GPIO_FN_SDHI1_D0, NULL);
- gpio_request(GPIO_FN_SDHI1_D1, NULL);
- gpio_request(GPIO_FN_SDHI1_D2, NULL);
- gpio_request(GPIO_FN_SDHI1_D3, NULL);
- gpio_request(GPIO_FN_SDHI1_CD, NULL);
- gpio_request(GPIO_FN_SDHI1_WP, NULL);
-
- /* SDSLOT2_PON */
- gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL);
+ pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
+ ARRAY_SIZE(eva_sdhi1_pinctrl_map));
+ platform_device_register(&vcc_sdhi1);
platform_device_register(&sdhi1_device);
}
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
new file mode 100644
index 000000000000..56ab56ed5f59
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -0,0 +1,43 @@
+/*
+ * Bock-W board support
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/platform_device.h>
+#include <mach/common.h>
+#include <mach/r8a7778.h>
+#include <asm/mach/arch.h>
+
+static void __init bockw_init(void)
+{
+ r8a7778_clock_init();
+ r8a7778_add_standard_devices();
+}
+
+static const char *bockw_boards_compat_dt[] __initdata = {
+ "renesas,bockw",
+ NULL,
+};
+
+DT_MACHINE_START(BOCKW_DT, "bockw")
+ .init_early = r8a7778_init_delay,
+ .init_irq = r8a7778_init_irq_dt,
+ .init_machine = bockw_init,
+ .init_time = shmobile_timer_init,
+ .dt_compat = bockw_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f86691539..70d992c540ae 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
},
};
+static const struct pinctrl_map lcdc0_pinctrl_map[] = {
+ /* LCD0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_data24_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_lclk_1", "lcd0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
+ "lcd0_sync", "lcd0"),
+};
+
/*
* SMSC 9221
*/
@@ -392,8 +403,8 @@ static void __init bonito_init(void)
/*
* base board settings
*/
- gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
- if (!gpio_get_value(GPIO_PORT176)) {
+ gpio_request_one(176, GPIOF_IN, NULL);
+ if (!gpio_get_value(176)) {
u16 bsw2;
u16 bsw3;
u16 bsw4;
@@ -430,38 +441,11 @@ static void __init bonito_init(void)
*/
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
- gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
- gpio_request(GPIO_FN_LCD0_D0, NULL);
- gpio_request(GPIO_FN_LCD0_D1, NULL);
- gpio_request(GPIO_FN_LCD0_D2, NULL);
- gpio_request(GPIO_FN_LCD0_D3, NULL);
- gpio_request(GPIO_FN_LCD0_D4, NULL);
- gpio_request(GPIO_FN_LCD0_D5, NULL);
- gpio_request(GPIO_FN_LCD0_D6, NULL);
- gpio_request(GPIO_FN_LCD0_D7, NULL);
- gpio_request(GPIO_FN_LCD0_D8, NULL);
- gpio_request(GPIO_FN_LCD0_D9, NULL);
- gpio_request(GPIO_FN_LCD0_D10, NULL);
- gpio_request(GPIO_FN_LCD0_D11, NULL);
- gpio_request(GPIO_FN_LCD0_D12, NULL);
- gpio_request(GPIO_FN_LCD0_D13, NULL);
- gpio_request(GPIO_FN_LCD0_D14, NULL);
- gpio_request(GPIO_FN_LCD0_D15, NULL);
- gpio_request(GPIO_FN_LCD0_D16, NULL);
- gpio_request(GPIO_FN_LCD0_D17, NULL);
- gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
- gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
- gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
- gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
- gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
- gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
- gpio_request(GPIO_FN_LCD0_DCK, NULL);
- gpio_request(GPIO_FN_LCD0_VSYN, NULL);
- gpio_request(GPIO_FN_LCD0_HSYN, NULL);
- gpio_request(GPIO_FN_LCD0_DISP, NULL);
- gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
-
- gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
+ pinctrl_register_mappings(lcdc0_pinctrl_map,
+ ARRAY_SIZE(lcdc0_pinctrl_map));
+ gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
+
+ gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */
/* backlight on */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860403ef..ef5ca0ef0cb5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,8 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
@@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
static struct gpio_keys_button gpio_buttons[] = {
- GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
- GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
- GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
- GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
- GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
- GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
- GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
- GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
- /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
- GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
- /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
+ GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
+ GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
+ GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
+ GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
+ GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
+ GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
+ GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
+ GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
+ /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
+ GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
+ /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
};
static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
#define GPIO_LED(n, g) { .name = n, .gpio = g }
static struct gpio_led gpio_leds[] = {
- GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
- GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
- GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
+ GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
+ GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
+ GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
};
static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
.name = "V2513",
.pin_gpio_fn = GPIO_FN_TPU1TO2,
- .pin_gpio = GPIO_PORT153,
+ .pin_gpio = 153,
.channel_offset = 0x90,
.timer_bit = 2,
.max_brightness = 1000,
@@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
.name = "V2514",
.pin_gpio_fn = GPIO_FN_TPU4TO1,
- .pin_gpio = GPIO_PORT199,
+ .pin_gpio = 199,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
.name = "V2515",
.pin_gpio_fn = GPIO_FN_TPU2TO1,
- .pin_gpio = GPIO_PORT197,
+ .pin_gpio = 197,
.channel_offset = 0x50,
.timer_bit = 1,
.max_brightness = 1000,
@@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
.name = "KEYLED",
.pin_gpio_fn = GPIO_FN_TPU3TO0,
- .pin_gpio = GPIO_PORT163,
+ .pin_gpio = 163,
.channel_offset = 0x10,
.timer_bit = 0,
.max_brightness = 1000,
@@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
&sdhi1_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kota2_pinctrl_map[] = {
+ /* KEYSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out04", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out5", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out6_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out7_0", "keysc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_out8_0", "keysc"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
+ "keysc_in8", pin_pullup_conf),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
+ /* SCIFA2 (UART2) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_data_0", "scifa2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
+ "scifa2_ctrl_0", "scifa2"),
+ /* SCIFA4 (UART1) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_data", "scifa4"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_ctrl", "scifa4"),
+ /* SCIFB (BT) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_data_0", "scifb"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_clk_0", "scifb"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
+ "scifb_ctrl_0", "scifb"),
+ /* SDHI0 (microSD) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "PORT256", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "PORT251", pin_pullup_conf),
+ /* SDHI1 (BCM4330) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_ctrl", "sdhi1"),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "sdhi1_data4", pin_pullup_conf),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
+ "PORT263", pin_pullup_conf),
+ /* SMSC911X */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_data_0_7", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_data_8_15", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_cs5_a", "bsc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_we0", "bsc"),
+};
+
static void __init kota2_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,97 +522,16 @@ static void __init kota2_init(void)
ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(kota2_pinctrl_map,
+ ARRAY_SIZE(kota2_pinctrl_map));
sh73a0_pinmux_init();
- /* SCIFA2 (UART2) */
- gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
- gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
- gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
-
- /* SCIFA4 (UART1) */
- gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
- gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
-
/* SMSC911X */
- gpio_request(GPIO_FN_D0_NAF0, NULL);
- gpio_request(GPIO_FN_D1_NAF1, NULL);
- gpio_request(GPIO_FN_D2_NAF2, NULL);
- gpio_request(GPIO_FN_D3_NAF3, NULL);
- gpio_request(GPIO_FN_D4_NAF4, NULL);
- gpio_request(GPIO_FN_D5_NAF5, NULL);
- gpio_request(GPIO_FN_D6_NAF6, NULL);
- gpio_request(GPIO_FN_D7_NAF7, NULL);
- gpio_request(GPIO_FN_D8_NAF8, NULL);
- gpio_request(GPIO_FN_D9_NAF9, NULL);
- gpio_request(GPIO_FN_D10_NAF10, NULL);
- gpio_request(GPIO_FN_D11_NAF11, NULL);
- gpio_request(GPIO_FN_D12_NAF12, NULL);
- gpio_request(GPIO_FN_D13_NAF13, NULL);
- gpio_request(GPIO_FN_D14_NAF14, NULL);
- gpio_request(GPIO_FN_D15_NAF15, NULL);
- gpio_request(GPIO_FN_CS5A_, NULL);
- gpio_request(GPIO_FN_WE0__FWE, NULL);
- gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
- gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
-
- /* KEYSC */
- gpio_request(GPIO_FN_KEYIN0_PU, NULL);
- gpio_request(GPIO_FN_KEYIN1_PU, NULL);
- gpio_request(GPIO_FN_KEYIN2_PU, NULL);
- gpio_request(GPIO_FN_KEYIN3_PU, NULL);
- gpio_request(GPIO_FN_KEYIN4_PU, NULL);
- gpio_request(GPIO_FN_KEYIN5_PU, NULL);
- gpio_request(GPIO_FN_KEYIN6_PU, NULL);
- gpio_request(GPIO_FN_KEYIN7_PU, NULL);
- gpio_request(GPIO_FN_KEYOUT0, NULL);
- gpio_request(GPIO_FN_KEYOUT1, NULL);
- gpio_request(GPIO_FN_KEYOUT2, NULL);
- gpio_request(GPIO_FN_KEYOUT3, NULL);
- gpio_request(GPIO_FN_KEYOUT4, NULL);
- gpio_request(GPIO_FN_KEYOUT5, NULL);
- gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
- gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
- gpio_request(GPIO_FN_KEYOUT8, NULL);
+ gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
+ gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
-
- /* SDHI0 (microSD) */
- gpio_request(GPIO_FN_SDHICD0_PU, NULL);
- gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
-
- /* SCIFB (BT) */
- gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
- gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
- gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
- gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
- gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
-
- /* SDHI1 (BCM4330) */
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
- gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+ gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
new file mode 100644
index 000000000000..aefa50d385b7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -0,0 +1,107 @@
+/*
+ * KZM-A9-GT board support - Reference Device Tree Implementation
+ *
+ * Copyright (C) 2012 Horms Solutions Ltd.
+ *
+ * Based on board-kzm9g.c
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/input.h>
+#include <linux/of_platform.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <mach/sh73a0.h>
+#include <mach/common.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+ PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
+ "i2c3_1", "i2c3"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
+ /* SCIFA4 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_data", "scifa4"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_ctrl", "scifa4"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+ "sdhi2_data4", "sdhi2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
+ "sdhi2_ctrl", "sdhi2"),
+};
+
+static void __init kzm_init(void)
+{
+ sh73a0_add_standard_devices_dt();
+ pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
+ sh73a0_pinmux_init();
+
+ /* enable SD */
+ gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
+ gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+ gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
+
+#ifdef CONFIG_CACHE_L2X0
+ /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+ l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+#endif
+}
+
+static const char *kzm9g_boards_compat_dt[] __initdata = {
+ "renesas,kzm9g-reference",
+ NULL,
+};
+
+DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
+ .smp = smp_ops(sh73a0_smp_ops),
+ .map_io = sh73a0_map_io,
+ .init_early = sh73a0_init_delay,
+ .nr_irqs = NR_IRQS_LEGACY,
+ .init_irq = irqchip_init,
+ .init_machine = kzm_init,
+ .init_time = shmobile_timer_init,
+ .dt_compat = kzm9g_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index d34d12ae496b..e2d33243ef52 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,8 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -61,8 +63,8 @@
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
- REGULATOR_SUPPLY("vddvario", "smsc911x"),
- REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+ REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
+ REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};
/*
@@ -373,13 +375,64 @@ static struct platform_device mmc_device = {
.resource = sh_mmcif_resources,
};
-/* Fixed 2.8V regulators to be used by SDHI0 and SDHI2 */
-static struct regulator_consumer_supply fixed2v8_power_consumers[] =
+/* Fixed 3.3V regulators to be used by SDHI0 */
+static struct regulator_consumer_supply vcc_sdhi0_consumers[] =
{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static struct regulator_init_data vcc_sdhi0_init_data = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi0_consumers),
+ .consumer_supplies = vcc_sdhi0_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi0_info = {
+ .supply_name = "SDHI0 Vcc",
+ .microvolts = 3300000,
+ .gpio = 15,
+ .enable_high = 1,
+ .init_data = &vcc_sdhi0_init_data,
+};
+
+static struct platform_device vcc_sdhi0 = {
+ .name = "reg-fixed-voltage",
+ .id = 0,
+ .dev = {
+ .platform_data = &vcc_sdhi0_info,
+ },
+};
+
+/* Fixed 3.3V regulators to be used by SDHI2 */
+static struct regulator_consumer_supply vcc_sdhi2_consumers[] =
+{
REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
- REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
+};
+
+static struct regulator_init_data vcc_sdhi2_init_data = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vcc_sdhi2_consumers),
+ .consumer_supplies = vcc_sdhi2_consumers,
+};
+
+static struct fixed_voltage_config vcc_sdhi2_info = {
+ .supply_name = "SDHI2 Vcc",
+ .microvolts = 3300000,
+ .gpio = 14,
+ .enable_high = 1,
+ .init_data = &vcc_sdhi2_init_data,
+};
+
+static struct platform_device vcc_sdhi2 = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &vcc_sdhi2_info,
+ },
};
/* SDHI */
@@ -387,8 +440,8 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
- .tmio_caps = MMC_CAP_SD_HIGHSPEED,
- .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
+ MMC_CAP_POWER_OFF_CARD,
};
static struct resource sdhi0_resources[] = {
@@ -431,9 +484,8 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT |
TMIO_MMC_USE_GPIO_CD |
TMIO_MMC_WRPROTECT_DISABLE,
- .tmio_caps = MMC_CAP_SD_HIGHSPEED,
- .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
- .cd_gpio = GPIO_PORT13,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_POWER_OFF_CARD,
+ .cd_gpio = 13,
};
static struct resource sdhi2_resources[] = {
@@ -592,6 +644,8 @@ static struct platform_device *kzm_devices[] __initdata = {
&usbhs_device,
&lcdc_device,
&mmc_device,
+ &vcc_sdhi0,
+ &vcc_sdhi2,
&sdhi0_device,
&sdhi2_device,
&gpio_keys_device,
@@ -599,6 +653,64 @@ static struct platform_device *kzm_devices[] __initdata = {
&fsi_ak4648_device,
};
+static unsigned long pin_pullup_conf[] = {
+ PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
+};
+
+static const struct pinctrl_map kzm_pinctrl_map[] = {
+ /* FSIA (AK4648) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_mclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_sclk_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_in", "fsia"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
+ "fsia_data_out", "fsia"),
+ /* I2C3 */
+ PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
+ "i2c3_1", "i2c3"),
+ /* LCD */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+ "lcd_data24", "lcd"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
+ "lcd_sync", "lcd"),
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_ctrl_0", "mmc0"),
+ PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "PORT279", pin_pullup_conf),
+ PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
+ "mmc0_data8_0", pin_pullup_conf),
+ /* SCIFA4 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_data", "scifa4"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
+ "scifa4_ctrl", "scifa4"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+ "sdhi2_data4", "sdhi2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
+ "sdhi2_ctrl", "sdhi2"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
+ "bsc_cs4", "bsc"),
+ /* USB */
+ PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
+ "usb_vbus", "usb"),
+};
+
/*
* FIXME
*
@@ -654,106 +766,26 @@ device_initcall(as3711_enable_lcdc_backlight);
static void __init kzm_init(void)
{
- regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
+ regulator_register_always_on(2, "fixed-1.8V", fixed1v8_power_consumers,
ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
- regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
- ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
- regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+ regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
- sh73a0_pinmux_init();
-
- /* enable SCIFA4 */
- gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
- gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
- gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
+ pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
- /* CS4 for SMSC/USB */
- gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
+ sh73a0_pinmux_init();
/* SMSC */
- gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
+ gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
- gpio_request(GPIO_FN_LCDD23, NULL);
- gpio_request(GPIO_FN_LCDD22, NULL);
- gpio_request(GPIO_FN_LCDD21, NULL);
- gpio_request(GPIO_FN_LCDD20, NULL);
- gpio_request(GPIO_FN_LCDD19, NULL);
- gpio_request(GPIO_FN_LCDD18, NULL);
- gpio_request(GPIO_FN_LCDD17, NULL);
- gpio_request(GPIO_FN_LCDD16, NULL);
- gpio_request(GPIO_FN_LCDD15, NULL);
- gpio_request(GPIO_FN_LCDD14, NULL);
- gpio_request(GPIO_FN_LCDD13, NULL);
- gpio_request(GPIO_FN_LCDD12, NULL);
- gpio_request(GPIO_FN_LCDD11, NULL);
- gpio_request(GPIO_FN_LCDD10, NULL);
- gpio_request(GPIO_FN_LCDD9, NULL);
- gpio_request(GPIO_FN_LCDD8, NULL);
- gpio_request(GPIO_FN_LCDD7, NULL);
- gpio_request(GPIO_FN_LCDD6, NULL);
- gpio_request(GPIO_FN_LCDD5, NULL);
- gpio_request(GPIO_FN_LCDD4, NULL);
- gpio_request(GPIO_FN_LCDD3, NULL);
- gpio_request(GPIO_FN_LCDD2, NULL);
- gpio_request(GPIO_FN_LCDD1, NULL);
- gpio_request(GPIO_FN_LCDD0, NULL);
- gpio_request(GPIO_FN_LCDDISP, NULL);
- gpio_request(GPIO_FN_LCDDCK, NULL);
-
- gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
- gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
+ gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
+ gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
/* Touchscreen */
- gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
-
- /* enable MMCIF */
- gpio_request(GPIO_FN_MMCCLK0, NULL);
- gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
- gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
+ gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
/* enable SD */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICD0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
- gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
- /* enable Micro SD */
- gpio_request(GPIO_FN_SDHID2_0, NULL);
- gpio_request(GPIO_FN_SDHID2_1, NULL);
- gpio_request(GPIO_FN_SDHID2_2, NULL);
- gpio_request(GPIO_FN_SDHID2_3, NULL);
- gpio_request(GPIO_FN_SDHICMD2, NULL);
- gpio_request(GPIO_FN_SDHICLK2, NULL);
- gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
-
- /* I2C 3 */
- gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
- gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
-
- /* enable FSI2 port A (ak4648) */
- gpio_request(GPIO_FN_FSIACK, NULL);
- gpio_request(GPIO_FN_FSIAILR, NULL);
- gpio_request(GPIO_FN_FSIAIBT, NULL);
- gpio_request(GPIO_FN_FSIAISLD, NULL);
- gpio_request(GPIO_FN_FSIAOSLD, NULL);
-
- /* enable USB */
- gpio_request(GPIO_FN_VBUS_0, NULL);
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
new file mode 100644
index 000000000000..ea6f9e5d3500
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -0,0 +1,46 @@
+/*
+ * Lager board support
+ *
+ * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irqchip.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <mach/common.h>
+#include <mach/r8a7790.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+static void __init lager_add_standard_devices(void)
+{
+ r8a7790_clock_init();
+ r8a7790_add_standard_devices();
+}
+
+static const char *lager_boards_compat_dt[] __initdata = {
+ "renesas,lager",
+ NULL,
+};
+
+DT_MACHINE_START(LAGER_DT, "lager")
+ .init_irq = irqchip_init,
+ .init_time = shmobile_timer_init,
+ .init_machine = lager_add_standard_devices,
+ .dt_compat = lager_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a585ff0..5b452e1e7d8a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/sh_flctl.h>
+#include <linux/pinctrl/machine.h>
#include <linux/pm_clock.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
@@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
static int mackerel_set_brightness(int brightness)
{
- gpio_set_value(GPIO_PORT31, brightness);
+ gpio_set_value(31, brightness);
return 0;
}
@@ -819,22 +820,22 @@ static struct platform_device usbhs1_device = {
static struct gpio_led mackerel_leds[] = {
{
.name = "led0",
- .gpio = GPIO_PORT0,
+ .gpio = 0,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
- .gpio = GPIO_PORT1,
+ .gpio = 1,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
- .gpio = GPIO_PORT2,
+ .gpio = 2,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
- .gpio = GPIO_PORT159,
+ .gpio = 159,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
@@ -962,40 +963,27 @@ static struct platform_device nand_flash_device = {
},
};
-/*
- * The card detect pin of the top SD/MMC slot (CN7) is active low and is
- * connected to GPIO A22 of SH7372 (GPIO_PORT41).
- */
-static int slot_cn7_get_cd(struct platform_device *pdev)
-{
- return !gpio_get_value(GPIO_PORT41);
-}
-
/* SDHI0 */
static struct sh_mobile_sdhi_info sdhi0_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
.tmio_flags = TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
- .cd_gpio = GPIO_PORT172,
+ .cd_gpio = 172,
};
static struct resource sdhi0_resources[] = {
- [0] = {
+ {
.name = "SDHI0",
.start = 0xe6850000,
.end = 0xe68500ff,
.flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
+ }, {
+ .name = SH_MOBILE_SDHI_IRQ_SDCARD,
.start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
.flags = IORESOURCE_IRQ,
- },
- [3] = {
+ }, {
+ .name = SH_MOBILE_SDHI_IRQ_SDIO,
.start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
.flags = IORESOURCE_IRQ,
},
@@ -1011,36 +999,30 @@ static struct platform_device sdhi0_device = {
},
};
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
/* SDHI1 */
+
+/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
- .tmio_ocr_mask = MMC_VDD_165_195,
- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
+ .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_NEEDS_POLL,
- .get_cd = slot_cn7_get_cd,
+ .cd_gpio = 41,
};
static struct resource sdhi1_resources[] = {
- [0] = {
+ {
.name = "SDHI1",
.start = 0xe6860000,
.end = 0xe68600ff,
.flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
- .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
+ }, {
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
.start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
.flags = IORESOURCE_IRQ,
- },
- [3] = {
+ }, {
.name = SH_MOBILE_SDHI_IRQ_SDIO,
.start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
.flags = IORESOURCE_IRQ,
@@ -1058,43 +1040,32 @@ static struct platform_device sdhi1_device = {
};
#endif
+/* SDHI2 */
+
/*
* The card detect pin of the top SD/MMC slot (CN23) is active low and is
- * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162).
+ * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
*/
-static int slot_cn23_get_cd(struct platform_device *pdev)
-{
- return !gpio_get_value(GPIO_PORT162);
-}
-
-/* SDHI2 */
static struct sh_mobile_sdhi_info sdhi2_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
.dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
- .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
+ .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
MMC_CAP_NEEDS_POLL,
- .get_cd = slot_cn23_get_cd,
+ .cd_gpio = 162,
};
static struct resource sdhi2_resources[] = {
- [0] = {
+ {
.name = "SDHI2",
.start = 0xe6870000,
.end = 0xe68700ff,
.flags = IORESOURCE_MEM,
- },
- [1] = {
- .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
- .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
- .flags = IORESOURCE_IRQ,
- },
- [2] = {
+ }, {
.name = SH_MOBILE_SDHI_IRQ_SDCARD,
.start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
.flags = IORESOURCE_IRQ,
- },
- [3] = {
+ }, {
.name = SH_MOBILE_SDHI_IRQ_SDIO,
.start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
.flags = IORESOURCE_IRQ,
@@ -1112,6 +1083,7 @@ static struct platform_device sdhi2_device = {
};
/* SH_MMCIF */
+#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
static struct resource sh_mmcif_resources[] = {
[0] = {
.name = "MMCIF",
@@ -1133,11 +1105,12 @@ static struct resource sh_mmcif_resources[] = {
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
- .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
.caps = MMC_CAP_4_BIT_DATA |
MMC_CAP_8_BIT_DATA |
MMC_CAP_NEEDS_POLL,
- .get_cd = slot_cn7_get_cd,
+ .use_cd_gpio = true,
+ /* card detect pin for SD/MMC slot (CN7) */
+ .cd_gpio = 41,
.slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
.slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
};
@@ -1153,7 +1126,7 @@ static struct platform_device sh_mmcif_device = {
.num_resources = ARRAY_SIZE(sh_mmcif_resources),
.resource = sh_mmcif_resources,
};
-
+#endif
static int mackerel_camera_add(struct soc_camera_device *icd);
static void mackerel_camera_del(struct soc_camera_device *icd);
@@ -1260,11 +1233,12 @@ static struct platform_device *mackerel_devices[] __initdata = {
&fsi_hdmi_device,
&nand_flash_device,
&sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
&sdhi1_device,
+#else
+ &sh_mmcif_device,
#endif
&sdhi2_device,
- &sh_mmcif_device,
&ceu_device,
&mackerel_camera,
&hdmi_device,
@@ -1328,6 +1302,34 @@ static struct i2c_board_info i2c1_devices[] = {
},
};
+static const struct pinctrl_map mackerel_pinctrl_map[] = {
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
+ "sdhi0_wp", "sdhi0"),
+ /* SDHI1 */
+#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_data4", "sdhi1"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
+ "sdhi1_ctrl", "sdhi1"),
+#else
+ /* MMCIF */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_data8_0", "mmc0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
+ "mmc0_ctrl_0", "mmc0"),
+#endif
+ /* SDHI2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+ "sdhi2_data4", "sdhi2"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
+ "sdhi2_ctrl", "sdhi2"),
+};
+
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define GPIO_PORT167CR IOMEM(0xE60520A7)
@@ -1344,10 +1346,11 @@ static void __init mackerel_init(void)
{ "A3SP", &usbhs0_device, },
{ "A3SP", &usbhs1_device, },
{ "A3SP", &nand_flash_device, },
- { "A3SP", &sh_mmcif_device, },
{ "A3SP", &sdhi0_device, },
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
+#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
{ "A3SP", &sdhi1_device, },
+#else
+ { "A3SP", &sh_mmcif_device, },
#endif
{ "A3SP", &sdhi2_device, },
{ "A4R", &ceu_device, },
@@ -1364,6 +1367,8 @@ static void __init mackerel_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
+ pinctrl_register_mappings(mackerel_pinctrl_map,
+ ARRAY_SIZE(mackerel_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
@@ -1403,9 +1408,9 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_LCDDCK, NULL);
/* backlight, off by default */
- gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL);
+ gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
- gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
+ gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
/* USBHS0 */
gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1426,10 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
- gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
+ gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
- gpio_request(GPIO_PORT9, NULL);
- gpio_request(GPIO_PORT10, NULL);
+ gpio_request(9, NULL);
+ gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
@@ -1453,53 +1458,9 @@ static void __init mackerel_init(void)
gpio_request(GPIO_FN_IRQ21, NULL);
irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
- /* enable SDHI0 */
- gpio_request(GPIO_FN_SDHIWP0, NULL);
- gpio_request(GPIO_FN_SDHICMD0, NULL);
- gpio_request(GPIO_FN_SDHICLK0, NULL);
- gpio_request(GPIO_FN_SDHID0_3, NULL);
- gpio_request(GPIO_FN_SDHID0_2, NULL);
- gpio_request(GPIO_FN_SDHID0_1, NULL);
- gpio_request(GPIO_FN_SDHID0_0, NULL);
-
/* SDHI0 PORT172 card-detect IRQ26 */
gpio_request(GPIO_FN_IRQ26_172, NULL);
-#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
- /* enable SDHI1 */
- gpio_request(GPIO_FN_SDHICMD1, NULL);
- gpio_request(GPIO_FN_SDHICLK1, NULL);
- gpio_request(GPIO_FN_SDHID1_3, NULL);
- gpio_request(GPIO_FN_SDHID1_2, NULL);
- gpio_request(GPIO_FN_SDHID1_1, NULL);
- gpio_request(GPIO_FN_SDHID1_0, NULL);
-#endif
- /* card detect pin for MMC slot (CN7) */
- gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
-
- /* enable SDHI2 */
- gpio_request(GPIO_FN_SDHICMD2, NULL);
- gpio_request(GPIO_FN_SDHICLK2, NULL);
- gpio_request(GPIO_FN_SDHID2_3, NULL);
- gpio_request(GPIO_FN_SDHID2_2, NULL);
- gpio_request(GPIO_FN_SDHID2_1, NULL);
- gpio_request(GPIO_FN_SDHID2_0, NULL);
-
- /* card detect pin for microSD slot (CN23) */
- gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL);
-
- /* MMCIF */
- gpio_request(GPIO_FN_MMCD0_0, NULL);
- gpio_request(GPIO_FN_MMCD0_1, NULL);
- gpio_request(GPIO_FN_MMCD0_2, NULL);
- gpio_request(GPIO_FN_MMCD0_3, NULL);
- gpio_request(GPIO_FN_MMCD0_4, NULL);
- gpio_request(GPIO_FN_MMCD0_5, NULL);
- gpio_request(GPIO_FN_MMCD0_6, NULL);
- gpio_request(GPIO_FN_MMCD0_7, NULL);
- gpio_request(GPIO_FN_MMCCMD0, NULL);
- gpio_request(GPIO_FN_MMCCLK0, NULL);
-
/* FLCTL */
gpio_request(GPIO_FN_D0_NAF0, NULL);
gpio_request(GPIO_FN_D1_NAF1, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
new file mode 100644
index 000000000000..480d882e42c7
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -0,0 +1,75 @@
+/*
+ * marzen board support - Reference DT implementation
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Copyright (C) 2011 Magnus Damm
+ * Copyright (C) 2013 Simon Horman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <linux/pinctrl/machine.h>
+#include <mach/r8a7779.h>
+#include <mach/common.h>
+#include <mach/irqs.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+ /* SCIF2 (CN18: DEBUG0) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+ "scif2_data_c", "scif2"),
+ /* SCIF4 (CN19: DEBUG1) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+ "scif4_data", "scif4"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_wp", "sdhi0"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "intc_irq1_b", "intc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "lbsc_ex_cs0", "lbsc"),
+};
+
+static void __init marzen_init(void)
+{
+ pinctrl_register_mappings(marzen_pinctrl_map,
+ ARRAY_SIZE(marzen_pinctrl_map));
+ r8a7779_pinmux_init();
+
+ r8a7779_add_standard_devices_dt();
+}
+
+static const char *marzen_boards_compat_dt[] __initdata = {
+ "renesas,marzen-reference",
+ NULL,
+};
+
+DT_MACHINE_START(MARZEN, "marzen")
+ .smp = smp_ops(r8a7779_smp_ops),
+ .map_io = r8a7779_map_io,
+ .init_early = r8a7779_init_delay,
+ .nr_irqs = NR_IRQS_LEGACY,
+ .init_irq = r8a7779_init_irq_dt,
+ .init_machine = marzen_init,
+ .init_time = shmobile_timer_init,
+ .dt_compat = marzen_boards_compat_dt,
+MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index cdcb799e802f..91052855cc12 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,13 +25,15 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/gpio.h>
+#include <linux/leds.h>
#include <linux/dma-mapping.h>
+#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/spi/spi.h>
#include <linux/spi/sh_hspi.h>
+#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/usb/otg.h>
@@ -66,7 +68,7 @@ static struct resource smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(28), /* IRQ 1 */
+ .start = gic_iid(0x3c), /* IRQ 1 */
.flags = IORESOURCE_IRQ,
},
};
@@ -96,7 +98,7 @@ static struct resource sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(104),
+ .start = gic_iid(0x88),
.flags = IORESOURCE_IRQ,
},
};
@@ -167,12 +169,43 @@ static struct platform_device usb_phy_device = {
.num_resources = ARRAY_SIZE(usb_phy_resources),
};
+/* LEDS */
+static struct gpio_led marzen_leds[] = {
+ {
+ .name = "led2",
+ .gpio = 157,
+ .default_state = LEDS_GPIO_DEFSTATE_ON,
+ }, {
+ .name = "led3",
+ .gpio = 158,
+ .default_state = LEDS_GPIO_DEFSTATE_ON,
+ }, {
+ .name = "led4",
+ .gpio = 159,
+ .default_state = LEDS_GPIO_DEFSTATE_ON,
+ },
+};
+
+static struct gpio_led_platform_data marzen_leds_pdata = {
+ .leds = marzen_leds,
+ .num_leds = ARRAY_SIZE(marzen_leds),
+};
+
+static struct platform_device leds_device = {
+ .name = "leds-gpio",
+ .id = 0,
+ .dev = {
+ .platform_data = &marzen_leds_pdata,
+ },
+};
+
static struct platform_device *marzen_devices[] __initdata = {
&eth_device,
&sdhi0_device,
&thermal_device,
&hspi_device,
&usb_phy_device,
+ &leds_device,
};
/* USB */
@@ -214,7 +247,7 @@ static struct resource ehci0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(44),
+ .start = gic_iid(0x4c),
.flags = IORESOURCE_IRQ,
},
};
@@ -238,7 +271,7 @@ static struct resource ehci1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(45),
+ .start = gic_iid(0x4d),
.flags = IORESOURCE_IRQ,
},
};
@@ -268,7 +301,7 @@ static struct resource ohci0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(44),
+ .start = gic_iid(0x4c),
.flags = IORESOURCE_IRQ,
},
};
@@ -292,7 +325,7 @@ static struct resource ohci1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = gic_spi(45),
+ .start = gic_iid(0x4d),
.flags = IORESOURCE_IRQ,
},
};
@@ -326,6 +359,41 @@ void __init marzen_init_late(void)
ARRAY_SIZE(marzen_late_devices));
}
+static const struct pinctrl_map marzen_pinctrl_map[] = {
+ /* HSPI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
+ "hspi0", "hspi0"),
+ /* SCIF2 (CN18: DEBUG0) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
+ "scif2_data_c", "scif2"),
+ /* SCIF4 (CN19: DEBUG1) */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
+ "scif4_data", "scif4"),
+ /* SDHI0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_data4", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_ctrl", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_cd", "sdhi0"),
+ PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
+ "sdhi0_wp", "sdhi0"),
+ /* SMSC */
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "intc_irq1_b", "intc"),
+ PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
+ "lbsc_ex_cs0", "lbsc"),
+ /* USB0 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+ "usb0", "usb0"),
+ /* USB1 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
+ "usb1", "usb1"),
+ /* USB2 */
+ PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
+ "usb2", "usb2"),
+};
+
static void __init marzen_init(void)
{
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -333,44 +401,10 @@ static void __init marzen_init(void)
regulator_register_fixed(1, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
+ pinctrl_register_mappings(marzen_pinctrl_map,
+ ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
- /* SCIF2 (CN18: DEBUG0) */
- gpio_request(GPIO_FN_TX2_C, NULL);
- gpio_request(GPIO_FN_RX2_C, NULL);
-
- /* SCIF4 (CN19: DEBUG1) */
- gpio_request(GPIO_FN_TX4, NULL);
- gpio_request(GPIO_FN_RX4, NULL);
-
- /* LAN89218 */
- gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
- gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
-
- /* SD0 (CN20) */
- gpio_request(GPIO_FN_SD0_CLK, NULL);
- gpio_request(GPIO_FN_SD0_CMD, NULL);
- gpio_request(GPIO_FN_SD0_DAT0, NULL);
- gpio_request(GPIO_FN_SD0_DAT1, NULL);
- gpio_request(GPIO_FN_SD0_DAT2, NULL);
- gpio_request(GPIO_FN_SD0_DAT3, NULL);
- gpio_request(GPIO_FN_SD0_CD, NULL);
- gpio_request(GPIO_FN_SD0_WP, NULL);
-
- /* HSPI 0 */
- gpio_request(GPIO_FN_HSPI_CLK0, NULL);
- gpio_request(GPIO_FN_HSPI_CS0, NULL);
- gpio_request(GPIO_FN_HSPI_TX0, NULL);
- gpio_request(GPIO_FN_HSPI_RX0, NULL);
-
- /* USB (CN21) */
- gpio_request(GPIO_FN_USB_OVC0, NULL);
- gpio_request(GPIO_FN_USB_OVC1, NULL);
- gpio_request(GPIO_FN_USB_OVC2, NULL);
-
- /* USB (CN22) */
- gpio_request(GPIO_FN_USB_PENC2, NULL);
-
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 5a879bbe145f..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
- GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
- GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
- GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
- GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
- GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
- GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
- GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
-
- GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
- GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
-
- GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
- GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
-
- GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
- GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
- GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
- GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
-
- GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
- GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
- GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
- GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
- GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
- GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
- GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
- GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
- GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
- GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
- GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
- GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
- GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
- GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
-
- GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
- GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
-
- GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
- GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
@@ -346,26 +307,6 @@ enum {
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
- /* SDHI0 */
- GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
- GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
- GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
-
- /* SDHI1 */
- GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
- GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
- GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
-
- /* SDHI2 */
- GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
- GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
-
- GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
- GPIO_FN_SDHI2_WP_PORT25,
-
- GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
- GPIO_FN_SDHI2_CD_PORT202,
-
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
@@ -417,21 +358,6 @@ enum {
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
- /* MMC */
- GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
- GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
- GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
- GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
- GPIO_FN_MMC0_CLK_PORT66,
- GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
-
- GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
- GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
- GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
- GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
- GPIO_FN_MMC1_CLK_PORT103,
- GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
-
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index af38750f38f7..945299ed1638 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,327 +4,6 @@
#include <linux/sh_clk.h>
#include <linux/pm_domain.h>
-/* Pin Function Controller:
- * GPIO_FN_xx - GPIO used to select pin function
- * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
- */
-enum {
- GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
- GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
- GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
- GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
- GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
- GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
- GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
- GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
-
- GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
- GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
- GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
- GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
- GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
- GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
- GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
- GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
-
- GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
- GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
- GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
- GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
- GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
- GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
- GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
- GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
-
- GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
- GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
- GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
- GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
- GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
- GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
- GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
- GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
-
- GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
- GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
- GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
- GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
- GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
- GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
- GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
- GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
-
- GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
- GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
- GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
- GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
- GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
- GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
- GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
- GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
-
- GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
- GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
- GPIO_GP_6_8,
-
- GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
- GPIO_FN_A19,
-
- /* IPSR0 */
- GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
- GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
- GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
- GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
- GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
- GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
- GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
- GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
- GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
- GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
- GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
- GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
- GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
- GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
- GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
- GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
-
- /* IPSR1 */
- GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
- GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
- GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
- GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
- GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
- GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
- GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
- GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
- GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
- GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
- GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
- GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
- GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
- GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
- GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
- GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
- GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
-
- /* IPSR2 */
- GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
- GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
- GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
- GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
- GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
- GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
- GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
- GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
- GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
- GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
- GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
- GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
- GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
- GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
- GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
- GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
- GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
- GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
- GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
- GPIO_FN_AUDATA2,
-
- /* IPSR3 */
- GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
- GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
- GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
- GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
- GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
- GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
- GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
- GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
- GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
- GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
- GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
- GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
- GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
- GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
- GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
- GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
- GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
- GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
- GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
-
- /* IPSR4 */
- GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
- GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
- GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
- GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
- GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
- GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
- GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
- GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
- GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
- GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
- GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
- GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
- GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
- GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
- GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
- GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
- GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
- GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
- GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
-
- /* IPSR5 */
- GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
- GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
- GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
- GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
- GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
- GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
- GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
- GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
- GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
- GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
- GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
- GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
- GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
- GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
- GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
- GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
- GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
- GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
- GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
- GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
- GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
- GPIO_FN_MOUT0,
-
- /* IPSR6 */
- GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
- GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
- GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
- GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
- GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
- GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
- GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
- GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
- GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
- GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
- GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
- GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
- GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
- GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
- GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
- GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
-
- /* IPSR7 */
- GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
- GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
- GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
- GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
- GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
- GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
- GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
- GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
- GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
- GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
- GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
- GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
- GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
- GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
- GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
- GPIO_FN_CTS1_B,
-
- /* IPSR8 */
- GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
- GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
- GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
- GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
- GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
- GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
- GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
- GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
- GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
- GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
- GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
- GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
- GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
- GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
- GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
- GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
- GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
- GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
- GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
-
- /* IPSR9 */
- GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
- GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
- GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
- GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
- GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
- GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
- GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
- GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
- GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
- GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
- GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
- GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
- GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
- GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
- GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
- GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
- GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
- GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
-
- /* IPSR10 */
- GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
- GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
- GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
- GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
- GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
- GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
- GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
- GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
- GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
- GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
- GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
- GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
- GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
- GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
- GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
- GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
- GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
- GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
- GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
-
- /* IPSR11 */
- GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
- GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
- GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
- GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
- GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
- GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
- GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
- GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
- GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
- GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
- GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
- GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
- GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
- GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
- GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
- GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
- GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
- GPIO_FN_HRTS0_B,
-
- /* IPSR12 */
- GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
- GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
- GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
- GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
- GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
- GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
- GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
- GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
- GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
-};
-
struct platform_device;
struct r8a7779_pm_ch {
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index f0ea60d6648a..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
- /*
- * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
- * 90, 91, 92, 99)
- */
- GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
- GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
- GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
- GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
-
- /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
- GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
- GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
- GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
- GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
-
/* SPU2 (PORT 65) */
GPIO_FN_VINT_I,
@@ -416,20 +401,6 @@ enum {
/* HDMI (PORT 169, 170) */
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
- /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
- GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
- GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
- GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
- GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
-
- /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
- GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
- GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
-
- /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
- GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
- GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
-
/* SDENC see MSEL4CR 19 */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 936da1b4a9c5..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
/* Table 25-1 (Function 0-7) */
- GPIO_FN_VBUS_0,
- GPIO_FN_GPI0,
+ GPIO_FN_GPI0 = 310,
GPIO_FN_GPI1,
GPIO_FN_GPI2,
GPIO_FN_GPI3,
@@ -103,15 +102,11 @@ enum {
GPIO_FN_GPI5,
GPIO_FN_GPI6,
GPIO_FN_GPI7,
- GPIO_FN_SCIFA7_RXD,
- GPIO_FN_SCIFA7_CTS_,
GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
- GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \
+ GPIO_FN_GPO5,
GPIO_FN_PORT16_VIO_CKOR,
- GPIO_FN_SCIFA0_TXD,
- GPIO_FN_SCIFA7_TXD,
- GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
+ GPIO_FN_PORT19_VIO_CKO2,
GPIO_FN_GPO0,
GPIO_FN_GPO1,
GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -119,83 +114,44 @@ enum {
GPIO_FN_GPO4, GPIO_FN_STATUS2,
GPIO_FN_VINT,
GPIO_FN_TCKON,
- GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \
+ GPIO_FN_XDVFS1,
GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
- GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \
+ GPIO_FN_XDVFS2,
GPIO_FN_PORT28_TPU1TO1,
GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
- GPIO_FN_SCIFA4_TXD,
- GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
- GPIO_FN_SCIFA4_RTS_,
- GPIO_FN_SCIFA4_CTS_,
- GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
- GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
- GPIO_FN_FSIBOSLD,
- GPIO_FN_FSIBISLD,
+ GPIO_FN_XWUP,
GPIO_FN_VACK,
GPIO_FN_XTAL1L,
- GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2,
- GPIO_FN_SCIFA0_RXD,
- GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1,
- GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT,
- GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR,
- GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF,
- GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD,
- GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \
- GPIO_FN_FSIAOMC,
- GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
-
- GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
- GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
- GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
- GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
- GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
- GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
- GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
+ GPIO_FN_PORT49_IROUT,
+ GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
+
+ GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
+ GPIO_FN_BBIF2_TXD2,
+ GPIO_FN_TPU3TO3,
+ GPIO_FN_TPU3TO2,
+ GPIO_FN_TPU0TO0,
GPIO_FN_A0, GPIO_FN_BS_,
- GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2,
- GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1,
- GPIO_FN_A14, GPIO_FN_KEYOUT5,
- GPIO_FN_A15, GPIO_FN_KEYOUT4,
- GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1,
- GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC,
- GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK,
- GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD,
- GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK,
- GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC,
- GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0,
- GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1,
- GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD,
- GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2,
- GPIO_FN_A26, GPIO_FN_KEYIN6,
- GPIO_FN_KEYIN7,
- GPIO_FN_D0_NAF0,
- GPIO_FN_D1_NAF1,
- GPIO_FN_D2_NAF2,
- GPIO_FN_D3_NAF3,
- GPIO_FN_D4_NAF4,
- GPIO_FN_D5_NAF5,
- GPIO_FN_D6_NAF6,
- GPIO_FN_D7_NAF7,
- GPIO_FN_D8_NAF8,
- GPIO_FN_D9_NAF9,
- GPIO_FN_D10_NAF10,
- GPIO_FN_D11_NAF11,
- GPIO_FN_D12_NAF12,
- GPIO_FN_D13_NAF13,
- GPIO_FN_D14_NAF14,
- GPIO_FN_D15_NAF15,
- GPIO_FN_CS4_,
- GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
- GPIO_FN_CS5B_, GPIO_FN_FCE1_,
- GPIO_FN_CS6B_, GPIO_FN_DACK0,
- GPIO_FN_FCE0_, GPIO_FN_CS6A_,
+ GPIO_FN_A12, GPIO_FN_TPU4TO2,
+ GPIO_FN_A13, GPIO_FN_TPU0TO1,
+ GPIO_FN_A14,
+ GPIO_FN_A15,
+ GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
+ GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
+ GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
+ GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
+ GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
+ GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
+ GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
+ GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
+ GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
+ GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
+ GPIO_FN_A26,
+ GPIO_FN_FCE1_,
+ GPIO_FN_DACK0,
+ GPIO_FN_FCE0_,
GPIO_FN_WAIT_, GPIO_FN_DREQ0,
- GPIO_FN_RD__FSC,
- GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
- GPIO_FN_WE1_,
GPIO_FN_FRB,
GPIO_FN_CKO,
GPIO_FN_NBRSTOUT_,
@@ -204,145 +160,118 @@ enum {
GPIO_FN_BBIF2_RXD,
GPIO_FN_BBIF2_SYNC,
GPIO_FN_BBIF2_SCK,
- GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2,
- GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1,
- GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1,
- GPIO_FN_SCIFA3_TXD,
+ GPIO_FN_MFG3_IN2,
+ GPIO_FN_MFG3_IN1,
+ GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
- GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \
- GPIO_FN_PORT115_I2C_SCL3,
- GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
- GPIO_FN_PORT116_I2C_SDA3,
+ GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
+ GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
GPIO_FN_HSI_TX_FLAG,
- GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \
- GPIO_FN_LCD2D0,
-
- GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \
- GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1,
- GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10,
- GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \
- GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11,
- GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \
- GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12,
- GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13,
- GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14,
- GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15,
- GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16,
- GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17,
- GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \
- GPIO_FN_LCD2D6,
- GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \
- GPIO_FN_LCD2D7,
- GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8,
- GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9,
- GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \
- GPIO_FN_LCD2D2,
- GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \
- GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3,
- GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
- GPIO_FN_LCD2D4,
- GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
- GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
- GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
- GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
- GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
+ GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
+
+ GPIO_FN_VIO_HD,
+ GPIO_FN_VIO2_HD,
+ GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
+ GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
+ GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
+ GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
+ GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
+ GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
+ GPIO_FN_VIO_D6,
+ GPIO_FN_VIO_D7,
+ GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
+ GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
+ GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
+ GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
+ GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
+ GPIO_FN_VIO_D13,
+ GPIO_FN_VIO2_D5,
+ GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
+ GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
+ GPIO_FN_VIO2_D7,
+ GPIO_FN_VIO_CLK,
+ GPIO_FN_VIO2_CLK,
+ GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
GPIO_FN_VIO_CKO,
- GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \
- GPIO_FN_PORT149_KEYOUT9,
+ GPIO_FN_A27, GPIO_FN_MFG0_IN1,
GPIO_FN_MFG0_IN2,
GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
- GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0,
- GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1,
- GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2,
- GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD,
- GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3,
- GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI,
- GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
- GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
- GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
- GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
+ GPIO_FN_MSIOF2_MCK0,
+ GPIO_FN_MSIOF2_MCK1,
+ GPIO_FN_PORT156_MSIOF2_SS2,
+ GPIO_FN_PORT157_MSIOF2_RXD,
+ GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
+ GPIO_FN_NMI,
GPIO_FN_TPU3TO0,
- GPIO_FN_LCDD0,
- GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1,
- GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1,
- GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1,
- GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
- GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
+ GPIO_FN_BBIF2_TSYNC1,
+ GPIO_FN_BBIF2_TSCK1,
+ GPIO_FN_BBIF2_TXD1,
+ GPIO_FN_MFG2_OUT2,
GPIO_FN_TPU2TO1,
- GPIO_FN_LCDD6,
- GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
- GPIO_FN_LCDD8, GPIO_FN_D16,
- GPIO_FN_LCDD9, GPIO_FN_D17,
- GPIO_FN_LCDD10, GPIO_FN_D18,
- GPIO_FN_LCDD11, GPIO_FN_D19,
- GPIO_FN_LCDD12, GPIO_FN_D20,
- GPIO_FN_LCDD13, GPIO_FN_D21,
- GPIO_FN_LCDD14, GPIO_FN_D22,
- GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
- GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
- GPIO_FN_LCDD17, GPIO_FN_D25,
- GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
- GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
- GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
- GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
- GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
- GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
- GPIO_FN_LCDDCK, GPIO_FN_LCDWR_,
- GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \
- GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
- GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
+ GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
+ GPIO_FN_D16,
+ GPIO_FN_D17,
+ GPIO_FN_D18,
+ GPIO_FN_D19,
+ GPIO_FN_D20,
+ GPIO_FN_D21,
+ GPIO_FN_D22,
+ GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
+ GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
+ GPIO_FN_D25,
+ GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
+ GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
+ GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
+ GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
+ GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
+ GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
+ GPIO_FN_DACK2,
+ GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
+ GPIO_FN_DACK3,
GPIO_FN_PORT218_VIO_CKOR,
- GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
- GPIO_FN_LCD2DCK_2,
- GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
- GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
+ GPIO_FN_DREQ1,
GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
- GPIO_FN_PORT221_LCD2HSYN,
- GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \
- GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN,
-
- GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2,
- GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2,
- GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN,
- GPIO_FN_SCIFA1_RXD,
- GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1,
- GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2,
- GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_,
- GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2,
- GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
- GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
- GPIO_FN_LCD2D20,
+ GPIO_FN_DACK1, GPIO_FN_OVCN,
+ GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
+
+ GPIO_FN_OVCN2,
+ GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
+ GPIO_FN_IDIN,
+ GPIO_FN_MFG1_IN1,
+ GPIO_FN_MSIOF1_TXD,
+ GPIO_FN_MSIOF1_TSYNC,
+ GPIO_FN_MSIOF1_TSCK,
+ GPIO_FN_MSIOF1_RXD,
+ GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
- GPIO_FN_LCD2D21,
- GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2,
- GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2,
- GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22,
- GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23,
- GPIO_FN_SCIFA6_TXD,
- GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
+ GPIO_FN_MSIOF1_MCK0,
+ GPIO_FN_MSIOF1_MCK1,
+ GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
+ GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
+ GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
GPIO_FN_TPU4TO0,
- GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2,
- GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2,
- GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \
- GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD,
- GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \
- GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD,
- GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \
- GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0,
- GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \
- GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1,
- GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \
- GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \
- GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK,
+ GPIO_FN_MFG4_IN2,
+ GPIO_FN_PORT243_VIO_CKO2,
+ GPIO_FN_MFG2_IN1,
+ GPIO_FN_MSIOF2R_RXD,
+ GPIO_FN_MFG2_IN2,
+ GPIO_FN_MSIOF2R_TXD,
+ GPIO_FN_MFG1_OUT1,
+ GPIO_FN_TPU1TO0,
+ GPIO_FN_MFG3_OUT2,
+ GPIO_FN_TPU3TO1,
+ GPIO_FN_MFG2_OUT1,
+ GPIO_FN_TPU2TO0,
+ GPIO_FN_MSIOF2R_TSCK,
GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
- GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC,
+ GPIO_FN_MSIOF2R_TSYNC,
GPIO_FN_SDHICLK0,
GPIO_FN_SDHICD0,
GPIO_FN_SDHID0_0,
@@ -435,54 +364,12 @@ enum {
GPIO_FN_IRQ9_MEM_INT,
GPIO_FN_IRQ9_MCP_INT,
GPIO_FN_A11,
- GPIO_FN_KEYOUT8,
GPIO_FN_TPU4TO3,
GPIO_FN_RESETA_N_PU_ON,
GPIO_FN_RESETA_N_PU_OFF,
GPIO_FN_EDBGREQ_PD,
GPIO_FN_EDBGREQ_PU,
- /* Functions with pull-ups */
- GPIO_FN_KEYIN0_PU,
- GPIO_FN_KEYIN1_PU,
- GPIO_FN_KEYIN2_PU,
- GPIO_FN_KEYIN3_PU,
- GPIO_FN_KEYIN4_PU,
- GPIO_FN_KEYIN5_PU,
- GPIO_FN_KEYIN6_PU,
- GPIO_FN_KEYIN7_PU,
- GPIO_FN_SDHICD0_PU,
- GPIO_FN_SDHID0_0_PU,
- GPIO_FN_SDHID0_1_PU,
- GPIO_FN_SDHID0_2_PU,
- GPIO_FN_SDHID0_3_PU,
- GPIO_FN_SDHICMD0_PU,
- GPIO_FN_SDHIWP0_PU,
- GPIO_FN_SDHID1_0_PU,
- GPIO_FN_SDHID1_1_PU,
- GPIO_FN_SDHID1_2_PU,
- GPIO_FN_SDHID1_3_PU,
- GPIO_FN_SDHICMD1_PU,
- GPIO_FN_SDHID2_0_PU,
- GPIO_FN_SDHID2_1_PU,
- GPIO_FN_SDHID2_2_PU,
- GPIO_FN_SDHID2_3_PU,
- GPIO_FN_SDHICMD2_PU,
- GPIO_FN_MMCCMD0_PU,
- GPIO_FN_MMCCMD1_PU,
- GPIO_FN_MMCD0_0_PU,
- GPIO_FN_MMCD0_1_PU,
- GPIO_FN_MMCD0_2_PU,
- GPIO_FN_MMCD0_3_PU,
- GPIO_FN_MMCD0_4_PU,
- GPIO_FN_MMCD0_5_PU,
- GPIO_FN_MMCD0_6_PU,
- GPIO_FN_MMCD0_7_PU,
- GPIO_FN_FSIACK_PU,
- GPIO_FN_FSIAILR_PU,
- GPIO_FN_FSIAIBT_PU,
- GPIO_FN_FSIAISLD_PU,
-
/* end of GPIO */
GPIO_NR,
};
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35e71a0..a460ba3dedcb 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/gpio-rcar.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
.end = 0xfffc023b,
.flags = IORESOURCE_MEM,
},
- [1] = {
- .start = 0xffc40000,
- .end = 0xffc46fff,
- .flags = IORESOURCE_MEM,
- }
};
static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
.num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
};
+#define R8A7779_GPIO(idx, npins) \
+static struct resource r8a7779_gpio##idx##_resources[] = { \
+ [0] = { \
+ .start = 0xffc40000 + 0x1000 * (idx), \
+ .end = 0xffc4002b + 0x1000 * (idx), \
+ .flags = IORESOURCE_MEM, \
+ }, \
+ [1] = { \
+ .start = gic_iid(0xad + (idx)), \
+ .flags = IORESOURCE_IRQ, \
+ } \
+}; \
+ \
+static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
+ .gpio_base = 32 * (idx), \
+ .irq_base = 0, \
+ .number_of_pins = npins, \
+ .pctl_name = "pfc-r8a7779", \
+}; \
+ \
+static struct platform_device r8a7779_gpio##idx##_device = { \
+ .name = "gpio_rcar", \
+ .id = idx, \
+ .resource = r8a7779_gpio##idx##_resources, \
+ .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
+ .dev = { \
+ .platform_data = &r8a7779_gpio##idx##_platform_data, \
+ }, \
+}
+
+R8A7779_GPIO(0, 32);
+R8A7779_GPIO(1, 32);
+R8A7779_GPIO(2, 32);
+R8A7779_GPIO(3, 32);
+R8A7779_GPIO(4, 32);
+R8A7779_GPIO(5, 32);
+R8A7779_GPIO(6, 9);
+
+static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
+ &r8a7779_pfc_device,
+ &r8a7779_gpio0_device,
+ &r8a7779_gpio1_device,
+ &r8a7779_gpio2_device,
+ &r8a7779_gpio3_device,
+ &r8a7779_gpio4_device,
+ &r8a7779_gpio5_device,
+ &r8a7779_gpio6_device,
+};
+
void __init r8a7779_pinmux_init(void)
{
- platform_device_register(&r8a7779_pfc_device);
+ platform_add_devices(r8a7779_pinctrl_devices,
+ ARRAY_SIZE(r8a7779_pinctrl_devices));
}
static struct plat_sci_port scif0_platform_data = {
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
index 96c6c2634cb4..eef17dcc3a41 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -8,12 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7203_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe3a9f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7203", NULL, 0);
+ return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
+ ARRAY_SIZE(sh7203_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
index b1b7c1bae127..569decbd6d93 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -8,12 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7264_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe393f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7264", NULL, 0);
+ return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
+ ARRAY_SIZE(sh7264_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index dc2a86830456..4c17fb6970b1 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,12 +9,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
+#include <linux/ioport.h>
#include <linux/kernel.h>
#include <cpu/pfc.h>
+static struct resource sh7269_pfc_resources[] = {
+ [0] = {
+ .start = 0xfffe3800,
+ .end = 0xfffe391f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7269", NULL, 0);
+ return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
+ ARRAY_SIZE(sh7269_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
index 7d3744ac7b08..26e90a66ebb7 100644
--- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7720_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7720", NULL, 0);
+ return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
+ ARRAY_SIZE(sh7720_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index d9bcc4290997..271bbc864929 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -1,10 +1,20 @@
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7722_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405018f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7722", NULL, 0);
+ return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
+ ARRAY_SIZE(sh7722_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
index bcec7ad7f783..99c637d5bf7a 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7723_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7723", NULL, 0);
+ return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
+ ARRAY_SIZE(sh7723_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
index 5c3541d6aed8..63be4749e341 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -13,12 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7724_pfc_resources[] = {
+ [0] = {
+ .start = 0xa4050100,
+ .end = 0xa405016f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7724", NULL, 0);
+ return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
+ ARRAY_SIZE(sh7724_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index cda6bd177b8c..567745d44221 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -13,12 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7757_pfc_resources[] = {
+ [0] = {
+ .start = 0xffec0000,
+ .end = 0xffec008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7757", NULL, 0);
+ return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
+ ARRAY_SIZE(sh7757_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
index 01055b809f64..e336ab8b5125 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
@@ -8,13 +8,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7785_pfc_resources[] = {
+ [0] = {
+ .start = 0xffe70000,
+ .end = 0xffe7008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7785", NULL, 0);
+ return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
+ ARRAY_SIZE(sh7785_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
index 3061778d55da..9a459556a2f7 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -13,13 +13,23 @@
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
+static struct resource sh7786_pfc_resources[] = {
+ [0] = {
+ .start = 0xffcc0000,
+ .end = 0xffcc008f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-sh7786", NULL, 0);
+ return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
+ ARRAY_SIZE(sh7786_pfc_resources));
}
-
arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
index ace84acc55ea..444bf25c60fa 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -7,12 +7,23 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
+#include <linux/ioport.h>
#include <cpu/pfc.h>
-static int __init shx3_pinmux_setup(void)
+static struct resource shx3_pfc_resources[] = {
+ [0] = {
+ .start = 0xffc70000,
+ .end = 0xffc7001f,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static int __init plat_pinmux_setup(void)
{
- return sh_pfc_register("pfc-shx3", NULL, 0);
+ return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
+ ARRAY_SIZE(shx3_pfc_resources));
}
-arch_initcall(shx3_pinmux_setup);
+arch_initcall(plat_pinmux_setup);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf99f28..d766e3cbef18 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -204,6 +204,12 @@ config GPIO_PXA
help
Say yes here to support the PXA GPIO device
+config GPIO_RCAR
+ tristate "Renesas R-Car GPIO"
+ depends on ARM
+ help
+ Say yes here to support GPIO on Renesas R-Car SoCs.
+
config GPIO_SPEAR_SPICS
bool "ST SPEAr13xx SPI Chip Select as GPIO support"
depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc9fcb5..b41c74d45287 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
+obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b820869ca93c..06ed257c5d31 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
+#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
@@ -22,6 +23,7 @@
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
+#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
#include <asm/mach/irq.h>
@@ -51,8 +53,7 @@ struct pl061_gpio {
spinlock_t lock;
void __iomem *base;
- int irq_base;
- struct irq_chip_generic *irq_gc;
+ struct irq_domain *domain;
struct gpio_chip gc;
#ifdef CONFIG_PM
@@ -60,6 +61,17 @@ struct pl061_gpio {
#endif
};
+static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ /*
+ * Map back to global GPIO space and request muxing, the direction
+ * parameter does not matter for this controller.
+ */
+ int gpio = chip->base + offset;
+
+ return pinctrl_request_gpio(gpio);
+}
+
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -122,24 +134,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
- if (chip->irq_base <= 0)
- return -EINVAL;
-
- return chip->irq_base + offset;
+ return irq_create_mapping(chip->domain, offset);
}
static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
- struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
- struct pl061_gpio *chip = gc->private;
- int offset = d->irq - chip->irq_base;
+ struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+ int offset = irqd_to_hwirq(d);
unsigned long flags;
u8 gpiois, gpioibe, gpioiev;
if (offset < 0 || offset >= PL061_GPIO_NR)
return -EINVAL;
- raw_spin_lock_irqsave(&gc->lock, flags);
+ spin_lock_irqsave(&chip->lock, flags);
gpioiev = readb(chip->base + GPIOIEV);
@@ -168,7 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
writeb(gpioiev, chip->base + GPIOIEV);
- raw_spin_unlock_irqrestore(&gc->lock, flags);
+ spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@@ -192,31 +200,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
chained_irq_exit(irqchip, desc);
}
-static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
+static void pl061_irq_mask(struct irq_data *d)
{
- struct irq_chip_type *ct;
+ struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+ u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
+ u8 gpioie;
+
+ spin_lock(&chip->lock);
+ gpioie = readb(chip->base + GPIOIE) & ~mask;
+ writeb(gpioie, chip->base + GPIOIE);
+ spin_unlock(&chip->lock);
+}
+
+static void pl061_irq_unmask(struct irq_data *d)
+{
+ struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
+ u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
+ u8 gpioie;
+
+ spin_lock(&chip->lock);
+ gpioie = readb(chip->base + GPIOIE) | mask;
+ writeb(gpioie, chip->base + GPIOIE);
+ spin_unlock(&chip->lock);
+}
- chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
- chip->base, handle_simple_irq);
- chip->irq_gc->private = chip;
+static struct irq_chip pl061_irqchip = {
+ .name = "pl061 gpio",
+ .irq_mask = pl061_irq_mask,
+ .irq_unmask = pl061_irq_unmask,
+ .irq_set_type = pl061_irq_type,
+};
+
+static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct pl061_gpio *chip = d->host_data;
- ct = chip->irq_gc->chip_types;
- ct->chip.irq_mask = irq_gc_mask_clr_bit;
- ct->chip.irq_unmask = irq_gc_mask_set_bit;
- ct->chip.irq_set_type = pl061_irq_type;
- ct->chip.irq_set_wake = irq_gc_set_wake;
- ct->regs.mask = GPIOIE;
+ irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
+ "pl061");
+ irq_set_chip_data(virq, chip);
+ irq_set_irq_type(virq, IRQ_TYPE_NONE);
- irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
- IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
+ return 0;
}
+static const struct irq_domain_ops pl061_domain_ops = {
+ .map = pl061_irq_map,
+ .xlate = irq_domain_xlate_twocell,
+};
+
static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
struct pl061_platform_data *pdata = dev->platform_data;
struct pl061_gpio *chip;
- int ret, irq, i;
+ int ret, irq, i, irq_base;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
@@ -224,24 +262,31 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
if (pdata) {
chip->gc.base = pdata->gpio_base;
- chip->irq_base = pdata->irq_base;
- } else if (adev->dev.of_node) {
+ irq_base = pdata->irq_base;
+ if (irq_base <= 0)
+ return -ENODEV;
+ } else {
chip->gc.base = -1;
- chip->irq_base = 0;
- } else
- return -ENODEV;
+ irq_base = 0;
+ }
if (!devm_request_mem_region(dev, adev->res.start,
- resource_size(&adev->res), "pl061"))
+ resource_size(&adev->res), "pl061"))
return -EBUSY;
chip->base = devm_ioremap(dev, adev->res.start,
- resource_size(&adev->res));
- if (chip->base == NULL)
+ resource_size(&adev->res));
+ if (!chip->base)
return -ENOMEM;
+ chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
+ irq_base, &pl061_domain_ops, chip);
+ if (!chip->domain)
+ return -ENODEV;
+
spin_lock_init(&chip->lock);
+ chip->gc.request = pl061_gpio_request;
chip->gc.direction_input = pl061_direction_input;
chip->gc.direction_output = pl061_direction_output;
chip->gc.get = pl061_get_value;
@@ -259,12 +304,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
/*
* irq_chip support
*/
-
- if (chip->irq_base <= 0)
- return 0;
-
- pl061_init_gc(chip, chip->irq_base);
-
writeb(0, chip->base + GPIOIE); /* disable irqs */
irq = adev->irq[0];
if (irq < 0)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
new file mode 100644
index 000000000000..b4ca450947b8
--- /dev/null
+++ b/drivers/gpio/gpio-rcar.c
@@ -0,0 +1,396 @@
+/*
+ * Renesas R-Car GPIO Support
+ *
+ * Copyright (C) 2013 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+struct gpio_rcar_priv {
+ void __iomem *base;
+ spinlock_t lock;
+ struct gpio_rcar_config config;
+ struct platform_device *pdev;
+ struct gpio_chip gpio_chip;
+ struct irq_chip irq_chip;
+ struct irq_domain *irq_domain;
+};
+
+#define IOINTSEL 0x00
+#define INOUTSEL 0x04
+#define OUTDT 0x08
+#define INDT 0x0c
+#define INTDT 0x10
+#define INTCLR 0x14
+#define INTMSK 0x18
+#define MSKCLR 0x1c
+#define POSNEG 0x20
+#define EDGLEVEL 0x24
+#define FILONOFF 0x28
+
+static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
+{
+ return ioread32(p->base + offs);
+}
+
+static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
+ u32 value)
+{
+ iowrite32(value, p->base + offs);
+}
+
+static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
+ int bit, bool value)
+{
+ u32 tmp = gpio_rcar_read(p, offs);
+
+ if (value)
+ tmp |= BIT(bit);
+ else
+ tmp &= ~BIT(bit);
+
+ gpio_rcar_write(p, offs, tmp);
+}
+
+static void gpio_rcar_irq_disable(struct irq_data *d)
+{
+ struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+ gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_irq_enable(struct irq_data *d)
+{
+ struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+
+ gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
+}
+
+static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
+ unsigned int hwirq,
+ bool active_high_rising_edge,
+ bool level_trigger)
+{
+ unsigned long flags;
+
+ /* follow steps in the GPIO documentation for
+ * "Setting Edge-Sensitive Interrupt Input Mode" and
+ * "Setting Level-Sensitive Interrupt Input Mode"
+ */
+
+ spin_lock_irqsave(&p->lock, flags);
+
+ /* Configure postive or negative logic in POSNEG */
+ gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
+
+ /* Configure edge or level trigger in EDGLEVEL */
+ gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
+
+ /* Select "Interrupt Input Mode" in IOINTSEL */
+ gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
+
+ /* Write INTCLR in case of edge trigger */
+ if (!level_trigger)
+ gpio_rcar_write(p, INTCLR, BIT(hwirq));
+
+ spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
+{
+ struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
+ unsigned int hwirq = irqd_to_hwirq(d);
+
+ dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
+
+ switch (type & IRQ_TYPE_SENSE_MASK) {
+ case IRQ_TYPE_LEVEL_HIGH:
+ gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
+{
+ struct gpio_rcar_priv *p = dev_id;
+ u32 pending;
+ unsigned int offset, irqs_handled = 0;
+
+ while ((pending = gpio_rcar_read(p, INTDT))) {
+ offset = __ffs(pending);
+ gpio_rcar_write(p, INTCLR, BIT(offset));
+ generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
+ irqs_handled++;
+ }
+
+ return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
+}
+
+static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
+{
+ return container_of(chip, struct gpio_rcar_priv, gpio_chip);
+}
+
+static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
+ unsigned int gpio,
+ bool output)
+{
+ struct gpio_rcar_priv *p = gpio_to_priv(chip);
+ unsigned long flags;
+
+ /* follow steps in the GPIO documentation for
+ * "Setting General Output Mode" and
+ * "Setting General Input Mode"
+ */
+
+ spin_lock_irqsave(&p->lock, flags);
+
+ /* Configure postive logic in POSNEG */
+ gpio_rcar_modify_bit(p, POSNEG, gpio, false);
+
+ /* Select "General Input/Output Mode" in IOINTSEL */
+ gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
+
+ /* Select Input Mode or Output Mode in INOUTSEL */
+ gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
+
+ spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
+{
+ return pinctrl_request_gpio(chip->base + offset);
+}
+
+static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
+{
+ pinctrl_free_gpio(chip->base + offset);
+
+ /* Set the GPIO as an input to ensure that the next GPIO request won't
+ * drive the GPIO pin as an output.
+ */
+ gpio_rcar_config_general_input_output_mode(chip, offset, false);
+}
+
+static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ gpio_rcar_config_general_input_output_mode(chip, offset, false);
+ return 0;
+}
+
+static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
+{
+ return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
+}
+
+static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+ struct gpio_rcar_priv *p = gpio_to_priv(chip);
+ unsigned long flags;
+
+ spin_lock_irqsave(&p->lock, flags);
+ gpio_rcar_modify_bit(p, OUTDT, offset, value);
+ spin_unlock_irqrestore(&p->lock, flags);
+}
+
+static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
+ int value)
+{
+ /* write GPIO value to output before selecting output mode of pin */
+ gpio_rcar_set(chip, offset, value);
+ gpio_rcar_config_general_input_output_mode(chip, offset, true);
+ return 0;
+}
+
+static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+ return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
+}
+
+static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
+ irq_hw_number_t hw)
+{
+ struct gpio_rcar_priv *p = h->host_data;
+
+ dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
+
+ irq_set_chip_data(virq, h->host_data);
+ irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
+ set_irq_flags(virq, IRQF_VALID); /* kill me now */
+ return 0;
+}
+
+static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
+ .map = gpio_rcar_irq_domain_map,
+};
+
+static int gpio_rcar_probe(struct platform_device *pdev)
+{
+ struct gpio_rcar_config *pdata = pdev->dev.platform_data;
+ struct gpio_rcar_priv *p;
+ struct resource *io, *irq;
+ struct gpio_chip *gpio_chip;
+ struct irq_chip *irq_chip;
+ const char *name = dev_name(&pdev->dev);
+ int ret;
+
+ p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
+ if (!p) {
+ dev_err(&pdev->dev, "failed to allocate driver data\n");
+ ret = -ENOMEM;
+ goto err0;
+ }
+
+ /* deal with driver instance configuration */
+ if (pdata)
+ p->config = *pdata;
+
+ p->pdev = pdev;
+ platform_set_drvdata(pdev, p);
+ spin_lock_init(&p->lock);
+
+ io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+
+ if (!io || !irq) {
+ dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
+ ret = -EINVAL;
+ goto err0;
+ }
+
+ p->base = devm_ioremap_nocache(&pdev->dev, io->start,
+ resource_size(io));
+ if (!p->base) {
+ dev_err(&pdev->dev, "failed to remap I/O memory\n");
+ ret = -ENXIO;
+ goto err0;
+ }
+
+ gpio_chip = &p->gpio_chip;
+ gpio_chip->request = gpio_rcar_request;
+ gpio_chip->free = gpio_rcar_free;
+ gpio_chip->direction_input = gpio_rcar_direction_input;
+ gpio_chip->get = gpio_rcar_get;
+ gpio_chip->direction_output = gpio_rcar_direction_output;
+ gpio_chip->set = gpio_rcar_set;
+ gpio_chip->to_irq = gpio_rcar_to_irq;
+ gpio_chip->label = name;
+ gpio_chip->owner = THIS_MODULE;
+ gpio_chip->base = p->config.gpio_base;
+ gpio_chip->ngpio = p->config.number_of_pins;
+
+ irq_chip = &p->irq_chip;
+ irq_chip->name = name;
+ irq_chip->irq_mask = gpio_rcar_irq_disable;
+ irq_chip->irq_unmask = gpio_rcar_irq_enable;
+ irq_chip->irq_enable = gpio_rcar_irq_enable;
+ irq_chip->irq_disable = gpio_rcar_irq_disable;
+ irq_chip->irq_set_type = gpio_rcar_irq_set_type;
+ irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
+
+ p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
+ p->config.number_of_pins,
+ p->config.irq_base,
+ &gpio_rcar_irq_domain_ops, p);
+ if (!p->irq_domain) {
+ ret = -ENXIO;
+ dev_err(&pdev->dev, "cannot initialize irq domain\n");
+ goto err1;
+ }
+
+ if (devm_request_irq(&pdev->dev, irq->start,
+ gpio_rcar_irq_handler, 0, name, p)) {
+ dev_err(&pdev->dev, "failed to request IRQ\n");
+ ret = -ENOENT;
+ goto err1;
+ }
+
+ ret = gpiochip_add(gpio_chip);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add GPIO controller\n");
+ goto err1;
+ }
+
+ dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
+
+ /* warn in case of mismatch if irq base is specified */
+ if (p->config.irq_base) {
+ ret = irq_find_mapping(p->irq_domain, 0);
+ if (p->config.irq_base != ret)
+ dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
+ p->config.irq_base, ret);
+ }
+
+ ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
+ gpio_chip->base, gpio_chip->ngpio);
+ if (ret < 0)
+ dev_warn(&pdev->dev, "failed to add pin range\n");
+
+ return 0;
+
+err1:
+ irq_domain_remove(p->irq_domain);
+err0:
+ return ret;
+}
+
+static int gpio_rcar_remove(struct platform_device *pdev)
+{
+ struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
+ int ret;
+
+ ret = gpiochip_remove(&p->gpio_chip);
+ if (ret)
+ return ret;
+
+ irq_domain_remove(p->irq_domain);
+ return 0;
+}
+
+static struct platform_driver gpio_rcar_device_driver = {
+ .probe = gpio_rcar_probe,
+ .remove = gpio_rcar_remove,
+ .driver = {
+ .name = "gpio_rcar",
+ }
+};
+
+module_platform_driver(gpio_rcar_device_driver);
+
+MODULE_AUTHOR("Magnus Damm");
+MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index a71a54a3e3f7..465f4ca57e80 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -193,7 +193,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!np)
return;
- do {
+ for (;; index++) {
ret = of_parse_phandle_with_args(np, "gpio-ranges",
"#gpio-range-cells", index, &pinspec);
if (ret)
@@ -203,27 +203,15 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!pctldev)
break;
- /*
- * This assumes that the n GPIO pins are consecutive in the
- * GPIO number space, and that the pins are also consecutive
- * in their local number space. Currently it is not possible
- * to add different ranges for one and the same GPIO chip,
- * as the code assumes that we have one consecutive range
- * on both, mapping 1-to-1.
- *
- * TODO: make the OF bindings handle multiple sparse ranges
- * on the same GPIO chip.
- */
ret = gpiochip_add_pin_range(chip,
pinctrl_dev_get_devname(pctldev),
- 0, /* offset in gpiochip */
pinspec.args[0],
- pinspec.args[1]);
+ pinspec.args[1],
+ pinspec.args[2]);
if (ret)
break;
-
- } while (index++);
+ }
}
#else
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 34f51d2d90d2..5a690ce6d60d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -166,6 +166,7 @@ config PINCTRL_SINGLE
depends on OF
select PINMUX
select PINCONF
+ select GENERIC_PINCONF
help
This selects the device tree based generic pinctrl driver.
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index b0de6e7f1fdb..f8a632dc877b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -27,6 +27,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/machine.h>
+#include <asm-generic/gpio.h>
#include "core.h"
#include "devicetree.h"
#include "pinmux.h"
@@ -277,6 +278,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
}
/**
+ * pinctrl_ready_for_gpio_range() - check if other GPIO pins of
+ * the same GPIO chip are in range
+ * @gpio: gpio pin to check taken from the global GPIO pin space
+ *
+ * This function is complement of pinctrl_match_gpio_range(). If the return
+ * value of pinctrl_match_gpio_range() is NULL, this function could be used
+ * to check whether pinctrl device is ready or not. Maybe some GPIO pins
+ * of the same GPIO chip don't have back-end pinctrl interface.
+ * If the return value is true, it means that pinctrl device is ready & the
+ * certain GPIO pin doesn't have back-end pinctrl device. If the return value
+ * is false, it means that pinctrl device may not be ready.
+ */
+static bool pinctrl_ready_for_gpio_range(unsigned gpio)
+{
+ struct pinctrl_dev *pctldev;
+ struct pinctrl_gpio_range *range = NULL;
+ struct gpio_chip *chip = gpio_to_chip(gpio);
+
+ /* Loop over the pin controllers */
+ list_for_each_entry(pctldev, &pinctrldev_list, node) {
+ /* Loop over the ranges */
+ list_for_each_entry(range, &pctldev->gpio_ranges, node) {
+ /* Check if any gpio range overlapped with gpio chip */
+ if (range->base + range->npins - 1 < chip->base ||
+ range->base > chip->base + chip->ngpio - 1)
+ continue;
+ return true;
+ }
+ }
+ return false;
+}
+
+/**
* pinctrl_get_device_gpio_range() - find device for GPIO range
* @gpio: the pin to locate the pin controller for
* @outdev: the pin control device if found
@@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio)
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret) {
+ if (pinctrl_ready_for_gpio_range(gpio))
+ ret = 0;
mutex_unlock(&pinctrl_mutex);
return ret;
}
@@ -979,9 +1015,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data)
*/
void devm_pinctrl_put(struct pinctrl *p)
{
- WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
+ WARN_ON(devres_release(p->dev, devm_pinctrl_release,
devm_pinctrl_match, p));
- pinctrl_put(p);
}
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fd40a11ad645..c7b7cb477129 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
if (pctldev) {
- struct pinctrl_ops *ops = pctldev->desc->pctlops;
+ const struct pinctrl_ops *ops = pctldev->desc->pctlops;
ops->dt_free_map(pctldev, map, num_maps);
} else {
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
@@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
{
struct device_node *np_pctldev;
struct pinctrl_dev *pctldev;
- struct pinctrl_ops *ops;
+ const struct pinctrl_ops *ops;
int ret;
struct pinctrl_map *map;
unsigned num_maps;
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index c689c04a4f52..61149914882d 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
return;
}
-static struct pinconf_ops mvebu_pinconf_ops = {
+static const struct pinconf_ops mvebu_pinconf_ops = {
.pin_config_group_get = mvebu_pinconf_group_get,
.pin_config_group_set = mvebu_pinconf_group_set,
.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
@@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
-static struct pinmux_ops mvebu_pinmux_ops = {
+static const struct pinmux_ops mvebu_pinmux_ops = {
.get_functions_count = mvebu_pinmux_get_funcs_count,
.get_function_name = mvebu_pinmux_get_func_name,
.get_function_groups = mvebu_pinmux_get_groups,
@@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
-static struct pinctrl_ops mvebu_pinctrl_ops = {
+static const struct pinctrl_ops mvebu_pinctrl_ops = {
.get_groups_count = mvebu_pinctrl_get_groups_count,
.get_group_name = mvebu_pinctrl_get_group_name,
.get_group_pins = mvebu_pinctrl_get_group_pins,
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 06c304ac6f7d..9c436858812c 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -12,6 +12,7 @@
#define pr_fmt(fmt) "generic pinconfig core: " fmt
#include <linux/kernel.h>
+#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
@@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
}
}
+void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned long config)
+{
+ int i;
+
+ for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
+ if (pinconf_to_config_param(config) != conf_items[i].param)
+ continue;
+ seq_printf(s, "%s: 0x%x", conf_items[i].display,
+ pinconf_to_config_argument(config));
+ }
+}
+EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index ac8d382a79bb..dae927f91088 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -622,7 +622,7 @@ static const struct file_operations pinconf_dbg_pinname_fops = {
static int pinconf_dbg_state_print(struct seq_file *s, void *d)
{
if (strlen(dbg_state_name))
- seq_printf(s, "%s\n", dbg_pinname);
+ seq_printf(s, "%s\n", dbg_state_name);
else
seq_printf(s, "No pin state set\n");
return 0;
@@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
struct pinctrl_maps *maps_node;
struct pinctrl_map const *map;
struct pinctrl_dev *pctldev = NULL;
- struct pinconf_ops *confops = NULL;
+ const struct pinconf_ops *confops = NULL;
int i, j;
bool found = false;
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index e3ed8cb072a5..92c7267244d2 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -90,7 +90,7 @@ static inline void pinconf_init_device_debugfs(struct dentry *devroot,
* pin config.
*/
-#ifdef CONFIG_GENERIC_PINCONF
+#if defined(CONFIG_GENERIC_PINCONF) && defined(CONFIG_DEBUG_FS)
void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin);
@@ -98,6 +98,8 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
struct seq_file *s, const char *gname);
+void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+ struct seq_file *s, unsigned long config);
#else
static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
@@ -114,4 +116,10 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
return;
}
+static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
+ struct seq_file *s,
+ unsigned long config)
+{
+ return;
+}
#endif
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index caecdd373061..0cf3fa4a21ae 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -422,7 +422,7 @@ static u8 abx500_get_mode(struct pinctrl_dev *pctldev, struct gpio_chip *chip,
}
/* check if pin use AlternateFunction register */
- if ((af.alt_bit1 == UNUSED) && (af.alt_bit1 == UNUSED))
+ if ((af.alt_bit1 == UNUSED) && (af.alt_bit2 == UNUSED))
return mode;
/*
* if pin GPIOSEL bit is set and pin supports alternate function,
@@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
{
}
-static struct pinmux_ops abx500_pinmux_ops = {
+static const struct pinmux_ops abx500_pinmux_ops = {
.get_functions_count = abx500_pmx_get_funcs_cnt,
.get_function_name = abx500_pmx_get_func_name,
.get_function_groups = abx500_pmx_get_func_groups,
@@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
chip->base + offset - 1);
}
-static struct pinctrl_ops abx500_pinctrl_ops = {
+static const struct pinctrl_ops abx500_pinctrl_ops = {
.get_groups_count = abx500_get_groups_cnt,
.get_group_name = abx500_get_group_name,
.get_group_pins = abx500_get_group_pins,
@@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
return ret;
}
-static struct pinconf_ops abx500_pinconf_ops = {
+static const struct pinconf_ops abx500_pinconf_ops = {
.pin_config_get = abx500_pin_config_get,
.pin_config_set = abx500_pin_config_set,
};
@@ -834,6 +834,7 @@ static const struct of_device_id abx500_gpio_match[] = {
{ .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
{ .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
{ .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
+ { }
};
static int abx500_gpio_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 75933a6aa828..e50fa5f863e1 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -294,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev,
{
}
-static struct pinctrl_ops at91_pctrl_ops = {
+static const struct pinctrl_ops at91_pctrl_ops = {
.get_groups_count = at91_get_groups_count,
.get_group_name = at91_get_group_name,
.get_group_pins = at91_get_group_pins,
@@ -696,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
/* Set the pin to some default state, GPIO is usually default */
}
-static struct pinmux_ops at91_pmx_ops = {
+static const struct pinmux_ops at91_pmx_ops = {
.get_functions_count = at91_pmx_get_funcs_count,
.get_function_name = at91_pmx_get_func_name,
.get_function_groups = at91_pmx_get_groups,
@@ -776,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
{
}
-static struct pinconf_ops at91_pinconf_ops = {
+static const struct pinconf_ops at91_pinconf_ops = {
.pin_config_get = at91_pinconf_get,
.pin_config_set = at91_pinconf_set,
.pin_config_dbg_show = at91_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 4eb6d2c4e4df..f28d4b08771a 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -795,7 +795,7 @@ out:
return err;
}
-static struct pinctrl_ops bcm2835_pctl_ops = {
+static const struct pinctrl_ops bcm2835_pctl_ops = {
.get_groups_count = bcm2835_pctl_get_groups_count,
.get_group_name = bcm2835_pctl_get_group_name,
.get_group_pins = bcm2835_pctl_get_group_pins,
@@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinmux_ops bcm2835_pmx_ops = {
+static const struct pinmux_ops bcm2835_pmx_ops = {
.get_functions_count = bcm2835_pmx_get_functions_count,
.get_function_name = bcm2835_pmx_get_function_name,
.get_function_groups = bcm2835_pmx_get_function_groups,
@@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinconf_ops bcm2835_pinconf_ops = {
+static const struct pinconf_ops bcm2835_pinconf_ops = {
.pin_config_get = bcm2835_pinconf_get,
.pin_config_set = bcm2835_pinconf_set,
};
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 1376eb7305db..169ea3e5f777 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
}
/* list of pinctrl callbacks for the pinctrl core */
-static struct pinctrl_ops exynos5440_pctrl_ops = {
+static const struct pinctrl_ops exynos5440_pctrl_ops = {
.get_groups_count = exynos5440_get_group_count,
.get_group_name = exynos5440_get_group_name,
.get_group_pins = exynos5440_get_group_pins,
@@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
}
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
-static struct pinmux_ops exynos5440_pinmux_ops = {
+static const struct pinmux_ops exynos5440_pinmux_ops = {
.get_functions_count = exynos5440_get_functions_count,
.get_function_name = exynos5440_pinmux_get_fname,
.get_function_groups = exynos5440_pinmux_get_groups,
@@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
}
/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
-static struct pinconf_ops exynos5440_pinconf_ops = {
+static const struct pinconf_ops exynos5440_pinconf_ops = {
.pin_config_get = exynos5440_pinconf_get,
.pin_config_set = exynos5440_pinconf_set,
.pin_config_group_get = exynos5440_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index af97a1f90007..f9b2a1d4854f 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
{
}
-static struct pinconf_ops falcon_pinconf_ops = {
+static const struct pinconf_ops falcon_pinconf_ops = {
.pin_config_get = falcon_pinconf_get,
.pin_config_set = falcon_pinconf_set,
.pin_config_group_get = falcon_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4cebb9c6c5c5..0ef190449eab 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -207,7 +207,7 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
-static struct pinctrl_ops imx_pctrl_ops = {
+static const struct pinctrl_ops imx_pctrl_ops = {
.get_groups_count = imx_get_groups_count,
.get_group_name = imx_get_group_name,
.get_group_pins = imx_get_group_pins,
@@ -299,7 +299,7 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
-static struct pinmux_ops imx_pmx_ops = {
+static const struct pinmux_ops imx_pmx_ops = {
.get_functions_count = imx_pmx_get_funcs_count,
.get_function_name = imx_pmx_get_func_name,
.get_function_groups = imx_pmx_get_groups,
@@ -397,7 +397,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
}
}
-static struct pinconf_ops imx_pinconf_ops = {
+static const struct pinconf_ops imx_pinconf_ops = {
.pin_config_get = imx_pinconf_get,
.pin_config_set = imx_pinconf_set,
.pin_config_dbg_show = imx_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index a70384611351..615c5002b757 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -169,7 +169,7 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinctrl_ops ltq_pctrl_ops = {
+static const struct pinctrl_ops ltq_pctrl_ops = {
.get_groups_count = ltq_get_group_count,
.get_group_name = ltq_get_group_name,
.get_group_pins = ltq_get_group_pins,
@@ -311,7 +311,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
return info->apply_mux(pctrldev, mfp, pin_func);
}
-static struct pinmux_ops ltq_pmx_ops = {
+static const struct pinmux_ops ltq_pmx_ops = {
.get_functions_count = ltq_pmx_func_count,
.get_function_name = ltq_pmx_func_name,
.get_function_groups = ltq_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
index 23af9f1f9c35..b45c4eb35798 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -158,7 +158,7 @@ static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
-static struct pinctrl_ops mxs_pinctrl_ops = {
+static const struct pinctrl_ops mxs_pinctrl_ops = {
.get_groups_count = mxs_get_groups_count,
.get_group_name = mxs_get_group_name,
.get_group_pins = mxs_get_group_pins,
@@ -219,7 +219,7 @@ static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
-static struct pinmux_ops mxs_pinmux_ops = {
+static const struct pinmux_ops mxs_pinmux_ops = {
.get_functions_count = mxs_pinctrl_get_funcs_count,
.get_function_name = mxs_pinctrl_get_func_name,
.get_function_groups = mxs_pinctrl_get_func_groups,
@@ -319,7 +319,7 @@ static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
seq_printf(s, "0x%lx", config);
}
-static struct pinconf_ops mxs_pinconf_ops = {
+static const struct pinconf_ops mxs_pinconf_ops = {
.pin_config_get = mxs_pinconf_get,
.pin_config_set = mxs_pinconf_set,
.pin_config_group_get = mxs_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 36d20293de5c..2328baaa86bf 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1764,7 +1764,7 @@ int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinctrl_ops nmk_pinctrl_ops = {
+static const struct pinctrl_ops nmk_pinctrl_ops = {
.get_groups_count = nmk_get_groups_cnt,
.get_group_name = nmk_get_group_name,
.get_group_pins = nmk_get_group_pins,
@@ -1975,7 +1975,7 @@ static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
/* Set the pin to some default state, GPIO is usually default */
}
-static struct pinmux_ops nmk_pinmux_ops = {
+static const struct pinmux_ops nmk_pinmux_ops = {
.get_functions_count = nmk_pmx_get_funcs_cnt,
.get_function_name = nmk_pmx_get_func_name,
.get_function_groups = nmk_pmx_get_func_groups,
@@ -2089,7 +2089,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
return 0;
}
-static struct pinconf_ops nmk_pinconf_ops = {
+static const struct pinconf_ops nmk_pinconf_ops = {
.pin_config_get = nmk_pin_config_get,
.pin_config_set = nmk_pin_config_set,
};
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 1f49bb02a6af..05e11de1d144 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -53,7 +53,7 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
return 0;
}
-static struct pinctrl_ops pxa3xx_pctrl_ops = {
+static const struct pinctrl_ops pxa3xx_pctrl_ops = {
.get_groups_count = pxa3xx_get_groups_count,
.get_group_name = pxa3xx_get_group_name,
.get_group_pins = pxa3xx_get_group_pins,
@@ -161,7 +161,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
return 0;
}
-static struct pinmux_ops pxa3xx_pmx_ops = {
+static const struct pinmux_ops pxa3xx_pmx_ops = {
.get_functions_count = pxa3xx_pmx_get_funcs_count,
.get_function_name = pxa3xx_pmx_get_func_name,
.get_function_groups = pxa3xx_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index f206df175656..3475b92b24a4 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -214,7 +214,7 @@ static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
}
/* list of pinctrl callbacks for the pinctrl core */
-static struct pinctrl_ops samsung_pctrl_ops = {
+static const struct pinctrl_ops samsung_pctrl_ops = {
.get_groups_count = samsung_get_group_count,
.get_group_name = samsung_get_group_name,
.get_group_pins = samsung_get_group_pins,
@@ -357,7 +357,7 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
}
/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
-static struct pinmux_ops samsung_pinmux_ops = {
+static const struct pinmux_ops samsung_pinmux_ops = {
.get_functions_count = samsung_get_functions_count,
.get_function_name = samsung_pinmux_get_fname,
.get_function_groups = samsung_pinmux_get_groups,
@@ -468,7 +468,7 @@ static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
}
/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
-static struct pinconf_ops samsung_pinconf_ops = {
+static const struct pinconf_ops samsung_pinconf_ops = {
.pin_config_get = samsung_pinconf_get,
.pin_config_set = samsung_pinconf_set,
.pin_config_group_get = samsung_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 5c32e880bcb2..e35dabd3135d 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -22,8 +22,10 @@
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf-generic.h>
#include "core.h"
+#include "pinconf.h"
#define DRIVER_NAME "pinctrl-single"
#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
@@ -59,6 +61,33 @@ struct pcs_func_vals {
};
/**
+ * struct pcs_conf_vals - pinconf parameter, pinconf register offset
+ * and value, enable, disable, mask
+ * @param: config parameter
+ * @val: user input bits in the pinconf register
+ * @enable: enable bits in the pinconf register
+ * @disable: disable bits in the pinconf register
+ * @mask: mask bits in the register value
+ */
+struct pcs_conf_vals {
+ enum pin_config_param param;
+ unsigned val;
+ unsigned enable;
+ unsigned disable;
+ unsigned mask;
+};
+
+/**
+ * struct pcs_conf_type - pinconf property name, pinconf param pair
+ * @name: property name in DTS file
+ * @param: config parameter
+ */
+struct pcs_conf_type {
+ const char *name;
+ enum pin_config_param param;
+};
+
+/**
* struct pcs_function - pinctrl function
* @name: pinctrl function name
* @vals: register and vals array
@@ -73,6 +102,22 @@ struct pcs_function {
unsigned nvals;
const char **pgnames;
int npgnames;
+ struct pcs_conf_vals *conf;
+ int nconfs;
+ struct list_head node;
+};
+
+/**
+ * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
+ * @offset: offset base of pins
+ * @npins: number pins with the same mux value of gpio function
+ * @gpiofunc: mux value of gpio function
+ * @node: list node
+ */
+struct pcs_gpiofunc_range {
+ unsigned offset;
+ unsigned npins;
+ unsigned gpiofunc;
struct list_head node;
};
@@ -117,12 +162,14 @@ struct pcs_name {
* @fshift: function register shift
* @foff: value to turn mux off
* @fmax: max number of functions in fmask
+ * @is_pinconf: whether supports pinconf
* @names: array of register names for pins
* @pins: physical pins on the SoC
* @pgtree: pingroup index radix tree
* @ftree: function index radix tree
* @pingroups: list of pingroups
* @functions: list of functions
+ * @gpiofuncs: list of gpio functions
* @ngroups: number of pingroups
* @nfuncs: number of functions
* @desc: pin controller descriptor
@@ -142,12 +189,14 @@ struct pcs_device {
unsigned foff;
unsigned fmax;
bool bits_per_mux;
+ bool is_pinconf;
struct pcs_name *names;
struct pcs_data pins;
struct radix_tree_root pgtree;
struct radix_tree_root ftree;
struct list_head pingroups;
struct list_head functions;
+ struct list_head gpiofuncs;
unsigned ngroups;
unsigned nfuncs;
struct pinctrl_desc desc;
@@ -155,6 +204,16 @@ struct pcs_device {
void (*write)(unsigned val, void __iomem *reg);
};
+static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
+ unsigned long *config);
+static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
+ unsigned long config);
+
+static enum pin_config_param pcs_bias[] = {
+ PIN_CONFIG_BIAS_PULL_DOWN,
+ PIN_CONFIG_BIAS_PULL_UP,
+};
+
/*
* REVISIT: Reads and writes could eventually use regmap or something
* generic. But at least on omaps, some mux registers are performance
@@ -270,7 +329,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
struct device_node *np_config,
struct pinctrl_map **map, unsigned *num_maps);
-static struct pinctrl_ops pcs_pinctrl_ops = {
+static const struct pinctrl_ops pcs_pinctrl_ops = {
.get_groups_count = pcs_get_groups_count,
.get_group_name = pcs_get_group_name,
.get_group_pins = pcs_get_group_pins,
@@ -326,6 +385,28 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
return 0;
}
+static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
+ struct pcs_function **func)
+{
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
+ const struct pinctrl_setting_mux *setting;
+ unsigned fselector;
+
+ /* If pin is not described in DTS & enabled, mux_setting is NULL. */
+ setting = pdesc->mux_setting;
+ if (!setting)
+ return -ENOTSUPP;
+ fselector = setting->func;
+ *func = radix_tree_lookup(&pcs->ftree, fselector);
+ if (!(*func)) {
+ dev_err(pcs->dev, "%s could not find function%i\n",
+ __func__, fselector);
+ return -ENOTSUPP;
+ }
+ return 0;
+}
+
static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
unsigned group)
{
@@ -334,6 +415,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
int i;
pcs = pinctrl_dev_get_drvdata(pctldev);
+ /* If function mask is null, needn't enable it. */
+ if (!pcs->fmask)
+ return 0;
func = radix_tree_lookup(&pcs->ftree, fselector);
if (!func)
return -EINVAL;
@@ -368,6 +452,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
int i;
pcs = pinctrl_dev_get_drvdata(pctldev);
+ /* If function mask is null, needn't disable it. */
+ if (!pcs->fmask)
+ return;
+
func = radix_tree_lookup(&pcs->ftree, fselector);
if (!func) {
dev_err(pcs->dev, "%s could not find function%i\n",
@@ -403,12 +491,33 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
}
static int pcs_request_gpio(struct pinctrl_dev *pctldev,
- struct pinctrl_gpio_range *range, unsigned offset)
+ struct pinctrl_gpio_range *range, unsigned pin)
{
- return -ENOTSUPP;
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_gpiofunc_range *frange = NULL;
+ struct list_head *pos, *tmp;
+ int mux_bytes = 0;
+ unsigned data;
+
+ /* If function mask is null, return directly. */
+ if (!pcs->fmask)
+ return -ENOTSUPP;
+
+ list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
+ frange = list_entry(pos, struct pcs_gpiofunc_range, node);
+ if (pin >= frange->offset + frange->npins
+ || pin < frange->offset)
+ continue;
+ mux_bytes = pcs->width / BITS_PER_BYTE;
+ data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
+ data |= frange->gpiofunc;
+ pcs->write(data, pcs->base + pin * mux_bytes);
+ break;
+ }
+ return 0;
}
-static struct pinmux_ops pcs_pinmux_ops = {
+static const struct pinmux_ops pcs_pinmux_ops = {
.get_functions_count = pcs_get_functions_count,
.get_function_name = pcs_get_function_name,
.get_function_groups = pcs_get_function_groups,
@@ -417,32 +526,191 @@ static struct pinmux_ops pcs_pinmux_ops = {
.gpio_request_enable = pcs_request_gpio,
};
+/* Clear BIAS value */
+static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
+{
+ unsigned long config;
+ int i;
+ for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
+ config = pinconf_to_config_packed(pcs_bias[i], 0);
+ pcs_pinconf_set(pctldev, pin, config);
+ }
+}
+
+/*
+ * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
+ * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
+ */
+static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
+{
+ unsigned long config;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
+ config = pinconf_to_config_packed(pcs_bias[i], 0);
+ if (!pcs_pinconf_get(pctldev, pin, &config))
+ goto out;
+ }
+ return true;
+out:
+ return false;
+}
+
static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long *config)
{
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_function *func;
+ enum pin_config_param param;
+ unsigned offset = 0, data = 0, i, j, ret;
+
+ ret = pcs_get_function(pctldev, pin, &func);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < func->nconfs; i++) {
+ param = pinconf_to_config_param(*config);
+ if (param == PIN_CONFIG_BIAS_DISABLE) {
+ if (pcs_pinconf_bias_disable(pctldev, pin)) {
+ *config = 0;
+ return 0;
+ } else {
+ return -ENOTSUPP;
+ }
+ } else if (param != func->conf[i].param) {
+ continue;
+ }
+
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ data = pcs->read(pcs->base + offset) & func->conf[i].mask;
+ switch (func->conf[i].param) {
+ /* 4 parameters */
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if ((data != func->conf[i].enable) ||
+ (data == func->conf[i].disable))
+ return -ENOTSUPP;
+ *config = 0;
+ break;
+ /* 2 parameters */
+ case PIN_CONFIG_INPUT_SCHMITT:
+ for (j = 0; j < func->nconfs; j++) {
+ switch (func->conf[j].param) {
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ if (data != func->conf[j].enable)
+ return -ENOTSUPP;
+ break;
+ default:
+ break;
+ }
+ }
+ *config = data;
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ case PIN_CONFIG_SLEW_RATE:
+ default:
+ *config = data;
+ break;
+ }
+ return 0;
+ }
return -ENOTSUPP;
}
static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
unsigned pin, unsigned long config)
{
+ struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
+ struct pcs_function *func;
+ unsigned offset = 0, shift = 0, arg = 0, i, data, ret;
+ u16 argument;
+
+ ret = pcs_get_function(pctldev, pin, &func);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < func->nconfs; i++) {
+ if (pinconf_to_config_param(config) == func->conf[i].param) {
+ offset = pin * (pcs->width / BITS_PER_BYTE);
+ data = pcs->read(pcs->base + offset);
+ argument = pinconf_to_config_argument(config);
+ switch (func->conf[i].param) {
+ /* 2 parameters */
+ case PIN_CONFIG_INPUT_SCHMITT:
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ case PIN_CONFIG_SLEW_RATE:
+ shift = ffs(func->conf[i].mask) - 1;
+ arg = pinconf_to_config_argument(config);
+ data &= ~func->conf[i].mask;
+ data |= (arg << shift) & func->conf[i].mask;
+ break;
+ /* 4 parameters */
+ case PIN_CONFIG_BIAS_DISABLE:
+ pcs_pinconf_clear_bias(pctldev, pin);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ if (argument)
+ pcs_pinconf_clear_bias(pctldev, pin);
+ /* fall through */
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ data &= ~func->conf[i].mask;
+ if (argument)
+ data |= func->conf[i].enable;
+ else
+ data |= func->conf[i].disable;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+ pcs->write(data, pcs->base + offset);
+ return 0;
+ }
+ }
return -ENOTSUPP;
}
static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
unsigned group, unsigned long *config)
{
- return -ENOTSUPP;
+ const unsigned *pins;
+ unsigned npins, old = 0;
+ int i, ret;
+
+ ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+ for (i = 0; i < npins; i++) {
+ if (pcs_pinconf_get(pctldev, pins[i], config))
+ return -ENOTSUPP;
+ /* configs do not match between two pins */
+ if (i && (old != *config))
+ return -ENOTSUPP;
+ old = *config;
+ }
+ return 0;
}
static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
unsigned group, unsigned long config)
{
- return -ENOTSUPP;
+ const unsigned *pins;
+ unsigned npins;
+ int i, ret;
+
+ ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
+ if (ret)
+ return ret;
+ for (i = 0; i < npins; i++) {
+ if (pcs_pinconf_set(pctldev, pins[i], config))
+ return -ENOTSUPP;
+ }
+ return 0;
}
static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
- struct seq_file *s, unsigned offset)
+ struct seq_file *s, unsigned pin)
{
}
@@ -451,13 +719,22 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
{
}
-static struct pinconf_ops pcs_pinconf_ops = {
+static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
+ struct seq_file *s,
+ unsigned long config)
+{
+ pinconf_generic_dump_config(pctldev, s, config);
+}
+
+static const struct pinconf_ops pcs_pinconf_ops = {
.pin_config_get = pcs_pinconf_get,
.pin_config_set = pcs_pinconf_set,
.pin_config_group_get = pcs_pinconf_group_get,
.pin_config_group_set = pcs_pinconf_group_set,
.pin_config_dbg_show = pcs_pinconf_dbg_show,
.pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
+ .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
+ .is_generic = true,
};
/**
@@ -648,11 +925,157 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
return index;
}
+/*
+ * check whether data matches enable bits or disable bits
+ * Return value: 1 for matching enable bits, 0 for matching disable bits,
+ * and negative value for matching failure.
+ */
+static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
+{
+ int ret = -EINVAL;
+
+ if (data == enable)
+ ret = 1;
+ else if (data == disable)
+ ret = 0;
+ return ret;
+}
+
+static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
+ unsigned value, unsigned enable, unsigned disable,
+ unsigned mask)
+{
+ (*conf)->param = param;
+ (*conf)->val = value;
+ (*conf)->enable = enable;
+ (*conf)->disable = disable;
+ (*conf)->mask = mask;
+ (*conf)++;
+}
+
+static void add_setting(unsigned long **setting, enum pin_config_param param,
+ unsigned arg)
+{
+ **setting = pinconf_to_config_packed(param, arg);
+ (*setting)++;
+}
+
+/* add pinconf setting with 2 parameters */
+static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
+ const char *name, enum pin_config_param param,
+ struct pcs_conf_vals **conf, unsigned long **settings)
+{
+ unsigned value[2];
+ int ret;
+
+ ret = of_property_read_u32_array(np, name, value, 2);
+ if (ret)
+ return;
+ /* set value & mask */
+ value[0] &= value[1];
+ /* skip enable & disable */
+ add_config(conf, param, value[0], 0, 0, value[1]);
+ add_setting(settings, param, value[0]);
+}
+
+/* add pinconf setting with 4 parameters */
+static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
+ const char *name, enum pin_config_param param,
+ struct pcs_conf_vals **conf, unsigned long **settings)
+{
+ unsigned value[4];
+ int ret;
+
+ /* value to set, enable, disable, mask */
+ ret = of_property_read_u32_array(np, name, value, 4);
+ if (ret)
+ return;
+ if (!value[3]) {
+ dev_err(pcs->dev, "mask field of the property can't be 0\n");
+ return;
+ }
+ value[0] &= value[3];
+ value[1] &= value[3];
+ value[2] &= value[3];
+ ret = pcs_config_match(value[0], value[1], value[2]);
+ if (ret < 0)
+ dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
+ add_config(conf, param, value[0], value[1], value[2], value[3]);
+ add_setting(settings, param, ret);
+}
+
+static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
+ struct pcs_function *func,
+ struct pinctrl_map **map)
+
+{
+ struct pinctrl_map *m = *map;
+ int i = 0, nconfs = 0;
+ unsigned long *settings = NULL, *s = NULL;
+ struct pcs_conf_vals *conf = NULL;
+ struct pcs_conf_type prop2[] = {
+ { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
+ { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
+ { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
+ };
+ struct pcs_conf_type prop4[] = {
+ { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
+ { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
+ { "pinctrl-single,input-schmitt-enable",
+ PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
+ };
+
+ /* If pinconf isn't supported, don't parse properties in below. */
+ if (!pcs->is_pinconf)
+ return 0;
+
+ /* cacluate how much properties are supported in current node */
+ for (i = 0; i < ARRAY_SIZE(prop2); i++) {
+ if (of_find_property(np, prop2[i].name, NULL))
+ nconfs++;
+ }
+ for (i = 0; i < ARRAY_SIZE(prop4); i++) {
+ if (of_find_property(np, prop4[i].name, NULL))
+ nconfs++;
+ }
+ if (!nconfs)
+ return 0;
+
+ func->conf = devm_kzalloc(pcs->dev,
+ sizeof(struct pcs_conf_vals) * nconfs,
+ GFP_KERNEL);
+ if (!func->conf)
+ return -ENOMEM;
+ func->nconfs = nconfs;
+ conf = &(func->conf[0]);
+ m++;
+ settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
+ GFP_KERNEL);
+ if (!settings)
+ return -ENOMEM;
+ s = &settings[0];
+
+ for (i = 0; i < ARRAY_SIZE(prop2); i++)
+ pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
+ &conf, &s);
+ for (i = 0; i < ARRAY_SIZE(prop4); i++)
+ pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
+ &conf, &s);
+ m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
+ m->data.configs.group_or_pin = np->name;
+ m->data.configs.configs = settings;
+ m->data.configs.num_configs = nconfs;
+ return 0;
+}
+
+static void pcs_free_pingroups(struct pcs_device *pcs);
+
/**
* smux_parse_one_pinctrl_entry() - parses a device tree mux entry
* @pcs: pinctrl driver instance
* @np: device node of the mux entry
* @map: map entry
+ * @num_maps: number of map
* @pgnames: pingroup names
*
* Note that this binding currently supports only sets of one register + value.
@@ -669,6 +1092,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
struct device_node *np,
struct pinctrl_map **map,
+ unsigned *num_maps,
const char **pgnames)
{
struct pcs_func_vals *vals;
@@ -741,8 +1165,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
(*map)->data.mux.group = np->name;
(*map)->data.mux.function = np->name;
+ if (pcs->is_pinconf) {
+ if (pcs_parse_pinconf(pcs, np, function, map))
+ goto free_pingroups;
+ *num_maps = 2;
+ } else {
+ *num_maps = 1;
+ }
return 0;
+free_pingroups:
+ pcs_free_pingroups(pcs);
+ *num_maps = 1;
free_function:
pcs_remove_function(pcs, function);
@@ -771,7 +1205,8 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
pcs = pinctrl_dev_get_drvdata(pctldev);
- *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL);
+ /* create 2 maps. One is for pinmux, and the other is for pinconf. */
+ *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
if (!*map)
return -ENOMEM;
@@ -783,13 +1218,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
goto free_map;
}
- ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames);
+ ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
+ pgnames);
if (ret < 0) {
dev_err(pcs->dev, "no pins entries for %s\n",
np_config->name);
goto free_pgnames;
}
- *num_maps = 1;
return 0;
@@ -879,6 +1314,37 @@ static void pcs_free_resources(struct pcs_device *pcs)
static struct of_device_id pcs_of_match[];
+static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
+{
+ const char *propname = "pinctrl-single,gpio-range";
+ const char *cellname = "#pinctrl-single,gpio-range-cells";
+ struct of_phandle_args gpiospec;
+ struct pcs_gpiofunc_range *range;
+ int ret, i;
+
+ for (i = 0; ; i++) {
+ ret = of_parse_phandle_with_args(node, propname, cellname,
+ i, &gpiospec);
+ /* Do not treat it as error. Only treat it as end condition. */
+ if (ret) {
+ ret = 0;
+ break;
+ }
+ range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
+ if (!range) {
+ ret = -ENOMEM;
+ break;
+ }
+ range->offset = gpiospec.args[0];
+ range->npins = gpiospec.args[1];
+ range->gpiofunc = gpiospec.args[2];
+ mutex_lock(&pcs->mutex);
+ list_add_tail(&range->node, &pcs->gpiofuncs);
+ mutex_unlock(&pcs->mutex);
+ }
+ return ret;
+}
+
static int pcs_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -900,14 +1366,23 @@ static int pcs_probe(struct platform_device *pdev)
mutex_init(&pcs->mutex);
INIT_LIST_HEAD(&pcs->pingroups);
INIT_LIST_HEAD(&pcs->functions);
+ INIT_LIST_HEAD(&pcs->gpiofuncs);
+ pcs->is_pinconf = match->data;
PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
"register width not specified\n");
- PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask,
- "function register mask not specified\n");
- pcs->fshift = ffs(pcs->fmask) - 1;
- pcs->fmax = pcs->fmask >> pcs->fshift;
+ ret = of_property_read_u32(np, "pinctrl-single,function-mask",
+ &pcs->fmask);
+ if (!ret) {
+ pcs->fshift = ffs(pcs->fmask) - 1;
+ pcs->fmax = pcs->fmask >> pcs->fshift;
+ } else {
+ /* If mask property doesn't exist, function mux is invalid. */
+ pcs->fmask = 0;
+ pcs->fshift = 0;
+ pcs->fmax = 0;
+ }
ret = of_property_read_u32(np, "pinctrl-single,function-off",
&pcs->foff);
@@ -961,7 +1436,8 @@ static int pcs_probe(struct platform_device *pdev)
pcs->desc.name = DRIVER_NAME;
pcs->desc.pctlops = &pcs_pinctrl_ops;
pcs->desc.pmxops = &pcs_pinmux_ops;
- pcs->desc.confops = &pcs_pinconf_ops;
+ if (pcs->is_pinconf)
+ pcs->desc.confops = &pcs_pinconf_ops;
pcs->desc.owner = THIS_MODULE;
ret = pcs_allocate_pin_table(pcs);
@@ -975,6 +1451,10 @@ static int pcs_probe(struct platform_device *pdev)
goto free;
}
+ ret = pcs_add_gpio_func(np, pcs);
+ if (ret < 0)
+ goto free;
+
dev_info(pcs->dev, "%i pins at pa %p size %u\n",
pcs->desc.npins, pcs->base, pcs->size);
@@ -999,7 +1479,8 @@ static int pcs_remove(struct platform_device *pdev)
}
static struct of_device_id pcs_of_match[] = {
- { .compatible = DRIVER_NAME, },
+ { .compatible = "pinctrl-single", .data = (void *)false },
+ { .compatible = "pinconf-single", .data = (void *)true },
{ },
};
MODULE_DEVICE_TABLE(of, pcs_of_match);
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index d02498b30c6e..0990a721758e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -979,7 +979,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
-static struct pinctrl_ops sirfsoc_pctrl_ops = {
+static const struct pinctrl_ops sirfsoc_pctrl_ops = {
.get_groups_count = sirfsoc_get_groups_count,
.get_group_name = sirfsoc_get_group_name,
.get_group_pins = sirfsoc_get_group_pins,
@@ -1181,7 +1181,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
return 0;
}
-static struct pinmux_ops sirfsoc_pinmux_ops = {
+static const struct pinmux_ops sirfsoc_pinmux_ops = {
.enable = sirfsoc_pinmux_enable,
.disable = sirfsoc_pinmux_disable,
.get_functions_count = sirfsoc_pinmux_get_funcs_count,
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 80b11e3415bc..cb491d6ba601 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -30,482 +30,856 @@
static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x4, "uart2")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */
+ SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x4, "uart2")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */
+ SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */
+ SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */
+ SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */
+ SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */
+ SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */
+ SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */
+ SUNXI_FUNCTION(0x3, "uart6"), /* TX */
SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */
+ SUNXI_FUNCTION(0x3, "uart6"), /* RX */
SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */
+ SUNXI_FUNCTION(0x3, "uart7"), /* TX */
SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */
+ SUNXI_FUNCTION(0x3, "uart7"), /* RX */
SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */
+ SUNXI_FUNCTION(0x3, "can"), /* TX */
SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */
+ SUNXI_FUNCTION(0x3, "can"), /* RX */
SUNXI_FUNCTION(0x4, "uart1")), /* RING */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
+ SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
+ SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
+ SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
+ SUNXI_FUNCTION(0x3, "ac97")), /* DO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2s"), /* DI */
+ SUNXI_FUNCTION(0x3, "ac97")), /* DI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
+ SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
+ SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart0")), /* TX */
+ SUNXI_FUNCTION(0x2, "uart0"), /* TX */
+ SUNXI_FUNCTION(0x3, "ir1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
- SUNXI_FUNCTION(0x2, "uart0")), /* RX */
+ SUNXI_FUNCTION(0x2, "uart0"), /* RX */
+ SUNXI_FUNCTION(0x3, "ir1")), /* RX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
+ SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
+ SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
+ SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
+ SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
+ SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
+ SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
+ SUNXI_FUNCTION(0x3, "sim")), /* DET */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
+ SUNXI_FUNCTION(0x3, "sim")), /* RST */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "sim")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "sim")), /* SDA */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
+ SUNXI_FUNCTION(0x3, "csi0")), /* CK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
+ SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
+ SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
+ SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
SUNXI_FUNCTION(0x4, "uart0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
+ SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
SUNXI_FUNCTION(0x4, "uart0")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
+ SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
+ SUNXI_FUNCTION(0x3, "csi1"), /* CK */
+ SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
+ SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
+ SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
+ SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
+ SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
+ SUNXI_FUNCTION(0x4, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
+ SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
+ SUNXI_FUNCTION(0x4, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* TX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
+ SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
+ SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
+ SUNXI_FUNCTION(0x4, "uart4"), /* TX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
+ SUNXI_FUNCTION(0x4, "uart4"), /* RX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
+ SUNXI_FUNCTION(0x4, "uart5"), /* TX */
+ SUNXI_FUNCTION(0x5, "ms"), /* BS */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
+ SUNXI_FUNCTION(0x4, "uart5"), /* RX */
+ SUNXI_FUNCTION(0x5, "ms"), /* CLK */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
+ SUNXI_FUNCTION(0x5, "ms"), /* D0 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
+ SUNXI_FUNCTION(0x5, "ms"), /* D1 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
+ SUNXI_FUNCTION(0x5, "ms"), /* D2 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
+ SUNXI_FUNCTION(0x5, "ms"), /* D3 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
+ SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
+ SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
+ SUNXI_FUNCTION(0x5, "sim"), /* RST */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
+ SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
+ SUNXI_FUNCTION(0x5, "sim"), /* SCK */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
+ SUNXI_FUNCTION(0x5, "sim"), /* SDA */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
+ SUNXI_FUNCTION(0x4, "can"), /* TX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
+ SUNXI_FUNCTION(0x4, "can"), /* RX */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
+ SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
+ SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
+ SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
+ SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
+ SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -518,277 +892,401 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
SUNXI_FUNCTION(0x1, "gpio_out")),
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "uart5")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart5")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "uart6")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
+ SUNXI_FUNCTION(0x3, "uart6")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
+ SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
+ SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
+ SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "uart2")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "uart2")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
+ SUNXI_FUNCTION(0x3, "uart7"), /* TX */
+ SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
+ SUNXI_FUNCTION(0x3, "uart7"), /* RX */
+ SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
};
static const struct sunxi_desc_pin sun5i_a13_pins[] = {
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "pwm")),
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "ir0")), /* RX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
+ SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
+ SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
+ SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
+ SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
+ SUNXI_FUNCTION(0x4, "spi2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
+ SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
+ SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
+ SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -802,24 +1300,34 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
SUNXI_FUNCTION(0x4, "uart1")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
SUNXI_FUNCTION(0x0, "gpio_in"),
SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
SUNXI_FUNCTION(0x4, "uart1")), /* RX */
- /* Hole */
+/* Hole */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
+ SUNXI_FUNCTION(0x3, "uart3")), /* TX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
+ SUNXI_FUNCTION(0x3, "uart3")), /* RX */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
+ SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
SUNXI_FUNCTION(0x0, "gpio_in"),
- SUNXI_FUNCTION(0x1, "gpio_out")),
+ SUNXI_FUNCTION(0x1, "gpio_out"),
+ SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
+ SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
};
static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
@@ -1029,7 +1537,7 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
-static struct pinctrl_ops sunxi_pctrl_ops = {
+static const struct pinctrl_ops sunxi_pctrl_ops = {
.dt_node_to_map = sunxi_pctrl_dt_node_to_map,
.dt_free_map = sunxi_pctrl_dt_free_map,
.get_groups_count = sunxi_pctrl_get_groups_count,
@@ -1098,7 +1606,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinconf_ops sunxi_pconf_ops = {
+static const struct pinconf_ops sunxi_pconf_ops = {
.pin_config_group_get = sunxi_pconf_group_get,
.pin_config_group_set = sunxi_pconf_group_set,
};
@@ -1204,7 +1712,7 @@ error:
return ret;
}
-static struct pinmux_ops sunxi_pmx_ops = {
+static const struct pinmux_ops sunxi_pmx_ops = {
.get_functions_count = sunxi_pmx_get_funcs_cnt,
.get_function_name = sunxi_pmx_get_func_name,
.get_function_groups = sunxi_pmx_get_func_groups,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index f195d77a3572..2fa9bc6cd7ab 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -316,7 +316,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
return 0;
}
-static struct pinctrl_ops tegra_pinctrl_ops = {
+static const struct pinctrl_ops tegra_pinctrl_ops = {
.get_groups_count = tegra_pinctrl_get_groups_count,
.get_group_name = tegra_pinctrl_get_group_name,
.get_group_pins = tegra_pinctrl_get_group_pins,
@@ -401,7 +401,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
}
-static struct pinmux_ops tegra_pinmux_ops = {
+static const struct pinmux_ops tegra_pinmux_ops = {
.get_functions_count = tegra_pinctrl_get_funcs_count,
.get_function_name = tegra_pinctrl_get_func_name,
.get_function_groups = tegra_pinctrl_get_func_groups,
@@ -676,7 +676,7 @@ static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
}
#endif
-static struct pinconf_ops tegra_pinconf_ops = {
+static const struct pinconf_ops tegra_pinconf_ops = {
.pin_config_get = tegra_pinconf_get,
.pin_config_set = tegra_pinconf_set,
.pin_config_group_get = tegra_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 2b5772550836..6a3a7503e6a0 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -860,7 +860,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
seq_printf(s, " " DRIVER_NAME);
}
-static struct pinctrl_ops u300_pctrl_ops = {
+static const struct pinctrl_ops u300_pctrl_ops = {
.get_groups_count = u300_get_groups_count,
.get_group_name = u300_get_group_name,
.get_group_pins = u300_get_group_pins,
@@ -1003,7 +1003,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
return 0;
}
-static struct pinmux_ops u300_pmx_ops = {
+static const struct pinmux_ops u300_pmx_ops = {
.get_functions_count = u300_pmx_get_funcs_count,
.get_function_name = u300_pmx_get_func_name,
.get_function_groups = u300_pmx_get_groups,
@@ -1046,7 +1046,7 @@ static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
return 0;
}
-static struct pinconf_ops u300_pconf_ops = {
+static const struct pinconf_ops u300_pconf_ops = {
.is_generic = true,
.pin_config_get = u300_pin_config_get,
.pin_config_set = u300_pin_config_set,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index 068224efa6fa..f2977cff8366 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -553,7 +553,7 @@ int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
return ret;
}
-static struct pinconf_ops xway_pinconf_ops = {
+static const struct pinconf_ops xway_pinconf_ops = {
.pin_config_get = xway_pinconf_get,
.pin_config_set = xway_pinconf_set,
.pin_config_group_set = xway_pinconf_group_set,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c3340f54d2ad..0e1f99c33d47 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
select PINMUX
select PINCONF
+ select GENERIC_PINCONF
def_bool y
help
This enables pin control drivers for SH and SH Mobile platforms
@@ -21,6 +22,11 @@ config GPIO_SH_PFC
This enables support for GPIOs within the SoC's pin function
controller.
+config PINCTRL_PFC_R8A73A4
+ def_bool y
+ depends on ARCH_R8A73A4
+ select PINCTRL_SH_PFC
+
config PINCTRL_PFC_R8A7740
def_bool y
depends on ARCH_R8A7740
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index e8b9562c47e1..211cd8e98a8a 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
sh-pfc-objs += gpio.o
endif
obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
+obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 970ddff2b0b6..b551336924a5 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -10,7 +10,6 @@
*/
#define DRV_NAME "sh-pfc"
-#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bitops.h>
#include <linux/err.h>
@@ -30,10 +29,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
struct resource *res;
int k;
- if (pdev->num_resources == 0) {
- pfc->num_windows = 0;
- return 0;
- }
+ if (pdev->num_resources == 0)
+ return -EINVAL;
pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
sizeof(*pfc->window), GFP_NOWAIT);
@@ -59,11 +56,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
unsigned long address)
{
struct sh_pfc_window *window;
- int k;
+ unsigned int i;
/* scan through physical windows and convert address */
- for (k = 0; k < pfc->num_windows; k++) {
- window = pfc->window + k;
+ for (i = 0; i < pfc->num_windows; i++) {
+ window = pfc->window + i;
if (address < window->phys)
continue;
@@ -74,11 +71,33 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
return window->virt + (address - window->phys);
}
- /* no windows defined, register must be 1:1 mapped virt:phys */
- return (void __iomem *)address;
+ BUG();
+ return NULL;
+}
+
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
+{
+ unsigned int offset;
+ unsigned int i;
+
+ if (pfc->info->ranges == NULL)
+ return pin;
+
+ for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
+ const struct pinmux_range *range = &pfc->info->ranges[i];
+
+ if (pin <= range->end)
+ return pin >= range->begin
+ ? offset + pin - range->begin : -1;
+
+ offset += range->end - range->begin + 1;
+ }
+
+ return -EINVAL;
}
-static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
+static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
+ const struct pinmux_range *r)
{
if (enum_id < r->begin)
return 0;
@@ -89,8 +108,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
return 1;
}
-static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
- unsigned long reg_width)
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+ unsigned long reg_width)
{
switch (reg_width) {
case 8:
@@ -105,8 +124,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
return 0;
}
-static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
- unsigned long reg_width, unsigned long data)
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+ unsigned long data)
{
switch (reg_width) {
case 8:
@@ -123,39 +142,8 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
BUG();
}
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
-{
- unsigned long pos;
-
- pos = dr->reg_width - (in_pos + 1);
-
- pr_debug("read_bit: addr = %lx, pos = %ld, "
- "r_width = %ld\n", dr->reg, pos, dr->reg_width);
-
- return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
-}
-
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
- unsigned long value)
-{
- unsigned long pos;
-
- pos = dr->reg_width - (in_pos + 1);
-
- pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
- "r_width = %ld\n",
- dr->reg, !!value, pos, dr->reg_width);
-
- if (value)
- set_bit(pos, &dr->reg_shadow);
- else
- clear_bit(pos, &dr->reg_shadow);
-
- sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
-}
-
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
+ const struct pinmux_cfg_reg *crp,
unsigned long in_pos,
void __iomem **mapped_regp,
unsigned long *maskp,
@@ -176,24 +164,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
}
}
-static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
- unsigned long field)
-{
- void __iomem *mapped_reg;
- unsigned long mask, pos;
-
- sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
-
- pr_debug("read_reg: addr = %lx, field = %ld, "
- "r_width = %ld, f_width = %ld\n",
- crp->reg, field, crp->reg_width, crp->field_width);
-
- return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
-}
-
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
- struct pinmux_cfg_reg *crp,
+ const struct pinmux_cfg_reg *crp,
unsigned long field, unsigned long value)
{
void __iomem *mapped_reg;
@@ -201,9 +173,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
- pr_debug("write_reg addr = %lx, value = %ld, field = %ld, "
- "r_width = %ld, f_width = %ld\n",
- crp->reg, value, field, crp->reg_width, crp->field_width);
+ dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
+ "r_width = %ld, f_width = %ld\n",
+ crp->reg, value, field, crp->reg_width, crp->field_width);
mask = ~(mask << pos);
value = value << pos;
@@ -220,83 +192,11 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
}
-static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
-{
- struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
- struct pinmux_data_reg *data_reg;
- int k, n;
-
- if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
- return -1;
-
- k = 0;
- while (1) {
- data_reg = pfc->info->data_regs + k;
-
- if (!data_reg->reg_width)
- break;
-
- data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
-
- for (n = 0; n < data_reg->reg_width; n++) {
- if (data_reg->enum_ids[n] == gpiop->enum_id) {
- gpiop->flags &= ~PINMUX_FLAG_DREG;
- gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
- gpiop->flags &= ~PINMUX_FLAG_DBIT;
- gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
- return 0;
- }
- }
- k++;
- }
-
- BUG();
-
- return -1;
-}
-
-static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
-{
- struct pinmux_data_reg *drp;
- int k;
-
- for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
- sh_pfc_setup_data_reg(pfc, k);
-
- k = 0;
- while (1) {
- drp = pfc->info->data_regs + k;
-
- if (!drp->reg_width)
- break;
-
- drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
- drp->reg_width);
- k++;
- }
-}
-
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp)
-{
- struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
- int k, n;
-
- if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
- return -1;
-
- k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
- n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
- *drp = pfc->info->data_regs + k;
- *bitp = n;
- return 0;
-}
-
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
- struct pinmux_cfg_reg **crp, int *fieldp,
- int *valuep, unsigned long **cntp)
+ const struct pinmux_cfg_reg **crp, int *fieldp,
+ int *valuep)
{
- struct pinmux_cfg_reg *config_reg;
+ const struct pinmux_cfg_reg *config_reg;
unsigned long r_width, f_width, curr_width, ncomb;
int k, m, n, pos, bit_pos;
@@ -324,7 +224,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
*crp = config_reg;
*fieldp = m;
*valuep = n;
- *cntp = &config_reg->cnt[m];
return 0;
}
}
@@ -334,50 +233,42 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
k++;
}
- return -1;
+ return -EINVAL;
}
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
- pinmux_enum_t *enum_idp)
+static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
+ pinmux_enum_t *enum_idp)
{
- pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id;
- pinmux_enum_t *data = pfc->info->gpio_data;
+ const pinmux_enum_t *data = pfc->info->gpio_data;
int k;
- if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
- if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
- pr_err("non data/mark enum_id for gpio %d\n", gpio);
- return -1;
- }
- }
-
if (pos) {
*enum_idp = data[pos + 1];
return pos + 1;
}
for (k = 0; k < pfc->info->gpio_data_size; k++) {
- if (data[k] == enum_id) {
+ if (data[k] == mark) {
*enum_idp = data[k + 1];
return k + 1;
}
}
- pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
- return -1;
+ dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
+ mark);
+ return -EINVAL;
}
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
- int cfg_mode)
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
- struct pinmux_cfg_reg *cr = NULL;
+ const struct pinmux_cfg_reg *cr = NULL;
pinmux_enum_t enum_id;
- struct pinmux_range *range;
+ const struct pinmux_range *range;
int in_range, pos, field, value;
- unsigned long *cntp;
+ int ret;
switch (pinmux_type) {
-
+ case PINMUX_TYPE_GPIO:
case PINMUX_TYPE_FUNCTION:
range = NULL;
break;
@@ -399,33 +290,37 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
break;
default:
- goto out_err;
+ return -EINVAL;
}
pos = 0;
enum_id = 0;
field = 0;
value = 0;
+
+ /* Iterate over all the configuration fields we need to update. */
while (1) {
- pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id);
- if (pos <= 0)
- goto out_err;
+ pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
+ if (pos < 0)
+ return pos;
if (!enum_id)
break;
- /* first check if this is a function enum */
+ /* Check if the configuration field selects a function. If it
+ * doesn't, skip the field if it's not applicable to the
+ * requested pinmux type.
+ */
in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
if (!in_range) {
- /* not a function enum */
- if (range) {
- /*
- * other range exists, so this pin is
- * a regular GPIO pin that now is being
- * bound to a specific direction.
- *
- * for this case we only allow function enums
- * and the enums that match the other range.
+ if (pinmux_type == PINMUX_TYPE_FUNCTION) {
+ /* Functions are allowed to modify all
+ * fields.
+ */
+ in_range = 1;
+ } else if (pinmux_type != PINMUX_TYPE_GPIO) {
+ /* Input/output types can only modify fields
+ * that correspond to their respective ranges.
*/
in_range = sh_pfc_enum_in_range(enum_id, range);
@@ -436,60 +331,29 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
*/
if (in_range && enum_id == range->force)
continue;
- } else {
- /*
- * no other range exists, so this pin
- * must then be of the function type.
- *
- * allow function type pins to select
- * any combination of function/in/out
- * in their MARK lists.
- */
- in_range = 1;
}
+ /* GPIOs are only allowed to modify function fields. */
}
if (!in_range)
continue;
- if (sh_pfc_get_config_reg(pfc, enum_id, &cr,
- &field, &value, &cntp) != 0)
- goto out_err;
-
- switch (cfg_mode) {
- case GPIO_CFG_DRYRUN:
- if (!*cntp ||
- (sh_pfc_read_config_reg(pfc, cr, field) != value))
- continue;
- break;
-
- case GPIO_CFG_REQ:
- sh_pfc_write_config_reg(pfc, cr, field, value);
- *cntp = *cntp + 1;
- break;
+ ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
+ if (ret < 0)
+ return ret;
- case GPIO_CFG_FREE:
- *cntp = *cntp - 1;
- break;
- }
+ sh_pfc_write_config_reg(pfc, cr, field, value);
}
return 0;
- out_err:
- return -1;
}
static int sh_pfc_probe(struct platform_device *pdev)
{
- struct sh_pfc_soc_info *info;
+ const struct sh_pfc_soc_info *info;
struct sh_pfc *pfc;
int ret;
- /*
- * Ensure that the type encoding fits
- */
- BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
-
info = pdev->id_entry->driver_data
? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
if (info == NULL)
@@ -509,7 +373,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
spin_lock_init(&pfc->lock);
pinctrl_provide_dummies();
- sh_pfc_setup_data_regs(pfc);
/*
* Initialize pinctrl bindings first
@@ -529,13 +392,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
* PFC state as it is, given that there are already
* extant users of it that have succeeded by this point.
*/
- pr_notice("failed to init GPIO chip, ignoring...\n");
+ dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
}
#endif
platform_set_drvdata(pdev, pfc);
- pr_info("%s support registered\n", info->name);
+ dev_info(pfc->dev, "%s support registered\n", info->name);
return 0;
}
@@ -555,6 +418,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
}
static const struct platform_device_id sh_pfc_id_table[] = {
+#ifdef CONFIG_PINCTRL_PFC_R8A73A4
+ { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
+#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7740
{ "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ba7c33c33599..89cb4289d761 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,13 +26,17 @@ struct sh_pfc_pinctrl;
struct sh_pfc {
struct device *dev;
- struct sh_pfc_soc_info *info;
+ const struct sh_pfc_soc_info *info;
spinlock_t lock;
unsigned int num_windows;
struct sh_pfc_window *window;
+ unsigned int nr_pins;
+
struct sh_pfc_chip *gpio;
+ struct sh_pfc_chip *func;
+
struct sh_pfc_pinctrl *pinctrl;
};
@@ -42,31 +46,30 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
-int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos);
-void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
- unsigned long value);
-int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
- struct pinmux_data_reg **drp, int *bitp);
-int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos,
- pinmux_enum_t *enum_idp);
-int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
- int cfg_mode);
+unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
+ unsigned long reg_width);
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
+ unsigned long data);
+
+int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
+int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
-extern struct sh_pfc_soc_info r8a7740_pinmux_info;
-extern struct sh_pfc_soc_info r8a7779_pinmux_info;
-extern struct sh_pfc_soc_info sh7203_pinmux_info;
-extern struct sh_pfc_soc_info sh7264_pinmux_info;
-extern struct sh_pfc_soc_info sh7269_pinmux_info;
-extern struct sh_pfc_soc_info sh7372_pinmux_info;
-extern struct sh_pfc_soc_info sh73a0_pinmux_info;
-extern struct sh_pfc_soc_info sh7720_pinmux_info;
-extern struct sh_pfc_soc_info sh7722_pinmux_info;
-extern struct sh_pfc_soc_info sh7723_pinmux_info;
-extern struct sh_pfc_soc_info sh7724_pinmux_info;
-extern struct sh_pfc_soc_info sh7734_pinmux_info;
-extern struct sh_pfc_soc_info sh7757_pinmux_info;
-extern struct sh_pfc_soc_info sh7785_pinmux_info;
-extern struct sh_pfc_soc_info sh7786_pinmux_info;
-extern struct sh_pfc_soc_info shx3_pinmux_info;
+extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info sh7203_pinmux_info;
+extern const struct sh_pfc_soc_info sh7264_pinmux_info;
+extern const struct sh_pfc_soc_info sh7269_pinmux_info;
+extern const struct sh_pfc_soc_info sh7372_pinmux_info;
+extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
+extern const struct sh_pfc_soc_info sh7720_pinmux_info;
+extern const struct sh_pfc_soc_info sh7722_pinmux_info;
+extern const struct sh_pfc_soc_info sh7723_pinmux_info;
+extern const struct sh_pfc_soc_info sh7724_pinmux_info;
+extern const struct sh_pfc_soc_info sh7734_pinmux_info;
+extern const struct sh_pfc_soc_info sh7757_pinmux_info;
+extern const struct sh_pfc_soc_info sh7785_pinmux_info;
+extern const struct sh_pfc_soc_info sh7786_pinmux_info;
+extern const struct sh_pfc_soc_info shx3_pinmux_info;
#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a535075c8b69..d37efa7dcf90 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -9,8 +9,6 @@
* for more details.
*/
-#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
-
#include <linux/device.h>
#include <linux/gpio.h>
#include <linux/init.h>
@@ -21,9 +19,23 @@
#include "core.h"
+struct sh_pfc_gpio_data_reg {
+ const struct pinmux_data_reg *info;
+ unsigned long shadow;
+};
+
+struct sh_pfc_gpio_pin {
+ u8 dbit;
+ u8 dreg;
+};
+
struct sh_pfc_chip {
- struct sh_pfc *pfc;
- struct gpio_chip gpio_chip;
+ struct sh_pfc *pfc;
+ struct gpio_chip gpio_chip;
+
+ struct sh_pfc_window *mem;
+ struct sh_pfc_gpio_data_reg *regs;
+ struct sh_pfc_gpio_pin *pins;
};
static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -36,143 +48,367 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
return gpio_to_pfc_chip(gc)->pfc;
}
-static int sh_gpio_request(struct gpio_chip *gc, unsigned offset)
+static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
+ struct sh_pfc_gpio_data_reg **reg,
+ unsigned int *bit)
{
- return pinctrl_request_gpio(offset);
+ int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
+ struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
+
+ *reg = &chip->regs[gpio_pin->dreg];
+ *bit = gpio_pin->dbit;
}
-static void sh_gpio_free(struct gpio_chip *gc, unsigned offset)
+static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
+ const struct pinmux_data_reg *dreg)
{
- pinctrl_free_gpio(offset);
+ void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
+
+ return sh_pfc_read_raw_reg(mem, dreg->reg_width);
}
-static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value)
+static void gpio_write_data_reg(struct sh_pfc_chip *chip,
+ const struct pinmux_data_reg *dreg,
+ unsigned long value)
{
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
+ void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
- if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
- BUG();
- else
- sh_pfc_write_bit(dr, bit, value);
+ sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
}
-static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio)
+static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
{
- struct pinmux_data_reg *dr = NULL;
- int bit = 0;
+ struct sh_pfc *pfc = chip->pfc;
+ struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
+ const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
+ const struct pinmux_data_reg *dreg;
+ unsigned int bit;
+ unsigned int i;
+
+ for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
+ for (bit = 0; bit < dreg->reg_width; bit++) {
+ if (dreg->enum_ids[bit] == pin->enum_id) {
+ gpio_pin->dreg = i;
+ gpio_pin->dbit = bit;
+ return;
+ }
+ }
+ }
- if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0)
+ BUG();
+}
+
+static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
+{
+ struct sh_pfc *pfc = chip->pfc;
+ const struct pinmux_data_reg *dreg;
+ unsigned int i;
+
+ /* Count the number of data registers, allocate memory and initialize
+ * them.
+ */
+ for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
+ ;
+
+ chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
+ GFP_KERNEL);
+ if (chip->regs == NULL)
+ return -ENOMEM;
+
+ for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
+ chip->regs[i].info = dreg;
+ chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
+ }
+
+ for (i = 0; i < pfc->info->nr_pins; i++) {
+ if (pfc->info->pins[i].enum_id == 0)
+ continue;
+
+ gpio_setup_data_reg(chip, i);
+ }
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Pin GPIOs
+ */
+
+static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
+{
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ int idx = sh_pfc_get_pin_index(pfc, offset);
+
+ if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
return -EINVAL;
- return sh_pfc_read_bit(dr, bit);
+ return pinctrl_request_gpio(offset);
+}
+
+static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
+{
+ return pinctrl_free_gpio(offset);
+}
+
+static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
+ int value)
+{
+ struct sh_pfc_gpio_data_reg *reg;
+ unsigned long pos;
+ unsigned int bit;
+
+ gpio_get_data_reg(chip, offset, &reg, &bit);
+
+ pos = reg->info->reg_width - (bit + 1);
+
+ if (value)
+ set_bit(pos, &reg->shadow);
+ else
+ clear_bit(pos, &reg->shadow);
+
+ gpio_write_data_reg(chip, reg->info, reg->shadow);
}
-static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
{
return pinctrl_gpio_direction_input(offset);
}
-static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
int value)
{
- sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
return pinctrl_gpio_direction_output(offset);
}
-static int sh_gpio_get(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
{
- return sh_gpio_get_value(gpio_to_pfc(gc), offset);
+ struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
+ struct sh_pfc_gpio_data_reg *reg;
+ unsigned long pos;
+ unsigned int bit;
+
+ gpio_get_data_reg(chip, offset, &reg, &bit);
+
+ pos = reg->info->reg_width - (bit + 1);
+
+ return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
}
-static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
+static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
{
- sh_gpio_set_value(gpio_to_pfc(gc), offset, value);
+ gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
}
-static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
+static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct sh_pfc *pfc = gpio_to_pfc(gc);
- pinmux_enum_t enum_id;
- pinmux_enum_t *enum_ids;
- int i, k, pos;
-
- pos = 0;
- enum_id = 0;
- while (1) {
- pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
- if (pos <= 0 || !enum_id)
- break;
+ int i, k;
- for (i = 0; i < pfc->info->gpio_irq_size; i++) {
- enum_ids = pfc->info->gpio_irq[i].enum_ids;
- for (k = 0; enum_ids[k]; k++) {
- if (enum_ids[k] == enum_id)
- return pfc->info->gpio_irq[i].irq;
- }
+ for (i = 0; i < pfc->info->gpio_irq_size; i++) {
+ unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
+
+ for (k = 0; gpios[k]; k++) {
+ if (gpios[k] == offset)
+ return pfc->info->gpio_irq[i].irq;
}
}
return -ENOSYS;
}
-static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip)
+static int gpio_pin_setup(struct sh_pfc_chip *chip)
{
struct sh_pfc *pfc = chip->pfc;
struct gpio_chip *gc = &chip->gpio_chip;
+ int ret;
+
+ chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
+ GFP_KERNEL);
+ if (chip->pins == NULL)
+ return -ENOMEM;
+
+ ret = gpio_setup_data_regs(chip);
+ if (ret < 0)
+ return ret;
+
+ gc->request = gpio_pin_request;
+ gc->free = gpio_pin_free;
+ gc->direction_input = gpio_pin_direction_input;
+ gc->get = gpio_pin_get;
+ gc->direction_output = gpio_pin_direction_output;
+ gc->set = gpio_pin_set;
+ gc->to_irq = gpio_pin_to_irq;
- gc->request = sh_gpio_request;
- gc->free = sh_gpio_free;
- gc->direction_input = sh_gpio_direction_input;
- gc->get = sh_gpio_get;
- gc->direction_output = sh_gpio_direction_output;
- gc->set = sh_gpio_set;
- gc->to_irq = sh_gpio_to_irq;
+ gc->label = pfc->info->name;
+ gc->dev = pfc->dev;
+ gc->owner = THIS_MODULE;
+ gc->base = 0;
+ gc->ngpio = pfc->nr_pins;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Function GPIOs
+ */
+
+static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
+{
+ static bool __print_once;
+ struct sh_pfc *pfc = gpio_to_pfc(gc);
+ unsigned int mark = pfc->info->func_gpios[offset].enum_id;
+ unsigned long flags;
+ int ret;
+
+ if (!__print_once) {
+ dev_notice(pfc->dev,
+ "Use of GPIO API for function requests is deprecated."
+ " Convert to pinctrl\n");
+ __print_once = true;
+ }
+
+ if (mark == 0)
+ return -EINVAL;
- WARN_ON(pfc->info->first_gpio != 0); /* needs testing */
+ spin_lock_irqsave(&pfc->lock, flags);
+ ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
+ spin_unlock_irqrestore(&pfc->lock, flags);
+
+ return ret;
+}
+
+static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
+{
+}
+
+static int gpio_function_setup(struct sh_pfc_chip *chip)
+{
+ struct sh_pfc *pfc = chip->pfc;
+ struct gpio_chip *gc = &chip->gpio_chip;
+
+ gc->request = gpio_function_request;
+ gc->free = gpio_function_free;
gc->label = pfc->info->name;
gc->owner = THIS_MODULE;
- gc->base = pfc->info->first_gpio;
- gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1;
+ gc->base = pfc->nr_pins;
+ gc->ngpio = pfc->info->nr_func_gpios;
+
+ return 0;
}
-int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+/* -----------------------------------------------------------------------------
+ * Register/unregister
+ */
+
+static struct sh_pfc_chip *
+sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
+ struct sh_pfc_window *mem)
{
struct sh_pfc_chip *chip;
int ret;
chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
if (unlikely(!chip))
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
+ chip->mem = mem;
chip->pfc = pfc;
- sh_pfc_gpio_setup(chip);
+ ret = setup(chip);
+ if (ret < 0)
+ return ERR_PTR(ret);
ret = gpiochip_add(&chip->gpio_chip);
if (unlikely(ret < 0))
- return ret;
+ return ERR_PTR(ret);
+
+ dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
+ chip->gpio_chip.label, chip->gpio_chip.base,
+ chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
+
+ return chip;
+}
+
+int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
+{
+ const struct pinmux_range *ranges;
+ struct pinmux_range def_range;
+ struct sh_pfc_chip *chip;
+ unsigned int nr_ranges;
+ unsigned int i;
+ int ret;
+
+ if (pfc->info->data_regs == NULL)
+ return 0;
+
+ /* Find the memory window that contain the GPIO registers. Boards that
+ * register a separate GPIO device will not supply a memory resource
+ * that covers the data registers. In that case don't try to handle
+ * GPIOs.
+ */
+ for (i = 0; i < pfc->num_windows; ++i) {
+ struct sh_pfc_window *window = &pfc->window[i];
+
+ if (pfc->info->data_regs[0].reg >= window->phys &&
+ pfc->info->data_regs[0].reg < window->phys + window->size)
+ break;
+ }
+
+ if (i == pfc->num_windows)
+ return 0;
+
+ /* Register the real GPIOs chip. */
+ chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
pfc->gpio = chip;
- pr_info("%s handling gpio %d -> %d\n",
- pfc->info->name, pfc->info->first_gpio,
- pfc->info->last_gpio);
+ /* Register the GPIO to pin mappings. */
+ if (pfc->info->ranges == NULL) {
+ def_range.begin = 0;
+ def_range.end = pfc->info->nr_pins - 1;
+ ranges = &def_range;
+ nr_ranges = 1;
+ } else {
+ ranges = pfc->info->ranges;
+ nr_ranges = pfc->info->nr_ranges;
+ }
+
+ for (i = 0; i < nr_ranges; ++i) {
+ const struct pinmux_range *range = &ranges[i];
+
+ ret = gpiochip_add_pin_range(&chip->gpio_chip,
+ dev_name(pfc->dev),
+ range->begin, range->begin,
+ range->end - range->begin + 1);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Register the function GPIOs chip. */
+ if (pfc->info->nr_func_gpios == 0)
+ return 0;
+
+ chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+
+ pfc->func = chip;
return 0;
}
int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
{
- struct sh_pfc_chip *chip = pfc->gpio;
+ int err;
int ret;
- ret = gpiochip_remove(&chip->gpio_chip);
- if (unlikely(ret < 0))
- return ret;
+ ret = gpiochip_remove(&pfc->gpio->gpio_chip);
+ err = gpiochip_remove(&pfc->func->gpio_chip);
- pfc->gpio = NULL;
- return 0;
+ return ret < 0 ? ret : err;
}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
new file mode 100644
index 000000000000..bbff5596e922
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -0,0 +1,2587 @@
+/*
+ * Copyright (C) 2012-2013 Renesas Solutions Corp.
+ * Copyright (C) 2013 Magnus Damm
+ * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <mach/irqs.h>
+#include <mach/r8a73a4.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define CPU_ALL_PORT(fn, pfx, sfx) \
+ /* Port0 - Port30 */ \
+ PORT_10(fn, pfx, sfx), \
+ PORT_10(fn, pfx##1, sfx), \
+ PORT_10(fn, pfx##2, sfx), \
+ PORT_1(fn, pfx##30, sfx), \
+ /* Port32 - Port40 */ \
+ PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
+ PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
+ PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
+ PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
+ PORT_1(fn, pfx##40, sfx), \
+ /* Port64 - Port85 */ \
+ PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
+ PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
+ PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
+ PORT_10(fn, pfx##7, sfx), \
+ PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
+ PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
+ PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
+ /* Port96 - Port126 */ \
+ PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
+ PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
+ PORT_10(fn, pfx##10, sfx), \
+ PORT_10(fn, pfx##11, sfx), \
+ PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
+ PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
+ PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
+ PORT_1(fn, pfx##126, sfx), \
+ /* Port128 - Port134 */ \
+ PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
+ PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
+ PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
+ PORT_1(fn, pfx##134, sfx), \
+ /* Port160 - Port178 */ \
+ PORT_10(fn, pfx##16, sfx), \
+ PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
+ PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
+ PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
+ PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
+ PORT_1(fn, pfx##178, sfx), \
+ /* Port192 - Port222 */ \
+ PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
+ PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
+ PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
+ PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
+ PORT_10(fn, pfx##20, sfx), \
+ PORT_10(fn, pfx##21, sfx), \
+ PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
+ PORT_1(fn, pfx##222, sfx), \
+ /* Port224 - Port250 */ \
+ PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
+ PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
+ PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
+ PORT_10(fn, pfx##23, sfx), \
+ PORT_10(fn, pfx##24, sfx), \
+ PORT_1(fn, pfx##250, sfx), \
+ /* Port256 - Port283 */ \
+ PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
+ PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
+ PORT_10(fn, pfx##26, sfx), \
+ PORT_10(fn, pfx##27, sfx), \
+ PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
+ PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
+ /* Port288 - Port308 */ \
+ PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
+ PORT_10(fn, pfx##29, sfx), \
+ PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
+ PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
+ PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
+ PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
+ PORT_1(fn, pfx##308, sfx), \
+ /* Port320 - Port329 */ \
+ PORT_10(fn, pfx##32, sfx)
+
+
+enum {
+ PINMUX_RESERVED = 0,
+
+ /* PORT0_DATA -> PORT329_DATA */
+ PINMUX_DATA_BEGIN,
+ PORT_ALL(DATA),
+ PINMUX_DATA_END,
+
+ /* PORT0_IN -> PORT329_IN */
+ PINMUX_INPUT_BEGIN,
+ PORT_ALL(IN),
+ PINMUX_INPUT_END,
+
+ /* PORT0_OUT -> PORT329_OUT */
+ PINMUX_OUTPUT_BEGIN,
+ PORT_ALL(OUT),
+ PINMUX_OUTPUT_END,
+
+ PINMUX_FUNCTION_BEGIN,
+ PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
+ PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
+ PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
+ PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
+ PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
+ PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
+ PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
+ PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
+ PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
+ PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
+
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ MSEL1CR_25_0, MSEL1CR_25_1,
+ MSEL1CR_24_0, MSEL1CR_24_1,
+ MSEL1CR_22_0, MSEL1CR_22_1,
+ MSEL1CR_21_0, MSEL1CR_21_1,
+ MSEL1CR_20_0, MSEL1CR_20_1,
+ MSEL1CR_19_0, MSEL1CR_19_1,
+ MSEL1CR_18_0, MSEL1CR_18_1,
+ MSEL1CR_17_0, MSEL1CR_17_1,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ MSEL1CR_11_0, MSEL1CR_11_1,
+ MSEL1CR_10_0, MSEL1CR_10_1,
+ MSEL1CR_09_0, MSEL1CR_09_1,
+ MSEL1CR_08_0, MSEL1CR_08_1,
+ MSEL1CR_07_0, MSEL1CR_07_1,
+ MSEL1CR_06_0, MSEL1CR_06_1,
+ MSEL1CR_05_0, MSEL1CR_05_1,
+ MSEL1CR_04_0, MSEL1CR_04_1,
+ MSEL1CR_03_0, MSEL1CR_03_1,
+ MSEL1CR_02_0, MSEL1CR_02_1,
+ MSEL1CR_01_0, MSEL1CR_01_1,
+ MSEL1CR_00_0, MSEL1CR_00_1,
+
+ MSEL3CR_31_0, MSEL3CR_31_1,
+ MSEL3CR_28_0, MSEL3CR_28_1,
+ MSEL3CR_27_0, MSEL3CR_27_1,
+ MSEL3CR_26_0, MSEL3CR_26_1,
+ MSEL3CR_23_0, MSEL3CR_23_1,
+ MSEL3CR_22_0, MSEL3CR_22_1,
+ MSEL3CR_21_0, MSEL3CR_21_1,
+ MSEL3CR_20_0, MSEL3CR_20_1,
+ MSEL3CR_19_0, MSEL3CR_19_1,
+ MSEL3CR_18_0, MSEL3CR_18_1,
+ MSEL3CR_17_0, MSEL3CR_17_1,
+ MSEL3CR_16_0, MSEL3CR_16_1,
+ MSEL3CR_15_0, MSEL3CR_15_1,
+ MSEL3CR_12_0, MSEL3CR_12_1,
+ MSEL3CR_11_0, MSEL3CR_11_1,
+ MSEL3CR_10_0, MSEL3CR_10_1,
+ MSEL3CR_09_0, MSEL3CR_09_1,
+ MSEL3CR_06_0, MSEL3CR_06_1,
+ MSEL3CR_03_0, MSEL3CR_03_1,
+ MSEL3CR_01_0, MSEL3CR_01_1,
+ MSEL3CR_00_0, MSEL3CR_00_1,
+
+ MSEL4CR_30_0, MSEL4CR_30_1,
+ MSEL4CR_29_0, MSEL4CR_29_1,
+ MSEL4CR_28_0, MSEL4CR_28_1,
+ MSEL4CR_27_0, MSEL4CR_27_1,
+ MSEL4CR_26_0, MSEL4CR_26_1,
+ MSEL4CR_25_0, MSEL4CR_25_1,
+ MSEL4CR_24_0, MSEL4CR_24_1,
+ MSEL4CR_23_0, MSEL4CR_23_1,
+ MSEL4CR_22_0, MSEL4CR_22_1,
+ MSEL4CR_21_0, MSEL4CR_21_1,
+ MSEL4CR_20_0, MSEL4CR_20_1,
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ MSEL4CR_17_0, MSEL4CR_17_1,
+ MSEL4CR_16_0, MSEL4CR_16_1,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ MSEL4CR_14_0, MSEL4CR_14_1,
+ MSEL4CR_13_0, MSEL4CR_13_1,
+ MSEL4CR_12_0, MSEL4CR_12_1,
+ MSEL4CR_11_0, MSEL4CR_11_1,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ MSEL4CR_09_0, MSEL4CR_09_1,
+ MSEL4CR_07_0, MSEL4CR_07_1,
+ MSEL4CR_04_0, MSEL4CR_04_1,
+ MSEL4CR_01_0, MSEL4CR_01_1,
+
+ MSEL5CR_31_0, MSEL5CR_31_1,
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ MSEL5CR_28_0, MSEL5CR_28_1,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ MSEL5CR_26_0, MSEL5CR_26_1,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ MSEL5CR_24_0, MSEL5CR_24_1,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ MSEL5CR_22_0, MSEL5CR_22_1,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ MSEL5CR_20_0, MSEL5CR_20_1,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ MSEL5CR_18_0, MSEL5CR_18_1,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ MSEL5CR_16_0, MSEL5CR_16_1,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ MSEL5CR_09_0, MSEL5CR_09_1,
+ MSEL5CR_08_0, MSEL5CR_08_1,
+ MSEL5CR_07_0, MSEL5CR_07_1,
+ MSEL5CR_06_0, MSEL5CR_06_1,
+
+ MSEL8CR_16_0, MSEL8CR_16_1,
+ MSEL8CR_01_0, MSEL8CR_01_1,
+ MSEL8CR_00_0, MSEL8CR_00_1,
+
+ PINMUX_FUNCTION_END,
+
+ PINMUX_MARK_BEGIN,
+
+
+#define F1(a) a##_MARK
+#define F2(a) a##_MARK
+#define F3(a) a##_MARK
+#define F4(a) a##_MARK
+#define F5(a) a##_MARK
+#define F6(a) a##_MARK
+#define F7(a) a##_MARK
+#define IRQ(a) IRQ##a##_MARK
+
+ F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
+ F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
+ F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
+ F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
+ F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
+ F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
+ F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
+ F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
+ F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
+ F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
+ F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
+ F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
+ F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
+ F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
+ F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
+ F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
+ F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
+ F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
+ F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
+ F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
+ F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
+ F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
+ F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
+ F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
+ F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
+ F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
+ F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
+ F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
+ F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
+ F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
+ F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
+ F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
+
+ F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
+ F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
+ F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
+ F1(SCIFA1_RTS), F7(CSCIF1_RTS),
+ F1(SCIFA1_CTS), F7(CSCIF1_CTS),
+ F1(SCIFA1_SCK), F7(CSCIF1_SCK),
+ F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
+ F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
+ F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
+ F7(CHSCIF0_HSCK), /* Port40 */
+
+ F1(PDM0_DATA), /* Port64 */
+ F1(PDM1_DATA),
+ F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
+ IRQ(40),
+ F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
+ F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
+ F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
+ F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
+ F7(CHSCIF1_HRTS), /* Port70 */
+ F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
+ F7(CHSCIF1_HCTS),
+ F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
+ F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
+ F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
+ F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
+ F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
+
+ F1(KEYIN0), /* Port96 */
+ F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
+ F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
+ F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
+ F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
+ F2(KEYOUT7), F5(RFANAEN), IRQ(45),
+ F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
+ F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
+ F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
+ F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
+ F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
+ F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
+ F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
+ F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
+ F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
+ F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
+ F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
+ F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
+ F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
+ F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
+ F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
+ F5(SIM0_VOLTSEL1), /* Port130 */
+ F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
+ F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
+ F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
+ IRQ(20), /* Port160 */
+ IRQ(21), IRQ(22), IRQ(23),
+ F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
+ F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
+ F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
+ IRQ(24), IRQ(25), IRQ(26), IRQ(27),
+ F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
+ F1(A9), F2(MMCD1_6), IRQ(32),
+ F1(A8), F2(MMCD1_5), IRQ(33),
+ F1(A7), F2(MMCD1_4), IRQ(34),
+ F1(A6), F2(MMCD1_3), IRQ(35),
+ F1(A5), F2(MMCD1_2), IRQ(36),
+ F1(A4), F2(MMCD1_1), IRQ(37),
+ F1(A3), F2(MMCD1_0), IRQ(38),
+ F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
+ F1(A1),
+ F1(A0), F2(BS),
+ F1(CKO), F2(MMCCLK1),
+ F1(CS0_N), F5(SIM0_GPO1),
+ F1(CS2_N), F5(SIM0_GPO2),
+ F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
+ F1(D15), F5(GIO_OUT15),
+ F1(D14), F5(GIO_OUT14),
+ F1(D13), F5(GIO_OUT13),
+ F1(D12), F5(GIO_OUT12), /* Port210 */
+ F1(D11), F5(WGM_TXP2),
+ F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
+ F1(D9), F2(VIO_D9), F5(GIO_OUT9),
+ F1(D8), F2(VIO_D8), F5(GIO_OUT8),
+ F1(D7), F2(VIO_D7), F5(GIO_OUT7),
+ F1(D6), F2(VIO_D6), F5(GIO_OUT6),
+ F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
+ F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
+ F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
+ F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
+ F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
+ F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
+ F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
+ F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
+ F1(WE0_N), F2(RDWR_227),
+ F1(WE1_N), F5(SIM0_GPO0),
+ F1(PWMO), F2(VIO_CKO1_229),
+ F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
+ F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
+ F2(VIO_CKO3_233), F4(SF_PORT_1_233),
+ F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
+ F1(FSIAISLD), F2(PDM3_DATA_235),
+ F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
+ F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
+ F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
+ F1(FSIBISLD), /* Port240 */
+ F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
+ F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
+ F1(FSIBCK), F3(ISP_SHUTTER0_245),
+ F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
+ F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
+ F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
+ F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
+ F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
+ F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
+ F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
+ F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
+ F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
+ F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
+ F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
+ F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
+ F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
+ F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
+ F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
+ F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
+ F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
+ F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
+ F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
+ F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
+ F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
+ F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
+ F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
+ F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
+ F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
+ F4(MSIOF6_SS1), /* Port300 */
+ F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
+ F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
+ F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
+ F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
+ IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
+ IRQ(55), IRQ(56), IRQ(57),
+ PINMUX_MARK_END,
+};
+
+#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
+#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
+
+static const pinmux_enum_t pinmux_data[] = {
+ /* specify valid pin states for each pin in GPIO mode */
+ PINMUX_DATA_ALL(),
+
+ /* Port0 */
+ PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
+ PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
+ PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
+ PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
+
+ /* Port1 */
+ PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
+ PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
+ PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
+ PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
+
+ /* Port2 */
+ PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
+ PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
+ PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
+ PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
+
+ /* Port3 */
+ PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
+ PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
+ PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
+ PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
+
+ /* Port4 */
+ PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
+ PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
+ PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
+ PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
+
+ /* Port5 */
+ PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
+ PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
+ PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
+ PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
+
+ /* Port6 */
+ PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
+ PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
+ PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
+ PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
+
+ /* Port7 */
+ PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
+ PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
+ PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
+ PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
+
+ /* Port8 */
+ PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
+ PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
+ PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
+ PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
+
+ /* Port9 */
+ PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
+ PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
+ PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
+ PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
+
+ /* Port10 */
+ PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
+ PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
+ PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
+ PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
+
+ /* Port11 */
+ PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
+ PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
+ PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
+ PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
+
+ /* Port12 */
+ PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
+ PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
+ PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
+ PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
+
+ /* Port13 */
+ PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
+ PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
+ PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
+ PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
+ PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
+
+ /* Port14 */
+ PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
+ PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
+ PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
+ PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
+ PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
+
+ /* Port15 */
+ PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
+ PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
+ PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
+ PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
+
+ /* Port16 */
+ PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
+ PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
+ PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
+
+ /* Port17 */
+ PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
+ PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
+ PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
+
+ /* Port18 */
+ PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
+ PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
+ PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
+
+ /* Port19 */
+ PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
+ PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
+ PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
+
+ /* Port20 */
+ PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
+ PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
+ PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
+
+ /* Port21 */
+ PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
+ PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
+ PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
+
+ /* Port22 */
+ PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
+ PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
+ PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
+
+ /* Port23 */
+ PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
+ PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
+ PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
+
+ /* Port24 */
+ PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
+ PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
+ PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
+ PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
+
+ /* Port25 */
+ PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
+ PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
+ PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
+
+ /* Port26 */
+ PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
+ PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
+ PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
+ PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
+
+ /* Port27 */
+ PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
+ PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
+ PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
+ PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
+
+ /* Port28 */
+ PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
+ PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
+ PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
+
+ /* Port29 */
+ PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
+ PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
+ PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
+
+ /* Port30 */
+ PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
+ PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
+ PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
+
+ /* Port32 */
+ PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
+ PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
+ PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
+
+ /* Port33 */
+ PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
+ PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
+ PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
+
+ /* Port34 */
+ PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
+ PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
+ PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
+
+ /* Port35 */
+ PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
+ PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
+
+ /* Port36 */
+ PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
+ PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
+
+ /* Port37 */
+ PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
+ PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
+
+ /* Port38 */
+ PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
+ PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
+ PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
+ PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
+
+ /* Port39 */
+ PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
+ PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
+ PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
+ PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
+
+ /* Port40 */
+ PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
+ PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
+ PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
+ PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
+
+ /* Port64 */
+ PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
+
+ /* Port65 */
+ PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
+
+ /* Port66 */
+ PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
+ PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
+ PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
+ PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
+ PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
+
+ /* Port67 */
+ PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
+ PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
+ PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
+ PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
+
+ /* Port68 */
+ PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
+ PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
+ PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
+ PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
+
+ /* Port69 */
+ PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
+ PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
+ PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
+ PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
+
+ /* Port70 */
+ PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
+ PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
+ PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
+ PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
+ PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
+
+ /* Port71 */
+ PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
+ PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
+ PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
+ PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
+ PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
+
+ /* Port72 */
+ PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
+ PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
+ PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
+ PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
+
+ /* Port73 */
+ PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
+ PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
+ PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
+ PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
+
+ /* Port74 - Port85 */
+ PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
+ PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
+ PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
+ PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
+ PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
+ PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
+ PINMUX_DATA(TXP_MARK, PORT80_FN1),
+ PINMUX_DATA(TXP2_MARK, PORT81_FN1),
+ PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
+ PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
+ PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
+ PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
+
+ /* Port96 - Port101 */
+ PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
+ PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
+ PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
+ PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
+ PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
+ PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
+
+ /* Port102 */
+ PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
+ PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
+
+ /* Port103 */
+ PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
+ PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
+
+ /* Port104 - Port108 */
+ PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
+ PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
+ PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
+ PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
+ PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
+
+ /* Port109 */
+ PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
+ PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
+
+ /* Port110 */
+ PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
+ PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
+
+ /* Port111 */
+ PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
+ PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
+ PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
+
+ /* Port112 */
+ PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
+ PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
+ PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
+ PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
+
+ /* Port113 */
+ PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
+ PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
+ PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
+ PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
+
+ /* Port114 */
+ PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
+ PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
+ PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
+ PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
+
+ /* Port115 */
+ PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
+ PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
+ PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
+ PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
+
+ /* Port116 */
+ PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
+ PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
+
+ /* Port117 */
+ PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
+ PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
+
+ /* Port118 */
+ PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
+ PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
+
+ /* Port119 */
+ PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
+ PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
+
+ /* Port120 */
+ PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
+ PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
+ PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
+
+ /* Port121 */
+ PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
+ PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
+
+ /* Port122 */
+ PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
+ PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
+
+ /* Port123 */
+ PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
+ PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
+
+ /* Port124 */
+ PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
+
+ /* Port125 */
+ PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
+ PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
+ PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
+ PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
+
+ /* Port126 */
+ PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
+ PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
+ PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
+
+ /* Port128 */
+ PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
+ PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
+ PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
+ PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
+
+ /* Port129 */
+ PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
+ PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
+ PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
+
+ /* Port130 */
+ PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
+ PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
+ PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
+ PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
+
+ /* Port131 */
+ PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
+ PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
+
+ /* Port132 */
+ PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
+ PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
+ PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
+
+ /* Port133 */
+ PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
+ PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
+ PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
+ PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
+
+ /* Port134 */
+ PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
+ PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
+ PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
+
+ /* Port160 - Port178 */
+ PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
+ PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
+ PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
+ PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
+ PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
+ PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
+ PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
+ PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
+ PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
+ PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
+ PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
+ PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
+ PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
+ PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
+ PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
+ PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
+ PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
+ PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
+ PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
+
+ /* Port192 - Port200 FN1 */
+ PINMUX_DATA(A10_MARK, PORT192_FN1),
+ PINMUX_DATA(A9_MARK, PORT193_FN1),
+ PINMUX_DATA(A8_MARK, PORT194_FN1),
+ PINMUX_DATA(A7_MARK, PORT195_FN1),
+ PINMUX_DATA(A6_MARK, PORT196_FN1),
+ PINMUX_DATA(A5_MARK, PORT197_FN1),
+ PINMUX_DATA(A4_MARK, PORT198_FN1),
+ PINMUX_DATA(A3_MARK, PORT199_FN1),
+ PINMUX_DATA(A2_MARK, PORT200_FN1),
+
+ /* Port192 - Port200 FN2 */
+ PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
+ PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
+ PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
+ PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
+ PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
+ PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
+ PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
+ PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
+ PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
+
+ /* Port192 - Port200 IRQ */
+ PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
+ PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
+ PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
+ PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
+ PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
+ PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
+ PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
+ PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
+ PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
+
+ /* Port201 */
+ PINMUX_DATA(A1_MARK, PORT201_FN1),
+
+ /* Port202 */
+ PINMUX_DATA(A0_MARK, PORT202_FN1),
+ PINMUX_DATA(BS_MARK, PORT202_FN2),
+
+ /* Port203 */
+ PINMUX_DATA(CKO_MARK, PORT203_FN1),
+ PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
+
+ /* Port204 */
+ PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
+ PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
+
+ /* Port205 */
+ PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
+ PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
+
+ /* Port206 */
+ PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
+ PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
+ PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
+
+ /* Port207 - Port212 FN1 */
+ PINMUX_DATA(D15_MARK, PORT207_FN1),
+ PINMUX_DATA(D14_MARK, PORT208_FN1),
+ PINMUX_DATA(D13_MARK, PORT209_FN1),
+ PINMUX_DATA(D12_MARK, PORT210_FN1),
+ PINMUX_DATA(D11_MARK, PORT211_FN1),
+ PINMUX_DATA(D10_MARK, PORT212_FN1),
+
+ /* Port207 - Port212 FN5 */
+ PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
+ PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
+ PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
+ PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
+ PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
+ PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
+
+ /* Port213 - Port222 FN1 */
+ PINMUX_DATA(D9_MARK, PORT213_FN1),
+ PINMUX_DATA(D8_MARK, PORT214_FN1),
+ PINMUX_DATA(D7_MARK, PORT215_FN1),
+ PINMUX_DATA(D6_MARK, PORT216_FN1),
+ PINMUX_DATA(D5_MARK, PORT217_FN1),
+ PINMUX_DATA(D4_MARK, PORT218_FN1),
+ PINMUX_DATA(D3_MARK, PORT219_FN1),
+ PINMUX_DATA(D2_MARK, PORT220_FN1),
+ PINMUX_DATA(D1_MARK, PORT221_FN1),
+ PINMUX_DATA(D0_MARK, PORT222_FN1),
+
+ /* Port213 - Port222 FN2 */
+ PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
+ PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
+ PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
+ PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
+ PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
+ PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
+ PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
+ PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
+ PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
+ PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
+
+ /* Port213 - Port222 FN5 */
+ PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
+ PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
+ PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
+ PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
+ PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
+ PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
+ PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
+ PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
+ PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
+ PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
+
+ /* Port224 */
+ PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
+ PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
+ PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
+
+ /* Port225 */
+ PINMUX_DATA(RD_N_MARK, PORT225_FN1),
+
+ /* Port226 */
+ PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
+ PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
+ PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
+
+ /* Port227 */
+ PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
+ PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
+
+ /* Port228 */
+ PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
+ PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
+
+ /* Port229 */
+ PINMUX_DATA(PWMO_MARK, PORT229_FN1),
+ PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
+
+ /* Port230 */
+ PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
+ PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
+
+ /* Port231 */
+ PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
+ PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
+
+ /* Port232 */
+ PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
+ PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
+
+ /* Port233 */
+ PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
+ PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
+
+ /* Port234 */
+ PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
+ PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
+ PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
+
+ /* Port235 */
+ PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
+ PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
+
+ /* Port236 */
+ PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
+ PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
+ PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
+
+ /* Port237 */
+ PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
+ PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
+
+ /* Port238 */
+ PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
+ PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
+
+ /* Port239 */
+ PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
+ PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
+
+ /* Port240 */
+ PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
+
+ /* Port241 */
+ PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
+ PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
+
+ /* Port242 */
+ PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
+ PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
+
+ /* Port243 */
+ PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
+ PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
+
+ /* Port244 */
+ PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
+ PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
+
+ /* Port245 */
+ PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
+ PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
+
+ /* Port246 - Port250 FN1 */
+ PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
+ PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
+ PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
+ PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
+ PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
+
+ /* Port256 - Port258 */
+ PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
+ PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
+ PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
+
+ /* Port259 */
+ PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
+ PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
+
+ /* Port260 */
+ PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
+
+ /* Port261 */
+ PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
+ PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
+
+ /* Port262 */
+ PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
+
+ /* Port263 - Port266 FN1 */
+ PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
+ PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
+ PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
+ PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
+
+ /* Port263 - Port266 FN4 */
+ PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
+ PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
+ PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
+ PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
+
+ /* Port267 */
+ PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
+
+ /* Port268 */
+ PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
+ PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
+
+ /* Port269 */
+ PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
+ PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
+
+ /* Port270 - Port273 FN1 */
+ PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
+ PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
+ PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
+ PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
+
+ /* Port270 - Port273 FN3 */
+ PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
+ PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
+ PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
+ PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
+
+ /* Port274 */
+ PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
+ PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
+
+ /* Port275 - Port280 */
+ PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
+ PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
+ PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
+ PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
+ PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
+ PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
+
+ /* Port281 */
+ PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
+ PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
+
+ /* Port282 */
+ PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
+ PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
+
+ /* Port283 */
+ PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
+
+ /* Port289 */
+ PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
+ PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
+
+ /* Port290 */
+ PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
+ PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
+ PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
+
+ /* Port291 - Port294 FN1 */
+ PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
+ PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
+ PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
+ PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
+
+ /* Port291 - Port294 FN3 */
+ PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
+ PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
+ PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
+ PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
+
+ /* Port295 */
+ PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
+ PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
+ PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
+ PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
+
+ /* Port296 */
+ PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
+ PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
+ PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
+
+ /* Port297 - Port300 FN1 */
+ PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
+ PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
+ PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
+ PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
+
+ /* Port297 - Port300 FN2 */
+ PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
+ PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
+ PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
+ PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
+
+ /* Port297 - Port300 FN3 */
+ PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
+ PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
+ PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
+ PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
+
+ /* Port297 - Port300 FN4 */
+ PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
+ PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
+ PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
+ PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
+
+ /* Port301 */
+ PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
+ PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
+
+ /* Port302 - Port306 FN1 */
+ PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
+ PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
+ PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
+ PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
+ PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
+
+ /* Port302 - Port306 FN3 */
+ PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
+ PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
+ PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
+ PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
+ PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
+
+ /* Port307 */
+ PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
+
+ /* Port308 */
+ PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
+ PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
+
+ /* Port320 - Port329 */
+ PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
+ PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
+ PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
+ PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
+ PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
+ PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
+ PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
+ PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
+ PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
+ PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
+};
+
+#define R8A73A4_PIN(pin, cfgs) \
+ { \
+ .name = __stringify(PORT##pin), \
+ .enum_id = PORT##pin##_DATA, \
+ .configs = cfgs, \
+ }
+
+#define __O (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
+#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
+
+static struct sh_pfc_pin pinmux_pins[] = {
+ R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
+ R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
+ R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
+ R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
+ R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
+ R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
+ R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
+ R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
+ R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
+ R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
+ R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
+ R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
+ R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
+ R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
+ R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
+ R8A73A4_PIN_IO_PU_PD(30),
+ R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
+ R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
+ R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
+ R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
+ R8A73A4_PIN_IO_PU_PD(40),
+ R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
+ R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
+ R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
+ R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
+ R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
+ R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
+ R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
+ R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
+ R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
+ R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
+ R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
+ R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
+ R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
+ R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
+ R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
+ R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
+ R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
+ R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
+ R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
+ R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
+ R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
+ R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
+ R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
+ R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
+ R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
+ R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
+ R8A73A4_PIN_IO_PU_PD(126),
+ R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
+ R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
+ R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
+ R8A73A4_PIN_IO_PU_PD(134),
+ R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
+ R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
+ R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
+ R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
+ R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
+ R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
+ R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
+ R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
+ R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
+ R8A73A4_PIN_IO_PU_PD(178),
+ R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
+ R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
+ R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
+ R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
+ R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
+ R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
+ R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
+ R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
+ R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
+ R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
+ R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
+ R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
+ R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
+ R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
+ R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
+ R8A73A4_PIN_IO_PU_PD(222),
+ R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
+ R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
+ R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
+ R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
+ R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
+ R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
+ R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
+ R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
+ R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
+ R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
+ R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
+ R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
+ R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
+ R8A73A4_PIN_IO_PU_PD(250),
+ R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
+ R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
+ R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
+ R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
+ R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
+ R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
+ R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
+ R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
+ R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
+ R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
+ R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
+ R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
+ R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
+ R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
+ R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
+ R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
+ R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
+ R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
+ R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
+ R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
+ R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
+ R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
+ R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
+ R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
+ R8A73A4_PIN_IO_PU_PD(308),
+ R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
+ R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
+ R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
+ R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
+ R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
+};
+
+static const struct pinmux_range pinmux_ranges[] = {
+ {.begin = 0, .end = 30,},
+ {.begin = 32, .end = 40,},
+ {.begin = 64, .end = 85,},
+ {.begin = 96, .end = 126,},
+ {.begin = 128, .end = 134,},
+ {.begin = 160, .end = 178,},
+ {.begin = 192, .end = 222,},
+ {.begin = 224, .end = 250,},
+ {.begin = 256, .end = 283,},
+ {.begin = 288, .end = 308,},
+ {.begin = 320, .end = 329,},
+};
+
+/* - IRQC ------------------------------------------------------------------- */
+#define IRQC_PINS_MUX(pin, irq_mark) \
+static const unsigned int irqc_irq##irq_mark##_pins[] = { \
+ pin, \
+}; \
+static const unsigned int irqc_irq##irq_mark##_mux[] = { \
+ IRQ##irq_mark##_MARK, \
+}
+IRQC_PINS_MUX(0, 0);
+IRQC_PINS_MUX(1, 1);
+IRQC_PINS_MUX(2, 2);
+IRQC_PINS_MUX(3, 3);
+IRQC_PINS_MUX(4, 4);
+IRQC_PINS_MUX(5, 5);
+IRQC_PINS_MUX(6, 6);
+IRQC_PINS_MUX(7, 7);
+IRQC_PINS_MUX(8, 8);
+IRQC_PINS_MUX(9, 9);
+IRQC_PINS_MUX(10, 10);
+IRQC_PINS_MUX(11, 11);
+IRQC_PINS_MUX(12, 12);
+IRQC_PINS_MUX(13, 13);
+IRQC_PINS_MUX(14, 14);
+IRQC_PINS_MUX(15, 15);
+IRQC_PINS_MUX(66, 40);
+IRQC_PINS_MUX(84, 19);
+IRQC_PINS_MUX(85, 18);
+IRQC_PINS_MUX(102, 41);
+IRQC_PINS_MUX(103, 42);
+IRQC_PINS_MUX(109, 43);
+IRQC_PINS_MUX(110, 44);
+IRQC_PINS_MUX(111, 45);
+IRQC_PINS_MUX(112, 46);
+IRQC_PINS_MUX(113, 47);
+IRQC_PINS_MUX(114, 48);
+IRQC_PINS_MUX(115, 49);
+IRQC_PINS_MUX(160, 20);
+IRQC_PINS_MUX(161, 21);
+IRQC_PINS_MUX(162, 22);
+IRQC_PINS_MUX(163, 23);
+IRQC_PINS_MUX(175, 24);
+IRQC_PINS_MUX(176, 25);
+IRQC_PINS_MUX(177, 26);
+IRQC_PINS_MUX(178, 27);
+IRQC_PINS_MUX(192, 31);
+IRQC_PINS_MUX(193, 32);
+IRQC_PINS_MUX(194, 33);
+IRQC_PINS_MUX(195, 34);
+IRQC_PINS_MUX(196, 35);
+IRQC_PINS_MUX(197, 36);
+IRQC_PINS_MUX(198, 37);
+IRQC_PINS_MUX(199, 38);
+IRQC_PINS_MUX(200, 39);
+IRQC_PINS_MUX(290, 51);
+IRQC_PINS_MUX(296, 52);
+IRQC_PINS_MUX(301, 50);
+IRQC_PINS_MUX(320, 16);
+IRQC_PINS_MUX(321, 17);
+IRQC_PINS_MUX(322, 28);
+IRQC_PINS_MUX(323, 29);
+IRQC_PINS_MUX(324, 30);
+IRQC_PINS_MUX(325, 53);
+IRQC_PINS_MUX(326, 54);
+IRQC_PINS_MUX(327, 55);
+IRQC_PINS_MUX(328, 56);
+IRQC_PINS_MUX(329, 57);
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+ /* SCIFA0_RXD, SCIFA0_TXD */
+ 117, 116,
+};
+static const unsigned int scifa0_data_mux[] = {
+ SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+ /* SCIFA0_SCK */
+ 34,
+};
+static const unsigned int scifa0_clk_mux[] = {
+ SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+ /* SCIFA0_RTS, SCIFA0_CTS */
+ 32, 33,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+ SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+ /* SCIFA1_RXD, SCIFA1_TXD */
+ 119, 118,
+};
+static const unsigned int scifa1_data_mux[] = {
+ SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+ /* SCIFA1_SCK */
+ 37,
+};
+static const unsigned int scifa1_clk_mux[] = {
+ SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+ /* SCIFA1_RTS, SCIFA1_CTS */
+ 35, 36,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+ SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+ /* SCIFB0_RXD, SCIFB0_TXD */
+ 123, 122,
+};
+static const unsigned int scifb0_data_mux[] = {
+ SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+ /* SCIFB0_SCK */
+ 40,
+};
+static const unsigned int scifb0_clk_mux[] = {
+ SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+ /* SCIFB0_RTS, SCIFB0_CTS */
+ 38, 39,
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+ SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+ /* SCIFB1_RXD, SCIFB1_TXD */
+ 27, 26,
+};
+static const unsigned int scifb1_data_mux[] = {
+ SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+ /* SCIFB1_SCK */
+ 28,
+};
+static const unsigned int scifb1_clk_mux[] = {
+ SCIFB1_SCK_28_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+ /* SCIFB1_RTS, SCIFB1_CTS */
+ 24, 25,
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+ SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+ /* SCIFB1_RXD, SCIFB1_TXD */
+ 72, 67,
+};
+static const unsigned int scifb1_data_b_mux[] = {
+ SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+ /* SCIFB1_SCK */
+ 261,
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+ SCIFB1_SCK_261_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+ /* SCIFB1_RTS, SCIFB1_CTS */
+ 70, 71,
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+ SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+ /* SCIFB2_RXD, SCIFB2_TXD */
+ 69, 68,
+};
+static const unsigned int scifb2_data_mux[] = {
+ SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+ /* SCIFB2_SCK */
+ 262,
+};
+static const unsigned int scifb2_clk_mux[] = {
+ SCIFB2_SCK_262_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+ /* SCIFB2_RTS, SCIFB2_CTS */
+ 73, 66,
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+ SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+ /* SCIFB2_RXD, SCIFB2_TXD */
+ 297, 295,
+};
+static const unsigned int scifb2_data_b_mux[] = {
+ SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+ /* SCIFB2_SCK */
+ 299,
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+ SCIFB2_SCK_299_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+ /* SCIFB2_RTS, SCIFB2_CTS */
+ 300, 298,
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+ SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
+};
+/* - SCIFB3 ----------------------------------------------------------------- */
+static const unsigned int scifb3_data_pins[] = {
+ /* SCIFB3_RXD, SCIFB3_TXD */
+ 22, 21,
+};
+static const unsigned int scifb3_data_mux[] = {
+ SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
+};
+static const unsigned int scifb3_clk_pins[] = {
+ /* SCIFB3_SCK */
+ 23,
+};
+static const unsigned int scifb3_clk_mux[] = {
+ SCIFB3_SCK_23_MARK,
+};
+static const unsigned int scifb3_ctrl_pins[] = {
+ /* SCIFB3_RTS, SCIFB3_CTS */
+ 19, 20,
+};
+static const unsigned int scifb3_ctrl_mux[] = {
+ SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
+};
+static const unsigned int scifb3_data_b_pins[] = {
+ /* SCIFB3_RXD, SCIFB3_TXD */
+ 120, 121,
+};
+static const unsigned int scifb3_data_b_mux[] = {
+ SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
+};
+static const unsigned int scifb3_clk_b_pins[] = {
+ /* SCIFB3_SCK */
+ 40,
+};
+static const unsigned int scifb3_clk_b_mux[] = {
+ SCIFB3_SCK_40_MARK,
+};
+static const unsigned int scifb3_ctrl_b_pins[] = {
+ /* SCIFB3_RTS, SCIFB3_CTS */
+ 38, 39,
+};
+static const unsigned int scifb3_ctrl_b_mux[] = {
+ SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(irqc_irq0),
+ SH_PFC_PIN_GROUP(irqc_irq1),
+ SH_PFC_PIN_GROUP(irqc_irq2),
+ SH_PFC_PIN_GROUP(irqc_irq3),
+ SH_PFC_PIN_GROUP(irqc_irq4),
+ SH_PFC_PIN_GROUP(irqc_irq5),
+ SH_PFC_PIN_GROUP(irqc_irq6),
+ SH_PFC_PIN_GROUP(irqc_irq7),
+ SH_PFC_PIN_GROUP(irqc_irq8),
+ SH_PFC_PIN_GROUP(irqc_irq9),
+ SH_PFC_PIN_GROUP(irqc_irq10),
+ SH_PFC_PIN_GROUP(irqc_irq11),
+ SH_PFC_PIN_GROUP(irqc_irq12),
+ SH_PFC_PIN_GROUP(irqc_irq13),
+ SH_PFC_PIN_GROUP(irqc_irq14),
+ SH_PFC_PIN_GROUP(irqc_irq15),
+ SH_PFC_PIN_GROUP(irqc_irq16),
+ SH_PFC_PIN_GROUP(irqc_irq17),
+ SH_PFC_PIN_GROUP(irqc_irq18),
+ SH_PFC_PIN_GROUP(irqc_irq19),
+ SH_PFC_PIN_GROUP(irqc_irq20),
+ SH_PFC_PIN_GROUP(irqc_irq21),
+ SH_PFC_PIN_GROUP(irqc_irq22),
+ SH_PFC_PIN_GROUP(irqc_irq23),
+ SH_PFC_PIN_GROUP(irqc_irq24),
+ SH_PFC_PIN_GROUP(irqc_irq25),
+ SH_PFC_PIN_GROUP(irqc_irq26),
+ SH_PFC_PIN_GROUP(irqc_irq27),
+ SH_PFC_PIN_GROUP(irqc_irq28),
+ SH_PFC_PIN_GROUP(irqc_irq29),
+ SH_PFC_PIN_GROUP(irqc_irq30),
+ SH_PFC_PIN_GROUP(irqc_irq31),
+ SH_PFC_PIN_GROUP(irqc_irq32),
+ SH_PFC_PIN_GROUP(irqc_irq33),
+ SH_PFC_PIN_GROUP(irqc_irq34),
+ SH_PFC_PIN_GROUP(irqc_irq35),
+ SH_PFC_PIN_GROUP(irqc_irq36),
+ SH_PFC_PIN_GROUP(irqc_irq37),
+ SH_PFC_PIN_GROUP(irqc_irq38),
+ SH_PFC_PIN_GROUP(irqc_irq39),
+ SH_PFC_PIN_GROUP(irqc_irq40),
+ SH_PFC_PIN_GROUP(irqc_irq41),
+ SH_PFC_PIN_GROUP(irqc_irq42),
+ SH_PFC_PIN_GROUP(irqc_irq43),
+ SH_PFC_PIN_GROUP(irqc_irq44),
+ SH_PFC_PIN_GROUP(irqc_irq45),
+ SH_PFC_PIN_GROUP(irqc_irq46),
+ SH_PFC_PIN_GROUP(irqc_irq47),
+ SH_PFC_PIN_GROUP(irqc_irq48),
+ SH_PFC_PIN_GROUP(irqc_irq49),
+ SH_PFC_PIN_GROUP(irqc_irq50),
+ SH_PFC_PIN_GROUP(irqc_irq51),
+ SH_PFC_PIN_GROUP(irqc_irq52),
+ SH_PFC_PIN_GROUP(irqc_irq53),
+ SH_PFC_PIN_GROUP(irqc_irq54),
+ SH_PFC_PIN_GROUP(irqc_irq55),
+ SH_PFC_PIN_GROUP(irqc_irq56),
+ SH_PFC_PIN_GROUP(irqc_irq57),
+ SH_PFC_PIN_GROUP(scifa0_data),
+ SH_PFC_PIN_GROUP(scifa0_clk),
+ SH_PFC_PIN_GROUP(scifa0_ctrl),
+ SH_PFC_PIN_GROUP(scifa1_data),
+ SH_PFC_PIN_GROUP(scifa1_clk),
+ SH_PFC_PIN_GROUP(scifa1_ctrl),
+ SH_PFC_PIN_GROUP(scifb0_data),
+ SH_PFC_PIN_GROUP(scifb0_clk),
+ SH_PFC_PIN_GROUP(scifb0_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data),
+ SH_PFC_PIN_GROUP(scifb1_clk),
+ SH_PFC_PIN_GROUP(scifb1_ctrl),
+ SH_PFC_PIN_GROUP(scifb1_data_b),
+ SH_PFC_PIN_GROUP(scifb1_clk_b),
+ SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb2_data),
+ SH_PFC_PIN_GROUP(scifb2_clk),
+ SH_PFC_PIN_GROUP(scifb2_ctrl),
+ SH_PFC_PIN_GROUP(scifb2_data_b),
+ SH_PFC_PIN_GROUP(scifb2_clk_b),
+ SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+ SH_PFC_PIN_GROUP(scifb3_data),
+ SH_PFC_PIN_GROUP(scifb3_clk),
+ SH_PFC_PIN_GROUP(scifb3_ctrl),
+ SH_PFC_PIN_GROUP(scifb3_data_b),
+ SH_PFC_PIN_GROUP(scifb3_clk_b),
+ SH_PFC_PIN_GROUP(scifb3_ctrl_b),
+};
+
+static const char * const irqc_groups[] = {
+ "irqc_irq0",
+ "irqc_irq1",
+ "irqc_irq2",
+ "irqc_irq3",
+ "irqc_irq4",
+ "irqc_irq5",
+ "irqc_irq6",
+ "irqc_irq7",
+ "irqc_irq8",
+ "irqc_irq9",
+ "irqc_irq10",
+ "irqc_irq11",
+ "irqc_irq12",
+ "irqc_irq13",
+ "irqc_irq14",
+ "irqc_irq15",
+ "irqc_irq16",
+ "irqc_irq17",
+ "irqc_irq18",
+ "irqc_irq19",
+ "irqc_irq20",
+ "irqc_irq21",
+ "irqc_irq22",
+ "irqc_irq23",
+ "irqc_irq24",
+ "irqc_irq25",
+ "irqc_irq26",
+ "irqc_irq27",
+ "irqc_irq28",
+ "irqc_irq29",
+ "irqc_irq30",
+ "irqc_irq31",
+ "irqc_irq32",
+ "irqc_irq33",
+ "irqc_irq34",
+ "irqc_irq35",
+ "irqc_irq36",
+ "irqc_irq37",
+ "irqc_irq38",
+ "irqc_irq39",
+ "irqc_irq40",
+ "irqc_irq41",
+ "irqc_irq42",
+ "irqc_irq43",
+ "irqc_irq44",
+ "irqc_irq45",
+ "irqc_irq46",
+ "irqc_irq47",
+ "irqc_irq48",
+ "irqc_irq49",
+ "irqc_irq50",
+ "irqc_irq51",
+ "irqc_irq52",
+ "irqc_irq53",
+ "irqc_irq54",
+ "irqc_irq55",
+ "irqc_irq56",
+ "irqc_irq57",
+};
+
+static const char * const scifa0_groups[] = {
+ "scifa0_data",
+ "scifa0_clk",
+ "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+ "scifa1_data",
+ "scifa1_clk",
+ "scifa1_ctrl",
+};
+
+static const char * const scifb0_groups[] = {
+ "scifb0_data",
+ "scifb0_clk",
+ "scifb0_ctrl",
+};
+
+static const char * const scifb1_groups[] = {
+ "scifb1_data",
+ "scifb1_clk",
+ "scifb1_ctrl",
+ "scifb1_data_b",
+ "scifb1_clk_b",
+ "scifb1_ctrl_b",
+};
+
+static const char * const scifb2_groups[] = {
+ "scifb2_data",
+ "scifb2_clk",
+ "scifb2_ctrl",
+ "scifb2_data_b",
+ "scifb2_clk_b",
+ "scifb2_ctrl_b",
+};
+
+static const char * const scifb3_groups[] = {
+ "scifb3_data",
+ "scifb3_clk",
+ "scifb3_ctrl",
+ "scifb3_data_b",
+ "scifb3_clk_b",
+ "scifb3_ctrl_b",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(irqc),
+ SH_PFC_FUNCTION(scifa0),
+ SH_PFC_FUNCTION(scifa1),
+ SH_PFC_FUNCTION(scifb0),
+ SH_PFC_FUNCTION(scifb1),
+ SH_PFC_FUNCTION(scifb2),
+ SH_PFC_FUNCTION(scifb3),
+};
+
+#undef PORTCR
+#define PORTCR(nr, reg) \
+ { \
+ PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
+ _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
+ PORT##nr##_FN0, PORT##nr##_FN1, \
+ PORT##nr##_FN2, PORT##nr##_FN3, \
+ PORT##nr##_FN4, PORT##nr##_FN5, \
+ PORT##nr##_FN6, PORT##nr##_FN7 } \
+ }
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
+ PORTCR(0, 0xe6050000),
+ PORTCR(1, 0xe6050001),
+ PORTCR(2, 0xe6050002),
+ PORTCR(3, 0xe6050003),
+ PORTCR(4, 0xe6050004),
+ PORTCR(5, 0xe6050005),
+ PORTCR(6, 0xe6050006),
+ PORTCR(7, 0xe6050007),
+ PORTCR(8, 0xe6050008),
+ PORTCR(9, 0xe6050009),
+ PORTCR(10, 0xe605000A),
+ PORTCR(11, 0xe605000B),
+ PORTCR(12, 0xe605000C),
+ PORTCR(13, 0xe605000D),
+ PORTCR(14, 0xe605000E),
+ PORTCR(15, 0xe605000F),
+ PORTCR(16, 0xe6050010),
+ PORTCR(17, 0xe6050011),
+ PORTCR(18, 0xe6050012),
+ PORTCR(19, 0xe6050013),
+ PORTCR(20, 0xe6050014),
+ PORTCR(21, 0xe6050015),
+ PORTCR(22, 0xe6050016),
+ PORTCR(23, 0xe6050017),
+ PORTCR(24, 0xe6050018),
+ PORTCR(25, 0xe6050019),
+ PORTCR(26, 0xe605001A),
+ PORTCR(27, 0xe605001B),
+ PORTCR(28, 0xe605001C),
+ PORTCR(29, 0xe605001D),
+ PORTCR(30, 0xe605001E),
+ PORTCR(32, 0xe6051020),
+ PORTCR(33, 0xe6051021),
+ PORTCR(34, 0xe6051022),
+ PORTCR(35, 0xe6051023),
+ PORTCR(36, 0xe6051024),
+ PORTCR(37, 0xe6051025),
+ PORTCR(38, 0xe6051026),
+ PORTCR(39, 0xe6051027),
+ PORTCR(40, 0xe6051028),
+ PORTCR(64, 0xe6050040),
+ PORTCR(65, 0xe6050041),
+ PORTCR(66, 0xe6050042),
+ PORTCR(67, 0xe6050043),
+ PORTCR(68, 0xe6050044),
+ PORTCR(69, 0xe6050045),
+ PORTCR(70, 0xe6050046),
+ PORTCR(71, 0xe6050047),
+ PORTCR(72, 0xe6050048),
+ PORTCR(73, 0xe6050049),
+ PORTCR(74, 0xe605004A),
+ PORTCR(75, 0xe605004B),
+ PORTCR(76, 0xe605004C),
+ PORTCR(77, 0xe605004D),
+ PORTCR(78, 0xe605004E),
+ PORTCR(79, 0xe605004F),
+ PORTCR(80, 0xe6050050),
+ PORTCR(81, 0xe6050051),
+ PORTCR(82, 0xe6050052),
+ PORTCR(83, 0xe6050053),
+ PORTCR(84, 0xe6050054),
+ PORTCR(85, 0xe6050055),
+ PORTCR(96, 0xe6051060),
+ PORTCR(97, 0xe6051061),
+ PORTCR(98, 0xe6051062),
+ PORTCR(99, 0xe6051063),
+ PORTCR(100, 0xe6051064),
+ PORTCR(101, 0xe6051065),
+ PORTCR(102, 0xe6051066),
+ PORTCR(103, 0xe6051067),
+ PORTCR(104, 0xe6051068),
+ PORTCR(105, 0xe6051069),
+ PORTCR(106, 0xe605106A),
+ PORTCR(107, 0xe605106B),
+ PORTCR(108, 0xe605106C),
+ PORTCR(109, 0xe605106D),
+ PORTCR(110, 0xe605106E),
+ PORTCR(111, 0xe605106F),
+ PORTCR(112, 0xe6051070),
+ PORTCR(113, 0xe6051071),
+ PORTCR(114, 0xe6051072),
+ PORTCR(115, 0xe6051073),
+ PORTCR(116, 0xe6051074),
+ PORTCR(117, 0xe6051075),
+ PORTCR(118, 0xe6051076),
+ PORTCR(119, 0xe6051077),
+ PORTCR(120, 0xe6051078),
+ PORTCR(121, 0xe6051079),
+ PORTCR(122, 0xe605107A),
+ PORTCR(123, 0xe605107B),
+ PORTCR(124, 0xe605107C),
+ PORTCR(125, 0xe605107D),
+ PORTCR(126, 0xe605107E),
+ PORTCR(128, 0xe6051080),
+ PORTCR(129, 0xe6051081),
+ PORTCR(130, 0xe6051082),
+ PORTCR(131, 0xe6051083),
+ PORTCR(132, 0xe6051084),
+ PORTCR(133, 0xe6051085),
+ PORTCR(134, 0xe6051086),
+ PORTCR(160, 0xe60520A0),
+ PORTCR(161, 0xe60520A1),
+ PORTCR(162, 0xe60520A2),
+ PORTCR(163, 0xe60520A3),
+ PORTCR(164, 0xe60520A4),
+ PORTCR(165, 0xe60520A5),
+ PORTCR(166, 0xe60520A6),
+ PORTCR(167, 0xe60520A7),
+ PORTCR(168, 0xe60520A8),
+ PORTCR(169, 0xe60520A9),
+ PORTCR(170, 0xe60520AA),
+ PORTCR(171, 0xe60520AB),
+ PORTCR(172, 0xe60520AC),
+ PORTCR(173, 0xe60520AD),
+ PORTCR(174, 0xe60520AE),
+ PORTCR(175, 0xe60520AF),
+ PORTCR(176, 0xe60520B0),
+ PORTCR(177, 0xe60520B1),
+ PORTCR(178, 0xe60520B2),
+ PORTCR(192, 0xe60520C0),
+ PORTCR(193, 0xe60520C1),
+ PORTCR(194, 0xe60520C2),
+ PORTCR(195, 0xe60520C3),
+ PORTCR(196, 0xe60520C4),
+ PORTCR(197, 0xe60520C5),
+ PORTCR(198, 0xe60520C6),
+ PORTCR(199, 0xe60520C7),
+ PORTCR(200, 0xe60520C8),
+ PORTCR(201, 0xe60520C9),
+ PORTCR(202, 0xe60520CA),
+ PORTCR(203, 0xe60520CB),
+ PORTCR(204, 0xe60520CC),
+ PORTCR(205, 0xe60520CD),
+ PORTCR(206, 0xe60520CE),
+ PORTCR(207, 0xe60520CF),
+ PORTCR(208, 0xe60520D0),
+ PORTCR(209, 0xe60520D1),
+ PORTCR(210, 0xe60520D2),
+ PORTCR(211, 0xe60520D3),
+ PORTCR(212, 0xe60520D4),
+ PORTCR(213, 0xe60520D5),
+ PORTCR(214, 0xe60520D6),
+ PORTCR(215, 0xe60520D7),
+ PORTCR(216, 0xe60520D8),
+ PORTCR(217, 0xe60520D9),
+ PORTCR(218, 0xe60520DA),
+ PORTCR(219, 0xe60520DB),
+ PORTCR(220, 0xe60520DC),
+ PORTCR(221, 0xe60520DD),
+ PORTCR(222, 0xe60520DE),
+ PORTCR(224, 0xe60520E0),
+ PORTCR(225, 0xe60520E1),
+ PORTCR(226, 0xe60520E2),
+ PORTCR(227, 0xe60520E3),
+ PORTCR(228, 0xe60520E4),
+ PORTCR(229, 0xe60520E5),
+ PORTCR(230, 0xe60520e6),
+ PORTCR(231, 0xe60520E7),
+ PORTCR(232, 0xe60520E8),
+ PORTCR(233, 0xe60520E9),
+ PORTCR(234, 0xe60520EA),
+ PORTCR(235, 0xe60520EB),
+ PORTCR(236, 0xe60520EC),
+ PORTCR(237, 0xe60520ED),
+ PORTCR(238, 0xe60520EE),
+ PORTCR(239, 0xe60520EF),
+ PORTCR(240, 0xe60520F0),
+ PORTCR(241, 0xe60520F1),
+ PORTCR(242, 0xe60520F2),
+ PORTCR(243, 0xe60520F3),
+ PORTCR(244, 0xe60520F4),
+ PORTCR(245, 0xe60520F5),
+ PORTCR(246, 0xe60520F6),
+ PORTCR(247, 0xe60520F7),
+ PORTCR(248, 0xe60520F8),
+ PORTCR(249, 0xe60520F9),
+ PORTCR(250, 0xe60520FA),
+ PORTCR(256, 0xe6052100),
+ PORTCR(257, 0xe6052101),
+ PORTCR(258, 0xe6052102),
+ PORTCR(259, 0xe6052103),
+ PORTCR(260, 0xe6052104),
+ PORTCR(261, 0xe6052105),
+ PORTCR(262, 0xe6052106),
+ PORTCR(263, 0xe6052107),
+ PORTCR(264, 0xe6052108),
+ PORTCR(265, 0xe6052109),
+ PORTCR(266, 0xe605210A),
+ PORTCR(267, 0xe605210B),
+ PORTCR(268, 0xe605210C),
+ PORTCR(269, 0xe605210D),
+ PORTCR(270, 0xe605210E),
+ PORTCR(271, 0xe605210F),
+ PORTCR(272, 0xe6052110),
+ PORTCR(273, 0xe6052111),
+ PORTCR(274, 0xe6052112),
+ PORTCR(275, 0xe6052113),
+ PORTCR(276, 0xe6052114),
+ PORTCR(277, 0xe6052115),
+ PORTCR(278, 0xe6052116),
+ PORTCR(279, 0xe6052117),
+ PORTCR(280, 0xe6052118),
+ PORTCR(281, 0xe6052119),
+ PORTCR(282, 0xe605211A),
+ PORTCR(283, 0xe605211B),
+ PORTCR(288, 0xe6053120),
+ PORTCR(289, 0xe6053121),
+ PORTCR(290, 0xe6053122),
+ PORTCR(291, 0xe6053123),
+ PORTCR(292, 0xe6053124),
+ PORTCR(293, 0xe6053125),
+ PORTCR(294, 0xe6053126),
+ PORTCR(295, 0xe6053127),
+ PORTCR(296, 0xe6053128),
+ PORTCR(297, 0xe6053129),
+ PORTCR(298, 0xe605312A),
+ PORTCR(299, 0xe605312B),
+ PORTCR(300, 0xe605312C),
+ PORTCR(301, 0xe605312D),
+ PORTCR(302, 0xe605312E),
+ PORTCR(303, 0xe605312F),
+ PORTCR(304, 0xe6053130),
+ PORTCR(305, 0xe6053131),
+ PORTCR(306, 0xe6053132),
+ PORTCR(307, 0xe6053133),
+ PORTCR(308, 0xe6053134),
+ PORTCR(320, 0xe6053140),
+ PORTCR(321, 0xe6053141),
+ PORTCR(322, 0xe6053142),
+ PORTCR(323, 0xe6053143),
+ PORTCR(324, 0xe6053144),
+ PORTCR(325, 0xe6053145),
+ PORTCR(326, 0xe6053146),
+ PORTCR(327, 0xe6053147),
+ PORTCR(328, 0xe6053148),
+ PORTCR(329, 0xe6053149),
+
+ { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
+ MSEL1CR_31_0, MSEL1CR_31_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL1CR_27_0, MSEL1CR_27_1,
+ 0, 0,
+ MSEL1CR_25_0, MSEL1CR_25_1,
+ MSEL1CR_24_0, MSEL1CR_24_1,
+ 0, 0,
+ MSEL1CR_22_0, MSEL1CR_22_1,
+ MSEL1CR_21_0, MSEL1CR_21_1,
+ MSEL1CR_20_0, MSEL1CR_20_1,
+ MSEL1CR_19_0, MSEL1CR_19_1,
+ MSEL1CR_18_0, MSEL1CR_18_1,
+ MSEL1CR_17_0, MSEL1CR_17_1,
+ MSEL1CR_16_0, MSEL1CR_16_1,
+ MSEL1CR_15_0, MSEL1CR_15_1,
+ MSEL1CR_14_0, MSEL1CR_14_1,
+ MSEL1CR_13_0, MSEL1CR_13_1,
+ MSEL1CR_12_0, MSEL1CR_12_1,
+ MSEL1CR_11_0, MSEL1CR_11_1,
+ MSEL1CR_10_0, MSEL1CR_10_1,
+ MSEL1CR_09_0, MSEL1CR_09_1,
+ MSEL1CR_08_0, MSEL1CR_08_1,
+ MSEL1CR_07_0, MSEL1CR_07_1,
+ MSEL1CR_06_0, MSEL1CR_06_1,
+ MSEL1CR_05_0, MSEL1CR_05_1,
+ MSEL1CR_04_0, MSEL1CR_04_1,
+ MSEL1CR_03_0, MSEL1CR_03_1,
+ MSEL1CR_02_0, MSEL1CR_02_1,
+ MSEL1CR_01_0, MSEL1CR_01_1,
+ MSEL1CR_00_0, MSEL1CR_00_1,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
+ MSEL3CR_31_0, MSEL3CR_31_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_28_0, MSEL3CR_28_1,
+ MSEL3CR_27_0, MSEL3CR_27_1,
+ MSEL3CR_26_0, MSEL3CR_26_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_23_0, MSEL3CR_23_1,
+ MSEL3CR_22_0, MSEL3CR_22_1,
+ MSEL3CR_21_0, MSEL3CR_21_1,
+ MSEL3CR_20_0, MSEL3CR_20_1,
+ MSEL3CR_19_0, MSEL3CR_19_1,
+ MSEL3CR_18_0, MSEL3CR_18_1,
+ MSEL3CR_17_0, MSEL3CR_17_1,
+ MSEL3CR_16_0, MSEL3CR_16_1,
+ MSEL3CR_15_0, MSEL3CR_15_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_12_0, MSEL3CR_12_1,
+ MSEL3CR_11_0, MSEL3CR_11_1,
+ MSEL3CR_10_0, MSEL3CR_10_1,
+ MSEL3CR_09_0, MSEL3CR_09_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_06_0, MSEL3CR_06_1,
+ 0, 0,
+ 0, 0,
+ MSEL3CR_03_0, MSEL3CR_03_1,
+ 0, 0,
+ MSEL3CR_01_0, MSEL3CR_01_1,
+ MSEL3CR_00_0, MSEL3CR_00_1,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
+ 0, 0,
+ MSEL4CR_30_0, MSEL4CR_30_1,
+ MSEL4CR_29_0, MSEL4CR_29_1,
+ MSEL4CR_28_0, MSEL4CR_28_1,
+ MSEL4CR_27_0, MSEL4CR_27_1,
+ MSEL4CR_26_0, MSEL4CR_26_1,
+ MSEL4CR_25_0, MSEL4CR_25_1,
+ MSEL4CR_24_0, MSEL4CR_24_1,
+ MSEL4CR_23_0, MSEL4CR_23_1,
+ MSEL4CR_22_0, MSEL4CR_22_1,
+ MSEL4CR_21_0, MSEL4CR_21_1,
+ MSEL4CR_20_0, MSEL4CR_20_1,
+ MSEL4CR_19_0, MSEL4CR_19_1,
+ MSEL4CR_18_0, MSEL4CR_18_1,
+ MSEL4CR_17_0, MSEL4CR_17_1,
+ MSEL4CR_16_0, MSEL4CR_16_1,
+ MSEL4CR_15_0, MSEL4CR_15_1,
+ MSEL4CR_14_0, MSEL4CR_14_1,
+ MSEL4CR_13_0, MSEL4CR_13_1,
+ MSEL4CR_12_0, MSEL4CR_12_1,
+ MSEL4CR_11_0, MSEL4CR_11_1,
+ MSEL4CR_10_0, MSEL4CR_10_1,
+ MSEL4CR_09_0, MSEL4CR_09_1,
+ 0, 0,
+ MSEL4CR_07_0, MSEL4CR_07_1,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_04_0, MSEL4CR_04_1,
+ 0, 0,
+ 0, 0,
+ MSEL4CR_01_0, MSEL4CR_01_1,
+ 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
+ MSEL5CR_31_0, MSEL5CR_31_1,
+ MSEL5CR_30_0, MSEL5CR_30_1,
+ MSEL5CR_29_0, MSEL5CR_29_1,
+ MSEL5CR_28_0, MSEL5CR_28_1,
+ MSEL5CR_27_0, MSEL5CR_27_1,
+ MSEL5CR_26_0, MSEL5CR_26_1,
+ MSEL5CR_25_0, MSEL5CR_25_1,
+ MSEL5CR_24_0, MSEL5CR_24_1,
+ MSEL5CR_23_0, MSEL5CR_23_1,
+ MSEL5CR_22_0, MSEL5CR_22_1,
+ MSEL5CR_21_0, MSEL5CR_21_1,
+ MSEL5CR_20_0, MSEL5CR_20_1,
+ MSEL5CR_19_0, MSEL5CR_19_1,
+ MSEL5CR_18_0, MSEL5CR_18_1,
+ MSEL5CR_17_0, MSEL5CR_17_1,
+ MSEL5CR_16_0, MSEL5CR_16_1,
+ MSEL5CR_15_0, MSEL5CR_15_1,
+ MSEL5CR_14_0, MSEL5CR_14_1,
+ MSEL5CR_13_0, MSEL5CR_13_1,
+ MSEL5CR_12_0, MSEL5CR_12_1,
+ MSEL5CR_11_0, MSEL5CR_11_1,
+ MSEL5CR_10_0, MSEL5CR_10_1,
+ MSEL5CR_09_0, MSEL5CR_09_1,
+ MSEL5CR_08_0, MSEL5CR_08_1,
+ MSEL5CR_07_0, MSEL5CR_07_1,
+ MSEL5CR_06_0, MSEL5CR_06_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ }
+ },
+ { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL8CR_16_0, MSEL8CR_16_1,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ 0, 0,
+ MSEL8CR_01_0, MSEL8CR_01_1,
+ MSEL8CR_00_0, MSEL8CR_00_1,
+ }
+ },
+ { },
+};
+
+static const struct pinmux_data_reg pinmux_data_regs[] = {
+
+ { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
+ 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
+ PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
+ PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
+ PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
+ PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
+ PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
+ PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
+ PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, PORT40_DATA,
+ PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
+ PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, PORT85_DATA, PORT84_DATA,
+ PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
+ PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
+ PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
+ PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
+ PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
+ 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
+ PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
+ PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
+ PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
+ PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
+ PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
+ PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
+ PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
+ PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
+ PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
+ PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
+ PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
+ PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
+ 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
+ PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
+ PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
+ PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
+ PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
+ PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
+ PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
+ PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
+ 0, 0, 0, 0,
+ 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
+ PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
+ PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
+ PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
+ PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
+ PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
+ PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
+ 0, 0, 0, 0,
+ PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
+ PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
+ PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
+ PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
+ PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
+ PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
+ PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, PORT308_DATA,
+ PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
+ PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
+ PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
+ PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
+ PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
+ }
+ },
+ { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ 0, 0, PORT329_DATA, PORT328_DATA,
+ PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
+ PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
+ }
+ },
+ { },
+};
+
+static const struct pinmux_irq pinmux_irqs[] = {
+ PINMUX_IRQ(irq_pin(0), 0),
+ PINMUX_IRQ(irq_pin(1), 1),
+ PINMUX_IRQ(irq_pin(2), 2),
+ PINMUX_IRQ(irq_pin(3), 3),
+ PINMUX_IRQ(irq_pin(4), 4),
+ PINMUX_IRQ(irq_pin(5), 5),
+ PINMUX_IRQ(irq_pin(6), 6),
+ PINMUX_IRQ(irq_pin(7), 7),
+ PINMUX_IRQ(irq_pin(8), 8),
+ PINMUX_IRQ(irq_pin(9), 9),
+ PINMUX_IRQ(irq_pin(10), 10),
+ PINMUX_IRQ(irq_pin(11), 11),
+ PINMUX_IRQ(irq_pin(12), 12),
+ PINMUX_IRQ(irq_pin(13), 13),
+ PINMUX_IRQ(irq_pin(14), 14),
+ PINMUX_IRQ(irq_pin(15), 15),
+ PINMUX_IRQ(irq_pin(16), 320),
+ PINMUX_IRQ(irq_pin(17), 321),
+ PINMUX_IRQ(irq_pin(18), 85),
+ PINMUX_IRQ(irq_pin(19), 84),
+ PINMUX_IRQ(irq_pin(20), 160),
+ PINMUX_IRQ(irq_pin(21), 161),
+ PINMUX_IRQ(irq_pin(22), 162),
+ PINMUX_IRQ(irq_pin(23), 163),
+ PINMUX_IRQ(irq_pin(24), 175),
+ PINMUX_IRQ(irq_pin(25), 176),
+ PINMUX_IRQ(irq_pin(26), 177),
+ PINMUX_IRQ(irq_pin(27), 178),
+ PINMUX_IRQ(irq_pin(28), 322),
+ PINMUX_IRQ(irq_pin(29), 323),
+ PINMUX_IRQ(irq_pin(30), 324),
+ PINMUX_IRQ(irq_pin(31), 192),
+ PINMUX_IRQ(irq_pin(32), 193),
+ PINMUX_IRQ(irq_pin(33), 194),
+ PINMUX_IRQ(irq_pin(34), 195),
+ PINMUX_IRQ(irq_pin(35), 196),
+ PINMUX_IRQ(irq_pin(36), 197),
+ PINMUX_IRQ(irq_pin(37), 198),
+ PINMUX_IRQ(irq_pin(38), 199),
+ PINMUX_IRQ(irq_pin(39), 200),
+ PINMUX_IRQ(irq_pin(40), 66),
+ PINMUX_IRQ(irq_pin(41), 102),
+ PINMUX_IRQ(irq_pin(42), 103),
+ PINMUX_IRQ(irq_pin(43), 109),
+ PINMUX_IRQ(irq_pin(44), 110),
+ PINMUX_IRQ(irq_pin(45), 111),
+ PINMUX_IRQ(irq_pin(46), 112),
+ PINMUX_IRQ(irq_pin(47), 113),
+ PINMUX_IRQ(irq_pin(48), 114),
+ PINMUX_IRQ(irq_pin(49), 115),
+ PINMUX_IRQ(irq_pin(50), 301),
+ PINMUX_IRQ(irq_pin(51), 290),
+ PINMUX_IRQ(irq_pin(52), 296),
+ PINMUX_IRQ(irq_pin(53), 325),
+ PINMUX_IRQ(irq_pin(54), 326),
+ PINMUX_IRQ(irq_pin(55), 327),
+ PINMUX_IRQ(irq_pin(56), 328),
+ PINMUX_IRQ(irq_pin(57), 329),
+};
+
+#define PORTCR_PULMD_OFF (0 << 6)
+#define PORTCR_PULMD_DOWN (2 << 6)
+#define PORTCR_PULMD_UP (3 << 6)
+#define PORTCR_PULMD_MASK (3 << 6)
+
+static const unsigned int r8a73a4_portcr_offsets[] = {
+ 0x00000000, 0x00001000, 0x00000000, 0x00001000,
+ 0x00001000, 0x00002000, 0x00002000, 0x00002000,
+ 0x00002000, 0x00003000, 0x00003000,
+};
+
+static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
+ unsigned int pin)
+{
+ void __iomem *addr;
+
+ addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+
+ switch (ioread8(addr) & PORTCR_PULMD_MASK) {
+ case PORTCR_PULMD_UP:
+ return PIN_CONFIG_BIAS_PULL_UP;
+ case PORTCR_PULMD_DOWN:
+ return PIN_CONFIG_BIAS_PULL_DOWN;
+ case PORTCR_PULMD_OFF:
+ default:
+ return PIN_CONFIG_BIAS_DISABLE;
+ }
+}
+
+static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+ unsigned int bias)
+{
+ void __iomem *addr;
+ u32 value;
+
+ addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
+ value = ioread8(addr) & ~PORTCR_PULMD_MASK;
+
+ switch (bias) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ value |= PORTCR_PULMD_UP;
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ value |= PORTCR_PULMD_DOWN;
+ break;
+ }
+
+ iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
+ .get_bias = r8a73a4_pinmux_get_bias,
+ .set_bias = r8a73a4_pinmux_set_bias,
+};
+
+const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
+ .name = "r8a73a4_pfc",
+ .ops = &r8a73a4_pinmux_ops,
+
+ .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
+ .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
+ .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+
+ .ranges = pinmux_ranges,
+ .nr_ranges = ARRAY_SIZE(pinmux_ranges),
+
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .cfg_regs = pinmux_config_regs,
+ .data_regs = pinmux_data_regs,
+
+ .gpio_data = pinmux_data,
+ .gpio_data_size = ARRAY_SIZE(pinmux_data),
+
+ .gpio_irq = pinmux_irqs,
+ .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 2b528280e3c1..bbd87d29bfd0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
/* I/O and Pull U/D */
@@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
};
-static struct pinmux_gpio pinmux_gpios[] = {
-
- /* PORT */
+static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
+};
+
+/* - LCD0 ------------------------------------------------------------------- */
+static const unsigned int lcd0_data8_pins[] = {
+ /* D[0:7] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+};
+static const unsigned int lcd0_data8_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+};
+static const unsigned int lcd0_data9_pins[] = {
+ /* D[0:8] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50,
+};
+static const unsigned int lcd0_data9_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK,
+};
+static const unsigned int lcd0_data12_pins[] = {
+ /* D[0:11] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47,
+};
+static const unsigned int lcd0_data12_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+};
+static const unsigned int lcd0_data16_pins[] = {
+ /* D[0:15] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+};
+static const unsigned int lcd0_data16_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+};
+static const unsigned int lcd0_data18_pins[] = {
+ /* D[0:17] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41,
+};
+static const unsigned int lcd0_data18_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK,
+};
+static const unsigned int lcd0_data24_0_pins[] = {
+ /* D[0:23] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 40, 4, 3, 2, 0, 1,
+};
+static const unsigned int lcd0_data24_0_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
+ LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
+ LCD0_D23_PORT1_MARK,
+};
+static const unsigned int lcd0_data24_1_pins[] = {
+ /* D[0:23] */
+ 58, 57, 56, 55, 54, 53, 52, 51,
+ 50, 49, 48, 47, 46, 45, 44, 43,
+ 42, 41, 163, 162, 161, 158, 160, 159,
+};
+static const unsigned int lcd0_data24_1_mux[] = {
+ LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
+ LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
+ LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
+ LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
+ LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
+ LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
+};
+static const unsigned int lcd0_display_pins[] = {
+ /* DON, VCPWC, VEPWC */
+ 61, 59, 60,
+};
+static const unsigned int lcd0_display_mux[] = {
+ LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
+};
+static const unsigned int lcd0_lclk_0_pins[] = {
+ /* LCLK */
+ 102,
+};
+static const unsigned int lcd0_lclk_0_mux[] = {
+ LCD0_LCLK_PORT102_MARK,
+};
+static const unsigned int lcd0_lclk_1_pins[] = {
+ /* LCLK */
+ 165,
+};
+static const unsigned int lcd0_lclk_1_mux[] = {
+ LCD0_LCLK_PORT165_MARK,
+};
+static const unsigned int lcd0_sync_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 63, 64, 62, 65,
+};
+static const unsigned int lcd0_sync_mux[] = {
+ LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
+};
+static const unsigned int lcd0_sys_pins[] = {
+ /* CS, WR, RD, RS */
+ 64, 62, 164, 65,
+};
+static const unsigned int lcd0_sys_mux[] = {
+ LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
+};
+/* - LCD1 ------------------------------------------------------------------- */
+static const unsigned int lcd1_data8_pins[] = {
+ /* D[0:7] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+};
+static const unsigned int lcd1_data8_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+};
+static const unsigned int lcd1_data9_pins[] = {
+ /* D[0:8] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93,
+};
+static const unsigned int lcd1_data9_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK,
+};
+static const unsigned int lcd1_data12_pins[] = {
+ /* D[0:12] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201,
+};
+static const unsigned int lcd1_data12_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+};
+static const unsigned int lcd1_data16_pins[] = {
+ /* D[0:15] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+};
+static const unsigned int lcd1_data16_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+};
+static const unsigned int lcd1_data18_pins[] = {
+ /* D[0:17] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+ 194, 193,
+};
+static const unsigned int lcd1_data18_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK,
+};
+static const unsigned int lcd1_data24_pins[] = {
+ /* D[0:23] */
+ 4, 3, 2, 1, 0, 91, 92, 23,
+ 93, 94, 21, 201, 200, 199, 196, 195,
+ 194, 193, 198, 197, 75, 74, 15, 14,
+};
+static const unsigned int lcd1_data24_mux[] = {
+ LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
+ LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
+ LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
+ LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
+ LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
+ LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
+};
+static const unsigned int lcd1_display_pins[] = {
+ /* DON, VCPWC, VEPWC */
+ 100, 5, 6,
+};
+static const unsigned int lcd1_display_mux[] = {
+ LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
+};
+static const unsigned int lcd1_lclk_pins[] = {
+ /* LCLK */
+ 40,
+};
+static const unsigned int lcd1_lclk_mux[] = {
+ LCD1_LCLK_MARK,
+};
+static const unsigned int lcd1_sync_pins[] = {
+ /* VSYN, HSYN, DCK, DISP */
+ 98, 97, 99, 12,
+};
+static const unsigned int lcd1_sync_mux[] = {
+ LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
+};
+static const unsigned int lcd1_sys_pins[] = {
+ /* CS, WR, RD, RS */
+ 97, 99, 13, 12,
+};
+static const unsigned int lcd1_sys_mux[] = {
+ LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 68,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMC0_D0_PORT68_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 68, 69, 70, 71, 72, 73, 74, 75,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
+ MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 149,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMC1_D0_PORT149_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 149, 148, 147, 146,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
+ MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 104, 103,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 77,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHI0_D0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 77, 78, 79, 80,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 76, 82,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHI0_CMD_MARK, SDHI0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 81,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHI0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 83,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHI0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 68,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHI1_D0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 68, 69, 70, 71,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHI1_CMD_MARK, SDHI1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ 72,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SDHI1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ 73,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SDHI1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 205,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHI2_D0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 205, 206, 207, 208,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 204, 203,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHI2_CMD_MARK, SDHI2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_0_pins[] = {
+ /* CD */
+ 202,
+};
+static const unsigned int sdhi2_cd_0_mux[] = {
+ SDHI2_CD_PORT202_MARK,
+};
+static const unsigned int sdhi2_wp_0_pins[] = {
+ /* WP */
+ 177,
+};
+static const unsigned int sdhi2_wp_0_mux[] = {
+ SDHI2_WP_PORT177_MARK,
+};
+static const unsigned int sdhi2_cd_1_pins[] = {
+ /* CD */
+ 24,
+};
+static const unsigned int sdhi2_cd_1_mux[] = {
+ SDHI2_CD_PORT24_MARK,
+};
+static const unsigned int sdhi2_wp_1_pins[] = {
+ /* WP */
+ 25,
+};
+static const unsigned int sdhi2_wp_1_mux[] = {
+ SDHI2_WP_PORT25_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(lcd0_data8),
+ SH_PFC_PIN_GROUP(lcd0_data9),
+ SH_PFC_PIN_GROUP(lcd0_data12),
+ SH_PFC_PIN_GROUP(lcd0_data16),
+ SH_PFC_PIN_GROUP(lcd0_data18),
+ SH_PFC_PIN_GROUP(lcd0_data24_0),
+ SH_PFC_PIN_GROUP(lcd0_data24_1),
+ SH_PFC_PIN_GROUP(lcd0_display),
+ SH_PFC_PIN_GROUP(lcd0_lclk_0),
+ SH_PFC_PIN_GROUP(lcd0_lclk_1),
+ SH_PFC_PIN_GROUP(lcd0_sync),
+ SH_PFC_PIN_GROUP(lcd0_sys),
+ SH_PFC_PIN_GROUP(lcd1_data8),
+ SH_PFC_PIN_GROUP(lcd1_data9),
+ SH_PFC_PIN_GROUP(lcd1_data12),
+ SH_PFC_PIN_GROUP(lcd1_data16),
+ SH_PFC_PIN_GROUP(lcd1_data18),
+ SH_PFC_PIN_GROUP(lcd1_data24),
+ SH_PFC_PIN_GROUP(lcd1_display),
+ SH_PFC_PIN_GROUP(lcd1_lclk),
+ SH_PFC_PIN_GROUP(lcd1_sync),
+ SH_PFC_PIN_GROUP(lcd1_sys),
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd_0),
+ SH_PFC_PIN_GROUP(sdhi2_wp_0),
+ SH_PFC_PIN_GROUP(sdhi2_cd_1),
+ SH_PFC_PIN_GROUP(sdhi2_wp_1),
+};
+
+static const char * const lcd0_groups[] = {
+ "lcd0_data8",
+ "lcd0_data9",
+ "lcd0_data12",
+ "lcd0_data16",
+ "lcd0_data18",
+ "lcd0_data24_0",
+ "lcd0_data24_1",
+ "lcd0_display",
+ "lcd0_lclk_0",
+ "lcd0_lclk_1",
+ "lcd0_sync",
+ "lcd0_sys",
+};
+
+static const char * const lcd1_groups[] = {
+ "lcd1_data8",
+ "lcd1_data9",
+ "lcd1_data12",
+ "lcd1_data16",
+ "lcd1_data18",
+ "lcd1_data24",
+ "lcd1_display",
+ "lcd1_lclk",
+ "lcd1_sync",
+ "lcd1_sys",
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd_0",
+ "sdhi2_wp_0",
+ "sdhi2_cd_1",
+ "sdhi2_wp_1",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(lcd0),
+ SH_PFC_FUNCTION(lcd1),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+};
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
GPIO_FN(IRQ1),
@@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SCIFB_RTS_PORT172),
GPIO_FN(SCIFB_CTS_PORT173),
- /* LCD0 */
- GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
- GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
- GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
- GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
- GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
- GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
- GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
- GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
- GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
- GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
- GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
-
- GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
- GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
- GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
- GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
-
- GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
- GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
- GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
- GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
-
- /* LCD1 */
- GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
- GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
- GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
- GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
- GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
- GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
- GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
- GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
- GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
- GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
- GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
- GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
-
/* RSPI */
GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
@@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
GPIO_FN(SIM_D_PORT199),
- /* SDHI0 */
- GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
- GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
- GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
-
- /* SDHI1 */
- GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
- GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
- GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
-
- /* SDHI2 */
- GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
- GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
-
- GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
- GPIO_FN(SDHI2_WP_PORT25),
-
- GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
- GPIO_FN(SDHI2_CD_PORT202),
-
/* MSIOF2 */
GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
GPIO_FN(MEMC_A0),
- /* MMC */
- GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
- GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
- GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
- GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
- GPIO_FN(MMC0_CLK_PORT66),
- GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
-
- GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
- GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
- GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
- GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
- GPIO_FN(MMC1_CLK_PORT103),
- GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
-
/* MSIOF0 */
GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
@@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(TRACEAUD_FROM_MEMC),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xe6050000), /* PORT0CR */
PORTCR(1, 0xe6050001), /* PORT1CR */
PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2544,7 +2993,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-static struct pinmux_irq pinmux_irqs[] = {
+static const struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
@@ -2579,11 +3028,8 @@ static struct pinmux_irq pinmux_irqs[] = {
PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
};
-struct sh_pfc_soc_info r8a7740_pinmux_info = {
+const struct sh_pfc_soc_info r8a7740_pinmux_info = {
.name = "r8a7740_pfc",
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN,
- PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN,
PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN,
PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN,
- PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN,
PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PORT0,
- .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 13feaa0c0eb7..62dcdcdec940 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,57 +19,77 @@
*/
#include <linux/kernel.h>
-#include <mach/r8a7779.h>
#include "sh_pfc.h"
-#define CPU_32_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_1(fn, pfx##31, sfx)
-
-#define CPU_32_PORT6(fn, pfx, sfx) \
- PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
- PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
- PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \
- PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
- PORT_1(fn, pfx##8, sfx)
-
-#define CPU_ALL_PORT(fn, pfx, sfx) \
- CPU_32_PORT(fn, pfx##_0_, sfx), \
- CPU_32_PORT(fn, pfx##_1_, sfx), \
- CPU_32_PORT(fn, pfx##_2_, sfx), \
- CPU_32_PORT(fn, pfx##_3_, sfx), \
- CPU_32_PORT(fn, pfx##_4_, sfx), \
- CPU_32_PORT(fn, pfx##_5_, sfx), \
- CPU_32_PORT6(fn, pfx##_6_, sfx)
-
-#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
-#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \
- GP##pfx##_IN, GP##pfx##_OUT)
-
-#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT
-#define _GP_INDT(pfx, sfx) GP##pfx##_DATA
-
-#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str)
-#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
-#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
-
-
-#define PORT_10_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
- PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
- PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
- PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
- PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
-
-#define CPU_32_PORT_REV(fn, pfx, sfx) \
- PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
- PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
- PORT_10_REV(fn, pfx, sfx)
-
-#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
-#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx) \
+ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
+ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
+ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
+ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
+ PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
+ PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
+ PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
+ PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
+ PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
+ PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
+ PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
+ PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
+ PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
+ PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
+ PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
+ PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_9(bank, fn, sfx) \
+ PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
+ PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
+ PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
+ PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
+ PORT_GP_1(bank, 8, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx) \
+ PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
+ PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
+ PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
+ PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
+ PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
+ PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
+ PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
+ PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
+ PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
+ PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
+ PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
+ PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
+ PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
+ PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
+ PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
+ PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx) \
+ PORT_GP_32(0, fn, sfx), \
+ PORT_GP_32(1, fn, sfx), \
+ PORT_GP_32(2, fn, sfx), \
+ PORT_GP_32(3, fn, sfx), \
+ PORT_GP_32(4, fn, sfx), \
+ PORT_GP_32(5, fn, sfx), \
+ PORT_GP_32_9(6, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx) \
+ [(bank * 32) + pin] = { \
+ .name = __stringify(_name), \
+ .enum_id = _name##_DATA, \
+ }
+
+#define _GP_DATA(bank, pin, name, sfx) \
+ PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -82,14 +102,6 @@ enum {
GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
PINMUX_DATA_END,
- PINMUX_INPUT_BEGIN,
- GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
- PINMUX_INPUT_END,
-
- PINMUX_OUTPUT_BEGIN,
- GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
- PINMUX_OUTPUT_END,
-
PINMUX_FUNCTION_BEGIN,
GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
@@ -371,7 +383,7 @@ enum {
FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
- FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
+ FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
@@ -447,7 +459,8 @@ enum {
A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
- USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
+ USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
+ SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
SCIF_CLK_MARK, TCLK0_C_MARK,
EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -632,7 +645,7 @@ enum {
HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
- VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK,
+ VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
@@ -649,7 +662,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
PINMUX_DATA(AVS1_MARK, FN_AVS1),
@@ -658,6 +671,9 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(A18_MARK, FN_A18),
PINMUX_DATA(A19_MARK, FN_A19),
+ PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
+ PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
+
PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
PINMUX_IPSR_DATA(IP0_2_0, PWM1),
@@ -1399,7 +1415,6 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
- PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
PINMUX_IPSR_DATA(IP11_26_24, TX2),
@@ -1450,280 +1465,1260 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
PINMUX_GPIO_GP_ALL(),
- GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
- GPIO_FN(A19),
+};
- /* IPSR0 */
- GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
- GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2),
- GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
- GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3),
- GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D),
- GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D),
- GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D),
- GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
- GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD),
- GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2),
- GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5),
- GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B),
- GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT),
- GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0),
- GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
- GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
- GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C),
+/* - DU0 -------------------------------------------------------------------- */
+static const unsigned int du0_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ 188, 187, 186, 185, 184, 183,
+ 194, 193, 192, 191, 190, 189,
+ 200, 199, 198, 197, 196, 195,
+};
+static const unsigned int du0_rgb666_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK,
+};
+static const unsigned int du0_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ 188, 187, 186, 185, 184, 183, 24, 23,
+ 194, 193, 192, 191, 190, 189, 26, 25,
+ 200, 199, 198, 197, 196, 195, 28, 27,
+};
+static const unsigned int du0_rgb888_mux[] = {
+ DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
+ DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
+ DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
+ DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
+ DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
+ DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
+};
+static const unsigned int du0_clk_in_pins[] = {
+ /* CLKIN */
+ 29,
+};
+static const unsigned int du0_clk_in_mux[] = {
+ DU0_DOTCLKIN_MARK,
+};
+static const unsigned int du0_clk_out_0_pins[] = {
+ /* CLKOUT */
+ 180,
+};
+static const unsigned int du0_clk_out_0_mux[] = {
+ DU0_DOTCLKOUT0_MARK,
+};
+static const unsigned int du0_clk_out_1_pins[] = {
+ /* CLKOUT */
+ 30,
+};
+static const unsigned int du0_clk_out_1_mux[] = {
+ DU0_DOTCLKOUT1_MARK,
+};
+static const unsigned int du0_sync_0_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 182, 181, 31,
+};
+static const unsigned int du0_sync_0_mux[] = {
+ DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_sync_1_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 182, 181, 32,
+};
+static const unsigned int du0_sync_1_mux[] = {
+ DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
+ DU0_DISP_MARK
+};
+static const unsigned int du0_oddf_pins[] = {
+ /* ODDF */
+ 31,
+};
+static const unsigned int du0_oddf_mux[] = {
+ DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du0_cde_pins[] = {
+ /* CDE */
+ 33,
+};
+static const unsigned int du0_cde_mux[] = {
+ DU0_CDE_MARK
+};
+/* - DU1 -------------------------------------------------------------------- */
+static const unsigned int du1_rgb666_pins[] = {
+ /* R[7:2], G[7:2], B[7:2] */
+ 41, 40, 39, 38, 37, 36,
+ 49, 48, 47, 46, 45, 44,
+ 57, 56, 55, 54, 53, 52,
+};
+static const unsigned int du1_rgb666_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK,
+};
+static const unsigned int du1_rgb888_pins[] = {
+ /* R[7:0], G[7:0], B[7:0] */
+ 41, 40, 39, 38, 37, 36, 35, 34,
+ 49, 48, 47, 46, 45, 44, 43, 32,
+ 57, 56, 55, 54, 53, 52, 51, 50,
+};
+static const unsigned int du1_rgb888_mux[] = {
+ DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
+ DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
+ DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
+ DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
+ DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
+ DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
+};
+static const unsigned int du1_clk_in_pins[] = {
+ /* CLKIN */
+ 58,
+};
+static const unsigned int du1_clk_in_mux[] = {
+ DU1_DOTCLKIN_MARK,
+};
+static const unsigned int du1_clk_out_pins[] = {
+ /* CLKOUT */
+ 59,
+};
+static const unsigned int du1_clk_out_mux[] = {
+ DU1_DOTCLKOUT_MARK,
+};
+static const unsigned int du1_sync_0_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 61, 60, 62,
+};
+static const unsigned int du1_sync_0_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_sync_1_pins[] = {
+ /* VSYNC, HSYNC, DISP */
+ 61, 60, 63,
+};
+static const unsigned int du1_sync_1_mux[] = {
+ DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
+ DU1_DISP_MARK
+};
+static const unsigned int du1_oddf_pins[] = {
+ /* ODDF */
+ 62,
+};
+static const unsigned int du1_oddf_mux[] = {
+ DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
+};
+static const unsigned int du1_cde_pins[] = {
+ /* CDE */
+ 64,
+};
+static const unsigned int du1_cde_mux[] = {
+ DU1_CDE_MARK
+};
+/* - HSPI0 ------------------------------------------------------------------ */
+static const unsigned int hspi0_pins[] = {
+ /* CLK, CS, RX, TX */
+ 150, 151, 153, 152,
+};
+static const unsigned int hspi0_mux[] = {
+ HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
+};
+/* - HSPI1 ------------------------------------------------------------------ */
+static const unsigned int hspi1_pins[] = {
+ /* CLK, CS, RX, TX */
+ 63, 58, 64, 62,
+};
+static const unsigned int hspi1_mux[] = {
+ HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
+};
+static const unsigned int hspi1_b_pins[] = {
+ /* CLK, CS, RX, TX */
+ 90, 91, 93, 92,
+};
+static const unsigned int hspi1_b_mux[] = {
+ HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
+};
+static const unsigned int hspi1_c_pins[] = {
+ /* CLK, CS, RX, TX */
+ 141, 142, 144, 143,
+};
+static const unsigned int hspi1_c_mux[] = {
+ HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
+};
+static const unsigned int hspi1_d_pins[] = {
+ /* CLK, CS, RX, TX */
+ 101, 102, 104, 103,
+};
+static const unsigned int hspi1_d_mux[] = {
+ HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
+};
+/* - HSPI2 ------------------------------------------------------------------ */
+static const unsigned int hspi2_pins[] = {
+ /* CLK, CS, RX, TX */
+ 9, 10, 11, 14,
+};
+static const unsigned int hspi2_mux[] = {
+ HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
+};
+static const unsigned int hspi2_b_pins[] = {
+ /* CLK, CS, RX, TX */
+ 7, 13, 8, 6,
+};
+static const unsigned int hspi2_b_mux[] = {
+ HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+ /* IRQ */
+ 78,
+};
+static const unsigned int intc_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_irq0_b_pins[] = {
+ /* IRQ */
+ 141,
+};
+static const unsigned int intc_irq0_b_mux[] = {
+ IRQ0_B_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+ /* IRQ */
+ 79,
+};
+static const unsigned int intc_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_irq1_b_pins[] = {
+ /* IRQ */
+ 142,
+};
+static const unsigned int intc_irq1_b_mux[] = {
+ IRQ1_B_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+ /* IRQ */
+ 88,
+};
+static const unsigned int intc_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_irq2_b_pins[] = {
+ /* IRQ */
+ 143,
+};
+static const unsigned int intc_irq2_b_mux[] = {
+ IRQ2_B_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+ /* IRQ */
+ 89,
+};
+static const unsigned int intc_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_irq3_b_pins[] = {
+ /* IRQ */
+ 144,
+};
+static const unsigned int intc_irq3_b_mux[] = {
+ IRQ3_B_MARK,
+};
+/* - LSBC ------------------------------------------------------------------- */
+static const unsigned int lbsc_cs0_pins[] = {
+ /* CS */
+ 13,
+};
+static const unsigned int lbsc_cs0_mux[] = {
+ CS0_MARK,
+};
+static const unsigned int lbsc_cs1_pins[] = {
+ /* CS */
+ 14,
+};
+static const unsigned int lbsc_cs1_mux[] = {
+ CS1_A26_MARK,
+};
+static const unsigned int lbsc_ex_cs0_pins[] = {
+ /* CS */
+ 15,
+};
+static const unsigned int lbsc_ex_cs0_mux[] = {
+ EX_CS0_MARK,
+};
+static const unsigned int lbsc_ex_cs1_pins[] = {
+ /* CS */
+ 16,
+};
+static const unsigned int lbsc_ex_cs1_mux[] = {
+ EX_CS1_MARK,
+};
+static const unsigned int lbsc_ex_cs2_pins[] = {
+ /* CS */
+ 17,
+};
+static const unsigned int lbsc_ex_cs2_mux[] = {
+ EX_CS2_MARK,
+};
+static const unsigned int lbsc_ex_cs3_pins[] = {
+ /* CS */
+ 18,
+};
+static const unsigned int lbsc_ex_cs3_mux[] = {
+ EX_CS3_MARK,
+};
+static const unsigned int lbsc_ex_cs4_pins[] = {
+ /* CS */
+ 19,
+};
+static const unsigned int lbsc_ex_cs4_mux[] = {
+ EX_CS4_MARK,
+};
+static const unsigned int lbsc_ex_cs5_pins[] = {
+ /* CS */
+ 20,
+};
+static const unsigned int lbsc_ex_cs5_mux[] = {
+ EX_CS5_MARK,
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+ /* D[0] */
+ 19,
+};
+static const unsigned int mmc0_data1_mux[] = {
+ MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+ /* D[0:3] */
+ 19, 20, 21, 2,
+};
+static const unsigned int mmc0_data4_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+ /* D[0:7] */
+ 19, 20, 21, 2, 10, 11, 15, 16,
+};
+static const unsigned int mmc0_data8_mux[] = {
+ MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+ MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 18, 17,
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+ MMC0_CMD_MARK, MMC0_CLK_MARK,
+};
+static const unsigned int mmc1_data1_pins[] = {
+ /* D[0] */
+ 72,
+};
+static const unsigned int mmc1_data1_mux[] = {
+ MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+ /* D[0:3] */
+ 72, 73, 74, 75,
+};
+static const unsigned int mmc1_data4_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+ /* D[0:7] */
+ 72, 73, 74, 75, 76, 77, 80, 81,
+};
+static const unsigned int mmc1_data8_mux[] = {
+ MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+ MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 68, 65,
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+ MMC1_CMD_MARK, MMC1_CLK_MARK,
+};
+/* - SCIF0 ------------------------------------------------------------------ */
+static const unsigned int scif0_data_pins[] = {
+ /* RXD, TXD */
+ 153, 152,
+};
+static const unsigned int scif0_data_mux[] = {
+ RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+ /* SCK */
+ 156,
+};
+static const unsigned int scif0_clk_mux[] = {
+ SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+ /* RTS, CTS */
+ 151, 150,
+};
+static const unsigned int scif0_ctrl_mux[] = {
+ RTS0_TANS_MARK, CTS0_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+ /* RXD, TXD */
+ 20, 19,
+};
+static const unsigned int scif0_data_b_mux[] = {
+ RX0_B_MARK, TX0_B_MARK,
+};
+static const unsigned int scif0_clk_b_pins[] = {
+ /* SCK */
+ 33,
+};
+static const unsigned int scif0_clk_b_mux[] = {
+ SCK0_B_MARK,
+};
+static const unsigned int scif0_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ 18, 11,
+};
+static const unsigned int scif0_ctrl_b_mux[] = {
+ RTS0_B_TANS_B_MARK, CTS0_B_MARK,
+};
+static const unsigned int scif0_data_c_pins[] = {
+ /* RXD, TXD */
+ 146, 147,
+};
+static const unsigned int scif0_data_c_mux[] = {
+ RX0_C_MARK, TX0_C_MARK,
+};
+static const unsigned int scif0_clk_c_pins[] = {
+ /* SCK */
+ 145,
+};
+static const unsigned int scif0_clk_c_mux[] = {
+ SCK0_C_MARK,
+};
+static const unsigned int scif0_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ 149, 148,
+};
+static const unsigned int scif0_ctrl_c_mux[] = {
+ RTS0_C_TANS_C_MARK, CTS0_C_MARK,
+};
+static const unsigned int scif0_data_d_pins[] = {
+ /* RXD, TXD */
+ 43, 42,
+};
+static const unsigned int scif0_data_d_mux[] = {
+ RX0_D_MARK, TX0_D_MARK,
+};
+static const unsigned int scif0_clk_d_pins[] = {
+ /* SCK */
+ 50,
+};
+static const unsigned int scif0_clk_d_mux[] = {
+ SCK0_D_MARK,
+};
+static const unsigned int scif0_ctrl_d_pins[] = {
+ /* RTS, CTS */
+ 51, 35,
+};
+static const unsigned int scif0_ctrl_d_mux[] = {
+ RTS0_D_TANS_D_MARK, CTS0_D_MARK,
+};
+/* - SCIF1 ------------------------------------------------------------------ */
+static const unsigned int scif1_data_pins[] = {
+ /* RXD, TXD */
+ 149, 148,
+};
+static const unsigned int scif1_data_mux[] = {
+ RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+ /* SCK */
+ 145,
+};
+static const unsigned int scif1_clk_mux[] = {
+ SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+ /* RTS, CTS */
+ 147, 146,
+};
+static const unsigned int scif1_ctrl_mux[] = {
+ RTS1_TANS_MARK, CTS1_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+ /* RXD, TXD */
+ 117, 114,
+};
+static const unsigned int scif1_data_b_mux[] = {
+ RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_clk_b_pins[] = {
+ /* SCK */
+ 113,
+};
+static const unsigned int scif1_clk_b_mux[] = {
+ SCK1_B_MARK,
+};
+static const unsigned int scif1_ctrl_b_pins[] = {
+ /* RTS, CTS */
+ 115, 116,
+};
+static const unsigned int scif1_ctrl_b_mux[] = {
+ RTS1_B_TANS_B_MARK, CTS1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+ /* RXD, TXD */
+ 67, 66,
+};
+static const unsigned int scif1_data_c_mux[] = {
+ RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_clk_c_pins[] = {
+ /* SCK */
+ 86,
+};
+static const unsigned int scif1_clk_c_mux[] = {
+ SCK1_C_MARK,
+};
+static const unsigned int scif1_ctrl_c_pins[] = {
+ /* RTS, CTS */
+ 69, 68,
+};
+static const unsigned int scif1_ctrl_c_mux[] = {
+ RTS1_C_TANS_C_MARK, CTS1_C_MARK,
+};
+/* - SCIF2 ------------------------------------------------------------------ */
+static const unsigned int scif2_data_pins[] = {
+ /* RXD, TXD */
+ 106, 105,
+};
+static const unsigned int scif2_data_mux[] = {
+ RX2_MARK, TX2_MARK,
+};
+static const unsigned int scif2_clk_pins[] = {
+ /* SCK */
+ 107,
+};
+static const unsigned int scif2_clk_mux[] = {
+ SCK2_MARK,
+};
+static const unsigned int scif2_data_b_pins[] = {
+ /* RXD, TXD */
+ 120, 119,
+};
+static const unsigned int scif2_data_b_mux[] = {
+ RX2_B_MARK, TX2_B_MARK,
+};
+static const unsigned int scif2_clk_b_pins[] = {
+ /* SCK */
+ 118,
+};
+static const unsigned int scif2_clk_b_mux[] = {
+ SCK2_B_MARK,
+};
+static const unsigned int scif2_data_c_pins[] = {
+ /* RXD, TXD */
+ 33, 31,
+};
+static const unsigned int scif2_data_c_mux[] = {
+ RX2_C_MARK, TX2_C_MARK,
+};
+static const unsigned int scif2_clk_c_pins[] = {
+ /* SCK */
+ 32,
+};
+static const unsigned int scif2_clk_c_mux[] = {
+ SCK2_C_MARK,
+};
+static const unsigned int scif2_data_d_pins[] = {
+ /* RXD, TXD */
+ 64, 62,
+};
+static const unsigned int scif2_data_d_mux[] = {
+ RX2_D_MARK, TX2_D_MARK,
+};
+static const unsigned int scif2_clk_d_pins[] = {
+ /* SCK */
+ 63,
+};
+static const unsigned int scif2_clk_d_mux[] = {
+ SCK2_D_MARK,
+};
+static const unsigned int scif2_data_e_pins[] = {
+ /* RXD, TXD */
+ 20, 19,
+};
+static const unsigned int scif2_data_e_mux[] = {
+ RX2_E_MARK, TX2_E_MARK,
+};
+/* - SCIF3 ------------------------------------------------------------------ */
+static const unsigned int scif3_data_pins[] = {
+ /* RXD, TXD */
+ 137, 136,
+};
+static const unsigned int scif3_data_mux[] = {
+ RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
+};
+static const unsigned int scif3_clk_pins[] = {
+ /* SCK */
+ 135,
+};
+static const unsigned int scif3_clk_mux[] = {
+ SCK3_MARK,
+};
- /* IPSR1 */
- GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6),
- GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7),
- GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE),
- GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD),
- GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B),
- GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B),
- GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0),
- GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
- GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B),
- GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1),
- GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
- GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9),
- GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG),
- GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
- GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA),
- GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
- GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
- GPIO_FN(CC5_STATE34),
+static const unsigned int scif3_data_b_pins[] = {
+ /* RXD, TXD */
+ 64, 62,
+};
+static const unsigned int scif3_data_b_mux[] = {
+ RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
+};
+static const unsigned int scif3_data_c_pins[] = {
+ /* RXD, TXD */
+ 15, 12,
+};
+static const unsigned int scif3_data_c_mux[] = {
+ RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
+};
+static const unsigned int scif3_data_d_pins[] = {
+ /* RXD, TXD */
+ 30, 29,
+};
+static const unsigned int scif3_data_d_mux[] = {
+ RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
+};
+static const unsigned int scif3_data_e_pins[] = {
+ /* RXD, TXD */
+ 35, 34,
+};
+static const unsigned int scif3_data_e_mux[] = {
+ RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
+};
+static const unsigned int scif3_clk_e_pins[] = {
+ /* SCK */
+ 42,
+};
+static const unsigned int scif3_clk_e_mux[] = {
+ SCK3_E_MARK,
+};
+/* - SCIF4 ------------------------------------------------------------------ */
+static const unsigned int scif4_data_pins[] = {
+ /* RXD, TXD */
+ 123, 122,
+};
+static const unsigned int scif4_data_mux[] = {
+ RX4_MARK, TX4_MARK,
+};
+static const unsigned int scif4_clk_pins[] = {
+ /* SCK */
+ 121,
+};
+static const unsigned int scif4_clk_mux[] = {
+ SCK4_MARK,
+};
+static const unsigned int scif4_data_b_pins[] = {
+ /* RXD, TXD */
+ 111, 110,
+};
+static const unsigned int scif4_data_b_mux[] = {
+ RX4_B_MARK, TX4_B_MARK,
+};
+static const unsigned int scif4_clk_b_pins[] = {
+ /* SCK */
+ 112,
+};
+static const unsigned int scif4_clk_b_mux[] = {
+ SCK4_B_MARK,
+};
+static const unsigned int scif4_data_c_pins[] = {
+ /* RXD, TXD */
+ 22, 21,
+};
+static const unsigned int scif4_data_c_mux[] = {
+ RX4_C_MARK, TX4_C_MARK,
+};
+static const unsigned int scif4_data_d_pins[] = {
+ /* RXD, TXD */
+ 69, 68,
+};
+static const unsigned int scif4_data_d_mux[] = {
+ RX4_D_MARK, TX4_D_MARK,
+};
+/* - SCIF5 ------------------------------------------------------------------ */
+static const unsigned int scif5_data_pins[] = {
+ /* RXD, TXD */
+ 51, 50,
+};
+static const unsigned int scif5_data_mux[] = {
+ RX5_MARK, TX5_MARK,
+};
+static const unsigned int scif5_clk_pins[] = {
+ /* SCK */
+ 43,
+};
+static const unsigned int scif5_clk_mux[] = {
+ SCK5_MARK,
+};
+static const unsigned int scif5_data_b_pins[] = {
+ /* RXD, TXD */
+ 18, 11,
+};
+static const unsigned int scif5_data_b_mux[] = {
+ RX5_B_MARK, TX5_B_MARK,
+};
+static const unsigned int scif5_clk_b_pins[] = {
+ /* SCK */
+ 19,
+};
+static const unsigned int scif5_clk_b_mux[] = {
+ SCK5_B_MARK,
+};
+static const unsigned int scif5_data_c_pins[] = {
+ /* RXD, TXD */
+ 24, 23,
+};
+static const unsigned int scif5_data_c_mux[] = {
+ RX5_C_MARK, TX5_C_MARK,
+};
+static const unsigned int scif5_clk_c_pins[] = {
+ /* SCK */
+ 28,
+};
+static const unsigned int scif5_clk_c_mux[] = {
+ SCK5_C_MARK,
+};
+static const unsigned int scif5_data_d_pins[] = {
+ /* RXD, TXD */
+ 8, 6,
+};
+static const unsigned int scif5_data_d_mux[] = {
+ RX5_D_MARK, TX5_D_MARK,
+};
+static const unsigned int scif5_clk_d_pins[] = {
+ /* SCK */
+ 7,
+};
+static const unsigned int scif5_clk_d_mux[] = {
+ SCK5_D_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 117,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 117, 118, 119, 120,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 114, 113,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SD0_CMD_MARK, SD0_CLK_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 115,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 116,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SD0_WP_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 19,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 19, 20, 21, 2,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 18, 17,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SD1_CMD_MARK, SD1_CLK_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+ /* CD */
+ 10,
+};
+static const unsigned int sdhi1_cd_mux[] = {
+ SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+ /* WP */
+ 11,
+};
+static const unsigned int sdhi1_wp_mux[] = {
+ SD1_WP_MARK,
+};
+/* - SDHI2 ------------------------------------------------------------------ */
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 97,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 97, 98, 99, 100,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 102, 101,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SD2_CMD_MARK, SD2_CLK_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+ /* CD */
+ 103,
+};
+static const unsigned int sdhi2_cd_mux[] = {
+ SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+ /* WP */
+ 104,
+};
+static const unsigned int sdhi2_wp_mux[] = {
+ SD2_WP_MARK,
+};
+/* - SDHI3 ------------------------------------------------------------------ */
+static const unsigned int sdhi3_data1_pins[] = {
+ /* D0 */
+ 50,
+};
+static const unsigned int sdhi3_data1_mux[] = {
+ SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+ /* D[0:3] */
+ 50, 51, 52, 53,
+};
+static const unsigned int sdhi3_data4_mux[] = {
+ SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+ /* CMD, CLK */
+ 35, 34,
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+ SD3_CMD_MARK, SD3_CLK_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+ /* CD */
+ 62,
+};
+static const unsigned int sdhi3_cd_mux[] = {
+ SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+ /* WP */
+ 64,
+};
+static const unsigned int sdhi3_wp_mux[] = {
+ SD3_WP_MARK,
+};
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_pins[] = {
+ /* OVC */
+ 150, 154,
+};
+static const unsigned int usb0_mux[] = {
+ USB_OVC0_MARK, USB_PENC0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_pins[] = {
+ /* OVC */
+ 152, 155,
+};
+static const unsigned int usb1_mux[] = {
+ USB_OVC1_MARK, USB_PENC1_MARK,
+};
+/* - USB2 ------------------------------------------------------------------- */
+static const unsigned int usb2_pins[] = {
+ /* OVC, PENC */
+ 125, 156,
+};
+static const unsigned int usb2_mux[] = {
+ USB_OVC2_MARK, USB_PENC2_MARK,
+};
- /* IPSR2 */
- GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C),
- GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
- GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
- GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5),
- GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
- GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
- GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
- GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C),
- GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
- GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS),
- GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
- GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
- GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0),
- GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
- GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
- GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C),
- GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3),
- GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5),
- GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7),
- GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
- GPIO_FN(AUDATA2),
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(du0_rgb666),
+ SH_PFC_PIN_GROUP(du0_rgb888),
+ SH_PFC_PIN_GROUP(du0_clk_in),
+ SH_PFC_PIN_GROUP(du0_clk_out_0),
+ SH_PFC_PIN_GROUP(du0_clk_out_1),
+ SH_PFC_PIN_GROUP(du0_sync_0),
+ SH_PFC_PIN_GROUP(du0_sync_1),
+ SH_PFC_PIN_GROUP(du0_oddf),
+ SH_PFC_PIN_GROUP(du0_cde),
+ SH_PFC_PIN_GROUP(du1_rgb666),
+ SH_PFC_PIN_GROUP(du1_rgb888),
+ SH_PFC_PIN_GROUP(du1_clk_in),
+ SH_PFC_PIN_GROUP(du1_clk_out),
+ SH_PFC_PIN_GROUP(du1_sync_0),
+ SH_PFC_PIN_GROUP(du1_sync_1),
+ SH_PFC_PIN_GROUP(du1_oddf),
+ SH_PFC_PIN_GROUP(du1_cde),
+ SH_PFC_PIN_GROUP(hspi0),
+ SH_PFC_PIN_GROUP(hspi1),
+ SH_PFC_PIN_GROUP(hspi1_b),
+ SH_PFC_PIN_GROUP(hspi1_c),
+ SH_PFC_PIN_GROUP(hspi1_d),
+ SH_PFC_PIN_GROUP(hspi2),
+ SH_PFC_PIN_GROUP(hspi2_b),
+ SH_PFC_PIN_GROUP(intc_irq0),
+ SH_PFC_PIN_GROUP(intc_irq0_b),
+ SH_PFC_PIN_GROUP(intc_irq1),
+ SH_PFC_PIN_GROUP(intc_irq1_b),
+ SH_PFC_PIN_GROUP(intc_irq2),
+ SH_PFC_PIN_GROUP(intc_irq2_b),
+ SH_PFC_PIN_GROUP(intc_irq3),
+ SH_PFC_PIN_GROUP(intc_irq3_b),
+ SH_PFC_PIN_GROUP(lbsc_cs0),
+ SH_PFC_PIN_GROUP(lbsc_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs0),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs1),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs2),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs3),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs4),
+ SH_PFC_PIN_GROUP(lbsc_ex_cs5),
+ SH_PFC_PIN_GROUP(mmc0_data1),
+ SH_PFC_PIN_GROUP(mmc0_data4),
+ SH_PFC_PIN_GROUP(mmc0_data8),
+ SH_PFC_PIN_GROUP(mmc0_ctrl),
+ SH_PFC_PIN_GROUP(mmc1_data1),
+ SH_PFC_PIN_GROUP(mmc1_data4),
+ SH_PFC_PIN_GROUP(mmc1_data8),
+ SH_PFC_PIN_GROUP(mmc1_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data),
+ SH_PFC_PIN_GROUP(scif0_clk),
+ SH_PFC_PIN_GROUP(scif0_ctrl),
+ SH_PFC_PIN_GROUP(scif0_data_b),
+ SH_PFC_PIN_GROUP(scif0_clk_b),
+ SH_PFC_PIN_GROUP(scif0_ctrl_b),
+ SH_PFC_PIN_GROUP(scif0_data_c),
+ SH_PFC_PIN_GROUP(scif0_clk_c),
+ SH_PFC_PIN_GROUP(scif0_ctrl_c),
+ SH_PFC_PIN_GROUP(scif0_data_d),
+ SH_PFC_PIN_GROUP(scif0_clk_d),
+ SH_PFC_PIN_GROUP(scif0_ctrl_d),
+ SH_PFC_PIN_GROUP(scif1_data),
+ SH_PFC_PIN_GROUP(scif1_clk),
+ SH_PFC_PIN_GROUP(scif1_ctrl),
+ SH_PFC_PIN_GROUP(scif1_data_b),
+ SH_PFC_PIN_GROUP(scif1_clk_b),
+ SH_PFC_PIN_GROUP(scif1_ctrl_b),
+ SH_PFC_PIN_GROUP(scif1_data_c),
+ SH_PFC_PIN_GROUP(scif1_clk_c),
+ SH_PFC_PIN_GROUP(scif1_ctrl_c),
+ SH_PFC_PIN_GROUP(scif2_data),
+ SH_PFC_PIN_GROUP(scif2_clk),
+ SH_PFC_PIN_GROUP(scif2_data_b),
+ SH_PFC_PIN_GROUP(scif2_clk_b),
+ SH_PFC_PIN_GROUP(scif2_data_c),
+ SH_PFC_PIN_GROUP(scif2_clk_c),
+ SH_PFC_PIN_GROUP(scif2_data_d),
+ SH_PFC_PIN_GROUP(scif2_clk_d),
+ SH_PFC_PIN_GROUP(scif2_data_e),
+ SH_PFC_PIN_GROUP(scif3_data),
+ SH_PFC_PIN_GROUP(scif3_clk),
+ SH_PFC_PIN_GROUP(scif3_data_b),
+ SH_PFC_PIN_GROUP(scif3_data_c),
+ SH_PFC_PIN_GROUP(scif3_data_d),
+ SH_PFC_PIN_GROUP(scif3_data_e),
+ SH_PFC_PIN_GROUP(scif3_clk_e),
+ SH_PFC_PIN_GROUP(scif4_data),
+ SH_PFC_PIN_GROUP(scif4_clk),
+ SH_PFC_PIN_GROUP(scif4_data_b),
+ SH_PFC_PIN_GROUP(scif4_clk_b),
+ SH_PFC_PIN_GROUP(scif4_data_c),
+ SH_PFC_PIN_GROUP(scif4_data_d),
+ SH_PFC_PIN_GROUP(scif5_data),
+ SH_PFC_PIN_GROUP(scif5_clk),
+ SH_PFC_PIN_GROUP(scif5_data_b),
+ SH_PFC_PIN_GROUP(scif5_clk_b),
+ SH_PFC_PIN_GROUP(scif5_data_c),
+ SH_PFC_PIN_GROUP(scif5_clk_c),
+ SH_PFC_PIN_GROUP(scif5_data_d),
+ SH_PFC_PIN_GROUP(scif5_clk_d),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi1_cd),
+ SH_PFC_PIN_GROUP(sdhi1_wp),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_cd),
+ SH_PFC_PIN_GROUP(sdhi2_wp),
+ SH_PFC_PIN_GROUP(sdhi3_data1),
+ SH_PFC_PIN_GROUP(sdhi3_data4),
+ SH_PFC_PIN_GROUP(sdhi3_ctrl),
+ SH_PFC_PIN_GROUP(sdhi3_cd),
+ SH_PFC_PIN_GROUP(sdhi3_wp),
+ SH_PFC_PIN_GROUP(usb0),
+ SH_PFC_PIN_GROUP(usb1),
+ SH_PFC_PIN_GROUP(usb2),
+};
- /* IPSR3 */
- GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
- GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10),
- GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4),
- GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13),
- GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7),
- GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16),
- GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
- GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
- GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C),
- GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3),
- GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
- GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
- GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
- GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
- GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
- GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
- GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
- GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
- GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
- GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
- GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
+static const char * const du0_groups[] = {
+ "du0_rgb666",
+ "du0_rgb888",
+ "du0_clk_in",
+ "du0_clk_out_0",
+ "du0_clk_out_1",
+ "du0_sync_0",
+ "du0_sync_1",
+ "du0_oddf",
+ "du0_cde",
+};
- /* IPSR4 */
- GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C),
- GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C),
- GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B),
- GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
- GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK),
- GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1),
- GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E),
- GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0),
- GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2),
- GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
- GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
- GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
- GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
- GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
- GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
- GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
- GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
- GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
- GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
- GPIO_FN(TX5), GPIO_FN(SCK0_D),
+static const char * const du1_groups[] = {
+ "du1_rgb666",
+ "du1_rgb888",
+ "du1_clk_in",
+ "du1_clk_out",
+ "du1_sync_0",
+ "du1_sync_1",
+ "du1_oddf",
+ "du1_cde",
+};
- /* IPSR5 */
- GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
- GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D),
- GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
- GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
- GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
- GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
- GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
- GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
- GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
- GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
- GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
- GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
- GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
- GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
- GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
- GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
- GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
- GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
- GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
- GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
- GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
- GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
+static const char * const hspi0_groups[] = {
+ "hspi0",
+};
- /* IPSR6 */
- GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1),
- GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2),
- GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5),
- GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6),
- GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34),
- GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
- GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
- GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
- GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
- GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
- GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
- GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
- GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
- GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
- GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
- GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
- GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
+static const char * const hspi1_groups[] = {
+ "hspi1",
+ "hspi1_b",
+ "hspi1_c",
+ "hspi1_d",
+};
- /* IPSR7 */
- GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
- GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
- GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
- GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
- GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
- GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
- GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
- GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
- GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
- GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
- GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
- GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
- GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
- GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
- GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
- GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
- GPIO_FN(CTS1_B),
+static const char * const hspi2_groups[] = {
+ "hspi2",
+ "hspi2_b",
+};
- /* IPSR8 */
- GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK),
- GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
- GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0),
- GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI),
- GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
- GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0),
- GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
- GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
- GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0),
- GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
- GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
- GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
- GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
- GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
- GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
- GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
- GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
- GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
- GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
- GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
+static const char * const intc_groups[] = {
+ "intc_irq0",
+ "intc_irq0_b",
+ "intc_irq1",
+ "intc_irq1_b",
+ "intc_irq2",
+ "intc_irq2_b",
+ "intc_irq3",
+ "intc_irq4_b",
+};
- /* IPSR9 */
- GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
- GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
- GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3),
- GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2),
- GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6),
- GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
- GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
- GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2),
- GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1),
- GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
- GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
- GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
- GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
- GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
- GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
- GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
- GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
- GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
+static const char * const lbsc_groups[] = {
+ "lbsc_cs0",
+ "lbsc_cs1",
+ "lbsc_ex_cs0",
+ "lbsc_ex_cs1",
+ "lbsc_ex_cs2",
+ "lbsc_ex_cs3",
+ "lbsc_ex_cs4",
+ "lbsc_ex_cs5",
+};
- /* IPSR10 */
- GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C),
- GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
- GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
- GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
- GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2),
- GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
- GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
- GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
- GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
- GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
- GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
- GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
- GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
- GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
- GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
- GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
- GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
- GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
- GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
- GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
- GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
+static const char * const mmc0_groups[] = {
+ "mmc0_data1",
+ "mmc0_data4",
+ "mmc0_data8",
+ "mmc0_ctrl",
+};
- /* IPSR11 */
- GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST),
- GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
- GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
- GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2),
- GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
- GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
- GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
- GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
- GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
- GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
- GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
- GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
- GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
- GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
- GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
- GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
- GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
- GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
- GPIO_FN(HRTS0_B),
+static const char * const mmc1_groups[] = {
+ "mmc1_data1",
+ "mmc1_data4",
+ "mmc1_data8",
+ "mmc1_ctrl",
+};
- /* IPSR12 */
- GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
- GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
- GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
- GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
- GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
- GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
- GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B),
- GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
- GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
- GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B),
-};
-
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const char * const scif0_groups[] = {
+ "scif0_data",
+ "scif0_clk",
+ "scif0_ctrl",
+ "scif0_data_b",
+ "scif0_clk_b",
+ "scif0_ctrl_b",
+ "scif0_data_c",
+ "scif0_clk_c",
+ "scif0_ctrl_c",
+ "scif0_data_d",
+ "scif0_clk_d",
+ "scif0_ctrl_d",
+};
+
+static const char * const scif1_groups[] = {
+ "scif1_data",
+ "scif1_clk",
+ "scif1_ctrl",
+ "scif1_data_b",
+ "scif1_clk_b",
+ "scif1_ctrl_b",
+ "scif1_data_c",
+ "scif1_clk_c",
+ "scif1_ctrl_c",
+};
+
+static const char * const scif2_groups[] = {
+ "scif2_data",
+ "scif2_clk",
+ "scif2_data_b",
+ "scif2_clk_b",
+ "scif2_data_c",
+ "scif2_clk_c",
+ "scif2_data_d",
+ "scif2_clk_d",
+ "scif2_data_e",
+};
+
+static const char * const scif3_groups[] = {
+ "scif3_data",
+ "scif3_clk",
+ "scif3_data_b",
+ "scif3_data_c",
+ "scif3_data_d",
+ "scif3_data_e",
+ "scif3_clk_e",
+};
+
+static const char * const scif4_groups[] = {
+ "scif4_data",
+ "scif4_clk",
+ "scif4_data_b",
+ "scif4_clk_b",
+ "scif4_data_c",
+ "scif4_data_d",
+};
+
+static const char * const scif5_groups[] = {
+ "scif5_data",
+ "scif5_clk",
+ "scif5_data_b",
+ "scif5_clk_b",
+ "scif5_data_c",
+ "scif5_clk_c",
+ "scif5_data_d",
+ "scif5_clk_d",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+ "sdhi1_cd",
+ "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+ "sdhi2_cd",
+ "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+ "sdhi3_data1",
+ "sdhi3_data4",
+ "sdhi3_ctrl",
+ "sdhi3_cd",
+ "sdhi3_wp",
+};
+
+static const char * const usb0_groups[] = {
+ "usb0",
+};
+
+static const char * const usb1_groups[] = {
+ "usb1",
+};
+
+static const char * const usb2_groups[] = {
+ "usb2",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(du0),
+ SH_PFC_FUNCTION(du1),
+ SH_PFC_FUNCTION(hspi0),
+ SH_PFC_FUNCTION(hspi1),
+ SH_PFC_FUNCTION(hspi2),
+ SH_PFC_FUNCTION(intc),
+ SH_PFC_FUNCTION(lbsc),
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(mmc1),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+ SH_PFC_FUNCTION(sdhi3),
+ SH_PFC_FUNCTION(scif0),
+ SH_PFC_FUNCTION(scif1),
+ SH_PFC_FUNCTION(scif2),
+ SH_PFC_FUNCTION(scif3),
+ SH_PFC_FUNCTION(scif4),
+ SH_PFC_FUNCTION(scif5),
+ SH_PFC_FUNCTION(usb0),
+ SH_PFC_FUNCTION(usb1),
+ SH_PFC_FUNCTION(usb2),
+};
+
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
GP_0_31_FN, FN_IP3_31_29,
GP_0_30_FN, FN_IP3_26_24,
@@ -2412,7 +3407,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
/* IP11_26_24 [3] */
- FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1,
+ FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
/* IP11_23_21 [3] */
FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
@@ -2558,66 +3553,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
},
- { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
- { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
- { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
- { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
- { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
- { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
- { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0,
- 0, 0,
- 0, 0,
- GP_6_8_IN, GP_6_8_OUT,
- GP_6_7_IN, GP_6_7_OUT,
- GP_6_6_IN, GP_6_6_OUT,
- GP_6_5_IN, GP_6_5_OUT,
- GP_6_4_IN, GP_6_4_OUT,
- GP_6_3_IN, GP_6_3_OUT,
- GP_6_2_IN, GP_6_2_OUT,
- GP_6_1_IN, GP_6_1_OUT,
- GP_6_0_IN, GP_6_0_OUT, }
- },
- { },
-};
-
-static struct pinmux_data_reg pinmux_data_regs[] = {
- { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
- { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
- { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
- { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
- { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
- { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
- { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
- GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
- GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
- },
{ },
};
-struct sh_pfc_soc_info r8a7779_pinmux_info = {
+const struct sh_pfc_soc_info r8a7779_pinmux_info = {
.name = "r8a7779_pfc",
.unlock_reg = 0xfffc0000, /* PMMR */
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
- .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
- .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_GP_0_0,
- .last_gpio = GPIO_FN_SCK4_B,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
- .data_regs = pinmux_data_regs,
.gpio_data = pinmux_data,
.gpio_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 01b425dfd162..f63d51dc3f4c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -272,7 +272,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* PA */
PINMUX_DATA(PA7_DATA, PA7_IN),
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* PA */
PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@@ -815,265 +815,269 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PF2, PF2_DATA),
PINMUX_GPIO(GPIO_PF1, PF1_DATA),
PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
- PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK),
- PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
-
- PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
- PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK),
- PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK),
- PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK),
- PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK),
+ GPIO_FN(PINT7_PB),
+ GPIO_FN(PINT6_PB),
+ GPIO_FN(PINT5_PB),
+ GPIO_FN(PINT4_PB),
+ GPIO_FN(PINT3_PB),
+ GPIO_FN(PINT2_PB),
+ GPIO_FN(PINT1_PB),
+ GPIO_FN(PINT0_PB),
+ GPIO_FN(PINT7_PD),
+ GPIO_FN(PINT6_PD),
+ GPIO_FN(PINT5_PD),
+ GPIO_FN(PINT4_PD),
+ GPIO_FN(PINT3_PD),
+ GPIO_FN(PINT2_PD),
+ GPIO_FN(PINT1_PD),
+ GPIO_FN(PINT0_PD),
+ GPIO_FN(IRQ7_PB),
+ GPIO_FN(IRQ6_PB),
+ GPIO_FN(IRQ5_PB),
+ GPIO_FN(IRQ4_PB),
+ GPIO_FN(IRQ3_PB),
+ GPIO_FN(IRQ2_PB),
+ GPIO_FN(IRQ1_PB),
+ GPIO_FN(IRQ0_PB),
+ GPIO_FN(IRQ7_PD),
+ GPIO_FN(IRQ6_PD),
+ GPIO_FN(IRQ5_PD),
+ GPIO_FN(IRQ4_PD),
+ GPIO_FN(IRQ3_PD),
+ GPIO_FN(IRQ2_PD),
+ GPIO_FN(IRQ1_PD),
+ GPIO_FN(IRQ0_PD),
+ GPIO_FN(IRQ7_PE),
+ GPIO_FN(IRQ6_PE),
+ GPIO_FN(IRQ5_PE),
+ GPIO_FN(IRQ4_PE),
+ GPIO_FN(IRQ3_PE),
+ GPIO_FN(IRQ2_PE),
+ GPIO_FN(IRQ1_PE),
+ GPIO_FN(IRQ0_PE),
+
+ GPIO_FN(WDTOVF),
+ GPIO_FN(IRQOUT),
+ GPIO_FN(REFOUT),
+ GPIO_FN(IRQOUT_REFOUT),
+ GPIO_FN(UBCTRG),
/* CAN */
- PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
- PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
- PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
- PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
+ GPIO_FN(CTX1),
+ GPIO_FN(CRX1),
+ GPIO_FN(CTX0),
+ GPIO_FN(CTX0_CTX1),
+ GPIO_FN(CRX0),
+ GPIO_FN(CRX0_CRX1),
/* IIC3 */
- PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
- PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
- PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
- PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
- PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
- PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
- PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
- PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+ GPIO_FN(SDA3),
+ GPIO_FN(SCL3),
+ GPIO_FN(SDA2),
+ GPIO_FN(SCL2),
+ GPIO_FN(SDA1),
+ GPIO_FN(SCL1),
+ GPIO_FN(SDA0),
+ GPIO_FN(SCL0),
/* DMAC */
- PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK),
- PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK),
- PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK),
- PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK),
- PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK),
- PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK),
+ GPIO_FN(TEND0_PD),
+ GPIO_FN(TEND0_PE),
+ GPIO_FN(DACK0_PD),
+ GPIO_FN(DACK0_PE),
+ GPIO_FN(DREQ0_PD),
+ GPIO_FN(DREQ0_PE),
+ GPIO_FN(TEND1_PD),
+ GPIO_FN(TEND1_PE),
+ GPIO_FN(DACK1_PD),
+ GPIO_FN(DACK1_PE),
+ GPIO_FN(DREQ1_PD),
+ GPIO_FN(DREQ1_PE),
+ GPIO_FN(DACK2),
+ GPIO_FN(DREQ2),
+ GPIO_FN(DACK3),
+ GPIO_FN(DREQ3),
/* ADC */
- PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK),
- PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK),
+ GPIO_FN(ADTRG_PD),
+ GPIO_FN(ADTRG_PE),
/* BSC */
- PINMUX_GPIO(GPIO_FN_D31, D31_MARK),
- PINMUX_GPIO(GPIO_FN_D30, D30_MARK),
- PINMUX_GPIO(GPIO_FN_D29, D29_MARK),
- PINMUX_GPIO(GPIO_FN_D28, D28_MARK),
- PINMUX_GPIO(GPIO_FN_D27, D27_MARK),
- PINMUX_GPIO(GPIO_FN_D26, D26_MARK),
- PINMUX_GPIO(GPIO_FN_D25, D25_MARK),
- PINMUX_GPIO(GPIO_FN_D24, D24_MARK),
- PINMUX_GPIO(GPIO_FN_D23, D23_MARK),
- PINMUX_GPIO(GPIO_FN_D22, D22_MARK),
- PINMUX_GPIO(GPIO_FN_D21, D21_MARK),
- PINMUX_GPIO(GPIO_FN_D20, D20_MARK),
- PINMUX_GPIO(GPIO_FN_D19, D19_MARK),
- PINMUX_GPIO(GPIO_FN_D18, D18_MARK),
- PINMUX_GPIO(GPIO_FN_D17, D17_MARK),
- PINMUX_GPIO(GPIO_FN_D16, D16_MARK),
- PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
- PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
- PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
- PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
- PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
- PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
- PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK),
- PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
- PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
- PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
- PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK),
- PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
- PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK),
- PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
- PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK),
- PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
- PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
- PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
- PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK),
- PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
- PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK),
- PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
- PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK),
- PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK),
- PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK),
- PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK),
- PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK),
- PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK),
- PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
- PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
- PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
- PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
- PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK),
+ GPIO_FN(D31),
+ GPIO_FN(D30),
+ GPIO_FN(D29),
+ GPIO_FN(D28),
+ GPIO_FN(D27),
+ GPIO_FN(D26),
+ GPIO_FN(D25),
+ GPIO_FN(D24),
+ GPIO_FN(D23),
+ GPIO_FN(D22),
+ GPIO_FN(D21),
+ GPIO_FN(D20),
+ GPIO_FN(D19),
+ GPIO_FN(D18),
+ GPIO_FN(D17),
+ GPIO_FN(D16),
+ GPIO_FN(A25),
+ GPIO_FN(A24),
+ GPIO_FN(A23),
+ GPIO_FN(A22),
+ GPIO_FN(A21),
+ GPIO_FN(CS4),
+ GPIO_FN(MRES),
+ GPIO_FN(BS),
+ GPIO_FN(IOIS16),
+ GPIO_FN(CS1),
+ GPIO_FN(CS6_CE1B),
+ GPIO_FN(CE2B),
+ GPIO_FN(CS5_CE1A),
+ GPIO_FN(CE2A),
+ GPIO_FN(FRAME),
+ GPIO_FN(WAIT),
+ GPIO_FN(RDWR),
+ GPIO_FN(CKE),
+ GPIO_FN(CASU),
+ GPIO_FN(BREQ),
+ GPIO_FN(RASU),
+ GPIO_FN(BACK),
+ GPIO_FN(CASL),
+ GPIO_FN(RASL),
+ GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
+ GPIO_FN(WE2_DQMUL_ICIORD),
+ GPIO_FN(WE1_DQMLU_WE),
+ GPIO_FN(WE0_DQMLL),
+ GPIO_FN(CS3),
+ GPIO_FN(CS2),
+ GPIO_FN(A1),
+ GPIO_FN(A0),
+ GPIO_FN(CS7),
/* TMU */
- PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK),
+ GPIO_FN(TIOC4D),
+ GPIO_FN(TIOC4C),
+ GPIO_FN(TIOC4B),
+ GPIO_FN(TIOC4A),
+ GPIO_FN(TIOC3D),
+ GPIO_FN(TIOC3C),
+ GPIO_FN(TIOC3B),
+ GPIO_FN(TIOC3A),
+ GPIO_FN(TIOC2B),
+ GPIO_FN(TIOC1B),
+ GPIO_FN(TIOC2A),
+ GPIO_FN(TIOC1A),
+ GPIO_FN(TIOC0D),
+ GPIO_FN(TIOC0C),
+ GPIO_FN(TIOC0B),
+ GPIO_FN(TIOC0A),
+ GPIO_FN(TCLKD_PD),
+ GPIO_FN(TCLKC_PD),
+ GPIO_FN(TCLKB_PD),
+ GPIO_FN(TCLKA_PD),
+ GPIO_FN(TCLKD_PF),
+ GPIO_FN(TCLKC_PF),
+ GPIO_FN(TCLKB_PF),
+ GPIO_FN(TCLKA_PF),
/* SSU */
- PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK),
- PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK),
- PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK),
+ GPIO_FN(SCS0_PD),
+ GPIO_FN(SSO0_PD),
+ GPIO_FN(SSI0_PD),
+ GPIO_FN(SSCK0_PD),
+ GPIO_FN(SCS0_PF),
+ GPIO_FN(SSO0_PF),
+ GPIO_FN(SSI0_PF),
+ GPIO_FN(SSCK0_PF),
+ GPIO_FN(SCS1_PD),
+ GPIO_FN(SSO1_PD),
+ GPIO_FN(SSI1_PD),
+ GPIO_FN(SSCK1_PD),
+ GPIO_FN(SCS1_PF),
+ GPIO_FN(SSO1_PF),
+ GPIO_FN(SSI1_PF),
+ GPIO_FN(SSCK1_PF),
/* SCIF */
- PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
- PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
- PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
- PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
- PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
- PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
- PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
- PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
- PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
- PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
- PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
- PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
- PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+ GPIO_FN(TXD0),
+ GPIO_FN(RXD0),
+ GPIO_FN(SCK0),
+ GPIO_FN(TXD1),
+ GPIO_FN(RXD1),
+ GPIO_FN(SCK1),
+ GPIO_FN(TXD2),
+ GPIO_FN(RXD2),
+ GPIO_FN(SCK2),
+ GPIO_FN(RTS3),
+ GPIO_FN(CTS3),
+ GPIO_FN(TXD3),
+ GPIO_FN(RXD3),
+ GPIO_FN(SCK3),
/* SSI */
- PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
+ GPIO_FN(AUDIO_CLK),
+ GPIO_FN(SSIDATA3),
+ GPIO_FN(SSIWS3),
+ GPIO_FN(SSISCK3),
+ GPIO_FN(SSIDATA2),
+ GPIO_FN(SSIWS2),
+ GPIO_FN(SSISCK2),
+ GPIO_FN(SSIDATA1),
+ GPIO_FN(SSIWS1),
+ GPIO_FN(SSISCK1),
+ GPIO_FN(SSIDATA0),
+ GPIO_FN(SSIWS0),
+ GPIO_FN(SSISCK0),
/* FLCTL */
- PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
- PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
- PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK),
- PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK),
- PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK),
- PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK),
- PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK),
- PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK),
- PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK),
- PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK),
- PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK),
- PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK),
- PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK),
- PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK),
+ GPIO_FN(FCE),
+ GPIO_FN(FRB),
+ GPIO_FN(NAF7),
+ GPIO_FN(NAF6),
+ GPIO_FN(NAF5),
+ GPIO_FN(NAF4),
+ GPIO_FN(NAF3),
+ GPIO_FN(NAF2),
+ GPIO_FN(NAF1),
+ GPIO_FN(NAF0),
+ GPIO_FN(FSC),
+ GPIO_FN(FOE),
+ GPIO_FN(FCDE),
+ GPIO_FN(FWE),
/* LCDC */
- PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+ GPIO_FN(LCD_VEPWC),
+ GPIO_FN(LCD_VCPWC),
+ GPIO_FN(LCD_CLK),
+ GPIO_FN(LCD_FLM),
+ GPIO_FN(LCD_M_DISP),
+ GPIO_FN(LCD_CL2),
+ GPIO_FN(LCD_CL1),
+ GPIO_FN(LCD_DON),
+ GPIO_FN(LCD_DATA15),
+ GPIO_FN(LCD_DATA14),
+ GPIO_FN(LCD_DATA13),
+ GPIO_FN(LCD_DATA12),
+ GPIO_FN(LCD_DATA11),
+ GPIO_FN(LCD_DATA10),
+ GPIO_FN(LCD_DATA9),
+ GPIO_FN(LCD_DATA8),
+ GPIO_FN(LCD_DATA7),
+ GPIO_FN(LCD_DATA6),
+ GPIO_FN(LCD_DATA5),
+ GPIO_FN(LCD_DATA4),
+ GPIO_FN(LCD_DATA3),
+ GPIO_FN(LCD_DATA2),
+ GPIO_FN(LCD_DATA1),
+ GPIO_FN(LCD_DATA0),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
0, 0,
0, 0,
@@ -1525,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
0, 0, 0, 0,
0, 0, 0, 0,
@@ -1571,19 +1575,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ },
};
-struct sh_pfc_soc_info sh7203_pinmux_info = {
+const struct sh_pfc_soc_info sh7203_pinmux_info = {
.name = "sh7203_pfc",
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA7,
- .last_gpio = GPIO_FN_LCD_DATA0,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 2ba5639dcf34..284675249ed9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -604,7 +604,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA3_DATA, PA3_IN),
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD_D2_MARK, PK0MD_10),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@@ -1216,257 +1216,261 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PK2, PK2_DATA),
PINMUX_GPIO(GPIO_PK1, PK1_DATA),
PINMUX_GPIO(GPIO_PK0, PK0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
- PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
-
- PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
+ GPIO_FN(PINT7_PG),
+ GPIO_FN(PINT6_PG),
+ GPIO_FN(PINT5_PG),
+ GPIO_FN(PINT4_PG),
+ GPIO_FN(PINT3_PG),
+ GPIO_FN(PINT2_PG),
+ GPIO_FN(PINT1_PG),
+
+ GPIO_FN(IRQ7_PC),
+ GPIO_FN(IRQ6_PC),
+ GPIO_FN(IRQ5_PC),
+ GPIO_FN(IRQ4_PC),
+ GPIO_FN(IRQ3_PG),
+ GPIO_FN(IRQ2_PG),
+ GPIO_FN(IRQ1_PJ),
+ GPIO_FN(IRQ0_PJ),
+ GPIO_FN(IRQ3_PE),
+ GPIO_FN(IRQ2_PE),
+ GPIO_FN(IRQ1_PE),
+ GPIO_FN(IRQ0_PE),
/* WDT */
- PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+ GPIO_FN(WDTOVF),
/* CAN */
- PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
- PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
- PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
+ GPIO_FN(CTX1),
+ GPIO_FN(CRX1),
+ GPIO_FN(CTX0),
+ GPIO_FN(CRX0),
+ GPIO_FN(CRX0_CRX1),
/* DMAC */
- PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
- PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
- PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
- PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+ GPIO_FN(TEND0),
+ GPIO_FN(DACK0),
+ GPIO_FN(DREQ0),
+ GPIO_FN(TEND1),
+ GPIO_FN(DACK1),
+ GPIO_FN(DREQ1),
/* ADC */
- PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+ GPIO_FN(ADTRG),
/* BSCh */
- PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
- PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
- PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
- PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
- PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
- PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
- PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
- PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
- PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
- PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
- PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
- PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
- PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
- PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
- PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
- PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
- PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
- PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
- PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
- PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
- PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
- PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
- PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
- PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
- PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
- PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-
- PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
- PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
- PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
- PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
- PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
- PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
- PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
- PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
- PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
- PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
- PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
- PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
- PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
- PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
- PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
- PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
-
- PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
- PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
- PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
- PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
- PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
- PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
- PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
- PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
- PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
- PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
- PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
- PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
- PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
- PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
- PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
- PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
- PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
- PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
- PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
- PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
- PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
- PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
- PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+ GPIO_FN(A25),
+ GPIO_FN(A24),
+ GPIO_FN(A23),
+ GPIO_FN(A22),
+ GPIO_FN(A21),
+ GPIO_FN(A20),
+ GPIO_FN(A19),
+ GPIO_FN(A18),
+ GPIO_FN(A17),
+ GPIO_FN(A16),
+ GPIO_FN(A15),
+ GPIO_FN(A14),
+ GPIO_FN(A13),
+ GPIO_FN(A12),
+ GPIO_FN(A11),
+ GPIO_FN(A10),
+ GPIO_FN(A9),
+ GPIO_FN(A8),
+ GPIO_FN(A7),
+ GPIO_FN(A6),
+ GPIO_FN(A5),
+ GPIO_FN(A4),
+ GPIO_FN(A3),
+ GPIO_FN(A2),
+ GPIO_FN(A1),
+ GPIO_FN(A0),
+
+ GPIO_FN(D15),
+ GPIO_FN(D14),
+ GPIO_FN(D13),
+ GPIO_FN(D12),
+ GPIO_FN(D11),
+ GPIO_FN(D10),
+ GPIO_FN(D9),
+ GPIO_FN(D8),
+ GPIO_FN(D7),
+ GPIO_FN(D6),
+ GPIO_FN(D5),
+ GPIO_FN(D4),
+ GPIO_FN(D3),
+ GPIO_FN(D2),
+ GPIO_FN(D1),
+ GPIO_FN(D0),
+
+ GPIO_FN(BS),
+ GPIO_FN(CS4),
+ GPIO_FN(CS3),
+ GPIO_FN(CS2),
+ GPIO_FN(CS1),
+ GPIO_FN(CS0),
+ GPIO_FN(CS6CE1B),
+ GPIO_FN(CS5CE1A),
+ GPIO_FN(CE2A),
+ GPIO_FN(CE2B),
+ GPIO_FN(RD),
+ GPIO_FN(RDWR),
+ GPIO_FN(ICIOWRAH),
+ GPIO_FN(ICIORD),
+ GPIO_FN(WE1DQMUWE),
+ GPIO_FN(WE0DQML),
+ GPIO_FN(RAS),
+ GPIO_FN(CAS),
+ GPIO_FN(CKE),
+ GPIO_FN(WAIT),
+ GPIO_FN(BREQ),
+ GPIO_FN(BACK),
+ GPIO_FN(IOIS16),
/* TMU */
- PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
+ GPIO_FN(TIOC4D),
+ GPIO_FN(TIOC4C),
+ GPIO_FN(TIOC4B),
+ GPIO_FN(TIOC4A),
+ GPIO_FN(TIOC3D),
+ GPIO_FN(TIOC3C),
+ GPIO_FN(TIOC3B),
+ GPIO_FN(TIOC3A),
+ GPIO_FN(TIOC2B),
+ GPIO_FN(TIOC1B),
+ GPIO_FN(TIOC2A),
+ GPIO_FN(TIOC1A),
+ GPIO_FN(TIOC0D),
+ GPIO_FN(TIOC0C),
+ GPIO_FN(TIOC0B),
+ GPIO_FN(TIOC0A),
+ GPIO_FN(TCLKD),
+ GPIO_FN(TCLKC),
+ GPIO_FN(TCLKB),
+ GPIO_FN(TCLKA),
/* SCIF */
- PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
- PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
- PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
- PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
- PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
- PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
- PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
- PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
- PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
- PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
- PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
- PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
- PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
- PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
- PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
- PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
- PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
- PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
- PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
- PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
- PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
- PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
- PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
+ GPIO_FN(TXD0),
+ GPIO_FN(RXD0),
+ GPIO_FN(SCK0),
+ GPIO_FN(TXD1),
+ GPIO_FN(RXD1),
+ GPIO_FN(SCK1),
+ GPIO_FN(TXD2),
+ GPIO_FN(RXD2),
+ GPIO_FN(SCK2),
+ GPIO_FN(RTS3),
+ GPIO_FN(CTS3),
+ GPIO_FN(TXD3),
+ GPIO_FN(RXD3),
+ GPIO_FN(SCK3),
+ GPIO_FN(TXD4),
+ GPIO_FN(RXD4),
+ GPIO_FN(TXD5),
+ GPIO_FN(RXD5),
+ GPIO_FN(TXD6),
+ GPIO_FN(RXD6),
+ GPIO_FN(TXD7),
+ GPIO_FN(RXD7),
+ GPIO_FN(RTS1),
+ GPIO_FN(CTS1),
/* RSPI */
- PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
- PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
- PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
- PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
- PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
- PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
- PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
- PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
- PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
+ GPIO_FN(RSPCK0),
+ GPIO_FN(MOSI0),
+ GPIO_FN(MISO0_PF12),
+ GPIO_FN(MISO1),
+ GPIO_FN(SSL00),
+ GPIO_FN(RSPCK1),
+ GPIO_FN(MOSI1),
+ GPIO_FN(MISO1_PG19),
+ GPIO_FN(SSL10),
/* IIC3 */
- PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
- PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
- PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
- PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
- PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
- PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+ GPIO_FN(SCL0),
+ GPIO_FN(SCL1),
+ GPIO_FN(SCL2),
+ GPIO_FN(SDA0),
+ GPIO_FN(SDA1),
+ GPIO_FN(SDA2),
/* SSI */
- PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
- PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
- PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
+ GPIO_FN(SSISCK0),
+ GPIO_FN(SSIWS0),
+ GPIO_FN(SSITXD0),
+ GPIO_FN(SSIRXD0),
+ GPIO_FN(SSIWS1),
+ GPIO_FN(SSIWS2),
+ GPIO_FN(SSIWS3),
+ GPIO_FN(SSISCK1),
+ GPIO_FN(SSISCK2),
+ GPIO_FN(SSISCK3),
+ GPIO_FN(SSIDATA1),
+ GPIO_FN(SSIDATA2),
+ GPIO_FN(SSIDATA3),
+ GPIO_FN(AUDIO_CLK),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
- PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
+ GPIO_FN(SIOFTXD),
+ GPIO_FN(SIOFRXD),
+ GPIO_FN(SIOFSYNC),
+ GPIO_FN(SIOFSCK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
- PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
- PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
+ GPIO_FN(SPDIF_IN),
+ GPIO_FN(SPDIF_OUT),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
- PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
- PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+ GPIO_FN(FCE),
+ GPIO_FN(FRB),
/* VDC3 */
- PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-
- PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+ GPIO_FN(DV_CLK),
+ GPIO_FN(DV_VSYNC),
+ GPIO_FN(DV_HSYNC),
+
+ GPIO_FN(DV_DATA7),
+ GPIO_FN(DV_DATA6),
+ GPIO_FN(DV_DATA5),
+ GPIO_FN(DV_DATA4),
+ GPIO_FN(DV_DATA3),
+ GPIO_FN(DV_DATA2),
+ GPIO_FN(DV_DATA1),
+ GPIO_FN(DV_DATA0),
+
+ GPIO_FN(LCD_CLK),
+ GPIO_FN(LCD_EXTCLK),
+ GPIO_FN(LCD_VSYNC),
+ GPIO_FN(LCD_HSYNC),
+ GPIO_FN(LCD_DE),
+
+ GPIO_FN(LCD_DATA15),
+ GPIO_FN(LCD_DATA14),
+ GPIO_FN(LCD_DATA13),
+ GPIO_FN(LCD_DATA12),
+ GPIO_FN(LCD_DATA11),
+ GPIO_FN(LCD_DATA10),
+ GPIO_FN(LCD_DATA9),
+ GPIO_FN(LCD_DATA8),
+ GPIO_FN(LCD_DATA7),
+ GPIO_FN(LCD_DATA6),
+ GPIO_FN(LCD_DATA5),
+ GPIO_FN(LCD_DATA4),
+ GPIO_FN(LCD_DATA3),
+ GPIO_FN(LCD_DATA2),
+ GPIO_FN(LCD_DATA1),
+ GPIO_FN(LCD_DATA0),
+
+ GPIO_FN(LCD_M_DISP),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
{ PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
@@ -2032,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
0, 0, 0, 0, 0, 0, 0, PA3_DATA,
0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@@ -2110,19 +2114,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
-struct sh_pfc_soc_info sh7264_pinmux_info = {
+const struct sh_pfc_soc_info sh7264_pinmux_info = {
.name = "sh7264_pfc",
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA3,
- .last_gpio = GPIO_FN_LCD_M_DISP,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index b1b5d6d4ad76..4c401a74acd5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -781,7 +781,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* Port A */
PINMUX_DATA(PA1_DATA, PA1_IN),
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
};
-static struct pinmux_gpio pinmux_gpios[] = {
+static struct sh_pfc_pin pinmux_pins[] = {
/* Port A */
PINMUX_GPIO(GPIO_PA1, PA1_DATA),
PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@@ -1613,339 +1613,343 @@ static struct pinmux_gpio pinmux_gpios[] = {
PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+static const struct pinmux_func pinmux_func_gpios[] = {
/* INTC */
- PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK),
- PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK),
-
- PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK),
- PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK),
- PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK),
- PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK),
+ GPIO_FN(IRQ7_PG),
+ GPIO_FN(IRQ6_PG),
+ GPIO_FN(IRQ5_PG),
+ GPIO_FN(IRQ4_PG),
+ GPIO_FN(IRQ3_PG),
+ GPIO_FN(IRQ2_PG),
+ GPIO_FN(IRQ1_PG),
+ GPIO_FN(IRQ0_PG),
+ GPIO_FN(IRQ7_PF),
+ GPIO_FN(IRQ6_PF),
+ GPIO_FN(IRQ5_PF),
+ GPIO_FN(IRQ4_PF),
+ GPIO_FN(IRQ3_PJ),
+ GPIO_FN(IRQ2_PJ),
+ GPIO_FN(IRQ1_PJ),
+ GPIO_FN(IRQ0_PJ),
+ GPIO_FN(IRQ1_PC),
+ GPIO_FN(IRQ0_PC),
+
+ GPIO_FN(PINT7_PG),
+ GPIO_FN(PINT6_PG),
+ GPIO_FN(PINT5_PG),
+ GPIO_FN(PINT4_PG),
+ GPIO_FN(PINT3_PG),
+ GPIO_FN(PINT2_PG),
+ GPIO_FN(PINT1_PG),
+ GPIO_FN(PINT0_PG),
+ GPIO_FN(PINT7_PH),
+ GPIO_FN(PINT6_PH),
+ GPIO_FN(PINT5_PH),
+ GPIO_FN(PINT4_PH),
+ GPIO_FN(PINT3_PH),
+ GPIO_FN(PINT2_PH),
+ GPIO_FN(PINT1_PH),
+ GPIO_FN(PINT0_PH),
+ GPIO_FN(PINT7_PJ),
+ GPIO_FN(PINT6_PJ),
+ GPIO_FN(PINT5_PJ),
+ GPIO_FN(PINT4_PJ),
+ GPIO_FN(PINT3_PJ),
+ GPIO_FN(PINT2_PJ),
+ GPIO_FN(PINT1_PJ),
+ GPIO_FN(PINT0_PJ),
/* WDT */
- PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+ GPIO_FN(WDTOVF),
/* CAN */
- PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
- PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
- PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK),
- PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK),
+ GPIO_FN(CTX1),
+ GPIO_FN(CRX1),
+ GPIO_FN(CTX0),
+ GPIO_FN(CRX0),
+ GPIO_FN(CRX0_CRX1),
+ GPIO_FN(CRX0_CRX1_CRX2),
/* DMAC */
- PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
- PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
- PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
- PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
- PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+ GPIO_FN(TEND0),
+ GPIO_FN(DACK0),
+ GPIO_FN(DREQ0),
+ GPIO_FN(TEND1),
+ GPIO_FN(DACK1),
+ GPIO_FN(DREQ1),
/* ADC */
- PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+ GPIO_FN(ADTRG),
/* BSCh */
- PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
- PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
- PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
- PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
- PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
- PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
- PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
- PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
- PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
- PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
- PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
- PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
- PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
- PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
- PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
- PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
- PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
- PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
- PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
- PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
- PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
- PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
- PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
- PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
- PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
- PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
-
- PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
- PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
- PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
- PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
- PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
- PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
- PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
- PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
- PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
- PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
- PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
- PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
- PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
- PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
- PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
- PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
-
- PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
- PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
- PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
- PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
- PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
- PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
- PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
- PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
- PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
- PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
- PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
- PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK),
- PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK),
- PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
- PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
- PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
- PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
- PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
- PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
- PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
- PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
- PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+ GPIO_FN(A25),
+ GPIO_FN(A24),
+ GPIO_FN(A23),
+ GPIO_FN(A22),
+ GPIO_FN(A21),
+ GPIO_FN(A20),
+ GPIO_FN(A19),
+ GPIO_FN(A18),
+ GPIO_FN(A17),
+ GPIO_FN(A16),
+ GPIO_FN(A15),
+ GPIO_FN(A14),
+ GPIO_FN(A13),
+ GPIO_FN(A12),
+ GPIO_FN(A11),
+ GPIO_FN(A10),
+ GPIO_FN(A9),
+ GPIO_FN(A8),
+ GPIO_FN(A7),
+ GPIO_FN(A6),
+ GPIO_FN(A5),
+ GPIO_FN(A4),
+ GPIO_FN(A3),
+ GPIO_FN(A2),
+ GPIO_FN(A1),
+ GPIO_FN(A0),
+
+ GPIO_FN(D15),
+ GPIO_FN(D14),
+ GPIO_FN(D13),
+ GPIO_FN(D12),
+ GPIO_FN(D11),
+ GPIO_FN(D10),
+ GPIO_FN(D9),
+ GPIO_FN(D8),
+ GPIO_FN(D7),
+ GPIO_FN(D6),
+ GPIO_FN(D5),
+ GPIO_FN(D4),
+ GPIO_FN(D3),
+ GPIO_FN(D2),
+ GPIO_FN(D1),
+ GPIO_FN(D0),
+
+ GPIO_FN(BS),
+ GPIO_FN(CS4),
+ GPIO_FN(CS3),
+ GPIO_FN(CS2),
+ GPIO_FN(CS1),
+ GPIO_FN(CS0),
+ GPIO_FN(CS5CE1A),
+ GPIO_FN(CE2A),
+ GPIO_FN(CE2B),
+ GPIO_FN(RD),
+ GPIO_FN(RDWR),
+ GPIO_FN(WE3ICIOWRAHDQMUU),
+ GPIO_FN(WE2ICIORDDQMUL),
+ GPIO_FN(WE1DQMUWE),
+ GPIO_FN(WE0DQML),
+ GPIO_FN(RAS),
+ GPIO_FN(CAS),
+ GPIO_FN(CKE),
+ GPIO_FN(WAIT),
+ GPIO_FN(BREQ),
+ GPIO_FN(BACK),
+ GPIO_FN(IOIS16),
/* TMU */
- PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
- PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
- PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
+ GPIO_FN(TIOC4D),
+ GPIO_FN(TIOC4C),
+ GPIO_FN(TIOC4B),
+ GPIO_FN(TIOC4A),
+ GPIO_FN(TIOC3D),
+ GPIO_FN(TIOC3C),
+ GPIO_FN(TIOC3B),
+ GPIO_FN(TIOC3A),
+ GPIO_FN(TIOC2B),
+ GPIO_FN(TIOC1B),
+ GPIO_FN(TIOC2A),
+ GPIO_FN(TIOC1A),
+ GPIO_FN(TIOC0D),
+ GPIO_FN(TIOC0C),
+ GPIO_FN(TIOC0B),
+ GPIO_FN(TIOC0A),
+ GPIO_FN(TCLKD),
+ GPIO_FN(TCLKC),
+ GPIO_FN(TCLKB),
+ GPIO_FN(TCLKA),
/* SCIF */
- PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
- PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
- PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
- PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
- PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
- PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
- PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
- PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
- PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
- PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
- PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
- PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
- PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
- PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
- PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
- PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
- PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK),
- PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
- PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
- PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK),
- PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK),
- PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK),
- PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
- PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
- PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK),
- PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
- PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
- PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK),
- PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK),
+ GPIO_FN(SCK0),
+ GPIO_FN(TXD0),
+ GPIO_FN(RXD0),
+ GPIO_FN(SCK1),
+ GPIO_FN(TXD1),
+ GPIO_FN(RXD1),
+ GPIO_FN(RTS1),
+ GPIO_FN(CTS1),
+ GPIO_FN(SCK2),
+ GPIO_FN(TXD2),
+ GPIO_FN(RXD2),
+ GPIO_FN(SCK3),
+ GPIO_FN(TXD3),
+ GPIO_FN(RXD3),
+ GPIO_FN(SCK4),
+ GPIO_FN(TXD4),
+ GPIO_FN(RXD4),
+ GPIO_FN(SCK5),
+ GPIO_FN(TXD5),
+ GPIO_FN(RXD5),
+ GPIO_FN(RTS5),
+ GPIO_FN(CTS5),
+ GPIO_FN(SCK6),
+ GPIO_FN(TXD6),
+ GPIO_FN(RXD6),
+ GPIO_FN(SCK7),
+ GPIO_FN(TXD7),
+ GPIO_FN(RXD7),
+ GPIO_FN(RTS7),
+ GPIO_FN(CTS7),
/* RSPI */
- PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK),
- PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK),
- PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK),
- PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK),
- PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK),
- PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK),
- PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK),
- PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK),
- PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
- PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
- PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
- PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
+ GPIO_FN(RSPCK0_PJ16),
+ GPIO_FN(SSL00_PJ17),
+ GPIO_FN(MOSI0_PJ18),
+ GPIO_FN(MISO0_PJ19),
+ GPIO_FN(RSPCK0_PB17),
+ GPIO_FN(SSL00_PB18),
+ GPIO_FN(MOSI0_PB19),
+ GPIO_FN(MISO0_PB20),
+ GPIO_FN(RSPCK1),
+ GPIO_FN(MOSI1),
+ GPIO_FN(MISO1),
+ GPIO_FN(SSL10),
/* IIC3 */
- PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
- PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
- PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
- PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
- PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
- PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+ GPIO_FN(SCL0),
+ GPIO_FN(SCL1),
+ GPIO_FN(SCL2),
+ GPIO_FN(SDA0),
+ GPIO_FN(SDA1),
+ GPIO_FN(SDA2),
/* SSI */
- PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
- PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
- PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
- PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
- PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK),
+ GPIO_FN(SSISCK0),
+ GPIO_FN(SSIWS0),
+ GPIO_FN(SSITXD0),
+ GPIO_FN(SSIRXD0),
+ GPIO_FN(SSIWS1),
+ GPIO_FN(SSIWS2),
+ GPIO_FN(SSIWS3),
+ GPIO_FN(SSISCK1),
+ GPIO_FN(SSISCK2),
+ GPIO_FN(SSISCK3),
+ GPIO_FN(SSIDATA1),
+ GPIO_FN(SSIDATA2),
+ GPIO_FN(SSIDATA3),
+ GPIO_FN(AUDIO_CLK),
+ GPIO_FN(AUDIO_XOUT),
/* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
- PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
+ GPIO_FN(SIOFTXD),
+ GPIO_FN(SIOFRXD),
+ GPIO_FN(SIOFSYNC),
+ GPIO_FN(SIOFSCK),
/* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
- PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
- PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
+ GPIO_FN(SPDIF_IN),
+ GPIO_FN(SPDIF_OUT),
/* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
- PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
- PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+ GPIO_FN(FCE),
+ GPIO_FN(FRB),
/* VDC3 */
- PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
-
- PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
- PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK),
- PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK),
-
- PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+ GPIO_FN(DV_CLK),
+ GPIO_FN(DV_VSYNC),
+ GPIO_FN(DV_HSYNC),
+
+ GPIO_FN(DV_DATA23),
+ GPIO_FN(DV_DATA22),
+ GPIO_FN(DV_DATA21),
+ GPIO_FN(DV_DATA20),
+ GPIO_FN(DV_DATA19),
+ GPIO_FN(DV_DATA18),
+ GPIO_FN(DV_DATA17),
+ GPIO_FN(DV_DATA16),
+ GPIO_FN(DV_DATA15),
+ GPIO_FN(DV_DATA14),
+ GPIO_FN(DV_DATA13),
+ GPIO_FN(DV_DATA12),
+ GPIO_FN(DV_DATA11),
+ GPIO_FN(DV_DATA10),
+ GPIO_FN(DV_DATA9),
+ GPIO_FN(DV_DATA8),
+ GPIO_FN(DV_DATA7),
+ GPIO_FN(DV_DATA6),
+ GPIO_FN(DV_DATA5),
+ GPIO_FN(DV_DATA4),
+ GPIO_FN(DV_DATA3),
+ GPIO_FN(DV_DATA2),
+ GPIO_FN(DV_DATA1),
+ GPIO_FN(DV_DATA0),
+
+ GPIO_FN(LCD_CLK),
+ GPIO_FN(LCD_EXTCLK),
+ GPIO_FN(LCD_VSYNC),
+ GPIO_FN(LCD_HSYNC),
+ GPIO_FN(LCD_DE),
+
+ GPIO_FN(LCD_DATA23_PG23),
+ GPIO_FN(LCD_DATA22_PG22),
+ GPIO_FN(LCD_DATA21_PG21),
+ GPIO_FN(LCD_DATA20_PG20),
+ GPIO_FN(LCD_DATA19_PG19),
+ GPIO_FN(LCD_DATA18_PG18),
+ GPIO_FN(LCD_DATA17_PG17),
+ GPIO_FN(LCD_DATA16_PG16),
+ GPIO_FN(LCD_DATA15_PG15),
+ GPIO_FN(LCD_DATA14_PG14),
+ GPIO_FN(LCD_DATA13_PG13),
+ GPIO_FN(LCD_DATA12_PG12),
+ GPIO_FN(LCD_DATA11_PG11),
+ GPIO_FN(LCD_DATA10_PG10),
+ GPIO_FN(LCD_DATA9_PG9),
+ GPIO_FN(LCD_DATA8_PG8),
+ GPIO_FN(LCD_DATA7_PG7),
+ GPIO_FN(LCD_DATA6_PG6),
+ GPIO_FN(LCD_DATA5_PG5),
+ GPIO_FN(LCD_DATA4_PG4),
+ GPIO_FN(LCD_DATA3_PG3),
+ GPIO_FN(LCD_DATA2_PG2),
+ GPIO_FN(LCD_DATA1_PG1),
+ GPIO_FN(LCD_DATA0_PG0),
+
+ GPIO_FN(LCD_DATA23_PJ23),
+ GPIO_FN(LCD_DATA22_PJ22),
+ GPIO_FN(LCD_DATA21_PJ21),
+ GPIO_FN(LCD_DATA20_PJ20),
+ GPIO_FN(LCD_DATA19_PJ19),
+ GPIO_FN(LCD_DATA18_PJ18),
+ GPIO_FN(LCD_DATA17_PJ17),
+ GPIO_FN(LCD_DATA16_PJ16),
+ GPIO_FN(LCD_DATA15_PJ15),
+ GPIO_FN(LCD_DATA14_PJ14),
+ GPIO_FN(LCD_DATA13_PJ13),
+ GPIO_FN(LCD_DATA12_PJ12),
+ GPIO_FN(LCD_DATA11_PJ11),
+ GPIO_FN(LCD_DATA10_PJ10),
+ GPIO_FN(LCD_DATA9_PJ9),
+ GPIO_FN(LCD_DATA8_PJ8),
+ GPIO_FN(LCD_DATA7_PJ7),
+ GPIO_FN(LCD_DATA6_PJ6),
+ GPIO_FN(LCD_DATA5_PJ5),
+ GPIO_FN(LCD_DATA4_PJ4),
+ GPIO_FN(LCD_DATA3_PJ3),
+ GPIO_FN(LCD_DATA2_PJ2),
+ GPIO_FN(LCD_DATA1_PJ1),
+ GPIO_FN(LCD_DATA0_PJ0),
+
+ GPIO_FN(LCD_M_DISP),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
/* "name" addr register_size Field_Width */
/* where Field_Width is 1 for single mode registers or 4 for upto 16
@@ -2734,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{}
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
0, 0, 0, 0, 0, 0, 0, PA1_DATA,
0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@@ -2813,19 +2817,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
{ }
};
-struct sh_pfc_soc_info sh7269_pinmux_info = {
+const struct sh_pfc_soc_info sh7269_pinmux_info = {
.name = "sh7269_pfc",
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PA1,
- .last_gpio = GPIO_FN_LCD_M_DISP,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d44e7f02069b..df0ae21a5ac8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -368,7 +368,7 @@ enum {
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
+static const pinmux_enum_t pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
@@ -929,11 +929,214 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
};
-static struct pinmux_gpio pinmux_gpios[] = {
-
- /* PORT */
+static struct sh_pfc_pin pinmux_pins[] = {
GPIO_PORT_ALL(),
+};
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_0_pins[] = {
+ /* D[0] */
+ 84,
+};
+static const unsigned int mmc0_data1_0_mux[] = {
+ MMCD0_0_MARK,
+};
+static const unsigned int mmc0_data4_0_pins[] = {
+ /* D[0:3] */
+ 84, 85, 86, 87,
+};
+static const unsigned int mmc0_data4_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+};
+static const unsigned int mmc0_data8_0_pins[] = {
+ /* D[0:7] */
+ 84, 85, 86, 87, 88, 89, 90, 91,
+};
+static const unsigned int mmc0_data8_0_mux[] = {
+ MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
+ MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
+};
+static const unsigned int mmc0_ctrl_0_pins[] = {
+ /* CMD, CLK */
+ 92, 99,
+};
+static const unsigned int mmc0_ctrl_0_mux[] = {
+ MMCCMD0_MARK, MMCCLK0_MARK,
+};
+
+static const unsigned int mmc0_data1_1_pins[] = {
+ /* D[0] */
+ 54,
+};
+static const unsigned int mmc0_data1_1_mux[] = {
+ MMCD1_0_MARK,
+};
+static const unsigned int mmc0_data4_1_pins[] = {
+ /* D[0:3] */
+ 54, 55, 56, 57,
+};
+static const unsigned int mmc0_data4_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+};
+static const unsigned int mmc0_data8_1_pins[] = {
+ /* D[0:7] */
+ 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int mmc0_data8_1_mux[] = {
+ MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
+ MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
+};
+static const unsigned int mmc0_ctrl_1_pins[] = {
+ /* CMD, CLK */
+ 67, 66,
+};
+static const unsigned int mmc0_ctrl_1_mux[] = {
+ MMCCMD1_MARK, MMCCLK1_MARK,
+};
+/* - SDHI0 ------------------------------------------------------------------ */
+static const unsigned int sdhi0_data1_pins[] = {
+ /* D0 */
+ 173,
+};
+static const unsigned int sdhi0_data1_mux[] = {
+ SDHID0_0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+ /* D[0:3] */
+ 173, 174, 175, 176,
+};
+static const unsigned int sdhi0_data4_mux[] = {
+ SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+ /* CMD, CLK */
+ 177, 171,
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+ SDHICMD0_MARK, SDHICLK0_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+ /* CD */
+ 172,
+};
+static const unsigned int sdhi0_cd_mux[] = {
+ SDHICD0_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+ /* WP */
+ 178,
+};
+static const unsigned int sdhi0_wp_mux[] = {
+ SDHIWP0_MARK,
+};
+/* - SDHI1 ------------------------------------------------------------------ */
+static const unsigned int sdhi1_data1_pins[] = {
+ /* D0 */
+ 180,
+};
+static const unsigned int sdhi1_data1_mux[] = {
+ SDHID1_0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+ /* D[0:3] */
+ 180, 181, 182, 183,
+};
+static const unsigned int sdhi1_data4_mux[] = {
+ SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+ /* CMD, CLK */
+ 184, 179,
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+ SDHICMD1_MARK, SDHICLK1_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+ /* D0 */
+ 186,
+};
+static const unsigned int sdhi2_data1_mux[] = {
+ SDHID2_0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+ /* D[0:3] */
+ 186, 187, 188, 189,
+};
+static const unsigned int sdhi2_data4_mux[] = {
+ SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+ /* CMD, CLK */
+ 190, 185,
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+ SDHICMD2_MARK, SDHICLK2_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+ SH_PFC_PIN_GROUP(mmc0_data1_0),
+ SH_PFC_PIN_GROUP(mmc0_data4_0),
+ SH_PFC_PIN_GROUP(mmc0_data8_0),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_0),
+ SH_PFC_PIN_GROUP(mmc0_data1_1),
+ SH_PFC_PIN_GROUP(mmc0_data4_1),
+ SH_PFC_PIN_GROUP(mmc0_data8_1),
+ SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+ SH_PFC_PIN_GROUP(sdhi0_data1),
+ SH_PFC_PIN_GROUP(sdhi0_data4),
+ SH_PFC_PIN_GROUP(sdhi0_ctrl),
+ SH_PFC_PIN_GROUP(sdhi0_cd),
+ SH_PFC_PIN_GROUP(sdhi0_wp),
+ SH_PFC_PIN_GROUP(sdhi1_data1),
+ SH_PFC_PIN_GROUP(sdhi1_data4),
+ SH_PFC_PIN_GROUP(sdhi1_ctrl),
+ SH_PFC_PIN_GROUP(sdhi2_data1),
+ SH_PFC_PIN_GROUP(sdhi2_data4),
+ SH_PFC_PIN_GROUP(sdhi2_ctrl),
+};
+
+static const char * const mmc0_groups[] = {
+ "mmc0_data1_0",
+ "mmc0_data4_0",
+ "mmc0_data8_0",
+ "mmc0_ctrl_0",
+ "mmc0_data1_1",
+ "mmc0_data4_1",
+ "mmc0_data8_1",
+ "mmc0_ctrl_1",
+};
+
+static const char * const sdhi0_groups[] = {
+ "sdhi0_data1",
+ "sdhi0_data4",
+ "sdhi0_ctrl",
+ "sdhi0_cd",
+ "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+ "sdhi1_data1",
+ "sdhi1_data4",
+ "sdhi1_ctrl",
+};
+
+static const char * const sdhi2_groups[] = {
+ "sdhi2_data1",
+ "sdhi2_data4",
+ "sdhi2_ctrl",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+ SH_PFC_FUNCTION(mmc0),
+ SH_PFC_FUNCTION(sdhi0),
+ SH_PFC_FUNCTION(sdhi1),
+ SH_PFC_FUNCTION(sdhi2),
+};
+
+#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
+
+static const struct pinmux_func pinmux_func_gpios[] = {
/* IRQ */
GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@@ -1074,18 +1277,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
- /* MMCIF(1) */
- GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2),
- GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5),
- GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0),
- GPIO_FN(MMCCLK0),
-
- /* MMCIF(2) */
- GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2),
- GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5),
- GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1),
- GPIO_FN(MMCCMD1),
-
/* SPU2 */
GPIO_FN(VINT_I),
@@ -1182,25 +1373,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
/* HDMI */
GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
- /* SDHI0 */
- GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0),
- GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1),
- GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3),
-
- /* SDHI1 */
- GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0),
- GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3),
-
- /* SDHI2 */
- GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0),
- GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3),
-
/* SDENC */
GPIO_FN(SDENC_CPG),
GPIO_FN(SDENC_DV_CLKI),
};
-static struct pinmux_cfg_reg pinmux_config_regs[] = {
+static const struct pinmux_cfg_reg pinmux_config_regs[] = {
PORTCR(0, 0xE6051000), /* PORT0CR */
PORTCR(1, 0xE6051001), /* PORT1CR */
PORTCR(2, 0xE6051002), /* PORT2CR */
@@ -1472,7 +1650,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
{ },
};
-static struct pinmux_data_reg pinmux_data_regs[] = {
+static const struct pinmux_data_reg pinmux_data_regs[] = {
{ PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@@ -1597,56 +1775,59 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
-static struct pinmux_irq pinmux_irqs[] = {
- PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0),
- PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0),
- PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0),
- PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0),
- PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0),
- PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0),
- PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0),
- PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0),
- PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0),
- PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0),
- PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0),
- PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0),
- PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0),
- PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0),
- PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0),
- PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0),
- PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0),
- PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0),
- PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0),
- PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0),
- PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0),
- PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0),
- PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0),
- PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0),
- PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0),
- PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0),
- PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0),
- PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0),
- PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0),
- PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0),
- PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0),
- PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0),
+static const struct pinmux_irq pinmux_irqs[] = {
+ PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
+ PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
+ PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
+ PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
+ PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
+ PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
+ PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
+ PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
+ PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
+ PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
+ PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
+ PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
+ PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
+ PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
+ PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
+ PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
+ PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
+ PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
+ PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
+ PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
+ PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
+ PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
+ PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
+ PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
+ PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
+ PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
+ PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
+ PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
+ PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
+ PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
+ PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
+ PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
};
-struct sh_pfc_soc_info sh7372_pinmux_info = {
+const struct sh_pfc_soc_info sh7372_pinmux_info = {
.name = "sh7372_pfc",
- .reserved_id = PINMUX_RESERVED,
- .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
.input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
.input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
- .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
- .first_gpio = GPIO_PORT0,
- .last_gpio = GPIO_FN_SDENC_DV_CLKI,
+ .pins = pinmux_pins,
+ .nr_pins = ARRAY_SIZE(pinmux_pins),
+ .groups = pinmux_groups,
+ .nr_groups = ARRAY_SIZE(pinmux_groups),
+ .functions = pinmux_functions,
+ .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+ .func_gpios = pinmux_func_gpios,
+ .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
- .gpios = pinmux_gpios,
.cfg_regs = pinmux_config_regs,
.data_regs = pinmux_data_regs,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6f15c03077a0..587f7772abf2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -18,18 +18,18 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
#include <mach/sh73a0.h>
#include <mach/irqs.h>
+#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
- PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
- PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
- PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
- PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
- PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
+ PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
PORT_10(fn, pfx##10, sfx), \
PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
@@ -66,14 +66,6 @@ enum {
PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
PINMUX_INPUT_END,
- PINMUX_INPUT_PULLUP_BEGIN,
- PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
- PINMUX_INPUT_PULLUP_END,
-
- PINMUX_INPUT_PULLDOWN_BEGIN,
- PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
- PINMUX_INPUT_PULLDOWN_END,
-
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
PINMUX_OUTPUT_END,
@@ -468,328 +460,15 @@ enum {
EDBGREQ_PD_MARK,
EDBGREQ_PU_MARK,
- /* Functions with pull-ups */
- KEYIN0_PU_MARK,
- KEYIN1_PU_MARK,
- KEYIN2_PU_MARK,
- KEYIN3_PU_MARK,
- KEYIN4_PU_MARK,
- KEYIN5_PU_MARK,
- KEYIN6_PU_MARK,
- KEYIN7_PU_MARK,
- SDHICD0_PU_MARK,
- SDHID0_0_PU_MARK,
- SDHID0_1_PU_MARK,
- SDHID0_2_PU_MARK,
- SDHID0_3_PU_MARK,
- SDHICMD0_PU_MARK,
- SDHIWP0_PU_MARK,
- SDHID1_0_PU_MARK,
- SDHID1_1_PU_MARK,
- SDHID1_2_PU_MARK,
- SDHID1_3_PU_MARK,
- SDHICMD1_PU_MARK,
- SDHID2_0_PU_MARK,
- SDHID2_1_PU_MARK,
- SDHID2_2_PU_MARK,
- SDHID2_3_PU_MARK,
- SDHICMD2_PU_MARK,
- MMCCMD0_PU_MARK,
- MMCCMD1_PU_MARK,
- MMCD0_0_PU_MARK,
- MMCD0_1_PU_MARK,
- MMCD0_2_PU_MARK,
- MMCD0_3_PU_MARK,
- MMCD0_4_PU_MARK,
- MMCD0_5_PU_MARK,
- MMCD0_6_PU_MARK,
- MMCD0_7_PU_MARK,
- FSIBISLD_PU_MARK,
- FSIACK_PU_MARK,
- FSIAILR_PU_MARK,
- FSIAIBT_PU_MARK,
- FSIAISLD_PU_MARK,
-
PINMUX_MARK_END,
};
-static pinmux_enum_t pinmux_data[] = {
- /* specify valid pin states for each pin in GPIO mode */
+#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
- /* Table 25-1 (I/O and Pull U/D) */
- PORT_DATA_I_PD(0),
- PORT_DATA_I_PU(1),
- PORT_DATA_I_PU(2),
- PORT_DATA_I_PU(3),
- PORT_DATA_I_PU(4),
- PORT_DATA_I_PU(5),
- PORT_DATA_I_PU(6),
- PORT_DATA_I_PU(7),
- PORT_DATA_I_PU(8),
- PORT_DATA_I_PD(9),
- PORT_DATA_I_PD(10),
- PORT_DATA_I_PU_PD(11),
- PORT_DATA_IO_PU_PD(12),
- PORT_DATA_IO_PU_PD(13),
- PORT_DATA_IO_PU_PD(14),
- PORT_DATA_IO_PU_PD(15),
- PORT_DATA_IO_PD(16),
- PORT_DATA_IO_PD(17),
- PORT_DATA_IO_PU(18),
- PORT_DATA_IO_PU(19),
- PORT_DATA_O(20),
- PORT_DATA_O(21),
- PORT_DATA_O(22),
- PORT_DATA_O(23),
- PORT_DATA_O(24),
- PORT_DATA_I_PD(25),
- PORT_DATA_I_PD(26),
- PORT_DATA_IO_PU(27),
- PORT_DATA_IO_PU(28),
- PORT_DATA_IO_PD(29),
- PORT_DATA_IO_PD(30),
- PORT_DATA_IO_PU(31),
- PORT_DATA_IO_PD(32),
- PORT_DATA_I_PU_PD(33),
- PORT_DATA_IO_PD(34),
- PORT_DATA_I_PU_PD(35),
- PORT_DATA_IO_PD(36),
- PORT_DATA_IO(37),
- PORT_DATA_O(38),
- PORT_DATA_I_PU(39),
- PORT_DATA_I_PU_PD(40),
- PORT_DATA_O(41),
- PORT_DATA_IO_PD(42),
- PORT_DATA_IO_PU_PD(43),
- PORT_DATA_IO_PU_PD(44),
- PORT_DATA_IO_PD(45),
- PORT_DATA_IO_PD(46),
- PORT_DATA_IO_PD(47),
- PORT_DATA_I_PD(48),
- PORT_DATA_IO_PU_PD(49),
- PORT_DATA_IO_PD(50),
-
- PORT_DATA_IO_PD(51),
- PORT_DATA_O(52),
- PORT_DATA_IO_PU_PD(53),
- PORT_DATA_IO_PU_PD(54),
- PORT_DATA_IO_PD(55),
- PORT_DATA_I_PU_PD(56),
- PORT_DATA_IO(57),
- PORT_DATA_IO(58),
- PORT_DATA_IO(59),
- PORT_DATA_IO(60),
- PORT_DATA_IO(61),
- PORT_DATA_IO_PD(62),
- PORT_DATA_IO_PD(63),
- PORT_DATA_IO_PU_PD(64),
- PORT_DATA_IO_PD(65),
- PORT_DATA_IO_PU_PD(66),
- PORT_DATA_IO_PU_PD(67),
- PORT_DATA_IO_PU_PD(68),
- PORT_DATA_IO_PU_PD(69),
- PORT_DATA_IO_PU_PD(70),
- PORT_DATA_IO_PU_PD(71),
- PORT_DATA_IO_PU_PD(72),
- PORT_DATA_I_PU_PD(73),
- PORT_DATA_IO_PU(74),
- PORT_DATA_IO_PU(75),
- PORT_DATA_IO_PU(76),
- PORT_DATA_IO_PU(77),
- PORT_DATA_IO_PU(78),
- PORT_DATA_IO_PU(79),
- PORT_DATA_IO_PU(80),
- PORT_DATA_IO_PU(81),
- PORT_DATA_IO_PU(82),
- PORT_DATA_IO_PU(83),
- PORT_DATA_IO_PU(84),
- PORT_DATA_IO_PU(85),
- PORT_DATA_IO_PU(86),
- PORT_DATA_IO_PU(87),
- PORT_DATA_IO_PU(88),
- PORT_DATA_IO_PU(89),
- PORT_DATA_O(90),
- PORT_DATA_IO_PU(91),
- PORT_DATA_O(92),
- PORT_DATA_IO_PU(93),
- PORT_DATA_O(94),
- PORT_DATA_I_PU_PD(95),
- PORT_DATA_IO(96),
- PORT_DATA_IO(97),
- PORT_DATA_IO(98),
- PORT_DATA_I_PU(99),
- PORT_DATA_O(100),
- PORT_DATA_O(101),
- PORT_DATA_I_PU(102),
- PORT_DATA_IO_PD(103),
- PORT_DATA_I_PU_PD(104),
- PORT_DATA_I_PD(105),
- PORT_DATA_I_PD(106),
- PORT_DATA_I_PU_PD(107),
- PORT_DATA_I_PU_PD(108),
- PORT_DATA_IO_PD(109),
- PORT_DATA_IO_PD(110),
- PORT_DATA_IO_PU_PD(111),
- PORT_DATA_IO_PU_PD(112),
- PORT_DATA_IO_PU_PD(113),
- PORT_DATA_IO_PD(114),
- PORT_DATA_IO_PU(115),
- PORT_DATA_IO_PU(116),
- PORT_DATA_IO_PU_PD(117),
- PORT_DATA_IO_PU_PD(118),
- PORT_DATA_IO_PD(128),
-
- PORT_DATA_IO_PD(129),
- PORT_DATA_IO_PU_PD(130),
- PORT_DATA_IO_PD(131),
- PORT_DATA_IO_PD(132),
- PORT_DATA_IO_PD(133),
- PORT_DATA_IO_PU_PD(134),
- PORT_DATA_IO_PU_PD(135),
- PORT_DATA_IO_PU_PD(136),
- PORT_DATA_IO_PU_PD(137),
- PORT_DATA_IO_PD(138),
- PORT_DATA_IO_PD(139),
- PORT_DATA_IO_PD(140),
- PORT_DATA_IO_PD(141),
- PORT_DATA_IO_PD(142),
- PORT_DATA_IO_PD(143),
- PORT_DATA_IO_PU_PD(144),
- PORT_DATA_IO_PD(145),
- PORT_DATA_IO_PU_PD(146),
- PORT_DATA_IO_PU_PD(147),
- PORT_DATA_IO_PU_PD(148),
- PORT_DATA_IO_PU_PD(149),
- PORT_DATA_I_PU_PD(150),
- PORT_DATA_IO_PU_PD(151),
- PORT_DATA_IO_PU_PD(152),
- PORT_DATA_IO_PD(153),
- PORT_DATA_IO_PD(154),
- PORT_DATA_I_PU_PD(155),
- PORT_DATA_IO_PU_PD(156),
- PORT_DATA_I_PD(157),
- PORT_DATA_IO_PD(158),
- PORT_DATA_IO_PU_PD(159),
- PORT_DATA_IO_PU_PD(160),
- PORT_DATA_I_PU_PD(161),
- PORT_DATA_I_PU_PD(162),
- PORT_DATA_IO_PU_PD(163),
- PORT_DATA_I_PU_PD(164),
- PORT_DATA_IO_PD(192),
- PORT_DATA_IO_PU_PD(193),
- PORT_DATA_IO_PD(194),
- PORT_DATA_IO_PU_PD(195),
- PORT_DATA_IO_PD(196),
- PORT_DATA_IO_PD(197),
- PORT_DATA_IO_PD(198),
- PORT_DATA_IO_PD(199),
- PORT_DATA_IO_PU_PD(200),
- PORT_DATA_IO_PU_PD(201),
- PORT_DATA_IO_PU_PD(202),
- PORT_DATA_IO_PU_PD(203),
- PORT_DATA_IO_PU_PD(204),
- PORT_DATA_IO_PU_PD(205),
- PORT_DATA_IO_PU_PD(206),
- PORT_DATA_IO_PD(207),
- PORT_DATA_IO_PD(208),
- PORT_DATA_IO_PD(209),
- PORT_DATA_IO_PD(210),
- PORT_DATA_IO_PD(211),
- PORT_DATA_IO_PD(212),
- PORT_DATA_IO_PD(213),
- PORT_DATA_IO_PU_PD(214),
- PORT_DATA_IO_PU_PD(215),
- PORT_DATA_IO_PD(216),
- PORT_DATA_IO_PD(217),
- PORT_DATA_O(218),
- PORT_DATA_IO_PD(219),
- PORT_DATA_IO_PD(220),
- PORT_DATA_IO_PU_PD(221),
- PORT_DATA_IO_PU_PD(222),
- PORT_DATA_I_PU_PD(223),
- PORT_DATA_I_PU_PD(224),
-
- PORT_DATA_IO_PU_PD(225),
- PORT_DATA_O(226),
- PORT_DATA_IO_PU_PD(227),
- PORT_DATA_I_PU_PD(228),
- PORT_DATA_I_PD(229),
- PORT_DATA_IO(230),
- PORT_DATA_IO_PU_PD(231),
- PORT_DATA_IO_PU_PD(232),
- PORT_DATA_I_PU_PD(233),
- PORT_DATA_IO_PU_PD(234),
- PORT_DATA_IO_PU_PD(235),
- PORT_DATA_IO_PU_PD(236),
- PORT_DATA_IO_PD(237),
- PORT_DATA_IO_PU_PD(238),
- PORT_DATA_IO_PU_PD(239),
- PORT_DATA_IO_PU_PD(240),
- PORT_DATA_O(241),
- PORT_DATA_I_PD(242),
- PORT_DATA_IO_PU_PD(243),
- PORT_DATA_IO_PU_PD(244),
- PORT_DATA_IO_PU_PD(245),
- PORT_DATA_IO_PU_PD(246),
- PORT_DATA_IO_PU_PD(247),
- PORT_DATA_IO_PU_PD(248),
- PORT_DATA_IO_PU_PD(249),
- PORT_DATA_IO_PU_PD(250),
- PORT_DATA_IO_PU_PD(251),
- PORT_DATA_IO_PU_PD(252),
- PORT_DATA_IO_PU_PD(253),
- PORT_DATA_IO_PU_PD(254),
- PORT_DATA_IO_PU_PD(255),
- PORT_DATA_IO_PU_PD(256),
- PORT_DATA_IO_PU_PD(257),
- PORT_DATA_IO_PU_PD(258),
- PORT_DATA_IO_PU_PD(259),
- PORT_DATA_IO_PU_PD(260),
- PORT_DATA_IO_PU_PD(261),
- PORT_DATA_IO_PU_PD(262),
- PORT_DATA_IO_PU_PD(263),
- PORT_DATA_IO_PU_PD(264),
- PORT_DATA_IO_PU_PD(265),
- PORT_DATA_IO_PU_PD(266),
- PORT_DATA_IO_PU_PD(267),
- PORT_DATA_IO_PU_PD(268),
- PORT_DATA_IO_PU_PD(269),
- PORT_DATA_IO_PU_PD(270),
- PORT_DATA_IO_PU_PD(271),
- PORT_DATA_IO_PU_PD(272),
- PORT_DATA_IO_PU_PD(273),
- PORT_DATA_IO_PU_PD(274),
- PORT_DATA_IO_PU_PD(275),
- PORT_DATA_IO_PU_PD(276),
- PORT_DATA_IO_PU_PD(277),
- PORT_DATA_IO_PU_PD(278),
- PORT_DATA_IO_PU_PD(279),
- PORT_DATA_IO_PU_PD(280),
- PORT_DATA_O(281),
- PORT_DATA_O(282),
- PORT_DATA_I_PU(288),
- PORT_DATA_IO_PU_PD(289),
- PORT_DATA_IO_PU_PD(290),
- PORT_DATA_IO_PU_PD(291),
- PORT_DATA_IO_PU_PD(292),
- PORT_DATA_IO_PU_PD(293),
- PORT_DATA_IO_PU_PD(294),
- PORT_DATA_IO_PU_PD(295),
- PORT_DATA_IO_PU_PD(296),
- PORT_DATA_IO_PU_PD(297),
- PORT_DATA_IO_PU_PD(298),
-
- PORT_DATA_IO_PU_PD(299),
- PORT_DATA_IO_PU_PD(300),
- PORT_DATA_IO_PU_PD(301),
- PORT_DATA_IO_PU_PD(302),
- PORT_DATA_IO_PU_PD(303),
- PORT_DATA_IO_PU_PD(304),
- PORT_DATA_IO_PU_PD(305),
- PORT_DATA_O(306),
- PORT_DATA_O(307),
- PORT_DATA_I_PU(308),
- PORT_DATA_O(309),
+static const pinmux_enum_t pinmux_data[] = {
+ /* specify valid pin states for each pin in GPIO mode */
+ PINMUX_DATA_GP_ALL(),
/* Table 25-1 (Function 0-7) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@@ -1358,28 +1037,19 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
- MSEL4CR_MSEL15_0),
- PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
- PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
- PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
- PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
- MSEL4CR_MSEL15_0), \
+ PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
- PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
- MSEL4CR_MSEL15_0),
+ PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1485,69 +1155,1791 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
+};
+
+#define SH73A0_PIN(pin, cfgs) \
+ { \
+ .name = __stringify(PORT##pin), \
+ .enum_id = PORT##pin##_DATA, \
+ .configs = cfgs, \
+ }
+
+#define __I (SH_PFC_PIN_CFG_INPUT)
+#define __O (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
+#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
+#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
+#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
+#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
+#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
+#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
+#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
+
+static struct sh_pfc_pin pinmux_pins[] = {
+ /* Table 25-1 (I/O and Pull U/D) */
+ SH73A0_PIN_I_PD(0),
+ SH73A0_PIN_I_PU(1),
+ SH73A0_PIN_I_PU(2),
+ SH73A0_PIN_I_PU(3),
+ SH73A0_PIN_I_PU(4),
+ SH73A0_PIN_I_PU(5),
+ SH73A0_PIN_I_PU(6),
+ SH73A0_PIN_I_PU(7),
+ SH73A0_PIN_I_PU(8),
+ SH73A0_PIN_I_PD(9),
+ SH73A0_PIN_I_PD(10),
+ SH73A0_PIN_I_PU_PD(11),
+ SH73A0_PIN_IO_PU_PD(12),
+ SH73A0_PIN_IO_PU_PD(13),
+ SH73A0_PIN_IO_PU_PD(14),
+ SH73A0_PIN_IO_PU_PD(15),
+ SH73A0_PIN_IO_PD(16),
+ SH73A0_PIN_IO_PD(17),
+ SH73A0_PIN_IO_PU(18),
+ SH73A0_PIN_IO_PU(19),
+ SH73A0_PIN_O(20),
+ SH73A0_PIN_O(21),
+ SH73A0_PIN_O(22),
+ SH73A0_PIN_O(23),
+ SH73A0_PIN_O(24),
+ SH73A0_PIN_I_PD(25),
+ SH73A0_PIN_I_PD(26),
+ SH73A0_PIN_IO_PU(27),
+ SH73A0_PIN_IO_PU(28),
+ SH73A0_PIN_IO_PD(29),
+ SH73A0_PIN_IO_PD(30),
+ SH73A0_PIN_IO_PU(31),
+ SH73A0_PIN_IO_PD(32),
+ SH73A0_PIN_I_PU_PD(33),
+ SH73A0_PIN_IO_PD(34),
+ SH73A0_PIN_I_PU_PD(35),
+ SH73A0_PIN_IO_PD(36),
+ SH73A0_PIN_IO(37),
+ SH73A0_PIN_O(38),
+ SH73A0_PIN_I_PU(39),
+ SH73A0_PIN_I_PU_PD(40),
+ SH73A0_PIN_O(41),
+ SH73A0_PIN_IO_PD(42),
+ SH73A0_PIN_IO_PU_PD(43),
+ SH73A0_PIN_IO_PU_PD(44),
+ SH73A0_PIN_IO_PD(45),
+ SH73A0_PIN_IO_PD(46),
+ SH73A0_PIN_IO_PD(47),
+ SH73A0_PIN_I_PD(48),
+ SH73A0_PIN_IO_PU_PD(49),
+ SH73A0_PIN_IO_PD(50),
+ SH73A0_PIN_IO_PD(51),
+ SH73A0_PIN_O(52),
+ SH73A0_PIN_IO_PU_PD(53),
+ SH73A0_PIN_IO_PU_PD(54),
+ SH73A0_PIN_IO_PD(55),
+ SH73A0_PIN_I_PU_PD(56),
+ SH73A0_PIN_IO(57),
+ SH73A0_PIN_IO(58),
+ SH73A0_PIN_IO(59),
+ SH73A0_PIN_IO(60),
+ SH73A0_PIN_IO(61),
+ SH73A0_PIN_IO_PD(62),
+ SH73A0_PIN_IO_PD(63),
+ SH73A0_PIN_IO_PU_PD(64),
+ SH73A0_PIN_IO_PD(65),
+ SH73A0_PIN_IO_PU_PD(66),
+ SH73A0_PIN_IO_PU_PD(67),
+ SH73A0_PIN_IO_PU_PD(68),
+ SH73A0_PIN_IO_PU_PD(69),
+ SH73A0_PIN_IO_PU_PD(70),
+ SH73A0_PIN_IO_PU_PD(71),
+ SH73A0_PIN_IO_PU_PD(72),
+ SH73A0_PIN_I_PU_PD(73),
+ SH73A0_PIN_IO_PU(74),
+ SH73A0_PIN_IO_PU(75),
+ SH73A0_PIN_IO_PU(76),
+ SH73A0_PIN_IO_PU(77),
+ SH73A0_PIN_IO_PU(78),
+ SH73A0_PIN_IO_PU(79),
+ SH73A0_PIN_IO_PU(80),
+ SH73A0_PIN_IO_PU(81),
+ SH73A0_PIN_IO_PU(82),
+ SH73A0_PIN_IO_PU(83),
+ SH73A0_PIN_IO_PU(84),
+ SH73A0_PIN_IO_PU(85),
+ SH73A0_PIN_IO_PU(86),
+ SH73A0_PIN_IO_PU(87),
+ SH73A0_PIN_IO_PU(88),
+ SH73A0_PIN_IO_PU(89),
+ SH73A0_PIN_O(90),
+ SH73A0_PIN_IO_PU(91),
+ SH73A0_PIN_O(92),
+ SH73A0_PIN_IO_PU(93),
+ SH73A0_PIN_O(94),
+ SH73A0_PIN_I_PU_PD(95),
+ SH73A0_PIN_IO(96),
+ SH73A0_PIN_IO(97),
+ SH73A0_PIN_IO(98),
+ SH73A0_PIN_I_PU(99),
+ SH73A0_PIN_O(100),
+ SH73A0_PIN_O(101),
+ SH73A0_PIN_I_PU(102),
+ SH73A0_PIN_IO_PD(103),
+ SH73A0_PIN_I_PU_PD(104),
+ SH73A0_PIN_I_PD(105),
+ SH73A0_PIN_I_PD(106),
+ SH73A0_PIN_I_PU_PD(107),
+ SH73A0_PIN_I_PU_PD(108),
+ SH73A0_PIN_IO_PD(109),
+ SH73A0_PIN_IO_PD(110),
+ SH73A0_PIN_IO_PU_PD(111),
+ SH73A0_PIN_IO_PU_PD(112),
+ SH73A0_PIN_IO_PU_PD(113),
+ SH73A0_PIN_IO_PD(114),
+ SH73A0_PIN_IO_PU(115),
+ SH73A0_PIN_IO_PU(116),
+ SH73A0_PIN_IO_PU_PD(117),
+ SH73A0_PIN_IO_PU_PD(118),
+ SH73A0_PIN_IO_PD(128),
+ SH73A0_PIN_IO_PD(129),
+ SH73A0_PIN_IO_PU_PD(130),
+ SH73A0_PIN_IO_PD(131),
+ SH73A0_PIN_IO_PD(132),
+ SH73A0_PIN_IO_PD(133),
+ SH73A0_PIN_IO_PU_PD(134),
+ SH73A0_PIN_IO_PU_PD(135),
+ SH73A0_PIN_IO_PU_PD(136),
+ SH73A0_PIN_IO_PU_PD(137),
+ SH73A0_PIN_IO_PD(138),
+ SH73A0_PIN_IO_PD(139),
+ SH73A0_PIN_IO_PD(140),
+ SH73A0_PIN_IO_PD(141),
+ SH73A0_PIN_IO_PD(142),
+ SH73A0_PIN_IO_PD(143),
+ SH73A0_PIN_IO_PU_PD(144),
+ SH73A0_PIN_IO_PD(145),
+ SH73A0_PIN_IO_PU_PD(146),
+ SH73A0_PIN_IO_PU_PD(147),
+ SH73A0_PIN_IO_PU_PD(148),
+ SH73A0_PIN_IO_PU_PD(149),
+ SH73A0_PIN_I_PU_PD(150),
+ SH73A0_PIN_IO_PU_PD(151),
+ SH73A0_PIN_IO_PU_PD(152),
+ SH73A0_PIN_IO_PD(153),
+ SH73A0_PIN_IO_PD(154),
+ SH73A0_PIN_I_PU_PD(155),
+ SH73A0_PIN_IO_PU_PD(156),
+ SH73A0_PIN_I_PD(157),
+ SH73A0_PIN_IO_PD(158),
+ SH73A0_PIN_IO_PU_PD(159),
+ SH73A0_PIN_IO_PU_PD(160),
+ SH73A0_PIN_I_PU_PD(161),
+ SH73A0_PIN_I_PU_PD(162),
+ SH73A0_PIN_IO_PU_PD(163),
+ SH73A0_PIN_I_PU_PD(164),
+ SH73A0_PIN_IO_PD(192),
+ SH73A0_PIN_IO_PU_PD(193),
+ SH73A0_PIN_IO_PD(194),
+ SH73A0_PIN_IO_PU_PD(195),
+ SH73A0_PIN_IO_PD(196),
+ SH73A0_PIN_IO_PD(197),
+ SH73A0_PIN_IO_PD(198),
+ SH73A0_PIN_IO_PD(199),
+ SH73A0_PIN_IO_PU_PD(200),
+ SH73A0_PIN_IO_PU_PD(201),
+ SH73A0_PIN_IO_PU_PD(202),
+ SH73A0_PIN_IO_PU_PD(203),
+ SH73A0_PIN_IO_PU_PD(204),
+ SH73A0_PIN_IO_PU_PD(205),
+ SH73A0_PIN_IO_PU_PD(206),
+ SH73A0_PIN_IO_PD(207),
+ SH73A0_PIN_IO_PD(208),
+ SH73A0_PIN_IO_PD(209),
+ SH73A0_PIN_IO_PD(210),
+ SH73A0_PIN_IO_PD(211),
+ SH73A0_PIN_IO_PD(212),
+ SH73A0_PIN_IO_PD(213),
+ SH73A0_PIN_IO_PU_PD(214),
+ SH73A0_PIN_IO_PU_PD(215),
+ SH73A0_PIN_IO_PD(216),
+ SH73A0_PIN_IO_PD(217),
+ SH73A0_PIN_O(218),
+ SH73A0_PIN_IO_PD(219),
+ SH73A0_PIN_IO_PD(220),
+ SH73A0_PIN_IO_PU_PD(221),
+ SH73A0_PIN_IO_PU_PD(222),
+ SH73A0_PIN_I_PU_PD(223),
+ SH73A0_PIN_I_PU_PD(224),
+ SH73A0_PIN_IO_PU_PD(225),
+ SH73A0_PIN_O(226),
+ SH73A0_PIN_IO_PU_PD(227),
+ SH73A0_PIN_I_PU_PD(228),
+ SH73A0_PIN_I_PD(229),
+ SH73A0_PIN_IO(230),
+ SH73A0_PIN_IO_PU_PD(231),
+ SH73A0_PIN_IO_PU_PD(232),
+ SH73A0_PIN_I_PU_PD(233),
+ SH73A0_PIN_IO_PU_PD(234),
+ SH73A0_PIN_IO_PU_PD(235),
+ SH73A0_PIN_IO_PU_PD(236),
+ SH73A0_PIN_IO_PD(237),
+ SH73A0_PIN_IO_PU_PD(238),
+ SH73A0_PIN_IO_PU_PD(239),
+ SH73A0_PIN_IO_PU_PD(240),
+ SH73A0_PIN_O(241),
+ SH73A0_PIN_I_PD(242),
+ SH73A0_PIN_IO_PU_PD(243),
+ SH73A0_PIN_IO_PU_PD(244),
+ SH73A0_PIN_IO_PU_PD(245),
+ SH73A0_PIN_IO_PU_PD(246),
+ SH73A0_PIN_IO_PU_PD(247),
+ SH73A0_PIN_IO_PU_PD(248),
+ SH73A0_PIN_IO_PU_PD(249),
+ SH73A0_PIN_IO_PU_PD(250),
+ SH73A0_PIN_IO_PU_PD(251),
+ SH73A0_PIN_IO_PU_PD(252),
+ SH73A0_PIN_IO_PU_PD(253),
+ SH73A0_PIN_IO_PU_PD(254),
+ SH73A0_PIN_IO_PU_PD(255),
+ SH73A0_PIN_IO_PU_PD(256),
+ SH73A0_PIN_IO_PU_PD(257),
+ SH73A0_PIN_IO_PU_PD(258),
+ SH73A0_PIN_IO_PU_PD(259),
+ SH73A0_PIN_IO_PU_PD(260),
+ SH73A0_PIN_IO_PU_PD(261),
+ SH73A0_PIN_IO_PU_PD(262),
+ SH73A0_PIN_IO_PU_PD(263),
+ SH73A0_PIN_IO_PU_PD(264),
+ SH73A0_PIN_IO_PU_PD(265),
+ SH73A0_PIN_IO_PU_PD(266),
+ SH73A0_PIN_IO_PU_PD(267),
+ SH73A0_PIN_IO_PU_PD(268),
+ SH73A0_PIN_IO_PU_PD(269),
+ SH73A0_PIN_IO_PU_PD(270),
+ SH73A0_PIN_IO_PU_PD(271),
+ SH73A0_PIN_IO_PU_PD(272),
+ SH73A0_PIN_IO_PU_PD(273),
+ SH73A0_PIN_IO_PU_PD(274),
+ SH73A0_PIN_IO_PU_PD(275),
+ SH73A0_PIN_IO_PU_PD(276),
+ SH73A0_PIN_IO_PU_PD(277),
+ SH73A0_PIN_IO_PU_PD(278),
+ SH73A0_PIN_IO_PU_PD(279),
+ SH73A0_PIN_IO_PU_PD(280),
+ SH73A0_PIN_O(281),
+ SH73A0_PIN_O(282),
+ SH73A0_PIN_I_PU(288),
+ SH73A0_PIN_IO_PU_PD(289),
+ SH73A0_PIN_IO_PU_PD(290),
+ SH73A0_PIN_IO_PU_PD(291),
+ SH73A0_PIN_IO_PU_PD(292),
+ SH73A0_PIN_IO_PU_PD(293),
+ SH73A0_PIN_IO_PU_PD(294),
+ SH73A0_PIN_IO_PU_PD(295),
+ SH73A0_PIN_IO_PU_PD(296),
+ SH73A0_PIN_IO_PU_PD(297),
+ SH73A0_PIN_IO_PU_PD(298),
+ SH73A0_PIN_IO_PU_PD(299),
+ SH73A0_PIN_IO_PU_PD(300),
+ SH73A0_PIN_IO_PU_PD(301),
+ SH73A0_PIN_IO_PU_PD(302),
+ SH73A0_PIN_IO_PU_PD(303),
+ SH73A0_PIN_IO_PU_PD(304),
+ SH73A0_PIN_IO_PU_PD(305),
+ SH73A0_PIN_O(306),
+ SH73A0_PIN_O(307),
+ SH73A0_PIN_I_PU(308),
+ SH73A0_PIN_O(309),
+};
+
+static const struct pinmux_range pinmux_ranges[] = {
+ {.begin = 0, .end = 118,},
+ {.begin = 128, .end = 164,},
+ {.begin = 192, .end = 282,},
+ {.begin = 288, .end = 309,},
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data_0_7_pins[] = {
+ /* D[0:7] */
+ 74, 75, 76, 77, 78, 79, 80, 81,
+};
+static const unsigned int bsc_data_0_7_mux[] = {
+ D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+ D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data_8_15_pins[] = {
+ /* D[8:15] */
+ 82, 83, 84, 85, 86, 87, 88, 89,
+};
+static const unsigned int bsc_data_8_15_mux[] = {
+ D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+ D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+ /* CS */
+ 90,
+};
+static const unsigned int bsc_cs4_mux[] = {
+ CS4__MARK,
+};
+static const unsigned int bsc_cs5_a_pins[] = {
+ /* CS */
+ 91,
+};
+static const unsigned int bsc_cs5_a_mux[] = {
+ CS5A__MARK,
+};
+static const unsigned int bsc_cs5_b_pins[] = {
+ /* CS */
+ 92,
+};
+static const unsigned int bsc_cs5_b_mux[] = {
+ CS5B__MARK,
+};
+static const unsigned int bsc_cs6_a_pins[] = {
+ /* CS */
+ 94,
+};
+static const unsigned int bsc_cs6_a_mux[] = {
+ CS6A__MARK,
+};
+static const unsigned int bsc_cs6_b_pins[] = {
+ /* CS */
+ 93,
+};
+static const unsigned int bsc_cs6_b_mux[] = {
+ CS6B__MARK,
+};
+static const unsigned int bsc_rd_pins[] = {
+ /* RD */
+ 96,
+};
+static const unsigned int bsc_rd_mux[] = {
+ RD__FSC_MARK,
+};
+static const unsigned int bsc_rdwr_0_pins[] = {
+ /* RDWR */
+ 91,
+};
+static const unsigned int bsc_rdwr_0_mux[] = {
+ PORT91_RDWR_MARK,
+};
+static const unsigned int bsc_rdwr_1_pins[] = {
+ /* RDWR */
+ 97,
+};
+static const unsigned int bsc_rdwr_1_mux[] = {
+ RDWR_FWE_MARK,
+};
+static const unsigned int bsc_rdwr_2_pins[] = {
+ /* RDWR */
+ 149,
+};
+static const unsigned int bsc_rdwr_2_mux[] = {
+ PORT149_RDWR_MARK,
+};
+static const unsigned int bsc_we0_pins[] = {
+ /* WE0 */
+ 97,
+};
+static const unsigned int bsc_we0_mux[] = {
+ WE0__FWE_MARK,
+};
+static const unsigned int bsc_we1_pins[] = {
+ /* WE1 */
+ 98,
+};
+static const unsigned int bsc_we1_mux[] = {
+ WE1__MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+ /* CK */
+ 49,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+ FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+ /* OMC */
+ 49,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+ FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 50, 51,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+ FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 50, 51,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+ FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+ /* ISLD */
+ 55,
+};
+static const unsigned int fsia_data_in_mux[] = {
+ FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+ /* OSLD */
+ 52,
+};
+static const unsigned int fsia_data_out_mux[] = {
+ FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsia_spdif_mux[] = {
+ FSIASPDIF_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+ /* CK */
+ 54,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+ FSIBCK_MARK,
+};
+static const unsigned int fsib_mclk_out_pins[] = {
+ /* OMC */
+ 54,
+};
+static const unsigned int fsib_mclk_out_mux[] = {
+ FSIBOMC_MARK,
+};
+static const unsigned int fsib_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 37, 36,
+};
+static const unsigned int fsib_sclk_in_mux[] = {
+ FSIBILR_MARK, FSIBIBT_MARK,
+};
+static const unsigned int fsib_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 37, 36,
+};
+static const unsigned int fsib_sclk_out_mux[] = {
+ FSIBOLR_MARK, FSIBOBT_MARK,
+};
+static const unsigned int fsib_data_in_pins[] = {
+ /* ISLD */
+ 39,
+};
+static const unsigned int fsib_data_in_mux[] = {
+ FSIBISLD_MARK,
+};
+static const unsigned int fsib_data_out_pins[] = {
+ /* OSLD */
+ 38,
+};
+static const unsigned int fsib_data_out_mux[] = {
+ FSIBOSLD_MARK,
+};
+static const unsigned int fsib_spdif_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsib_spdif_mux[] = {
+ FSIBSPDIF_MARK,
+};
+/* - FSIC ------------------------------------------------------------------- */
+static const unsigned int fsic_mclk_in_pins[] = {
+ /* CK */
+ 54,
+};
+static const unsigned int fsic_mclk_in_mux[] = {
+ FSICCK_MARK,
+};
+static const unsigned int fsic_mclk_out_pins[] = {
+ /* OMC */
+ 54,
+};
+static const unsigned int fsic_mclk_out_mux[] = {
+ FSICOMC_MARK,
+};
+static const unsigned int fsic_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 46, 45,
+};
+static const unsigned int fsic_sclk_in_mux[] = {
+ FSICILR_MARK, FSICIBT_MARK,
+};
+static const unsigned int fsic_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 46, 45,
+};
+static const unsigned int fsic_sclk_out_mux[] = {
+ FSICOLR_MARK, FSICOBT_MARK,
+};
+static const unsigned int fsic_data_in_pins[] = {
+ /* ISLD */
+ 48,
+};
+static const unsigned int fsic_data_in_mux[] = {
+ FSICISLD_MARK,
+};
+static const unsigned int fsic_data_out_pins[] = {
+ /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
+ 47, 44, 42, 16,
+};
+static const unsigned int fsic_data_out_mux[] = {
+ FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
+};
+static const unsigned int fsic_spdif_0_pins[] = {
+ /* SPDIF */
+ 53,
+};
+static const unsigned int fsic_spdif_0_mux[] = {
+ PORT53_FSICSPDIF_MARK,
+};
+static const unsigned int fsic_spdif_1_pins[] = {
+ /* SPDIF */
+ 47,
+};
+static const unsigned int fsic_spdif_1_mux[] = {
+ PORT47_FSICSPDIF_MARK,
+};
+/* - FSID ------------------------------------------------------------------- */
+static const unsigned int fsid_sclk_in_pins[] = {
+ /* ILR, IBT */
+ 46, 45,
+};
+static const unsigned int fsid_sclk_in_mux[] = {
+ FSIDILR_MARK, FSIDIBT_MARK,
+};
+static const unsigned int fsid_sclk_out_pins[] = {
+ /* OLR, OBT */
+ 46, 45,
+};
+static const unsigned int fsid_sclk_out_mux[] = {
+ FSIDOLR_MARK, FSIDOBT_MARK,
+};
+static const unsigned int fsid_data_in_pins[] = {
+ /* ISLD */
+ 48,
+};
+static const unsigned int fsid_data_in_mux[] = {
+ FSIDISLD_MARK,
+};
+/* - I2C2 ------------------------------------------------------------------- */
+static const unsigned int i2c2_0_pins[] = {
+ /* SCL, SDA */
+ 237, 236,
+};
+static const unsigned int i2c2_0_mux[] = {
+ PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_1_pins[] = {
+ /* SCL, SDA */
+ 27, 28,
+};
+static const unsigned int i2c2_1_mux[] = {
+ PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
+};
+static const unsigned int i2c2_2_pins[] = {
+ /* SCL, SDA */
+ 115, 116,
+};
+static const unsigned int i2c2_2_mux[] = {
+ PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
+};
+/* - I2C3 ------------------------------------------------------------------- */
+static const unsigned int i2c3_0_pins[] = {
+ /* SCL, SDA */
+ 248, 249,
+};
+static const unsigned int i2c3_0_mux[] = {
+ PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_1_pins[] = {
+ /* SCL, SDA */
+ 27, 28,
+};
+static const unsigned int i2c3_1_mux[] = {
+ PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
+};
+static const unsigned int i2c3_2_pins[] = {
+ /* SCL, SDA */
+ 115, 116,
+};
+static const unsigned int i2c3_2_mux[] = {
+ PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
+};
+/* - IrDA ------------------------------------------------------------------- */
+static const unsigned int irda_0_pins[] = {
+ /* OUT, IN, FIRSEL */
+ 241, 242, 243,
+};
+static const unsigned int irda_0_mux[] = {
+ PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
+};
+static const unsigned int irda_1_pins[] = {
+ /* OUT, IN, FIRSEL */
+ 49, 53, 54,
+};
+static const unsigned int irda_1_mux[] = {
+ PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
+};
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in5_pins[] = {
+ /* KEYIN[0:4] */
+ 66, 67, 68, 69, 70,
+};
+static const unsigned int keysc_in5_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+ /* KEYIN[0:5] */
+ 66, 67, 68, 69, 70, 71,
+};
+static const unsigned int keysc_in6_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+ /* KEYIN[0:6] */
+ 66, 67, 68, 69, 70, 71, 72,
+};
+static const unsigned int keysc_in7_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
+};
+static const unsigned int keysc_in8_pins[] = {
+ /* KEYIN[0:7] */
+ 66, 67, 68, 69, 70, 71, 72, 73,
+};
+static const unsigned int keysc_in8_mux[] = {
+ KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
+ KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
+};
+static const unsigned int keysc_out04_pins[] = {
+ /* KEYOUT[0:4] */
+ 65, 64, 63, 62, 61,
+};
+static const unsigned int keysc_out04_mux[] = {
+ KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+ /* KEYOUT5 */
+ 60,
+};
+static const unsigned int keysc_out5_mux[] = {
+ KEYOUT5_MARK,
+};
+static const unsigned int keysc_out6_0_pins[] = {
+ /* KEYOUT6 */
+ 59,
+};
+static const unsigned int keysc_out6_0_mux[] = {
+ PORT59_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_1_pins[] = {
+ /* KEYOUT6 */
+ 131,
+};
+static const unsigned int keysc_out6_1_mux[] = {
+ PORT131_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out6_2_pins[] = {
+ /* KEYOUT6 */
+ 143,
+};
+static const unsigned int keysc_out6_2_mux[] = {
+ PORT143_KEYOUT6_MARK,
+};
+static const unsigned int keysc_out7_0_pins[] = {
+ /* KEYOUT7 */
+ 58,
+};
+static const unsigned int keysc_out7_0_mux[] = {
+ PORT58_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_1_pins[] = {
+ /* KEYOUT7 */
+ 132,
+};
+static const unsigned int keysc_out7_1_mux[] = {
+ PORT132_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out7_2_pins[] = {
+ /* KEYOUT7 */
+ 144,
+};
+static const unsigned int keysc_out7_2_mux[] = {
+ PORT144_KEYOUT7_MARK,
+};
+static const unsigned int keysc_out8_0_pins[] = {
+ /* KEYOUT8 */
+ PIN_NUMBER(6, 26),
+};
+static const unsigned int keysc_out8_0_mux[] = {
+ KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_1_pins[] = {
+ /* KEYOUT8 */
+ 136,
+};
+static const unsigned int keysc_out8_1_mux[] = {
+ PORT136_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out8_2_pins[] = {
+ /* KEYOUT8 */
+ 138,
+};
+static const unsigned int keysc_out8_2_mux[] = {
+ PORT138_KEYOUT8_MARK,
+};
+static const unsigned int keysc_out9_0_pins[] = {
+ /* KEYOUT9 */
+ 137,
+};
+static const unsigned int keysc_out9_0_mux[] = {
+ PORT137_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_1_pins[] = {
+ /* KEYOUT9 */
+ 139,
+};
+static const unsigned int keysc_out9_1_mux[] = {
+ PORT139_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out9_2_pins[] = {
+ /* KEYOUT9 */
+ 149,
+};
+static const unsigned int keysc_out9_2_mux[] = {
+ PORT149_KEYOUT9_MARK,
+};
+static const unsigned int keysc_out10_0_pins[] = {
+ /* KEYOUT10 */
+ 132,
+};
+static const unsigned int keysc_out10_0_mux[] = {
+ PORT132_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out10_1_pins[] = {
+ /* KEYOUT10 */
+ 142,
+};
+static const unsigned int keysc_out10_1_mux[] = {
+ PORT142_KEYOUT10_MARK,
+};
+static const unsigned int keysc_out11_0_pins[] = {
+ /* KEYOUT11 */
+ 131,
+};
+static const unsigned int keysc_out11_0_mux[] = {
+ PORT131_KEYOUT11_MARK,
+};
+static const unsigned int keysc_out11_1_pins[] = {
+ /* KEYOUT11 */
+ 143,
+};
+static const unsigned int keysc_out11_1_mux[] = {
+ PORT143_KEYOUT11_MARK,