diff options
| author | Heiko Stuebner <heiko.stuebner@vrull.eu> | 2022-12-23 23:13:30 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-12-29 06:59:50 -0800 |
| commit | 088ec01fce4eaba17ada8b1831be0c172c941657 (patch) | |
| tree | 556f4367f8cc604827972c50b1d921cd12becfc1 | |
| parent | 8963d6224009d7ac0523a05ceb9ea5d04ad5d12d (diff) | |
RISC-V: add rd reg parsing to insn.h header
Add a macro to allow parsing of the rd register from an instruction.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20221223221332.4127602-11-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/include/asm/insn.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 21ec817abec1..2a23890b4577 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -60,6 +60,7 @@ #define RVG_RS1_OPOFF 15 #define RVG_RS2_OPOFF 20 #define RVG_RD_OPOFF 7 +#define RVG_RD_MASK GENMASK(4, 0) /* The bit field of immediate value in RVC J instruction */ #define RVC_J_IMM_SIGN_OPOFF 12 @@ -244,6 +245,10 @@ static __always_inline bool riscv_insn_is_branch(u32 code) #define RV_X(X, s, mask) (((X) >> (s)) & (mask)) #define RVC_X(X, s, mask) RV_X(X, s, mask) +#define RV_EXTRACT_RD_REG(x) \ + ({typeof(x) x_ = (x); \ + (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); }) + #define RV_EXTRACT_UTYPE_IMM(x) \ ({typeof(x) x_ = (x); \ (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); }) |