diff options
| author | Jocelyn Falempe <jfalempe@redhat.com> | 2025-06-24 11:01:19 +0200 |
|---|---|---|
| committer | Maarten Lankhorst <dev@lankhorst.se> | 2025-06-27 11:48:23 +0200 |
| commit | 0cc88243aa240e5807515d09b47336370df34de8 (patch) | |
| tree | d782568f81e4fac5d6e5f37df22488d870c97864 | |
| parent | 116d86dd69af8a596e5a894393927627ab709636 (diff) | |
drm/i915/display: Add drm_panic support for 4-tiling with DPT
On Alder Lake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements 4-Tiling support, to still be able to draw
the panic screen.
Signed-off-by: Jocelyn Falempe <jfalempe@redhat.com>
Link: https://lore.kernel.org/r/20250624091501.257661-11-jfalempe@redhat.com
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_plane.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c index 62eeb9a145ff..de6d10d8f1fa 100644 --- a/drivers/gpu/drm/i915/display/intel_plane.c +++ b/drivers/gpu/drm/i915/display/intel_plane.c @@ -1298,6 +1298,25 @@ static unsigned int intel_ytile_get_offset(unsigned int width, unsigned int x, u return offset; } +static unsigned int intel_4tile_get_offset(unsigned int width, unsigned int x, unsigned int y) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks = DIV_ROUND_UP(width, 32); + + /* Block offset */ + offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE; + + x = x % YTILE_WIDTH; + y = y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle = (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | + ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset += swizzle * 4; + return offset; +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state = to_intel_plane_state(plane->state); @@ -1341,6 +1360,7 @@ static unsigned int (*intel_get_tiling_func(u64 fb_modifier))(unsigned int width case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_get_offset; case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: |