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authorMiquel Raynal <miquel.raynal@bootlin.com>2025-04-03 11:19:29 +0200
committerMiquel Raynal <miquel.raynal@bootlin.com>2025-04-29 11:05:34 +0200
commit25e08bf666607f572d5b9b87b0728d126b9bdef9 (patch)
treebc00331c2dc7742aadf5b24d35f8120e708f7c55
parent1ac5ff2f2ad671612f9a96ffda948632ed48502f (diff)
mtd: spinand: winbond: Add support for W35N02JW and W35N04JW chips
These chips support single SPI, octal SPI and octal DDR SPI. For now, only the SDR protocols are supported. Tested with the W35N02JW variant, but the 04 one just has twice more dies and is described in the same datasheet, so we can reasonably expect that it will behave identically. Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
-rw-r--r--drivers/mtd/nand/spi/winbond.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index c263c9b5affe..19f8dd4a6370 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -287,6 +287,24 @@ static const struct spinand_info winbond_spinand_table[] = {
&update_cache_octal_variants),
0,
SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)),
+ SPINAND_INFO("W35N02JW", /* 1.8V */
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22),
+ NAND_MEMORG(1, 4096, 128, 64, 512, 10, 2, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants),
+ 0,
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)),
+ SPINAND_INFO("W35N04JW", /* 1.8V */
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23),
+ NAND_MEMORG(1, 4096, 128, 64, 512, 10, 4, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants),
+ 0,
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL)),
/* 2G-bit densities */
SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),