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authorMario Limonciello <mario.limonciello@amd.com>2024-12-09 12:52:40 -0600
committerMario Limonciello <mario.limonciello@amd.com>2024-12-11 10:44:53 -0600
commit474e7218e81e7932ed18f91969b72169005ff038 (patch)
tree8eaebd1b8667b5621afa8045d62d5860a8a6f7c5
parent88a95ba066a962d4d39c6a36b18bf665f51d3767 (diff)
cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on success
If writing the MSR MSR_AMD_CPPC_REQ fails then the cached value in the amd_cpudata structure should not be updated. Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Link: https://lore.kernel.org/r/20241209185248.16301-8-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
-rw-r--r--drivers/cpufreq/amd-pstate.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
index fbd1b36846c5..ebfc9e20b6cb 100644
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -278,11 +278,15 @@ static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp)
value &= ~AMD_CPPC_EPP_PERF_MASK;
value |= FIELD_PREP(AMD_CPPC_EPP_PERF_MASK, epp);
- WRITE_ONCE(cpudata->cppc_req_cached, value);
ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
- if (!ret)
- cpudata->epp_cached = epp;
+ if (ret) {
+ pr_err("failed to set energy perf value (%d)\n", ret);
+ return ret;
+ }
+
+ cpudata->epp_cached = epp;
+ WRITE_ONCE(cpudata->cppc_req_cached, value);
return ret;
}