diff options
| author | Svyatoslav Ryhel <clamor95@gmail.com> | 2025-02-26 12:56:12 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2025-03-06 18:45:45 +0100 |
| commit | 645b331b308d229ef6f6d61f0bf943946f91e7ae (patch) | |
| tree | ea7eea718dda8c04cbbfceadf508be9a566005ff | |
| parent | 2b3db788f2f614b875b257cdb079adadedc060f3 (diff) | |
ARM: tegra: Add ARM PMU node on Tegra114
Add ARM PMU node for Tegra114 like it is done for Tegra30 and Tegra124.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Link: https://lore.kernel.org/r/20250226105615.61087-4-clamor95@gmail.com
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/nvidia/tegra114.dtsi | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvidia/tegra114.dtsi index 6c057b506951..ace862f6feb8 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -805,31 +805,40 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <3>; }; }; + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = |