diff options
| author | Kishore Kadiyala <kishore.kadiyala@ti.com> | 2010-01-07 22:10:02 +0530 |
|---|---|---|
| committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2010-01-11 04:33:52 +0530 |
| commit | 7f7a691a0b53e24a2c578eef790638cdf965b55b (patch) | |
| tree | 15dd77ccc8c6716504f501f3610119ecd7b39d27 | |
| parent | 598c968d156a19c82536f4fb9e1b19b0b28e9c69 (diff) | |
Fixing clock divider issue for MMC on OMAP4
This fixes the clock frequency selected for CLK pin on MMC/SD card
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
| -rw-r--r-- | drivers/mmc/host/omap_hsmmc.c | 16 |
1 files changed, 5 insertions, 11 deletions
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c index 3b15e26b98e0..f5079bc7a345 100644 --- a/drivers/mmc/host/omap_hsmmc.c +++ b/drivers/mmc/host/omap_hsmmc.c @@ -877,21 +877,15 @@ static void set_data_timeout(struct mmc_omap_host *host, unsigned int timeout, cycle_ns; uint32_t reg, clkd, dto = 0; - /* TO FIX : Calculations needs to be done below - * as it is running into divide by zero. - * Hard coding SYSCTL register - */ - if (cpu_is_omap44xx()) { - reg = 0xe00c7; - OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); - return; - } reg = OMAP_HSMMC_READ(host->base, SYSCTL); clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; if (clkd == 0) clkd = 1; - - cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); + /* TO FIX : Remove hardcoding 96Mhz and use clk_get_rate */ + if (cpu_is_omap44xx()) + cycle_ns = 1000000000 / (96000000 / clkd); + else + cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); timeout = req->data->timeout_ns / cycle_ns; timeout += req->data->timeout_clks; if (timeout) { |