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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2025-03-24 22:51:23 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2025-03-24 22:51:23 -0700 |
| commit | 8ac6067bd808ceb147d562e624d0348796e4e355 (patch) | |
| tree | b51749cf34e707c9d54360af6b84fe55e3460e82 | |
| parent | a49a879f0ac19ed0a562e220019741857b261551 (diff) | |
| parent | f0373cc0907ca7918266a507d6b3b5d75ee839ba (diff) | |
Merge tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 SEV updates from Ingo Molnar:
- Improve sme_enable() PIC build robustness (Kevin Loughlin)
- Simplify vc_handle_msr() a bit (Peng Hao)
[ Just reminding myself and everybody else about the endless stream of
x86 TLAs: "SEV" is AMD's Secure Encrypted Virtualization - Linus ]
* tag 'x86-sev-2025-03-22' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/sev: Simplify the code by removing unnecessary 'else' statement
x86/sev: Add missing RIP_REL_REF() invocations during sme_enable()
| -rw-r--r-- | arch/x86/coco/sev/core.c | 3 | ||||
| -rw-r--r-- | arch/x86/mm/mem_encrypt_identity.c | 4 |
2 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c index d14bce0f82cc..b0c1a7a57497 100644 --- a/arch/x86/coco/sev/core.c +++ b/arch/x86/coco/sev/core.c @@ -1480,8 +1480,7 @@ static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) case MSR_AMD64_GUEST_TSC_FREQ: if (sev_status & MSR_AMD64_SNP_SECURE_TSC) return __vc_handle_secure_tsc_msrs(regs, write); - else - break; + break; default: break; } diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c index 4e991dedc1db..5eecdd92da10 100644 --- a/arch/x86/mm/mem_encrypt_identity.c +++ b/arch/x86/mm/mem_encrypt_identity.c @@ -563,7 +563,7 @@ void __head sme_enable(struct boot_params *bp) } RIP_REL_REF(sme_me_mask) = me_mask; - physical_mask &= ~me_mask; - cc_vendor = CC_VENDOR_AMD; + RIP_REL_REF(physical_mask) &= ~me_mask; + RIP_REL_REF(cc_vendor) = CC_VENDOR_AMD; cc_set_mask(me_mask); } |