diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2021-05-14 16:22:44 -0700 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2021-06-07 10:59:45 -0700 |
| commit | 9b2e49a14838584b659548565b799e0523659295 (patch) | |
| tree | 659cd69b5c6b161a4c9d680e61d49a4927b47033 | |
| parent | abb9fe438b827d8d7b844958f1acd261c5ad2b46 (diff) | |
drm/i915/display: Fix fastsets involving PSR
Commit 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware
configuration read out") is not allowing fastsets to happen when PSR
states changes but PSR is a feature that can be enabled and disabled
during fastsets.
So here moving the PSR pipe conf checks to a block that is only
executed when checking if HW state matches with requested state, not
during the phase where it checks if fastset is possible or not.
There still a state mismatch not allowing fastsets between states
turning off or on PSR because of crtc_state->infoframes.enable
BIT(DP_SDP_VSC) but at least for now it will allow a fastset between
PSR1 <-> PSR2, that is a case heavilly used by CI due to pipe CRC not
work with PSR2, but the remaning issue will be fixed in a future patch.
Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 78b772e1a01f ("drm/i915/display: Fill PSR state during hardware configuration read out")
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210514232247.144542-1-jose.souza@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a363664b233e..09d83d6dc0e9 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8603,6 +8603,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, bp_gamma = intel_color_get_gamma_bit_precision(pipe_config); if (bp_gamma) PIPE_CONF_CHECK_COLOR_LUT(gamma_mode, hw.gamma_lut, bp_gamma); + + PIPE_CONF_CHECK_BOOL(has_psr); + PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); + PIPE_CONF_CHECK_I(dc3co_exitline); } PIPE_CONF_CHECK_BOOL(double_wide); @@ -8687,11 +8692,6 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.pipeline_full); PIPE_CONF_CHECK_I(vrr.guardband); - PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); - PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); - PIPE_CONF_CHECK_I(dc3co_exitline); - #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I #undef PIPE_CONF_CHECK_BOOL |