diff options
| author | Sebastien Jan <s-jan@ti.com> | 2012-08-20 17:11:41 +0200 |
|---|---|---|
| committer | Xavier Boudet <x-boudet@ti.com> | 2012-08-21 09:39:48 +0200 |
| commit | c31b7f88cccbd563403cf7ae3132b40c972fe338 (patch) | |
| tree | c24f3abc3ee1fba1eddf0378ce1e749a881d595a | |
| parent | bdb72ae0b215b422b32c0fe5b38e69ae09bdf9de (diff) | |
omap4460: fix smp_twd clock definition
Add a 4460 dedicated smp_twd entry using the virtual mpu dpll.
Using the bad clock data for smp_twd on 4460 has the effect of providing
a bad mpu clock value, resulting in a bad (too short) programming of
the twd (local timer). Hence any timer interrupt fires too early.
Kernel (hrtimer_interrupt) notices that the next timer event is not there
yet and reprograms the timer interrupt for the same (not elapsed) event,
which is again programmed too early for the same reason, ...
The effect is multiple additional (and unused / useless) timer interrupts
for each real timer event (including scheduler tick). (I observed 5
additional interrupts for the schedulter tick with MPU @ 1.2GHz. Note that
lower MPU freqs led to less interrupts).
This patch fixes this 'fancy' effect, with effectively observed reduced
twd triggering rate, verified on each MPU OPP.
Signed-off-by: Sebastien Jan <s-jan@ti.com>
| -rw-r--r-- | arch/arm/mach-omap2/clock44xx_data.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 06604393032a..ec286803edd2 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -3156,6 +3156,14 @@ static struct clk auxclkreq5_ck = { .recalc = &omap2_clksel_recalc, }; +static struct clk smp_twd_446x = { + .name = "smp_twd", + .parent = &virt_dpll_mpu_ck, + .ops = &clkops_null, + .fixed_div = 2, + .recalc = &omap_fixed_divisor_recalc, +}; + /* * clkdev */ @@ -3246,7 +3254,8 @@ static struct omap_clk omap44xx_clks[] = { CLK(NULL, "l4_div_ck", &l4_div_ck, CK_44XX), CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_44XX), CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_44XX), - CLK("smp_twd", NULL, &mpu_periphclk, CK_44XX), + CLK("smp_twd", NULL, &mpu_periphclk, CK_443X), + CLK("smp_twd", NULL, &smp_twd_446x, CK_446X), CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_44XX), CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_44XX), CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_44XX), |