diff options
| author | Ignacio Encinas <ignacio@iencinas.com> | 2025-03-11 18:20:22 +0100 |
|---|---|---|
| committer | Yury Norov <yury.norov@gmail.com> | 2025-03-12 19:27:15 -0400 |
| commit | e3f42c436d7e0cb432935fe3ae275dd8d9b60f71 (patch) | |
| tree | 08c4b9178b68a417bfe447979b4649a5e5e30a17 | |
| parent | 0312e94abe484b9ee58c32d2f8ba177e04955b35 (diff) | |
riscv: fix test_and_{set,clear}_bit ordering documentation
test_and_{set,clear}_bit are fully ordered as specified in
Documentation/atomic_bitops.txt. Fix incorrect comment stating otherwise.
Note that the implementation is correct since commit
9347ce54cd69 ("RISC-V: __test_and_op_bit_ord should be strongly ordered")
was introduced.
Signed-off-by: Ignacio Encinas <ignacio@iencinas.com>
Signed-off-by: Yury Norov <yury.norov@gmail.com>
| -rw-r--r-- | arch/riscv/include/asm/bitops.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index c6bd3d8354a9..49a0f48d93df 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -226,7 +226,7 @@ legacy: * @nr: Bit to set * @addr: Address to count from * - * This operation may be reordered on other architectures than x86. + * This is an atomic fully-ordered operation (implied full memory barrier). */ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long *addr) { @@ -238,7 +238,7 @@ static __always_inline int arch_test_and_set_bit(int nr, volatile unsigned long * @nr: Bit to clear * @addr: Address to count from * - * This operation can be reordered on other architectures other than x86. + * This is an atomic fully-ordered operation (implied full memory barrier). */ static __always_inline int arch_test_and_clear_bit(int nr, volatile unsigned long *addr) { |