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author | Dan Williams <dan.j.williams@intel.com> | 2017-05-04 23:38:43 -0700 |
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committer | Dan Williams <dan.j.williams@intel.com> | 2017-05-04 23:38:43 -0700 |
commit | 736163671bcb163fc82600b46c83dfa89d532d95 (patch) | |
tree | 0639dc9d9fa180450b4e8fbda706eaae5f1876da /Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt | |
parent | d5483feda85a8f39ee2e940e279547c686aac30c (diff) | |
parent | 1ef97fe4f8abd3317d5c3c860f990e02c2633959 (diff) |
Merge branch 'for-4.12/dax' into libnvdimm-for-nextlibnvdimm-for-4.12
Diffstat (limited to 'Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt')
-rw-r--r-- | Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt new file mode 100644 index 000000000000..4dc412437b08 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt @@ -0,0 +1,21 @@ +Lattice iCE40 FPGA Manager + +Required properties: +- compatible: Should contain "lattice,ice40-fpga-mgr" +- reg: SPI chip select +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000) +- cdone-gpios: GPIO input connected to CDONE pin +- reset-gpios: Active-low GPIO output connected to CRESET_B pin. Note + that unless the GPIO is held low during startup, the + FPGA will enter Master SPI mode and drive SCK with a + clock signal potentially jamming other devices on the + bus until the firmware is loaded. + +Example: + fpga: fpga@0 { + compatible = "lattice,ice40-fpga-mgr"; + reg = <0>; + spi-max-frequency = <1000000>; + cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>; + }; |