diff options
| author | Stafford Horne <shorne@gmail.com> | 2023-04-14 08:25:58 +0100 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2023-04-26 15:08:06 +0100 |
| commit | 63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf (patch) | |
| tree | b547d7264d6e02178c8e755168edb0d17702f760 /arch/openrisc/kernel/traps.c | |
| parent | 812489ac4dd91144a74ce65ecf232252a2e406fb (diff) | |
openrisc: Support storing and restoring fpu state
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions. We need to save
only the floating point status and control register, FPCSR.
Add support to maintain the FPCSR unconditionally upon exceptions and
switches. On machines that do not support FPU this will always just
store 0x0 and restore is a no-op. On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/kernel/traps.c')
| -rw-r--r-- | arch/openrisc/kernel/traps.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/openrisc/kernel/traps.c b/arch/openrisc/kernel/traps.c index fd9a0f2b66c4..f5bbe6b55849 100644 --- a/arch/openrisc/kernel/traps.c +++ b/arch/openrisc/kernel/traps.c @@ -75,8 +75,9 @@ void show_registers(struct pt_regs *regs) in_kernel = 0; printk("CPU #: %d\n" - " PC: %08lx SR: %08lx SP: %08lx\n", - smp_processor_id(), regs->pc, regs->sr, regs->sp); + " PC: %08lx SR: %08lx SP: %08lx FPCSR: %08lx\n", + smp_processor_id(), regs->pc, regs->sr, regs->sp, + regs->fpcsr); printk("GPR00: %08lx GPR01: %08lx GPR02: %08lx GPR03: %08lx\n", 0L, regs->gpr[1], regs->gpr[2], regs->gpr[3]); printk("GPR04: %08lx GPR05: %08lx GPR06: %08lx GPR07: %08lx\n", |