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| author | Olof Johansson <olof@lixom.net> | 2018-09-25 11:30:47 -0700 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2018-09-25 11:30:47 -0700 |
| commit | cdddeefc39cc26b2d429f8f7ea3c35bf8cb8c6a1 (patch) | |
| tree | 2628d4922d0675df5659439f22f5ebda9c4b302a /arch/x86/include/asm/pgtable-3level.h | |
| parent | bf1da406909b13903873d1f91346f99303fd8cb3 (diff) | |
| parent | 11da3a7f84f19c26da6f86af878298694ede0804 (diff) | |
Merge tag 'v4.19-rc3' into next/drivers
Linux 4.19-rc3
Diffstat (limited to 'arch/x86/include/asm/pgtable-3level.h')
| -rw-r--r-- | arch/x86/include/asm/pgtable-3level.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/x86/include/asm/pgtable-3level.h b/arch/x86/include/asm/pgtable-3level.h index a564084c6141..f8b1ad2c3828 100644 --- a/arch/x86/include/asm/pgtable-3level.h +++ b/arch/x86/include/asm/pgtable-3level.h @@ -2,6 +2,8 @@ #ifndef _ASM_X86_PGTABLE_3LEVEL_H #define _ASM_X86_PGTABLE_3LEVEL_H +#include <asm/atomic64_32.h> + /* * Intel Physical Address Extension (PAE) Mode - three-level page * tables on PPro+ CPUs. @@ -150,10 +152,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *ptep) { pte_t res; - /* xchg acts as a barrier before the setting of the high bits */ - res.pte_low = xchg(&ptep->pte_low, 0); - res.pte_high = ptep->pte_high; - ptep->pte_high = 0; + res.pte = (pteval_t)arch_atomic64_xchg((atomic64_t *)ptep, 0); return res; } |