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| author | Ross Zwisler <ross.zwisler@linux.intel.com> | 2018-02-03 00:26:10 -0700 |
|---|---|---|
| committer | Ross Zwisler <ross.zwisler@linux.intel.com> | 2018-02-03 00:26:10 -0700 |
| commit | d121f07691415df824e6b60520f782f6d13b3c81 (patch) | |
| tree | 422ad3cc6fd631604fef4e469e49bacba8202e52 /arch/x86/kernel/cpu/microcode/intel.c | |
| parent | 59858d3d54cfad1f8db67c2c07e4dd33bb6ed955 (diff) | |
| parent | 569d0365f571fa6421a5c80bc30d1b2cdab857fe (diff) | |
Merge branch 'for-4.16/dax' into libnvdimm-for-next
Diffstat (limited to 'arch/x86/kernel/cpu/microcode/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/microcode/intel.c | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 7dbcb7adf797..8ccdca6d3f9e 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -565,15 +565,6 @@ static void print_ucode(struct ucode_cpu_info *uci) } #else -/* - * Flush global tlb. We only do this in x86_64 where paging has been enabled - * already and PGE should be enabled as well. - */ -static inline void flush_tlb_early(void) -{ - __native_flush_tlb_global_irq_disabled(); -} - static inline void print_ucode(struct ucode_cpu_info *uci) { struct microcode_intel *mc; @@ -602,10 +593,6 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) if (rev != mc->hdr.rev) return -1; -#ifdef CONFIG_X86_64 - /* Flush global tlb. This is precaution. */ - flush_tlb_early(); -#endif uci->cpu_sig.rev = rev; if (early) |