diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2014-08-05 12:31:35 +1000 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2014-08-05 13:07:33 +1000 |
| commit | 5f4121b6f09ddc9ce2ed2f19f934482d2d3a8079 (patch) | |
| tree | 848dd39931517bd690c029f420b2c48abba957ff /arch | |
| parent | 704cfc0249d190cef5df8a12dd1f148f78451537 (diff) | |
| parent | 8bb652eb38e50ce4e8709fbfd9e73f9d11ac3ff6 (diff) | |
Merge remote-tracking branch 'drm/drm-next'
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/exynos4.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5.dtsi | 1 | ||||
| -rw-r--r-- | arch/arm/boot/dts/exynos5420.dtsi | 19 |
3 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 08ea6dc9a92f..fc9f588f76f5 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -638,6 +638,7 @@ clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>; clock-names = "sclk_fimd", "fimd"; samsung,power-domain = <&pd_lcd0>; + samsung,sysreg = <&sys_reg>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index 79d0608d6dcc..fdead12952a1 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -87,6 +87,7 @@ reg = <0x14400000 0x40000>; interrupt-names = "fifo", "vsync", "lcd_sys"; interrupts = <18 4>, <18 5>, <18 6>; + samsung,sysreg = <&sysreg_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index cb2b70e7ca0a..bfe056d9148c 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -515,6 +515,25 @@ phy-names = "dp"; }; + mipi_phy: video-phy@10040714 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10040714 12>; + #phy-cells = <1>; + }; + + dsi@14500000 { + compatible = "samsung,exynos5410-mipi-dsi"; + reg = <0x14500000 0x10000>; + interrupts = <0 82 0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + fimd: fimd@14400000 { clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; |