diff options
| author | Peter De Schrijver <pdeschrijver@nvidia.com> | 2017-07-25 13:34:06 +0300 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2017-08-23 15:59:15 -0700 |
| commit | bc7b34a2fb78661b2980d949aad8edc39c253e3a (patch) | |
| tree | a518f04fca7e3146d3ba85d0f49550cb737155b1 /drivers/clk/mediatek | |
| parent | e34e69cc866a26ec42be789a49ea6174ddc801ca (diff) | |
clk: tegra: Init cfg structure in _get_pll_mnp
Not all fields are read from the hw depending on the PLL type. Make sure
the other fields are 0 by clearing the structure beforehand to prevent
users such as the rate re-calculation code from using bogus values.
Based on work by Alex Frid <afrid@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/mediatek')
0 files changed, 0 insertions, 0 deletions