diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:15:54 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 11:32:39 +0100 |
| commit | bb6d3fa98a418b071c5f735e75558604f5f4af66 (patch) | |
| tree | 24b49efbe47f240e566c1c27240ab9ce0847ddd1 /drivers/clk/renesas/rcar-gen3-cpg.c | |
| parent | 627151b4966fe68029cd14aa5fd81f5f0c67fa26 (diff) | |
clk: renesas: rcar-gen3: Switch to new SD clock handling
The old SD handling code was huge and could not handle all the details
which showed up on R-Car Gen3 SoCs meanwhile. It is time to switch to
another design. Have SDnH a separate clock, use the existing divider
clocks and move the errata handling from the clock driver to the SDHI
driver where it belongs.
This patch removes the old SD handling code and switch to the new one.
This updates the SDHI driver at the same time. Because the SDHI driver
can only communicate with the clock driver via clk_set_rate(), I don't
see an alternative to this flag-day-approach, so we cross subsystems
here.
The patch sadly looks messy for the CPG lib, but it is basically a huge
chunk of code removed and smaller chunks added. It looks much better
when you just view the resulting source file.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC
Link: https://lore.kernel.org/r/20211110191610.5664-6-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/rcar-gen3-cpg.c')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index 0c815684dd47..941dadf07230 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -406,9 +406,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, __clk_get_name(parent), notifiers); case CLK_TYPE_GEN3_SD: - return cpg_sd_clk_register(core->name, base, core->offset, - __clk_get_name(parent), notifiers, - cpg_quirks & SD_SKIP_FIRST); + return cpg_sd_clk_register(core->name, base + core->offset, + __clk_get_name(parent)); case CLK_TYPE_GEN3_R: if (cpg_quirks & RCKCR_CKSEL) { |