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authorChen-Yu Tsai <wens@csie.org>2017-07-24 21:58:57 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2017-08-30 14:01:47 +0200
commitdc8797e39fca777217fd4cfc9c74a5337a3daa76 (patch)
tree327f605a7a0187e67b30e8b59d123efafc278742 /drivers/clk/sunxi-ng/ccu-sun8i-a83t.c
parentf6f64ed868d32a121f1535da9f42791c91562e4a (diff)
clk: sunxi-ng: Add MP_MMC clocks that support MMC timing modes switching
All of our MMC clocks are of the MP clock type. A few MMC clocks on some SoCs, such as MMC2 on the A83T, support new/old timing mode switching. >From a clock rate point of view, when the new timing mode is active. the output clock rate is halved. This patch adds a special wrapper class of clocks, MP_MMC, around the generic MP type clocks. The rate related callbacks in ccu_mp_mmc_ops for this class look at the timing mode bit and apply the /2 post-divider when needed, before passing it through to the generic class ops, ccu_mp_ops. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu-sun8i-a83t.c')
0 files changed, 0 insertions, 0 deletions