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| author | James Morris <james.l.morris@oracle.com> | 2017-09-24 22:41:55 -0700 |
|---|---|---|
| committer | James Morris <james.l.morris@oracle.com> | 2017-09-24 22:41:55 -0700 |
| commit | 25eabb13c7d67ae32298015c5e28d00f604f412c (patch) | |
| tree | 5bd75c2c1e385c79425bb099f0d19db7fb9c391f /drivers/clk/sunxi-ng/ccu_mp.h | |
| parent | ab5348c9c23cd253f5902980d2d8fe067dc24c82 (diff) | |
| parent | e19b205be43d11bff638cad4487008c48d21c103 (diff) | |
Merge tag 'v4.14-rc2' into next-general
Linux 4.14-rc2
Sync to v4.14-rc2 for security subsystem developers to track.
Diffstat (limited to 'drivers/clk/sunxi-ng/ccu_mp.h')
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu_mp.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/clk/sunxi-ng/ccu_mp.h b/drivers/clk/sunxi-ng/ccu_mp.h index 915625e97d98..aaef11d747ea 100644 --- a/drivers/clk/sunxi-ng/ccu_mp.h +++ b/drivers/clk/sunxi-ng/ccu_mp.h @@ -14,6 +14,7 @@ #ifndef _CCU_MP_H_ #define _CCU_MP_H_ +#include <linux/bitops.h> #include <linux/clk-provider.h> #include "ccu_common.h" @@ -74,4 +75,33 @@ static inline struct ccu_mp *hw_to_ccu_mp(struct clk_hw *hw) extern const struct clk_ops ccu_mp_ops; +/* + * Special class of M-P clock that supports MMC timing modes + * + * Since the MMC clock registers all follow the same layout, we can + * simplify the macro for this particular case. In addition, as + * switching modes also affects the output clock rate, we need to + * have CLK_GET_RATE_NOCACHE for all these types of clocks. + */ + +#define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ + _flags) \ + struct ccu_mp _struct = { \ + .enable = BIT(31), \ + .m = _SUNXI_CCU_DIV(0, 4), \ + .p = _SUNXI_CCU_DIV(16, 2), \ + .mux = _SUNXI_CCU_MUX(24, 2), \ + .common = { \ + .reg = _reg, \ + .features = CCU_FEATURE_MMC_TIMING_SWITCH, \ + .hw.init = CLK_HW_INIT_PARENTS(_name, \ + _parents, \ + &ccu_mp_mmc_ops, \ + CLK_GET_RATE_NOCACHE | \ + _flags), \ + } \ + } + +extern const struct clk_ops ccu_mp_mmc_ops; + #endif /* _CCU_MP_H_ */ |