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| author | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 17:23:50 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-06-25 17:23:50 -0700 |
| commit | e2c18eb50c7bb191d1ebfed973c2ec3e0066ad37 (patch) | |
| tree | 4168ed5db574298a40196a453106e00f6e1d6414 /drivers/cxl/core/port.c | |
| parent | aeaefabc59ec3c7edd6d0ca7add7aff2ff6f59d0 (diff) | |
| parent | adfe19738b71a893da62cb2e30bd6bdb4299ea67 (diff) | |
Merge branch 'for-6.5/cxl-region-fixes' into for-6.5/cxl
Pick up the recent fixes to how CPU caches are managed relative to
region setup / teardown, and make sure that all decoders transition
successfully before updating the region state from COMMIT => ACTIVE.
Diffstat (limited to 'drivers/cxl/core/port.c')
0 files changed, 0 insertions, 0 deletions