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authorBorislav Petkov <borislav.petkov@amd.com>2010-03-08 18:29:35 +0100
committerGreg Kroah-Hartman <gregkh@suse.de>2010-08-10 10:20:38 -0700
commit568590d41c7a89fa30874cffcd0ba658ed6e01bc (patch)
treeb9cbb8f47bbbc2e98f44b062359a48a2991f7603 /drivers/edac
parentfcd6ae1e01e0740ad84bc9440edd217ef6c791aa (diff)
amd64_edac: Fix DCT base address selector
commit 9975a5f22a4fcc8d08035c65439900a983f891ad upstream. The correct check is to verify whether in high range we're below 4GB and not to extract the DctSelBaseAddr again. See "2.8.5 Routing DRAM Requests" in the F10h BKDG. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com> Acked-by: Doug Thompson <dougthompson@xmission.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/edac')
-rw-r--r--drivers/edac/amd64_edac.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 01bc8e232456..1c220dc62d89 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1491,7 +1491,7 @@ static inline u64 f10_get_base_addr_offset(u64 sys_addr, int hi_range_sel,
u64 chan_off;
if (hi_range_sel) {
- if (!(dct_sel_base_addr & 0xFFFFF800) &&
+ if (!(dct_sel_base_addr & 0xFFFF0000) &&
hole_valid && (sys_addr >= 0x100000000ULL))
chan_off = hole_off << 16;
else